cgx_fw_if.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Marvell OcteonTx2 CGX driver
  3 *
  4 * Copyright (C) 2018 Marvell.
  5 *
  6 */
  7
  8#ifndef __CGX_FW_INTF_H__
  9#define __CGX_FW_INTF_H__
 10
 11#include <linux/bitops.h>
 12#include <linux/bitfield.h>
 13
 14#define CGX_FIRMWARE_MAJOR_VER		1
 15#define CGX_FIRMWARE_MINOR_VER		0
 16
 17#define CGX_EVENT_ACK                   1UL
 18
 19/* CGX error types. set for cmd response status as CGX_STAT_FAIL */
 20enum cgx_error_type {
 21	CGX_ERR_NONE,
 22	CGX_ERR_LMAC_NOT_ENABLED,
 23	CGX_ERR_LMAC_MODE_INVALID,
 24	CGX_ERR_REQUEST_ID_INVALID,
 25	CGX_ERR_PREV_ACK_NOT_CLEAR,
 26	CGX_ERR_PHY_LINK_DOWN,
 27	CGX_ERR_PCS_RESET_FAIL,
 28	CGX_ERR_AN_CPT_FAIL,
 29	CGX_ERR_TX_NOT_IDLE,
 30	CGX_ERR_RX_NOT_IDLE,
 31	CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
 32	CGX_ERR_SPUX_RX_ALIGN_FAIL,
 33	CGX_ERR_SPUX_TX_FAULT,
 34	CGX_ERR_SPUX_RX_FAULT,
 35	CGX_ERR_SPUX_RESET_FAIL,
 36	CGX_ERR_SPUX_AN_RESET_FAIL,
 37	CGX_ERR_SPUX_USX_AN_RESET_FAIL,
 38	CGX_ERR_SMUX_RX_LINK_NOT_OK,
 39	CGX_ERR_PCS_RECV_LINK_FAIL,
 40	CGX_ERR_TRAINING_FAIL,
 41	CGX_ERR_RX_EQU_FAIL,
 42	CGX_ERR_SPUX_BER_FAIL,
 43	CGX_ERR_SPUX_RSFEC_ALGN_FAIL,
 44	CGX_ERR_SPUX_MARKER_LOCK_FAIL,
 45	CGX_ERR_SET_FEC_INVALID,
 46	CGX_ERR_SET_FEC_FAIL,
 47	CGX_ERR_MODULE_INVALID,
 48	CGX_ERR_MODULE_NOT_PRESENT,
 49	CGX_ERR_SPEED_CHANGE_INVALID,
 50};
 51
 52/* LINK speed types */
 53enum cgx_link_speed {
 54	CGX_LINK_NONE,
 55	CGX_LINK_10M,
 56	CGX_LINK_100M,
 57	CGX_LINK_1G,
 58	CGX_LINK_2HG,
 59	CGX_LINK_5G,
 60	CGX_LINK_10G,
 61	CGX_LINK_20G,
 62	CGX_LINK_25G,
 63	CGX_LINK_40G,
 64	CGX_LINK_50G,
 65	CGX_LINK_80G,
 66	CGX_LINK_100G,
 67	CGX_LINK_SPEED_MAX,
 68};
 69
 70enum CGX_MODE_ {
 71	CGX_MODE_SGMII,
 72	CGX_MODE_1000_BASEX,
 73	CGX_MODE_QSGMII,
 74	CGX_MODE_10G_C2C,
 75	CGX_MODE_10G_C2M,
 76	CGX_MODE_10G_KR,
 77	CGX_MODE_20G_C2C,
 78	CGX_MODE_25G_C2C,
 79	CGX_MODE_25G_C2M,
 80	CGX_MODE_25G_2_C2C,
 81	CGX_MODE_25G_CR,
 82	CGX_MODE_25G_KR,
 83	CGX_MODE_40G_C2C,
 84	CGX_MODE_40G_C2M,
 85	CGX_MODE_40G_CR4,
 86	CGX_MODE_40G_KR4,
 87	CGX_MODE_40GAUI_C2C,
 88	CGX_MODE_50G_C2C,
 89	CGX_MODE_50G_C2M,
 90	CGX_MODE_50G_4_C2C,
 91	CGX_MODE_50G_CR,
 92	CGX_MODE_50G_KR,
 93	CGX_MODE_80GAUI_C2C,
 94	CGX_MODE_100G_C2C,
 95	CGX_MODE_100G_C2M,
 96	CGX_MODE_100G_CR4,
 97	CGX_MODE_100G_KR4,
 98	CGX_MODE_LAUI_2_C2C_BIT,
 99	CGX_MODE_LAUI_2_C2M_BIT,
100	CGX_MODE_50GBASE_CR2_C_BIT,
101	CGX_MODE_50GBASE_KR2_C_BIT,     /* = 30 */
102	CGX_MODE_100GAUI_2_C2C_BIT,
103	CGX_MODE_100GAUI_2_C2M_BIT,
104	CGX_MODE_100GBASE_CR2_BIT,
105	CGX_MODE_100GBASE_KR2_BIT,
106	CGX_MODE_SFI_1G_BIT,
107	CGX_MODE_25GBASE_CR_C_BIT,
108	CGX_MODE_25GBASE_KR_C_BIT,
109	CGX_MODE_SGMII_10M_BIT,
110	CGX_MODE_SGMII_100M_BIT,        /* = 39 */
111	CGX_MODE_2500_BASEX_BIT = 42, /* Mode group 1 */
112	CGX_MODE_5000_BASEX_BIT,
113	CGX_MODE_O_USGMII_BIT,
114	CGX_MODE_Q_USGMII_BIT,
115	CGX_MODE_2_5G_USXGMII_BIT,
116	CGX_MODE_5G_USXGMII_BIT,
117	CGX_MODE_10G_SXGMII_BIT,
118	CGX_MODE_10G_DXGMII_BIT,
119	CGX_MODE_10G_QXGMII_BIT,
120	CGX_MODE_TP_BIT,
121	CGX_MODE_FIBER_BIT,
122	CGX_MODE_MAX /* = 53 */
123};
124/* REQUEST ID types. Input to firmware */
125enum cgx_cmd_id {
126	CGX_CMD_NONE,
127	CGX_CMD_GET_FW_VER,
128	CGX_CMD_GET_MAC_ADDR,
129	CGX_CMD_SET_MTU,
130	CGX_CMD_GET_LINK_STS,		/* optional to user */
131	CGX_CMD_LINK_BRING_UP,
132	CGX_CMD_LINK_BRING_DOWN,
133	CGX_CMD_INTERNAL_LBK,
134	CGX_CMD_EXTERNAL_LBK,
135	CGX_CMD_HIGIG,
136	CGX_CMD_LINK_STAT_CHANGE,
137	CGX_CMD_MODE_CHANGE,		/* hot plug support */
138	CGX_CMD_INTF_SHUTDOWN,
139	CGX_CMD_GET_MKEX_PRFL_SIZE,
140	CGX_CMD_GET_MKEX_PRFL_ADDR,
141	CGX_CMD_GET_FWD_BASE,		/* get base address of shared FW data */
142	CGX_CMD_GET_LINK_MODES,		/* Supported Link Modes */
143	CGX_CMD_SET_LINK_MODE,
144	CGX_CMD_GET_SUPPORTED_FEC,
145	CGX_CMD_SET_FEC,
146	CGX_CMD_GET_AN,
147	CGX_CMD_SET_AN,
148	CGX_CMD_GET_ADV_LINK_MODES,
149	CGX_CMD_GET_ADV_FEC,
150	CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */
151	CGX_CMD_SET_PHY_MOD_TYPE,
152	CGX_CMD_PRBS,
153	CGX_CMD_DISPLAY_EYE,
154	CGX_CMD_GET_PHY_FEC_STATS,
155};
156
157/* async event ids */
158enum cgx_evt_id {
159	CGX_EVT_NONE,
160	CGX_EVT_LINK_CHANGE,
161};
162
163/* event types - cause of interrupt */
164enum cgx_evt_type {
165	CGX_EVT_ASYNC,
166	CGX_EVT_CMD_RESP
167};
168
169enum cgx_stat {
170	CGX_STAT_SUCCESS,
171	CGX_STAT_FAIL
172};
173
174enum cgx_cmd_own {
175	CGX_CMD_OWN_NS,
176	CGX_CMD_OWN_FIRMWARE,
177};
178
179/* m - bit mask
180 * y - value to be written in the bitrange
181 * x - input value whose bitrange to be modified
182 */
183#define FIELD_SET(m, y, x)		\
184	(((x) & ~(m)) |			\
185	FIELD_PREP((m), (y)))
186
187/* scratchx(0) CSR used for ATF->non-secure SW communication.
188 * This acts as the status register
189 * Provides details on command ack/status, command response, error details
190 */
191#define EVTREG_ACK		BIT_ULL(0)
192#define EVTREG_EVT_TYPE		BIT_ULL(1)
193#define EVTREG_STAT		BIT_ULL(2)
194#define EVTREG_ID		GENMASK_ULL(8, 3)
195
196/* Response to command IDs with command status as CGX_STAT_FAIL
197 *
198 * Not applicable for commands :
199 * CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
200 */
201#define EVTREG_ERRTYPE		GENMASK_ULL(18, 9)
202
203/* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as
204 * CGX_STAT_SUCCESS
205 */
206#define RESP_MAJOR_VER		GENMASK_ULL(12, 9)
207#define RESP_MINOR_VER		GENMASK_ULL(16, 13)
208
209/* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as
210 * CGX_STAT_SUCCESS
211 */
212#define RESP_MAC_ADDR		GENMASK_ULL(56, 9)
213
214/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_SIZE with cmd status as
215 * CGX_STAT_SUCCESS
216 */
217#define RESP_MKEX_PRFL_SIZE		GENMASK_ULL(63, 9)
218
219/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_ADDR with cmd status as
220 * CGX_STAT_SUCCESS
221 */
222#define RESP_MKEX_PRFL_ADDR		GENMASK_ULL(63, 9)
223
224/* Response to cmd ID as CGX_CMD_GET_FWD_BASE with cmd status as
225 * CGX_STAT_SUCCESS
226 */
227#define RESP_FWD_BASE		GENMASK_ULL(56, 9)
228#define RESP_LINKSTAT_LMAC_TYPE                GENMASK_ULL(35, 28)
229
230/* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
231 * status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
232 *
233 * In case of CGX_STAT_FAIL, it indicates CGX configuration failed
234 * when processing link up/down/change command.
235 * Both err_type and current link status will be updated
236 *
237 * In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
238 * link status will be updated
239 */
240struct cgx_lnk_sts {
241	uint64_t reserved1:9;
242	uint64_t link_up:1;
243	uint64_t full_duplex:1;
244	uint64_t speed:4;		/* cgx_link_speed */
245	uint64_t err_type:10;
246	uint64_t an:1;			/* AN supported or not */
247	uint64_t fec:2;			/* FEC type if enabled, if not 0 */
248	uint64_t port:8;
249	uint64_t reserved2:28;
250};
251
252#define RESP_LINKSTAT_UP		GENMASK_ULL(9, 9)
253#define RESP_LINKSTAT_FDUPLEX		GENMASK_ULL(10, 10)
254#define RESP_LINKSTAT_SPEED		GENMASK_ULL(14, 11)
255#define RESP_LINKSTAT_ERRTYPE		GENMASK_ULL(24, 15)
256#define RESP_LINKSTAT_AN		GENMASK_ULL(25, 25)
257#define RESP_LINKSTAT_FEC		GENMASK_ULL(27, 26)
258#define RESP_LINKSTAT_PORT		GENMASK_ULL(35, 28)
259
260/* scratchx(1) CSR used for non-secure SW->ATF communication
261 * This CSR acts as a command register
262 */
263#define CMDREG_OWN	BIT_ULL(0)
264#define CMDREG_ID	GENMASK_ULL(7, 2)
265
266/* Any command using enable/disable as an argument need
267 * to set this bitfield.
268 * Ex: Loopback, HiGig...
269 */
270#define CMDREG_ENABLE	BIT_ULL(8)
271
272/* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
273#define CMDMTU_SIZE	GENMASK_ULL(23, 8)
274
275/* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
276#define CMDLINKCHANGE_LINKUP	BIT_ULL(8)
277#define CMDLINKCHANGE_FULLDPLX	BIT_ULL(9)
278#define CMDLINKCHANGE_SPEED	GENMASK_ULL(13, 10)
279
280#define CMDSETFEC			GENMASK_ULL(9, 8)
281/* command argument to be passed for cmd ID - CGX_CMD_MODE_CHANGE */
282#define CMDMODECHANGE_SPEED		GENMASK_ULL(11, 8)
283#define CMDMODECHANGE_DUPLEX		GENMASK_ULL(12, 12)
284#define CMDMODECHANGE_AN		GENMASK_ULL(13, 13)
285/* this field categorize the mode ID(FLAGS) range to accommodate
286 * more modes.
287 * To specify mode ID range of 0 - 41, this field will be 0.
288 * To specify mode ID range of 42 - 83, this field will be 1.
289 */
290#define CMDMODECHANGE_MODE_BASEIDX	GENMASK_ULL(21, 20)
291#define CMDMODECHANGE_FLAGS		GENMASK_ULL(63, 22)
292
293/* LINK_BRING_UP command timeout */
294#define LINKCFG_TIMEOUT		GENMASK_ULL(21, 8)
295#endif /* __CGX_FW_INTF_H__ */