octep_vf_tx.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
  3 *
  4 * Copyright (C) 2020 Marvell.
  5 *
  6 */
  7
  8#ifndef _OCTEP_VF_TX_H_
  9#define _OCTEP_VF_TX_H_
 10
 11#define IQ_SEND_OK          0
 12#define IQ_SEND_STOP        1
 13#define IQ_SEND_FAILED     -1
 14
 15#define TX_BUFTYPE_NONE          0
 16#define TX_BUFTYPE_NET           1
 17#define TX_BUFTYPE_NET_SG        2
 18#define NUM_TX_BUFTYPES          3
 19
 20/* Hardware format for Scatter/Gather list
 21 *
 22 * 63      48|47     32|31     16|15       0
 23 * -----------------------------------------
 24 * |  Len 0  |  Len 1  |  Len 2  |  Len 3  |
 25 * -----------------------------------------
 26 * |                Ptr 0                  |
 27 * -----------------------------------------
 28 * |                Ptr 1                  |
 29 * -----------------------------------------
 30 * |                Ptr 2                  |
 31 * -----------------------------------------
 32 * |                Ptr 3                  |
 33 * -----------------------------------------
 34 */
 35struct octep_vf_tx_sglist_desc {
 36	u16 len[4];
 37	dma_addr_t dma_ptr[4];
 38};
 39
 40static_assert(sizeof(struct octep_vf_tx_sglist_desc) == 40);
 41
 42/* Each Scatter/Gather entry sent to hardwar hold four pointers.
 43 * So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1'
 44 * is for main skb which also goes as a gather buffer to Octeon hardware.
 45 * To allocate sufficient SGLIST entries for a packet with max fragments,
 46 * align by adding 3 before calcuating max SGLIST entries per packet.
 47 */
 48#define OCTEP_VF_SGLIST_ENTRIES_PER_PKT ((MAX_SKB_FRAGS + 1 + 3) / 4)
 49#define OCTEP_VF_SGLIST_SIZE_PER_PKT \
 50	(OCTEP_VF_SGLIST_ENTRIES_PER_PKT * sizeof(struct octep_vf_tx_sglist_desc))
 51
 52struct octep_vf_tx_buffer {
 53	struct sk_buff *skb;
 54	dma_addr_t dma;
 55	struct octep_vf_tx_sglist_desc *sglist;
 56	dma_addr_t sglist_dma;
 57	u8 gather;
 58};
 59
 60#define OCTEP_VF_IQ_TXBUFF_INFO_SIZE (sizeof(struct octep_vf_tx_buffer))
 61
 62/* VF Hardware interface Tx statistics */
 63struct octep_vf_iface_tx_stats {
 64	/* Total frames sent on the interface */
 65	u64 pkts;
 66
 67	/* Total octets sent on the interface */
 68	u64 octs;
 69
 70	/* Packets sent to a broadcast DMAC */
 71	u64 bcst;
 72
 73	/* Packets sent to the multicast DMAC */
 74	u64 mcst;
 75
 76	/* Packets dropped */
 77	u64 dropped;
 78
 79	/* Reserved */
 80	u64 reserved[13];
 81};
 82
 83/* VF Input Queue statistics */
 84struct octep_vf_iq_stats {
 85	/* Instructions posted to this queue. */
 86	u64 instr_posted;
 87
 88	/* Instructions copied by hardware for processing. */
 89	u64 instr_completed;
 90
 91	/* Instructions that could not be processed. */
 92	u64 instr_dropped;
 93
 94	/* Bytes sent through this queue. */
 95	u64 bytes_sent;
 96
 97	/* Gather entries sent through this queue. */
 98	u64 sgentry_sent;
 99
100	/* Number of transmit failures due to TX_BUSY */
101	u64 tx_busy;
102
103	/* Number of times the queue is restarted */
104	u64 restart_cnt;
105};
106
107/* The instruction (input) queue.
108 * The input queue is used to post raw (instruction) mode data or packet
109 * data to Octeon device from the host. Each input queue (up to 4) for
110 * a Octeon device has one such structure to represent it.
111 */
112struct octep_vf_iq {
113	u32 q_no;
114
115	struct octep_vf_device *octep_vf_dev;
116	struct net_device *netdev;
117	struct device *dev;
118	struct netdev_queue *netdev_q;
119
120	/* Index in input ring where driver should write the next packet */
121	u16 host_write_index;
122
123	/* Index in input ring where Octeon is expected to read next packet */
124	u16 octep_vf_read_index;
125
126	/* This index aids in finding the window in the queue where Octeon
127	 * has read the commands.
128	 */
129	u16 flush_index;
130
131	/* Statistics for this input queue. */
132	struct octep_vf_iq_stats *stats;
133
134	/* Pointer to the Virtual Base addr of the input ring. */
135	struct octep_vf_tx_desc_hw *desc_ring;
136
137	/* DMA mapped base address of the input descriptor ring. */
138	dma_addr_t desc_ring_dma;
139
140	/* Info of Tx buffers pending completion. */
141	struct octep_vf_tx_buffer *buff_info;
142
143	/* Base pointer to Scatter/Gather lists for all ring descriptors. */
144	struct octep_vf_tx_sglist_desc *sglist;
145
146	/* DMA mapped addr of Scatter Gather Lists */
147	dma_addr_t sglist_dma;
148
149	/* Octeon doorbell register for the ring. */
150	u8 __iomem *doorbell_reg;
151
152	/* Octeon instruction count register for this ring. */
153	u8 __iomem *inst_cnt_reg;
154
155	/* interrupt level register for this ring */
156	u8 __iomem *intr_lvl_reg;
157
158	/* Maximum no. of instructions in this queue. */
159	u32 max_count;
160	u32 ring_size_mask;
161
162	u32 pkt_in_done;
163	u32 pkts_processed;
164
165	u32 status;
166
167	/* Number of instructions pending to be posted to Octeon. */
168	u32 fill_cnt;
169
170	/* The max. number of instructions that can be held pending by the
171	 * driver before ringing doorbell.
172	 */
173	u32 fill_threshold;
174};
175
176/* Hardware Tx Instruction Header */
177struct octep_vf_instr_hdr {
178	/* Data Len */
179	u64 tlen:16;
180
181	/* Reserved */
182	u64 rsvd:20;
183
184	/* PKIND for SDP */
185	u64 pkind:6;
186
187	/* Front Data size */
188	u64 fsz:6;
189
190	/* No. of entries in gather list */
191	u64 gsz:14;
192
193	/* Gather indicator 1=gather*/
194	u64 gather:1;
195
196	/* Reserved3 */
197	u64 reserved3:1;
198};
199
200static_assert(sizeof(struct octep_vf_instr_hdr) == 8);
201
202/* Tx offload flags */
203#define OCTEP_VF_TX_OFFLOAD_VLAN_INSERT	BIT(0)
204#define OCTEP_VF_TX_OFFLOAD_IPV4_CKSUM	BIT(1)
205#define OCTEP_VF_TX_OFFLOAD_UDP_CKSUM	BIT(2)
206#define OCTEP_VF_TX_OFFLOAD_TCP_CKSUM	BIT(3)
207#define OCTEP_VF_TX_OFFLOAD_SCTP_CKSUM	BIT(4)
208#define OCTEP_VF_TX_OFFLOAD_TCP_TSO	BIT(5)
209#define OCTEP_VF_TX_OFFLOAD_UDP_TSO	BIT(6)
210
211#define OCTEP_VF_TX_OFFLOAD_CKSUM	(OCTEP_VF_TX_OFFLOAD_IPV4_CKSUM | \
212					 OCTEP_VF_TX_OFFLOAD_UDP_CKSUM | \
213					 OCTEP_VF_TX_OFFLOAD_TCP_CKSUM)
214
215#define OCTEP_VF_TX_OFFLOAD_TSO		(OCTEP_VF_TX_OFFLOAD_TCP_TSO | \
216					 OCTEP_VF_TX_OFFLOAD_UDP_TSO)
217
218#define OCTEP_VF_TX_IP_CSUM(flags)	((flags) & \
219					 (OCTEP_VF_TX_OFFLOAD_IPV4_CKSUM | \
220					  OCTEP_VF_TX_OFFLOAD_TCP_CKSUM | \
221					  OCTEP_VF_TX_OFFLOAD_UDP_CKSUM))
222
223#define OCTEP_VF_TX_TSO(flags)		((flags) & \
224					 (OCTEP_VF_TX_OFFLOAD_TCP_TSO | \
225					  OCTEP_VF_TX_OFFLOAD_UDP_TSO))
226
227struct tx_mdata {
228	/* offload flags */
229	u16 ol_flags;
230
231	/* gso size */
232	u16 gso_size;
233
234	/* gso flags */
235	u16 gso_segs;
236
237	/* reserved */
238	u16 rsvd1;
239
240	/* reserved */
241	u64 rsvd2;
242};
243
244static_assert(sizeof(struct tx_mdata) == 16);
245
246/* 64-byte Tx instruction format.
247 * Format of instruction for a 64-byte mode input queue.
248 *
249 * only first 16-bytes (dptr and ih) are mandatory; rest are optional
250 * and filled by the driver based on firmware/hardware capabilities.
251 * These optional headers together called Front Data and its size is
252 * described by ih->fsz.
253 */
254struct octep_vf_tx_desc_hw {
255	/* Pointer where the input data is available. */
256	u64 dptr;
257
258	/* Instruction Header. */
259	union {
260		struct octep_vf_instr_hdr ih;
261		u64 ih64;
262	};
263
264	union  {
265		u64 txm64[2];
266		struct tx_mdata txm;
267	};
268
269	/* Additional headers available in a 64-byte instruction. */
270	u64 exhdr[4];
271};
272
273static_assert(sizeof(struct octep_vf_tx_desc_hw) == 64);
274
275#define OCTEP_VF_IQ_DESC_SIZE (sizeof(struct octep_vf_tx_desc_hw))
276#endif /* _OCTEP_VF_TX_H_ */