octep_vf_regs_cnxk.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
  3 *
  4 * Copyright (C) 2020 Marvell.
  5 *
  6 */
  7#ifndef _OCTEP_VF_REGS_CNXK_H_
  8#define _OCTEP_VF_REGS_CNXK_H_
  9
 10/*############################ RST #########################*/
 11#define     CNXK_VF_CONFIG_XPANSION_BAR         0x38
 12#define     CNXK_VF_CONFIG_PCIE_CAP             0x70
 13#define     CNXK_VF_CONFIG_PCIE_DEVCAP          0x74
 14#define     CNXK_VF_CONFIG_PCIE_DEVCTL          0x78
 15#define     CNXK_VF_CONFIG_PCIE_LINKCAP         0x7C
 16#define     CNXK_VF_CONFIG_PCIE_LINKCTL         0x80
 17#define     CNXK_VF_CONFIG_PCIE_SLOTCAP         0x84
 18#define     CNXK_VF_CONFIG_PCIE_SLOTCTL         0x88
 19
 20#define     CNXK_VF_RING_OFFSET                    (0x1ULL << 17)
 21
 22/*###################### RING IN REGISTERS #########################*/
 23#define    CNXK_VF_SDP_R_IN_CONTROL_START          0x10000
 24#define    CNXK_VF_SDP_R_IN_ENABLE_START           0x10010
 25#define    CNXK_VF_SDP_R_IN_INSTR_BADDR_START      0x10020
 26#define    CNXK_VF_SDP_R_IN_INSTR_RSIZE_START      0x10030
 27#define    CNXK_VF_SDP_R_IN_INSTR_DBELL_START      0x10040
 28#define    CNXK_VF_SDP_R_IN_CNTS_START             0x10050
 29#define    CNXK_VF_SDP_R_IN_INT_LEVELS_START       0x10060
 30#define    CNXK_VF_SDP_R_IN_PKT_CNT_START          0x10080
 31#define    CNXK_VF_SDP_R_IN_BYTE_CNT_START         0x10090
 32#define    CNXK_VF_SDP_R_ERR_TYPE_START            0x10400
 33
 34#define CNXK_VF_SDP_R_ERR_TYPE(ring)                 \
 35	(CNXK_VF_SDP_R_ERR_TYPE_START + ((ring) * CNXK_VF_RING_OFFSET))
 36
 37#define    CNXK_VF_SDP_R_IN_CONTROL(ring)          \
 38	(CNXK_VF_SDP_R_IN_CONTROL_START + ((ring) * CNXK_VF_RING_OFFSET))
 39
 40#define    CNXK_VF_SDP_R_IN_ENABLE(ring)          \
 41	(CNXK_VF_SDP_R_IN_ENABLE_START + ((ring) * CNXK_VF_RING_OFFSET))
 42
 43#define    CNXK_VF_SDP_R_IN_INSTR_BADDR(ring)          \
 44	(CNXK_VF_SDP_R_IN_INSTR_BADDR_START + ((ring) * CNXK_VF_RING_OFFSET))
 45
 46#define    CNXK_VF_SDP_R_IN_INSTR_RSIZE(ring)          \
 47	(CNXK_VF_SDP_R_IN_INSTR_RSIZE_START + ((ring) * CNXK_VF_RING_OFFSET))
 48
 49#define    CNXK_VF_SDP_R_IN_INSTR_DBELL(ring)          \
 50	(CNXK_VF_SDP_R_IN_INSTR_DBELL_START + ((ring) * CNXK_VF_RING_OFFSET))
 51
 52#define    CNXK_VF_SDP_R_IN_CNTS(ring)          \
 53	(CNXK_VF_SDP_R_IN_CNTS_START + ((ring) * CNXK_VF_RING_OFFSET))
 54
 55#define    CNXK_VF_SDP_R_IN_INT_LEVELS(ring)          \
 56	(CNXK_VF_SDP_R_IN_INT_LEVELS_START + ((ring) * CNXK_VF_RING_OFFSET))
 57
 58#define    CNXK_VF_SDP_R_IN_PKT_CNT(ring)          \
 59	(CNXK_VF_SDP_R_IN_PKT_CNT_START + ((ring) * CNXK_VF_RING_OFFSET))
 60
 61#define    CNXK_VF_SDP_R_IN_BYTE_CNT(ring)          \
 62	(CNXK_VF_SDP_R_IN_BYTE_CNT_START + ((ring) * CNXK_VF_RING_OFFSET))
 63
 64/*------------------ R_IN Masks ----------------*/
 65
 66/** Rings per Virtual Function **/
 67#define    CNXK_VF_R_IN_CTL_RPVF_MASK    (0xF)
 68#define	   CNXK_VF_R_IN_CTL_RPVF_POS     (48)
 69
 70/* Number of instructions to be read in one MAC read request.
 71 * setting to Max value(4)
 72 **/
 73#define    CNXK_VF_R_IN_CTL_IDLE                  (0x1ULL << 28)
 74#define    CNXK_VF_R_IN_CTL_RDSIZE                (0x3ULL << 25)
 75#define    CNXK_VF_R_IN_CTL_IS_64B                (0x1ULL << 24)
 76#define    CNXK_VF_R_IN_CTL_D_NSR                 (0x1ULL << 8)
 77#define    CNXK_VF_R_IN_CTL_D_ESR                 (0x1ULL << 6)
 78#define    CNXK_VF_R_IN_CTL_D_ROR                 (0x1ULL << 5)
 79#define    CNXK_VF_R_IN_CTL_NSR                   (0x1ULL << 3)
 80#define    CNXK_VF_R_IN_CTL_ESR                   (0x1ULL << 1)
 81#define    CNXK_VF_R_IN_CTL_ROR                   (0x1ULL << 0)
 82
 83#define    CNXK_VF_R_IN_CTL_MASK     (CNXK_VF_R_IN_CTL_RDSIZE | CNXK_VF_R_IN_CTL_IS_64B)
 84
 85/*###################### RING OUT REGISTERS #########################*/
 86#define    CNXK_VF_SDP_R_OUT_CNTS_START            0x10100
 87#define    CNXK_VF_SDP_R_OUT_INT_LEVELS_START      0x10110
 88#define    CNXK_VF_SDP_R_OUT_SLIST_BADDR_START     0x10120
 89#define    CNXK_VF_SDP_R_OUT_SLIST_RSIZE_START     0x10130
 90#define    CNXK_VF_SDP_R_OUT_SLIST_DBELL_START     0x10140
 91#define    CNXK_VF_SDP_R_OUT_CONTROL_START         0x10150
 92#define    CNXK_VF_SDP_R_OUT_WMARK_START           0x10160
 93#define    CNXK_VF_SDP_R_OUT_ENABLE_START          0x10170
 94#define    CNXK_VF_SDP_R_OUT_PKT_CNT_START         0x10180
 95#define    CNXK_VF_SDP_R_OUT_BYTE_CNT_START        0x10190
 96
 97#define    CNXK_VF_SDP_R_OUT_CONTROL(ring)          \
 98	(CNXK_VF_SDP_R_OUT_CONTROL_START + ((ring) * CNXK_VF_RING_OFFSET))
 99
100#define    CNXK_VF_SDP_R_OUT_ENABLE(ring)          \
101	(CNXK_VF_SDP_R_OUT_ENABLE_START + ((ring) * CNXK_VF_RING_OFFSET))
102
103#define    CNXK_VF_SDP_R_OUT_SLIST_BADDR(ring)          \
104	(CNXK_VF_SDP_R_OUT_SLIST_BADDR_START + ((ring) * CNXK_VF_RING_OFFSET))
105
106#define    CNXK_VF_SDP_R_OUT_SLIST_RSIZE(ring)          \
107	(CNXK_VF_SDP_R_OUT_SLIST_RSIZE_START + ((ring) * CNXK_VF_RING_OFFSET))
108
109#define    CNXK_VF_SDP_R_OUT_SLIST_DBELL(ring)          \
110	(CNXK_VF_SDP_R_OUT_SLIST_DBELL_START + ((ring) * CNXK_VF_RING_OFFSET))
111
112#define    CNXK_VF_SDP_R_OUT_WMARK(ring)          \
113	(CNXK_VF_SDP_R_OUT_WMARK_START + ((ring) * CNXK_VF_RING_OFFSET))
114
115#define    CNXK_VF_SDP_R_OUT_CNTS(ring)          \
116	(CNXK_VF_SDP_R_OUT_CNTS_START + ((ring) * CNXK_VF_RING_OFFSET))
117
118#define    CNXK_VF_SDP_R_OUT_INT_LEVELS(ring)          \
119	(CNXK_VF_SDP_R_OUT_INT_LEVELS_START + ((ring) * CNXK_VF_RING_OFFSET))
120
121#define    CNXK_VF_SDP_R_OUT_PKT_CNT(ring)          \
122	(CNXK_VF_SDP_R_OUT_PKT_CNT_START + ((ring) * CNXK_VF_RING_OFFSET))
123
124#define    CNXK_VF_SDP_R_OUT_BYTE_CNT(ring)          \
125	(CNXK_VF_SDP_R_OUT_BYTE_CNT_START + ((ring) * CNXK_VF_RING_OFFSET))
126
127/*------------------ R_OUT Masks ----------------*/
128#define    CNXK_VF_R_OUT_INT_LEVELS_BMODE            BIT_ULL(63)
129#define    CNXK_VF_R_OUT_INT_LEVELS_TIMET            (32)
130
131#define    CNXK_VF_R_OUT_CTL_IDLE                    BIT_ULL(40)
132#define    CNXK_VF_R_OUT_CTL_ES_I                    BIT_ULL(34)
133#define    CNXK_VF_R_OUT_CTL_NSR_I                   BIT_ULL(33)
134#define    CNXK_VF_R_OUT_CTL_ROR_I                   BIT_ULL(32)
135#define    CNXK_VF_R_OUT_CTL_ES_D                    BIT_ULL(30)
136#define    CNXK_VF_R_OUT_CTL_NSR_D                   BIT_ULL(29)
137#define    CNXK_VF_R_OUT_CTL_ROR_D                   BIT_ULL(28)
138#define    CNXK_VF_R_OUT_CTL_ES_P                    BIT_ULL(26)
139#define    CNXK_VF_R_OUT_CTL_NSR_P                   BIT_ULL(25)
140#define    CNXK_VF_R_OUT_CTL_ROR_P                   BIT_ULL(24)
141#define    CNXK_VF_R_OUT_CTL_IMODE                   BIT_ULL(23)
142
143/* ##################### Mail Box Registers ########################## */
144/* SDP PF to VF Mailbox Data Register */
145#define    CNXK_VF_SDP_R_MBOX_PF_VF_DATA_START    0x10210
146/* SDP Packet PF to VF Mailbox Interrupt Register */
147#define    CNXK_VF_SDP_R_MBOX_PF_VF_INT_START     0x10220
148/* SDP VF to PF Mailbox Data Register */
149#define    CNXK_VF_SDP_R_MBOX_VF_PF_DATA_START    0x10230
150
151#define    CNXK_VF_SDP_R_MBOX_PF_VF_INT_ENAB         BIT_ULL(1)
152#define    CNXK_VF_SDP_R_MBOX_PF_VF_INT_STATUS       BIT_ULL(0)
153
154#define    CNXK_VF_SDP_R_MBOX_PF_VF_DATA(ring)          \
155	(CNXK_VF_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CNXK_VF_RING_OFFSET))
156
157#define    CNXK_VF_SDP_R_MBOX_PF_VF_INT(ring)          \
158	(CNXK_VF_SDP_R_MBOX_PF_VF_INT_START + ((ring) * CNXK_VF_RING_OFFSET))
159
160#define    CNXK_VF_SDP_R_MBOX_VF_PF_DATA(ring)          \
161	(CNXK_VF_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CNXK_VF_RING_OFFSET))
162#endif /* _OCTEP_VF_REGS_CNXK_H_ */