FILE
octep_regs_cn9k_pf.h
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linux-6.19.14/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8#ifndef _OCTEP_REGS_CN9K_PF_H_ 9#define _OCTEP_REGS_CN9K_PF_H_ 10 11/* ############################ RST ######################### */ 12#define CN93_RST_BOOT 0x000087E006001600ULL 13#define CN93_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL 14#define CN93_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL 15 16#define CN93_CONFIG_XPANSION_BAR 0x38 17#define CN93_CONFIG_PCIE_CAP 0x70 18#define CN93_CONFIG_PCIE_DEVCAP 0x74 19#define CN93_CONFIG_PCIE_DEVCTL 0x78 20#define CN93_CONFIG_PCIE_LINKCAP 0x7C 21#define CN93_CONFIG_PCIE_LINKCTL 0x80 22#define CN93_CONFIG_PCIE_SLOTCAP 0x84 23#define CN93_CONFIG_PCIE_SLOTCTL 0x88 24 25#define CN93_PCIE_SRIOV_FDL 0x188 /* 0x98 */ 26#define CN93_PCIE_SRIOV_FDL_BIT_POS 0x10 27#define CN93_PCIE_SRIOV_FDL_MASK 0xFF 28 29#define CN93_CONFIG_PCIE_FLTMSK 0x720 30 31/* ################# Offsets of RING, EPF, MAC ######################### */ 32#define CN93_RING_OFFSET (0x1ULL << 17) 33#define CN93_EPF_OFFSET (0x1ULL << 25) 34#define CN93_MAC_OFFSET (0x1ULL << 4) 35#define CN93_BIT_ARRAY_OFFSET (0x1ULL << 4) 36#define CN93_EPVF_RING_OFFSET (0x1ULL << 4) 37 38/* ################# Scratch Registers ######################### */ 39#define CN93_SDP_EPF_SCRATCH 0x205E0 40 41/* ################# Window Registers ######################### */ 42#define CN93_SDP_WIN_WR_ADDR64 0x20000 43#define CN93_SDP_WIN_RD_ADDR64 0x20010 44#define CN93_SDP_WIN_WR_DATA64 0x20020 45#define CN93_SDP_WIN_WR_MASK_REG 0x20030 46#define CN93_SDP_WIN_RD_DATA64 0x20040 47 48#define CN93_SDP_MAC_NUMBER 0x2C100 49 50/* ################# Global Previliged registers ######################### */ 51#define CN93_SDP_EPF_RINFO 0x205F0 52 53#define CN93_SDP_EPF_RINFO_SRN(val) ((val) & 0xFF) 54#define CN93_SDP_EPF_RINFO_RPVF(val) (((val) >> 32) & 0xF) 55#define CN93_SDP_EPF_RINFO_NVFS(val) (((val) >> 48) & 0xFF) 56 57/* SDP Function select */ 58#define CN93_SDP_FUNC_SEL_EPF_BIT_POS 8 59#define CN93_SDP_FUNC_SEL_FUNC_BIT_POS 0 60 61/* ##### RING IN (Into device from PCI: Tx Ring) REGISTERS #### */ 62#define CN93_SDP_R_IN_CONTROL_START 0x10000 63#define CN93_SDP_R_IN_ENABLE_START 0x10010 64#define CN93_SDP_R_IN_INSTR_BADDR_START 0x10020 65#define CN93_SDP_R_IN_INSTR_RSIZE_START 0x10030 66#define CN93_SDP_R_IN_INSTR_DBELL_START 0x10040 67#define CN93_SDP_R_IN_CNTS_START 0x10050 68#define CN93_SDP_R_IN_INT_LEVELS_START 0x10060 69#define CN93_SDP_R_IN_PKT_CNT_START 0x10080 70#define CN93_SDP_R_IN_BYTE_CNT_START 0x10090 71 72#define CN93_SDP_R_IN_CONTROL(ring) \ 73 (CN93_SDP_R_IN_CONTROL_START + ((ring) * CN93_RING_OFFSET)) 74 75#define CN93_SDP_R_IN_ENABLE(ring) \ 76 (CN93_SDP_R_IN_ENABLE_START + ((ring) * CN93_RING_OFFSET)) 77 78#define CN93_SDP_R_IN_INSTR_BADDR(ring) \ 79 (CN93_SDP_R_IN_INSTR_BADDR_START + ((ring) * CN93_RING_OFFSET)) 80 81#define CN93_SDP_R_IN_INSTR_RSIZE(ring) \ 82 (CN93_SDP_R_IN_INSTR_RSIZE_START + ((ring) * CN93_RING_OFFSET)) 83 84#define CN93_SDP_R_IN_INSTR_DBELL(ring) \ 85 (CN93_SDP_R_IN_INSTR_DBELL_START + ((ring) * CN93_RING_OFFSET)) 86 87#define CN93_SDP_R_IN_CNTS(ring) \ 88 (CN93_SDP_R_IN_CNTS_START + ((ring) * CN93_RING_OFFSET)) 89 90#define CN93_SDP_R_IN_INT_LEVELS(ring) \ 91 (CN93_SDP_R_IN_INT_LEVELS_START + ((ring) * CN93_RING_OFFSET)) 92 93#define CN93_SDP_R_IN_PKT_CNT(ring) \ 94 (CN93_SDP_R_IN_PKT_CNT_START + ((ring) * CN93_RING_OFFSET)) 95 96#define CN93_SDP_R_IN_BYTE_CNT(ring) \ 97 (CN93_SDP_R_IN_BYTE_CNT_START + ((ring) * CN93_RING_OFFSET)) 98 99/* Rings per Virtual Function */ 100#define CN93_R_IN_CTL_RPVF_MASK (0xF) 101#define CN93_R_IN_CTL_RPVF_POS (48) 102 103/* Number of instructions to be read in one MAC read request. 104 * setting to Max value(4) 105 */ 106#define CN93_R_IN_CTL_IDLE (0x1ULL << 28) 107#define CN93_R_IN_CTL_RDSIZE (0x3ULL << 25) 108#define CN93_R_IN_CTL_IS_64B (0x1ULL << 24) 109#define CN93_R_IN_CTL_D_NSR (0x1ULL << 8) 110#define CN93_R_IN_CTL_D_ESR (0x1ULL << 6) 111#define CN93_R_IN_CTL_D_ROR (0x1ULL << 5) 112#define CN93_R_IN_CTL_NSR (0x1ULL << 3) 113#define CN93_R_IN_CTL_ESR (0x1ULL << 1) 114#define CN93_R_IN_CTL_ROR (0x1ULL << 0) 115 116#define CN93_R_IN_CTL_MASK (CN93_R_IN_CTL_RDSIZE | CN93_R_IN_CTL_IS_64B) 117 118/* ##### RING OUT (out from device to PCI host: Rx Ring) REGISTERS #### */ 119#define CN93_SDP_R_OUT_CNTS_START 0x10100 120#define CN93_SDP_R_OUT_INT_LEVELS_START 0x10110 121#define CN93_SDP_R_OUT_SLIST_BADDR_START 0x10120 122#define CN93_SDP_R_OUT_SLIST_RSIZE_START 0x10130 123#define CN93_SDP_R_OUT_SLIST_DBELL_START 0x10140 124#define CN93_SDP_R_OUT_CONTROL_START 0x10150 125#define CN93_SDP_R_OUT_ENABLE_START 0x10160 126#define CN93_SDP_R_OUT_PKT_CNT_START 0x10180 127#define CN93_SDP_R_OUT_BYTE_CNT_START 0x10190 128 129#define CN93_SDP_R_OUT_CONTROL(ring) \ 130 (CN93_SDP_R_OUT_CONTROL_START + ((ring) * CN93_RING_OFFSET)) 131 132#define CN93_SDP_R_OUT_ENABLE(ring) \ 133 (CN93_SDP_R_OUT_ENABLE_START + ((ring) * CN93_RING_OFFSET)) 134 135#define CN93_SDP_R_OUT_SLIST_BADDR(ring) \ 136 (CN93_SDP_R_OUT_SLIST_BADDR_START + ((ring) * CN93_RING_OFFSET)) 137 138#define CN93_SDP_R_OUT_SLIST_RSIZE(ring) \ 139 (CN93_SDP_R_OUT_SLIST_RSIZE_START + ((ring) * CN93_RING_OFFSET)) 140 141#define CN93_SDP_R_OUT_SLIST_DBELL(ring) \ 142 (CN93_SDP_R_OUT_SLIST_DBELL_START + ((ring) * CN93_RING_OFFSET)) 143 144#define CN93_SDP_R_OUT_CNTS(ring) \ 145 (CN93_SDP_R_OUT_CNTS_START + ((ring) * CN93_RING_OFFSET)) 146 147#define CN93_SDP_R_OUT_INT_LEVELS(ring) \ 148 (CN93_SDP_R_OUT_INT_LEVELS_START + ((ring) * CN93_RING_OFFSET)) 149 150#define CN93_SDP_R_OUT_PKT_CNT(ring) \ 151 (CN93_SDP_R_OUT_PKT_CNT_START + ((ring) * CN93_RING_OFFSET)) 152 153#define CN93_SDP_R_OUT_BYTE_CNT(ring) \ 154 (CN93_SDP_R_OUT_BYTE_CNT_START + ((ring) * CN93_RING_OFFSET)) 155 156/*------------------ R_OUT Masks ----------------*/ 157#define CN93_R_OUT_INT_LEVELS_BMODE BIT_ULL(63) 158#define CN93_R_OUT_INT_LEVELS_TIMET (32) 159 160#define CN93_R_OUT_CTL_IDLE BIT_ULL(40) 161#define CN93_R_OUT_CTL_ES_I BIT_ULL(34) 162#define CN93_R_OUT_CTL_NSR_I BIT_ULL(33) 163#define CN93_R_OUT_CTL_ROR_I BIT_ULL(32) 164#define CN93_R_OUT_CTL_ES_D BIT_ULL(30) 165#define CN93_R_OUT_CTL_NSR_D BIT_ULL(29) 166#define CN93_R_OUT_CTL_ROR_D BIT_ULL(28) 167#define CN93_R_OUT_CTL_ES_P BIT_ULL(26) 168#define CN93_R_OUT_CTL_NSR_P BIT_ULL(25) 169#define CN93_R_OUT_CTL_ROR_P BIT_ULL(24) 170#define CN93_R_OUT_CTL_IMODE BIT_ULL(23) 171 172/* ############### Interrupt Moderation Registers ############### */ 173#define CN93_SDP_R_IN_INT_MDRT_CTL0_START 0x10280 174#define CN93_SDP_R_IN_INT_MDRT_CTL1_START 0x102A0 175#define CN93_SDP_R_IN_INT_MDRT_DBG_START 0x102C0 176 177#define CN93_SDP_R_OUT_INT_MDRT_CTL0_START 0x10380 178#define CN93_SDP_R_OUT_INT_MDRT_CTL1_START 0x103A0 179#define CN93_SDP_R_OUT_INT_MDRT_DBG_START 0x103C0 180 181#define CN93_SDP_R_IN_INT_MDRT_CTL0(ring) \ 182 (CN93_SDP_R_IN_INT_MDRT_CTL0_START + ((ring) * CN93_RING_OFFSET)) 183 184#define CN93_SDP_R_IN_INT_MDRT_CTL1(ring) \ 185 (CN93_SDP_R_IN_INT_MDRT_CTL1_START + ((ring) * CN93_RING_OFFSET)) 186 187#define CN93_SDP_R_IN_INT_MDRT_DBG(ring) \ 188 (CN93_SDP_R_IN_INT_MDRT_DBG_START + ((ring) * CN93_RING_OFFSET)) 189 190#define CN93_SDP_R_OUT_INT_MDRT_CTL0(ring) \ 191 (CN93_SDP_R_OUT_INT_MDRT_CTL0_START + ((ring) * CN93_RING_OFFSET)) 192 193#define CN93_SDP_R_OUT_INT_MDRT_CTL1(ring) \ 194 (CN93_SDP_R_OUT_INT_MDRT_CTL1_START + ((ring) * CN93_RING_OFFSET)) 195 196#define CN93_SDP_R_OUT_INT_MDRT_DBG(ring) \ 197 (CN93_SDP_R_OUT_INT_MDRT_DBG_START + ((ring) * CN93_RING_OFFSET)) 198 199/* ##################### Mail Box Registers ########################## */ 200/* INT register for VF. when a MBOX write from PF happed to a VF, 201 * corresponding bit will be set in this register as well as in 202 * PF_VF_INT register. 203 * 204 * This is a RO register, the int can be cleared by writing 1 to PF_VF_INT 205 */ 206/* Basically first 3 are from PF to VF. The last one is data from VF to PF */ 207#define CN93_SDP_R_MBOX_PF_VF_DATA_START 0x10210 208#define CN93_SDP_R_MBOX_PF_VF_INT_START 0x10220 209#define CN93_SDP_R_MBOX_VF_PF_DATA_START 0x10230 210 211#define CN93_SDP_MBOX_VF_PF_DATA_START 0x24000 212#define CN93_SDP_MBOX_PF_VF_DATA_START 0x22000 213 214#define CN93_SDP_R_MBOX_PF_VF_DATA(ring) \ 215 (CN93_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CN93_RING_OFFSET)) 216 217#define CN93_SDP_R_MBOX_PF_VF_INT(ring) \ 218 (CN93_SDP_R_MBOX_PF_VF_INT_START + ((ring) * CN93_RING_OFFSET)) 219 220#define CN93_SDP_R_MBOX_VF_PF_DATA(ring) \ 221 (CN93_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CN93_RING_OFFSET)) 222 223#define CN93_SDP_MBOX_VF_PF_DATA(ring) \ 224 (CN93_SDP_MBOX_VF_PF_DATA_START + ((ring) * CN93_EPVF_RING_OFFSET)) 225 226#define CN93_SDP_MBOX_PF_VF_DATA(ring) \ 227 (CN93_SDP_MBOX_PF_VF_DATA_START + ((ring) * CN93_EPVF_RING_OFFSET)) 228 229/* ##################### Interrupt Registers ########################## */ 230#define CN93_SDP_R_ERR_TYPE_START 0x10400 231 232#define CN93_SDP_R_ERR_TYPE(ring) \ 233 (CN93_SDP_R_ERR_TYPE_START + ((ring) * CN93_RING_OFFSET)) 234 235#define CN93_SDP_R_MBOX_ISM_START 0x10500 236#define CN93_SDP_R_OUT_CNTS_ISM_START 0x10510 237#define CN93_SDP_R_IN_CNTS_ISM_START 0x10520 238 239#define CN93_SDP_R_MBOX_ISM(ring) \ 240 (CN93_SDP_R_MBOX_ISM_START + ((ring) * CN93_RING_OFFSET)) 241 242#define CN93_SDP_R_OUT_CNTS_ISM(ring) \ 243 (CN93_SDP_R_OUT_CNTS_ISM_START + ((ring) * CN93_RING_OFFSET)) 244 245#define CN93_SDP_R_IN_CNTS_ISM(ring) \ 246 (CN93_SDP_R_IN_CNTS_ISM_START + ((ring) * CN93_RING_OFFSET)) 247 248#define CN93_SDP_EPF_MBOX_RINT_START 0x20100 249#define CN93_SDP_EPF_MBOX_RINT_W1S_START 0x20120 250#define CN93_SDP_EPF_MBOX_RINT_ENA_W1C_START 0x20140 251#define CN93_SDP_EPF_MBOX_RINT_ENA_W1S_START 0x20160 252 253#define CN93_SDP_EPF_VFIRE_RINT_START 0x20180 254#define CN93_SDP_EPF_VFIRE_RINT_W1S_START 0x201A0 255#define CN93_SDP_EPF_VFIRE_RINT_ENA_W1C_START 0x201C0 256#define CN93_SDP_EPF_VFIRE_RINT_ENA_W1S_START 0x201E0 257 258#define CN93_SDP_EPF_IRERR_RINT 0x20200 259#define CN93_SDP_EPF_IRERR_RINT_W1S 0x20210 260#define CN93_SDP_EPF_IRERR_RINT_ENA_W1C 0x20220 261#define CN93_SDP_EPF_IRERR_RINT_ENA_W1S 0x20230 262 263#define CN93_SDP_EPF_VFORE_RINT_START 0x20240 264#define CN93_SDP_EPF_VFORE_RINT_W1S_START 0x20260 265#define CN93_SDP_EPF_VFORE_RINT_ENA_W1C_START 0x20280 266#define CN93_SDP_EPF_VFORE_RINT_ENA_W1S_START 0x202A0 267 268#define CN93_SDP_EPF_ORERR_RINT 0x20320 269#define CN93_SDP_EPF_ORERR_RINT_W1S 0x20330 270#define CN93_SDP_EPF_ORERR_RINT_ENA_W1C 0x20340 271#define CN93_SDP_EPF_ORERR_RINT_ENA_W1S 0x20350 272 273#define CN93_SDP_EPF_OEI_RINT 0x20360 274#define CN93_SDP_EPF_OEI_RINT_W1S 0x20370 275#define CN93_SDP_EPF_OEI_RINT_ENA_W1C 0x20380 276#define CN93_SDP_EPF_OEI_RINT_ENA_W1S 0x20390 277 278#define CN93_SDP_EPF_DMA_RINT 0x20400 279#define CN93_SDP_EPF_DMA_RINT_W1S 0x20410 280#define CN93_SDP_EPF_DMA_RINT_ENA_W1C 0x20420 281#define CN93_SDP_EPF_DMA_RINT_ENA_W1S 0x20430 282 283#define CN93_SDP_EPF_DMA_INT_LEVEL_START 0x20440 284#define CN93_SDP_EPF_DMA_CNT_START 0x20460 285#define CN93_SDP_EPF_DMA_TIM_START 0x20480 286 287#define CN93_SDP_EPF_MISC_RINT 0x204A0 288#define CN93_SDP_EPF_MISC_RINT_W1S 0x204B0 289#define CN93_SDP_EPF_MISC_RINT_ENA_W1C 0x204C0 290#define CN93_SDP_EPF_MISC_RINT_ENA_W1S 0x204D0 291 292#define CN93_SDP_EPF_DMA_VF_RINT_START 0x204E0 293#define CN93_SDP_EPF_DMA_VF_RINT_W1S_START 0x20500 294#define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C_START 0x20520 295#define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S_START 0x20540 296 297#define CN93_SDP_EPF_PP_VF_RINT_START 0x20560 298#define CN93_SDP_EPF_PP_VF_RINT_W1S_START 0x20580 299#define CN93_SDP_EPF_PP_VF_RINT_ENA_W1C_START 0x205A0 300#define CN93_SDP_EPF_PP_VF_RINT_ENA_W1S_START 0x205C0 301 302#define CN93_SDP_EPF_MBOX_RINT(index) \ 303 (CN93_SDP_EPF_MBOX_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 304#define CN93_SDP_EPF_MBOX_RINT_W1S(index) \ 305 (CN93_SDP_EPF_MBOX_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 306#define CN93_SDP_EPF_MBOX_RINT_ENA_W1C(index) \ 307 (CN93_SDP_EPF_MBOX_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 308#define CN93_SDP_EPF_MBOX_RINT_ENA_W1S(index) \ 309 (CN93_SDP_EPF_MBOX_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 310 311#define CN93_SDP_EPF_VFIRE_RINT(index) \ 312 (CN93_SDP_EPF_VFIRE_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 313#define CN93_SDP_EPF_VFIRE_RINT_W1S(index) \ 314 (CN93_SDP_EPF_VFIRE_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 315#define CN93_SDP_EPF_VFIRE_RINT_ENA_W1C(index) \ 316 (CN93_SDP_EPF_VFIRE_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 317#define CN93_SDP_EPF_VFIRE_RINT_ENA_W1S(index) \ 318 (CN93_SDP_EPF_VFIRE_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 319 320#define CN93_SDP_EPF_VFORE_RINT(index) \ 321 (CN93_SDP_EPF_VFORE_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 322#define CN93_SDP_EPF_VFORE_RINT_W1S(index) \ 323 (CN93_SDP_EPF_VFORE_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 324#define CN93_SDP_EPF_VFORE_RINT_ENA_W1C(index) \ 325 (CN93_SDP_EPF_VFORE_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 326#define CN93_SDP_EPF_VFORE_RINT_ENA_W1S(index) \ 327 (CN93_SDP_EPF_VFORE_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 328 329#define CN93_SDP_EPF_DMA_VF_RINT(index) \ 330 (CN93_SDP_EPF_DMA_VF_RINT_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 331#define CN93_SDP_EPF_DMA_VF_RINT_W1S(index) \ 332 (CN93_SDP_EPF_DMA_VF_RINT_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 333#define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C(index) \ 334 (CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 335#define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S(index) \ 336 (CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 337 338#define CN93_SDP_EPF_PP_VF_RINT(index) \ 339 (CN93_SDP_EPF_PP_VF_RINT_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 340#define CN93_SDP_EPF_PP_VF_RINT_W1S(index) \ 341 (CN93_SDP_EPF_PP_VF_RINT_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 342#define CN93_SDP_EPF_PP_VF_RINT_ENA_W1C(index) \ 343 (CN93_SDP_EPF_PP_VF_RINT_ENA_W1C_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 344#define CN93_SDP_EPF_PP_VF_RINT_ENA_W1S(index) \ 345 (CN93_SDP_EPF_PP_VF_RINT_ENA_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 346 347/*------------------ Interrupt Masks ----------------*/ 348#define CN93_INTR_R_SEND_ISM BIT_ULL(63) 349#define CN93_INTR_R_OUT_INT BIT_ULL(62) 350#define CN93_INTR_R_IN_INT BIT_ULL(61) 351#define CN93_INTR_R_MBOX_INT BIT_ULL(60) 352#define CN93_INTR_R_RESEND BIT_ULL(59) 353#define CN93_INTR_R_CLR_TIM BIT_ULL(58) 354 355/* ####################### Ring Mapping Registers ################################## */ 356#define CN93_SDP_EPVF_RING_START 0x26000 357#define CN93_SDP_IN_RING_TB_MAP_START 0x28000 358#define CN93_SDP_IN_RATE_LIMIT_START 0x2A000 359#define CN93_SDP_MAC_PF_RING_CTL_START 0x2C000 360 361#define CN93_SDP_EPVF_RING(ring) \ 362 (CN93_SDP_EPVF_RING_START + ((ring) * CN93_EPVF_RING_OFFSET)) 363#define CN93_SDP_IN_RING_TB_MAP(ring) \ 364 (CN93_SDP_N_RING_TB_MAP_START + ((ring) * CN93_EPVF_RING_OFFSET)) 365#define CN93_SDP_IN_RATE_LIMIT(ring) \ 366 (CN93_SDP_IN_RATE_LIMIT_START + ((ring) * CN93_EPVF_RING_OFFSET)) 367#define CN93_SDP_MAC_PF_RING_CTL(mac) \ 368 (CN93_SDP_MAC_PF_RING_CTL_START + ((mac) * CN93_MAC_OFFSET)) 369 370#define CN93_SDP_MAC_PF_RING_CTL_NPFS(val) ((val) & 0xF) 371#define CN93_SDP_MAC_PF_RING_CTL_SRN(val) (((val) >> 8) & 0xFF) 372#define CN93_SDP_MAC_PF_RING_CTL_RPPF(val) (((val) >> 16) & 0x3F) 373 374#define CN98_SDP_MAC_PF_RING_CTL_NPFS(val) (((val) >> 48) & 0xF) 375#define CN98_SDP_MAC_PF_RING_CTL_SRN(val) ((val) & 0xFF) 376#define CN98_SDP_MAC_PF_RING_CTL_RPPF(val) (((val) >> 32) & 0x3F) 377 378/* Number of non-queue interrupts in CN93xx */ 379#define CN93_NUM_NON_IOQ_INTR 16 380 381/* bit 0 for control mbox interrupt */ 382#define CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0) 383/* bit 1 for firmware heartbeat interrupt */ 384#define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1) 385 386#define CN93_PEM_BAR4_INDEX 7 387#define CN93_PEM_BAR4_INDEX_SIZE 0x400000ULL 388#define CN93_PEM_BAR4_INDEX_OFFSET (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE) 389#define CN93_INT_ENA_BIT BIT_ULL(62) 390 391#endif /* _OCTEP_REGS_CN9K_PF_H_ */
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