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octep_cnxk_pf.c
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linux-6.19.14/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
1// SPDX-License-Identifier: GPL-2.0 2/* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8#include <linux/pci.h> 9#include <linux/netdevice.h> 10#include <linux/etherdevice.h> 11#include <linux/jiffies.h> 12 13#include "octep_config.h" 14#include "octep_main.h" 15#include "octep_regs_cnxk_pf.h" 16 17/* We will support 128 pf's in control mbox */ 18#define CTRL_MBOX_MAX_PF 128 19#define CTRL_MBOX_SZ ((size_t)(0x400000 / CTRL_MBOX_MAX_PF)) 20 21/* Names of Hardware non-queue generic interrupts */ 22static char *cnxk_non_ioq_msix_names[] = { 23 "epf_ire_rint", 24 "epf_ore_rint", 25 "epf_vfire_rint", 26 "epf_rsvd0", 27 "epf_vfore_rint", 28 "epf_rsvd1", 29 "epf_mbox_rint", 30 "epf_rsvd2_0", 31 "epf_rsvd2_1", 32 "epf_dma_rint", 33 "epf_dma_vf_rint", 34 "epf_rsvd3", 35 "epf_pp_vf_rint", 36 "epf_rsvd3", 37 "epf_misc_rint", 38 "epf_rsvd5", 39 /* Next 16 are for OEI_RINT */ 40 "epf_oei_rint0", 41 "epf_oei_rint1", 42 "epf_oei_rint2", 43 "epf_oei_rint3", 44 "epf_oei_rint4", 45 "epf_oei_rint5", 46 "epf_oei_rint6", 47 "epf_oei_rint7", 48 "epf_oei_rint8", 49 "epf_oei_rint9", 50 "epf_oei_rint10", 51 "epf_oei_rint11", 52 "epf_oei_rint12", 53 "epf_oei_rint13", 54 "epf_oei_rint14", 55 "epf_oei_rint15", 56 /* IOQ interrupt */ 57 "octeon_ep" 58}; 59 60/* Dump useful hardware CSRs for debug purpose */ 61static void cnxk_dump_regs(struct octep_device *oct, int qno) 62{ 63 struct device *dev = &oct->pdev->dev; 64 65 dev_info(dev, "IQ-%d register dump\n", qno); 66 dev_info(dev, "R[%d]_IN_INSTR_DBELL[0x%llx]: 0x%016llx\n", 67 qno, CNXK_SDP_R_IN_INSTR_DBELL(qno), 68 octep_read_csr64(oct, CNXK_SDP_R_IN_INSTR_DBELL(qno))); 69 dev_info(dev, "R[%d]_IN_CONTROL[0x%llx]: 0x%016llx\n", 70 qno, CNXK_SDP_R_IN_CONTROL(qno), 71 octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(qno))); 72 dev_info(dev, "R[%d]_IN_ENABLE[0x%llx]: 0x%016llx\n", 73 qno, CNXK_SDP_R_IN_ENABLE(qno), 74 octep_read_csr64(oct, CNXK_SDP_R_IN_ENABLE(qno))); 75 dev_info(dev, "R[%d]_IN_INSTR_BADDR[0x%llx]: 0x%016llx\n", 76 qno, CNXK_SDP_R_IN_INSTR_BADDR(qno), 77 octep_read_csr64(oct, CNXK_SDP_R_IN_INSTR_BADDR(qno))); 78 dev_info(dev, "R[%d]_IN_INSTR_RSIZE[0x%llx]: 0x%016llx\n", 79 qno, CNXK_SDP_R_IN_INSTR_RSIZE(qno), 80 octep_read_csr64(oct, CNXK_SDP_R_IN_INSTR_RSIZE(qno))); 81 dev_info(dev, "R[%d]_IN_CNTS[0x%llx]: 0x%016llx\n", 82 qno, CNXK_SDP_R_IN_CNTS(qno), 83 octep_read_csr64(oct, CNXK_SDP_R_IN_CNTS(qno))); 84 dev_info(dev, "R[%d]_IN_INT_LEVELS[0x%llx]: 0x%016llx\n", 85 qno, CNXK_SDP_R_IN_INT_LEVELS(qno), 86 octep_read_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(qno))); 87 dev_info(dev, "R[%d]_IN_PKT_CNT[0x%llx]: 0x%016llx\n", 88 qno, CNXK_SDP_R_IN_PKT_CNT(qno), 89 octep_read_csr64(oct, CNXK_SDP_R_IN_PKT_CNT(qno))); 90 dev_info(dev, "R[%d]_IN_BYTE_CNT[0x%llx]: 0x%016llx\n", 91 qno, CNXK_SDP_R_IN_BYTE_CNT(qno), 92 octep_read_csr64(oct, CNXK_SDP_R_IN_BYTE_CNT(qno))); 93 94 dev_info(dev, "OQ-%d register dump\n", qno); 95 dev_info(dev, "R[%d]_OUT_SLIST_DBELL[0x%llx]: 0x%016llx\n", 96 qno, CNXK_SDP_R_OUT_SLIST_DBELL(qno), 97 octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_DBELL(qno))); 98 dev_info(dev, "R[%d]_OUT_CONTROL[0x%llx]: 0x%016llx\n", 99 qno, CNXK_SDP_R_OUT_CONTROL(qno), 100 octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(qno))); 101 dev_info(dev, "R[%d]_OUT_ENABLE[0x%llx]: 0x%016llx\n", 102 qno, CNXK_SDP_R_OUT_ENABLE(qno), 103 octep_read_csr64(oct, CNXK_SDP_R_OUT_ENABLE(qno))); 104 dev_info(dev, "R[%d]_OUT_SLIST_BADDR[0x%llx]: 0x%016llx\n", 105 qno, CNXK_SDP_R_OUT_SLIST_BADDR(qno), 106 octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(qno))); 107 dev_info(dev, "R[%d]_OUT_SLIST_RSIZE[0x%llx]: 0x%016llx\n", 108 qno, CNXK_SDP_R_OUT_SLIST_RSIZE(qno), 109 octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(qno))); 110 dev_info(dev, "R[%d]_OUT_CNTS[0x%llx]: 0x%016llx\n", 111 qno, CNXK_SDP_R_OUT_CNTS(qno), 112 octep_read_csr64(oct, CNXK_SDP_R_OUT_CNTS(qno))); 113 dev_info(dev, "R[%d]_OUT_INT_LEVELS[0x%llx]: 0x%016llx\n", 114 qno, CNXK_SDP_R_OUT_INT_LEVELS(qno), 115 octep_read_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(qno))); 116 dev_info(dev, "R[%d]_OUT_PKT_CNT[0x%llx]: 0x%016llx\n", 117 qno, CNXK_SDP_R_OUT_PKT_CNT(qno), 118 octep_read_csr64(oct, CNXK_SDP_R_OUT_PKT_CNT(qno))); 119 dev_info(dev, "R[%d]_OUT_BYTE_CNT[0x%llx]: 0x%016llx\n", 120 qno, CNXK_SDP_R_OUT_BYTE_CNT(qno), 121 octep_read_csr64(oct, CNXK_SDP_R_OUT_BYTE_CNT(qno))); 122 dev_info(dev, "R[%d]_ERR_TYPE[0x%llx]: 0x%016llx\n", 123 qno, CNXK_SDP_R_ERR_TYPE(qno), 124 octep_read_csr64(oct, CNXK_SDP_R_ERR_TYPE(qno))); 125} 126 127/* Reset Hardware Tx queue */ 128static int cnxk_reset_iq(struct octep_device *oct, int q_no) 129{ 130 struct octep_config *conf = oct->conf; 131 u64 val = 0ULL; 132 133 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no); 134 135 /* Get absolute queue number */ 136 q_no += conf->pf_ring_cfg.srn; 137 138 /* Disable the Tx/Instruction Ring */ 139 octep_write_csr64(oct, CNXK_SDP_R_IN_ENABLE(q_no), val); 140 141 /* clear the Instruction Ring packet/byte counts and doorbell CSRs */ 142 octep_write_csr64(oct, CNXK_SDP_R_IN_CNTS(q_no), val); 143 octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(q_no), val); 144 octep_write_csr64(oct, CNXK_SDP_R_IN_PKT_CNT(q_no), val); 145 octep_write_csr64(oct, CNXK_SDP_R_IN_BYTE_CNT(q_no), val); 146 octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_BADDR(q_no), val); 147 octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_RSIZE(q_no), val); 148 149 val = 0xFFFFFFFF; 150 octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_DBELL(q_no), val); 151 152 return 0; 153} 154 155/* Reset Hardware Rx queue */ 156static void cnxk_reset_oq(struct octep_device *oct, int q_no) 157{ 158 u64 val = 0ULL; 159 160 q_no += CFG_GET_PORTS_PF_SRN(oct->conf); 161 162 /* Disable Output (Rx) Ring */ 163 octep_write_csr64(oct, CNXK_SDP_R_OUT_ENABLE(q_no), val); 164 octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(q_no), val); 165 octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(q_no), val); 166 octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(q_no), val); 167 168 /* Clear count CSRs */ 169 val = octep_read_csr(oct, CNXK_SDP_R_OUT_CNTS(q_no)); 170 octep_write_csr(oct, CNXK_SDP_R_OUT_CNTS(q_no), val); 171 172 octep_write_csr64(oct, CNXK_SDP_R_OUT_PKT_CNT(q_no), 0xFFFFFFFFFULL); 173 octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_DBELL(q_no), 0xFFFFFFFF); 174} 175 176/* Reset all hardware Tx/Rx queues */ 177static void octep_reset_io_queues_cnxk_pf(struct octep_device *oct) 178{ 179 struct pci_dev *pdev = oct->pdev; 180 int q; 181 182 dev_dbg(&pdev->dev, "Reset OCTEP_CNXK PF IO Queues\n"); 183 184 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) { 185 cnxk_reset_iq(oct, q); 186 cnxk_reset_oq(oct, q); 187 } 188} 189 190/* Initialize windowed addresses to access some hardware registers */ 191static void octep_setup_pci_window_regs_cnxk_pf(struct octep_device *oct) 192{ 193 u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr; 194 195 oct->pci_win_regs.pci_win_wr_addr = (u8 __iomem *)(bar0_pciaddr + CNXK_SDP_WIN_WR_ADDR64); 196 oct->pci_win_regs.pci_win_rd_addr = (u8 __iomem *)(bar0_pciaddr + CNXK_SDP_WIN_RD_ADDR64); 197 oct->pci_win_regs.pci_win_wr_data = (u8 __iomem *)(bar0_pciaddr + CNXK_SDP_WIN_WR_DATA64); 198 oct->pci_win_regs.pci_win_rd_data = (u8 __iomem *)(bar0_pciaddr + CNXK_SDP_WIN_RD_DATA64); 199} 200 201/* Configure Hardware mapping: inform hardware which rings belong to PF. */ 202static void octep_configure_ring_mapping_cnxk_pf(struct octep_device *oct) 203{ 204 struct octep_config *conf = oct->conf; 205 struct pci_dev *pdev = oct->pdev; 206 u64 pf_srn = CFG_GET_PORTS_PF_SRN(oct->conf); 207 int q; 208 209 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(conf); q++) { 210 u64 regval = 0; 211 212 if (oct->pcie_port) 213 regval = 8 << CNXK_SDP_FUNC_SEL_EPF_BIT_POS; 214 215 octep_write_csr64(oct, CNXK_SDP_EPVF_RING(pf_srn + q), regval); 216 217 regval = octep_read_csr64(oct, CNXK_SDP_EPVF_RING(pf_srn + q)); 218 dev_dbg(&pdev->dev, "Write SDP_EPVF_RING[0x%llx] = 0x%llx\n", 219 CNXK_SDP_EPVF_RING(pf_srn + q), regval); 220 } 221} 222 223/* Initialize configuration limits and initial active config */ 224static void octep_init_config_cnxk_pf(struct octep_device *oct) 225{ 226 struct octep_config *conf = oct->conf; 227 struct pci_dev *pdev = oct->pdev; 228 u8 link = 0; 229 u64 val; 230 int pos; 231 232 /* Read ring configuration: 233 * PF ring count, number of VFs and rings per VF supported 234 */ 235 val = octep_read_csr64(oct, CNXK_SDP_EPF_RINFO); 236 dev_info(&pdev->dev, "SDP_EPF_RINFO[0x%x]:0x%llx\n", CNXK_SDP_EPF_RINFO, val); 237 conf->sriov_cfg.max_rings_per_vf = CNXK_SDP_EPF_RINFO_RPVF(val); 238 conf->sriov_cfg.active_rings_per_vf = conf->sriov_cfg.max_rings_per_vf; 239 conf->sriov_cfg.max_vfs = CNXK_SDP_EPF_RINFO_NVFS(val); 240 conf->sriov_cfg.active_vfs = conf->sriov_cfg.max_vfs; 241 conf->sriov_cfg.vf_srn = CNXK_SDP_EPF_RINFO_SRN(val); 242 243 val = octep_read_csr64(oct, CNXK_SDP_MAC_PF_RING_CTL(oct->pcie_port)); 244 dev_info(&pdev->dev, "SDP_MAC_PF_RING_CTL[%d]:0x%llx\n", oct->pcie_port, val); 245 conf->pf_ring_cfg.srn = CNXK_SDP_MAC_PF_RING_CTL_SRN(val); 246 conf->pf_ring_cfg.max_io_rings = CNXK_SDP_MAC_PF_RING_CTL_RPPF(val); 247 conf->pf_ring_cfg.active_io_rings = conf->pf_ring_cfg.max_io_rings; 248 dev_info(&pdev->dev, "pf_srn=%u rpvf=%u nvfs=%u rppf=%u\n", 249 conf->pf_ring_cfg.srn, conf->sriov_cfg.active_rings_per_vf, 250 conf->sriov_cfg.active_vfs, conf->pf_ring_cfg.active_io_rings); 251 252 conf->iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS; 253 conf->iq.instr_type = OCTEP_64BYTE_INSTR; 254 conf->iq.db_min = OCTEP_DB_MIN; 255 conf->iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD; 256 257 conf->oq.num_descs = OCTEP_OQ_MAX_DESCRIPTORS; 258 conf->oq.buf_size = OCTEP_OQ_BUF_SIZE; 259 conf->oq.refill_threshold = OCTEP_OQ_REFILL_THRESHOLD; 260 conf->oq.oq_intr_pkt = OCTEP_OQ_INTR_PKT_THRESHOLD; 261 conf->oq.oq_intr_time = OCTEP_OQ_INTR_TIME_THRESHOLD; 262 conf->oq.wmark = OCTEP_OQ_WMARK_MIN; 263 264 conf->msix_cfg.non_ioq_msix = CNXK_NUM_NON_IOQ_INTR; 265 conf->msix_cfg.ioq_msix = conf->pf_ring_cfg.active_io_rings; 266 conf->msix_cfg.non_ioq_msix_names = cnxk_non_ioq_msix_names; 267 268 pos = pci_find_ext_capability(oct->pdev, PCI_EXT_CAP_ID_SRIOV); 269 if (pos) { 270 pci_read_config_byte(oct->pdev, 271 pos + PCI_SRIOV_FUNC_LINK, 272 &link); 273 link = PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link); 274 } 275 conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr + 276 CNXK_PEM_BAR4_INDEX_OFFSET + 277 (link * CTRL_MBOX_SZ); 278 279 conf->fw_info.hb_interval = OCTEP_DEFAULT_FW_HB_INTERVAL; 280 conf->fw_info.hb_miss_count = OCTEP_DEFAULT_FW_HB_MISS_COUNT; 281} 282 283/* Setup registers for a hardware Tx Queue */ 284static void octep_setup_iq_regs_cnxk_pf(struct octep_device *oct, int iq_no) 285{ 286 struct octep_iq *iq = oct->iq[iq_no]; 287 u32 reset_instr_cnt; 288 u64 reg_val; 289 290 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 291 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no)); 292 293 /* wait for IDLE to set to 1 */ 294 if (!(reg_val & CNXK_R_IN_CTL_IDLE)) { 295 do { 296 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no)); 297 } while (!(reg_val & CNXK_R_IN_CTL_IDLE)); 298 } 299 300 reg_val |= CNXK_R_IN_CTL_RDSIZE; 301 reg_val |= CNXK_R_IN_CTL_IS_64B; 302 reg_val |= CNXK_R_IN_CTL_ESR; 303 octep_write_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no), reg_val); 304 305 /* Write the start of the input queue's ring and its size */ 306 octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_BADDR(iq_no), 307 iq->desc_ring_dma); 308 octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_RSIZE(iq_no), 309 iq->max_count); 310 311 /* Remember the doorbell & instruction count register addr 312 * for this queue 313 */ 314 iq->doorbell_reg = oct->mmio[0].hw_addr + 315 CNXK_SDP_R_IN_INSTR_DBELL(iq_no); 316 iq->inst_cnt_reg = oct->mmio[0].hw_addr + 317 CNXK_SDP_R_IN_CNTS(iq_no); 318 iq->intr_lvl_reg = oct->mmio[0].hw_addr + 319 CNXK_SDP_R_IN_INT_LEVELS(iq_no); 320 321 /* Store the current instruction counter (used in flush_iq calculation) */ 322 reset_instr_cnt = readl(iq->inst_cnt_reg); 323 writel(reset_instr_cnt, iq->inst_cnt_reg); 324 325 /* INTR_THRESHOLD is set to max(FFFFFFFF) to disable the INTR */ 326 reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff; 327 octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(iq_no), reg_val); 328} 329 330/* Setup registers for a hardware Rx Queue */ 331static int octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no) 332{ 333 struct octep_oq *oq = oct->oq[oq_no]; 334 unsigned long t_out_jiffies; 335 u32 time_threshold = 0; 336 u64 oq_ctl = 0ULL; 337 u64 reg_ba_val; 338 u64 reg_val; 339 340 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 341 reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); 342 343 /* wait for IDLE to set to 1 */ 344 if (!(reg_val & CNXK_R_OUT_CTL_IDLE)) { 345 do { 346 reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); 347 } while (!(reg_val & CNXK_R_OUT_CTL_IDLE)); 348 } 349 octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), oq->max_count); 350 /* Wait for WMARK to get applied */ 351 usleep_range(10, 15); 352 353 octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), 354 oq->desc_ring_dma); 355 octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), 356 oq->max_count); 357 reg_ba_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); 358 359 if (reg_ba_val != oq->desc_ring_dma) { 360 t_out_jiffies = jiffies + 10 * HZ; 361 do { 362 if (reg_ba_val == ULLONG_MAX) 363 return -EFAULT; 364 octep_write_csr64(oct, 365 CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), 366 oq->desc_ring_dma); 367 octep_write_csr64(oct, 368 CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), 369 oq->max_count); 370 reg_ba_val = 371 octep_read_csr64(oct, 372 CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); 373 } while ((reg_ba_val != oq->desc_ring_dma) && 374 time_before(jiffies, t_out_jiffies)); 375 376 if (reg_ba_val != oq->desc_ring_dma) 377 return -EAGAIN; 378 } 379 380 reg_val &= ~(CNXK_R_OUT_CTL_IMODE); 381 reg_val &= ~(CNXK_R_OUT_CTL_ROR_P); 382 reg_val &= ~(CNXK_R_OUT_CTL_NSR_P); 383 reg_val &= ~(CNXK_R_OUT_CTL_ROR_I); 384 reg_val &= ~(CNXK_R_OUT_CTL_NSR_I); 385 reg_val &= ~(CNXK_R_OUT_CTL_ES_I); 386 reg_val &= ~(CNXK_R_OUT_CTL_ROR_D); 387 reg_val &= ~(CNXK_R_OUT_CTL_NSR_D); 388 reg_val &= ~(CNXK_R_OUT_CTL_ES_D); 389 reg_val |= (CNXK_R_OUT_CTL_ES_P); 390 391 octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), reg_val); 392 393 oq_ctl = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); 394 395 /* Clear the ISIZE and BSIZE (22-0) */ 396 oq_ctl &= ~0x7fffffULL; 397 398 /* Populate the BSIZE (15-0) */ 399 oq_ctl |= (oq->buffer_size & 0xffff); 400 octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), oq_ctl); 401 402 /* Get the mapped address of the pkt_sent and pkts_credit regs */ 403 oq->pkts_sent_reg = oct->mmio[0].hw_addr + CNXK_SDP_R_OUT_CNTS(oq_no); 404 oq->pkts_credit_reg = oct->mmio[0].hw_addr + 405 CNXK_SDP_R_OUT_SLIST_DBELL(oq_no); 406 407 time_threshold = CFG_GET_OQ_INTR_TIME(oct->conf); 408 reg_val = ((u64)time_threshold << 32) | 409 CFG_GET_OQ_INTR_PKT(oct->conf); 410 octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); 411 412 /* set watermark for backpressure */ 413 reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no)); 414 reg_val &= ~0xFFFFFFFFULL; 415 reg_val |= CFG_GET_OQ_WMARK(oct->conf); 416 octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), reg_val); 417 return 0; 418} 419 420/* Setup registers for a PF mailbox */ 421static void octep_setup_mbox_regs_cnxk_pf(struct octep_device *oct, int q_no) 422{ 423 struct octep_mbox *mbox = oct->mbox[q_no]; 424 425 /* PF to VF DATA reg. PF writes into this reg */ 426 mbox->pf_vf_data_reg = oct->mmio[0].hw_addr + CNXK_SDP_MBOX_PF_VF_DATA(q_no); 427 428 /* VF to PF DATA reg. PF reads from this reg */ 429 mbox->vf_pf_data_reg = oct->mmio[0].hw_addr + CNXK_SDP_MBOX_VF_PF_DATA(q_no); 430} 431 432static void octep_poll_pfvf_mailbox_cnxk_pf(struct octep_device *oct) 433{ 434 u32 vf, active_vfs, active_rings_per_vf, vf_mbox_queue; 435 u64 reg0; 436 437 reg0 = octep_read_csr64(oct, CNXK_SDP_EPF_MBOX_RINT(0)); 438 if (reg0) { 439 active_vfs = CFG_GET_ACTIVE_VFS(oct->conf); 440 active_rings_per_vf = CFG_GET_ACTIVE_RPVF(oct->conf); 441 for (vf = 0; vf < active_vfs; vf++) { 442 vf_mbox_queue = vf * active_rings_per_vf; 443 if (!(reg0 & (0x1UL << vf_mbox_queue))) 444 continue; 445 446 if (!oct->mbox[vf_mbox_queue]) { 447 dev_err(&oct->pdev->dev, "bad mbox vf %d\n", vf); 448 continue; 449 } 450 schedule_work(&oct->mbox[vf_mbox_queue]->wk.work); 451 } 452 if (reg0) 453 octep_write_csr64(oct, CNXK_SDP_EPF_MBOX_RINT(0), reg0); 454 } 455} 456 457static irqreturn_t octep_pfvf_mbox_intr_handler_cnxk_pf(void *dev) 458{ 459 struct octep_device *oct = (struct octep_device *)dev; 460 461 octep_poll_pfvf_mailbox_cnxk_pf(oct); 462 return IRQ_HANDLED; 463} 464 465/* Poll OEI events like heartbeat */ 466static void octep_poll_oei_cnxk_pf(struct octep_device *oct) 467{ 468 u64 reg0; 469 470 /* Check for OEI INTR */ 471 reg0 = octep_read_csr64(oct, CNXK_SDP_EPF_OEI_RINT); 472 if (reg0) { 473 octep_write_csr64(oct, CNXK_SDP_EPF_OEI_RINT, reg0); 474 if (reg0 & CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX) 475 queue_work(octep_wq, &oct->ctrl_mbox_task); 476 if (reg0 & CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT) 477 atomic_set(&oct->hb_miss_cnt, 0); 478 } 479} 480 481/* OEI interrupt handler */ 482static irqreturn_t octep_oei_intr_handler_cnxk_pf(void *dev) 483{ 484 struct octep_device *oct = (struct octep_device *)dev; 485 486 octep_poll_oei_cnxk_pf(oct); 487 return IRQ_HANDLED; 488} 489 490/* Process non-ioq interrupts required to keep pf interface running. 491 * OEI_RINT is needed for control mailbox 492 * MBOX_RINT is needed for pfvf mailbox 493 */ 494static void octep_poll_non_ioq_interrupts_cnxk_pf(struct octep_device *oct) 495{ 496 octep_poll_pfvf_mailbox_cnxk_pf(oct); 497 octep_poll_oei_cnxk_pf(oct); 498} 499 500/* Interrupt handler for input ring error interrupts. */ 501static irqreturn_t octep_ire_intr_handler_cnxk_pf(void *dev) 502{ 503 struct octep_device *oct = (struct octep_device *)dev; 504 struct pci_dev *pdev = oct->pdev; 505 u64 reg_val = 0; 506 int i = 0; 507 508 /* Check for IRERR INTR */ 509 reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_IRERR_RINT); 510 if (reg_val) { 511 dev_info(&pdev->dev, 512 "received IRERR_RINT intr: 0x%llx\n", reg_val); 513 octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT, reg_val); 514 515 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) { 516 reg_val = octep_read_csr64(oct, 517 CNXK_SDP_R_ERR_TYPE(i)); 518 if (reg_val) { 519 dev_info(&pdev->dev, 520 "Received err type on IQ-%d: 0x%llx\n", 521 i, reg_val); 522 octep_write_csr64(oct, CNXK_SDP_R_ERR_TYPE(i), 523 reg_val); 524 } 525 } 526 } 527 return IRQ_HANDLED; 528} 529 530/* Interrupt handler for output ring error interrupts. */ 531static irqreturn_t octep_ore_intr_handler_cnxk_pf(void *dev) 532{ 533 struct octep_device *oct = (struct octep_device *)dev; 534 struct pci_dev *pdev = oct->pdev; 535 u64 reg_val = 0; 536 int i = 0; 537 538 /* Check for ORERR INTR */ 539 reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_ORERR_RINT); 540 if (reg_val) { 541 dev_info(&pdev->dev, 542 "Received ORERR_RINT intr: 0x%llx\n", reg_val); 543 octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT, reg_val); 544 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) { 545 reg_val = octep_read_csr64(oct, CNXK_SDP_R_ERR_TYPE(i)); 546 if (reg_val) { 547 dev_info(&pdev->dev, 548 "Received err type on OQ-%d: 0x%llx\n", 549 i, reg_val); 550 octep_write_csr64(oct, CNXK_SDP_R_ERR_TYPE(i), 551 reg_val); 552 } 553 } 554 } 555 return IRQ_HANDLED; 556} 557 558/* Interrupt handler for vf input ring error interrupts. */ 559static irqreturn_t octep_vfire_intr_handler_cnxk_pf(void *dev) 560{ 561 struct octep_device *oct = (struct octep_device *)dev; 562 struct pci_dev *pdev = oct->pdev; 563 u64 reg_val = 0; 564 565 /* Check for VFIRE INTR */ 566 reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT(0)); 567 if (reg_val) { 568 dev_info(&pdev->dev, 569 "Received VFIRE_RINT intr: 0x%llx\n", reg_val); 570 octep_write_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT(0), reg_val); 571 } 572 return IRQ_HANDLED; 573} 574 575/* Interrupt handler for vf output ring error interrupts. */ 576static irqreturn_t octep_vfore_intr_handler_cnxk_pf(void *dev) 577{ 578 struct octep_device *oct = (struct octep_device *)dev; 579 struct pci_dev *pdev = oct->pdev; 580 u64 reg_val = 0; 581 582 /* Check for VFORE INTR */ 583 reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_VFORE_RINT(0)); 584 if (reg_val) { 585 dev_info(&pdev->dev, 586 "Received VFORE_RINT intr: 0x%llx\n", reg_val); 587 octep_write_csr64(oct, CNXK_SDP_EPF_VFORE_RINT(0), reg_val); 588 } 589 return IRQ_HANDLED; 590} 591 592/* Interrupt handler for dpi dma related interrupts. */ 593static irqreturn_t octep_dma_intr_handler_cnxk_pf(void *dev) 594{ 595 struct octep_device *oct = (struct octep_device *)dev; 596 u64 reg_val = 0; 597 598 /* Check for DMA INTR */ 599 reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_DMA_RINT); 600 if (reg_val) 601 octep_write_csr64(oct, CNXK_SDP_EPF_DMA_RINT, reg_val); 602 603 return IRQ_HANDLED; 604} 605 606/* Interrupt handler for dpi dma transaction error interrupts for VFs */ 607static irqreturn_t octep_dma_vf_intr_handler_cnxk_pf(void *dev) 608{ 609 struct octep_device *oct = (struct octep_device *)dev; 610 struct pci_dev *pdev = oct->pdev; 611 u64 reg_val = 0; 612 613 /* Check for DMA VF INTR */ 614 reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT(0)); 615 if (reg_val) { 616 dev_info(&pdev->dev, 617 "Received DMA_VF_RINT intr: 0x%llx\n", reg_val); 618 octep_write_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT(0), reg_val); 619 } 620 return IRQ_HANDLED; 621} 622 623/* Interrupt handler for pp transaction error interrupts for VFs */ 624static irqreturn_t octep_pp_vf_intr_handler_cnxk_pf(void *dev) 625{ 626 struct octep_device *oct = (struct octep_device *)dev; 627 struct pci_dev *pdev = oct->pdev; 628 u64 reg_val = 0; 629 630 /* Check for PPVF INTR */ 631 reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT(0)); 632 if (reg_val) { 633 dev_info(&pdev->dev, 634 "Received PP_VF_RINT intr: 0x%llx\n", reg_val); 635 octep_write_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT(0), reg_val); 636 } 637 return IRQ_HANDLED; 638} 639 640/* Interrupt handler for mac related interrupts. */ 641static irqreturn_t octep_misc_intr_handler_cnxk_pf(void *dev) 642{ 643 struct octep_device *oct = (struct octep_device *)dev; 644 struct pci_dev *pdev = oct->pdev; 645 u64 reg_val = 0; 646 647 /* Check for MISC INTR */ 648 reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_MISC_RINT); 649 if (reg_val) { 650 dev_info(&pdev->dev, 651 "Received MISC_RINT intr: 0x%llx\n", reg_val); 652 octep_write_csr64(oct, CNXK_SDP_EPF_MISC_RINT, reg_val); 653 } 654 return IRQ_HANDLED; 655} 656 657/* Interrupts handler for all reserved interrupts. */ 658static irqreturn_t octep_rsvd_intr_handler_cnxk_pf(void *dev) 659{ 660 struct octep_device *oct = (struct octep_device *)dev; 661 struct pci_dev *pdev = oct->pdev; 662 663 dev_info(&pdev->dev, "Reserved interrupts raised; Ignore\n"); 664 return IRQ_HANDLED; 665} 666 667/* Tx/Rx queue interrupt handler */ 668static irqreturn_t octep_ioq_intr_handler_cnxk_pf(void *data) 669{ 670 struct octep_ioq_vector *vector = (struct octep_ioq_vector *)data; 671 struct octep_oq *oq = vector->oq; 672 673 napi_schedule_irqoff(oq->napi); 674 return IRQ_HANDLED; 675} 676 677/* soft reset */ 678static int octep_soft_reset_cnxk_pf(struct octep_device *oct) 679{ 680 dev_info(&oct->pdev->dev, "CNXKXX: Doing soft reset\n"); 681 682 octep_write_csr64(oct, CNXK_SDP_WIN_WR_MASK_REG, 0xFF); 683 684 /* Firmware status CSR is supposed to be cleared by 685 * core domain reset, but due to a hw bug, it is not. 686 * Set it to RUNNING right before reset so that it is not 687 * left in READY (1) state after a reset. This is required 688 * in addition to the early setting to handle the case where 689 * the OcteonTX is unexpectedly reset, reboots, and then 690 * the module is removed. 691 */ 692 OCTEP_PCI_WIN_WRITE(oct, CNXK_PEMX_PFX_CSX_PFCFGX(0, 0, CNXK_PCIEEP_VSECST_CTL), 693 FW_STATUS_RUNNING); 694 695 /* Set chip domain reset bit */ 696 OCTEP_PCI_WIN_WRITE(oct, CNXK_RST_CHIP_DOMAIN_W1S, 1); 697 /* Wait till Octeon resets. */ 698 mdelay(10); 699 /* restore the reset value */ 700 octep_write_csr64(oct, CNXK_SDP_WIN_WR_MASK_REG, 0xFF); 701 702 return 0; 703} 704 705/* Re-initialize Octeon hardware registers */ 706static void octep_reinit_regs_cnxk_pf(struct octep_device *oct) 707{ 708 u32 i; 709 710 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) 711 oct->hw_ops.setup_iq_regs(oct, i); 712 713 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) 714 oct->hw_ops.setup_oq_regs(oct, i); 715 716 oct->hw_ops.enable_interrupts(oct); 717 oct->hw_ops.enable_io_queues(oct); 718 719 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) 720 writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg); 721} 722 723/* Enable all interrupts */ 724static void octep_enable_interrupts_cnxk_pf(struct octep_device *oct) 725{ 726 u64 intr_mask = 0ULL; 727 int srn, num_rings, i; 728 729 srn = CFG_GET_PORTS_PF_SRN(oct->conf); 730 num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); 731 732 for (i = 0; i < num_rings; i++) 733 intr_mask |= (0x1ULL << (srn + i)); 734 735 octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1S, intr_mask); 736 octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1S, intr_mask); 737 octep_write_csr64(oct, CNXK_SDP_EPF_OEI_RINT_ENA_W1S, -1ULL); 738 739 octep_write_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S(0), -1ULL); 740 octep_write_csr64(oct, CNXK_SDP_EPF_VFORE_RINT_ENA_W1S(0), -1ULL); 741 742 octep_write_csr64(oct, CNXK_SDP_EPF_MISC_RINT_ENA_W1S, intr_mask); 743 octep_write_csr64(oct, CNXK_SDP_EPF_DMA_RINT_ENA_W1S, intr_mask); 744 octep_write_csr64(oct, CNXK_SDP_EPF_MBOX_RINT_ENA_W1S(0), -1ULL); 745 746 octep_write_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S(0), -1ULL); 747 octep_write_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S(0), -1ULL); 748} 749 750/* Disable all interrupts */ 751static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct) 752{ 753 u64 reg_val, intr_mask = 0ULL; 754 int srn, num_rings, i; 755 756 srn = CFG_GET_PORTS_PF_SRN(oct->conf); 757 num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); 758 759 for (i = 0; i < num_rings; i++) { 760 intr_mask |= BIT_ULL(srn + i); 761 reg_val = octep_read_csr64(oct, 762 CNXK_SDP_R_IN_INT_LEVELS(srn + i)); 763 reg_val &= ~CNXK_INT_ENA_BIT; 764 octep_write_csr64(oct, 765 CNXK_SDP_R_IN_INT_LEVELS(srn + i), reg_val); 766 767 reg_val = octep_read_csr64(oct, 768 CNXK_SDP_R_OUT_INT_LEVELS(srn + i)); 769 reg_val &= ~CNXK_INT_ENA_BIT; 770 octep_write_csr64(oct, 771 CNXK_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); 772 } 773 774 octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); 775 octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); 776 octep_write_csr64(oct, CNXK_SDP_EPF_OEI_RINT_ENA_W1C, -1ULL); 777 778 octep_write_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C(0), -1ULL); 779 octep_write_csr64(oct, CNXK_SDP_EPF_VFORE_RINT_ENA_W1C(0), -1ULL); 780 781 octep_write_csr64(oct, CNXK_SDP_EPF_MISC_RINT_ENA_W1C, intr_mask); 782 octep_write_csr64(oct, CNXK_SDP_EPF_DMA_RINT_ENA_W1C, intr_mask); 783 octep_write_csr64(oct, CNXK_SDP_EPF_MBOX_RINT_ENA_W1C(0), -1ULL); 784 785 octep_write_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C(0), -1ULL); 786 octep_write_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C(0), -1ULL); 787} 788 789/* Get new Octeon Read Index: index of descriptor that Octeon reads next. */ 790static u32 octep_update_iq_read_index_cnxk_pf(struct octep_iq *iq) 791{ 792 u32 pkt_in_done = readl(iq->inst_cnt_reg); 793 u32 last_done, new_idx; 794 795 last_done = pkt_in_done - iq->pkt_in_done; 796 iq->pkt_in_done = pkt_in_done; 797 798 new_idx = (iq->octep_read_index + last_done) % iq->max_count; 799 800 return new_idx; 801} 802 803/* Enable a hardware Tx Queue */ 804static void octep_enable_iq_cnxk_pf(struct octep_device *oct, int iq_no) 805{ 806 u64 loop = HZ; 807 u64 reg_val; 808 809 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 810 811 octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_DBELL(iq_no), 0xFFFFFFFF); 812 813 while (octep_read_csr64(oct, CNXK_SDP_R_IN_INSTR_DBELL(iq_no)) && 814 loop--) { 815 schedule_timeout_interruptible(1); 816 } 817 818 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(iq_no)); 819 reg_val |= (0x1ULL << 62); 820 octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(iq_no), reg_val); 821 822 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no)); 823 reg_val |= 0x1ULL; 824 octep_write_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no), reg_val); 825} 826 827/* Enable a hardware Rx Queue */ 828static void octep_enable_oq_cnxk_pf(struct octep_device *oct, int oq_no) 829{ 830 u64 reg_val = 0ULL; 831 832 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 833 834 reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(oq_no)); 835 reg_val |= (0x1ULL << 62); 836 octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); 837 838 octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_DBELL(oq_no), 0xFFFFFFFF); 839 840 reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no)); 841 reg_val |= 0x1ULL; 842 octep_write_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no), reg_val); 843} 844 845/* Enable all hardware Tx/Rx Queues assined to PF */ 846static void octep_enable_io_queues_cnxk_pf(struct octep_device *oct) 847{ 848 u8 q; 849 850 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) { 851 octep_enable_iq_cnxk_pf(oct, q); 852 octep_enable_oq_cnxk_pf(oct, q); 853 } 854} 855 856/* Disable a hardware Tx Queue assined to PF */ 857static void octep_disable_iq_cnxk_pf(struct octep_device *oct, int iq_no) 858{ 859 u64 reg_val = 0ULL; 860 861 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 862 863 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no)); 864 reg_val &= ~0x1ULL; 865 octep_write_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no), reg_val); 866} 867 868/* Disable a hardware Rx Queue assined to PF */ 869static void octep_disable_oq_cnxk_pf(struct octep_device *oct, int oq_no) 870{ 871 u64 reg_val = 0ULL; 872 873 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 874 reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no)); 875 reg_val &= ~0x1ULL; 876 octep_write_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no), reg_val); 877} 878 879/* Disable all hardware Tx/Rx Queues assined to PF */ 880static void octep_disable_io_queues_cnxk_pf(struct octep_device *oct) 881{ 882 int q = 0; 883 884 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) { 885 octep_disable_iq_cnxk_pf(oct, q); 886 octep_disable_oq_cnxk_pf(oct, q); 887 } 888} 889 890/* Dump hardware registers (including Tx/Rx queues) for debugging. */ 891static void octep_dump_registers_cnxk_pf(struct octep_device *oct) 892{ 893 u8 srn, num_rings, q; 894 895 srn = CFG_GET_PORTS_PF_SRN(oct->conf); 896 num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); 897 898 for (q = srn; q < srn + num_rings; q++) 899 cnxk_dump_regs(oct, q); 900} 901 902/** 903 * octep_device_setup_cnxk_pf() - Setup Octeon device. 904 * 905 * @oct: Octeon device private data structure. 906 * 907 * - initialize hardware operations. 908 * - get target side pcie port number for the device. 909 * - setup window access to hardware registers. 910 * - set initial configuration and max limits. 911 * - setup hardware mapping of rings to the PF device. 912 */ 913void octep_device_setup_cnxk_pf(struct octep_device *oct) 914{ 915 oct->hw_ops.setup_iq_regs = octep_setup_iq_regs_cnxk_pf; 916 oct->hw_ops.setup_oq_regs = octep_setup_oq_regs_cnxk_pf; 917 oct->hw_ops.setup_mbox_regs = octep_setup_mbox_regs_cnxk_pf; 918 919 oct->hw_ops.mbox_intr_handler = octep_pfvf_mbox_intr_handler_cnxk_pf; 920 oct->hw_ops.oei_intr_handler = octep_oei_intr_handler_cnxk_pf; 921 oct->hw_ops.ire_intr_handler = octep_ire_intr_handler_cnxk_pf; 922 oct->hw_ops.ore_intr_handler = octep_ore_intr_handler_cnxk_pf; 923 oct->hw_ops.vfire_intr_handler = octep_vfire_intr_handler_cnxk_pf; 924 oct->hw_ops.vfore_intr_handler = octep_vfore_intr_handler_cnxk_pf; 925 oct->hw_ops.dma_intr_handler = octep_dma_intr_handler_cnxk_pf; 926 oct->hw_ops.dma_vf_intr_handler = octep_dma_vf_intr_handler_cnxk_pf; 927 oct->hw_ops.pp_vf_intr_handler = octep_pp_vf_intr_handler_cnxk_pf; 928 oct->hw_ops.misc_intr_handler = octep_misc_intr_handler_cnxk_pf; 929 oct->hw_ops.rsvd_intr_handler = octep_rsvd_intr_handler_cnxk_pf; 930 oct->hw_ops.ioq_intr_handler = octep_ioq_intr_handler_cnxk_pf; 931 oct->hw_ops.soft_reset = octep_soft_reset_cnxk_pf; 932 oct->hw_ops.reinit_regs = octep_reinit_regs_cnxk_pf; 933 934 oct->hw_ops.enable_interrupts = octep_enable_interrupts_cnxk_pf; 935 oct->hw_ops.disable_interrupts = octep_disable_interrupts_cnxk_pf; 936 oct->hw_ops.poll_non_ioq_interrupts = octep_poll_non_ioq_interrupts_cnxk_pf; 937 938 oct->hw_ops.update_iq_read_idx = octep_update_iq_read_index_cnxk_pf; 939 940 oct->hw_ops.enable_iq = octep_enable_iq_cnxk_pf; 941 oct->hw_ops.enable_oq = octep_enable_oq_cnxk_pf; 942 oct->hw_ops.enable_io_queues = octep_enable_io_queues_cnxk_pf; 943 944 oct->hw_ops.disable_iq = octep_disable_iq_cnxk_pf; 945 oct->hw_ops.disable_oq = octep_disable_oq_cnxk_pf; 946 oct->hw_ops.disable_io_queues = octep_disable_io_queues_cnxk_pf; 947 oct->hw_ops.reset_io_queues = octep_reset_io_queues_cnxk_pf; 948 949 oct->hw_ops.dump_registers = octep_dump_registers_cnxk_pf; 950 951 octep_setup_pci_window_regs_cnxk_pf(oct); 952 953 oct->pcie_port = octep_read_csr64(oct, CNXK_SDP_MAC_NUMBER) & 0xff; 954 dev_info(&oct->pdev->dev, 955 "Octeon device using PCIE Port %d\n", oct->pcie_port); 956 957 octep_init_config_cnxk_pf(oct); 958 octep_configure_ring_mapping_cnxk_pf(oct); 959 960 /* Firmware status CSR is supposed to be cleared by 961 * core domain reset, but due to IPBUPEM-38842, it is not. 962 * Set it to RUNNING early in boot, so that unexpected resets 963 * leave it in a state that is not READY (1). 964 */ 965 OCTEP_PCI_WIN_WRITE(oct, CNXK_PEMX_PFX_CSX_PFCFGX(0, 0, CNXK_PCIEEP_VSECST_CTL), 966 FW_STATUS_RUNNING); 967}
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