FILE
octep_cn9k_pf.c
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linux-6.19.14/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
1// SPDX-License-Identifier: GPL-2.0 2/* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8#include <linux/pci.h> 9#include <linux/netdevice.h> 10#include <linux/etherdevice.h> 11 12#include "octep_config.h" 13#include "octep_main.h" 14#include "octep_regs_cn9k_pf.h" 15 16#define CTRL_MBOX_MAX_PF 128 17#define CTRL_MBOX_SZ ((size_t)(0x400000 / CTRL_MBOX_MAX_PF)) 18 19/* Names of Hardware non-queue generic interrupts */ 20static char *cn93_non_ioq_msix_names[] = { 21 "epf_ire_rint", 22 "epf_ore_rint", 23 "epf_vfire_rint0", 24 "epf_vfire_rint1", 25 "epf_vfore_rint0", 26 "epf_vfore_rint1", 27 "epf_mbox_rint0", 28 "epf_mbox_rint1", 29 "epf_oei_rint", 30 "epf_dma_rint", 31 "epf_dma_vf_rint0", 32 "epf_dma_vf_rint1", 33 "epf_pp_vf_rint0", 34 "epf_pp_vf_rint1", 35 "epf_misc_rint", 36 "epf_rsvd", 37}; 38 39/* Dump useful hardware CSRs for debug purpose */ 40static void cn93_dump_regs(struct octep_device *oct, int qno) 41{ 42 struct device *dev = &oct->pdev->dev; 43 44 dev_info(dev, "IQ-%d register dump\n", qno); 45 dev_info(dev, "R[%d]_IN_INSTR_DBELL[0x%llx]: 0x%016llx\n", 46 qno, CN93_SDP_R_IN_INSTR_DBELL(qno), 47 octep_read_csr64(oct, CN93_SDP_R_IN_INSTR_DBELL(qno))); 48 dev_info(dev, "R[%d]_IN_CONTROL[0x%llx]: 0x%016llx\n", 49 qno, CN93_SDP_R_IN_CONTROL(qno), 50 octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(qno))); 51 dev_info(dev, "R[%d]_IN_ENABLE[0x%llx]: 0x%016llx\n", 52 qno, CN93_SDP_R_IN_ENABLE(qno), 53 octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(qno))); 54 dev_info(dev, "R[%d]_IN_INSTR_BADDR[0x%llx]: 0x%016llx\n", 55 qno, CN93_SDP_R_IN_INSTR_BADDR(qno), 56 octep_read_csr64(oct, CN93_SDP_R_IN_INSTR_BADDR(qno))); 57 dev_info(dev, "R[%d]_IN_INSTR_RSIZE[0x%llx]: 0x%016llx\n", 58 qno, CN93_SDP_R_IN_INSTR_RSIZE(qno), 59 octep_read_csr64(oct, CN93_SDP_R_IN_INSTR_RSIZE(qno))); 60 dev_info(dev, "R[%d]_IN_CNTS[0x%llx]: 0x%016llx\n", 61 qno, CN93_SDP_R_IN_CNTS(qno), 62 octep_read_csr64(oct, CN93_SDP_R_IN_CNTS(qno))); 63 dev_info(dev, "R[%d]_IN_INT_LEVELS[0x%llx]: 0x%016llx\n", 64 qno, CN93_SDP_R_IN_INT_LEVELS(qno), 65 octep_read_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(qno))); 66 dev_info(dev, "R[%d]_IN_PKT_CNT[0x%llx]: 0x%016llx\n", 67 qno, CN93_SDP_R_IN_PKT_CNT(qno), 68 octep_read_csr64(oct, CN93_SDP_R_IN_PKT_CNT(qno))); 69 dev_info(dev, "R[%d]_IN_BYTE_CNT[0x%llx]: 0x%016llx\n", 70 qno, CN93_SDP_R_IN_BYTE_CNT(qno), 71 octep_read_csr64(oct, CN93_SDP_R_IN_BYTE_CNT(qno))); 72 73 dev_info(dev, "OQ-%d register dump\n", qno); 74 dev_info(dev, "R[%d]_OUT_SLIST_DBELL[0x%llx]: 0x%016llx\n", 75 qno, CN93_SDP_R_OUT_SLIST_DBELL(qno), 76 octep_read_csr64(oct, CN93_SDP_R_OUT_SLIST_DBELL(qno))); 77 dev_info(dev, "R[%d]_OUT_CONTROL[0x%llx]: 0x%016llx\n", 78 qno, CN93_SDP_R_OUT_CONTROL(qno), 79 octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(qno))); 80 dev_info(dev, "R[%d]_OUT_ENABLE[0x%llx]: 0x%016llx\n", 81 qno, CN93_SDP_R_OUT_ENABLE(qno), 82 octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(qno))); 83 dev_info(dev, "R[%d]_OUT_SLIST_BADDR[0x%llx]: 0x%016llx\n", 84 qno, CN93_SDP_R_OUT_SLIST_BADDR(qno), 85 octep_read_csr64(oct, CN93_SDP_R_OUT_SLIST_BADDR(qno))); 86 dev_info(dev, "R[%d]_OUT_SLIST_RSIZE[0x%llx]: 0x%016llx\n", 87 qno, CN93_SDP_R_OUT_SLIST_RSIZE(qno), 88 octep_read_csr64(oct, CN93_SDP_R_OUT_SLIST_RSIZE(qno))); 89 dev_info(dev, "R[%d]_OUT_CNTS[0x%llx]: 0x%016llx\n", 90 qno, CN93_SDP_R_OUT_CNTS(qno), 91 octep_read_csr64(oct, CN93_SDP_R_OUT_CNTS(qno))); 92 dev_info(dev, "R[%d]_OUT_INT_LEVELS[0x%llx]: 0x%016llx\n", 93 qno, CN93_SDP_R_OUT_INT_LEVELS(qno), 94 octep_read_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(qno))); 95 dev_info(dev, "R[%d]_OUT_PKT_CNT[0x%llx]: 0x%016llx\n", 96 qno, CN93_SDP_R_OUT_PKT_CNT(qno), 97 octep_read_csr64(oct, CN93_SDP_R_OUT_PKT_CNT(qno))); 98 dev_info(dev, "R[%d]_OUT_BYTE_CNT[0x%llx]: 0x%016llx\n", 99 qno, CN93_SDP_R_OUT_BYTE_CNT(qno), 100 octep_read_csr64(oct, CN93_SDP_R_OUT_BYTE_CNT(qno))); 101 dev_info(dev, "R[%d]_ERR_TYPE[0x%llx]: 0x%016llx\n", 102 qno, CN93_SDP_R_ERR_TYPE(qno), 103 octep_read_csr64(oct, CN93_SDP_R_ERR_TYPE(qno))); 104} 105 106/* Reset Hardware Tx queue */ 107static int cn93_reset_iq(struct octep_device *oct, int q_no) 108{ 109 struct octep_config *conf = oct->conf; 110 u64 val = 0ULL; 111 112 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no); 113 114 /* Get absolute queue number */ 115 q_no += conf->pf_ring_cfg.srn; 116 117 /* Disable the Tx/Instruction Ring */ 118 octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(q_no), val); 119 120 /* clear the Instruction Ring packet/byte counts and doorbell CSRs */ 121 octep_write_csr64(oct, CN93_SDP_R_IN_CNTS(q_no), val); 122 octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(q_no), val); 123 octep_write_csr64(oct, CN93_SDP_R_IN_PKT_CNT(q_no), val); 124 octep_write_csr64(oct, CN93_SDP_R_IN_BYTE_CNT(q_no), val); 125 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_BADDR(q_no), val); 126 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_RSIZE(q_no), val); 127 128 val = 0xFFFFFFFF; 129 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_DBELL(q_no), val); 130 131 return 0; 132} 133 134/* Reset Hardware Rx queue */ 135static void cn93_reset_oq(struct octep_device *oct, int q_no) 136{ 137 u64 val = 0ULL; 138 139 q_no += CFG_GET_PORTS_PF_SRN(oct->conf); 140 141 /* Disable Output (Rx) Ring */ 142 octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(q_no), val); 143 144 /* Clear count CSRs */ 145 val = octep_read_csr(oct, CN93_SDP_R_OUT_CNTS(q_no)); 146 octep_write_csr(oct, CN93_SDP_R_OUT_CNTS(q_no), val); 147 148 octep_write_csr64(oct, CN93_SDP_R_OUT_PKT_CNT(q_no), 0xFFFFFFFFFULL); 149 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_DBELL(q_no), 0xFFFFFFFF); 150} 151 152/* Reset all hardware Tx/Rx queues */ 153static void octep_reset_io_queues_cn93_pf(struct octep_device *oct) 154{ 155 struct pci_dev *pdev = oct->pdev; 156 int q; 157 158 dev_dbg(&pdev->dev, "Reset OCTEP_CN93 PF IO Queues\n"); 159 160 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) { 161 cn93_reset_iq(oct, q); 162 cn93_reset_oq(oct, q); 163 } 164} 165 166/* Initialize windowed addresses to access some hardware registers */ 167static void octep_setup_pci_window_regs_cn93_pf(struct octep_device *oct) 168{ 169 u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr; 170 171 oct->pci_win_regs.pci_win_wr_addr = (u8 __iomem *)(bar0_pciaddr + CN93_SDP_WIN_WR_ADDR64); 172 oct->pci_win_regs.pci_win_rd_addr = (u8 __iomem *)(bar0_pciaddr + CN93_SDP_WIN_RD_ADDR64); 173 oct->pci_win_regs.pci_win_wr_data = (u8 __iomem *)(bar0_pciaddr + CN93_SDP_WIN_WR_DATA64); 174 oct->pci_win_regs.pci_win_rd_data = (u8 __iomem *)(bar0_pciaddr + CN93_SDP_WIN_RD_DATA64); 175} 176 177/* Configure Hardware mapping: inform hardware which rings belong to PF. */ 178static void octep_configure_ring_mapping_cn93_pf(struct octep_device *oct) 179{ 180 struct octep_config *conf = oct->conf; 181 struct pci_dev *pdev = oct->pdev; 182 u64 pf_srn = CFG_GET_PORTS_PF_SRN(oct->conf); 183 int q; 184 185 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(conf); q++) { 186 u64 regval = 0; 187 188 if (oct->pcie_port) 189 regval = 8 << CN93_SDP_FUNC_SEL_EPF_BIT_POS; 190 191 octep_write_csr64(oct, CN93_SDP_EPVF_RING(pf_srn + q), regval); 192 193 regval = octep_read_csr64(oct, CN93_SDP_EPVF_RING(pf_srn + q)); 194 dev_dbg(&pdev->dev, "Write SDP_EPVF_RING[0x%llx] = 0x%llx\n", 195 CN93_SDP_EPVF_RING(pf_srn + q), regval); 196 } 197} 198 199/* Initialize configuration limits and initial active config 93xx PF. */ 200static void octep_init_config_cn93_pf(struct octep_device *oct) 201{ 202 struct octep_config *conf = oct->conf; 203 struct pci_dev *pdev = oct->pdev; 204 u8 link = 0; 205 u64 val; 206 int pos; 207 208 /* Read ring configuration: 209 * PF ring count, number of VFs and rings per VF supported 210 */ 211 val = octep_read_csr64(oct, CN93_SDP_EPF_RINFO); 212 conf->sriov_cfg.max_rings_per_vf = CN93_SDP_EPF_RINFO_RPVF(val); 213 conf->sriov_cfg.active_rings_per_vf = conf->sriov_cfg.max_rings_per_vf; 214 conf->sriov_cfg.max_vfs = CN93_SDP_EPF_RINFO_NVFS(val); 215 conf->sriov_cfg.active_vfs = conf->sriov_cfg.max_vfs; 216 conf->sriov_cfg.vf_srn = CN93_SDP_EPF_RINFO_SRN(val); 217 218 val = octep_read_csr64(oct, CN93_SDP_MAC_PF_RING_CTL(oct->pcie_port)); 219 if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF) { 220 conf->pf_ring_cfg.srn = CN98_SDP_MAC_PF_RING_CTL_SRN(val); 221 conf->pf_ring_cfg.max_io_rings = CN98_SDP_MAC_PF_RING_CTL_RPPF(val); 222 conf->pf_ring_cfg.active_io_rings = conf->pf_ring_cfg.max_io_rings; 223 } else { 224 conf->pf_ring_cfg.srn = CN93_SDP_MAC_PF_RING_CTL_SRN(val); 225 conf->pf_ring_cfg.max_io_rings = CN93_SDP_MAC_PF_RING_CTL_RPPF(val); 226 conf->pf_ring_cfg.active_io_rings = conf->pf_ring_cfg.max_io_rings; 227 } 228 dev_info(&pdev->dev, "pf_srn=%u rpvf=%u nvfs=%u rppf=%u\n", 229 conf->pf_ring_cfg.srn, conf->sriov_cfg.active_rings_per_vf, 230 conf->sriov_cfg.active_vfs, conf->pf_ring_cfg.active_io_rings); 231 232 conf->iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS; 233 conf->iq.instr_type = OCTEP_64BYTE_INSTR; 234 conf->iq.db_min = OCTEP_DB_MIN; 235 conf->iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD; 236 237 conf->oq.num_descs = OCTEP_OQ_MAX_DESCRIPTORS; 238 conf->oq.buf_size = OCTEP_OQ_BUF_SIZE; 239 conf->oq.refill_threshold = OCTEP_OQ_REFILL_THRESHOLD; 240 conf->oq.oq_intr_pkt = OCTEP_OQ_INTR_PKT_THRESHOLD; 241 conf->oq.oq_intr_time = OCTEP_OQ_INTR_TIME_THRESHOLD; 242 243 conf->msix_cfg.non_ioq_msix = CN93_NUM_NON_IOQ_INTR; 244 conf->msix_cfg.ioq_msix = conf->pf_ring_cfg.active_io_rings; 245 conf->msix_cfg.non_ioq_msix_names = cn93_non_ioq_msix_names; 246 247 pos = pci_find_ext_capability(oct->pdev, PCI_EXT_CAP_ID_SRIOV); 248 if (pos) { 249 pci_read_config_byte(oct->pdev, 250 pos + PCI_SRIOV_FUNC_LINK, 251 &link); 252 link = PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link); 253 } 254 conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr + 255 CN93_PEM_BAR4_INDEX_OFFSET + 256 (link * CTRL_MBOX_SZ); 257 258 conf->fw_info.hb_interval = OCTEP_DEFAULT_FW_HB_INTERVAL; 259 conf->fw_info.hb_miss_count = OCTEP_DEFAULT_FW_HB_MISS_COUNT; 260} 261 262/* Setup registers for a hardware Tx Queue */ 263static void octep_setup_iq_regs_cn93_pf(struct octep_device *oct, int iq_no) 264{ 265 struct octep_iq *iq = oct->iq[iq_no]; 266 u32 reset_instr_cnt; 267 u64 reg_val; 268 269 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 270 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); 271 272 /* wait for IDLE to set to 1 */ 273 if (!(reg_val & CN93_R_IN_CTL_IDLE)) { 274 do { 275 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); 276 } while (!(reg_val & CN93_R_IN_CTL_IDLE)); 277 } 278 279 reg_val |= CN93_R_IN_CTL_RDSIZE; 280 reg_val |= CN93_R_IN_CTL_IS_64B; 281 reg_val |= CN93_R_IN_CTL_ESR; 282 octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val); 283 284 /* Write the start of the input queue's ring and its size */ 285 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_BADDR(iq_no), 286 iq->desc_ring_dma); 287 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_RSIZE(iq_no), 288 iq->max_count); 289 290 /* Remember the doorbell & instruction count register addr 291 * for this queue 292 */ 293 iq->doorbell_reg = oct->mmio[0].hw_addr + 294 CN93_SDP_R_IN_INSTR_DBELL(iq_no); 295 iq->inst_cnt_reg = oct->mmio[0].hw_addr + 296 CN93_SDP_R_IN_CNTS(iq_no); 297 iq->intr_lvl_reg = oct->mmio[0].hw_addr + 298 CN93_SDP_R_IN_INT_LEVELS(iq_no); 299 300 /* Store the current instruction counter (used in flush_iq calculation) */ 301 reset_instr_cnt = readl(iq->inst_cnt_reg); 302 writel(reset_instr_cnt, iq->inst_cnt_reg); 303 304 /* INTR_THRESHOLD is set to max(FFFFFFFF) to disable the INTR */ 305 reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff; 306 octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no), reg_val); 307} 308 309/* Setup registers for a hardware Rx Queue */ 310static int octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_no) 311{ 312 u64 reg_val; 313 u64 oq_ctl = 0ULL; 314 u32 time_threshold = 0; 315 struct octep_oq *oq = oct->oq[oq_no]; 316 317 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 318 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no)); 319 320 /* wait for IDLE to set to 1 */ 321 if (!(reg_val & CN93_R_OUT_CTL_IDLE)) { 322 do { 323 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no)); 324 } while (!(reg_val & CN93_R_OUT_CTL_IDLE)); 325 } 326 327 reg_val &= ~(CN93_R_OUT_CTL_IMODE); 328 reg_val &= ~(CN93_R_OUT_CTL_ROR_P); 329 reg_val &= ~(CN93_R_OUT_CTL_NSR_P); 330 reg_val &= ~(CN93_R_OUT_CTL_ROR_I); 331 reg_val &= ~(CN93_R_OUT_CTL_NSR_I); 332 reg_val &= ~(CN93_R_OUT_CTL_ES_I); 333 reg_val &= ~(CN93_R_OUT_CTL_ROR_D); 334 reg_val &= ~(CN93_R_OUT_CTL_NSR_D); 335 reg_val &= ~(CN93_R_OUT_CTL_ES_D); 336 reg_val |= (CN93_R_OUT_CTL_ES_P); 337 338 octep_write_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no), reg_val); 339 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_BADDR(oq_no), 340 oq->desc_ring_dma); 341 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_RSIZE(oq_no), 342 oq->max_count); 343 344 oq_ctl = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no)); 345 oq_ctl &= ~0x7fffffULL; //clear the ISIZE and BSIZE (22-0) 346 oq_ctl |= (oq->buffer_size & 0xffff); //populate the BSIZE (15-0) 347 octep_write_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no), oq_ctl); 348 349 /* Get the mapped address of the pkt_sent and pkts_credit regs */ 350 oq->pkts_sent_reg = oct->mmio[0].hw_addr + CN93_SDP_R_OUT_CNTS(oq_no); 351 oq->pkts_credit_reg = oct->mmio[0].hw_addr + 352 CN93_SDP_R_OUT_SLIST_DBELL(oq_no); 353 354 time_threshold = CFG_GET_OQ_INTR_TIME(oct->conf); 355 reg_val = ((u64)time_threshold << 32) | 356 CFG_GET_OQ_INTR_PKT(oct->conf); 357 octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); 358 return 0; 359} 360 361/* Setup registers for a PF mailbox */ 362static void octep_setup_mbox_regs_cn93_pf(struct octep_device *oct, int q_no) 363{ 364 struct octep_mbox *mbox = oct->mbox[q_no]; 365 366 /* PF to VF DATA reg. PF writes into this reg */ 367 mbox->pf_vf_data_reg = oct->mmio[0].hw_addr + CN93_SDP_MBOX_PF_VF_DATA(q_no); 368 369 /* VF to PF DATA reg. PF reads from this reg */ 370 mbox->vf_pf_data_reg = oct->mmio[0].hw_addr + CN93_SDP_MBOX_VF_PF_DATA(q_no); 371} 372 373/* Poll for mailbox messages from VF */ 374static void octep_poll_pfvf_mailbox(struct octep_device *oct) 375{ 376 u32 vf, active_vfs, active_rings_per_vf, vf_mbox_queue; 377 u64 reg0, reg1; 378 379 reg0 = octep_read_csr64(oct, CN93_SDP_EPF_MBOX_RINT(0)); 380 reg1 = octep_read_csr64(oct, CN93_SDP_EPF_MBOX_RINT(1)); 381 if (reg0 || reg1) { 382 active_vfs = CFG_GET_ACTIVE_VFS(oct->conf); 383 active_rings_per_vf = CFG_GET_ACTIVE_RPVF(oct->conf); 384 for (vf = 0; vf < active_vfs; vf++) { 385 vf_mbox_queue = vf * active_rings_per_vf; 386 387 if (vf_mbox_queue < 64) { 388 if (!(reg0 & (0x1UL << vf_mbox_queue))) 389 continue; 390 } else { 391 if (!(reg1 & (0x1UL << (vf_mbox_queue - 64)))) 392 continue; 393 } 394 395 if (!oct->mbox[vf_mbox_queue]) { 396 dev_err(&oct->pdev->dev, "bad mbox vf %d\n", vf); 397 continue; 398 } 399 schedule_work(&oct->mbox[vf_mbox_queue]->wk.work); 400 } 401 if (reg0) 402 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT(0), reg0); 403 if (reg1) 404 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT(1), reg1); 405 } 406} 407 408/* PF-VF mailbox interrupt handler */ 409static irqreturn_t octep_pfvf_mbox_intr_handler_cn93_pf(void *dev) 410{ 411 struct octep_device *oct = (struct octep_device *)dev; 412 413 octep_poll_pfvf_mailbox(oct); 414 return IRQ_HANDLED; 415} 416 417/* Poll OEI events like heartbeat */ 418static void octep_poll_oei_cn93_pf(struct octep_device *oct) 419{ 420 u64 reg; 421 422 reg = octep_read_csr64(oct, CN93_SDP_EPF_OEI_RINT); 423 if (reg) { 424 octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT, reg); 425 if (reg & CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX) 426 queue_work(octep_wq, &oct->ctrl_mbox_task); 427 else if (reg & CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT) 428 atomic_set(&oct->hb_miss_cnt, 0); 429 } 430} 431 432/* OEI interrupt handler */ 433static irqreturn_t octep_oei_intr_handler_cn93_pf(void *dev) 434{ 435 struct octep_device *oct = (struct octep_device *)dev; 436 437 octep_poll_oei_cn93_pf(oct); 438 return IRQ_HANDLED; 439} 440 441/* Process non-ioq interrupts required to keep pf interface running. 442 * OEI_RINT is needed for control mailbox 443 */ 444static void octep_poll_non_ioq_interrupts_cn93_pf(struct octep_device *oct) 445{ 446 octep_poll_pfvf_mailbox(oct); 447 octep_poll_oei_cn93_pf(oct); 448} 449 450/* Interrupt handler for input ring error interrupts. */ 451static irqreturn_t octep_ire_intr_handler_cn93_pf(void *dev) 452{ 453 struct octep_device *oct = (struct octep_device *)dev; 454 struct pci_dev *pdev = oct->pdev; 455 u64 reg_val = 0; 456 int i = 0; 457 458 /* Check for IRERR INTR */ 459 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_IRERR_RINT); 460 if (reg_val) { 461 dev_info(&pdev->dev, 462 "received IRERR_RINT intr: 0x%llx\n", reg_val); 463 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT, reg_val); 464 465 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) { 466 reg_val = octep_read_csr64(oct, 467 CN93_SDP_R_ERR_TYPE(i)); 468 if (reg_val) { 469 dev_info(&pdev->dev, 470 "Received err type on IQ-%d: 0x%llx\n", 471 i, reg_val); 472 octep_write_csr64(oct, CN93_SDP_R_ERR_TYPE(i), 473 reg_val); 474 } 475 } 476 } 477 return IRQ_HANDLED; 478} 479 480/* Interrupt handler for output ring error interrupts. */ 481static irqreturn_t octep_ore_intr_handler_cn93_pf(void *dev) 482{ 483 struct octep_device *oct = (struct octep_device *)dev; 484 struct pci_dev *pdev = oct->pdev; 485 u64 reg_val = 0; 486 int i = 0; 487 488 /* Check for ORERR INTR */ 489 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_ORERR_RINT); 490 if (reg_val) { 491 dev_info(&pdev->dev, 492 "Received ORERR_RINT intr: 0x%llx\n", reg_val); 493 octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT, reg_val); 494 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) { 495 reg_val = octep_read_csr64(oct, CN93_SDP_R_ERR_TYPE(i)); 496 if (reg_val) { 497 dev_info(&pdev->dev, 498 "Received err type on OQ-%d: 0x%llx\n", 499 i, reg_val); 500 octep_write_csr64(oct, CN93_SDP_R_ERR_TYPE(i), 501 reg_val); 502 } 503 } 504 } 505 return IRQ_HANDLED; 506} 507 508/* Interrupt handler for vf input ring error interrupts. */ 509static irqreturn_t octep_vfire_intr_handler_cn93_pf(void *dev) 510{ 511 struct octep_device *oct = (struct octep_device *)dev; 512 struct pci_dev *pdev = oct->pdev; 513 u64 reg_val = 0; 514 515 /* Check for VFIRE INTR */ 516 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0)); 517 if (reg_val) { 518 dev_info(&pdev->dev, 519 "Received VFIRE_RINT intr: 0x%llx\n", reg_val); 520 octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0), reg_val); 521 } 522 return IRQ_HANDLED; 523} 524 525/* Interrupt handler for vf output ring error interrupts. */ 526static irqreturn_t octep_vfore_intr_handler_cn93_pf(void *dev) 527{ 528 struct octep_device *oct = (struct octep_device *)dev; 529 struct pci_dev *pdev = oct->pdev; 530 u64 reg_val = 0; 531 532 /* Check for VFORE INTR */ 533 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0)); 534 if (reg_val) { 535 dev_info(&pdev->dev, 536 "Received VFORE_RINT intr: 0x%llx\n", reg_val); 537 octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0), reg_val); 538 } 539 return IRQ_HANDLED; 540} 541 542/* Interrupt handler for dpi dma related interrupts. */ 543static irqreturn_t octep_dma_intr_handler_cn93_pf(void *dev) 544{ 545 struct octep_device *oct = (struct octep_device *)dev; 546 u64 reg_val = 0; 547 548 /* Check for DMA INTR */ 549 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_RINT); 550 if (reg_val) { 551 octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT, reg_val); 552 } 553 return IRQ_HANDLED; 554} 555 556/* Interrupt handler for dpi dma transaction error interrupts for VFs */ 557static irqreturn_t octep_dma_vf_intr_handler_cn93_pf(void *dev) 558{ 559 struct octep_device *oct = (struct octep_device *)dev; 560 struct pci_dev *pdev = oct->pdev; 561 u64 reg_val = 0; 562 563 /* Check for DMA VF INTR */ 564 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0)); 565 if (reg_val) { 566 dev_info(&pdev->dev, 567 "Received DMA_VF_RINT intr: 0x%llx\n", reg_val); 568 octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0), reg_val); 569 } 570 return IRQ_HANDLED; 571} 572 573/* Interrupt handler for pp transaction error interrupts for VFs */ 574static irqreturn_t octep_pp_vf_intr_handler_cn93_pf(void *dev) 575{ 576 struct octep_device *oct = (struct octep_device *)dev; 577 struct pci_dev *pdev = oct->pdev; 578 u64 reg_val = 0; 579 580 /* Check for PPVF INTR */ 581 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0)); 582 if (reg_val) { 583 dev_info(&pdev->dev, 584 "Received PP_VF_RINT intr: 0x%llx\n", reg_val); 585 octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0), reg_val); 586 } 587 return IRQ_HANDLED; 588} 589 590/* Interrupt handler for mac related interrupts. */ 591static irqreturn_t octep_misc_intr_handler_cn93_pf(void *dev) 592{ 593 struct octep_device *oct = (struct octep_device *)dev; 594 struct pci_dev *pdev = oct->pdev; 595 u64 reg_val = 0; 596 597 /* Check for MISC INTR */ 598 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_MISC_RINT); 599 if (reg_val) { 600 dev_info(&pdev->dev, 601 "Received MISC_RINT intr: 0x%llx\n", reg_val); 602 octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT, reg_val); 603 } 604 return IRQ_HANDLED; 605} 606 607/* Interrupts handler for all reserved interrupts. */ 608static irqreturn_t octep_rsvd_intr_handler_cn93_pf(void *dev) 609{ 610 struct octep_device *oct = (struct octep_device *)dev; 611 struct pci_dev *pdev = oct->pdev; 612 613 dev_info(&pdev->dev, "Reserved interrupts raised; Ignore\n"); 614 return IRQ_HANDLED; 615} 616 617/* Tx/Rx queue interrupt handler */ 618static irqreturn_t octep_ioq_intr_handler_cn93_pf(void *data) 619{ 620 struct octep_ioq_vector *vector = (struct octep_ioq_vector *)data; 621 struct octep_oq *oq = vector->oq; 622 623 napi_schedule_irqoff(oq->napi); 624 return IRQ_HANDLED; 625} 626 627/* soft reset of 98xx */ 628static int octep_soft_reset_cn98_pf(struct octep_device *oct) 629{ 630 dev_info(&oct->pdev->dev, "CN98XX: skip soft reset\n"); 631 return 0; 632} 633 634/* soft reset of 93xx */ 635static int octep_soft_reset_cn93_pf(struct octep_device *oct) 636{ 637 dev_info(&oct->pdev->dev, "CN93XX: Doing soft reset\n"); 638 639 octep_write_csr64(oct, CN93_SDP_WIN_WR_MASK_REG, 0xFF); 640 641 /* Set core domain reset bit */ 642 OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1S, 1); 643 /* Wait for 100ms as Octeon resets. */ 644 mdelay(100); 645 /* clear core domain reset bit */ 646 OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1C, 1); 647 648 return 0; 649} 650 651/* Re-initialize Octeon hardware registers */ 652static void octep_reinit_regs_cn93_pf(struct octep_device *oct) 653{ 654 u32 i; 655 656 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) 657 oct->hw_ops.setup_iq_regs(oct, i); 658 659 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) 660 oct->hw_ops.setup_oq_regs(oct, i); 661 662 oct->hw_ops.enable_interrupts(oct); 663 oct->hw_ops.enable_io_queues(oct); 664 665 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) 666 writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg); 667} 668 669/* Enable all interrupts */ 670static void octep_enable_interrupts_cn93_pf(struct octep_device *oct) 671{ 672 u64 intr_mask = 0ULL; 673 int srn, num_rings, i; 674 675 srn = CFG_GET_PORTS_PF_SRN(oct->conf); 676 num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); 677 678 for (i = 0; i < num_rings; i++) 679 intr_mask |= (0x1ULL << (srn + i)); 680 681 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1S, intr_mask); 682 octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1S, intr_mask); 683 octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT_ENA_W1S, -1ULL); 684 685 octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT_ENA_W1S(0), -1ULL); 686 octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT_ENA_W1S(0), -1ULL); 687 688 octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT_ENA_W1S, intr_mask); 689 octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT_ENA_W1S, intr_mask); 690 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1S(0), -1ULL); 691 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1S(1), -1ULL); 692 693 octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S(0), -1ULL); 694 octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT_ENA_W1S(0), -1ULL); 695} 696 697/* Disable all interrupts */ 698static void octep_disable_interrupts_cn93_pf(struct octep_device *oct) 699{ 700 u64 reg_val, intr_mask = 0ULL; 701 int srn, num_rings, i; 702 703 srn = CFG_GET_PORTS_PF_SRN(oct->conf); 704 num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); 705 706 for (i = 0; i < num_rings; i++) { 707 intr_mask |= BIT_ULL(srn + i); 708 reg_val = octep_read_csr64(oct, 709 CN93_SDP_R_IN_INT_LEVELS(srn + i)); 710 reg_val &= ~CN93_INT_ENA_BIT; 711 octep_write_csr64(oct, 712 CN93_SDP_R_IN_INT_LEVELS(srn + i), reg_val); 713 714 reg_val = octep_read_csr64(oct, 715 CN93_SDP_R_OUT_INT_LEVELS(srn + i)); 716 reg_val &= ~CN93_INT_ENA_BIT; 717 octep_write_csr64(oct, 718 CN93_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); 719 } 720 721 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); 722 octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); 723 octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT_ENA_W1C, -1ULL); 724 725 octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT_ENA_W1C(0), -1ULL); 726 octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT_ENA_W1C(0), -1ULL); 727 728 octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT_ENA_W1C, intr_mask); 729 octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT_ENA_W1C, intr_mask); 730 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1C(0), -1ULL); 731 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1C(1), -1ULL); 732 733 octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C(0), -1ULL); 734 octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT_ENA_W1C(0), -1ULL); 735} 736 737/* Get new Octeon Read Index: index of descriptor that Octeon reads next. */ 738static u32 octep_update_iq_read_index_cn93_pf(struct octep_iq *iq) 739{ 740 u32 pkt_in_done = readl(iq->inst_cnt_reg); 741 u32 last_done, new_idx; 742 743 last_done = pkt_in_done - iq->pkt_in_done; 744 iq->pkt_in_done = pkt_in_done; 745 746 new_idx = (iq->octep_read_index + last_done) % iq->max_count; 747 748 return new_idx; 749} 750 751/* Enable a hardware Tx Queue */ 752static void octep_enable_iq_cn93_pf(struct octep_device *oct, int iq_no) 753{ 754 u64 loop = HZ; 755 u64 reg_val; 756 757 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 758 759 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_DBELL(iq_no), 0xFFFFFFFF); 760 761 while (octep_read_csr64(oct, CN93_SDP_R_IN_INSTR_DBELL(iq_no)) && 762 loop--) { 763 schedule_timeout_interruptible(1); 764 } 765 766 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no)); 767 reg_val |= (0x1ULL << 62); 768 octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no), reg_val); 769 770 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no)); 771 reg_val |= 0x1ULL; 772 octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no), reg_val); 773} 774 775/* Enable a hardware Rx Queue */ 776static void octep_enable_oq_cn93_pf(struct octep_device *oct, int oq_no) 777{ 778 u64 reg_val = 0ULL; 779 780 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 781 782 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no)); 783 reg_val |= (0x1ULL << 62); 784 octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); 785 786 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_DBELL(oq_no), 0xFFFFFFFF); 787 788 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no)); 789 reg_val |= 0x1ULL; 790 octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no), reg_val); 791} 792 793/* Enable all hardware Tx/Rx Queues assined to PF */ 794static void octep_enable_io_queues_cn93_pf(struct octep_device *oct) 795{ 796 u8 q; 797 798 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) { 799 octep_enable_iq_cn93_pf(oct, q); 800 octep_enable_oq_cn93_pf(oct, q); 801 } 802} 803 804/* Disable a hardware Tx Queue assined to PF */ 805static void octep_disable_iq_cn93_pf(struct octep_device *oct, int iq_no) 806{ 807 u64 reg_val = 0ULL; 808 809 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 810 811 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no)); 812 reg_val &= ~0x1ULL; 813 octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no), reg_val); 814} 815 816/* Disable a hardware Rx Queue assined to PF */ 817static void octep_disable_oq_cn93_pf(struct octep_device *oct, int oq_no) 818{ 819 u64 reg_val = 0ULL; 820 821 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); 822 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no)); 823 reg_val &= ~0x1ULL; 824 octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no), reg_val); 825} 826 827/* Disable all hardware Tx/Rx Queues assined to PF */ 828static void octep_disable_io_queues_cn93_pf(struct octep_device *oct) 829{ 830 int q = 0; 831 832 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) { 833 octep_disable_iq_cn93_pf(oct, q); 834 octep_disable_oq_cn93_pf(oct, q); 835 } 836} 837 838/* Dump hardware registers (including Tx/Rx queues) for debugging. */ 839static void octep_dump_registers_cn93_pf(struct octep_device *oct) 840{ 841 u8 srn, num_rings, q; 842 843 srn = CFG_GET_PORTS_PF_SRN(oct->conf); 844 num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); 845 846 for (q = srn; q < srn + num_rings; q++) 847 cn93_dump_regs(oct, q); 848} 849 850/** 851 * octep_device_setup_cn93_pf() - Setup Octeon device. 852 * 853 * @oct: Octeon device private data structure. 854 * 855 * - initialize hardware operations. 856 * - get target side pcie port number for the device. 857 * - setup window access to hardware registers. 858 * - set initial configuration and max limits. 859 * - setup hardware mapping of rings to the PF device. 860 */ 861void octep_device_setup_cn93_pf(struct octep_device *oct) 862{ 863 oct->hw_ops.setup_iq_regs = octep_setup_iq_regs_cn93_pf; 864 oct->hw_ops.setup_oq_regs = octep_setup_oq_regs_cn93_pf; 865 oct->hw_ops.setup_mbox_regs = octep_setup_mbox_regs_cn93_pf; 866 867 oct->hw_ops.mbox_intr_handler = octep_pfvf_mbox_intr_handler_cn93_pf; 868 oct->hw_ops.oei_intr_handler = octep_oei_intr_handler_cn93_pf; 869 oct->hw_ops.ire_intr_handler = octep_ire_intr_handler_cn93_pf; 870 oct->hw_ops.ore_intr_handler = octep_ore_intr_handler_cn93_pf; 871 oct->hw_ops.vfire_intr_handler = octep_vfire_intr_handler_cn93_pf; 872 oct->hw_ops.vfore_intr_handler = octep_vfore_intr_handler_cn93_pf; 873 oct->hw_ops.dma_intr_handler = octep_dma_intr_handler_cn93_pf; 874 oct->hw_ops.dma_vf_intr_handler = octep_dma_vf_intr_handler_cn93_pf; 875 oct->hw_ops.pp_vf_intr_handler = octep_pp_vf_intr_handler_cn93_pf; 876 oct->hw_ops.misc_intr_handler = octep_misc_intr_handler_cn93_pf; 877 oct->hw_ops.rsvd_intr_handler = octep_rsvd_intr_handler_cn93_pf; 878 oct->hw_ops.ioq_intr_handler = octep_ioq_intr_handler_cn93_pf; 879 if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF) 880 oct->hw_ops.soft_reset = octep_soft_reset_cn98_pf; 881 else 882 oct->hw_ops.soft_reset = octep_soft_reset_cn93_pf; 883 oct->hw_ops.reinit_regs = octep_reinit_regs_cn93_pf; 884 885 oct->hw_ops.enable_interrupts = octep_enable_interrupts_cn93_pf; 886 oct->hw_ops.disable_interrupts = octep_disable_interrupts_cn93_pf; 887 oct->hw_ops.poll_non_ioq_interrupts = octep_poll_non_ioq_interrupts_cn93_pf; 888 889 oct->hw_ops.update_iq_read_idx = octep_update_iq_read_index_cn93_pf; 890 891 oct->hw_ops.enable_iq = octep_enable_iq_cn93_pf; 892 oct->hw_ops.enable_oq = octep_enable_oq_cn93_pf; 893 oct->hw_ops.enable_io_queues = octep_enable_io_queues_cn93_pf; 894 895 oct->hw_ops.disable_iq = octep_disable_iq_cn93_pf; 896 oct->hw_ops.disable_oq = octep_disable_oq_cn93_pf; 897 oct->hw_ops.disable_io_queues = octep_disable_io_queues_cn93_pf; 898 oct->hw_ops.reset_io_queues = octep_reset_io_queues_cn93_pf; 899 900 oct->hw_ops.dump_registers = octep_dump_registers_cn93_pf; 901 902 octep_setup_pci_window_regs_cn93_pf(oct); 903 904 oct->pcie_port = octep_read_csr64(oct, CN93_SDP_MAC_NUMBER) & 0xff; 905 dev_info(&oct->pdev->dev, 906 "Octeon device using PCIE Port %d\n", oct->pcie_port); 907 908 octep_init_config_cn93_pf(oct); 909 octep_configure_ring_mapping_cn93_pf(oct); 910}
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