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mv643xx_eth.c
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linux-6.19.14/drivers/net/ethernet/marvell/mv643xx_eth.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports 4 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> 5 * 6 * Based on the 64360 driver from: 7 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> 8 * Rabeeh Khoury <rabeeh@marvell.com> 9 * 10 * Copyright (C) 2003 PMC-Sierra, Inc., 11 * written by Manish Lachwani 12 * 13 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> 14 * 15 * Copyright (C) 2004-2006 MontaVista Software, Inc. 16 * Dale Farnsworth <dale@farnsworth.org> 17 * 18 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> 19 * <sjhill@realitydiluted.com> 20 * 21 * Copyright (C) 2007-2008 Marvell Semiconductor 22 * Lennert Buytenhek <buytenh@marvell.com> 23 * 24 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de> 25 */ 26 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29#include <linux/init.h> 30#include <linux/dma-mapping.h> 31#include <linux/in.h> 32#include <linux/ip.h> 33#include <net/tso.h> 34#include <linux/tcp.h> 35#include <linux/udp.h> 36#include <linux/etherdevice.h> 37#include <linux/delay.h> 38#include <linux/ethtool.h> 39#include <linux/platform_device.h> 40#include <linux/module.h> 41#include <linux/kernel.h> 42#include <linux/spinlock.h> 43#include <linux/workqueue.h> 44#include <linux/phy.h> 45#include <linux/mv643xx_eth.h> 46#include <linux/io.h> 47#include <linux/interrupt.h> 48#include <linux/types.h> 49#include <linux/slab.h> 50#include <linux/clk.h> 51#include <linux/of.h> 52#include <linux/of_irq.h> 53#include <linux/of_net.h> 54#include <linux/of_mdio.h> 55 56static char mv643xx_eth_driver_name[] = "mv643xx_eth"; 57static char mv643xx_eth_driver_version[] = "1.4"; 58 59 60/* 61 * Registers shared between all ports. 62 */ 63#define PHY_ADDR 0x0000 64#define WINDOW_BASE(w) (0x0200 + ((w) << 3)) 65#define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) 66#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) 67#define WINDOW_BAR_ENABLE 0x0290 68#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) 69 70/* 71 * Main per-port registers. These live at offset 0x0400 for 72 * port #0, 0x0800 for port #1, and 0x0c00 for port #2. 73 */ 74#define PORT_CONFIG 0x0000 75#define UNICAST_PROMISCUOUS_MODE 0x00000001 76#define PORT_CONFIG_EXT 0x0004 77#define MAC_ADDR_LOW 0x0014 78#define MAC_ADDR_HIGH 0x0018 79#define SDMA_CONFIG 0x001c 80#define TX_BURST_SIZE_16_64BIT 0x01000000 81#define TX_BURST_SIZE_4_64BIT 0x00800000 82#define BLM_TX_NO_SWAP 0x00000020 83#define BLM_RX_NO_SWAP 0x00000010 84#define RX_BURST_SIZE_16_64BIT 0x00000008 85#define RX_BURST_SIZE_4_64BIT 0x00000004 86#define PORT_SERIAL_CONTROL 0x003c 87#define SET_MII_SPEED_TO_100 0x01000000 88#define SET_GMII_SPEED_TO_1000 0x00800000 89#define SET_FULL_DUPLEX_MODE 0x00200000 90#define MAX_RX_PACKET_9700BYTE 0x000a0000 91#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 92#define DO_NOT_FORCE_LINK_FAIL 0x00000400 93#define SERIAL_PORT_CONTROL_RESERVED 0x00000200 94#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 95#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 96#define FORCE_LINK_PASS 0x00000002 97#define SERIAL_PORT_ENABLE 0x00000001 98#define PORT_STATUS 0x0044 99#define TX_FIFO_EMPTY 0x00000400 100#define TX_IN_PROGRESS 0x00000080 101#define PORT_SPEED_MASK 0x00000030 102#define PORT_SPEED_1000 0x00000010 103#define PORT_SPEED_100 0x00000020 104#define PORT_SPEED_10 0x00000000 105#define FLOW_CONTROL_ENABLED 0x00000008 106#define FULL_DUPLEX 0x00000004 107#define LINK_UP 0x00000002 108#define TXQ_COMMAND 0x0048 109#define TXQ_FIX_PRIO_CONF 0x004c 110#define PORT_SERIAL_CONTROL1 0x004c 111#define RGMII_EN 0x00000008 112#define CLK125_BYPASS_EN 0x00000010 113#define TX_BW_RATE 0x0050 114#define TX_BW_MTU 0x0058 115#define TX_BW_BURST 0x005c 116#define INT_CAUSE 0x0060 117#define INT_TX_END 0x07f80000 118#define INT_TX_END_0 0x00080000 119#define INT_RX 0x000003fc 120#define INT_RX_0 0x00000004 121#define INT_EXT 0x00000002 122#define INT_CAUSE_EXT 0x0064 123#define INT_EXT_LINK_PHY 0x00110000 124#define INT_EXT_TX 0x000000ff 125#define INT_MASK 0x0068 126#define INT_MASK_EXT 0x006c 127#define TX_FIFO_URGENT_THRESHOLD 0x0074 128#define RX_DISCARD_FRAME_CNT 0x0084 129#define RX_OVERRUN_FRAME_CNT 0x0088 130#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc 131#define TX_BW_RATE_MOVED 0x00e0 132#define TX_BW_MTU_MOVED 0x00e8 133#define TX_BW_BURST_MOVED 0x00ec 134#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) 135#define RXQ_COMMAND 0x0280 136#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) 137#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) 138#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) 139#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) 140 141/* 142 * Misc per-port registers. 143 */ 144#define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) 145#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) 146#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) 147#define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) 148 149 150/* 151 * SDMA configuration register default value. 152 */ 153#if defined(__BIG_ENDIAN) 154#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 155 (RX_BURST_SIZE_4_64BIT | \ 156 TX_BURST_SIZE_4_64BIT) 157#elif defined(__LITTLE_ENDIAN) 158#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 159 (RX_BURST_SIZE_4_64BIT | \ 160 BLM_RX_NO_SWAP | \ 161 BLM_TX_NO_SWAP | \ 162 TX_BURST_SIZE_4_64BIT) 163#else 164#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 165#endif 166 167 168/* 169 * Misc definitions. 170 */ 171#define DEFAULT_RX_QUEUE_SIZE 128 172#define DEFAULT_TX_QUEUE_SIZE 512 173#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 174 175/* Max number of allowed TCP segments for software TSO */ 176#define MV643XX_MAX_TSO_SEGS 100 177#define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 178 179#define IS_TSO_HEADER(txq, addr) \ 180 ((addr >= txq->tso_hdrs_dma) && \ 181 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 182 183#define DESC_DMA_MAP_SINGLE 0 184#define DESC_DMA_MAP_PAGE 1 185 186/* 187 * RX/TX descriptors. 188 */ 189#if defined(__BIG_ENDIAN) 190struct rx_desc { 191 u16 byte_cnt; /* Descriptor buffer byte count */ 192 u16 buf_size; /* Buffer size */ 193 u32 cmd_sts; /* Descriptor command status */ 194 u32 next_desc_ptr; /* Next descriptor pointer */ 195 u32 buf_ptr; /* Descriptor buffer pointer */ 196}; 197 198struct tx_desc { 199 u16 byte_cnt; /* buffer byte count */ 200 u16 l4i_chk; /* CPU provided TCP checksum */ 201 u32 cmd_sts; /* Command/status field */ 202 u32 next_desc_ptr; /* Pointer to next descriptor */ 203 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 204}; 205#elif defined(__LITTLE_ENDIAN) 206struct rx_desc { 207 u32 cmd_sts; /* Descriptor command status */ 208 u16 buf_size; /* Buffer size */ 209 u16 byte_cnt; /* Descriptor buffer byte count */ 210 u32 buf_ptr; /* Descriptor buffer pointer */ 211 u32 next_desc_ptr; /* Next descriptor pointer */ 212}; 213 214struct tx_desc { 215 u32 cmd_sts; /* Command/status field */ 216 u16 l4i_chk; /* CPU provided TCP checksum */ 217 u16 byte_cnt; /* buffer byte count */ 218 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 219 u32 next_desc_ptr; /* Pointer to next descriptor */ 220}; 221#else 222#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 223#endif 224 225/* RX & TX descriptor command */ 226#define BUFFER_OWNED_BY_DMA 0x80000000 227 228/* RX & TX descriptor status */ 229#define ERROR_SUMMARY 0x00000001 230 231/* RX descriptor status */ 232#define LAYER_4_CHECKSUM_OK 0x40000000 233#define RX_ENABLE_INTERRUPT 0x20000000 234#define RX_FIRST_DESC 0x08000000 235#define RX_LAST_DESC 0x04000000 236#define RX_IP_HDR_OK 0x02000000 237#define RX_PKT_IS_IPV4 0x01000000 238#define RX_PKT_IS_ETHERNETV2 0x00800000 239#define RX_PKT_LAYER4_TYPE_MASK 0x00600000 240#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 241#define RX_PKT_IS_VLAN_TAGGED 0x00080000 242 243/* TX descriptor command */ 244#define TX_ENABLE_INTERRUPT 0x00800000 245#define GEN_CRC 0x00400000 246#define TX_FIRST_DESC 0x00200000 247#define TX_LAST_DESC 0x00100000 248#define ZERO_PADDING 0x00080000 249#define GEN_IP_V4_CHECKSUM 0x00040000 250#define GEN_TCP_UDP_CHECKSUM 0x00020000 251#define UDP_FRAME 0x00010000 252#define MAC_HDR_EXTRA_4_BYTES 0x00008000 253#define GEN_TCP_UDP_CHK_FULL 0x00000400 254#define MAC_HDR_EXTRA_8_BYTES 0x00000200 255 256#define TX_IHL_SHIFT 11 257 258 259/* global *******************************************************************/ 260struct mv643xx_eth_shared_private { 261 /* 262 * Ethernet controller base address. 263 */ 264 void __iomem *base; 265 266 /* 267 * Per-port MBUS window access register value. 268 */ 269 u32 win_protect; 270 271 /* 272 * Hardware-specific parameters. 273 */ 274 int extended_rx_coal_limit; 275 int tx_bw_control; 276 int tx_csum_limit; 277 struct clk *clk; 278}; 279 280#define TX_BW_CONTROL_ABSENT 0 281#define TX_BW_CONTROL_OLD_LAYOUT 1 282#define TX_BW_CONTROL_NEW_LAYOUT 2 283 284static int mv643xx_eth_open(struct net_device *dev); 285static int mv643xx_eth_stop(struct net_device *dev); 286 287 288/* per-port *****************************************************************/ 289struct mib_counters { 290 u64 good_octets_received; 291 u32 bad_octets_received; 292 u32 internal_mac_transmit_err; 293 u32 good_frames_received; 294 u32 bad_frames_received; 295 u32 broadcast_frames_received; 296 u32 multicast_frames_received; 297 u32 frames_64_octets; 298 u32 frames_65_to_127_octets; 299 u32 frames_128_to_255_octets; 300 u32 frames_256_to_511_octets; 301 u32 frames_512_to_1023_octets; 302 u32 frames_1024_to_max_octets; 303 u64 good_octets_sent; 304 u32 good_frames_sent; 305 u32 excessive_collision; 306 u32 multicast_frames_sent; 307 u32 broadcast_frames_sent; 308 u32 unrec_mac_control_received; 309 u32 fc_sent; 310 u32 good_fc_received; 311 u32 bad_fc_received; 312 u32 undersize_received; 313 u32 fragments_received; 314 u32 oversize_received; 315 u32 jabber_received; 316 u32 mac_receive_error; 317 u32 bad_crc_event; 318 u32 collision; 319 u32 late_collision; 320 /* Non MIB hardware counters */ 321 u32 rx_discard; 322 u32 rx_overrun; 323}; 324 325struct rx_queue { 326 int index; 327 328 int rx_ring_size; 329 330 int rx_desc_count; 331 int rx_curr_desc; 332 int rx_used_desc; 333 334 struct rx_desc *rx_desc_area; 335 dma_addr_t rx_desc_dma; 336 int rx_desc_area_size; 337 struct sk_buff **rx_skb; 338}; 339 340struct tx_queue { 341 int index; 342 343 int tx_ring_size; 344 345 int tx_desc_count; 346 int tx_curr_desc; 347 int tx_used_desc; 348 349 int tx_stop_threshold; 350 int tx_wake_threshold; 351 352 char *tso_hdrs; 353 dma_addr_t tso_hdrs_dma; 354 355 struct tx_desc *tx_desc_area; 356 char *tx_desc_mapping; /* array to track the type of the dma mapping */ 357 dma_addr_t tx_desc_dma; 358 int tx_desc_area_size; 359 360 struct sk_buff_head tx_skb; 361 362 unsigned long tx_packets; 363 unsigned long tx_bytes; 364 unsigned long tx_dropped; 365}; 366 367struct mv643xx_eth_private { 368 struct mv643xx_eth_shared_private *shared; 369 void __iomem *base; 370 int port_num; 371 372 struct net_device *dev; 373 374 struct timer_list mib_counters_timer; 375 spinlock_t mib_counters_lock; 376 struct mib_counters mib_counters; 377 378 struct work_struct tx_timeout_task; 379 380 struct napi_struct napi; 381 u32 int_mask; 382 u8 oom; 383 u8 work_link; 384 u8 work_tx; 385 u8 work_tx_end; 386 u8 work_rx; 387 u8 work_rx_refill; 388 389 int skb_size; 390 391 /* 392 * RX state. 393 */ 394 int rx_ring_size; 395 unsigned long rx_desc_sram_addr; 396 int rx_desc_sram_size; 397 int rxq_count; 398 struct timer_list rx_oom; 399 struct rx_queue rxq[8]; 400 401 /* 402 * TX state. 403 */ 404 int tx_ring_size; 405 unsigned long tx_desc_sram_addr; 406 int tx_desc_sram_size; 407 int txq_count; 408 struct tx_queue txq[8]; 409 410 /* 411 * Hardware-specific parameters. 412 */ 413 struct clk *clk; 414 unsigned int t_clk; 415}; 416 417 418/* port register accessors **************************************************/ 419static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) 420{ 421 return readl(mp->shared->base + offset); 422} 423 424static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) 425{ 426 return readl(mp->base + offset); 427} 428 429static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) 430{ 431 writel(data, mp->shared->base + offset); 432} 433 434static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) 435{ 436 writel(data, mp->base + offset); 437} 438 439 440/* rxq/txq helper functions *************************************************/ 441static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) 442{ 443 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); 444} 445 446static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) 447{ 448 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); 449} 450 451static void rxq_enable(struct rx_queue *rxq) 452{ 453 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 454 wrlp(mp, RXQ_COMMAND, 1 << rxq->index); 455} 456 457static void rxq_disable(struct rx_queue *rxq) 458{ 459 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 460 u8 mask = 1 << rxq->index; 461 462 wrlp(mp, RXQ_COMMAND, mask << 8); 463 while (rdlp(mp, RXQ_COMMAND) & mask) 464 udelay(10); 465} 466 467static void txq_reset_hw_ptr(struct tx_queue *txq) 468{ 469 struct mv643xx_eth_private *mp = txq_to_mp(txq); 470 u32 addr; 471 472 addr = (u32)txq->tx_desc_dma; 473 addr += txq->tx_curr_desc * sizeof(struct tx_desc); 474 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); 475} 476 477static void txq_enable(struct tx_queue *txq) 478{ 479 struct mv643xx_eth_private *mp = txq_to_mp(txq); 480 wrlp(mp, TXQ_COMMAND, 1 << txq->index); 481} 482 483static void txq_disable(struct tx_queue *txq) 484{ 485 struct mv643xx_eth_private *mp = txq_to_mp(txq); 486 u8 mask = 1 << txq->index; 487 488 wrlp(mp, TXQ_COMMAND, mask << 8); 489 while (rdlp(mp, TXQ_COMMAND) & mask) 490 udelay(10); 491} 492 493static void txq_maybe_wake(struct tx_queue *txq) 494{ 495 struct mv643xx_eth_private *mp = txq_to_mp(txq); 496 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 497 498 if (netif_tx_queue_stopped(nq)) { 499 __netif_tx_lock(nq, smp_processor_id()); 500 if (txq->tx_desc_count <= txq->tx_wake_threshold) 501 netif_tx_wake_queue(nq); 502 __netif_tx_unlock(nq); 503 } 504} 505 506static int rxq_process(struct rx_queue *rxq, int budget) 507{ 508 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 509 struct net_device_stats *stats = &mp->dev->stats; 510 int rx; 511 512 rx = 0; 513 while (rx < budget && rxq->rx_desc_count) { 514 struct rx_desc *rx_desc; 515 unsigned int cmd_sts; 516 struct sk_buff *skb; 517 u16 byte_cnt; 518 519 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; 520 521 cmd_sts = rx_desc->cmd_sts; 522 if (cmd_sts & BUFFER_OWNED_BY_DMA) 523 break; 524 rmb(); 525 526 skb = rxq->rx_skb[rxq->rx_curr_desc]; 527 rxq->rx_skb[rxq->rx_curr_desc] = NULL; 528 529 rxq->rx_curr_desc++; 530 if (rxq->rx_curr_desc == rxq->rx_ring_size) 531 rxq->rx_curr_desc = 0; 532 533 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, 534 rx_desc->buf_size, DMA_FROM_DEVICE); 535 rxq->rx_desc_count--; 536 rx++; 537 538 mp->work_rx_refill |= 1 << rxq->index; 539 540 byte_cnt = rx_desc->byte_cnt; 541 542 /* 543 * Update statistics. 544 * 545 * Note that the descriptor byte count includes 2 dummy 546 * bytes automatically inserted by the hardware at the 547 * start of the packet (which we don't count), and a 4 548 * byte CRC at the end of the packet (which we do count). 549 */ 550 stats->rx_packets++; 551 stats->rx_bytes += byte_cnt - 2; 552 553 /* 554 * In case we received a packet without first / last bits 555 * on, or the error summary bit is set, the packet needs 556 * to be dropped. 557 */ 558 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) 559 != (RX_FIRST_DESC | RX_LAST_DESC)) 560 goto err; 561 562 /* 563 * The -4 is for the CRC in the trailer of the 564 * received packet 565 */ 566 skb_put(skb, byte_cnt - 2 - 4); 567 568 if (cmd_sts & LAYER_4_CHECKSUM_OK) 569 skb->ip_summed = CHECKSUM_UNNECESSARY; 570 skb->protocol = eth_type_trans(skb, mp->dev); 571 572 napi_gro_receive(&mp->napi, skb); 573 574 continue; 575 576err: 577 stats->rx_dropped++; 578 579 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 580 (RX_FIRST_DESC | RX_LAST_DESC)) { 581 if (net_ratelimit()) 582 netdev_err(mp->dev, 583 "received packet spanning multiple descriptors\n"); 584 } 585 586 if (cmd_sts & ERROR_SUMMARY) 587 stats->rx_errors++; 588 589 dev_kfree_skb(skb); 590 } 591 592 if (rx < budget) 593 mp->work_rx &= ~(1 << rxq->index); 594 595 return rx; 596} 597 598static int rxq_refill(struct rx_queue *rxq, int budget) 599{ 600 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 601 int refilled; 602 603 refilled = 0; 604 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { 605 struct sk_buff *skb; 606 int rx; 607 struct rx_desc *rx_desc; 608 int size; 609 610 skb = netdev_alloc_skb(mp->dev, mp->skb_size); 611 612 if (skb == NULL) { 613 mp->oom = 1; 614 goto oom; 615 } 616 617 if (SKB_DMA_REALIGN) 618 skb_reserve(skb, SKB_DMA_REALIGN); 619 620 refilled++; 621 rxq->rx_desc_count++; 622 623 rx = rxq->rx_used_desc++; 624 if (rxq->rx_used_desc == rxq->rx_ring_size) 625 rxq->rx_used_desc = 0; 626 627 rx_desc = rxq->rx_desc_area + rx; 628 629 size = skb_end_pointer(skb) - skb->data; 630 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, 631 skb->data, size, 632 DMA_FROM_DEVICE); 633 rx_desc->buf_size = size; 634 rxq->rx_skb[rx] = skb; 635 wmb(); 636 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; 637 wmb(); 638 639 /* 640 * The hardware automatically prepends 2 bytes of 641 * dummy data to each received packet, so that the 642 * IP header ends up 16-byte aligned. 643 */ 644 skb_reserve(skb, 2); 645 } 646 647 if (refilled < budget) 648 mp->work_rx_refill &= ~(1 << rxq->index); 649 650oom: 651 return refilled; 652} 653 654 655/* tx ***********************************************************************/ 656static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 657{ 658 int frag; 659 660 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 661 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 662 663 if (skb_frag_size(fragp) <= 8 && skb_frag_off(fragp) & 7) 664 return 1; 665 } 666 667 return 0; 668} 669 670static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb, 671 u16 *l4i_chk, u32 *command, int length) 672{ 673 int ret; 674 u32 cmd = 0; 675 676 if (skb->ip_summed == CHECKSUM_PARTIAL) { 677 int hdr_len; 678 int tag_bytes; 679 680 BUG_ON(skb->protocol != htons(ETH_P_IP) && 681 skb->protocol != htons(ETH_P_8021Q)); 682 683 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; 684 tag_bytes = hdr_len - ETH_HLEN; 685 686 if (length - hdr_len > mp->shared->tx_csum_limit || 687 unlikely(tag_bytes & ~12)) { 688 ret = skb_checksum_help(skb); 689 if (!ret) 690 goto no_csum; 691 return ret; 692 } 693 694 if (tag_bytes & 4) 695 cmd |= MAC_HDR_EXTRA_4_BYTES; 696 if (tag_bytes & 8) 697 cmd |= MAC_HDR_EXTRA_8_BYTES; 698 699 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL | 700 GEN_IP_V4_CHECKSUM | 701 ip_hdr(skb)->ihl << TX_IHL_SHIFT; 702 703 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL 704 * it seems we don't need to pass the initial checksum. 705 */ 706 switch (ip_hdr(skb)->protocol) { 707 case IPPROTO_UDP: 708 cmd |= UDP_FRAME; 709 *l4i_chk = 0; 710 break; 711 case IPPROTO_TCP: 712 *l4i_chk = 0; 713 break; 714 default: 715 WARN(1, "protocol not supported"); 716 } 717 } else { 718no_csum: 719 /* Errata BTS #50, IHL must be 5 if no HW checksum */ 720 cmd |= 5 << TX_IHL_SHIFT; 721 } 722 *command = cmd; 723 return 0; 724} 725 726static inline int 727txq_put_data_tso(struct net_device *dev, struct tx_queue *txq, 728 struct sk_buff *skb, char *data, int length, 729 bool last_tcp, bool is_last) 730{ 731 int tx_index; 732 u32 cmd_sts; 733 struct tx_desc *desc; 734 735 tx_index = txq->tx_curr_desc++; 736 if (txq->tx_curr_desc == txq->tx_ring_size) 737 txq->tx_curr_desc = 0; 738 desc = &txq->tx_desc_area[tx_index]; 739 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 740 741 desc->l4i_chk = 0; 742 desc->byte_cnt = length; 743 744 if (length <= 8 && (uintptr_t)data & 0x7) { 745 /* Copy unaligned small data fragment to TSO header data area */ 746 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE, 747 data, length); 748 desc->buf_ptr = txq->tso_hdrs_dma 749 + tx_index * TSO_HEADER_SIZE; 750 } else { 751 /* Alignment is okay, map buffer and hand off to hardware */ 752 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 753 desc->buf_ptr = dma_map_single(dev->dev.parent, data, 754 length, DMA_TO_DEVICE); 755 if (unlikely(dma_mapping_error(dev->dev.parent, 756 desc->buf_ptr))) { 757 WARN(1, "dma_map_single failed!\n"); 758 return -ENOMEM; 759 } 760 } 761 762 cmd_sts = BUFFER_OWNED_BY_DMA; 763 if (last_tcp) { 764 /* last descriptor in the TCP packet */ 765 cmd_sts |= ZERO_PADDING | TX_LAST_DESC; 766 /* last descriptor in SKB */ 767 if (is_last) 768 cmd_sts |= TX_ENABLE_INTERRUPT; 769 } 770 desc->cmd_sts = cmd_sts; 771 return 0; 772} 773 774static inline void 775txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length, 776 u32 *first_cmd_sts, bool first_desc) 777{ 778 struct mv643xx_eth_private *mp = txq_to_mp(txq); 779 int hdr_len = skb_tcp_all_headers(skb); 780 int tx_index; 781 struct tx_desc *desc; 782 int ret; 783 u32 cmd_csum = 0; 784 u16 l4i_chk = 0; 785 u32 cmd_sts; 786 787 tx_index = txq->tx_curr_desc; 788 desc = &txq->tx_desc_area[tx_index]; 789 790 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length); 791 if (ret) 792 WARN(1, "failed to prepare checksum!"); 793 794 /* Should we set this? Can't use the value from skb_tx_csum() 795 * as it's not the correct initial L4 checksum to use. 796 */ 797 desc->l4i_chk = 0; 798 799 desc->byte_cnt = hdr_len; 800 desc->buf_ptr = txq->tso_hdrs_dma + 801 txq->tx_curr_desc * TSO_HEADER_SIZE; 802 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC | 803 GEN_CRC; 804 805 /* Defer updating the first command descriptor until all 806 * following descriptors have been written. 807 */ 808 if (first_desc) 809 *first_cmd_sts = cmd_sts; 810 else 811 desc->cmd_sts = cmd_sts; 812 813 txq->tx_curr_desc++; 814 if (txq->tx_curr_desc == txq->tx_ring_size) 815 txq->tx_curr_desc = 0; 816} 817 818static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb, 819 struct net_device *dev) 820{ 821 struct mv643xx_eth_private *mp = txq_to_mp(txq); 822 int hdr_len, total_len, data_left, ret; 823 int desc_count = 0; 824 struct tso_t tso; 825 struct tx_desc *first_tx_desc; 826 u32 first_cmd_sts = 0; 827 828 /* Count needed descriptors */ 829 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) { 830 netdev_dbg(dev, "not enough descriptors for TSO!\n"); 831 return -EBUSY; 832 } 833 834 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc]; 835 836 /* Initialize the TSO handler, and prepare the first payload */ 837 hdr_len = tso_start(skb, &tso); 838 839 total_len = skb->len - hdr_len; 840 while (total_len > 0) { 841 bool first_desc = (desc_count == 0); 842 char *hdr; 843 844 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 845 total_len -= data_left; 846 desc_count++; 847 848 /* prepare packet headers: MAC + IP + TCP */ 849 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE; 850 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 851 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts, 852 first_desc); 853 854 while (data_left > 0) { 855 int size; 856 desc_count++; 857 858 size = min_t(int, tso.size, data_left); 859 ret = txq_put_data_tso(dev, txq, skb, tso.data, size, 860 size == data_left, 861 total_len == 0); 862 if (ret) 863 goto err_release; 864 data_left -= size; 865 tso_build_data(skb, &tso, size); 866 } 867 } 868 869 __skb_queue_tail(&txq->tx_skb, skb); 870 skb_tx_timestamp(skb); 871 872 /* ensure all other descriptors are written before first cmd_sts */ 873 wmb(); 874 first_tx_desc->cmd_sts = first_cmd_sts; 875 876 /* clear TX_END status */ 877 mp->work_tx_end &= ~(1 << txq->index); 878 879 /* ensure all descriptors are written before poking hardware */ 880 wmb(); 881 txq_enable(txq); 882 txq->tx_desc_count += desc_count; 883 return 0; 884err_release: 885 /* TODO: Release all used data descriptors; header descriptors must not 886 * be DMA-unmapped. 887 */ 888 return ret; 889} 890 891static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) 892{ 893 struct mv643xx_eth_private *mp = txq_to_mp(txq); 894 int nr_frags = skb_shinfo(skb)->nr_frags; 895 int frag; 896 897 for (frag = 0; frag < nr_frags; frag++) { 898 skb_frag_t *this_frag; 899 int tx_index; 900 struct tx_desc *desc; 901 902 this_frag = &skb_shinfo(skb)->frags[frag]; 903 tx_index = txq->tx_curr_desc++; 904 if (txq->tx_curr_desc == txq->tx_ring_size) 905 txq->tx_curr_desc = 0; 906 desc = &txq->tx_desc_area[tx_index]; 907 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE; 908 909 /* 910 * The last fragment will generate an interrupt 911 * which will free the skb on TX completion. 912 */ 913 if (frag == nr_frags - 1) { 914 desc->cmd_sts = BUFFER_OWNED_BY_DMA | 915 ZERO_PADDING | TX_LAST_DESC | 916 TX_ENABLE_INTERRUPT; 917 } else { 918 desc->cmd_sts = BUFFER_OWNED_BY_DMA; 919 } 920 921 desc->l4i_chk = 0; 922 desc->byte_cnt = skb_frag_size(this_frag); 923 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent, 924 this_frag, 0, desc->byte_cnt, 925 DMA_TO_DEVICE); 926 } 927} 928 929static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb, 930 struct net_device *dev) 931{ 932 struct mv643xx_eth_private *mp = txq_to_mp(txq); 933 int nr_frags = skb_shinfo(skb)->nr_frags; 934 int tx_index; 935 struct tx_desc *desc; 936 u32 cmd_sts; 937 u16 l4i_chk; 938 int length, ret; 939 940 cmd_sts = 0; 941 l4i_chk = 0; 942 943 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { 944 if (net_ratelimit()) 945 netdev_err(dev, "tx queue full?!\n"); 946 return -EBUSY; 947 } 948 949 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len); 950 if (ret) 951 return ret; 952 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; 953 954 tx_index = txq->tx_curr_desc++; 955 if (txq->tx_curr_desc == txq->tx_ring_size) 956 txq->tx_curr_desc = 0; 957 desc = &txq->tx_desc_area[tx_index]; 958 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 959 960 if (nr_frags) { 961 txq_submit_frag_skb(txq, skb); 962 length = skb_headlen(skb); 963 } else { 964 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; 965 length = skb->len; 966 } 967 968 desc->l4i_chk = l4i_chk; 969 desc->byte_cnt = length; 970 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, 971 length, DMA_TO_DEVICE); 972 973 __skb_queue_tail(&txq->tx_skb, skb); 974 975 skb_tx_timestamp(skb); 976 977 /* ensure all other descriptors are written before first cmd_sts */ 978 wmb(); 979 desc->cmd_sts = cmd_sts; 980 981 /* clear TX_END status */ 982 mp->work_tx_end &= ~(1 << txq->index); 983 984 /* ensure all descriptors are written before poking hardware */ 985 wmb(); 986 txq_enable(txq); 987 988 txq->tx_desc_count += nr_frags + 1; 989 990 return 0; 991} 992 993static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) 994{ 995 struct mv643xx_eth_private *mp = netdev_priv(dev); 996 int length, queue, ret; 997 struct tx_queue *txq; 998 struct netdev_queue *nq; 999 1000 queue = skb_get_queue_mapping(skb); 1001 txq = mp->txq + queue; 1002 nq = netdev_get_tx_queue(dev, queue); 1003 1004 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 1005 netdev_printk(KERN_DEBUG, dev, 1006 "failed to linearize skb with tiny unaligned fragment\n"); 1007 return NETDEV_TX_BUSY; 1008 } 1009 1010 length = skb->len; 1011 1012 if (skb_is_gso(skb)) 1013 ret = txq_submit_tso(txq, skb, dev); 1014 else 1015 ret = txq_submit_skb(txq, skb, dev); 1016 if (!ret) { 1017 txq->tx_bytes += length; 1018 txq->tx_packets++; 1019 1020 if (txq->tx_desc_count >= txq->tx_stop_threshold) 1021 netif_tx_stop_queue(nq); 1022 } else { 1023 txq->tx_dropped++; 1024 dev_kfree_skb_any(skb); 1025 } 1026 1027 return NETDEV_TX_OK; 1028} 1029 1030 1031/* tx napi ******************************************************************/ 1032static void txq_kick(struct tx_queue *txq) 1033{ 1034 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1035 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1036 u32 hw_desc_ptr; 1037 u32 expected_ptr; 1038 1039 __netif_tx_lock(nq, smp_processor_id()); 1040 1041 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) 1042 goto out; 1043 1044 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); 1045 expected_ptr = (u32)txq->tx_desc_dma + 1046 txq->tx_curr_desc * sizeof(struct tx_desc); 1047 1048 if (hw_desc_ptr != expected_ptr) 1049 txq_enable(txq); 1050 1051out: 1052 __netif_tx_unlock(nq); 1053 1054 mp->work_tx_end &= ~(1 << txq->index); 1055} 1056 1057static int txq_reclaim(struct tx_queue *txq, int budget, int force) 1058{ 1059 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1060 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1061 int reclaimed; 1062 1063 __netif_tx_lock_bh(nq); 1064 1065 reclaimed = 0; 1066 while (reclaimed < budget && txq->tx_desc_count > 0) { 1067 int tx_index; 1068 struct tx_desc *desc; 1069 u32 cmd_sts; 1070 char desc_dma_map; 1071 1072 tx_index = txq->tx_used_desc; 1073 desc = &txq->tx_desc_area[tx_index]; 1074 desc_dma_map = txq->tx_desc_mapping[tx_index]; 1075 1076 cmd_sts = desc->cmd_sts; 1077 1078 if (cmd_sts & BUFFER_OWNED_BY_DMA) { 1079 if (!force) 1080 break; 1081 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; 1082 } 1083 1084 txq->tx_used_desc = tx_index + 1; 1085 if (txq->tx_used_desc == txq->tx_ring_size) 1086 txq->tx_used_desc = 0; 1087 1088 reclaimed++; 1089 txq->tx_desc_count--; 1090 1091 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) { 1092 1093 if (desc_dma_map == DESC_DMA_MAP_PAGE) 1094 dma_unmap_page(mp->dev->dev.parent, 1095 desc->buf_ptr, 1096 desc->byte_cnt, 1097 DMA_TO_DEVICE); 1098 else 1099 dma_unmap_single(mp->dev->dev.parent, 1100 desc->buf_ptr, 1101 desc->byte_cnt, 1102 DMA_TO_DEVICE); 1103 } 1104 1105 if (cmd_sts & TX_ENABLE_INTERRUPT) { 1106 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb); 1107 1108 if (!WARN_ON(!skb)) 1109 dev_consume_skb_any(skb); 1110 } 1111 1112 if (cmd_sts & ERROR_SUMMARY) { 1113 netdev_info(mp->dev, "tx error\n"); 1114 mp->dev->stats.tx_errors++; 1115 } 1116 1117 } 1118 1119 __netif_tx_unlock_bh(nq); 1120 1121 if (reclaimed < budget) 1122 mp->work_tx &= ~(1 << txq->index); 1123 1124 return reclaimed; 1125} 1126 1127 1128/* tx rate control **********************************************************/ 1129/* 1130 * Set total maximum TX rate (shared by all TX queues for this port) 1131 * to 'rate' bits per second, with a maximum burst of 'burst' bytes. 1132 */ 1133static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) 1134{ 1135 int token_rate; 1136 int mtu; 1137 int bucket_size; 1138 1139 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1140 if (token_rate > 1023) 1141 token_rate = 1023; 1142 1143 mtu = (mp->dev->mtu + 255) >> 8; 1144 if (mtu > 63) 1145 mtu = 63; 1146 1147 bucket_size = (burst + 255) >> 8; 1148 if (bucket_size > 65535) 1149 bucket_size = 65535; 1150 1151 switch (mp->shared->tx_bw_control) { 1152 case TX_BW_CONTROL_OLD_LAYOUT: 1153 wrlp(mp, TX_BW_RATE, token_rate); 1154 wrlp(mp, TX_BW_MTU, mtu); 1155 wrlp(mp, TX_BW_BURST, bucket_size); 1156 break; 1157 case TX_BW_CONTROL_NEW_LAYOUT: 1158 wrlp(mp, TX_BW_RATE_MOVED, token_rate); 1159 wrlp(mp, TX_BW_MTU_MOVED, mtu); 1160 wrlp(mp, TX_BW_BURST_MOVED, bucket_size); 1161 break; 1162 } 1163} 1164 1165static void txq_set_rate(struct tx_queue *txq, int rate, int burst) 1166{ 1167 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1168 int token_rate; 1169 int bucket_size; 1170 1171 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1172 if (token_rate > 1023) 1173 token_rate = 1023; 1174 1175 bucket_size = (burst + 255) >> 8; 1176 if (bucket_size > 65535) 1177 bucket_size = 65535; 1178 1179 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); 1180 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); 1181} 1182 1183static void txq_set_fixed_prio_mode(struct tx_queue *txq) 1184{ 1185 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1186 int off; 1187 u32 val; 1188 1189 /* 1190 * Turn on fixed priority mode. 1191 */ 1192 off = 0; 1193 switch (mp->shared->tx_bw_control) { 1194 case TX_BW_CONTROL_OLD_LAYOUT: 1195 off = TXQ_FIX_PRIO_CONF; 1196 break; 1197 case TX_BW_CONTROL_NEW_LAYOUT: 1198 off = TXQ_FIX_PRIO_CONF_MOVED; 1199 break; 1200 } 1201 1202 if (off) { 1203 val = rdlp(mp, off); 1204 val |= 1 << txq->index; 1205 wrlp(mp, off, val); 1206 } 1207} 1208 1209 1210/* mii management interface *************************************************/ 1211static void mv643xx_eth_adjust_link(struct net_device *dev) 1212{ 1213 struct mv643xx_eth_private *mp = netdev_priv(dev); 1214 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 1215 u32 autoneg_disable = FORCE_LINK_PASS | 1216 DISABLE_AUTO_NEG_SPEED_GMII | 1217 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1218 DISABLE_AUTO_NEG_FOR_DUPLEX; 1219 1220 if (dev->phydev->autoneg == AUTONEG_ENABLE) { 1221 /* enable auto negotiation */ 1222 pscr &= ~autoneg_disable; 1223 goto out_write; 1224 } 1225 1226 pscr |= autoneg_disable; 1227 1228 if (dev->phydev->speed == SPEED_1000) { 1229 /* force gigabit, half duplex not supported */ 1230 pscr |= SET_GMII_SPEED_TO_1000; 1231 pscr |= SET_FULL_DUPLEX_MODE; 1232 goto out_write; 1233 } 1234 1235 pscr &= ~SET_GMII_SPEED_TO_1000; 1236 1237 if (dev->phydev->speed == SPEED_100) 1238 pscr |= SET_MII_SPEED_TO_100; 1239 else 1240 pscr &= ~SET_MII_SPEED_TO_100; 1241 1242 if (dev->phydev->duplex == DUPLEX_FULL) 1243 pscr |= SET_FULL_DUPLEX_MODE; 1244 else 1245 pscr &= ~SET_FULL_DUPLEX_MODE; 1246 1247out_write: 1248 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 1249} 1250 1251/* statistics ***************************************************************/ 1252static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) 1253{ 1254 struct mv643xx_eth_private *mp = netdev_priv(dev); 1255 struct net_device_stats *stats = &dev->stats; 1256 unsigned long tx_packets = 0; 1257 unsigned long tx_bytes = 0; 1258 unsigned long tx_dropped = 0; 1259 int i; 1260 1261 for (i = 0; i < mp->txq_count; i++) { 1262 struct tx_queue *txq = mp->txq + i; 1263 1264 tx_packets += txq->tx_packets; 1265 tx_bytes += txq->tx_bytes; 1266 tx_dropped += txq->tx_dropped; 1267 } 1268 1269 stats->tx_packets = tx_packets; 1270 stats->tx_bytes = tx_bytes; 1271 stats->tx_dropped = tx_dropped; 1272 1273 return stats; 1274} 1275 1276static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) 1277{ 1278 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); 1279} 1280 1281static void mib_counters_clear(struct mv643xx_eth_private *mp) 1282{ 1283 int i; 1284 1285 for (i = 0; i < 0x80; i += 4) 1286 mib_read(mp, i); 1287 1288 /* Clear non MIB hw counters also */ 1289 rdlp(mp, RX_DISCARD_FRAME_CNT); 1290 rdlp(mp, RX_OVERRUN_FRAME_CNT); 1291} 1292 1293static void mib_counters_update(struct mv643xx_eth_private *mp) 1294{ 1295 struct mib_counters *p = &mp->mib_counters; 1296 1297 spin_lock_bh(&mp->mib_counters_lock); 1298 p->good_octets_received += mib_read(mp, 0x00); 1299 p->bad_octets_received += mib_read(mp, 0x08); 1300 p->internal_mac_transmit_err += mib_read(mp, 0x0c); 1301 p->good_frames_received += mib_read(mp, 0x10); 1302 p->bad_frames_received += mib_read(mp, 0x14); 1303 p->broadcast_frames_received += mib_read(mp, 0x18); 1304 p->multicast_frames_received += mib_read(mp, 0x1c); 1305 p->frames_64_octets += mib_read(mp, 0x20); 1306 p->frames_65_to_127_octets += mib_read(mp, 0x24); 1307 p->frames_128_to_255_octets += mib_read(mp, 0x28); 1308 p->frames_256_to_511_octets += mib_read(mp, 0x2c); 1309 p->frames_512_to_1023_octets += mib_read(mp, 0x30); 1310 p->frames_1024_to_max_octets += mib_read(mp, 0x34); 1311 p->good_octets_sent += mib_read(mp, 0x38); 1312 p->good_frames_sent += mib_read(mp, 0x40); 1313 p->excessive_collision += mib_read(mp, 0x44); 1314 p->multicast_frames_sent += mib_read(mp, 0x48); 1315 p->broadcast_frames_sent += mib_read(mp, 0x4c); 1316 p->unrec_mac_control_received += mib_read(mp, 0x50); 1317 p->fc_sent += mib_read(mp, 0x54); 1318 p->good_fc_received += mib_read(mp, 0x58); 1319 p->bad_fc_received += mib_read(mp, 0x5c); 1320 p->undersize_received += mib_read(mp, 0x60); 1321 p->fragments_received += mib_read(mp, 0x64); 1322 p->oversize_received += mib_read(mp, 0x68); 1323 p->jabber_received += mib_read(mp, 0x6c); 1324 p->mac_receive_error += mib_read(mp, 0x70); 1325 p->bad_crc_event += mib_read(mp, 0x74); 1326 p->collision += mib_read(mp, 0x78); 1327 p->late_collision += mib_read(mp, 0x7c); 1328 /* Non MIB hardware counters */ 1329 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT); 1330 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT); 1331 spin_unlock_bh(&mp->mib_counters_lock); 1332} 1333 1334static void mib_counters_timer_wrapper(struct timer_list *t) 1335{ 1336 struct mv643xx_eth_private *mp = timer_container_of(mp, t, 1337 mib_counters_timer); 1338 mib_counters_update(mp); 1339 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); 1340} 1341 1342 1343/* interrupt coalescing *****************************************************/ 1344/* 1345 * Hardware coalescing parameters are set in units of 64 t_clk 1346 * cycles. I.e.: 1347 * 1348 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate 1349 * 1350 * register_value = coal_delay_in_usec * t_clk_rate / 64000000 1351 * 1352 * In the ->set*() methods, we round the computed register value 1353 * to the nearest integer. 1354 */ 1355static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) 1356{ 1357 u32 val = rdlp(mp, SDMA_CONFIG); 1358 u64 temp; 1359 1360 if (mp->shared->extended_rx_coal_limit) 1361 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); 1362 else 1363 temp = (val & 0x003fff00) >> 8; 1364 1365 temp *= 64000000; 1366 temp += mp->t_clk / 2; 1367 do_div(temp, mp->t_clk); 1368 1369 return (unsigned int)temp; 1370} 1371 1372static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1373{ 1374 u64 temp; 1375 u32 val; 1376 1377 temp = (u64)usec * mp->t_clk; 1378 temp += 31999999; 1379 do_div(temp, 64000000); 1380 1381 val = rdlp(mp, SDMA_CONFIG); 1382 if (mp->shared->extended_rx_coal_limit) { 1383 if (temp > 0xffff) 1384 temp = 0xffff; 1385 val &= ~0x023fff80; 1386 val |= (temp & 0x8000) << 10; 1387 val |= (temp & 0x7fff) << 7; 1388 } else { 1389 if (temp > 0x3fff) 1390 temp = 0x3fff; 1391 val &= ~0x003fff00; 1392 val |= (temp & 0x3fff) << 8; 1393 } 1394 wrlp(mp, SDMA_CONFIG, val); 1395} 1396 1397static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) 1398{ 1399 u64 temp; 1400 1401 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; 1402 temp *= 64000000; 1403 temp += mp->t_clk / 2; 1404 do_div(temp, mp->t_clk); 1405 1406 return (unsigned int)temp; 1407} 1408 1409static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1410{ 1411 u64 temp; 1412 1413 temp = (u64)usec * mp->t_clk; 1414 temp += 31999999; 1415 do_div(temp, 64000000); 1416 1417 if (temp > 0x3fff) 1418 temp = 0x3fff; 1419 1420 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); 1421} 1422 1423 1424/* ethtool ******************************************************************/ 1425struct mv643xx_eth_stats { 1426 char stat_string[ETH_GSTRING_LEN]; 1427 int sizeof_stat; 1428 int netdev_off; 1429 int mp_off; 1430}; 1431 1432#define SSTAT(m) \ 1433 { #m, sizeof_field(struct net_device_stats, m), \ 1434 offsetof(struct net_device, stats.m), -1 } 1435 1436#define MIBSTAT(m) \ 1437 { #m, sizeof_field(struct mib_counters, m), \ 1438 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } 1439 1440static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { 1441 SSTAT(rx_packets), 1442 SSTAT(tx_packets), 1443 SSTAT(rx_bytes), 1444 SSTAT(tx_bytes), 1445 SSTAT(rx_errors), 1446 SSTAT(tx_errors), 1447 SSTAT(rx_dropped), 1448 SSTAT(tx_dropped), 1449 MIBSTAT(good_octets_received), 1450 MIBSTAT(bad_octets_received), 1451 MIBSTAT(internal_mac_transmit_err), 1452 MIBSTAT(good_frames_received), 1453 MIBSTAT(bad_frames_received), 1454 MIBSTAT(broadcast_frames_received), 1455 MIBSTAT(multicast_frames_received), 1456 MIBSTAT(frames_64_octets), 1457 MIBSTAT(frames_65_to_127_octets), 1458 MIBSTAT(frames_128_to_255_octets), 1459 MIBSTAT(frames_256_to_511_octets), 1460 MIBSTAT(frames_512_to_1023_octets), 1461 MIBSTAT(frames_1024_to_max_octets), 1462 MIBSTAT(good_octets_sent), 1463 MIBSTAT(good_frames_sent), 1464 MIBSTAT(excessive_collision), 1465 MIBSTAT(multicast_frames_sent), 1466 MIBSTAT(broadcast_frames_sent), 1467 MIBSTAT(unrec_mac_control_received), 1468 MIBSTAT(fc_sent), 1469 MIBSTAT(good_fc_received), 1470 MIBSTAT(bad_fc_received), 1471 MIBSTAT(undersize_received), 1472 MIBSTAT(fragments_received), 1473 MIBSTAT(oversize_received), 1474 MIBSTAT(jabber_received), 1475 MIBSTAT(mac_receive_error), 1476 MIBSTAT(bad_crc_event), 1477 MIBSTAT(collision), 1478 MIBSTAT(late_collision), 1479 MIBSTAT(rx_discard), 1480 MIBSTAT(rx_overrun), 1481}; 1482 1483static int 1484mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp, 1485 struct ethtool_link_ksettings *cmd) 1486{ 1487 struct net_device *dev = mp->dev; 1488 1489 phy_ethtool_ksettings_get(dev->phydev, cmd); 1490 1491 /* 1492 * The MAC does not support 1000baseT_Half. 1493 */ 1494 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1495 cmd->link_modes.supported); 1496 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1497 cmd->link_modes.advertising); 1498 1499 return 0; 1500} 1501 1502static int 1503mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp, 1504 struct ethtool_link_ksettings *cmd) 1505{ 1506 u32 port_status; 1507 u32 supported, advertising; 1508 1509 port_status = rdlp(mp, PORT_STATUS); 1510 1511 supported = SUPPORTED_MII; 1512 advertising = ADVERTISED_MII; 1513 switch (port_status & PORT_SPEED_MASK) { 1514 case PORT_SPEED_10: 1515 cmd->base.speed = SPEED_10; 1516 break; 1517 case PORT_SPEED_100: 1518 cmd->base.speed = SPEED_100; 1519 break; 1520 case PORT_SPEED_1000: 1521 cmd->base.speed = SPEED_1000; 1522 break; 1523 default: 1524 cmd->base.speed = -1; 1525 break; 1526 } 1527 cmd->base.duplex = (port_status & FULL_DUPLEX) ? 1528 DUPLEX_FULL : DUPLEX_HALF; 1529 cmd->base.port = PORT_MII; 1530 cmd->base.phy_address = 0; 1531 cmd->base.autoneg = AUTONEG_DISABLE; 1532 1533 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1534 supported); 1535 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1536 advertising); 1537 1538 return 0; 1539} 1540 1541static void 1542mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1543{ 1544 wol->supported = 0; 1545 wol->wolopts = 0; 1546 if (dev->phydev) 1547 phy_ethtool_get_wol(dev->phydev, wol); 1548} 1549 1550static int 1551mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1552{ 1553 int err; 1554 1555 if (!dev->phydev) 1556 return -EOPNOTSUPP; 1557 1558 err = phy_ethtool_set_wol(dev->phydev, wol); 1559 /* Given that mv643xx_eth works without the marvell-specific PHY driver, 1560 * this debugging hint is useful to have. 1561 */ 1562 if (err == -EOPNOTSUPP) 1563 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n"); 1564 return err; 1565} 1566 1567static int 1568mv643xx_eth_get_link_ksettings(struct net_device *dev, 1569 struct ethtool_link_ksettings *cmd) 1570{ 1571 struct mv643xx_eth_private *mp = netdev_priv(dev); 1572 1573 if (dev->phydev) 1574 return mv643xx_eth_get_link_ksettings_phy(mp, cmd); 1575 else 1576 return mv643xx_eth_get_link_ksettings_phyless(mp, cmd); 1577} 1578 1579static int 1580mv643xx_eth_set_link_ksettings(struct net_device *dev, 1581 const struct ethtool_link_ksettings *cmd) 1582{ 1583 struct ethtool_link_ksettings c = *cmd; 1584 u32 advertising; 1585 int ret; 1586 1587 if (!dev->phydev) 1588 return -EINVAL; 1589 1590 /* 1591 * The MAC does not support 1000baseT_Half. 1592 */ 1593 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1594 c.link_modes.advertising); 1595 advertising &= ~ADVERTISED_1000baseT_Half; 1596 ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising, 1597 advertising); 1598 1599 ret = phy_ethtool_ksettings_set(dev->phydev, &c); 1600 if (!ret) 1601 mv643xx_eth_adjust_link(dev); 1602 return ret; 1603} 1604 1605static void mv643xx_eth_get_drvinfo(struct net_device *dev, 1606 struct ethtool_drvinfo *drvinfo) 1607{ 1608 strscpy(drvinfo->driver, mv643xx_eth_driver_name, 1609 sizeof(drvinfo->driver)); 1610 strscpy(drvinfo->version, mv643xx_eth_driver_version, 1611 sizeof(drvinfo->version)); 1612 strscpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 1613 strscpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info)); 1614} 1615 1616static int mv643xx_eth_get_coalesce(struct net_device *dev, 1617 struct ethtool_coalesce *ec, 1618 struct kernel_ethtool_coalesce *kernel_coal, 1619 struct netlink_ext_ack *extack) 1620{ 1621 struct mv643xx_eth_private *mp = netdev_priv(dev); 1622 1623 ec->rx_coalesce_usecs = get_rx_coal(mp); 1624 ec->tx_coalesce_usecs = get_tx_coal(mp); 1625 1626 return 0; 1627} 1628 1629static int mv643xx_eth_set_coalesce(struct net_device *dev, 1630 struct ethtool_coalesce *ec, 1631 struct kernel_ethtool_coalesce *kernel_coal, 1632 struct netlink_ext_ack *extack) 1633{ 1634 struct mv643xx_eth_private *mp = netdev_priv(dev); 1635 1636 set_rx_coal(mp, ec->rx_coalesce_usecs); 1637 set_tx_coal(mp, ec->tx_coalesce_usecs); 1638 1639 return 0; 1640} 1641 1642static void 1643mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er, 1644 struct kernel_ethtool_ringparam *kernel_er, 1645 struct netlink_ext_ack *extack) 1646{ 1647 struct mv643xx_eth_private *mp = netdev_priv(dev); 1648 1649 er->rx_max_pending = 4096; 1650 er->tx_max_pending = 4096; 1651 1652 er->rx_pending = mp->rx_ring_size; 1653 er->tx_pending = mp->tx_ring_size; 1654} 1655 1656static int 1657mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er, 1658 struct kernel_ethtool_ringparam *kernel_er, 1659 struct netlink_ext_ack *extack) 1660{ 1661 struct mv643xx_eth_private *mp = netdev_priv(dev); 1662 1663 if (er->rx_mini_pending || er->rx_jumbo_pending) 1664 return -EINVAL; 1665 1666 mp->rx_ring_size = min(er->rx_pending, 4096U); 1667 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending, 1668 MV643XX_MAX_SKB_DESCS * 2, 4096); 1669 if (mp->tx_ring_size != er->tx_pending) 1670 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 1671 mp->tx_ring_size, er->tx_pending); 1672 1673 if (netif_running(dev)) { 1674 mv643xx_eth_stop(dev); 1675 if (mv643xx_eth_open(dev)) { 1676 netdev_err(dev, 1677 "fatal error on re-opening device after ring param change\n"); 1678 return -ENOMEM; 1679 } 1680 } 1681 1682 return 0; 1683} 1684 1685 1686static int 1687mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features) 1688{ 1689 struct mv643xx_eth_private *mp = netdev_priv(dev); 1690 bool rx_csum = features & NETIF_F_RXCSUM; 1691 1692 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); 1693 1694 return 0; 1695} 1696 1697static void mv643xx_eth_get_strings(struct net_device *dev, 1698 uint32_t stringset, uint8_t *data) 1699{ 1700 int i; 1701 1702 if (stringset == ETH_SS_STATS) 1703 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) 1704 ethtool_puts(&data, mv643xx_eth_stats[i].stat_string); 1705} 1706 1707static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, 1708 struct ethtool_stats *stats, 1709 uint64_t *data) 1710{ 1711 struct mv643xx_eth_private *mp = netdev_priv(dev); 1712 int i; 1713 1714 mv643xx_eth_get_stats(dev); 1715 mib_counters_update(mp); 1716 1717 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1718 const struct mv643xx_eth_stats *stat; 1719 void *p; 1720 1721 stat = mv643xx_eth_stats + i; 1722 1723 if (stat->netdev_off >= 0) 1724 p = ((void *)mp->dev) + stat->netdev_off; 1725 else 1726 p = ((void *)mp) + stat->mp_off; 1727 1728 data[i] = (stat->sizeof_stat == 8) ? 1729 *(uint64_t *)p : *(uint32_t *)p; 1730 } 1731} 1732 1733static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) 1734{ 1735 if (sset == ETH_SS_STATS) 1736 return ARRAY_SIZE(mv643xx_eth_stats); 1737 1738 return -EOPNOTSUPP; 1739} 1740 1741static const struct ethtool_ops mv643xx_eth_ethtool_ops = { 1742 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 1743 .get_drvinfo = mv643xx_eth_get_drvinfo, 1744 .nway_reset = phy_ethtool_nway_reset, 1745 .get_link = ethtool_op_get_link, 1746 .get_coalesce = mv643xx_eth_get_coalesce, 1747 .set_coalesce = mv643xx_eth_set_coalesce, 1748 .get_ringparam = mv643xx_eth_get_ringparam, 1749 .set_ringparam = mv643xx_eth_set_ringparam, 1750 .get_strings = mv643xx_eth_get_strings, 1751 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, 1752 .get_sset_count = mv643xx_eth_get_sset_count, 1753 .get_ts_info = ethtool_op_get_ts_info, 1754 .get_wol = mv643xx_eth_get_wol, 1755 .set_wol = mv643xx_eth_set_wol, 1756 .get_link_ksettings = mv643xx_eth_get_link_ksettings, 1757 .set_link_ksettings = mv643xx_eth_set_link_ksettings, 1758}; 1759 1760 1761/* address handling *********************************************************/ 1762static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) 1763{ 1764 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); 1765 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); 1766 1767 addr[0] = (mac_h >> 24) & 0xff; 1768 addr[1] = (mac_h >> 16) & 0xff; 1769 addr[2] = (mac_h >> 8) & 0xff; 1770 addr[3] = mac_h & 0xff; 1771 addr[4] = (mac_l >> 8) & 0xff; 1772 addr[5] = mac_l & 0xff; 1773} 1774 1775static void uc_addr_set(struct mv643xx_eth_private *mp, const u8 *addr) 1776{ 1777 wrlp(mp, MAC_ADDR_HIGH, 1778 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); 1779 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); 1780} 1781 1782static u32 uc_addr_filter_mask(struct net_device *dev) 1783{ 1784 struct netdev_hw_addr *ha; 1785 u32 nibbles; 1786 1787 if (dev->flags & IFF_PROMISC) 1788 return 0; 1789 1790 nibbles = 1 << (dev->dev_addr[5] & 0x0f); 1791 netdev_for_each_uc_addr(ha, dev) { 1792 if (memcmp(dev->dev_addr, ha->addr, 5)) 1793 return 0; 1794 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) 1795 return 0; 1796 1797 nibbles |= 1 << (ha->addr[5] & 0x0f); 1798 } 1799 1800 return nibbles; 1801} 1802 1803static void mv643xx_eth_program_unicast_filter(struct net_device *dev) 1804{ 1805 struct mv643xx_eth_private *mp = netdev_priv(dev); 1806 u32 port_config; 1807 u32 nibbles; 1808 int i; 1809 1810 uc_addr_set(mp, dev->dev_addr); 1811 1812 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; 1813 1814 nibbles = uc_addr_filter_mask(dev); 1815 if (!nibbles) { 1816 port_config |= UNICAST_PROMISCUOUS_MODE; 1817 nibbles = 0xffff; 1818 } 1819 1820 for (i = 0; i < 16; i += 4) { 1821 int off = UNICAST_TABLE(mp->port_num) + i; 1822 u32 v; 1823 1824 v = 0; 1825 if (nibbles & 1) 1826 v |= 0x00000001; 1827 if (nibbles & 2) 1828 v |= 0x00000100; 1829 if (nibbles & 4) 1830 v |= 0x00010000; 1831 if (nibbles & 8) 1832 v |= 0x01000000; 1833 nibbles >>= 4; 1834 1835 wrl(mp, off, v); 1836 } 1837 1838 wrlp(mp, PORT_CONFIG, port_config); 1839} 1840 1841static int addr_crc(unsigned char *addr) 1842{ 1843 int crc = 0; 1844 int i; 1845 1846 for (i = 0; i < 6; i++) { 1847 int j; 1848 1849 crc = (crc ^ addr[i]) << 8; 1850 for (j = 7; j >= 0; j--) { 1851 if (crc & (0x100 << j)) 1852 crc ^= 0x107 << j; 1853 } 1854 } 1855 1856 return crc; 1857} 1858 1859static void mv643xx_eth_program_multicast_filter(struct net_device *dev) 1860{ 1861 struct mv643xx_eth_private *mp = netdev_priv(dev); 1862 u32 *mc_spec; 1863 u32 *mc_other; 1864 struct netdev_hw_addr *ha; 1865 int i; 1866 1867 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) 1868 goto promiscuous; 1869 1870 /* Allocate both mc_spec and mc_other tables */ 1871 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC); 1872 if (!mc_spec) 1873 goto promiscuous; 1874 mc_other = &mc_spec[64]; 1875 1876 netdev_for_each_mc_addr(ha, dev) { 1877 u8 *a = ha->addr; 1878 u32 *table; 1879 u8 entry; 1880 1881 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { 1882 table = mc_spec; 1883 entry = a[5]; 1884 } else { 1885 table = mc_other; 1886 entry = addr_crc(a); 1887 } 1888 1889 table[entry >> 2] |= 1 << (8 * (entry & 3)); 1890 } 1891 1892 for (i = 0; i < 64; i++) { 1893 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1894 mc_spec[i]); 1895 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1896 mc_other[i]); 1897 } 1898 1899 kfree(mc_spec); 1900 return; 1901 1902promiscuous: 1903 for (i = 0; i < 64; i++) { 1904 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1905 0x01010101u); 1906 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1907 0x01010101u); 1908 } 1909} 1910 1911static void mv643xx_eth_set_rx_mode(struct net_device *dev) 1912{ 1913 mv643xx_eth_program_unicast_filter(dev); 1914 mv643xx_eth_program_multicast_filter(dev); 1915} 1916 1917static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) 1918{ 1919 struct sockaddr *sa = addr; 1920 1921 if (!is_valid_ether_addr(sa->sa_data)) 1922 return -EADDRNOTAVAIL; 1923 1924 eth_hw_addr_set(dev, sa->sa_data); 1925 1926 netif_addr_lock_bh(dev); 1927 mv643xx_eth_program_unicast_filter(dev); 1928 netif_addr_unlock_bh(dev); 1929 1930 return 0; 1931} 1932 1933 1934/* rx/tx queue initialisation ***********************************************/ 1935static int rxq_init(struct mv643xx_eth_private *mp, int index) 1936{ 1937 struct rx_queue *rxq = mp->rxq + index; 1938 struct rx_desc *rx_desc; 1939 int size; 1940 int i; 1941 1942 rxq->index = index; 1943 1944 rxq->rx_ring_size = mp->rx_ring_size; 1945 1946 rxq->rx_desc_count = 0; 1947 rxq->rx_curr_desc = 0; 1948 rxq->rx_used_desc = 0; 1949 1950 size = rxq->rx_ring_size * sizeof(struct rx_desc); 1951 1952 if (index == 0 && size <= mp->rx_desc_sram_size) { 1953 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, 1954 mp->rx_desc_sram_size); 1955 rxq->rx_desc_dma = mp->rx_desc_sram_addr; 1956 } else { 1957 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 1958 size, &rxq->rx_desc_dma, 1959 GFP_KERNEL); 1960 } 1961 1962 if (rxq->rx_desc_area == NULL) { 1963 netdev_err(mp->dev, 1964 "can't allocate rx ring (%d bytes)\n", size); 1965 goto out; 1966 } 1967 memset(rxq->rx_desc_area, 0, size); 1968 1969 rxq->rx_desc_area_size = size; 1970 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb), 1971 GFP_KERNEL); 1972 if (rxq->rx_skb == NULL) 1973 goto out_free; 1974 1975 rx_desc = rxq->rx_desc_area; 1976 for (i = 0; i < rxq->rx_ring_size; i++) { 1977 int nexti; 1978 1979 nexti = i + 1; 1980 if (nexti == rxq->rx_ring_size) 1981 nexti = 0; 1982 1983 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + 1984 nexti * sizeof(struct rx_desc); 1985 } 1986 1987 return 0; 1988 1989 1990out_free: 1991 if (index == 0 && size <= mp->rx_desc_sram_size) 1992 iounmap(rxq->rx_desc_area); 1993 else 1994 dma_free_coherent(mp->dev->dev.parent, size, 1995 rxq->rx_desc_area, 1996 rxq->rx_desc_dma); 1997 1998out: 1999 return -ENOMEM; 2000} 2001 2002static void rxq_deinit(struct rx_queue *rxq) 2003{ 2004 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 2005 int i; 2006 2007 rxq_disable(rxq); 2008 2009 for (i = 0; i < rxq->rx_ring_size; i++) { 2010 if (rxq->rx_skb[i]) { 2011 dev_consume_skb_any(rxq->rx_skb[i]); 2012 rxq->rx_desc_count--; 2013 } 2014 } 2015 2016 if (rxq->rx_desc_count) { 2017 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n", 2018 rxq->rx_desc_count); 2019 } 2020 2021 if (rxq->index == 0 && 2022 rxq->rx_desc_area_size <= mp->rx_desc_sram_size) 2023 iounmap(rxq->rx_desc_area); 2024 else 2025 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, 2026 rxq->rx_desc_area, rxq->rx_desc_dma); 2027 2028 kfree(rxq->rx_skb); 2029} 2030 2031static int txq_init(struct mv643xx_eth_private *mp, int index) 2032{ 2033 struct tx_queue *txq = mp->txq + index; 2034 struct tx_desc *tx_desc; 2035 int size; 2036 int ret; 2037 int i; 2038 2039 txq->index = index; 2040 2041 txq->tx_ring_size = mp->tx_ring_size; 2042 2043 /* A queue must always have room for at least one skb. 2044 * Therefore, stop the queue when the free entries reaches 2045 * the maximum number of descriptors per skb. 2046 */ 2047 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS; 2048 txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 2049 2050 txq->tx_desc_count = 0; 2051 txq->tx_curr_desc = 0; 2052 txq->tx_used_desc = 0; 2053 2054 size = txq->tx_ring_size * sizeof(struct tx_desc); 2055 2056 if (index == 0 && size <= mp->tx_desc_sram_size) { 2057 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, 2058 mp->tx_desc_sram_size); 2059 txq->tx_desc_dma = mp->tx_desc_sram_addr; 2060 } else { 2061 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 2062 size, &txq->tx_desc_dma, 2063 GFP_KERNEL); 2064 } 2065 2066 if (txq->tx_desc_area == NULL) { 2067 netdev_err(mp->dev, 2068 "can't allocate tx ring (%d bytes)\n", size); 2069 return -ENOMEM; 2070 } 2071 memset(txq->tx_desc_area, 0, size); 2072 2073 txq->tx_desc_area_size = size; 2074 2075 tx_desc = txq->tx_desc_area; 2076 for (i = 0; i < txq->tx_ring_size; i++) { 2077 struct tx_desc *txd = tx_desc + i; 2078 int nexti; 2079 2080 nexti = i + 1; 2081 if (nexti == txq->tx_ring_size) 2082 nexti = 0; 2083 2084 txd->cmd_sts = 0; 2085 txd->next_desc_ptr = txq->tx_desc_dma + 2086 nexti * sizeof(struct tx_desc); 2087 } 2088 2089 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char), 2090 GFP_KERNEL); 2091 if (!txq->tx_desc_mapping) { 2092 ret = -ENOMEM; 2093 goto err_free_desc_area; 2094 } 2095 2096 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 2097 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent, 2098 txq->tx_ring_size * TSO_HEADER_SIZE, 2099 &txq->tso_hdrs_dma, GFP_KERNEL); 2100 if (txq->tso_hdrs == NULL) { 2101 ret = -ENOMEM; 2102 goto err_free_desc_mapping; 2103 } 2104 skb_queue_head_init(&txq->tx_skb); 2105 2106 return 0; 2107 2108err_free_desc_mapping: 2109 kfree(txq->tx_desc_mapping); 2110err_free_desc_area: 2111 if (index == 0 && size <= mp->tx_desc_sram_size) 2112 iounmap(txq->tx_desc_area); 2113 else 2114 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2115 txq->tx_desc_area, txq->tx_desc_dma); 2116 return ret; 2117} 2118 2119static void txq_deinit(struct tx_queue *txq) 2120{ 2121 struct mv643xx_eth_private *mp = txq_to_mp(txq); 2122 2123 txq_disable(txq); 2124 txq_reclaim(txq, txq->tx_ring_size, 1); 2125 2126 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); 2127 2128 if (txq->index == 0 && 2129 txq->tx_desc_area_size <= mp->tx_desc_sram_size) 2130 iounmap(txq->tx_desc_area); 2131 else 2132 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2133 txq->tx_desc_area, txq->tx_desc_dma); 2134 kfree(txq->tx_desc_mapping); 2135 2136 if (txq->tso_hdrs) 2137 dma_free_coherent(mp->dev->dev.parent, 2138 txq->tx_ring_size * TSO_HEADER_SIZE, 2139 txq->tso_hdrs, txq->tso_hdrs_dma); 2140} 2141 2142 2143/* netdev ops and related ***************************************************/ 2144static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) 2145{ 2146 u32 int_cause; 2147 u32 int_cause_ext; 2148 2149 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; 2150 if (int_cause == 0) 2151 return 0; 2152 2153 int_cause_ext = 0; 2154 if (int_cause & INT_EXT) { 2155 int_cause &= ~INT_EXT; 2156 int_cause_ext = rdlp(mp, INT_CAUSE_EXT); 2157 } 2158 2159 if (int_cause) { 2160 wrlp(mp, INT_CAUSE, ~int_cause); 2161 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & 2162 ~(rdlp(mp, TXQ_COMMAND) & 0xff); 2163 mp->work_rx |= (int_cause & INT_RX) >> 2; 2164 } 2165 2166 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; 2167 if (int_cause_ext) { 2168 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); 2169 if (int_cause_ext & INT_EXT_LINK_PHY) 2170 mp->work_link = 1; 2171 mp->work_tx |= int_cause_ext & INT_EXT_TX; 2172 } 2173 2174 return 1; 2175} 2176 2177static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) 2178{ 2179 struct net_device *dev = (struct net_device *)dev_id; 2180 struct mv643xx_eth_private *mp = netdev_priv(dev); 2181 2182 if (unlikely(!mv643xx_eth_collect_events(mp))) 2183 return IRQ_NONE; 2184 2185 wrlp(mp, INT_MASK, 0); 2186 napi_schedule(&mp->napi); 2187 2188 return IRQ_HANDLED; 2189} 2190 2191static void handle_link_event(struct mv643xx_eth_private *mp) 2192{ 2193 struct net_device *dev = mp->dev; 2194 u32 port_status; 2195 int speed; 2196 int duplex; 2197 int fc; 2198 2199 port_status = rdlp(mp, PORT_STATUS); 2200 if (!(port_status & LINK_UP)) { 2201 if (netif_carrier_ok(dev)) { 2202 int i; 2203 2204 netdev_info(dev, "link down\n"); 2205 2206 netif_carrier_off(dev); 2207 2208 for (i = 0; i < mp->txq_count; i++) { 2209 struct tx_queue *txq = mp->txq + i; 2210 2211 txq_reclaim(txq, txq->tx_ring_size, 1); 2212 txq_reset_hw_ptr(txq); 2213 } 2214 } 2215 return; 2216 } 2217 2218 switch (port_status & PORT_SPEED_MASK) { 2219 case PORT_SPEED_10: 2220 speed = 10; 2221 break; 2222 case PORT_SPEED_100: 2223 speed = 100; 2224 break; 2225 case PORT_SPEED_1000: 2226 speed = 1000; 2227 break; 2228 default: 2229 speed = -1; 2230 break; 2231 } 2232 duplex = (port_status & FULL_DUPLEX) ? 1 : 0; 2233 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; 2234 2235 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n", 2236 speed, duplex ? "full" : "half", fc ? "en" : "dis"); 2237 2238 if (!netif_carrier_ok(dev)) 2239 netif_carrier_on(dev); 2240} 2241 2242static int mv643xx_eth_poll(struct napi_struct *napi, int budget) 2243{ 2244 struct mv643xx_eth_private *mp; 2245 int work_done; 2246 2247 mp = container_of(napi, struct mv643xx_eth_private, napi); 2248 2249 if (unlikely(mp->oom)) { 2250 mp->oom = 0; 2251 timer_delete(&mp->rx_oom); 2252 } 2253 2254 work_done = 0; 2255 while (work_done < budget) { 2256 u8 queue_mask; 2257 int queue; 2258 int work_tbd; 2259 2260 if (mp->work_link) { 2261 mp->work_link = 0; 2262 handle_link_event(mp); 2263 work_done++; 2264 continue; 2265 } 2266 2267 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; 2268 if (likely(!mp->oom)) 2269 queue_mask |= mp->work_rx_refill; 2270 2271 if (!queue_mask) { 2272 if (mv643xx_eth_collect_events(mp)) 2273 continue; 2274 break; 2275 } 2276 2277 queue = fls(queue_mask) - 1; 2278 queue_mask = 1 << queue; 2279 2280 work_tbd = budget - work_done; 2281 if (work_tbd > 16) 2282 work_tbd = 16; 2283 2284 if (mp->work_tx_end & queue_mask) { 2285 txq_kick(mp->txq + queue); 2286 } else if (mp->work_tx & queue_mask) { 2287 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); 2288 txq_maybe_wake(mp->txq + queue); 2289 } else if (mp->work_rx & queue_mask) { 2290 work_done += rxq_process(mp->rxq + queue, work_tbd); 2291 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { 2292 work_done += rxq_refill(mp->rxq + queue, work_tbd); 2293 } else { 2294 BUG(); 2295 } 2296 } 2297 2298 if (work_done < budget) { 2299 if (mp->oom) 2300 mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); 2301 napi_complete_done(napi, work_done); 2302 wrlp(mp, INT_MASK, mp->int_mask); 2303 } 2304 2305 return work_done; 2306} 2307 2308static inline void oom_timer_wrapper(struct timer_list *t) 2309{ 2310 struct mv643xx_eth_private *mp = timer_container_of(mp, t, rx_oom); 2311 2312 napi_schedule(&mp->napi); 2313} 2314 2315static void port_start(struct mv643xx_eth_private *mp) 2316{ 2317 struct net_device *dev = mp->dev; 2318 u32 pscr; 2319 int i; 2320 2321 /* 2322 * Perform PHY reset, if there is a PHY. 2323 */ 2324 if (dev->phydev) { 2325 struct ethtool_link_ksettings cmd; 2326 2327 mv643xx_eth_get_link_ksettings(dev, &cmd); 2328 phy_init_hw(dev->phydev); 2329 mv643xx_eth_set_link_ksettings( 2330 dev, (const struct ethtool_link_ksettings *)&cmd); 2331 phy_start(dev->phydev); 2332 } 2333 2334 /* 2335 * Configure basic link parameters. 2336 */ 2337 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2338 2339 pscr |= SERIAL_PORT_ENABLE; 2340 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2341 2342 pscr |= DO_NOT_FORCE_LINK_FAIL; 2343 if (!dev->phydev) 2344 pscr |= FORCE_LINK_PASS; 2345 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2346 2347 /* 2348 * Configure TX path and queues. 2349 */ 2350 tx_set_rate(mp, 1000000000, 16777216); 2351 for (i = 0; i < mp->txq_count; i++) { 2352 struct tx_queue *txq = mp->txq + i; 2353 2354 txq_reset_hw_ptr(txq); 2355 txq_set_rate(txq, 1000000000, 16777216); 2356 txq_set_fixed_prio_mode(txq); 2357 } 2358 2359 /* 2360 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast 2361 * frames to RX queue #0, and include the pseudo-header when 2362 * calculating receive checksums. 2363 */ 2364 mv643xx_eth_set_features(mp->dev, mp->dev->features); 2365 2366 /* 2367 * Treat BPDUs as normal multicasts, and disable partition mode. 2368 */ 2369 wrlp(mp, PORT_CONFIG_EXT, 0x00000000); 2370 2371 /* 2372 * Add configured unicast addresses to address filter table. 2373 */ 2374 mv643xx_eth_program_unicast_filter(mp->dev); 2375 2376 /* 2377 * Enable the receive queues. 2378 */ 2379 for (i = 0; i < mp->rxq_count; i++) { 2380 struct rx_queue *rxq = mp->rxq + i; 2381 u32 addr; 2382 2383 addr = (u32)rxq->rx_desc_dma; 2384 addr += rxq->rx_curr_desc * sizeof(struct rx_desc); 2385 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); 2386 2387 rxq_enable(rxq); 2388 } 2389} 2390 2391static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) 2392{ 2393 int skb_size; 2394 2395 /* 2396 * Reserve 2+14 bytes for an ethernet header (the hardware 2397 * automatically prepends 2 bytes of dummy data to each 2398 * received packet), 16 bytes for up to four VLAN tags, and 2399 * 4 bytes for the trailing FCS -- 36 bytes total. 2400 */ 2401 skb_size = mp->dev->mtu + 36; 2402 2403 /* 2404 * Make sure that the skb size is a multiple of 8 bytes, as 2405 * the lower three bits of the receive descriptor's buffer 2406 * size field are ignored by the hardware. 2407 */ 2408 mp->skb_size = (skb_size + 7) & ~7; 2409 2410 /* 2411 * If NET_SKB_PAD is smaller than a cache line, 2412 * netdev_alloc_skb() will cause skb->data to be misaligned 2413 * to a cache line boundary. If this is the case, include 2414 * some extra space to allow re-aligning the data area. 2415 */ 2416 mp->skb_size += SKB_DMA_REALIGN; 2417} 2418 2419static int mv643xx_eth_open(struct net_device *dev) 2420{ 2421 struct mv643xx_eth_private *mp = netdev_priv(dev); 2422 int err; 2423 int i; 2424 2425 wrlp(mp, INT_CAUSE, 0); 2426 wrlp(mp, INT_CAUSE_EXT, 0); 2427 rdlp(mp, INT_CAUSE_EXT); 2428 2429 err = request_irq(dev->irq, mv643xx_eth_irq, 2430 IRQF_SHARED, dev->name, dev); 2431 if (err) { 2432 netdev_err(dev, "can't assign irq\n"); 2433 return -EAGAIN; 2434 } 2435 2436 mv643xx_eth_recalc_skb_size(mp); 2437 2438 napi_enable(&mp->napi); 2439 2440 mp->int_mask = INT_EXT; 2441 2442 for (i = 0; i < mp->rxq_count; i++) { 2443 err = rxq_init(mp, i); 2444 if (err) { 2445 while (--i >= 0) 2446 rxq_deinit(mp->rxq + i); 2447 goto out; 2448 } 2449 2450 rxq_refill(mp->rxq + i, INT_MAX); 2451 mp->int_mask |= INT_RX_0 << i; 2452 } 2453 2454 if (mp->oom) { 2455 mp->rx_oom.expires = jiffies + (HZ / 10); 2456 add_timer(&mp->rx_oom); 2457 } 2458 2459 for (i = 0; i < mp->txq_count; i++) { 2460 err = txq_init(mp, i); 2461 if (err) { 2462 while (--i >= 0) 2463 txq_deinit(mp->txq + i); 2464 goto out_free; 2465 } 2466 mp->int_mask |= INT_TX_END_0 << i; 2467 } 2468 2469 add_timer(&mp->mib_counters_timer); 2470 port_start(mp); 2471 2472 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); 2473 wrlp(mp, INT_MASK, mp->int_mask); 2474 2475 return 0; 2476 2477 2478out_free: 2479 for (i = 0; i < mp->rxq_count; i++) 2480 rxq_deinit(mp->rxq + i); 2481out: 2482 napi_disable(&mp->napi); 2483 free_irq(dev->irq, dev); 2484 2485 return err; 2486} 2487 2488static void port_reset(struct mv643xx_eth_private *mp) 2489{ 2490 unsigned int data; 2491 int i; 2492 2493 for (i = 0; i < mp->rxq_count; i++) 2494 rxq_disable(mp->rxq + i); 2495 for (i = 0; i < mp->txq_count; i++) 2496 txq_disable(mp->txq + i); 2497 2498 while (1) { 2499 u32 ps = rdlp(mp, PORT_STATUS); 2500 2501 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) 2502 break; 2503 udelay(10); 2504 } 2505 2506 /* Reset the Enable bit in the Configuration Register */ 2507 data = rdlp(mp, PORT_SERIAL_CONTROL); 2508 data &= ~(SERIAL_PORT_ENABLE | 2509 DO_NOT_FORCE_LINK_FAIL | 2510 FORCE_LINK_PASS); 2511 wrlp(mp, PORT_SERIAL_CONTROL, data); 2512} 2513 2514static int mv643xx_eth_stop(struct net_device *dev) 2515{ 2516 struct mv643xx_eth_private *mp = netdev_priv(dev); 2517 int i; 2518 2519 wrlp(mp, INT_MASK_EXT, 0x00000000); 2520 wrlp(mp, INT_MASK, 0x00000000); 2521 rdlp(mp, INT_MASK); 2522 2523 napi_disable(&mp->napi); 2524 2525 timer_delete_sync(&mp->rx_oom); 2526 2527 netif_carrier_off(dev); 2528 if (dev->phydev) 2529 phy_stop(dev->phydev); 2530 free_irq(dev->irq, dev); 2531 2532 port_reset(mp); 2533 mv643xx_eth_get_stats(dev); 2534 mib_counters_update(mp); 2535 timer_delete_sync(&mp->mib_counters_timer); 2536 2537 for (i = 0; i < mp->rxq_count; i++) 2538 rxq_deinit(mp->rxq + i); 2539 for (i = 0; i < mp->txq_count; i++) 2540 txq_deinit(mp->txq + i); 2541 2542 return 0; 2543} 2544 2545static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2546{ 2547 int ret; 2548 2549 if (!dev->phydev) 2550 return -ENOTSUPP; 2551 2552 ret = phy_mii_ioctl(dev->phydev, ifr, cmd); 2553 if (!ret) 2554 mv643xx_eth_adjust_link(dev); 2555 return ret; 2556} 2557 2558static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) 2559{ 2560 struct mv643xx_eth_private *mp = netdev_priv(dev); 2561 2562 WRITE_ONCE(dev->mtu, new_mtu); 2563 mv643xx_eth_recalc_skb_size(mp); 2564 tx_set_rate(mp, 1000000000, 16777216); 2565 2566 if (!netif_running(dev)) 2567 return 0; 2568 2569 /* 2570 * Stop and then re-open the interface. This will allocate RX 2571 * skbs of the new MTU. 2572 * There is a possible danger that the open will not succeed, 2573 * due to memory being full. 2574 */ 2575 mv643xx_eth_stop(dev); 2576 if (mv643xx_eth_open(dev)) { 2577 netdev_err(dev, 2578 "fatal error on re-opening device after MTU change\n"); 2579 } 2580 2581 return 0; 2582} 2583 2584static void tx_timeout_task(struct work_struct *ugly) 2585{ 2586 struct mv643xx_eth_private *mp; 2587 2588 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); 2589 if (netif_running(mp->dev)) { 2590 netif_tx_stop_all_queues(mp->dev); 2591 port_reset(mp); 2592 port_start(mp); 2593 netif_tx_wake_all_queues(mp->dev); 2594 } 2595} 2596 2597static void mv643xx_eth_tx_timeout(struct net_device *dev, unsigned int txqueue) 2598{ 2599 struct mv643xx_eth_private *mp = netdev_priv(dev); 2600 2601 netdev_info(dev, "tx timeout\n"); 2602 2603 schedule_work(&mp->tx_timeout_task); 2604} 2605 2606#ifdef CONFIG_NET_POLL_CONTROLLER 2607static void mv643xx_eth_netpoll(struct net_device *dev) 2608{ 2609 struct mv643xx_eth_private *mp = netdev_priv(dev); 2610 2611 wrlp(mp, INT_MASK, 0x00000000); 2612 rdlp(mp, INT_MASK); 2613 2614 mv643xx_eth_irq(dev->irq, dev); 2615 2616 wrlp(mp, INT_MASK, mp->int_mask); 2617} 2618#endif 2619 2620 2621/* platform glue ************************************************************/ 2622static void 2623mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, 2624 const struct mbus_dram_target_info *dram) 2625{ 2626 void __iomem *base = msp->base; 2627 u32 win_enable; 2628 u32 win_protect; 2629 int i; 2630 2631 for (i = 0; i < 6; i++) { 2632 writel(0, base + WINDOW_BASE(i)); 2633 writel(0, base + WINDOW_SIZE(i)); 2634 if (i < 4) 2635 writel(0, base + WINDOW_REMAP_HIGH(i)); 2636 } 2637 2638 win_enable = 0x3f; 2639 win_protect = 0; 2640 2641 for (i = 0; i < dram->num_cs; i++) { 2642 const struct mbus_dram_window *cs = dram->cs + i; 2643 2644 writel((cs->base & 0xffff0000) | 2645 (cs->mbus_attr << 8) | 2646 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 2647 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 2648 2649 win_enable &= ~(1 << i); 2650 win_protect |= 3 << (2 * i); 2651 } 2652 2653 writel(win_enable, base + WINDOW_BAR_ENABLE); 2654 msp->win_protect = win_protect; 2655} 2656 2657static void infer_hw_params(struct mv643xx_eth_shared_private *msp) 2658{ 2659 /* 2660 * Check whether we have a 14-bit coal limit field in bits 2661 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the 2662 * SDMA config register. 2663 */ 2664 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); 2665 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) 2666 msp->extended_rx_coal_limit = 1; 2667 else 2668 msp->extended_rx_coal_limit = 0; 2669 2670 /* 2671 * Check whether the MAC supports TX rate control, and if 2672 * yes, whether its associated registers are in the old or 2673 * the new place. 2674 */ 2675 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); 2676 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { 2677 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; 2678 } else { 2679 writel(7, msp->base + 0x0400 + TX_BW_RATE); 2680 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) 2681 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; 2682 else 2683 msp->tx_bw_control = TX_BW_CONTROL_ABSENT; 2684 } 2685} 2686 2687#if defined(CONFIG_OF) 2688static const struct of_device_id mv643xx_eth_shared_ids[] = { 2689 { .compatible = "marvell,orion-eth", }, 2690 { .compatible = "marvell,kirkwood-eth", }, 2691 { } 2692}; 2693MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids); 2694#endif 2695 2696#ifdef CONFIG_OF_IRQ 2697#define mv643xx_eth_property(_np, _name, _v) \ 2698 do { \ 2699 u32 tmp; \ 2700 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \ 2701 _v = tmp; \ 2702 } while (0) 2703 2704static struct platform_device *port_platdev[3]; 2705 2706static void mv643xx_eth_shared_of_remove(void) 2707{ 2708 struct mv643xx_eth_platform_data *pd; 2709 int n; 2710 2711 for (n = 0; n < 3; n++) { 2712 if (!port_platdev[n]) 2713 continue; 2714 pd = dev_get_platdata(&port_platdev[n]->dev); 2715 if (pd) 2716 of_node_put(pd->phy_node); 2717 platform_device_del(port_platdev[n]); 2718 port_platdev[n] = NULL; 2719 } 2720} 2721 2722static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev, 2723 struct device_node *pnp) 2724{ 2725 struct platform_device *ppdev; 2726 struct mv643xx_eth_platform_data ppd; 2727 struct resource res; 2728 int ret; 2729 int dev_num = 0; 2730 2731 memset(&ppd, 0, sizeof(ppd)); 2732 ppd.shared = pdev; 2733 2734 memset(&res, 0, sizeof(res)); 2735 if (of_irq_to_resource(pnp, 0, &res) <= 0) { 2736 dev_err(&pdev->dev, "missing interrupt on %pOFn\n", pnp); 2737 return -EINVAL; 2738 } 2739 2740 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) { 2741 dev_err(&pdev->dev, "missing reg property on %pOFn\n", pnp); 2742 return -EINVAL; 2743 } 2744 2745 if (ppd.port_number >= 3) { 2746 dev_err(&pdev->dev, "invalid reg property on %pOFn\n", pnp); 2747 return -EINVAL; 2748 } 2749 2750 while (dev_num < 3 && port_platdev[dev_num]) 2751 dev_num++; 2752 2753 if (dev_num == 3) { 2754 dev_err(&pdev->dev, "too many ports registered\n"); 2755 return -EINVAL; 2756 } 2757 2758 ret = of_get_mac_address(pnp, ppd.mac_addr); 2759 if (ret == -EPROBE_DEFER) 2760 return ret; 2761 2762 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size); 2763 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr); 2764 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size); 2765 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size); 2766 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr); 2767 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size); 2768 2769 of_get_phy_mode(pnp, &ppd.interface); 2770 2771 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0); 2772 if (!ppd.phy_node) { 2773 ppd.phy_addr = MV643XX_ETH_PHY_NONE; 2774 of_property_read_u32(pnp, "speed", &ppd.speed); 2775 of_property_read_u32(pnp, "duplex", &ppd.duplex); 2776 } 2777 2778 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num); 2779 if (!ppdev) { 2780 ret = -ENOMEM; 2781 goto put_err; 2782 } 2783 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 2784 ppdev->dev.of_node = pnp; 2785 2786 ret = platform_device_add_resources(ppdev, &res, 1); 2787 if (ret) 2788 goto port_err; 2789 2790 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 2791 if (ret) 2792 goto port_err; 2793 2794 ret = platform_device_add(ppdev); 2795 if (ret) 2796 goto port_err; 2797 2798 port_platdev[dev_num] = ppdev; 2799 2800 return 0; 2801 2802port_err: 2803 platform_device_put(ppdev); 2804put_err: 2805 of_node_put(ppd.phy_node); 2806 return ret; 2807} 2808 2809static int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2810{ 2811 struct mv643xx_eth_shared_platform_data *pd; 2812 struct device_node *np = pdev->dev.of_node; 2813 int ret; 2814 2815 /* bail out if not registered from DT */ 2816 if (!np) 2817 return 0; 2818 2819 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); 2820 if (!pd) 2821 return -ENOMEM; 2822 pdev->dev.platform_data = pd; 2823 2824 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit); 2825 2826 for_each_available_child_of_node_scoped(np, pnp) { 2827 ret = mv643xx_eth_shared_of_add_port(pdev, pnp); 2828 if (ret) { 2829 mv643xx_eth_shared_of_remove(); 2830 return ret; 2831 } 2832 } 2833 return 0; 2834} 2835 2836#else 2837static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2838{ 2839 return 0; 2840} 2841 2842static inline void mv643xx_eth_shared_of_remove(void) 2843{ 2844} 2845#endif 2846 2847static int mv643xx_eth_shared_probe(struct platform_device *pdev) 2848{ 2849 static int mv643xx_eth_version_printed; 2850 struct mv643xx_eth_shared_platform_data *pd; 2851 struct mv643xx_eth_shared_private *msp; 2852 const struct mbus_dram_target_info *dram; 2853 int ret; 2854 2855 if (!mv643xx_eth_version_printed++) 2856 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n", 2857 mv643xx_eth_driver_version); 2858 2859 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL); 2860 if (msp == NULL) 2861 return -ENOMEM; 2862 platform_set_drvdata(pdev, msp); 2863 2864 msp->base = devm_platform_ioremap_resource(pdev, 0); 2865 if (IS_ERR(msp->base)) 2866 return PTR_ERR(msp->base); 2867 2868 msp->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 2869 if (IS_ERR(msp->clk)) 2870 return PTR_ERR(msp->clk); 2871 2872 /* 2873 * (Re-)program MBUS remapping windows if we are asked to. 2874 */ 2875 dram = mv_mbus_dram_info(); 2876 if (dram) 2877 mv643xx_eth_conf_mbus_windows(msp, dram); 2878 2879 ret = mv643xx_eth_shared_of_probe(pdev); 2880 if (ret) 2881 return ret; 2882 pd = dev_get_platdata(&pdev->dev); 2883 2884 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ? 2885 pd->tx_csum_limit : 9 * 1024; 2886 infer_hw_params(msp); 2887 2888 return 0; 2889} 2890 2891static void mv643xx_eth_shared_remove(struct platform_device *pdev) 2892{ 2893 mv643xx_eth_shared_of_remove(); 2894} 2895 2896static struct platform_driver mv643xx_eth_shared_driver = { 2897 .probe = mv643xx_eth_shared_probe, 2898 .remove = mv643xx_eth_shared_remove, 2899 .driver = { 2900 .name = MV643XX_ETH_SHARED_NAME, 2901 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids), 2902 }, 2903}; 2904 2905static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) 2906{ 2907 int addr_shift = 5 * mp->port_num; 2908 u32 data; 2909 2910 data = rdl(mp, PHY_ADDR); 2911 data &= ~(0x1f << addr_shift); 2912 data |= (phy_addr & 0x1f) << addr_shift; 2913 wrl(mp, PHY_ADDR, data); 2914} 2915 2916static int phy_addr_get(struct mv643xx_eth_private *mp) 2917{ 2918 unsigned int data; 2919 2920 data = rdl(mp, PHY_ADDR); 2921 2922 return (data >> (5 * mp->port_num)) & 0x1f; 2923} 2924 2925static void set_params(struct mv643xx_eth_private *mp, 2926 struct mv643xx_eth_platform_data *pd) 2927{ 2928 struct net_device *dev = mp->dev; 2929 unsigned int tx_ring_size; 2930 2931 if (is_valid_ether_addr(pd->mac_addr)) { 2932 eth_hw_addr_set(dev, pd->mac_addr); 2933 } else { 2934 u8 addr[ETH_ALEN]; 2935 2936 uc_addr_get(mp, addr); 2937 eth_hw_addr_set(dev, addr); 2938 } 2939 2940 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; 2941 if (pd->rx_queue_size) 2942 mp->rx_ring_size = pd->rx_queue_size; 2943 mp->rx_desc_sram_addr = pd->rx_sram_addr; 2944 mp->rx_desc_sram_size = pd->rx_sram_size; 2945 2946 mp->rxq_count = pd->rx_queue_count ? : 1; 2947 2948 tx_ring_size = DEFAULT_TX_QUEUE_SIZE; 2949 if (pd->tx_queue_size) 2950 tx_ring_size = pd->tx_queue_size; 2951 2952 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size, 2953 MV643XX_MAX_SKB_DESCS * 2, 4096); 2954 if (mp->tx_ring_size != tx_ring_size) 2955 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 2956 mp->tx_ring_size, tx_ring_size); 2957 2958 mp->tx_desc_sram_addr = pd->tx_sram_addr; 2959 mp->tx_desc_sram_size = pd->tx_sram_size; 2960 2961 mp->txq_count = pd->tx_queue_count ? : 1; 2962} 2963 2964static int get_phy_mode(struct mv643xx_eth_private *mp) 2965{ 2966 struct device *dev = mp->dev->dev.parent; 2967 phy_interface_t iface; 2968 int err; 2969 2970 if (dev->of_node) 2971 err = of_get_phy_mode(dev->of_node, &iface); 2972 2973 /* Historical default if unspecified. We could also read/write 2974 * the interface state in the PSC1 2975 */ 2976 if (!dev->of_node || err) 2977 iface = PHY_INTERFACE_MODE_GMII; 2978 return iface; 2979} 2980 2981static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, 2982 int phy_addr) 2983{ 2984 struct phy_device *phydev; 2985 int start; 2986 int num; 2987 int i; 2988 char phy_id[MII_BUS_ID_SIZE + 3]; 2989 2990 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { 2991 start = phy_addr_get(mp) & 0x1f; 2992 num = 32; 2993 } else { 2994 start = phy_addr & 0x1f; 2995 num = 1; 2996 } 2997 2998 /* Attempt to connect to the PHY using orion-mdio */ 2999 phydev = ERR_PTR(-ENODEV); 3000 for (i = 0; i < num; i++) { 3001 int addr = (start + i) & 0x1f; 3002 3003 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 3004 "orion-mdio-mii", addr); 3005 3006 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link, 3007 get_phy_mode(mp)); 3008 if (!IS_ERR(phydev)) { 3009 phy_addr_set(mp, addr); 3010 break; 3011 } 3012 } 3013 3014 return phydev; 3015} 3016 3017static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) 3018{ 3019 struct net_device *dev = mp->dev; 3020 struct phy_device *phy = dev->phydev; 3021 3022 if (speed == 0) { 3023 phy->autoneg = AUTONEG_ENABLE; 3024 phy->speed = 0; 3025 phy->duplex = 0; 3026 linkmode_copy(phy->advertising, phy->supported); 3027 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3028 phy->advertising); 3029 } else { 3030 phy->autoneg = AUTONEG_DISABLE; 3031 linkmode_zero(phy->advertising); 3032 phy->speed = speed; 3033 phy->duplex = duplex; 3034 } 3035 phy_start_aneg(phy); 3036} 3037 3038static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) 3039{ 3040 struct net_device *dev = mp->dev; 3041 u32 pscr; 3042 3043 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 3044 if (pscr & SERIAL_PORT_ENABLE) { 3045 pscr &= ~SERIAL_PORT_ENABLE; 3046 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 3047 } 3048 3049 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; 3050 if (!dev->phydev) { 3051 pscr |= DISABLE_AUTO_NEG_SPEED_GMII; 3052 if (speed == SPEED_1000) 3053 pscr |= SET_GMII_SPEED_TO_1000; 3054 else if (speed == SPEED_100) 3055 pscr |= SET_MII_SPEED_TO_100; 3056 3057 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; 3058 3059 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; 3060 if (duplex == DUPLEX_FULL) 3061 pscr |= SET_FULL_DUPLEX_MODE; 3062 } 3063 3064 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 3065} 3066 3067static const struct net_device_ops mv643xx_eth_netdev_ops = { 3068 .ndo_open = mv643xx_eth_open, 3069 .ndo_stop = mv643xx_eth_stop, 3070 .ndo_start_xmit = mv643xx_eth_xmit, 3071 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, 3072 .ndo_set_mac_address = mv643xx_eth_set_mac_address, 3073 .ndo_validate_addr = eth_validate_addr, 3074 .ndo_eth_ioctl = mv643xx_eth_ioctl, 3075 .ndo_change_mtu = mv643xx_eth_change_mtu, 3076 .ndo_set_features = mv643xx_eth_set_features, 3077 .ndo_tx_timeout = mv643xx_eth_tx_timeout, 3078 .ndo_get_stats = mv643xx_eth_get_stats, 3079#ifdef CONFIG_NET_POLL_CONTROLLER 3080 .ndo_poll_controller = mv643xx_eth_netpoll, 3081#endif 3082}; 3083 3084static int mv643xx_eth_probe(struct platform_device *pdev) 3085{ 3086 struct mv643xx_eth_platform_data *pd; 3087 struct mv643xx_eth_private *mp; 3088 struct net_device *dev; 3089 struct phy_device *phydev = NULL; 3090 u32 psc1r; 3091 int err, irq; 3092 3093 pd = dev_get_platdata(&pdev->dev); 3094 if (pd == NULL) { 3095 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n"); 3096 return -ENODEV; 3097 } 3098 3099 if (pd->shared == NULL) { 3100 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n"); 3101 return -ENODEV; 3102 } 3103 3104 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); 3105 if (!dev) 3106 return -ENOMEM; 3107 3108 SET_NETDEV_DEV(dev, &pdev->dev); 3109 mp = netdev_priv(dev); 3110 platform_set_drvdata(pdev, mp); 3111 3112 mp->shared = platform_get_drvdata(pd->shared); 3113 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); 3114 mp->port_num = pd->port_number; 3115 3116 mp->dev = dev; 3117 3118 if (of_device_is_compatible(pdev->dev.of_node, 3119 "marvell,kirkwood-eth-port")) { 3120 psc1r = rdlp(mp, PORT_SERIAL_CONTROL1); 3121 3122 /* Kirkwood resets some registers on gated clocks. Especially 3123 * CLK125_BYPASS_EN must be cleared but is not available on 3124 * all other SoCs/System Controllers using this driver. 3125 */ 3126 psc1r &= ~CLK125_BYPASS_EN; 3127 3128 /* On Kirkwood with two Ethernet controllers, if both of them 3129 * have RGMII_EN disabled, the first controller will be in GMII 3130 * mode and the second one is effectively disabled, instead of 3131 * two MII interfaces. 3132 * 3133 * To enable GMII in the first controller, the second one must 3134 * also be configured (and may be enabled) with RGMII_EN 3135 * disabled too, even though it cannot be used at all. 3136 */ 3137 switch (pd->interface) { 3138 /* Use internal to denote second controller being disabled */ 3139 case PHY_INTERFACE_MODE_INTERNAL: 3140 case PHY_INTERFACE_MODE_MII: 3141 case PHY_INTERFACE_MODE_GMII: 3142 psc1r &= ~RGMII_EN; 3143 break; 3144 case PHY_INTERFACE_MODE_RGMII: 3145 case PHY_INTERFACE_MODE_RGMII_ID: 3146 case PHY_INTERFACE_MODE_RGMII_RXID: 3147 case PHY_INTERFACE_MODE_RGMII_TXID: 3148 psc1r |= RGMII_EN; 3149 break; 3150 default: 3151 /* Unknown; don't touch */ 3152 break; 3153 } 3154 3155 wrlp(mp, PORT_SERIAL_CONTROL1, psc1r); 3156 } 3157 3158 /* 3159 * Start with a default rate, and if there is a clock, allow 3160 * it to override the default. 3161 */ 3162 mp->t_clk = 133000000; 3163 mp->clk = devm_clk_get(&pdev->dev, NULL); 3164 if (!IS_ERR(mp->clk)) { 3165 clk_prepare_enable(mp->clk); 3166 mp->t_clk = clk_get_rate(mp->clk); 3167 } else if (!IS_ERR(mp->shared->clk)) { 3168 mp->t_clk = clk_get_rate(mp->shared->clk); 3169 } 3170 3171 set_params(mp, pd); 3172 netif_set_real_num_tx_queues(dev, mp->txq_count); 3173 netif_set_real_num_rx_queues(dev, mp->rxq_count); 3174 3175 err = 0; 3176 if (pd->phy_node) { 3177 phydev = of_phy_connect(mp->dev, pd->phy_node, 3178 mv643xx_eth_adjust_link, 0, 3179 get_phy_mode(mp)); 3180 if (!phydev) 3181 err = -ENODEV; 3182 else 3183 phy_addr_set(mp, phydev->mdio.addr); 3184 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) { 3185 phydev = phy_scan(mp, pd->phy_addr); 3186 3187 if (IS_ERR(phydev)) 3188 err = PTR_ERR(phydev); 3189 else 3190 phy_init(mp, pd->speed, pd->duplex); 3191 } 3192 if (err == -ENODEV) { 3193 err = -EPROBE_DEFER; 3194 goto out; 3195 } 3196 if (err) 3197 goto out; 3198 3199 dev->ethtool_ops = &mv643xx_eth_ethtool_ops; 3200 3201 init_pscr(mp, pd->speed, pd->duplex); 3202 3203 3204 mib_counters_clear(mp); 3205 3206 timer_setup(&mp->mib_counters_timer, mib_counters_timer_wrapper, 0); 3207 mp->mib_counters_timer.expires = jiffies + 30 * HZ; 3208 3209 spin_lock_init(&mp->mib_counters_lock); 3210 3211 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); 3212 3213 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll); 3214 3215 timer_setup(&mp->rx_oom, oom_timer_wrapper, 0); 3216 3217 3218 irq = platform_get_irq(pdev, 0); 3219 if (WARN_ON(irq < 0)) { 3220 err = irq; 3221 goto out; 3222 } 3223 dev->irq = irq; 3224 3225 dev->netdev_ops = &mv643xx_eth_netdev_ops; 3226 3227 dev->watchdog_timeo = 2 * HZ; 3228 dev->base_addr = 0; 3229 3230 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 3231 dev->vlan_features = dev->features; 3232 3233 dev->features |= NETIF_F_RXCSUM; 3234 dev->hw_features = dev->features; 3235 3236 dev->priv_flags |= IFF_UNICAST_FLT; 3237 netif_set_tso_max_segs(dev, MV643XX_MAX_TSO_SEGS); 3238 3239 /* MTU range: 64 - 9500 */ 3240 dev->min_mtu = 64; 3241 dev->max_mtu = 9500; 3242 3243 if (mp->shared->win_protect) 3244 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); 3245 3246 netif_carrier_off(dev); 3247 3248 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); 3249 3250 set_rx_coal(mp, 250); 3251 set_tx_coal(mp, 0); 3252 3253 err = register_netdev(dev); 3254 if (err) 3255 goto out; 3256 3257 netdev_notice(dev, "port %d with MAC address %pM\n", 3258 mp->port_num, dev->dev_addr); 3259 3260 if (mp->tx_desc_sram_size > 0) 3261 netdev_notice(dev, "configured with sram\n"); 3262 3263 return 0; 3264 3265out: 3266 if (!IS_ERR(mp->clk)) 3267 clk_disable_unprepare(mp->clk); 3268 free_netdev(dev); 3269 3270 return err; 3271} 3272 3273static void mv643xx_eth_remove(struct platform_device *pdev) 3274{ 3275 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3276 struct net_device *dev = mp->dev; 3277 3278 unregister_netdev(mp->dev); 3279 if (dev->phydev) 3280 phy_disconnect(dev->phydev); 3281 cancel_work_sync(&mp->tx_timeout_task); 3282 3283 if (!IS_ERR(mp->clk)) 3284 clk_disable_unprepare(mp->clk); 3285 3286 free_netdev(mp->dev); 3287} 3288 3289static void mv643xx_eth_shutdown(struct platform_device *pdev) 3290{ 3291 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3292 3293 /* Mask all interrupts on ethernet port */ 3294 wrlp(mp, INT_MASK, 0); 3295 rdlp(mp, INT_MASK); 3296 3297 if (netif_running(mp->dev)) 3298 port_reset(mp); 3299} 3300 3301static struct platform_driver mv643xx_eth_driver = { 3302 .probe = mv643xx_eth_probe, 3303 .remove = mv643xx_eth_remove, 3304 .shutdown = mv643xx_eth_shutdown, 3305 .driver = { 3306 .name = MV643XX_ETH_NAME, 3307 }, 3308}; 3309 3310static struct platform_driver * const drivers[] = { 3311 &mv643xx_eth_shared_driver, 3312 &mv643xx_eth_driver, 3313}; 3314 3315static int __init mv643xx_eth_init_module(void) 3316{ 3317 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 3318} 3319module_init(mv643xx_eth_init_module); 3320 3321static void __exit mv643xx_eth_cleanup_module(void) 3322{ 3323 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 3324} 3325module_exit(mv643xx_eth_cleanup_module); 3326 3327MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " 3328 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); 3329MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 3330MODULE_LICENSE("GPL"); 3331MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); 3332MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
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