ixgbevf.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright(c) 1999 - 2024 Intel Corporation. */
  3
  4#ifndef _IXGBEVF_H_
  5#define _IXGBEVF_H_
  6
  7#include <linux/types.h>
  8#include <linux/bitops.h>
  9#include <linux/timer.h>
 10#include <linux/io.h>
 11#include <linux/netdevice.h>
 12#include <linux/if_vlan.h>
 13#include <linux/u64_stats_sync.h>
 14#include <net/xdp.h>
 15
 16#include "vf.h"
 17#include "ipsec.h"
 18
 19#define IXGBE_MAX_TXD_PWR	14
 20#define IXGBE_MAX_DATA_PER_TXD	BIT(IXGBE_MAX_TXD_PWR)
 21
 22/* Tx Descriptors needed, worst case */
 23#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
 24#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
 25
 26/* wrapper around a pointer to a socket buffer,
 27 * so a DMA handle can be stored along with the buffer
 28 */
 29struct ixgbevf_tx_buffer {
 30	union ixgbe_adv_tx_desc *next_to_watch;
 31	unsigned long time_stamp;
 32	union {
 33		struct sk_buff *skb;
 34		/* XDP uses address ptr on irq_clean */
 35		void *data;
 36	};
 37	unsigned int bytecount;
 38	unsigned short gso_segs;
 39	__be16 protocol;
 40	DEFINE_DMA_UNMAP_ADDR(dma);
 41	DEFINE_DMA_UNMAP_LEN(len);
 42	u32 tx_flags;
 43};
 44
 45struct ixgbevf_rx_buffer {
 46	dma_addr_t dma;
 47	struct page *page;
 48#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
 49	__u32 page_offset;
 50#else
 51	__u16 page_offset;
 52#endif
 53	__u16 pagecnt_bias;
 54};
 55
 56struct ixgbevf_stats {
 57	u64 packets;
 58	u64 bytes;
 59};
 60
 61struct ixgbevf_tx_queue_stats {
 62	u64 restart_queue;
 63	u64 tx_busy;
 64	u64 tx_done_old;
 65};
 66
 67struct ixgbevf_rx_queue_stats {
 68	u64 alloc_rx_page_failed;
 69	u64 alloc_rx_buff_failed;
 70	u64 alloc_rx_page;
 71	u64 csum_err;
 72};
 73
 74enum ixgbevf_ring_state_t {
 75	__IXGBEVF_RX_3K_BUFFER,
 76	__IXGBEVF_RX_BUILD_SKB_ENABLED,
 77	__IXGBEVF_TX_DETECT_HANG,
 78	__IXGBEVF_HANG_CHECK_ARMED,
 79	__IXGBEVF_TX_XDP_RING,
 80	__IXGBEVF_TX_XDP_RING_PRIMED,
 81};
 82
 83#define ring_is_xdp(ring) \
 84		test_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state)
 85#define set_ring_xdp(ring) \
 86		set_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state)
 87#define clear_ring_xdp(ring) \
 88		clear_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state)
 89
 90struct ixgbevf_ring {
 91	struct ixgbevf_ring *next;
 92	struct ixgbevf_q_vector *q_vector;	/* backpointer to q_vector */
 93	struct net_device *netdev;
 94	struct bpf_prog *xdp_prog;
 95	struct device *dev;
 96	void *desc;			/* descriptor ring memory */
 97	dma_addr_t dma;			/* phys. address of descriptor ring */
 98	unsigned int size;		/* length in bytes */
 99	u16 count;			/* amount of descriptors */
100	u16 next_to_use;
101	u16 next_to_clean;
102	u16 next_to_alloc;
103
104	union {
105		struct ixgbevf_tx_buffer *tx_buffer_info;
106		struct ixgbevf_rx_buffer *rx_buffer_info;
107	};
108	unsigned long state;
109	struct ixgbevf_stats stats;
110	struct u64_stats_sync syncp;
111	union {
112		struct ixgbevf_tx_queue_stats tx_stats;
113		struct ixgbevf_rx_queue_stats rx_stats;
114	};
115	struct xdp_rxq_info xdp_rxq;
116	u64 hw_csum_rx_error;
117	u8 __iomem *tail;
118	struct sk_buff *skb;
119
120	/* holds the special value that gets the hardware register offset
121	 * associated with this ring, which is different for DCB and RSS modes
122	 */
123	u16 reg_idx;
124	int queue_index; /* needed for multiqueue queue management */
125} ____cacheline_internodealigned_in_smp;
126
127/* How many Rx Buffers do we bundle into one write to the hardware ? */
128#define IXGBEVF_RX_BUFFER_WRITE	16	/* Must be power of 2 */
129
130#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
131#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
132#define MAX_XDP_QUEUES IXGBE_VF_MAX_TX_QUEUES
133#define IXGBEVF_MAX_RSS_QUEUES		2
134#define IXGBEVF_82599_RETA_SIZE		128	/* 128 entries */
135#define IXGBEVF_X550_VFRETA_SIZE	64	/* 64 entries */
136#define IXGBEVF_RSS_HASH_KEY_SIZE	40
137#define IXGBEVF_VFRSSRK_REGS		10	/* 10 registers for RSS key */
138
139#define IXGBEVF_DEFAULT_TXD	1024
140#define IXGBEVF_DEFAULT_RXD	512
141#define IXGBEVF_MAX_TXD		4096
142#define IXGBEVF_MIN_TXD		64
143#define IXGBEVF_MAX_RXD		4096
144#define IXGBEVF_MIN_RXD		64
145
146/* Supported Rx Buffer Sizes */
147#define IXGBEVF_RXBUFFER_256	256    /* Used for packet split */
148#define IXGBEVF_RXBUFFER_2048	2048
149#define IXGBEVF_RXBUFFER_3072	3072
150
151#define IXGBEVF_RX_HDR_SIZE	IXGBEVF_RXBUFFER_256
152
153#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
154
155#define IXGBEVF_SKB_PAD		(NET_SKB_PAD + NET_IP_ALIGN)
156#if (PAGE_SIZE < 8192)
157#define IXGBEVF_MAX_FRAME_BUILD_SKB \
158	(SKB_WITH_OVERHEAD(IXGBEVF_RXBUFFER_2048) - IXGBEVF_SKB_PAD)
159#else
160#define IXGBEVF_MAX_FRAME_BUILD_SKB	IXGBEVF_RXBUFFER_2048
161#endif
162
163#define IXGBE_TX_FLAGS_CSUM		BIT(0)
164#define IXGBE_TX_FLAGS_VLAN		BIT(1)
165#define IXGBE_TX_FLAGS_TSO		BIT(2)
166#define IXGBE_TX_FLAGS_IPV4		BIT(3)
167#define IXGBE_TX_FLAGS_IPSEC		BIT(4)
168#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
169#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK	0x0000e000
170#define IXGBE_TX_FLAGS_VLAN_SHIFT	16
171
172#define ring_uses_large_buffer(ring) \
173	test_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state)
174#define set_ring_uses_large_buffer(ring) \
175	set_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state)
176#define clear_ring_uses_large_buffer(ring) \
177	clear_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state)
178
179#define ring_uses_build_skb(ring) \
180	test_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state)
181#define set_ring_build_skb_enabled(ring) \
182	set_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state)
183#define clear_ring_build_skb_enabled(ring) \
184	clear_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state)
185
186static inline unsigned int ixgbevf_rx_bufsz(struct ixgbevf_ring *ring)
187{
188#if (PAGE_SIZE < 8192)
189	if (ring_uses_large_buffer(ring))
190		return IXGBEVF_RXBUFFER_3072;
191
192	if (ring_uses_build_skb(ring))
193		return IXGBEVF_MAX_FRAME_BUILD_SKB;
194#endif
195	return IXGBEVF_RXBUFFER_2048;
196}
197
198static inline unsigned int ixgbevf_rx_pg_order(struct ixgbevf_ring *ring)
199{
200#if (PAGE_SIZE < 8192)
201	if (ring_uses_large_buffer(ring))
202		return 1;
203#endif
204	return 0;
205}
206
207#define ixgbevf_rx_pg_size(_ring) (PAGE_SIZE << ixgbevf_rx_pg_order(_ring))
208
209#define check_for_tx_hang(ring) \
210	test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
211#define set_check_for_tx_hang(ring) \
212	set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
213#define clear_check_for_tx_hang(ring) \
214	clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
215
216struct ixgbevf_ring_container {
217	struct ixgbevf_ring *ring;	/* pointer to linked list of rings */
218	unsigned int total_bytes;	/* total bytes processed this int */
219	unsigned int total_packets;	/* total packets processed this int */
220	u8 count;			/* total number of rings in vector */
221	u8 itr;				/* current ITR setting for ring */
222};
223
224/* iterator for handling rings in ring container */
225#define ixgbevf_for_each_ring(pos, head) \
226	for (pos = (head).ring; pos != NULL; pos = pos->next)
227
228/* MAX_MSIX_Q_VECTORS of these are allocated,
229 * but we only use one per queue-specific vector.
230 */
231struct ixgbevf_q_vector {
232	struct ixgbevf_adapter *adapter;
233	/* index of q_vector within array, also used for finding the bit in
234	 * EICR and friends that represents the vector for this ring
235	 */
236	u16 v_idx;
237	u16 itr; /* Interrupt throttle rate written to EITR */
238	struct napi_struct napi;
239	struct ixgbevf_ring_container rx, tx;
240	struct rcu_head rcu;    /* to avoid race with update stats on free */
241	char name[IFNAMSIZ + 9];
242
243	/* for dynamic allocation of rings associated with this q_vector */
244	struct ixgbevf_ring ring[] ____cacheline_internodealigned_in_smp;
245};
246
247/* microsecond values for various ITR rates shifted by 2 to fit itr register
248 * with the first 3 bits reserved 0
249 */
250#define IXGBE_MIN_RSC_ITR	24
251#define IXGBE_100K_ITR		40
252#define IXGBE_20K_ITR		200
253#define IXGBE_12K_ITR		336
254
255/* Helper macros to switch between ints/sec and what the register uses.
256 * And yes, it's the same math going both ways.  The lowest value
257 * supported by all of the ixgbe hardware is 8.
258 */
259#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
260	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
261#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
262
263/* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */
264static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
265					  const u32 stat_err_bits)
266{
267	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
268}
269
270static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
271{
272	u16 ntc = ring->next_to_clean;
273	u16 ntu = ring->next_to_use;
274
275	return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
276}
277
278static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
279{
280	writel(value, ring->tail);
281}
282
283#define IXGBEVF_RX_DESC(R, i)	\
284	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
285#define IXGBEVF_TX_DESC(R, i)	\
286	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
287#define IXGBEVF_TX_CTXTDESC(R, i)	\
288	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
289
290#define IXGBE_MAX_JUMBO_FRAME_SIZE	9728 /* Maximum Supported Size 9.5KB */
291
292#define OTHER_VECTOR	1
293#define NON_Q_VECTORS	(OTHER_VECTOR)
294
295#define MAX_MSIX_Q_VECTORS	2
296
297#define MIN_MSIX_Q_VECTORS	1
298#define MIN_MSIX_COUNT		(MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
299
300#define IXGBEVF_RX_DMA_ATTR \
301	(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
302
303/* board specific private data structure */
304struct ixgbevf_adapter {
305	/* this field must be first, see ixgbevf_process_skb_fields */
306	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
307
308	struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
309
310	/* Interrupt Throttle Rate */
311	u16 rx_itr_setting;
312	u16 tx_itr_setting;
313
314	/* interrupt masks */
315	u32 eims_enable_mask;
316	u32 eims_other;
317
318	/* XDP */
319	int num_xdp_queues;
320	struct ixgbevf_ring *xdp_ring[MAX_XDP_QUEUES];
321
322	/* TX */
323	int num_tx_queues;
324	struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */
325	u64 restart_queue;
326	u32 tx_timeout_count;
327	u64 tx_ipsec;
328
329	/* RX */
330	int num_rx_queues;
331	struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */
332	u64 hw_csum_rx_error;
333	int num_msix_vectors;
334	u64 alloc_rx_page_failed;
335	u64 alloc_rx_buff_failed;
336	u64 alloc_rx_page;
337	u64 rx_ipsec;
338
339	struct msix_entry *msix_entries;
340
341	/* OS defined structs */
342	struct net_device *netdev;
343	struct bpf_prog *xdp_prog;
344	struct pci_dev *pdev;
345
346	/* structs defined in ixgbe_vf.h */
347	struct ixgbe_hw hw;
348	u16 msg_enable;
349
350	u32 pf_features;
351#define IXGBEVF_PF_SUP_IPSEC		BIT(0)
352#define IXGBEVF_PF_SUP_ESX_MBX		BIT(1)
353
354#define IXGBEVF_SUPPORTED_FEATURES	(IXGBEVF_PF_SUP_IPSEC | \
355					IXGBEVF_PF_SUP_ESX_MBX)
356
357	struct ixgbevf_hw_stats stats;
358
359	unsigned long state;
360	u64 tx_busy;
361	unsigned int tx_ring_count;
362	unsigned int xdp_ring_count;
363	unsigned int rx_ring_count;
364
365	u8 __iomem *io_addr; /* Mainly for iounmap use */
366	u32 link_speed;
367	bool link_up;
368
369	struct timer_list service_timer;
370	struct work_struct service_task;
371
372	spinlock_t mbx_lock;
373	unsigned long last_reset;
374
375	u32 *rss_key;
376	u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE];
377	u32 flags;
378	bool link_state;
379
380#define IXGBEVF_FLAGS_LEGACY_RX		BIT(1)
381
382#ifdef CONFIG_XFRM
383	struct ixgbevf_ipsec *ipsec;
384#endif /* CONFIG_XFRM */
385};
386
387enum ixbgevf_state_t {
388	__IXGBEVF_TESTING,
389	__IXGBEVF_RESETTING,
390	__IXGBEVF_DOWN,
391	__IXGBEVF_DISABLED,
392	__IXGBEVF_REMOVING,
393	__IXGBEVF_SERVICE_SCHED,
394	__IXGBEVF_SERVICE_INITED,
395	__IXGBEVF_RESET_REQUESTED,
396	__IXGBEVF_QUEUE_RESET_REQUESTED,
397};
398
399enum ixgbevf_boards {
400	board_82599_vf,
401	board_82599_vf_hv,
402	board_X540_vf,
403	board_X540_vf_hv,
404	board_X550_vf,
405	board_X550_vf_hv,
406	board_X550EM_x_vf,
407	board_X550EM_x_vf_hv,
408	board_x550em_a_vf,
409	board_e610_vf,
410	board_e610_vf_hv,
411};
412
413enum ixgbevf_xcast_modes {
414	IXGBEVF_XCAST_MODE_NONE = 0,
415	IXGBEVF_XCAST_MODE_MULTI,
416	IXGBEVF_XCAST_MODE_ALLMULTI,
417	IXGBEVF_XCAST_MODE_PROMISC,
418};
419
420extern const struct ixgbevf_info ixgbevf_82599_vf_info;
421extern const struct ixgbevf_info ixgbevf_X540_vf_info;
422extern const struct ixgbevf_info ixgbevf_X550_vf_info;
423extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
424extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
425extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops_legacy;
426extern const struct ixgbevf_info ixgbevf_x550em_a_vf_info;
427extern const struct ixgbevf_info ixgbevf_e610_vf_info;
428
429extern const struct ixgbevf_info ixgbevf_82599_vf_hv_info;
430extern const struct ixgbevf_info ixgbevf_X540_vf_hv_info;
431extern const struct ixgbevf_info ixgbevf_X550_vf_hv_info;
432extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_hv_info;
433extern const struct ixgbevf_info ixgbevf_e610_vf_hv_info;
434
435/* needed by ethtool.c */
436extern const char ixgbevf_driver_name[];
437
438int ixgbevf_open(struct net_device *netdev);
439int ixgbevf_close(struct net_device *netdev);
440void ixgbevf_up(struct ixgbevf_adapter *adapter);
441void ixgbevf_down(struct ixgbevf_adapter *adapter);
442void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
443void ixgbevf_reset(struct ixgbevf_adapter *adapter);
444void ixgbevf_set_ethtool_ops(struct net_device *netdev);
445int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter,
446			       struct ixgbevf_ring *rx_ring);
447int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
448void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
449void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
450void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
451int ethtool_ioctl(struct ifreq *ifr);
452
453extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);
454
455#ifdef CONFIG_IXGBEVF_IPSEC
456void ixgbevf_init_ipsec_offload(struct ixgbevf_adapter *adapter);
457void ixgbevf_stop_ipsec_offload(struct ixgbevf_adapter *adapter);
458void ixgbevf_ipsec_restore(struct ixgbevf_adapter *adapter);
459void ixgbevf_ipsec_rx(struct ixgbevf_ring *rx_ring,
460		      union ixgbe_adv_rx_desc *rx_desc,
461		      struct sk_buff *skb);
462int ixgbevf_ipsec_tx(struct ixgbevf_ring *tx_ring,
463		     struct ixgbevf_tx_buffer *first,
464		     struct ixgbevf_ipsec_tx_data *itd);
465#else
466static inline void ixgbevf_init_ipsec_offload(struct ixgbevf_adapter *adapter)
467{ }
468static inline void ixgbevf_stop_ipsec_offload(struct ixgbevf_adapter *adapter)
469{ }
470static inline void ixgbevf_ipsec_restore(struct ixgbevf_adapter *adapter) { }
471static inline void ixgbevf_ipsec_rx(struct ixgbevf_ring *rx_ring,
472				    union ixgbe_adv_rx_desc *rx_desc,
473				    struct sk_buff *skb) { }
474static inline int ixgbevf_ipsec_tx(struct ixgbevf_ring *tx_ring,
475				   struct ixgbevf_tx_buffer *first,
476				   struct ixgbevf_ipsec_tx_data *itd)
477{ return 0; }
478#endif /* CONFIG_IXGBEVF_IPSEC */
479
480#define ixgbevf_hw_to_netdev(hw) \
481	(((struct ixgbevf_adapter *)(hw)->back)->netdev)
482
483#define hw_dbg(hw, format, arg...) \
484	netdev_dbg(ixgbevf_hw_to_netdev(hw), format, ## arg)
485
486s32 ixgbevf_poll_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size);
487s32 ixgbevf_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size);
488
489#endif /* _IXGBEVF_H_ */