ixgbe_ptp.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4#include "ixgbe.h"
   5#include <linux/ptp_classify.h>
   6#include <linux/clocksource.h>
   7
   8/*
   9 * The 82599 and the X540 do not have true 64bit nanosecond scale
  10 * counter registers. Instead, SYSTIME is defined by a fixed point
  11 * system which allows the user to define the scale counter increment
  12 * value at every level change of the oscillator driving the SYSTIME
  13 * value. For both devices the TIMINCA:IV field defines this
  14 * increment. On the X540 device, 31 bits are provided. However on the
  15 * 82599 only provides 24 bits. The time unit is determined by the
  16 * clock frequency of the oscillator in combination with the TIMINCA
  17 * register. When these devices link at 10Gb the oscillator has a
  18 * period of 6.4ns. In order to convert the scale counter into
  19 * nanoseconds the cyclecounter and timecounter structures are
  20 * used. The SYSTIME registers need to be converted to ns values by use
  21 * of only a right shift (division by power of 2). The following math
  22 * determines the largest incvalue that will fit into the available
  23 * bits in the TIMINCA register.
  24 *
  25 * PeriodWidth: Number of bits to store the clock period
  26 * MaxWidth: The maximum width value of the TIMINCA register
  27 * Period: The clock period for the oscillator
  28 * round(): discard the fractional portion of the calculation
  29 *
  30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
  31 *
  32 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
  33 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
  34 *
  35 * The period also changes based on the link speed:
  36 * At 10Gb link or no link, the period remains the same.
  37 * At 1Gb link, the period is multiplied by 10. (64ns)
  38 * At 100Mb link, the period is multiplied by 100. (640ns)
  39 *
  40 * The calculated value allows us to right shift the SYSTIME register
  41 * value in order to quickly convert it into a nanosecond clock,
  42 * while allowing for the maximum possible adjustment value.
  43 *
  44 * These diagrams are only for the 10Gb link period
  45 *
  46 *           SYSTIMEH            SYSTIMEL
  47 *       +--------------+  +--------------+
  48 * X540  |      32      |  | 1 | 3 |  28  |
  49 *       *--------------+  +--------------+
  50 *        \________ 36 bits ______/  fract
  51 *
  52 *       +--------------+  +--------------+
  53 * 82599 |      32      |  | 8 | 3 |  21  |
  54 *       *--------------+  +--------------+
  55 *        \________ 43 bits ______/  fract
  56 *
  57 * The 36 bit X540 SYSTIME overflows every
  58 *   2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
  59 *
  60 * The 43 bit 82599 SYSTIME overflows every
  61 *   2^43 * 10^-9 / 3600 = 2.4 hours
  62 */
  63#define IXGBE_INCVAL_10GB 0x66666666
  64#define IXGBE_INCVAL_1GB  0x40000000
  65#define IXGBE_INCVAL_100  0x50000000
  66
  67#define IXGBE_INCVAL_SHIFT_10GB  28
  68#define IXGBE_INCVAL_SHIFT_1GB   24
  69#define IXGBE_INCVAL_SHIFT_100   21
  70
  71#define IXGBE_INCVAL_SHIFT_82599 7
  72#define IXGBE_INCPER_SHIFT_82599 24
  73
  74#define IXGBE_OVERFLOW_PERIOD    (HZ * 30)
  75#define IXGBE_PTP_TX_TIMEOUT     (HZ)
  76
  77/* We use our own definitions instead of NSEC_PER_SEC because we want to mark
  78 * the value as a ULL to force precision when bit shifting.
  79 */
  80#define NS_PER_SEC      1000000000ULL
  81#define NS_PER_HALF_SEC  500000000ULL
  82
  83/* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL
  84 * which contain measurements of seconds and nanoseconds respectively. This
  85 * matches the standard linux representation of time in the kernel. In addition,
  86 * the X550 also has a SYSTIMER register which represents residue, or
  87 * subnanosecond overflow adjustments. To control clock adjustment, the TIMINCA
  88 * register is used, but it is unlike the X540 and 82599 devices. TIMINCA
  89 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
  90 * high bit representing whether the adjustent is positive or negative. Every
  91 * clock cycle, the X550 will add 12.5 ns + TIMINCA which can result in a range
  92 * of 12 to 13 nanoseconds adjustment. Unlike the 82599 and X540 devices, the
  93 * X550's clock for purposes of SYSTIME generation is constant and not dependent
  94 * on the link speed.
  95 *
  96 *           SYSTIMEH           SYSTIMEL        SYSTIMER
  97 *       +--------------+  +--------------+  +-------------+
  98 * X550  |      32      |  |      32      |  |     32      |
  99 *       *--------------+  +--------------+  +-------------+
 100 *       \____seconds___/   \_nanoseconds_/  \__2^-32 ns__/
 101 *
 102 * This results in a full 96 bits to represent the clock, with 32 bits for
 103 * seconds, 32 bits for nanoseconds (largest value is 0d999999999 or just under
 104 * 1 second) and an additional 32 bits to measure sub nanosecond adjustments for
 105 * underflow of adjustments.
 106 *
 107 * The 32 bits of seconds for the X550 overflows every
 108 *   2^32 / ( 365.25 * 24 * 60 * 60 ) = ~136 years.
 109 *
 110 * In order to adjust the clock frequency for the X550, the TIMINCA register is
 111 * provided. This register represents a + or minus nearly 0.5 ns adjustment to
 112 * the base frequency. It is measured in 2^-32 ns units, with the high bit being
 113 * the sign bit. This register enables software to calculate frequency
 114 * adjustments and apply them directly to the clock rate.
 115 *
 116 * The math for converting scaled_ppm into TIMINCA values is fairly
 117 * straightforward.
 118 *
 119 *   TIMINCA value = ( Base_Frequency * scaled_ppm ) / 1000000ULL << 16
 120 *
 121 * To avoid overflow, we simply use mul_u64_u64_div_u64.
 122 *
 123 * This assumes that scaled_ppm is never high enough to create a value bigger
 124 * than TIMINCA's 31 bits can store. This is ensured by the stack, and is
 125 * measured in parts per billion. Calculating this value is also simple.
 126 *   Max ppb = ( Max Adjustment / Base Frequency ) / 1000000000ULL
 127 *
 128 * For the X550, the Max adjustment is +/- 0.5 ns, and the base frequency is
 129 * 12.5 nanoseconds. This means that the Max ppb is 39999999
 130 *   Note: We subtract one in order to ensure no overflow, because the TIMINCA
 131 *         register can only hold slightly under 0.5 nanoseconds.
 132 *
 133 * Because TIMINCA is measured in 2^-32 ns units, we have to convert 12.5 ns
 134 * into 2^-32 units, which is
 135 *
 136 *  12.5 * 2^32 = C80000000
 137 *
 138 * Some revisions of hardware have a faster base frequency than the registers
 139 * were defined for. To fix this, we use a timecounter structure with the
 140 * proper mult and shift to convert the cycles into nanoseconds of time.
 141 */
 142#define IXGBE_X550_BASE_PERIOD 0xC80000000ULL
 143#define IXGBE_E610_BASE_PERIOD 0x333333333ULL
 144#define INCVALUE_MASK	0x7FFFFFFF
 145#define ISGN		0x80000000
 146
 147/**
 148 * ixgbe_ptp_setup_sdp_X540
 149 * @adapter: private adapter structure
 150 *
 151 * this function enables or disables the clock out feature on SDP0 for
 152 * the X540 device. It will create a 1 second periodic output that can
 153 * be used as the PPS (via an interrupt).
 154 *
 155 * It calculates when the system time will be on an exact second, and then
 156 * aligns the start of the PPS signal to that value.
 157 *
 158 * This works by using the cycle counter shift and mult values in reverse, and
 159 * assumes that the values we're shifting will not overflow.
 160 */
 161static void ixgbe_ptp_setup_sdp_X540(struct ixgbe_adapter *adapter)
 162{
 163	struct cyclecounter *cc = &adapter->hw_cc;
 164	struct ixgbe_hw *hw = &adapter->hw;
 165	u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
 166	u64 ns = 0, clock_edge = 0, clock_period;
 167	unsigned long flags;
 168
 169	/* disable the pin first */
 170	IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 171	IXGBE_WRITE_FLUSH(hw);
 172
 173	if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
 174		return;
 175
 176	esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 177
 178	/* enable the SDP0 pin as output, and connected to the
 179	 * native function for Timesync (ClockOut)
 180	 */
 181	esdp |= IXGBE_ESDP_SDP0_DIR |
 182		IXGBE_ESDP_SDP0_NATIVE;
 183
 184	/* enable the Clock Out feature on SDP0, and allow
 185	 * interrupts to occur when the pin changes
 186	 */
 187	tsauxc = (IXGBE_TSAUXC_EN_CLK |
 188		  IXGBE_TSAUXC_SYNCLK |
 189		  IXGBE_TSAUXC_SDP0_INT);
 190
 191	/* Determine the clock time period to use. This assumes that the
 192	 * cycle counter shift is small enough to avoid overflow.
 193	 */
 194	clock_period = div_u64((NS_PER_HALF_SEC << cc->shift), cc->mult);
 195	clktiml = (u32)(clock_period);
 196	clktimh = (u32)(clock_period >> 32);
 197
 198	/* Read the current clock time, and save the cycle counter value */
 199	spin_lock_irqsave(&adapter->tmreg_lock, flags);
 200	ns = timecounter_read(&adapter->hw_tc);
 201	clock_edge = adapter->hw_tc.cycle_last;
 202	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 203
 204	/* Figure out how many seconds to add in order to round up */
 205	div_u64_rem(ns, NS_PER_SEC, &rem);
 206
 207	/* Figure out how many nanoseconds to add to round the clock edge up
 208	 * to the next full second
 209	 */
 210	rem = (NS_PER_SEC - rem);
 211
 212	/* Adjust the clock edge to align with the next full second. */
 213	clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
 214	trgttiml = (u32)clock_edge;
 215	trgttimh = (u32)(clock_edge >> 32);
 216
 217	IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
 218	IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
 219	IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
 220	IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
 221
 222	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 223	IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
 224
 225	IXGBE_WRITE_FLUSH(hw);
 226}
 227
 228/**
 229 * ixgbe_ptp_setup_sdp_X550
 230 * @adapter: private adapter structure
 231 *
 232 * Enable or disable a clock output signal on SDP 0 for X550 hardware.
 233 *
 234 * Use the target time feature to align the output signal on the next full
 235 * second.
 236 *
 237 * This works by using the cycle counter shift and mult values in reverse, and
 238 * assumes that the values we're shifting will not overflow.
 239 */
 240static void ixgbe_ptp_setup_sdp_X550(struct ixgbe_adapter *adapter)
 241{
 242	u32 esdp, tsauxc, freqout, trgttiml, trgttimh, rem, tssdp;
 243	struct cyclecounter *cc = &adapter->hw_cc;
 244	struct ixgbe_hw *hw = &adapter->hw;
 245	u64 ns = 0, clock_edge = 0;
 246	struct timespec64 ts;
 247	unsigned long flags;
 248
 249	/* disable the pin first */
 250	IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 251	IXGBE_WRITE_FLUSH(hw);
 252
 253	if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
 254		return;
 255
 256	esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 257
 258	/* enable the SDP0 pin as output, and connected to the
 259	 * native function for Timesync (ClockOut)
 260	 */
 261	esdp |= IXGBE_ESDP_SDP0_DIR |
 262		IXGBE_ESDP_SDP0_NATIVE;
 263
 264	/* enable the Clock Out feature on SDP0, and use Target Time 0 to
 265	 * enable generation of interrupts on the clock change.
 266	 */
 267#define IXGBE_TSAUXC_DIS_TS_CLEAR 0x40000000
 268	tsauxc = (IXGBE_TSAUXC_EN_CLK | IXGBE_TSAUXC_ST0 |
 269		  IXGBE_TSAUXC_EN_TT0 | IXGBE_TSAUXC_SDP0_INT |
 270		  IXGBE_TSAUXC_DIS_TS_CLEAR);
 271
 272	tssdp = (IXGBE_TSSDP_TS_SDP0_EN |
 273		 IXGBE_TSSDP_TS_SDP0_CLK0);
 274
 275	/* Determine the clock time period to use. This assumes that the
 276	 * cycle counter shift is small enough to avoid overflowing a 32bit
 277	 * value.
 278	 */
 279	freqout = div_u64(NS_PER_HALF_SEC << cc->shift,  cc->mult);
 280
 281	/* Read the current clock time, and save the cycle counter value */
 282	spin_lock_irqsave(&adapter->tmreg_lock, flags);
 283	ns = timecounter_read(&adapter->hw_tc);
 284	clock_edge = adapter->hw_tc.cycle_last;
 285	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 286
 287	/* Figure out how far past the next second we are */
 288	div_u64_rem(ns, NS_PER_SEC, &rem);
 289
 290	/* Figure out how many nanoseconds to add to round the clock edge up
 291	 * to the next full second
 292	 */
 293	rem = (NS_PER_SEC - rem);
 294
 295	/* Adjust the clock edge to align with the next full second. */
 296	clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
 297
 298	/* X550 hardware stores the time in 32bits of 'billions of cycles' and
 299	 * 32bits of 'cycles'. There's no guarantee that cycles represents
 300	 * nanoseconds. However, we can use the math from a timespec64 to
 301	 * convert into the hardware representation.
 302	 *
 303	 * See ixgbe_ptp_read_X550() for more details.
 304	 */
 305	ts = ns_to_timespec64(clock_edge);
 306	trgttiml = (u32)ts.tv_nsec;
 307	trgttimh = (u32)ts.tv_sec;
 308
 309	IXGBE_WRITE_REG(hw, IXGBE_FREQOUT0, freqout);
 310	IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
 311	IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
 312
 313	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 314	IXGBE_WRITE_REG(hw, IXGBE_TSSDP, tssdp);
 315	IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
 316
 317	IXGBE_WRITE_FLUSH(hw);
 318}
 319
 320/**
 321 * ixgbe_ptp_read_X550 - read cycle counter value
 322 * @cc: cyclecounter structure
 323 *
 324 * This function reads SYSTIME registers. It is called by the cyclecounter
 325 * structure to convert from internal representation into nanoseconds. We need
 326 * this for X550 since some skews do not have expected clock frequency and
 327 * result of SYSTIME is 32bits of "billions of cycles" and 32 bits of
 328 * "cycles", rather than seconds and nanoseconds.
 329 */
 330static u64 ixgbe_ptp_read_X550(struct cyclecounter *cc)
 331{
 332	struct ixgbe_adapter *adapter =
 333		container_of(cc, struct ixgbe_adapter, hw_cc);
 334	struct ixgbe_hw *hw = &adapter->hw;
 335	struct timespec64 ts;
 336
 337	/* storage is 32 bits of 'billions of cycles' and 32 bits of 'cycles'.
 338	 * Some revisions of hardware run at a higher frequency and so the
 339	 * cycles are not guaranteed to be nanoseconds. The timespec64 created
 340	 * here is used for its math/conversions but does not necessarily
 341	 * represent nominal time.
 342	 *
 343	 * It should be noted that this cyclecounter will overflow at a
 344	 * non-bitmask field since we have to convert our billions of cycles
 345	 * into an actual cycles count. This results in some possible weird
 346	 * situations at high cycle counter stamps. However given that 32 bits
 347	 * of "seconds" is ~138 years this isn't a problem. Even at the
 348	 * increased frequency of some revisions, this is still ~103 years.
 349	 * Since the SYSTIME values start at 0 and we never write them, it is
 350	 * highly unlikely for the cyclecounter to overflow in practice.
 351	 */
 352	IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
 353	ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 354	ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
 355
 356	return (u64)timespec64_to_ns(&ts);
 357}
 358
 359/**
 360 * ixgbe_ptp_read_82599 - read raw cycle counter (to be used by time counter)
 361 * @cc: the cyclecounter structure
 362 *
 363 * this function reads the cyclecounter registers and is called by the
 364 * cyclecounter structure used to construct a ns counter from the
 365 * arbitrary fixed point registers
 366 */
 367static u64 ixgbe_ptp_read_82599(struct cyclecounter *cc)
 368{
 369	struct ixgbe_adapter *adapter =
 370		container_of(cc, struct ixgbe_adapter, hw_cc);
 371	struct ixgbe_hw *hw = &adapter->hw;
 372	u64 stamp = 0;
 373
 374	stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 375	stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 376
 377	return stamp;
 378}
 379
 380/**
 381 * ixgbe_ptp_convert_to_hwtstamp - convert register value to hw timestamp
 382 * @adapter: private adapter structure
 383 * @hwtstamp: stack timestamp structure
 384 * @timestamp: unsigned 64bit system time value
 385 *
 386 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value
 387 * which can be used by the stack's ptp functions.
 388 *
 389 * The lock is used to protect consistency of the cyclecounter and the SYSTIME
 390 * registers. However, it does not need to protect against the Rx or Tx
 391 * timestamp registers, as there can't be a new timestamp until the old one is
 392 * unlatched by reading.
 393 *
 394 * In addition to the timestamp in hardware, some controllers need a software
 395 * overflow cyclecounter, and this function takes this into account as well.
 396 **/
 397static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter,
 398					  struct skb_shared_hwtstamps *hwtstamp,
 399					  u64 timestamp)
 400{
 401	unsigned long flags;
 402	struct timespec64 systime;
 403	u64 ns;
 404
 405	memset(hwtstamp, 0, sizeof(*hwtstamp));
 406
 407	switch (adapter->hw.mac.type) {
 408	/* X550 and later hardware supposedly represent time using a seconds
 409	 * and nanoseconds counter, instead of raw 64bits nanoseconds. We need
 410	 * to convert the timestamp into cycles before it can be fed to the
 411	 * cyclecounter. We need an actual cyclecounter because some revisions
 412	 * of hardware run at a higher frequency and thus the counter does
 413	 * not represent seconds/nanoseconds. Instead it can be thought of as
 414	 * cycles and billions of cycles.
 415	 */
 416	case ixgbe_mac_X550:
 417	case ixgbe_mac_X550EM_x:
 418	case ixgbe_mac_x550em_a:
 419	case ixgbe_mac_e610:
 420		/* Upper 32 bits represent billions of cycles, lower 32 bits
 421		 * represent cycles. However, we use timespec64_to_ns for the
 422		 * correct math even though the units haven't been corrected
 423		 * yet.
 424		 */
 425		systime.tv_sec = timestamp >> 32;
 426		systime.tv_nsec = timestamp & 0xFFFFFFFF;
 427
 428		timestamp = timespec64_to_ns(&systime);
 429		break;
 430	default:
 431		break;
 432	}
 433
 434	spin_lock_irqsave(&adapter->tmreg_lock, flags);
 435	ns = timecounter_cyc2time(&adapter->hw_tc, timestamp);
 436	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 437
 438	hwtstamp->hwtstamp = ns_to_ktime(ns);
 439}
 440
 441/**
 442 * ixgbe_ptp_adjfine_82599
 443 * @ptp: the ptp clock structure
 444 * @scaled_ppm: scaled parts per million adjustment from base
 445 *
 446 * Adjust the frequency of the ptp cycle counter by the
 447 * indicated scaled_ppm from the base frequency.
 448 *
 449 * Scaled parts per million is ppm with a 16-bit binary fractional field.
 450 */
 451static int ixgbe_ptp_adjfine_82599(struct ptp_clock_info *ptp, long scaled_ppm)
 452{
 453	struct ixgbe_adapter *adapter =
 454		container_of(ptp, struct ixgbe_adapter, ptp_caps);
 455	struct ixgbe_hw *hw = &adapter->hw;
 456	u64 incval;
 457
 458	smp_mb();
 459	incval = READ_ONCE(adapter->base_incval);
 460	incval = adjust_by_scaled_ppm(incval, scaled_ppm);
 461
 462	switch (hw->mac.type) {
 463	case ixgbe_mac_X540:
 464		if (incval > 0xFFFFFFFFULL)
 465			e_dev_warn("PTP scaled_ppm adjusted SYSTIME rate overflowed!\n");
 466		IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval);
 467		break;
 468	case ixgbe_mac_82599EB:
 469		if (incval > 0x00FFFFFFULL)
 470			e_dev_warn("PTP scaled_ppm adjusted SYSTIME rate overflowed!\n");
 471		IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 472				BIT(IXGBE_INCPER_SHIFT_82599) |
 473				((u32)incval & 0x00FFFFFFUL));
 474		break;
 475	default:
 476		break;
 477	}
 478
 479	return 0;
 480}
 481
 482/**
 483 * ixgbe_ptp_adjfine_X550
 484 * @ptp: the ptp clock structure
 485 * @scaled_ppm: scaled parts per million adjustment from base
 486 *
 487 * Adjust the frequency of the SYSTIME registers by the indicated scaled_ppm
 488 * from base frequency.
 489 *
 490 * Scaled parts per million is ppm with a 16-bit binary fractional field.
 491 */
 492static int ixgbe_ptp_adjfine_X550(struct ptp_clock_info *ptp, long scaled_ppm)
 493{
 494	struct ixgbe_adapter *adapter =
 495			container_of(ptp, struct ixgbe_adapter, ptp_caps);
 496	struct ixgbe_hw *hw = &adapter->hw;
 497	u64 rate, base;
 498	bool neg_adj;
 499	u32 inca;
 500
 501	base = hw->mac.type == ixgbe_mac_e610 ? IXGBE_E610_BASE_PERIOD :
 502						IXGBE_X550_BASE_PERIOD;
 503	neg_adj = diff_by_scaled_ppm(base, scaled_ppm, &rate);
 504
 505	/* warn if rate is too large */
 506	if (rate >= INCVALUE_MASK)
 507		e_dev_warn("PTP scaled_ppm adjusted SYSTIME rate overflowed!\n");
 508
 509	inca = rate & INCVALUE_MASK;
 510	if (neg_adj)
 511		inca |= ISGN;
 512
 513	IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca);
 514
 515	return 0;
 516}
 517
 518/**
 519 * ixgbe_ptp_adjtime
 520 * @ptp: the ptp clock structure
 521 * @delta: offset to adjust the cycle counter by
 522 *
 523 * adjust the timer by resetting the timecounter structure.
 524 */
 525static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 526{
 527	struct ixgbe_adapter *adapter =
 528		container_of(ptp, struct ixgbe_adapter, ptp_caps);
 529	unsigned long flags;
 530
 531	spin_lock_irqsave(&adapter->tmreg_lock, flags);
 532	timecounter_adjtime(&adapter->hw_tc, delta);
 533	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 534
 535	if (adapter->ptp_setup_sdp)
 536		adapter->ptp_setup_sdp(adapter);
 537
 538	return 0;
 539}
 540
 541/**
 542 * ixgbe_ptp_gettimex
 543 * @ptp: the ptp clock structure
 544 * @ts: timespec to hold the PHC timestamp
 545 * @sts: structure to hold the system time before and after reading the PHC
 546 *
 547 * read the timecounter and return the correct value on ns,
 548 * after converting it into a struct timespec.
 549 */
 550static int ixgbe_ptp_gettimex(struct ptp_clock_info *ptp,
 551			      struct timespec64 *ts,
 552			      struct ptp_system_timestamp *sts)
 553{
 554	struct ixgbe_adapter *adapter =
 555		container_of(ptp, struct ixgbe_adapter, ptp_caps);
 556	struct ixgbe_hw *hw = &adapter->hw;
 557	unsigned long flags;
 558	u64 ns, stamp;
 559
 560	spin_lock_irqsave(&adapter->tmreg_lock, flags);
 561
 562	switch (adapter->hw.mac.type) {
 563	case ixgbe_mac_X550:
 564	case ixgbe_mac_X550EM_x:
 565	case ixgbe_mac_x550em_a:
 566	case ixgbe_mac_e610:
 567		/* Upper 32 bits represent billions of cycles, lower 32 bits
 568		 * represent cycles. However, we use timespec64_to_ns for the
 569		 * correct math even though the units haven't been corrected
 570		 * yet.
 571		 */
 572		ptp_read_system_prets(sts);
 573		IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
 574		ptp_read_system_postts(sts);
 575		ts->tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 576		ts->tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
 577		stamp = timespec64_to_ns(ts);
 578		break;
 579	default:
 580		ptp_read_system_prets(sts);
 581		stamp = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 582		ptp_read_system_postts(sts);
 583		stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 584		break;
 585	}
 586
 587	ns = timecounter_cyc2time(&adapter->hw_tc, stamp);
 588
 589	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 590
 591	*ts = ns_to_timespec64(ns);
 592
 593	return 0;
 594}
 595
 596/**
 597 * ixgbe_ptp_settime
 598 * @ptp: the ptp clock structure
 599 * @ts: the timespec containing the new time for the cycle counter
 600 *
 601 * reset the timecounter to use a new base value instead of the kernel
 602 * wall timer value.
 603 */
 604static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
 605			     const struct timespec64 *ts)
 606{
 607	struct ixgbe_adapter *adapter =
 608		container_of(ptp, struct ixgbe_adapter, ptp_caps);
 609	unsigned long flags;
 610	u64 ns = timespec64_to_ns(ts);
 611
 612	/* reset the timecounter */
 613	spin_lock_irqsave(&adapter->tmreg_lock, flags);
 614	timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns);
 615	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 616
 617	if (adapter->ptp_setup_sdp)
 618		adapter->ptp_setup_sdp(adapter);
 619	return 0;
 620}
 621
 622/**
 623 * ixgbe_ptp_feature_enable
 624 * @ptp: the ptp clock structure
 625 * @rq: the requested feature to change
 626 * @on: whether to enable or disable the feature
 627 *
 628 * enable (or disable) ancillary features of the phc subsystem.
 629 * our driver only supports the PPS feature on the X540
 630 */
 631static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
 632				    struct ptp_clock_request *rq, int on)
 633{
 634	struct ixgbe_adapter *adapter =
 635		container_of(ptp, struct ixgbe_adapter, ptp_caps);
 636
 637	/**
 638	 * When PPS is enabled, unmask the interrupt for the ClockOut
 639	 * feature, so that the interrupt handler can send the PPS
 640	 * event when the clock SDP triggers. Clear mask when PPS is
 641	 * disabled
 642	 */
 643	if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp)
 644		return -EOPNOTSUPP;
 645
 646	if (on)
 647		adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
 648	else
 649		adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
 650
 651	adapter->ptp_setup_sdp(adapter);
 652	return 0;
 653}
 654
 655/**
 656 * ixgbe_ptp_check_pps_event
 657 * @adapter: the private adapter structure
 658 *
 659 * This function is called by the interrupt routine when checking for
 660 * interrupts. It will check and handle a pps event.
 661 */
 662void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter)
 663{
 664	struct ixgbe_hw *hw = &adapter->hw;
 665	struct ptp_clock_event event;
 666
 667	event.type = PTP_CLOCK_PPS;
 668
 669	/* this check is necessary in case the interrupt was enabled via some
 670	 * alternative means (ex. debug_fs). Better to check here than
 671	 * everywhere that calls this function.
 672	 */
 673	if (!adapter->ptp_clock)
 674		return;
 675
 676	switch (hw->mac.type) {
 677	case ixgbe_mac_X540:
 678		ptp_clock_event(adapter->ptp_clock, &event);
 679		break;
 680	default:
 681		break;
 682	}
 683}
 684
 685/**
 686 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
 687 * @adapter: private adapter struct
 688 *
 689 * this watchdog task periodically reads the timecounter
 690 * in order to prevent missing when the system time registers wrap
 691 * around. This needs to be run approximately twice a minute.
 692 */
 693void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
 694{
 695	bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
 696					     IXGBE_OVERFLOW_PERIOD);
 697	unsigned long flags;
 698
 699	if (timeout) {
 700		/* Update the timecounter */
 701		spin_lock_irqsave(&adapter->tmreg_lock, flags);
 702		timecounter_read(&adapter->hw_tc);
 703		spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 704
 705		adapter->last_overflow_check = jiffies;
 706	}
 707}
 708
 709/**
 710 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
 711 * @adapter: private network adapter structure
 712 *
 713 * this watchdog task is scheduled to detect error case where hardware has
 714 * dropped an Rx packet that was timestamped when the ring is full. The
 715 * particular error is rare but leaves the device in a state unable to timestamp
 716 * any future packets.
 717 */
 718void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
 719{
 720	struct ixgbe_hw *hw = &adapter->hw;
 721	u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 722	struct ixgbe_ring *rx_ring;
 723	unsigned long rx_event;
 724	int n;
 725
 726	/* if we don't have a valid timestamp in the registers, just update the
 727	 * timeout counter and exit
 728	 */
 729	if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
 730		adapter->last_rx_ptp_check = jiffies;
 731		return;
 732	}
 733
 734	/* determine the most recent watchdog or rx_timestamp event */
 735	rx_event = adapter->last_rx_ptp_check;
 736	for (n = 0; n < adapter->num_rx_queues; n++) {
 737		rx_ring = adapter->rx_ring[n];
 738		if (time_after(rx_ring->last_rx_timestamp, rx_event))
 739			rx_event = rx_ring->last_rx_timestamp;
 740	}
 741
 742	/* only need to read the high RXSTMP register to clear the lock */
 743	if (time_is_before_jiffies(rx_event + 5 * HZ)) {
 744		IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
 745		adapter->last_rx_ptp_check = jiffies;
 746
 747		adapter->rx_hwtstamp_cleared++;
 748		e_warn(drv, "clearing RX Timestamp hang\n");
 749	}
 750}
 751
 752/**
 753 * ixgbe_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state
 754 * @adapter: the private adapter structure
 755 *
 756 * This function should be called whenever the state related to a Tx timestamp
 757 * needs to be cleared. This helps ensure that all related bits are reset for
 758 * the next Tx timestamp event.
 759 */
 760static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter)
 761{
 762	struct ixgbe_hw *hw = &adapter->hw;
 763
 764	IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
 765	if (adapter->ptp_tx_skb) {
 766		dev_kfree_skb_any(adapter->ptp_tx_skb);
 767		adapter->ptp_tx_skb = NULL;
 768	}
 769	clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
 770}
 771
 772/**
 773 * ixgbe_ptp_tx_hang - detect error case where Tx timestamp never finishes
 774 * @adapter: private network adapter structure
 775 */
 776void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter)
 777{
 778	bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
 779					      IXGBE_PTP_TX_TIMEOUT);
 780
 781	if (!adapter->ptp_tx_skb)
 782		return;
 783
 784	if (!test_bit(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state))
 785		return;
 786
 787	/* If we haven't received a timestamp within the timeout, it is
 788	 * reasonable to assume that it will never occur, so we can unlock the
 789	 * timestamp bit when this occurs.
 790	 */
 791	if (timeout) {
 792		cancel_work_sync(&adapter->ptp_tx_work);
 793		ixgbe_ptp_clear_tx_timestamp(adapter);
 794		adapter->tx_hwtstamp_timeouts++;
 795		e_warn(drv, "clearing Tx timestamp hang\n");
 796	}
 797}
 798
 799/**
 800 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 801 * @adapter: the private adapter struct
 802 *
 803 * if the timestamp is valid, we convert it into the timecounter ns
 804 * value, then store that result into the shhwtstamps structure which
 805 * is passed up the network stack
 806 */
 807static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
 808{
 809	struct sk_buff *skb = adapter->ptp_tx_skb;
 810	struct ixgbe_hw *hw = &adapter->hw;
 811	struct skb_shared_hwtstamps shhwtstamps;
 812	u64 regval = 0;
 813
 814	regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
 815	regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
 816	ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval);
 817
 818	/* Handle cleanup of the ptp_tx_skb ourselves, and unlock the state
 819	 * bit prior to notifying the stack via skb_tstamp_tx(). This prevents
 820	 * well behaved applications from attempting to timestamp again prior
 821	 * to the lock bit being clear.
 822	 */
 823	adapter->ptp_tx_skb = NULL;
 824	clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
 825
 826	/* Notify the stack and then free the skb after we've unlocked */
 827	skb_tstamp_tx(skb, &shhwtstamps);
 828	dev_kfree_skb_any(skb);
 829}
 830
 831/**
 832 * ixgbe_ptp_tx_hwtstamp_work
 833 * @work: pointer to the work struct
 834 *
 835 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
 836 * timestamp has been taken for the current skb. It is necessary, because the
 837 * descriptor's "done" bit does not correlate with the timestamp event.
 838 */
 839static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
 840{
 841	struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
 842						     ptp_tx_work);
 843	struct ixgbe_hw *hw = &adapter->hw;
 844	bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
 845					      IXGBE_PTP_TX_TIMEOUT);
 846	u32 tsynctxctl;
 847
 848	/* we have to have a valid skb to poll for a timestamp */
 849	if (!adapter->ptp_tx_skb) {
 850		ixgbe_ptp_clear_tx_timestamp(adapter);
 851		return;
 852	}
 853
 854	/* stop polling once we have a valid timestamp */
 855	tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 856	if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) {
 857		ixgbe_ptp_tx_hwtstamp(adapter);
 858		return;
 859	}
 860
 861	if (timeout) {
 862		ixgbe_ptp_clear_tx_timestamp(adapter);
 863		adapter->tx_hwtstamp_timeouts++;
 864		e_warn(drv, "clearing Tx Timestamp hang\n");
 865	} else {
 866		/* reschedule to keep checking if it's not available yet */
 867		schedule_work(&adapter->ptp_tx_work);
 868	}
 869}
 870
 871/**
 872 * ixgbe_ptp_rx_pktstamp - utility function to get RX time stamp from buffer
 873 * @q_vector: structure containing interrupt and ring information
 874 * @skb: the packet
 875 *
 876 * This function will be called by the Rx routine of the timestamp for this
 877 * packet is stored in the buffer. The value is stored in little endian format
 878 * starting at the end of the packet data.
 879 */
 880void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector,
 881			   struct sk_buff *skb)
 882{
 883	__le64 regval;
 884
 885	/* copy the bits out of the skb, and then trim the skb length */
 886	skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, &regval,
 887		      IXGBE_TS_HDR_LEN);
 888	__pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN);
 889
 890	/* The timestamp is recorded in little endian format, and is stored at
 891	 * the end of the packet.
 892	 *
 893	 * DWORD: N              N + 1      N + 2
 894	 * Field: End of Packet  SYSTIMH    SYSTIML
 895	 */
 896	ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
 897				      le64_to_cpu(regval));
 898}
 899
 900/**
 901 * ixgbe_ptp_rx_rgtstamp - utility function which checks for RX time stamp
 902 * @q_vector: structure containing interrupt and ring information
 903 * @skb: particular skb to send timestamp with
 904 *
 905 * if the timestamp is valid, we convert it into the timecounter ns
 906 * value, then store that result into the shhwtstamps structure which
 907 * is passed up the network stack
 908 */
 909void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector,
 910			   struct sk_buff *skb)
 911{
 912	struct ixgbe_adapter *adapter;
 913	struct ixgbe_hw *hw;
 914	u64 regval = 0;
 915	u32 tsyncrxctl;
 916
 917	/* we cannot process timestamps on a ring without a q_vector */
 918	if (!q_vector || !q_vector->adapter)
 919		return;
 920
 921	adapter = q_vector->adapter;
 922	hw = &adapter->hw;
 923
 924	/* Read the tsyncrxctl register afterwards in order to prevent taking an
 925	 * I/O hit on every packet.
 926	 */
 927
 928	tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 929	if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
 930		return;
 931
 932	regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
 933	regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
 934
 935	ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
 936}
 937
 938/**
 939 * ixgbe_ptp_hwtstamp_get - get current hardware timestamping configuration
 940 * @netdev: pointer to net device structure
 941 * @config: timestamping configuration structure
 942 *
 943 * This function returns the current timestamping settings. Rather than
 944 * attempt to deconstruct registers to fill in the values, simply keep a copy
 945 * of the old settings around, and return a copy when requested.
 946 */
 947int ixgbe_ptp_hwtstamp_get(struct net_device *netdev,
 948			   struct kernel_hwtstamp_config *config)
 949{
 950	struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev);
 951
 952	*config = adapter->tstamp_config;
 953
 954	return 0;
 955}
 956
 957/**
 958 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
 959 * @adapter: the private ixgbe adapter structure
 960 * @config: the hwtstamp configuration requested
 961 *
 962 * Outgoing time stamping can be enabled and disabled. Play nice and
 963 * disable it when requested, although it shouldn't cause any overhead
 964 * when no packet needs it. At most one packet in the queue may be
 965 * marked for time stamping, otherwise it would be impossible to tell
 966 * for sure to which packet the hardware time stamp belongs.
 967 *
 968 * Incoming time stamping has to be configured via the hardware
 969 * filters. Not all combinations are supported, in particular event
 970 * type has to be specified. Matching the kind of event packet is
 971 * not supported, with the exception of "all V2 events regardless of
 972 * level 2 or 4".
 973 *
 974 * Since hardware always timestamps Path delay packets when timestamping V2
 975 * packets, regardless of the type specified in the register, only use V2
 976 * Event mode. This more accurately tells the user what the hardware is going
 977 * to do anyways.
 978 *
 979 * Note: this may modify the hwtstamp configuration towards a more general
 980 * mode, if required to support the specifically requested mode.
 981 */
 982static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
 983					struct kernel_hwtstamp_config *config)
 984{
 985	struct ixgbe_hw *hw = &adapter->hw;
 986	u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
 987	u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
 988	u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
 989	u32 aflags = adapter->flags;
 990	bool is_l2 = false;
 991	u32 regval;
 992
 993	switch (config->tx_type) {
 994	case HWTSTAMP_TX_OFF:
 995		tsync_tx_ctl = 0;
 996		break;
 997	case HWTSTAMP_TX_ON:
 998		break;
 999	default:
1000		return -ERANGE;
1001	}
1002
1003	switch (config->rx_filter) {
1004	case HWTSTAMP_FILTER_NONE:
1005		tsync_rx_ctl = 0;
1006		tsync_rx_mtrl = 0;
1007		aflags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1008			    IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1009		break;
1010	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1011		tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
1012		tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
1013		aflags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1014			   IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1015		break;
1016	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1017		tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
1018		tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
1019		aflags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1020			   IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1021		break;
1022	case HWTSTAMP_FILTER_PTP_V2_EVENT:
1023	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1024	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1025	case HWTSTAMP_FILTER_PTP_V2_SYNC:
1026	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1027	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1028	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1029	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1030	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1031		tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
1032		is_l2 = true;
1033		config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1034		aflags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1035			   IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1036		break;
1037	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1038	case HWTSTAMP_FILTER_NTP_ALL:
1039	case HWTSTAMP_FILTER_ALL:
1040		/* The X550 controller is capable of timestamping all packets,
1041		 * which allows it to accept any filter.
1042		 */
1043		if (hw->mac.type >= ixgbe_mac_X550) {
1044			tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL;
1045			config->rx_filter = HWTSTAMP_FILTER_ALL;
1046			aflags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
1047			break;
1048		}
1049		fallthrough;
1050	default:
1051		/*
1052		 * register RXMTRL must be set in order to do V1 packets,
1053		 * therefore it is not possible to time stamp both V1 Sync and
1054		 * Delay_Req messages and hardware does not support
1055		 * timestamping all packets => return error
1056		 */
1057		config->rx_filter = HWTSTAMP_FILTER_NONE;
1058		return -ERANGE;
1059	}
1060
1061	if (hw->mac.type == ixgbe_mac_82598EB) {
1062		adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1063				    IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1064		if (tsync_rx_ctl | tsync_tx_ctl)
1065			return -ERANGE;
1066		return 0;
1067	}
1068
1069	/* Per-packet timestamping only works if the filter is set to all
1070	 * packets. Since this is desired, always timestamp all packets as long
1071	 * as any Rx filter was configured.
1072	 */
1073	switch (hw->mac.type) {
1074	case ixgbe_mac_X550:
1075	case ixgbe_mac_X550EM_x:
1076	case ixgbe_mac_x550em_a:
1077	case ixgbe_mac_e610:
1078		/* enable timestamping all packets only if at least some
1079		 * packets were requested. Otherwise, play nice and disable
1080		 * timestamping
1081		 */
1082		if (config->rx_filter == HWTSTAMP_FILTER_NONE)
1083			break;
1084
1085		tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED |
1086			       IXGBE_TSYNCRXCTL_TYPE_ALL |
1087			       IXGBE_TSYNCRXCTL_TSIP_UT_EN;
1088		config->rx_filter = HWTSTAMP_FILTER_ALL;
1089		aflags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
1090		aflags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER;
1091		is_l2 = true;
1092		break;
1093	default:
1094		break;
1095	}
1096
1097	/* define ethertype filter for timestamping L2 packets */
1098	if (is_l2)
1099		IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
1100				(IXGBE_ETQF_FILTER_EN | /* enable filter */
1101				 IXGBE_ETQF_1588 | /* enable timestamping */
1102				 ETH_P_1588));     /* 1588 eth protocol type */
1103	else
1104		IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
1105
1106	/* enable/disable TX */
1107	regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
1108	regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
1109	regval |= tsync_tx_ctl;
1110	IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
1111
1112	/* enable/disable RX */
1113	regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
1114	regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
1115	regval |= tsync_rx_ctl;
1116	IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
1117
1118	/* define which PTP packets are time stamped */
1119	IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
1120
1121	IXGBE_WRITE_FLUSH(hw);
1122
1123	/* configure adapter flags only when HW is actually configured */
1124	adapter->flags = aflags;
1125
1126	/* clear TX/RX time stamp registers, just to be sure */
1127	ixgbe_ptp_clear_tx_timestamp(adapter);
1128	IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
1129
1130	return 0;
1131}
1132
1133/**
1134 * ixgbe_ptp_hwtstamp_set - user entry point for timestamp mode
1135 * @netdev: pointer to net device structure
1136 * @config: timestamping configuration structure
1137 * @extack: netlink extended ack structure for error reporting
1138 *
1139 * Set hardware to requested mode. If unsupported, return an error with no
1140 * changes. Otherwise, store the mode for future reference.
1141 */
1142int ixgbe_ptp_hwtstamp_set(struct net_device *netdev,
1143			   struct kernel_hwtstamp_config *config,
1144			   struct netlink_ext_ack *extack)
1145{
1146	struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev);
1147	int err;
1148
1149	err = ixgbe_ptp_set_timestamp_mode(adapter, config);
1150	if (err)
1151		return err;
1152
1153	/* save these settings for future reference */
1154	adapter->tstamp_config = *config;
1155
1156	return 0;
1157}
1158
1159static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter,
1160					u32 *shift, u32 *incval)
1161{
1162	/**
1163	 * Scale the NIC cycle counter by a large factor so that
1164	 * relatively small corrections to the frequency can be added
1165	 * or subtracted. The drawbacks of a large factor include
1166	 * (a) the clock register overflows more quickly, (b) the cycle
1167	 * counter structure must be able to convert the systime value
1168	 * to nanoseconds using only a multiplier and a right-shift,
1169	 * and (c) the value must fit within the timinca register space
1170	 * => math based on internal DMA clock rate and available bits
1171	 *
1172	 * Note that when there is no link, internal DMA clock is same as when
1173	 * link speed is 10Gb. Set the registers correctly even when link is
1174	 * down to preserve the clock setting
1175	 */
1176	switch (adapter->link_speed) {
1177	case IXGBE_LINK_SPEED_100_FULL:
1178		*shift = IXGBE_INCVAL_SHIFT_100;
1179		*incval = IXGBE_INCVAL_100;
1180		break;
1181	case IXGBE_LINK_SPEED_1GB_FULL:
1182		*shift = IXGBE_INCVAL_SHIFT_1GB;
1183		*incval = IXGBE_INCVAL_1GB;
1184		break;
1185	case IXGBE_LINK_SPEED_10GB_FULL:
1186	default:
1187		*shift = IXGBE_INCVAL_SHIFT_10GB;
1188		*incval = IXGBE_INCVAL_10GB;
1189		break;
1190	}
1191}
1192
1193/**
1194 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
1195 * @adapter: pointer to the adapter structure
1196 *
1197 * This function should be called to set the proper values for the TIMINCA
1198 * register and tell the cyclecounter structure what the tick rate of SYSTIME
1199 * is. It does not directly modify SYSTIME registers or the timecounter
1200 * structure. It should be called whenever a new TIMINCA value is necessary,
1201 * such as during initialization or when the link speed changes.
1202 */
1203void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
1204{
1205	struct ixgbe_hw *hw = &adapter->hw;
1206	struct cyclecounter cc;
1207	unsigned long flags;
1208	u32 incval = 0;
1209	u32 fuse0 = 0;
1210
1211	/* For some of the boards below this mask is technically incorrect.
1212	 * The timestamp mask overflows at approximately 61bits. However the
1213	 * particular hardware does not overflow on an even bitmask value.
1214	 * Instead, it overflows due to conversion of upper 32bits billions of
1215	 * cycles. Timecounters are not really intended for this purpose so
1216	 * they do not properly function if the overflow point isn't 2^N-1.
1217	 * However, the actual SYSTIME values in question take ~138 years to
1218	 * overflow. In practice this means they won't actually overflow. A
1219	 * proper fix to this problem would require modification of the
1220	 * timecounter delta calculations.
1221	 */
1222	cc.mask = CLOCKSOURCE_MASK(64);
1223	cc.mult = 1;
1224	cc.shift = 0;
1225
1226	switch (hw->mac.type) {
1227	case ixgbe_mac_X550EM_x:
1228		/* SYSTIME assumes X550EM_x board frequency is 300Mhz, and is
1229		 * designed to represent seconds and nanoseconds when this is
1230		 * the case. However, some revisions of hardware have a 400Mhz
1231		 * clock and we have to compensate for this frequency
1232		 * variation using corrected mult and shift values.
1233		 */
1234		fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
1235		if (!(fuse0 & IXGBE_FUSES0_300MHZ)) {
1236			cc.mult = 3;
1237			cc.shift = 2;
1238		}
1239		fallthrough;
1240	case ixgbe_mac_x550em_a:
1241	case ixgbe_mac_X550:
1242	case ixgbe_mac_e610:
1243		cc.read = ixgbe_ptp_read_X550;
1244		break;
1245	case ixgbe_mac_X540:
1246		cc.read = ixgbe_ptp_read_82599;
1247
1248		ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1249		IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
1250		break;
1251	case ixgbe_mac_82599EB:
1252		cc.read = ixgbe_ptp_read_82599;
1253
1254		ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1255		incval >>= IXGBE_INCVAL_SHIFT_82599;
1256		cc.shift -= IXGBE_INCVAL_SHIFT_82599;
1257		IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
1258				BIT(IXGBE_INCPER_SHIFT_82599) | incval);
1259		break;
1260	default:
1261		/* other devices aren't supported */
1262		return;
1263	}
1264
1265	/* update the base incval used to calculate frequency adjustment */
1266	WRITE_ONCE(adapter->base_incval, incval);
1267	smp_mb();
1268
1269	/* need lock to prevent incorrect read while modifying cyclecounter */
1270	spin_lock_irqsave(&adapter->tmreg_lock, flags);
1271	memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc));
1272	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1273}
1274
1275/**
1276 * ixgbe_ptp_init_systime - Initialize SYSTIME registers
1277 * @adapter: the ixgbe private board structure
1278 *
1279 * Initialize and start the SYSTIME registers.
1280 */
1281static void ixgbe_ptp_init_systime(struct ixgbe_adapter *adapter)
1282{
1283	struct ixgbe_hw *hw = &adapter->hw;
1284	u32 tsauxc;
1285
1286	switch (hw->mac.type) {
1287	case ixgbe_mac_X550EM_x:
1288	case ixgbe_mac_x550em_a:
1289	case ixgbe_mac_X550:
1290	case ixgbe_mac_e610:
1291		tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
1292
1293		/* Reset SYSTIME registers to 0 */
1294		IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0);
1295		IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1296		IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1297
1298		/* Reset interrupt settings */
1299		IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS);
1300		IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC);
1301
1302		/* Activate the SYSTIME counter */
1303		IXGBE_WRITE_REG(hw, IXGBE_TSAUXC,
1304				tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME);
1305		break;
1306	case ixgbe_mac_X540:
1307	case ixgbe_mac_82599EB:
1308		/* Reset SYSTIME registers to 0 */
1309		IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1310		IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1311		break;
1312	default:
1313		/* Other devices aren't supported */
1314		return;
1315	}
1316
1317	IXGBE_WRITE_FLUSH(hw);
1318}
1319
1320/**
1321 * ixgbe_ptp_reset
1322 * @adapter: the ixgbe private board structure
1323 *
1324 * When the MAC resets, all the hardware bits for timesync are reset. This
1325 * function is used to re-enable the device for PTP based on current settings.
1326 * We do lose the current clock time, so just reset the cyclecounter to the
1327 * system real clock time.
1328 *
1329 * This function will maintain hwtstamp_config settings, and resets the SDP
1330 * output if it was enabled.
1331 */
1332void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
1333{
1334	struct ixgbe_hw *hw = &adapter->hw;
1335	unsigned long flags;
1336
1337	/* reset the hardware timestamping mode */
1338	ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1339
1340	/* 82598 does not support PTP */
1341	if (hw->mac.type == ixgbe_mac_82598EB)
1342		return;
1343
1344	ixgbe_ptp_start_cyclecounter(adapter);
1345
1346	ixgbe_ptp_init_systime(adapter);
1347
1348	spin_lock_irqsave(&adapter->tmreg_lock, flags);
1349	timecounter_init(&adapter->hw_tc, &adapter->hw_cc,
1350			 ktime_to_ns(ktime_get_real()));
1351	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1352
1353	adapter->last_overflow_check = jiffies;
1354
1355	/* Now that the shift has been calculated and the systime
1356	 * registers reset, (re-)enable the Clock out feature
1357	 */
1358	if (adapter->ptp_setup_sdp)
1359		adapter->ptp_setup_sdp(adapter);
1360}
1361
1362/**
1363 * ixgbe_ptp_create_clock
1364 * @adapter: the ixgbe private adapter structure
1365 *
1366 * This function performs setup of the user entry point function table and
1367 * initializes the PTP clock device, which is used to access the clock-like
1368 * features of the PTP core. It will be called by ixgbe_ptp_init, and may
1369 * reuse a previously initialized clock (such as during a suspend/resume
1370 * cycle).
1371 */
1372static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
1373{
1374	struct net_device *netdev = adapter->netdev;
1375	long err;
1376
1377	/* do nothing if we already have a clock device */
1378	if (!IS_ERR_OR_NULL(adapter->ptp_clock))
1379		return 0;
1380
1381	switch (adapter->hw.mac.type) {
1382	case ixgbe_mac_X540:
1383		snprintf(adapter->ptp_caps.name,
1384			 sizeof(adapter->ptp_caps.name),
1385			 "%s", netdev->name);
1386		adapter->ptp_caps.owner = THIS_MODULE;
1387		adapter->ptp_caps.max_adj = 250000000;
1388		adapter->ptp_caps.n_alarm = 0;
1389		adapter->ptp_caps.n_ext_ts = 0;
1390		adapter->ptp_caps.n_per_out = 0;
1391		adapter->ptp_caps.pps = 1;
1392		adapter->ptp_caps.adjfine = ixgbe_ptp_adjfine_82599;
1393		adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1394		adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1395		adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1396		adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1397		adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X540;
1398		break;
1399	case ixgbe_mac_82599EB:
1400		snprintf(adapter->ptp_caps.name,
1401			 sizeof(adapter->ptp_caps.name),
1402			 "%s", netdev->name);
1403		adapter->ptp_caps.owner = THIS_MODULE;
1404		adapter->ptp_caps.max_adj = 250000000;
1405		adapter->ptp_caps.n_alarm = 0;
1406		adapter->ptp_caps.n_ext_ts = 0;
1407		adapter->ptp_caps.n_per_out = 0;
1408		adapter->ptp_caps.pps = 0;
1409		adapter->ptp_caps.adjfine = ixgbe_ptp_adjfine_82599;
1410		adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1411		adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1412		adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1413		adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1414		break;
1415	case ixgbe_mac_X550:
1416	case ixgbe_mac_X550EM_x:
1417	case ixgbe_mac_x550em_a:
1418	case ixgbe_mac_e610:
1419		snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
1420		adapter->ptp_caps.owner = THIS_MODULE;
1421		adapter->ptp_caps.max_adj = 30000000;
1422		adapter->ptp_caps.n_alarm = 0;
1423		adapter->ptp_caps.n_ext_ts = 0;
1424		adapter->ptp_caps.n_per_out = 0;
1425		adapter->ptp_caps.pps = 1;
1426		adapter->ptp_caps.adjfine = ixgbe_ptp_adjfine_X550;
1427		adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1428		adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1429		adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1430		adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1431		adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X550;
1432		break;
1433	default:
1434		adapter->ptp_clock = NULL;
1435		adapter->ptp_setup_sdp = NULL;
1436		return -EOPNOTSUPP;
1437	}
1438
1439	adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1440						&adapter->pdev->dev);
1441	if (IS_ERR(adapter->ptp_clock)) {
1442		err = PTR_ERR(adapter->ptp_clock);
1443		adapter->ptp_clock = NULL;
1444		e_dev_err("ptp_clock_register failed\n");
1445		return err;
1446	} else if (adapter->ptp_clock)
1447		e_dev_info("registered PHC device on %s\n", netdev->name);
1448
1449	/* set default timestamp mode to disabled here. We do this in
1450	 * create_clock instead of init, because we don't want to override the
1451	 * previous settings during a resume cycle.
1452	 */
1453	adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1454	adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1455
1456	return 0;
1457}
1458
1459/**
1460 * ixgbe_ptp_init
1461 * @adapter: the ixgbe private adapter structure
1462 *
1463 * This function performs the required steps for enabling PTP
1464 * support. If PTP support has already been loaded it simply calls the
1465 * cyclecounter init routine and exits.
1466 */
1467void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
1468{
1469	/* initialize the spin lock first since we can't control when a user
1470	 * will call the entry functions once we have initialized the clock
1471	 * device
1472	 */
1473	spin_lock_init(&adapter->tmreg_lock);
1474
1475	/* obtain a PTP device, or re-use an existing device */
1476	if (ixgbe_ptp_create_clock(adapter))
1477		return;
1478
1479	/* we have a clock so we can initialize work now */
1480	INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
1481
1482	/* reset the PTP related hardware bits */
1483	ixgbe_ptp_reset(adapter);
1484
1485	/* enter the IXGBE_PTP_RUNNING state */
1486	set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
1487
1488	return;
1489}
1490
1491/**
1492 * ixgbe_ptp_suspend - stop PTP work items
1493 * @adapter: pointer to adapter struct
1494 *
1495 * this function suspends PTP activity, and prevents more PTP work from being
1496 * generated, but does not destroy the PTP clock device.
1497 */
1498void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
1499{
1500	/* Leave the IXGBE_PTP_RUNNING state. */
1501	if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1502		return;
1503
1504	adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
1505	if (adapter->ptp_setup_sdp)
1506		adapter->ptp_setup_sdp(adapter);
1507
1508	/* ensure that we cancel any pending PTP Tx work item in progress */
1509	cancel_work_sync(&adapter->ptp_tx_work);
1510	ixgbe_ptp_clear_tx_timestamp(adapter);
1511}
1512
1513/**
1514 * ixgbe_ptp_stop - close the PTP device
1515 * @adapter: pointer to adapter struct
1516 *
1517 * completely destroy the PTP device, should only be called when the device is
1518 * being fully closed.
1519 */
1520void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
1521{
1522	/* first, suspend PTP activity */
1523	ixgbe_ptp_suspend(adapter);
1524
1525	/* disable the PTP clock device */
1526	if (adapter->ptp_clock) {
1527		ptp_clock_unregister(adapter->ptp_clock);
1528		adapter->ptp_clock = NULL;
1529		e_dev_info("removed PHC on %s\n",
1530			   adapter->netdev->name);
1531	}
1532}