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ixgbe_phy.c
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linux-6.19.14/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 1999 - 2024 Intel Corporation. */ 3 4#include <linux/pci.h> 5#include <linux/delay.h> 6#include <linux/iopoll.h> 7#include <linux/sched.h> 8 9#include "ixgbe.h" 10#include "ixgbe_phy.h" 11 12static void ixgbe_i2c_start(struct ixgbe_hw *hw); 13static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 14static int ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 15static int ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 16static int ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 17static int ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 18static int ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 19static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 20static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 21static int ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 22static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 23static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 24static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 25static int ixgbe_get_phy_id(struct ixgbe_hw *hw); 26static int ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 27 28/** 29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 30 * @hw: pointer to the hardware structure 31 * @byte: byte to send 32 * 33 * Returns an error code on error. 34 **/ 35static int ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 36{ 37 int status; 38 39 status = ixgbe_clock_out_i2c_byte(hw, byte); 40 if (status) 41 return status; 42 return ixgbe_get_i2c_ack(hw); 43} 44 45/** 46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 47 * @hw: pointer to the hardware structure 48 * @byte: pointer to a u8 to receive the byte 49 * 50 * Returns an error code on error. 51 **/ 52static int ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 53{ 54 int status; 55 56 status = ixgbe_clock_in_i2c_byte(hw, byte); 57 if (status) 58 return status; 59 /* ACK */ 60 return ixgbe_clock_out_i2c_bit(hw, false); 61} 62 63/** 64 * ixgbe_ones_comp_byte_add - Perform one's complement addition 65 * @add1: addend 1 66 * @add2: addend 2 67 * 68 * Returns one's complement 8-bit sum. 69 **/ 70static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 71{ 72 u16 sum = add1 + add2; 73 74 sum = (sum & 0xFF) + (sum >> 8); 75 return sum & 0xFF; 76} 77 78/** 79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 80 * @hw: pointer to the hardware structure 81 * @addr: I2C bus address to read from 82 * @reg: I2C device register to read from 83 * @val: pointer to location to receive read value 84 * @lock: true if to take and release semaphore 85 * 86 * Returns an error code on error. 87 */ 88int ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 89 u16 reg, u16 *val, bool lock) 90{ 91 u32 swfw_mask = hw->phy.phy_semaphore_mask; 92 int max_retry = 3; 93 int retry = 0; 94 u8 csum_byte; 95 u8 high_bits; 96 u8 low_bits; 97 u8 reg_high; 98 u8 csum; 99 100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 102 csum = ~csum; 103 do { 104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 105 return -EBUSY; 106 ixgbe_i2c_start(hw); 107 /* Device Address and write indication */ 108 if (ixgbe_out_i2c_byte_ack(hw, addr)) 109 goto fail; 110 /* Write bits 14:8 */ 111 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 112 goto fail; 113 /* Write bits 7:0 */ 114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 115 goto fail; 116 /* Write csum */ 117 if (ixgbe_out_i2c_byte_ack(hw, csum)) 118 goto fail; 119 /* Re-start condition */ 120 ixgbe_i2c_start(hw); 121 /* Device Address and read indication */ 122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 123 goto fail; 124 /* Get upper bits */ 125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 126 goto fail; 127 /* Get low bits */ 128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 129 goto fail; 130 /* Get csum */ 131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 132 goto fail; 133 /* NACK */ 134 if (ixgbe_clock_out_i2c_bit(hw, false)) 135 goto fail; 136 ixgbe_i2c_stop(hw); 137 if (lock) 138 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 139 *val = (high_bits << 8) | low_bits; 140 return 0; 141 142fail: 143 ixgbe_i2c_bus_clear(hw); 144 if (lock) 145 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 146 retry++; 147 if (retry < max_retry) 148 hw_dbg(hw, "I2C byte read combined error - Retry.\n"); 149 else 150 hw_dbg(hw, "I2C byte read combined error.\n"); 151 } while (retry < max_retry); 152 153 return -EIO; 154} 155 156/** 157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 158 * @hw: pointer to the hardware structure 159 * @addr: I2C bus address to write to 160 * @reg: I2C device register to write to 161 * @val: value to write 162 * @lock: true if to take and release semaphore 163 * 164 * Returns an error code on error. 165 */ 166int ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 167 u16 reg, u16 val, bool lock) 168{ 169 u32 swfw_mask = hw->phy.phy_semaphore_mask; 170 int max_retry = 3; 171 int retry = 0; 172 u8 reg_high; 173 u8 csum; 174 175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 179 csum = ~csum; 180 do { 181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 182 return -EBUSY; 183 ixgbe_i2c_start(hw); 184 /* Device Address and write indication */ 185 if (ixgbe_out_i2c_byte_ack(hw, addr)) 186 goto fail; 187 /* Write bits 14:8 */ 188 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 189 goto fail; 190 /* Write bits 7:0 */ 191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 192 goto fail; 193 /* Write data 15:8 */ 194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 195 goto fail; 196 /* Write data 7:0 */ 197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 198 goto fail; 199 /* Write csum */ 200 if (ixgbe_out_i2c_byte_ack(hw, csum)) 201 goto fail; 202 ixgbe_i2c_stop(hw); 203 if (lock) 204 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 205 return 0; 206 207fail: 208 ixgbe_i2c_bus_clear(hw); 209 if (lock) 210 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 211 retry++; 212 if (retry < max_retry) 213 hw_dbg(hw, "I2C byte write combined error - Retry.\n"); 214 else 215 hw_dbg(hw, "I2C byte write combined error.\n"); 216 } while (retry < max_retry); 217 218 return -EIO; 219} 220 221/** 222 * ixgbe_probe_phy - Probe a single address for a PHY 223 * @hw: pointer to hardware structure 224 * @phy_addr: PHY address to probe 225 * 226 * Returns true if PHY found 227 **/ 228static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 229{ 230 u16 ext_ability = 0; 231 232 hw->phy.mdio.prtad = phy_addr; 233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0) 234 return false; 235 236 if (ixgbe_get_phy_id(hw)) 237 return false; 238 239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 240 241 if (hw->phy.type == ixgbe_phy_unknown) { 242 hw->phy.ops.read_reg(hw, 243 MDIO_PMA_EXTABLE, 244 MDIO_MMD_PMAPMD, 245 &ext_ability); 246 if (ext_ability & 247 (MDIO_PMA_EXTABLE_10GBT | 248 MDIO_PMA_EXTABLE_1000BT)) 249 hw->phy.type = ixgbe_phy_cu_unknown; 250 else 251 hw->phy.type = ixgbe_phy_generic; 252 } 253 254 return true; 255} 256 257/** 258 * ixgbe_identify_phy_generic - Get physical layer module 259 * @hw: pointer to hardware structure 260 * 261 * Determines the physical layer module found on the current adapter. 262 **/ 263int ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 264{ 265 u32 status = -EFAULT; 266 u32 phy_addr; 267 268 if (!hw->phy.phy_semaphore_mask) { 269 if (hw->bus.lan_id) 270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 271 else 272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 273 } 274 275 if (hw->phy.type != ixgbe_phy_unknown) 276 return 0; 277 278 if (hw->phy.nw_mng_if_sel) { 279 phy_addr = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD, 280 hw->phy.nw_mng_if_sel); 281 if (ixgbe_probe_phy(hw, phy_addr)) 282 return 0; 283 else 284 return -EFAULT; 285 } 286 287 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 288 if (ixgbe_probe_phy(hw, phy_addr)) { 289 status = 0; 290 break; 291 } 292 } 293 294 /* Certain media types do not have a phy so an address will not 295 * be found and the code will take this path. Caller has to 296 * decide if it is an error or not. 297 */ 298 if (status) 299 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 300 301 return status; 302} 303 304/** 305 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 306 * @hw: pointer to the hardware structure 307 * 308 * This function checks the MMNGC.MNG_VETO bit to see if there are 309 * any constraints on link from manageability. For MAC's that don't 310 * have this bit just return false since the link can not be blocked 311 * via this method. 312 **/ 313bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 314{ 315 u32 mmngc; 316 317 /* If we don't have this bit, it can't be blocking */ 318 if (hw->mac.type == ixgbe_mac_82598EB) 319 return false; 320 321 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 322 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 323 hw_dbg(hw, "MNG_VETO bit detected.\n"); 324 return true; 325 } 326 327 return false; 328} 329 330/** 331 * ixgbe_get_phy_id - Get the phy type 332 * @hw: pointer to hardware structure 333 * 334 **/ 335static int ixgbe_get_phy_id(struct ixgbe_hw *hw) 336{ 337 u16 phy_id_high = 0; 338 u16 phy_id_low = 0; 339 int status; 340 341 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, 342 &phy_id_high); 343 344 if (!status) { 345 hw->phy.id = (u32)(phy_id_high << 16); 346 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, 347 &phy_id_low); 348 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 349 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 350 } 351 return status; 352} 353 354/** 355 * ixgbe_get_phy_type_from_id - Get the phy type 356 * @phy_id: hardware phy id 357 * 358 **/ 359static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 360{ 361 enum ixgbe_phy_type phy_type; 362 363 switch (phy_id) { 364 case TN1010_PHY_ID: 365 phy_type = ixgbe_phy_tn; 366 break; 367 case X550_PHY_ID2: 368 case X550_PHY_ID3: 369 case X540_PHY_ID: 370 phy_type = ixgbe_phy_aq; 371 break; 372 case QT2022_PHY_ID: 373 phy_type = ixgbe_phy_qt; 374 break; 375 case ATH_PHY_ID: 376 phy_type = ixgbe_phy_nl; 377 break; 378 case X557_PHY_ID: 379 case X557_PHY_ID2: 380 phy_type = ixgbe_phy_x550em_ext_t; 381 break; 382 case BCM54616S_E_PHY_ID: 383 phy_type = ixgbe_phy_ext_1g_t; 384 break; 385 default: 386 phy_type = ixgbe_phy_unknown; 387 break; 388 } 389 390 return phy_type; 391} 392 393/** 394 * ixgbe_reset_phy_generic - Performs a PHY reset 395 * @hw: pointer to hardware structure 396 **/ 397int ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 398{ 399 u32 i; 400 u16 ctrl = 0; 401 int status = 0; 402 403 if (hw->phy.type == ixgbe_phy_unknown) 404 status = ixgbe_identify_phy_generic(hw); 405 406 if (status != 0 || hw->phy.type == ixgbe_phy_none) 407 return status; 408 409 /* Don't reset PHY if it's shut down due to overtemp. */ 410 if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw)) 411 return 0; 412 413 /* Blocked by MNG FW so bail */ 414 if (ixgbe_check_reset_blocked(hw)) 415 return 0; 416 417 /* 418 * Perform soft PHY reset to the PHY_XS. 419 * This will cause a soft reset to the PHY 420 */ 421 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 422 MDIO_MMD_PHYXS, 423 MDIO_CTRL1_RESET); 424 425 /* 426 * Poll for reset bit to self-clear indicating reset is complete. 427 * Some PHYs could take up to 3 seconds to complete and need about 428 * 1.7 usec delay after the reset is complete. 429 */ 430 for (i = 0; i < 30; i++) { 431 msleep(100); 432 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 433 status = hw->phy.ops.read_reg(hw, 434 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 435 MDIO_MMD_PMAPMD, &ctrl); 436 if (status) 437 return status; 438 439 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 440 udelay(2); 441 break; 442 } 443 } else { 444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, 445 MDIO_MMD_PHYXS, &ctrl); 446 if (status) 447 return status; 448 449 if (!(ctrl & MDIO_CTRL1_RESET)) { 450 udelay(2); 451 break; 452 } 453 } 454 } 455 456 if (ctrl & MDIO_CTRL1_RESET) { 457 hw_dbg(hw, "PHY reset polling failed to complete.\n"); 458 return -EIO; 459 } 460 461 return 0; 462} 463 464/** 465 * ixgbe_read_phy_reg_mdi - read PHY register 466 * @hw: pointer to hardware structure 467 * @reg_addr: 32 bit address of PHY register to read 468 * @device_type: 5 bit device type 469 * @phy_data: Pointer to read data from PHY register 470 * 471 * Reads a value from a specified PHY register without the SWFW lock 472 **/ 473int ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 474 u16 *phy_data) 475{ 476 u32 i, data, command; 477 478 /* Setup and write the address cycle command */ 479 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 480 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 481 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 482 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 483 484 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 485 486 /* Check every 10 usec to see if the address cycle completed. 487 * The MDI Command bit will clear when the operation is 488 * complete 489 */ 490 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 491 udelay(10); 492 493 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 494 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 495 break; 496 } 497 498 499 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 500 hw_dbg(hw, "PHY address command did not complete.\n"); 501 return -EIO; 502 } 503 504 /* Address cycle complete, setup and write the read 505 * command 506 */ 507 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 508 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 509 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 510 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 511 512 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 513 514 /* Check every 10 usec to see if the address cycle 515 * completed. The MDI Command bit will clear when the 516 * operation is complete 517 */ 518 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 519 udelay(10); 520 521 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 522 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 523 break; 524 } 525 526 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 527 hw_dbg(hw, "PHY read command didn't complete\n"); 528 return -EIO; 529 } 530 531 /* Read operation is complete. Get the data 532 * from MSRWD 533 */ 534 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 535 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 536 *phy_data = (u16)(data); 537 538 return 0; 539} 540 541/** 542 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 543 * using the SWFW lock - this function is needed in most cases 544 * @hw: pointer to hardware structure 545 * @reg_addr: 32 bit address of PHY register to read 546 * @device_type: 5 bit device type 547 * @phy_data: Pointer to read data from PHY register 548 **/ 549int ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 550 u32 device_type, u16 *phy_data) 551{ 552 u32 gssr = hw->phy.phy_semaphore_mask; 553 int status; 554 555 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 556 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 557 phy_data); 558 hw->mac.ops.release_swfw_sync(hw, gssr); 559 } else { 560 return -EBUSY; 561 } 562 563 return status; 564} 565 566/** 567 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 568 * without SWFW lock 569 * @hw: pointer to hardware structure 570 * @reg_addr: 32 bit PHY register to write 571 * @device_type: 5 bit device type 572 * @phy_data: Data to write to the PHY register 573 **/ 574int ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 575 u16 phy_data) 576{ 577 u32 i, command; 578 579 /* Put the data in the MDI single read and write data register*/ 580 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 581 582 /* Setup and write the address cycle command */ 583 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 584 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 585 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 586 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 587 588 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 589 590 /* 591 * Check every 10 usec to see if the address cycle completed. 592 * The MDI Command bit will clear when the operation is 593 * complete 594 */ 595 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 596 udelay(10); 597 598 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 599 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 600 break; 601 } 602 603 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 604 hw_dbg(hw, "PHY address cmd didn't complete\n"); 605 return -EIO; 606 } 607 608 /* 609 * Address cycle complete, setup and write the write 610 * command 611 */ 612 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 613 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 614 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 615 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 616 617 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 618 619 /* Check every 10 usec to see if the address cycle 620 * completed. The MDI Command bit will clear when the 621 * operation is complete 622 */ 623 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 624 udelay(10); 625 626 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 627 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 628 break; 629 } 630 631 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 632 hw_dbg(hw, "PHY write cmd didn't complete\n"); 633 return -EIO; 634 } 635 636 return 0; 637} 638 639/** 640 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 641 * using SWFW lock- this function is needed in most cases 642 * @hw: pointer to hardware structure 643 * @reg_addr: 32 bit PHY register to write 644 * @device_type: 5 bit device type 645 * @phy_data: Data to write to the PHY register 646 **/ 647int ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 648 u32 device_type, u16 phy_data) 649{ 650 u32 gssr = hw->phy.phy_semaphore_mask; 651 int status; 652 653 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 654 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 655 phy_data); 656 hw->mac.ops.release_swfw_sync(hw, gssr); 657 } else { 658 return -EBUSY; 659 } 660 661 return status; 662} 663 664#define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr) 665 666/** 667 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout 668 * @hw: pointer to hardware structure 669 * @cmd: command register value to write 670 **/ 671static int ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd) 672{ 673 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd); 674 675 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd, 676 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10, 677 10 * IXGBE_MDIO_COMMAND_TIMEOUT); 678} 679 680/** 681 * ixgbe_mii_bus_read_generic_c22 - Read a clause 22 register with gssr flags 682 * @hw: pointer to hardware structure 683 * @addr: address 684 * @regnum: register number 685 * @gssr: semaphore flags to acquire 686 **/ 687static int ixgbe_mii_bus_read_generic_c22(struct ixgbe_hw *hw, int addr, 688 int regnum, u32 gssr) 689{ 690 u32 hwaddr, cmd; 691 int data; 692 693 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 694 return -EBUSY; 695 696 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT; 697 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT; 698 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | 699 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND; 700 701 data = ixgbe_msca_cmd(hw, cmd); 702 if (data < 0) 703 goto mii_bus_read_done; 704 705 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 706 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0); 707 708mii_bus_read_done: 709 hw->mac.ops.release_swfw_sync(hw, gssr); 710 return data; 711} 712 713/** 714 * ixgbe_mii_bus_read_generic_c45 - Read a clause 45 register with gssr flags 715 * @hw: pointer to hardware structure 716 * @addr: address 717 * @devad: device address to read 718 * @regnum: register number 719 * @gssr: semaphore flags to acquire 720 **/ 721static int ixgbe_mii_bus_read_generic_c45(struct ixgbe_hw *hw, int addr, 722 int devad, int regnum, u32 gssr) 723{ 724 u32 hwaddr, cmd; 725 int data; 726 727 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 728 return -EBUSY; 729 730 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT; 731 hwaddr |= devad << 16 | regnum; 732 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND; 733 734 data = ixgbe_msca_cmd(hw, cmd); 735 if (data < 0) 736 goto mii_bus_read_done; 737 738 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND; 739 data = ixgbe_msca_cmd(hw, cmd); 740 if (data < 0) 741 goto mii_bus_read_done; 742 743 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 744 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0); 745 746mii_bus_read_done: 747 hw->mac.ops.release_swfw_sync(hw, gssr); 748 return data; 749} 750 751/** 752 * ixgbe_mii_bus_write_generic_c22 - Write a clause 22 register with gssr flags 753 * @hw: pointer to hardware structure 754 * @addr: address 755 * @regnum: register number 756 * @val: value to write 757 * @gssr: semaphore flags to acquire 758 **/ 759static int ixgbe_mii_bus_write_generic_c22(struct ixgbe_hw *hw, int addr, 760 int regnum, u16 val, u32 gssr) 761{ 762 u32 hwaddr, cmd; 763 int err; 764 765 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 766 return -EBUSY; 767 768 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val); 769 770 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT; 771 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT; 772 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE | 773 IXGBE_MSCA_MDI_COMMAND; 774 775 err = ixgbe_msca_cmd(hw, cmd); 776 777 hw->mac.ops.release_swfw_sync(hw, gssr); 778 return err; 779} 780 781/** 782 * ixgbe_mii_bus_write_generic_c45 - Write a clause 45 register with gssr flags 783 * @hw: pointer to hardware structure 784 * @addr: address 785 * @devad: device address to read 786 * @regnum: register number 787 * @val: value to write 788 * @gssr: semaphore flags to acquire 789 **/ 790static int ixgbe_mii_bus_write_generic_c45(struct ixgbe_hw *hw, int addr, 791 int devad, int regnum, u16 val, 792 u32 gssr) 793{ 794 u32 hwaddr, cmd; 795 int err; 796 797 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 798 return -EBUSY; 799 800 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val); 801 802 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT; 803 hwaddr |= devad << 16 | regnum; 804 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND; 805 806 err = ixgbe_msca_cmd(hw, cmd); 807 if (err < 0) 808 goto mii_bus_write_done; 809 810 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND; 811 err = ixgbe_msca_cmd(hw, cmd); 812 813mii_bus_write_done: 814 hw->mac.ops.release_swfw_sync(hw, gssr); 815 return err; 816} 817 818/** 819 * ixgbe_mii_bus_read_c22 - Read a clause 22 register 820 * @bus: pointer to mii_bus structure which points to our driver private 821 * @addr: address 822 * @regnum: register number 823 **/ 824static int ixgbe_mii_bus_read_c22(struct mii_bus *bus, int addr, int regnum) 825{ 826 struct ixgbe_adapter *adapter = bus->priv; 827 struct ixgbe_hw *hw = &adapter->hw; 828 u32 gssr = hw->phy.phy_semaphore_mask; 829 830 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr); 831} 832 833/** 834 * ixgbe_mii_bus_read_c45 - Read a clause 45 register 835 * @bus: pointer to mii_bus structure which points to our driver private 836 * @devad: device address to read 837 * @addr: address 838 * @regnum: register number 839 **/ 840static int ixgbe_mii_bus_read_c45(struct mii_bus *bus, int devad, int addr, 841 int regnum) 842{ 843 struct ixgbe_adapter *adapter = bus->priv; 844 struct ixgbe_hw *hw = &adapter->hw; 845 u32 gssr = hw->phy.phy_semaphore_mask; 846 847 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr); 848} 849 850/** 851 * ixgbe_mii_bus_write_c22 - Write a clause 22 register 852 * @bus: pointer to mii_bus structure which points to our driver private 853 * @addr: address 854 * @regnum: register number 855 * @val: value to write 856 **/ 857static int ixgbe_mii_bus_write_c22(struct mii_bus *bus, int addr, int regnum, 858 u16 val) 859{ 860 struct ixgbe_adapter *adapter = bus->priv; 861 struct ixgbe_hw *hw = &adapter->hw; 862 u32 gssr = hw->phy.phy_semaphore_mask; 863 864 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr); 865} 866 867/** 868 * ixgbe_mii_bus_write_c45 - Write a clause 45 register 869 * @bus: pointer to mii_bus structure which points to our driver private 870 * @addr: address 871 * @devad: device address to read 872 * @regnum: register number 873 * @val: value to write 874 **/ 875static int ixgbe_mii_bus_write_c45(struct mii_bus *bus, int addr, int devad, 876 int regnum, u16 val) 877{ 878 struct ixgbe_adapter *adapter = bus->priv; 879 struct ixgbe_hw *hw = &adapter->hw; 880 u32 gssr = hw->phy.phy_semaphore_mask; 881 882 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val, 883 gssr); 884} 885 886/** 887 * ixgbe_x550em_a_mii_bus_read_c22 - Read a clause 22 register on x550em_a 888 * @bus: pointer to mii_bus structure which points to our driver private 889 * @addr: address 890 * @regnum: register number 891 **/ 892static int ixgbe_x550em_a_mii_bus_read_c22(struct mii_bus *bus, int addr, 893 int regnum) 894{ 895 struct ixgbe_adapter *adapter = bus->priv; 896 struct ixgbe_hw *hw = &adapter->hw; 897 u32 gssr = hw->phy.phy_semaphore_mask; 898 899 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM; 900 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr); 901} 902 903/** 904 * ixgbe_x550em_a_mii_bus_read_c45 - Read a clause 45 register on x550em_a 905 * @bus: pointer to mii_bus structure which points to our driver private 906 * @addr: address 907 * @devad: device address to read 908 * @regnum: register number 909 **/ 910static int ixgbe_x550em_a_mii_bus_read_c45(struct mii_bus *bus, int addr, 911 int devad, int regnum) 912{ 913 struct ixgbe_adapter *adapter = bus->priv; 914 struct ixgbe_hw *hw = &adapter->hw; 915 u32 gssr = hw->phy.phy_semaphore_mask; 916 917 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM; 918 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr); 919} 920 921/** 922 * ixgbe_x550em_a_mii_bus_write_c22 - Write a clause 22 register on x550em_a 923 * @bus: pointer to mii_bus structure which points to our driver private 924 * @addr: address 925 * @regnum: register number 926 * @val: value to write 927 **/ 928static int ixgbe_x550em_a_mii_bus_write_c22(struct mii_bus *bus, int addr, 929 int regnum, u16 val) 930{ 931 struct ixgbe_adapter *adapter = bus->priv; 932 struct ixgbe_hw *hw = &adapter->hw; 933 u32 gssr = hw->phy.phy_semaphore_mask; 934 935 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM; 936 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr); 937} 938 939/** 940 * ixgbe_x550em_a_mii_bus_write_c45 - Write a clause 45 register on x550em_a 941 * @bus: pointer to mii_bus structure which points to our driver private 942 * @addr: address 943 * @devad: device address to read 944 * @regnum: register number 945 * @val: value to write 946 **/ 947static int ixgbe_x550em_a_mii_bus_write_c45(struct mii_bus *bus, int addr, 948 int devad, int regnum, u16 val) 949{ 950 struct ixgbe_adapter *adapter = bus->priv; 951 struct ixgbe_hw *hw = &adapter->hw; 952 u32 gssr = hw->phy.phy_semaphore_mask; 953 954 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM; 955 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val, 956 gssr); 957} 958 959/** 960 * ixgbe_get_first_secondary_devfn - get first device downstream of root port 961 * @devfn: PCI_DEVFN of root port on domain 0, bus 0 962 * 963 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root 964 * on domain 0, bus 0, devfn = 'devfn' 965 **/ 966static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn) 967{ 968 struct pci_dev *rp_pdev; 969 int bus; 970 971 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn); 972 if (rp_pdev && rp_pdev->subordinate) { 973 bus = rp_pdev->subordinate->number; 974 pci_dev_put(rp_pdev); 975 return pci_get_domain_bus_and_slot(0, bus, 0); 976 } 977 978 pci_dev_put(rp_pdev); 979 return NULL; 980} 981 982/** 983 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function? 984 * @hw: pointer to hardware structure 985 * 986 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in 987 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a, 988 * but we only want to register one MDIO bus. 989 **/ 990static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw) 991{ 992 struct ixgbe_adapter *adapter = hw->back; 993 struct pci_dev *pdev = adapter->pdev; 994 struct pci_dev *func0_pdev; 995 bool has_mii = false; 996 997 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices 998 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0 999 * It's not valid for function 0 to be disabled and function 1 is up, 1000 * so the lowest numbered ixgbe dev will be device 0 function 0 on one 1001 * of those two root ports 1002 */ 1003 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0)); 1004 if (func0_pdev) { 1005 if (func0_pdev == pdev) 1006 has_mii = true; 1007 goto out; 1008 } 1009 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0)); 1010 if (func0_pdev == pdev) 1011 has_mii = true; 1012 1013out: 1014 pci_dev_put(func0_pdev); 1015 return has_mii; 1016} 1017 1018/** 1019 * ixgbe_mii_bus_init - mii_bus structure setup 1020 * @hw: pointer to hardware structure 1021 * 1022 * Returns 0 on success, negative on failure 1023 * 1024 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter 1025 **/ 1026int ixgbe_mii_bus_init(struct ixgbe_hw *hw) 1027{ 1028 int (*write_c22)(struct mii_bus *bus, int addr, int regnum, u16 val); 1029 int (*read_c22)(struct mii_bus *bus, int addr, int regnum); 1030 int (*write_c45)(struct mii_bus *bus, int addr, int devad, int regnum, 1031 u16 val); 1032 int (*read_c45)(struct mii_bus *bus, int addr, int devad, int regnum); 1033 struct ixgbe_adapter *adapter = hw->back; 1034 struct pci_dev *pdev = adapter->pdev; 1035 struct device *dev = &adapter->netdev->dev; 1036 struct mii_bus *bus; 1037 1038 switch (hw->device_id) { 1039 /* C3000 SoCs */ 1040 case IXGBE_DEV_ID_X550EM_A_KR: 1041 case IXGBE_DEV_ID_X550EM_A_KR_L: 1042 case IXGBE_DEV_ID_X550EM_A_SFP_N: 1043 case IXGBE_DEV_ID_X550EM_A_SGMII: 1044 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 1045 case IXGBE_DEV_ID_X550EM_A_10G_T: 1046 case IXGBE_DEV_ID_X550EM_A_SFP: 1047 case IXGBE_DEV_ID_X550EM_A_1G_T: 1048 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 1049 if (!ixgbe_x550em_a_has_mii(hw)) 1050 return 0; 1051 read_c22 = ixgbe_x550em_a_mii_bus_read_c22; 1052 write_c22 = ixgbe_x550em_a_mii_bus_write_c22; 1053 read_c45 = ixgbe_x550em_a_mii_bus_read_c45; 1054 write_c45 = ixgbe_x550em_a_mii_bus_write_c45; 1055 break; 1056 default: 1057 read_c22 = ixgbe_mii_bus_read_c22; 1058 write_c22 = ixgbe_mii_bus_write_c22; 1059 read_c45 = ixgbe_mii_bus_read_c45; 1060 write_c45 = ixgbe_mii_bus_write_c45; 1061 break; 1062 } 1063 1064 bus = devm_mdiobus_alloc(dev); 1065 if (!bus) 1066 return -ENOMEM; 1067 1068 bus->read = read_c22; 1069 bus->write = write_c22; 1070 bus->read_c45 = read_c45; 1071 bus->write_c45 = write_c45; 1072 1073 /* Use the position of the device in the PCI hierarchy as the id */ 1074 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name, 1075 pci_name(pdev)); 1076 1077 bus->name = "ixgbe-mdio"; 1078 bus->priv = adapter; 1079 bus->parent = dev; 1080 bus->phy_mask = GENMASK(31, 0); 1081 1082 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22 1083 * unfortunately that causes some clause 22 frames to be sent with 1084 * clause 45 addressing. We don't want that. 1085 */ 1086 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22; 1087 1088 adapter->mii_bus = bus; 1089 return mdiobus_register(bus); 1090} 1091 1092/** 1093 * ixgbe_setup_phy_link_generic - Set and restart autoneg 1094 * @hw: pointer to hardware structure 1095 * 1096 * Restart autonegotiation and PHY and waits for completion. 1097 **/ 1098int ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 1099{ 1100 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1101 ixgbe_link_speed speed; 1102 bool autoneg = false; 1103 int status = 0; 1104 1105 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1106 1107 /* Set or unset auto-negotiation 10G advertisement */ 1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg); 1109 1110 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 1111 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 1112 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 1113 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 1114 1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg); 1116 1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 1118 MDIO_MMD_AN, &autoneg_reg); 1119 1120 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_e610) { 1121 /* Set or unset auto-negotiation 5G advertisement */ 1122 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 1123 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 1124 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 1125 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 1126 1127 /* Set or unset auto-negotiation 2.5G advertisement */ 1128 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 1129 if ((hw->phy.autoneg_advertised & 1130 IXGBE_LINK_SPEED_2_5GB_FULL) && 1131 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 1132 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 1133 } 1134 1135 /* Set or unset auto-negotiation 1G advertisement */ 1136 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 1137 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 1138 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 1139 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 1140 1141 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 1142 MDIO_MMD_AN, autoneg_reg); 1143 1144 /* Set or unset auto-negotiation 100M advertisement */ 1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); 1146 1147 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF); 1148 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 1149 (speed & IXGBE_LINK_SPEED_100_FULL)) 1150 autoneg_reg |= ADVERTISE_100FULL; 1151 1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); 1153 1154 /* Blocked by MNG FW so don't reset PHY */ 1155 if (ixgbe_check_reset_blocked(hw)) 1156 return 0; 1157 1158 /* Restart PHY autonegotiation and wait for completion */ 1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 1160 MDIO_MMD_AN, &autoneg_reg); 1161 1162 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 1163 1164 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 1165 MDIO_MMD_AN, autoneg_reg); 1166 1167 return status; 1168} 1169 1170/** 1171 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 1172 * @hw: pointer to hardware structure 1173 * @speed: new link speed 1174 * @autoneg_wait_to_complete: unused 1175 **/ 1176int ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 1177 ixgbe_link_speed speed, 1178 bool autoneg_wait_to_complete) 1179{ 1180 /* Clear autoneg_advertised and set new values based on input link 1181 * speed. 1182 */ 1183 hw->phy.autoneg_advertised = 0; 1184 1185 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1186 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 1187 1188 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 1189 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 1190 1191 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 1192 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 1193 1194 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1195 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 1196 1197 if (speed & IXGBE_LINK_SPEED_100_FULL) 1198 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 1199 1200 if (speed & IXGBE_LINK_SPEED_10_FULL) 1201 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 1202 1203 /* Setup link based on the new speed settings */ 1204 if (hw->phy.ops.setup_link) 1205 hw->phy.ops.setup_link(hw); 1206 1207 return 0; 1208} 1209 1210/** 1211 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy 1212 * @hw: pointer to hardware structure 1213 * 1214 * Determines the supported link capabilities by reading the PHY auto 1215 * negotiation register. 1216 */ 1217static int ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 1218{ 1219 u16 speed_ability; 1220 int status; 1221 1222 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 1223 &speed_ability); 1224 if (status) 1225 return status; 1226 1227 if (speed_ability & MDIO_SPEED_10G) 1228 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 1229 if (speed_ability & MDIO_PMA_SPEED_1000) 1230 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 1231 if (speed_ability & MDIO_PMA_SPEED_100) 1232 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 1233 1234 switch (hw->mac.type) { 1235 case ixgbe_mac_X550: 1236 case ixgbe_mac_e610: 1237 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 1238 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 1239 break; 1240 case ixgbe_mac_X550EM_x: 1241 case ixgbe_mac_x550em_a: 1242 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 1243 break; 1244 default: 1245 break; 1246 } 1247 1248 return 0; 1249} 1250 1251/** 1252 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 1253 * @hw: pointer to hardware structure 1254 * @speed: pointer to link speed 1255 * @autoneg: boolean auto-negotiation value 1256 */ 1257int ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 1258 ixgbe_link_speed *speed, 1259 bool *autoneg) 1260{ 1261 int status = 0; 1262 1263 *autoneg = true; 1264 if (!hw->phy.speeds_supported) 1265 status = ixgbe_get_copper_speeds_supported(hw); 1266 1267 *speed = hw->phy.speeds_supported; 1268 return status; 1269} 1270 1271/** 1272 * ixgbe_check_phy_link_tnx - Determine link and speed status 1273 * @hw: pointer to hardware structure 1274 * @speed: link speed 1275 * @link_up: status of link 1276 * 1277 * Reads the VS1 register to determine if link is up and the current speed for 1278 * the PHY. 1279 **/ 1280int ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1281 bool *link_up) 1282{ 1283 u32 max_time_out = 10; 1284 u16 phy_speed = 0; 1285 u16 phy_link = 0; 1286 u16 phy_data = 0; 1287 u32 time_out; 1288 int status; 1289 1290 /* Initialize speed and link to default case */ 1291 *link_up = false; 1292 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1293 1294 /* 1295 * Check current speed and link status of the PHY register. 1296 * This is a vendor specific register and may have to 1297 * be changed for other copper PHYs. 1298 */ 1299 for (time_out = 0; time_out < max_time_out; time_out++) { 1300 udelay(10); 1301 status = hw->phy.ops.read_reg(hw, 1302 MDIO_STAT1, 1303 MDIO_MMD_VEND1, 1304 &phy_data); 1305 phy_link = phy_data & 1306 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1307 phy_speed = phy_data & 1308 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1309 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1310 *link_up = true; 1311 if (phy_speed == 1312 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1313 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1314 break; 1315 } 1316 } 1317 1318 return status; 1319} 1320 1321/** 1322 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 1323 * @hw: pointer to hardware structure 1324 * 1325 * Restart autonegotiation and PHY and waits for completion. 1326 * This function always returns success, this is necessary since 1327 * it is called via a function pointer that could call other 1328 * functions that could return an error. 1329 **/ 1330int ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1331{ 1332 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1333 bool autoneg = false; 1334 ixgbe_link_speed speed; 1335 1336 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1337 1338 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1339 /* Set or unset auto-negotiation 10G advertisement */ 1340 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 1341 MDIO_MMD_AN, 1342 &autoneg_reg); 1343 1344 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 1345 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1346 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 1347 1348 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 1349 MDIO_MMD_AN, 1350 autoneg_reg); 1351 } 1352 1353 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1354 /* Set or unset auto-negotiation 1G advertisement */ 1355 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1356 MDIO_MMD_AN, 1357 &autoneg_reg); 1358 1359 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1360 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1361 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1362 1363 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1364 MDIO_MMD_AN, 1365 autoneg_reg); 1366 } 1367 1368 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1369 /* Set or unset auto-negotiation 100M advertisement */ 1370 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 1371 MDIO_MMD_AN, 1372 &autoneg_reg); 1373 1374 autoneg_reg &= ~(ADVERTISE_100FULL | 1375 ADVERTISE_100HALF); 1376 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1377 autoneg_reg |= ADVERTISE_100FULL; 1378 1379 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 1380 MDIO_MMD_AN, 1381 autoneg_reg); 1382 } 1383 1384 /* Blocked by MNG FW so don't reset PHY */ 1385 if (ixgbe_check_reset_blocked(hw)) 1386 return 0; 1387 1388 /* Restart PHY autonegotiation and wait for completion */ 1389 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 1390 MDIO_MMD_AN, &autoneg_reg); 1391 1392 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 1393 1394 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 1395 MDIO_MMD_AN, autoneg_reg); 1396 return 0; 1397} 1398 1399/** 1400 * ixgbe_reset_phy_nl - Performs a PHY reset 1401 * @hw: pointer to hardware structure 1402 **/ 1403int ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1404{ 1405 u16 phy_offset, control, eword, edata, block_crc; 1406 u16 list_offset, data_offset; 1407 bool end_data = false; 1408 u16 phy_data = 0; 1409 int ret_val; 1410 u32 i; 1411 1412 /* Blocked by MNG FW so bail */ 1413 if (ixgbe_check_reset_blocked(hw)) 1414 return 0; 1415 1416 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); 1417 1418 /* reset the PHY and poll for completion */ 1419 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 1420 (phy_data | MDIO_CTRL1_RESET)); 1421 1422 for (i = 0; i < 100; i++) { 1423 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 1424 &phy_data); 1425 if ((phy_data & MDIO_CTRL1_RESET) == 0) 1426 break; 1427 usleep_range(10000, 20000); 1428 } 1429 1430 if ((phy_data & MDIO_CTRL1_RESET) != 0) { 1431 hw_dbg(hw, "PHY reset did not complete.\n"); 1432 return -EIO; 1433 } 1434 1435 /* Get init offsets */ 1436 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1437 &data_offset); 1438 if (ret_val) 1439 return ret_val; 1440 1441 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1442 data_offset++; 1443 while (!end_data) { 1444 /* 1445 * Read control word from PHY init contents offset 1446 */ 1447 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1448 if (ret_val) 1449 goto err_eeprom; 1450 control = FIELD_GET(IXGBE_CONTROL_MASK_NL, eword); 1451 edata = eword & IXGBE_DATA_MASK_NL; 1452 switch (control) { 1453 case IXGBE_DELAY_NL: 1454 data_offset++; 1455 hw_dbg(hw, "DELAY: %d MS\n", edata); 1456 usleep_range(edata * 1000, edata * 2000); 1457 break; 1458 case IXGBE_DATA_NL: 1459 hw_dbg(hw, "DATA:\n"); 1460 data_offset++; 1461 ret_val = hw->eeprom.ops.read(hw, data_offset++, 1462 &phy_offset); 1463 if (ret_val) 1464 goto err_eeprom; 1465 for (i = 0; i < edata; i++) { 1466 ret_val = hw->eeprom.ops.read(hw, data_offset, 1467 &eword); 1468 if (ret_val) 1469 goto err_eeprom; 1470 hw->phy.ops.write_reg(hw, phy_offset, 1471 MDIO_MMD_PMAPMD, eword); 1472 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, 1473 phy_offset); 1474 data_offset++; 1475 phy_offset++; 1476 } 1477 break; 1478 case IXGBE_CONTROL_NL: 1479 data_offset++; 1480 hw_dbg(hw, "CONTROL:\n"); 1481 if (edata == IXGBE_CONTROL_EOL_NL) { 1482 hw_dbg(hw, "EOL\n"); 1483 end_data = true; 1484 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1485 hw_dbg(hw, "SOL\n"); 1486 } else { 1487 hw_dbg(hw, "Bad control value\n"); 1488 return -EIO; 1489 } 1490 break; 1491 default: 1492 hw_dbg(hw, "Bad control type\n"); 1493 return -EIO; 1494 } 1495 } 1496 1497 return ret_val; 1498 1499err_eeprom: 1500 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 1501 return -EIO; 1502} 1503 1504/** 1505 * ixgbe_identify_module_generic - Identifies module type 1506 * @hw: pointer to hardware structure 1507 * 1508 * Determines HW type and calls appropriate function. 1509 **/ 1510int ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1511{ 1512 switch (hw->mac.ops.get_media_type(hw)) { 1513 case ixgbe_media_type_fiber: 1514 return ixgbe_identify_sfp_module_generic(hw); 1515 case ixgbe_media_type_fiber_qsfp: 1516 return ixgbe_identify_qsfp_module_generic(hw); 1517 default: 1518 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1519 return -ENOENT; 1520 } 1521 1522 return -ENOENT; 1523} 1524 1525/** 1526 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1527 * @hw: pointer to hardware structure 1528 * 1529 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1530 **/ 1531int ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1532{ 1533 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1534 struct ixgbe_adapter *adapter = hw->back; 1535 u8 oui_bytes[3] = {0, 0, 0}; 1536 u8 bitrate_nominal = 0; 1537 u8 comp_codes_10g = 0; 1538 u8 comp_codes_1g = 0; 1539 u16 enforce_sfp = 0; 1540 u32 vendor_oui = 0; 1541 u8 identifier = 0; 1542 u8 cable_tech = 0; 1543 u8 cable_spec = 0; 1544 int status; 1545 1546 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1547 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1548 return -ENOENT; 1549 } 1550 1551 /* LAN ID is needed for sfp_type determination */ 1552 hw->mac.ops.set_lan_id(hw); 1553 1554 status = hw->phy.ops.read_i2c_eeprom(hw, 1555 IXGBE_SFF_IDENTIFIER, 1556 &identifier); 1557 1558 if (status) 1559 goto err_read_i2c_eeprom; 1560 1561 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1562 hw->phy.type = ixgbe_phy_sfp_unsupported; 1563 return -EOPNOTSUPP; 1564 } 1565 status = hw->phy.ops.read_i2c_eeprom(hw, 1566 IXGBE_SFF_1GBE_COMP_CODES, 1567 &comp_codes_1g); 1568 1569 if (status) 1570 goto err_read_i2c_eeprom; 1571 1572 status = hw->phy.ops.read_i2c_eeprom(hw, 1573 IXGBE_SFF_10GBE_COMP_CODES, 1574 &comp_codes_10g); 1575 1576 if (status) 1577 goto err_read_i2c_eeprom; 1578 status = hw->phy.ops.read_i2c_eeprom(hw, 1579 IXGBE_SFF_CABLE_TECHNOLOGY, 1580 &cable_tech); 1581 if (status) 1582 goto err_read_i2c_eeprom; 1583 1584 status = hw->phy.ops.read_i2c_eeprom(hw, 1585 IXGBE_SFF_BITRATE_NOMINAL, 1586 &bitrate_nominal); 1587 if (status) 1588 goto err_read_i2c_eeprom; 1589 1590 /* ID Module 1591 * ========= 1592 * 0 SFP_DA_CU 1593 * 1 SFP_SR 1594 * 2 SFP_LR 1595 * 3 SFP_DA_CORE0 - 82599-specific 1596 * 4 SFP_DA_CORE1 - 82599-specific 1597 * 5 SFP_SR/LR_CORE0 - 82599-specific 1598 * 6 SFP_SR/LR_CORE1 - 82599-specific 1599 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1600 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1601 * 9 SFP_1g_cu_CORE0 - 82599-specific 1602 * 10 SFP_1g_cu_CORE1 - 82599-specific 1603 * 11 SFP_1g_sx_CORE0 - 82599-specific 1604 * 12 SFP_1g_sx_CORE1 - 82599-specific 1605 */ 1606 if (hw->mac.type == ixgbe_mac_82598EB) { 1607 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1608 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1609 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1610 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1611 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1612 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1613 else 1614 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1615 } else { 1616 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1617 if (hw->bus.lan_id == 0) 1618 hw->phy.sfp_type = 1619 ixgbe_sfp_type_da_cu_core0; 1620 else 1621 hw->phy.sfp_type = 1622 ixgbe_sfp_type_da_cu_core1; 1623 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1624 hw->phy.ops.read_i2c_eeprom( 1625 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1626 &cable_spec); 1627 if (cable_spec & 1628 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1629 if (hw->bus.lan_id == 0) 1630 hw->phy.sfp_type = 1631 ixgbe_sfp_type_da_act_lmt_core0; 1632 else 1633 hw->phy.sfp_type = 1634 ixgbe_sfp_type_da_act_lmt_core1; 1635 } else { 1636 hw->phy.sfp_type = 1637 ixgbe_sfp_type_unknown; 1638 } 1639 } else if (comp_codes_10g & 1640 (IXGBE_SFF_10GBASESR_CAPABLE | 1641 IXGBE_SFF_10GBASELR_CAPABLE)) { 1642 if (hw->bus.lan_id == 0) 1643 hw->phy.sfp_type = 1644 ixgbe_sfp_type_srlr_core0; 1645 else 1646 hw->phy.sfp_type = 1647 ixgbe_sfp_type_srlr_core1; 1648 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1649 if (hw->bus.lan_id == 0) 1650 hw->phy.sfp_type = 1651 ixgbe_sfp_type_1g_cu_core0; 1652 else 1653 hw->phy.sfp_type = 1654 ixgbe_sfp_type_1g_cu_core1; 1655 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1656 if (hw->bus.lan_id == 0) 1657 hw->phy.sfp_type = 1658 ixgbe_sfp_type_1g_sx_core0; 1659 else 1660 hw->phy.sfp_type = 1661 ixgbe_sfp_type_1g_sx_core1; 1662 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1663 if (hw->bus.lan_id == 0) 1664 hw->phy.sfp_type = 1665 ixgbe_sfp_type_1g_lx_core0; 1666 else 1667 hw->phy.sfp_type = 1668 ixgbe_sfp_type_1g_lx_core1; 1669 /* Support only Ethernet 1000BASE-BX10, checking the Bit Rate 1670 * Nominal Value as per SFF-8472 by convention 1.25 Gb/s should 1671 * be rounded up to 0Dh (13 in units of 100 MBd) for 1000BASE-BX 1672 */ 1673 } else if ((comp_codes_1g & IXGBE_SFF_BASEBX10_CAPABLE) && 1674 (bitrate_nominal == 0xD)) { 1675 if (hw->bus.lan_id == 0) 1676 hw->phy.sfp_type = 1677 ixgbe_sfp_type_1g_bx_core0; 1678 else 1679 hw->phy.sfp_type = 1680 ixgbe_sfp_type_1g_bx_core1; 1681 } else { 1682 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1683 } 1684 } 1685 1686 if (hw->phy.sfp_type != stored_sfp_type) 1687 hw->phy.sfp_setup_needed = true; 1688 1689 /* Determine if the SFP+ PHY is dual speed or not. */ 1690 hw->phy.multispeed_fiber = false; 1691 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1692 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1693 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1694 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1695 hw->phy.multispeed_fiber = true; 1696 1697 /* Determine PHY vendor */ 1698 if (hw->phy.type != ixgbe_phy_nl) { 1699 hw->phy.id = identifier; 1700 status = hw->phy.ops.read_i2c_eeprom(hw, 1701 IXGBE_SFF_VENDOR_OUI_BYTE0, 1702 &oui_bytes[0]); 1703 1704 if (status != 0) 1705 goto err_read_i2c_eeprom; 1706 1707 status = hw->phy.ops.read_i2c_eeprom(hw, 1708 IXGBE_SFF_VENDOR_OUI_BYTE1, 1709 &oui_bytes[1]); 1710 1711 if (status != 0) 1712 goto err_read_i2c_eeprom; 1713 1714 status = hw->phy.ops.read_i2c_eeprom(hw, 1715 IXGBE_SFF_VENDOR_OUI_BYTE2, 1716 &oui_bytes[2]); 1717 1718 if (status != 0) 1719 goto err_read_i2c_eeprom; 1720 1721 vendor_oui = 1722 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1723 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1724 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1725 1726 switch (vendor_oui) { 1727 case IXGBE_SFF_VENDOR_OUI_TYCO: 1728 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1729 hw->phy.type = 1730 ixgbe_phy_sfp_passive_tyco; 1731 break; 1732 case IXGBE_SFF_VENDOR_OUI_FTL: 1733 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1734 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1735 else 1736 hw->phy.type = ixgbe_phy_sfp_ftl; 1737 break; 1738 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1739 hw->phy.type = ixgbe_phy_sfp_avago; 1740 break; 1741 case IXGBE_SFF_VENDOR_OUI_INTEL: 1742 hw->phy.type = ixgbe_phy_sfp_intel; 1743 break; 1744 default: 1745 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1746 hw->phy.type = 1747 ixgbe_phy_sfp_passive_unknown; 1748 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1749 hw->phy.type = 1750 ixgbe_phy_sfp_active_unknown; 1751 else 1752 hw->phy.type = ixgbe_phy_sfp_unknown; 1753 break; 1754 } 1755 } 1756 1757 /* Allow any DA cable vendor */ 1758 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1759 IXGBE_SFF_DA_ACTIVE_CABLE)) 1760 return 0; 1761 1762 /* Verify supported 1G SFP modules */ 1763 if (comp_codes_10g == 0 && 1764 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1765 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1766 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1767 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1768 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1769 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || 1770 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 || 1771 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) { 1772 hw->phy.type = ixgbe_phy_sfp_unsupported; 1773 return -EOPNOTSUPP; 1774 } 1775 1776 /* Anything else 82598-based is supported */ 1777 if (hw->mac.type == ixgbe_mac_82598EB) 1778 return 0; 1779 1780 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1781 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1782 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1783 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1784 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1785 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1786 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1787 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || 1788 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 || 1789 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) { 1790 /* Make sure we're a supported PHY type */ 1791 if (hw->phy.type == ixgbe_phy_sfp_intel) 1792 return 0; 1793 if (hw->allow_unsupported_sfp) { 1794 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1795 return 0; 1796 } 1797 hw_dbg(hw, "SFP+ module not supported\n"); 1798 hw->phy.type = ixgbe_phy_sfp_unsupported; 1799 return -EOPNOTSUPP; 1800 } 1801 return 0; 1802 1803err_read_i2c_eeprom: 1804 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1805 if (hw->phy.type != ixgbe_phy_nl) { 1806 hw->phy.id = 0; 1807 hw->phy.type = ixgbe_phy_unknown; 1808 } 1809 return -ENOENT; 1810} 1811 1812/** 1813 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1814 * @hw: pointer to hardware structure 1815 * 1816 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1817 **/ 1818static int ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1819{ 1820 struct ixgbe_adapter *adapter = hw->back; 1821 int status; 1822 u32 vendor_oui = 0; 1823 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1824 u8 identifier = 0; 1825 u8 comp_codes_1g = 0; 1826 u8 comp_codes_10g = 0; 1827 u8 oui_bytes[3] = {0, 0, 0}; 1828 u16 enforce_sfp = 0; 1829 u8 connector = 0; 1830 u8 cable_length = 0; 1831 u8 device_tech = 0; 1832 bool active_cable = false; 1833 1834 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1835 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1836 return -ENOENT; 1837 } 1838 1839 /* LAN ID is needed for sfp_type determination */ 1840 hw->mac.ops.set_lan_id(hw); 1841 1842 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1843 &identifier); 1844 1845 if (status != 0) 1846 goto err_read_i2c_eeprom; 1847 1848 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1849 hw->phy.type = ixgbe_phy_sfp_unsupported; 1850 return -EOPNOTSUPP; 1851 } 1852 1853 hw->phy.id = identifier; 1854 1855 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1856 &comp_codes_10g); 1857 1858 if (status != 0) 1859 goto err_read_i2c_eeprom; 1860 1861 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1862 &comp_codes_1g); 1863 1864 if (status != 0) 1865 goto err_read_i2c_eeprom; 1866 1867 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1868 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1869 if (hw->bus.lan_id == 0) 1870 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1871 else 1872 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1873 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1874 IXGBE_SFF_10GBASELR_CAPABLE)) { 1875 if (hw->bus.lan_id == 0) 1876 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1877 else 1878 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1879 } else { 1880 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1881 active_cable = true; 1882 1883 if (!active_cable) { 1884 /* check for active DA cables that pre-date 1885 * SFF-8436 v3.6 1886 */ 1887 hw->phy.ops.read_i2c_eeprom(hw, 1888 IXGBE_SFF_QSFP_CONNECTOR, 1889 &connector); 1890 1891 hw->phy.ops.read_i2c_eeprom(hw, 1892 IXGBE_SFF_QSFP_CABLE_LENGTH, 1893 &cable_length); 1894 1895 hw->phy.ops.read_i2c_eeprom(hw, 1896 IXGBE_SFF_QSFP_DEVICE_TECH, 1897 &device_tech); 1898 1899 if ((connector == 1900 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1901 (cable_length > 0) && 1902 ((device_tech >> 4) == 1903 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1904 active_cable = true; 1905 } 1906 1907 if (active_cable) { 1908 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1909 if (hw->bus.lan_id == 0) 1910 hw->phy.sfp_type = 1911 ixgbe_sfp_type_da_act_lmt_core0; 1912 else 1913 hw->phy.sfp_type = 1914 ixgbe_sfp_type_da_act_lmt_core1; 1915 } else { 1916 /* unsupported module type */ 1917 hw->phy.type = ixgbe_phy_sfp_unsupported; 1918 return -EOPNOTSUPP; 1919 } 1920 } 1921 1922 if (hw->phy.sfp_type != stored_sfp_type) 1923 hw->phy.sfp_setup_needed = true; 1924 1925 /* Determine if the QSFP+ PHY is dual speed or not. */ 1926 hw->phy.multispeed_fiber = false; 1927 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1928 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1929 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1930 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1931 hw->phy.multispeed_fiber = true; 1932 1933 /* Determine PHY vendor for optical modules */ 1934 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1935 IXGBE_SFF_10GBASELR_CAPABLE)) { 1936 status = hw->phy.ops.read_i2c_eeprom(hw, 1937 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1938 &oui_bytes[0]); 1939 1940 if (status != 0) 1941 goto err_read_i2c_eeprom; 1942 1943 status = hw->phy.ops.read_i2c_eeprom(hw, 1944 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1945 &oui_bytes[1]); 1946 1947 if (status != 0) 1948 goto err_read_i2c_eeprom; 1949 1950 status = hw->phy.ops.read_i2c_eeprom(hw, 1951 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1952 &oui_bytes[2]); 1953 1954 if (status != 0) 1955 goto err_read_i2c_eeprom; 1956 1957 vendor_oui = 1958 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1959 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1960 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1961 1962 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1963 hw->phy.type = ixgbe_phy_qsfp_intel; 1964 else 1965 hw->phy.type = ixgbe_phy_qsfp_unknown; 1966 1967 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1968 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1969 /* Make sure we're a supported PHY type */ 1970 if (hw->phy.type == ixgbe_phy_qsfp_intel) 1971 return 0; 1972 if (hw->allow_unsupported_sfp) { 1973 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1974 return 0; 1975 } 1976 hw_dbg(hw, "QSFP module not supported\n"); 1977 hw->phy.type = ixgbe_phy_sfp_unsupported; 1978 return -EOPNOTSUPP; 1979 } 1980 return 0; 1981 } 1982 return 0; 1983 1984err_read_i2c_eeprom: 1985 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1986 hw->phy.id = 0; 1987 hw->phy.type = ixgbe_phy_unknown; 1988 1989 return -ENOENT; 1990} 1991 1992/** 1993 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1994 * @hw: pointer to hardware structure 1995 * @list_offset: offset to the SFP ID list 1996 * @data_offset: offset to the SFP data block 1997 * 1998 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1999 * so it returns the offsets to the phy init sequence block. 2000 **/ 2001int ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 2002 u16 *list_offset, 2003 u16 *data_offset) 2004{ 2005 u16 sfp_id; 2006 u16 sfp_type = hw->phy.sfp_type; 2007 2008 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 2009 return -EOPNOTSUPP; 2010 2011 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2012 return -ENOENT; 2013 2014 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 2015 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 2016 return -EOPNOTSUPP; 2017 2018 /* 2019 * Limiting active cables and 1G Phys must be initialized as 2020 * SR modules 2021 */ 2022 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 2023 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 2024 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 2025 sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2026 sfp_type == ixgbe_sfp_type_1g_bx_core0) 2027 sfp_type = ixgbe_sfp_type_srlr_core0; 2028 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 2029 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 2030 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 2031 sfp_type == ixgbe_sfp_type_1g_sx_core1 || 2032 sfp_type == ixgbe_sfp_type_1g_bx_core1) 2033 sfp_type = ixgbe_sfp_type_srlr_core1; 2034 2035 /* Read offset to PHY init contents */ 2036 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 2037 hw_err(hw, "eeprom read at %d failed\n", 2038 IXGBE_PHY_INIT_OFFSET_NL); 2039 return -EIO; 2040 } 2041 2042 if ((!*list_offset) || (*list_offset == 0xFFFF)) 2043 return -EIO; 2044 2045 /* Shift offset to first ID word */ 2046 (*list_offset)++; 2047 2048 /* 2049 * Find the matching SFP ID in the EEPROM 2050 * and program the init sequence 2051 */ 2052 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 2053 goto err_phy; 2054 2055 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 2056 if (sfp_id == sfp_type) { 2057 (*list_offset)++; 2058 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 2059 goto err_phy; 2060 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 2061 hw_dbg(hw, "SFP+ module not supported\n"); 2062 return -EOPNOTSUPP; 2063 } else { 2064 break; 2065 } 2066 } else { 2067 (*list_offset) += 2; 2068 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 2069 goto err_phy; 2070 } 2071 } 2072 2073 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 2074 hw_dbg(hw, "No matching SFP+ module found\n"); 2075 return -EOPNOTSUPP; 2076 } 2077 2078 return 0; 2079 2080err_phy: 2081 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset); 2082 return -EIO; 2083} 2084 2085/** 2086 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 2087 * @hw: pointer to hardware structure 2088 * @byte_offset: EEPROM byte offset to read 2089 * @eeprom_data: value read 2090 * 2091 * Performs byte read operation to SFP module's EEPROM over I2C interface. 2092 **/ 2093int ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2094 u8 *eeprom_data) 2095{ 2096 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2097 IXGBE_I2C_EEPROM_DEV_ADDR, 2098 eeprom_data); 2099} 2100 2101/** 2102 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 2103 * @hw: pointer to hardware structure 2104 * @byte_offset: byte offset at address 0xA2 2105 * @sff8472_data: value read 2106 * 2107 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2108 **/ 2109int ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2110 u8 *sff8472_data) 2111{ 2112 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2113 IXGBE_I2C_EEPROM_DEV_ADDR2, 2114 sff8472_data); 2115} 2116 2117/** 2118 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2119 * @hw: pointer to hardware structure 2120 * @byte_offset: EEPROM byte offset to write 2121 * @eeprom_data: value to write 2122 * 2123 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2124 **/ 2125int ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2126 u8 eeprom_data) 2127{ 2128 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2129 IXGBE_I2C_EEPROM_DEV_ADDR, 2130 eeprom_data); 2131} 2132 2133/** 2134 * ixgbe_is_sfp_probe - Returns true if SFP is being detected 2135 * @hw: pointer to hardware structure 2136 * @offset: eeprom offset to be read 2137 * @addr: I2C address to be read 2138 */ 2139static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2140{ 2141 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2142 offset == IXGBE_SFF_IDENTIFIER && 2143 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2144 return true; 2145 return false; 2146} 2147 2148/** 2149 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2150 * @hw: pointer to hardware structure 2151 * @byte_offset: byte offset to read 2152 * @dev_addr: device address 2153 * @data: value read 2154 * @lock: true if to take and release semaphore 2155 * 2156 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2157 * a specified device address. 2158 */ 2159static int ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2160 u8 dev_addr, u8 *data, bool lock) 2161{ 2162 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2163 u32 max_retry = 10; 2164 bool nack = true; 2165 u32 retry = 0; 2166 int status; 2167 2168 if (hw->mac.type >= ixgbe_mac_X550) 2169 max_retry = 3; 2170 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2171 max_retry = IXGBE_SFP_DETECT_RETRIES; 2172 2173 *data = 0; 2174 2175 do { 2176 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2177 return -EBUSY; 2178 2179 ixgbe_i2c_start(hw); 2180 2181 /* Device Address and write indication */ 2182 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2183 if (status != 0) 2184 goto fail; 2185 2186 status = ixgbe_get_i2c_ack(hw); 2187 if (status != 0) 2188 goto fail; 2189 2190 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2191 if (status != 0) 2192 goto fail; 2193 2194 status = ixgbe_get_i2c_ack(hw); 2195 if (status != 0) 2196 goto fail; 2197 2198 ixgbe_i2c_start(hw); 2199 2200 /* Device Address and read indication */ 2201 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2202 if (status != 0) 2203 goto fail; 2204 2205 status = ixgbe_get_i2c_ack(hw); 2206 if (status != 0) 2207 goto fail; 2208 2209 status = ixgbe_clock_in_i2c_byte(hw, data); 2210 if (status != 0) 2211 goto fail; 2212 2213 status = ixgbe_clock_out_i2c_bit(hw, nack); 2214 if (status != 0) 2215 goto fail; 2216 2217 ixgbe_i2c_stop(hw); 2218 if (lock) 2219 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2220 return 0; 2221 2222fail: 2223 ixgbe_i2c_bus_clear(hw); 2224 if (lock) { 2225 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2226 msleep(100); 2227 } 2228 retry++; 2229 if (retry < max_retry) 2230 hw_dbg(hw, "I2C byte read error - Retrying.\n"); 2231 else 2232 hw_dbg(hw, "I2C byte read error.\n"); 2233 2234 } while (retry < max_retry); 2235 2236 return status; 2237} 2238 2239/** 2240 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2241 * @hw: pointer to hardware structure 2242 * @byte_offset: byte offset to read 2243 * @dev_addr: device address 2244 * @data: value read 2245 * 2246 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2247 * a specified device address. 2248 */ 2249int ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2250 u8 dev_addr, u8 *data) 2251{ 2252 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2253 data, true); 2254} 2255 2256/** 2257 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2258 * @hw: pointer to hardware structure 2259 * @byte_offset: byte offset to read 2260 * @dev_addr: device address 2261 * @data: value read 2262 * 2263 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2264 * a specified device address. 2265 */ 2266int ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2267 u8 dev_addr, u8 *data) 2268{ 2269 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2270 data, false); 2271} 2272 2273/** 2274 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2275 * @hw: pointer to hardware structure 2276 * @byte_offset: byte offset to write 2277 * @dev_addr: device address 2278 * @data: value to write 2279 * @lock: true if to take and release semaphore 2280 * 2281 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2282 * a specified device address. 2283 */ 2284static int ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2285 u8 dev_addr, u8 data, bool lock) 2286{ 2287 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2288 u32 max_retry = 3; 2289 u32 retry = 0; 2290 int status; 2291 2292 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2293 return -EBUSY; 2294 2295 do { 2296 ixgbe_i2c_start(hw); 2297 2298 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2299 if (status != 0) 2300 goto fail; 2301 2302 status = ixgbe_get_i2c_ack(hw); 2303 if (status != 0) 2304 goto fail; 2305 2306 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2307 if (status != 0) 2308 goto fail; 2309 2310 status = ixgbe_get_i2c_ack(hw); 2311 if (status != 0) 2312 goto fail; 2313 2314 status = ixgbe_clock_out_i2c_byte(hw, data); 2315 if (status != 0) 2316 goto fail; 2317 2318 status = ixgbe_get_i2c_ack(hw); 2319 if (status != 0) 2320 goto fail; 2321 2322 ixgbe_i2c_stop(hw); 2323 if (lock) 2324 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2325 return 0; 2326 2327fail: 2328 ixgbe_i2c_bus_clear(hw); 2329 retry++; 2330 if (retry < max_retry) 2331 hw_dbg(hw, "I2C byte write error - Retrying.\n"); 2332 else 2333 hw_dbg(hw, "I2C byte write error.\n"); 2334 } while (retry < max_retry); 2335 2336 if (lock) 2337 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2338 2339 return status; 2340} 2341 2342/** 2343 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2344 * @hw: pointer to hardware structure 2345 * @byte_offset: byte offset to write 2346 * @dev_addr: device address 2347 * @data: value to write 2348 * 2349 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2350 * a specified device address. 2351 */ 2352int ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2353 u8 dev_addr, u8 data) 2354{ 2355 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2356 data, true); 2357} 2358 2359/** 2360 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2361 * @hw: pointer to hardware structure 2362 * @byte_offset: byte offset to write 2363 * @dev_addr: device address 2364 * @data: value to write 2365 * 2366 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2367 * a specified device address. 2368 */ 2369int ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2370 u8 dev_addr, u8 data) 2371{ 2372 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2373 data, false); 2374} 2375 2376/** 2377 * ixgbe_i2c_start - Sets I2C start condition 2378 * @hw: pointer to hardware structure 2379 * 2380 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2381 * Set bit-bang mode on X550 hardware. 2382 **/ 2383static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2384{ 2385 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2386 2387 i2cctl |= IXGBE_I2C_BB_EN(hw); 2388 2389 /* Start condition must begin with data and clock high */ 2390 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2391 ixgbe_raise_i2c_clk(hw, &i2cctl); 2392 2393 /* Setup time for start condition (4.7us) */ 2394 udelay(IXGBE_I2C_T_SU_STA); 2395 2396 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2397 2398 /* Hold time for start condition (4us) */ 2399 udelay(IXGBE_I2C_T_HD_STA); 2400 2401 ixgbe_lower_i2c_clk(hw, &i2cctl); 2402 2403 /* Minimum low period of clock is 4.7 us */ 2404 udelay(IXGBE_I2C_T_LOW); 2405 2406} 2407 2408/** 2409 * ixgbe_i2c_stop - Sets I2C stop condition 2410 * @hw: pointer to hardware structure 2411 * 2412 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2413 * Disables bit-bang mode and negates data output enable on X550 2414 * hardware. 2415 **/ 2416static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2417{ 2418 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2419 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2420 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); 2421 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw); 2422 2423 /* Stop condition must begin with data low and clock high */ 2424 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2425 ixgbe_raise_i2c_clk(hw, &i2cctl); 2426 2427 /* Setup time for stop condition (4us) */ 2428 udelay(IXGBE_I2C_T_SU_STO); 2429 2430 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2431 2432 /* bus free time between stop and start (4.7us)*/ 2433 udelay(IXGBE_I2C_T_BUF); 2434 2435 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2436 i2cctl &= ~bb_en_bit; 2437 i2cctl |= data_oe_bit | clk_oe_bit; 2438 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2439 IXGBE_WRITE_FLUSH(hw); 2440 } 2441} 2442 2443/** 2444 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2445 * @hw: pointer to hardware structure 2446 * @data: data byte to clock in 2447 * 2448 * Clocks in one byte data via I2C data/clock 2449 **/ 2450static int ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2451{ 2452 bool bit = false; 2453 int i; 2454 2455 *data = 0; 2456 for (i = 7; i >= 0; i--) { 2457 ixgbe_clock_in_i2c_bit(hw, &bit); 2458 *data |= bit << i; 2459 } 2460 2461 return 0; 2462} 2463 2464/** 2465 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2466 * @hw: pointer to hardware structure 2467 * @data: data byte clocked out 2468 * 2469 * Clocks out one byte data via I2C data/clock 2470 **/ 2471static int ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2472{ 2473 bool bit = false; 2474 int status; 2475 u32 i2cctl; 2476 int i; 2477 2478 for (i = 7; i >= 0; i--) { 2479 bit = (data >> i) & 0x1; 2480 status = ixgbe_clock_out_i2c_bit(hw, bit); 2481 2482 if (status != 0) 2483 break; 2484 } 2485 2486 /* Release SDA line (set high) */ 2487 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2488 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2489 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw); 2490 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2491 IXGBE_WRITE_FLUSH(hw); 2492 2493 return status; 2494} 2495 2496/** 2497 * ixgbe_get_i2c_ack - Polls for I2C ACK 2498 * @hw: pointer to hardware structure 2499 * 2500 * Clocks in/out one bit via I2C data/clock 2501 **/ 2502static int ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2503{ 2504 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2505 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2506 u32 timeout = 10; 2507 bool ack = true; 2508 int status = 0; 2509 u32 i = 0; 2510 2511 if (data_oe_bit) { 2512 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2513 i2cctl |= data_oe_bit; 2514 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2515 IXGBE_WRITE_FLUSH(hw); 2516 } 2517 ixgbe_raise_i2c_clk(hw, &i2cctl); 2518 2519 /* Minimum high period of clock is 4us */ 2520 udelay(IXGBE_I2C_T_HIGH); 2521 2522 /* Poll for ACK. Note that ACK in I2C spec is 2523 * transition from 1 to 0 */ 2524 for (i = 0; i < timeout; i++) { 2525 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2526 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2527 2528 udelay(1); 2529 if (ack == 0) 2530 break; 2531 } 2532 2533 if (ack == 1) { 2534 hw_dbg(hw, "I2C ack was not received.\n"); 2535 status = -EIO; 2536 } 2537 2538 ixgbe_lower_i2c_clk(hw, &i2cctl); 2539 2540 /* Minimum low period of clock is 4.7 us */ 2541 udelay(IXGBE_I2C_T_LOW); 2542 2543 return status; 2544} 2545 2546/** 2547 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2548 * @hw: pointer to hardware structure 2549 * @data: read data value 2550 * 2551 * Clocks in one bit via I2C data/clock 2552 **/ 2553static int ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2554{ 2555 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2556 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2557 2558 if (data_oe_bit) { 2559 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2560 i2cctl |= data_oe_bit; 2561 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2562 IXGBE_WRITE_FLUSH(hw); 2563 } 2564 ixgbe_raise_i2c_clk(hw, &i2cctl); 2565 2566 /* Minimum high period of clock is 4us */ 2567 udelay(IXGBE_I2C_T_HIGH); 2568 2569 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2570 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2571 2572 ixgbe_lower_i2c_clk(hw, &i2cctl); 2573 2574 /* Minimum low period of clock is 4.7 us */ 2575 udelay(IXGBE_I2C_T_LOW); 2576 2577 return 0; 2578} 2579 2580/** 2581 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2582 * @hw: pointer to hardware structure 2583 * @data: data value to write 2584 * 2585 * Clocks out one bit via I2C data/clock 2586 **/ 2587static int ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2588{ 2589 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2590 int status; 2591 2592 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2593 if (status == 0) { 2594 ixgbe_raise_i2c_clk(hw, &i2cctl); 2595 2596 /* Minimum high period of clock is 4us */ 2597 udelay(IXGBE_I2C_T_HIGH); 2598 2599 ixgbe_lower_i2c_clk(hw, &i2cctl); 2600 2601 /* Minimum low period of clock is 4.7 us. 2602 * This also takes care of the data hold time. 2603 */ 2604 udelay(IXGBE_I2C_T_LOW); 2605 } else { 2606 hw_dbg(hw, "I2C data was not set to %X\n", data); 2607 return -EIO; 2608 } 2609 2610 return 0; 2611} 2612/** 2613 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2614 * @hw: pointer to hardware structure 2615 * @i2cctl: Current value of I2CCTL register 2616 * 2617 * Raises the I2C clock line '0'->'1' 2618 * Negates the I2C clock output enable on X550 hardware. 2619 **/ 2620static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2621{ 2622 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); 2623 u32 i = 0; 2624 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2625 u32 i2cctl_r = 0; 2626 2627 if (clk_oe_bit) { 2628 *i2cctl |= clk_oe_bit; 2629 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2630 } 2631 2632 for (i = 0; i < timeout; i++) { 2633 *i2cctl |= IXGBE_I2C_CLK_OUT(hw); 2634 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2635 IXGBE_WRITE_FLUSH(hw); 2636 /* SCL rise time (1000ns) */ 2637 udelay(IXGBE_I2C_T_RISE); 2638 2639 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2640 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw)) 2641 break; 2642 } 2643} 2644 2645/** 2646 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2647 * @hw: pointer to hardware structure 2648 * @i2cctl: Current value of I2CCTL register 2649 * 2650 * Lowers the I2C clock line '1'->'0' 2651 * Asserts the I2C clock output enable on X550 hardware. 2652 **/ 2653static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2654{ 2655 2656 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw); 2657 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw); 2658 2659 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2660 IXGBE_WRITE_FLUSH(hw); 2661 2662 /* SCL fall time (300ns) */ 2663 udelay(IXGBE_I2C_T_FALL); 2664} 2665 2666/** 2667 * ixgbe_set_i2c_data - Sets the I2C data bit 2668 * @hw: pointer to hardware structure 2669 * @i2cctl: Current value of I2CCTL register 2670 * @data: I2C data value (0 or 1) to set 2671 * 2672 * Sets the I2C data bit 2673 * Asserts the I2C data output enable on X550 hardware. 2674 **/ 2675static int ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2676{ 2677 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2678 2679 if (data) 2680 *i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2681 else 2682 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw); 2683 *i2cctl &= ~data_oe_bit; 2684 2685 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2686 IXGBE_WRITE_FLUSH(hw); 2687 2688 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2689 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2690 2691 if (!data) /* Can't verify data in this case */ 2692 return 0; 2693 if (data_oe_bit) { 2694 *i2cctl |= data_oe_bit; 2695 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2696 IXGBE_WRITE_FLUSH(hw); 2697 } 2698 2699 /* Verify data was set correctly */ 2700 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2701 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2702 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); 2703 return -EIO; 2704 } 2705 2706 return 0; 2707} 2708 2709/** 2710 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2711 * @hw: pointer to hardware structure 2712 * @i2cctl: Current value of I2CCTL register 2713 * 2714 * Returns the I2C data bit value 2715 * Negates the I2C data output enable on X550 hardware. 2716 **/ 2717static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2718{ 2719 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2720 2721 if (data_oe_bit) { 2722 *i2cctl |= data_oe_bit; 2723 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2724 IXGBE_WRITE_FLUSH(hw); 2725 udelay(IXGBE_I2C_T_FALL); 2726 } 2727 2728 if (*i2cctl & IXGBE_I2C_DATA_IN(hw)) 2729 return true; 2730 return false; 2731} 2732 2733/** 2734 * ixgbe_i2c_bus_clear - Clears the I2C bus 2735 * @hw: pointer to hardware structure 2736 * 2737 * Clears the I2C bus by sending nine clock pulses. 2738 * Used when data line is stuck low. 2739 **/ 2740static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2741{ 2742 u32 i2cctl; 2743 u32 i; 2744 2745 ixgbe_i2c_start(hw); 2746 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2747 2748 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2749 2750 for (i = 0; i < 9; i++) { 2751 ixgbe_raise_i2c_clk(hw, &i2cctl); 2752 2753 /* Min high period of clock is 4us */ 2754 udelay(IXGBE_I2C_T_HIGH); 2755 2756 ixgbe_lower_i2c_clk(hw, &i2cctl); 2757 2758 /* Min low period of clock is 4.7us*/ 2759 udelay(IXGBE_I2C_T_LOW); 2760 } 2761 2762 ixgbe_i2c_start(hw); 2763 2764 /* Put the i2c bus back to default state */ 2765 ixgbe_i2c_stop(hw); 2766} 2767 2768/** 2769 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2770 * @hw: pointer to hardware structure 2771 * 2772 * Checks if the LASI temp alarm status was triggered due to overtemp 2773 * 2774 * Return true when an overtemp event detected, otherwise false. 2775 **/ 2776bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2777{ 2778 u16 phy_data = 0; 2779 u32 status; 2780 2781 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2782 return false; 2783 2784 /* Check that the LASI temp alarm status was triggered */ 2785 status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2786 MDIO_MMD_PMAPMD, &phy_data); 2787 if (status) 2788 return false; 2789 2790 return !!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM); 2791} 2792 2793/** ixgbe_set_copper_phy_power - Control power for copper phy 2794 * @hw: pointer to hardware structure 2795 * @on: true for on, false for off 2796 **/ 2797int ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2798{ 2799 u32 status; 2800 u16 reg; 2801 2802 /* Bail if we don't have copper phy */ 2803 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2804 return 0; 2805 2806 if (!on && ixgbe_mng_present(hw)) 2807 return 0; 2808 2809 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®); 2810 if (status) 2811 return status; 2812 2813 if (on) { 2814 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2815 } else { 2816 if (ixgbe_check_reset_blocked(hw)) 2817 return 0; 2818 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2819 } 2820 2821 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg); 2822 return status; 2823}
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