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ixgbe_e610.c
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linux-6.19.14/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2024 Intel Corporation. */ 3 4#include "ixgbe_common.h" 5#include "ixgbe_e610.h" 6#include "ixgbe_x550.h" 7#include "ixgbe_type.h" 8#include "ixgbe_x540.h" 9#include "ixgbe_mbx.h" 10#include "ixgbe_phy.h" 11 12/** 13 * ixgbe_should_retry_aci_send_cmd_execute - decide if ACI command should 14 * be resent 15 * @opcode: ACI opcode 16 * 17 * Check if ACI command should be sent again depending on the provided opcode. 18 * It may happen when CSR is busy during link state changes. 19 * 20 * Return: true if the sending command routine should be repeated, 21 * otherwise false. 22 */ 23static bool ixgbe_should_retry_aci_send_cmd_execute(u16 opcode) 24{ 25 switch (opcode) { 26 case ixgbe_aci_opc_disable_rxen: 27 case ixgbe_aci_opc_get_phy_caps: 28 case ixgbe_aci_opc_get_link_status: 29 case ixgbe_aci_opc_get_link_topo: 30 return true; 31 } 32 33 return false; 34} 35 36/** 37 * ixgbe_aci_send_cmd_execute - execute sending FW Admin Command to FW Admin 38 * Command Interface 39 * @hw: pointer to the HW struct 40 * @desc: descriptor describing the command 41 * @buf: buffer to use for indirect commands (NULL for direct commands) 42 * @buf_size: size of buffer for indirect commands (0 for direct commands) 43 * 44 * Admin Command is sent using CSR by setting descriptor and buffer in specific 45 * registers. 46 * 47 * Return: the exit code of the operation. 48 * * - 0 - success. 49 * * - -EIO - CSR mechanism is not enabled. 50 * * - -EBUSY - CSR mechanism is busy. 51 * * - -EINVAL - buf_size is too big or 52 * invalid argument buf or buf_size. 53 * * - -ETIME - Admin Command X command timeout. 54 * * - -EIO - Admin Command X invalid state of HICR register or 55 * Admin Command failed because of bad opcode was returned or 56 * Admin Command failed with error Y. 57 */ 58static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw, 59 struct libie_aq_desc *desc, 60 void *buf, u16 buf_size) 61{ 62 u16 opcode, buf_tail_size = buf_size % 4; 63 u32 *raw_desc = (u32 *)desc; 64 u32 hicr, i, buf_tail = 0; 65 bool valid_buf = false; 66 67 hw->aci.last_status = LIBIE_AQ_RC_OK; 68 69 /* It's necessary to check if mechanism is enabled */ 70 hicr = IXGBE_READ_REG(hw, IXGBE_PF_HICR); 71 72 if (!(hicr & IXGBE_PF_HICR_EN)) 73 return -EIO; 74 75 if (hicr & IXGBE_PF_HICR_C) { 76 hw->aci.last_status = LIBIE_AQ_RC_EBUSY; 77 return -EBUSY; 78 } 79 80 opcode = le16_to_cpu(desc->opcode); 81 82 if (buf_size > IXGBE_ACI_MAX_BUFFER_SIZE) 83 return -EINVAL; 84 85 if (buf) 86 desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF); 87 88 if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_BUF)) { 89 if ((buf && !buf_size) || 90 (!buf && buf_size)) 91 return -EINVAL; 92 if (buf && buf_size) 93 valid_buf = true; 94 } 95 96 if (valid_buf) { 97 if (buf_tail_size) 98 memcpy(&buf_tail, buf + buf_size - buf_tail_size, 99 buf_tail_size); 100 101 if (((buf_size + 3) & ~0x3) > LIBIE_AQ_LG_BUF) 102 desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB); 103 104 desc->datalen = cpu_to_le16(buf_size); 105 106 if (desc->flags & cpu_to_le16(LIBIE_AQ_FLAG_RD)) { 107 for (i = 0; i < buf_size / 4; i++) 108 IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), ((u32 *)buf)[i]); 109 if (buf_tail_size) 110 IXGBE_WRITE_REG(hw, IXGBE_PF_HIBA(i), buf_tail); 111 } 112 } 113 114 /* Descriptor is written to specific registers */ 115 for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) 116 IXGBE_WRITE_REG(hw, IXGBE_PF_HIDA(i), raw_desc[i]); 117 118 /* SW has to set PF_HICR.C bit and clear PF_HICR.SV and 119 * PF_HICR_EV 120 */ 121 hicr = (IXGBE_READ_REG(hw, IXGBE_PF_HICR) | IXGBE_PF_HICR_C) & 122 ~(IXGBE_PF_HICR_SV | IXGBE_PF_HICR_EV); 123 IXGBE_WRITE_REG(hw, IXGBE_PF_HICR, hicr); 124 125#define MAX_SLEEP_RESP_US 1000 126#define MAX_TMOUT_RESP_SYNC_US 100000000 127 128 /* Wait for sync Admin Command response */ 129 read_poll_timeout(IXGBE_READ_REG, hicr, 130 (hicr & IXGBE_PF_HICR_SV) || 131 !(hicr & IXGBE_PF_HICR_C), 132 MAX_SLEEP_RESP_US, MAX_TMOUT_RESP_SYNC_US, true, hw, 133 IXGBE_PF_HICR); 134 135#define MAX_TMOUT_RESP_ASYNC_US 150000000 136 137 /* Wait for async Admin Command response */ 138 read_poll_timeout(IXGBE_READ_REG, hicr, 139 (hicr & IXGBE_PF_HICR_EV) || 140 !(hicr & IXGBE_PF_HICR_C), 141 MAX_SLEEP_RESP_US, MAX_TMOUT_RESP_ASYNC_US, true, hw, 142 IXGBE_PF_HICR); 143 144 /* Read sync Admin Command response */ 145 if ((hicr & IXGBE_PF_HICR_SV)) { 146 for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) { 147 raw_desc[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIDA(i)); 148 raw_desc[i] = raw_desc[i]; 149 } 150 } 151 152 /* Read async Admin Command response */ 153 if ((hicr & IXGBE_PF_HICR_EV) && !(hicr & IXGBE_PF_HICR_C)) { 154 for (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) { 155 raw_desc[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIDA_2(i)); 156 raw_desc[i] = raw_desc[i]; 157 } 158 } 159 160 /* Handle timeout and invalid state of HICR register */ 161 if (hicr & IXGBE_PF_HICR_C) 162 return -ETIME; 163 164 if (!(hicr & IXGBE_PF_HICR_SV) && !(hicr & IXGBE_PF_HICR_EV)) 165 return -EIO; 166 167 /* For every command other than 0x0014 treat opcode mismatch 168 * as an error. Response to 0x0014 command read from HIDA_2 169 * is a descriptor of an event which is expected to contain 170 * different opcode than the command. 171 */ 172 if (desc->opcode != cpu_to_le16(opcode) && 173 opcode != ixgbe_aci_opc_get_fw_event) 174 return -EIO; 175 176 if (desc->retval) { 177 hw->aci.last_status = (enum libie_aq_err) 178 le16_to_cpu(desc->retval); 179 return -EIO; 180 } 181 182 /* Write a response values to a buf */ 183 if (valid_buf) { 184 for (i = 0; i < buf_size / 4; i++) 185 ((u32 *)buf)[i] = IXGBE_READ_REG(hw, IXGBE_PF_HIBA(i)); 186 if (buf_tail_size) { 187 buf_tail = IXGBE_READ_REG(hw, IXGBE_PF_HIBA(i)); 188 memcpy(buf + buf_size - buf_tail_size, &buf_tail, 189 buf_tail_size); 190 } 191 } 192 193 return 0; 194} 195 196/** 197 * ixgbe_aci_send_cmd - send FW Admin Command to FW Admin Command Interface 198 * @hw: pointer to the HW struct 199 * @desc: descriptor describing the command 200 * @buf: buffer to use for indirect commands (NULL for direct commands) 201 * @buf_size: size of buffer for indirect commands (0 for direct commands) 202 * 203 * Helper function to send FW Admin Commands to the FW Admin Command Interface. 204 * 205 * Retry sending the FW Admin Command multiple times to the FW ACI 206 * if the EBUSY Admin Command error is returned. 207 * 208 * Return: the exit code of the operation. 209 */ 210int ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct libie_aq_desc *desc, 211 void *buf, u16 buf_size) 212{ 213 u16 opcode = le16_to_cpu(desc->opcode); 214 struct libie_aq_desc desc_cpy; 215 enum libie_aq_err last_status; 216 u8 idx = 0, *buf_cpy = NULL; 217 bool is_cmd_for_retry; 218 unsigned long timeout; 219 int err; 220 221 is_cmd_for_retry = ixgbe_should_retry_aci_send_cmd_execute(opcode); 222 if (is_cmd_for_retry) { 223 if (buf) { 224 buf_cpy = kmalloc(buf_size, GFP_KERNEL); 225 if (!buf_cpy) 226 return -ENOMEM; 227 *buf_cpy = *(u8 *)buf; 228 } 229 desc_cpy = *desc; 230 } 231 232 timeout = jiffies + msecs_to_jiffies(IXGBE_ACI_SEND_TIMEOUT_MS); 233 do { 234 mutex_lock(&hw->aci.lock); 235 err = ixgbe_aci_send_cmd_execute(hw, desc, buf, buf_size); 236 last_status = hw->aci.last_status; 237 mutex_unlock(&hw->aci.lock); 238 239 if (!is_cmd_for_retry || !err || 240 last_status != LIBIE_AQ_RC_EBUSY) 241 break; 242 243 if (buf) 244 memcpy(buf, buf_cpy, buf_size); 245 *desc = desc_cpy; 246 247 msleep(IXGBE_ACI_SEND_DELAY_TIME_MS); 248 } while (++idx < IXGBE_ACI_SEND_MAX_EXECUTE && 249 time_before(jiffies, timeout)); 250 251 kfree(buf_cpy); 252 253 return err; 254} 255 256/** 257 * ixgbe_aci_check_event_pending - check if there are any pending events 258 * @hw: pointer to the HW struct 259 * 260 * Determine if there are any pending events. 261 * 262 * Return: true if there are any currently pending events 263 * otherwise false. 264 */ 265bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw) 266{ 267 u32 ep_bit_mask = hw->bus.func ? GL_FWSTS_EP_PF1 : GL_FWSTS_EP_PF0; 268 u32 fwsts = IXGBE_READ_REG(hw, GL_FWSTS); 269 270 return (fwsts & ep_bit_mask) ? true : false; 271} 272 273/** 274 * ixgbe_aci_get_event - get an event from ACI 275 * @hw: pointer to the HW struct 276 * @e: event information structure 277 * @pending: optional flag signaling that there are more pending events 278 * 279 * Obtain an event from ACI and return its content 280 * through 'e' using ACI command (0x0014). 281 * Provide information if there are more events 282 * to retrieve through 'pending'. 283 * 284 * Return: the exit code of the operation. 285 */ 286int ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e, 287 bool *pending) 288{ 289 struct libie_aq_desc desc; 290 int err; 291 292 if (!e || (!e->msg_buf && e->buf_len)) 293 return -EINVAL; 294 295 mutex_lock(&hw->aci.lock); 296 297 /* Check if there are any events pending */ 298 if (!ixgbe_aci_check_event_pending(hw)) { 299 err = -ENOENT; 300 goto aci_get_event_exit; 301 } 302 303 /* Obtain pending event */ 304 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_fw_event); 305 err = ixgbe_aci_send_cmd_execute(hw, &desc, e->msg_buf, e->buf_len); 306 if (err) 307 goto aci_get_event_exit; 308 309 /* Returned 0x0014 opcode indicates that no event was obtained */ 310 if (desc.opcode == cpu_to_le16(ixgbe_aci_opc_get_fw_event)) { 311 err = -ENOENT; 312 goto aci_get_event_exit; 313 } 314 315 /* Determine size of event data */ 316 e->msg_len = min_t(u16, le16_to_cpu(desc.datalen), e->buf_len); 317 /* Write event descriptor to event info structure */ 318 memcpy(&e->desc, &desc, sizeof(e->desc)); 319 320 /* Check if there are any further events pending */ 321 if (pending) 322 *pending = ixgbe_aci_check_event_pending(hw); 323 324aci_get_event_exit: 325 mutex_unlock(&hw->aci.lock); 326 327 return err; 328} 329 330/** 331 * ixgbe_fill_dflt_direct_cmd_desc - fill ACI descriptor with default values. 332 * @desc: pointer to the temp descriptor (non DMA mem) 333 * @opcode: the opcode can be used to decide which flags to turn off or on 334 * 335 * Helper function to fill the descriptor desc with default values 336 * and the provided opcode. 337 */ 338void ixgbe_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode) 339{ 340 /* Zero out the desc. */ 341 memset(desc, 0, sizeof(*desc)); 342 desc->opcode = cpu_to_le16(opcode); 343 desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI); 344} 345 346/** 347 * ixgbe_aci_get_fw_ver - Get the firmware version 348 * @hw: pointer to the HW struct 349 * 350 * Get the firmware version using ACI command (0x0001). 351 * 352 * Return: the exit code of the operation. 353 */ 354static int ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw) 355{ 356 struct libie_aqc_get_ver *resp; 357 struct libie_aq_desc desc; 358 int err; 359 360 resp = &desc.params.get_ver; 361 362 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_ver); 363 364 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 365 if (!err) { 366 hw->fw_branch = resp->fw_branch; 367 hw->fw_maj_ver = resp->fw_major; 368 hw->fw_min_ver = resp->fw_minor; 369 hw->fw_patch = resp->fw_patch; 370 hw->fw_build = le32_to_cpu(resp->fw_build); 371 hw->api_branch = resp->api_branch; 372 hw->api_maj_ver = resp->api_major; 373 hw->api_min_ver = resp->api_minor; 374 hw->api_patch = resp->api_patch; 375 } 376 377 return err; 378} 379 380/** 381 * ixgbe_aci_req_res - request a common resource 382 * @hw: pointer to the HW struct 383 * @res: resource ID 384 * @access: access type 385 * @sdp_number: resource number 386 * @timeout: the maximum time in ms that the driver may hold the resource 387 * 388 * Requests a common resource using the ACI command (0x0008). 389 * Specifies the maximum time the driver may hold the resource. 390 * If the requested resource is currently occupied by some other driver, 391 * a busy return value is returned and the timeout field value indicates the 392 * maximum time the current owner has to free it. 393 * 394 * Return: the exit code of the operation. 395 */ 396static int ixgbe_aci_req_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 397 enum libie_aq_res_access_type access, 398 u8 sdp_number, u32 *timeout) 399{ 400 struct libie_aqc_req_res *cmd_resp; 401 struct libie_aq_desc desc; 402 int err; 403 404 cmd_resp = &desc.params.res_owner; 405 406 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_req_res); 407 408 cmd_resp->res_id = cpu_to_le16(res); 409 cmd_resp->access_type = cpu_to_le16(access); 410 cmd_resp->res_number = cpu_to_le32(sdp_number); 411 cmd_resp->timeout = cpu_to_le32(*timeout); 412 *timeout = 0; 413 414 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 415 416 /* If the resource is held by some other driver, the command completes 417 * with a busy return value and the timeout field indicates the maximum 418 * time the current owner of the resource has to free it. 419 */ 420 if (!err || hw->aci.last_status == LIBIE_AQ_RC_EBUSY) 421 *timeout = le32_to_cpu(cmd_resp->timeout); 422 423 return err; 424} 425 426/** 427 * ixgbe_aci_release_res - release a common resource using ACI 428 * @hw: pointer to the HW struct 429 * @res: resource ID 430 * @sdp_number: resource number 431 * 432 * Release a common resource using ACI command (0x0009). 433 * 434 * Return: the exit code of the operation. 435 */ 436static int ixgbe_aci_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 437 u8 sdp_number) 438{ 439 struct libie_aqc_req_res *cmd; 440 struct libie_aq_desc desc; 441 442 cmd = &desc.params.res_owner; 443 444 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_release_res); 445 446 cmd->res_id = cpu_to_le16(res); 447 cmd->res_number = cpu_to_le32(sdp_number); 448 449 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 450} 451 452/** 453 * ixgbe_acquire_res - acquire the ownership of a resource 454 * @hw: pointer to the HW structure 455 * @res: resource ID 456 * @access: access type (read or write) 457 * @timeout: timeout in milliseconds 458 * 459 * Make an attempt to acquire the ownership of a resource using 460 * the ixgbe_aci_req_res to utilize ACI. 461 * In case if some other driver has previously acquired the resource and 462 * performed any necessary updates, the -EALREADY is returned, 463 * and the caller does not obtain the resource and has no further work to do. 464 * If needed, the function will poll until the current lock owner timeouts. 465 * 466 * Return: the exit code of the operation. 467 */ 468int ixgbe_acquire_res(struct ixgbe_hw *hw, enum libie_aq_res_id res, 469 enum libie_aq_res_access_type access, u32 timeout) 470{ 471#define IXGBE_RES_POLLING_DELAY_MS 10 472 u32 delay = IXGBE_RES_POLLING_DELAY_MS; 473 u32 res_timeout = timeout; 474 u32 retry_timeout; 475 int err; 476 477 err = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout); 478 479 /* A return code of -EALREADY means that another driver has 480 * previously acquired the resource and performed any necessary updates; 481 * in this case the caller does not obtain the resource and has no 482 * further work to do. 483 */ 484 if (err == -EALREADY) 485 return err; 486 487 /* If necessary, poll until the current lock owner timeouts. 488 * Set retry_timeout to the timeout value reported by the FW in the 489 * response to the "Request Resource Ownership" (0x0008) Admin Command 490 * as it indicates the maximum time the current owner of the resource 491 * is allowed to hold it. 492 */ 493 retry_timeout = res_timeout; 494 while (err && retry_timeout && res_timeout) { 495 msleep(delay); 496 retry_timeout = (retry_timeout > delay) ? 497 retry_timeout - delay : 0; 498 err = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout); 499 500 /* Success - lock acquired. 501 * -EALREADY - lock free, no work to do. 502 */ 503 if (!err || err == -EALREADY) 504 break; 505 } 506 507 return err; 508} 509 510/** 511 * ixgbe_release_res - release a common resource 512 * @hw: pointer to the HW structure 513 * @res: resource ID 514 * 515 * Release a common resource using ixgbe_aci_release_res. 516 */ 517void ixgbe_release_res(struct ixgbe_hw *hw, enum libie_aq_res_id res) 518{ 519 u32 total_delay = 0; 520 int err; 521 522 err = ixgbe_aci_release_res(hw, res, 0); 523 524 /* There are some rare cases when trying to release the resource 525 * results in an admin command timeout, so handle them correctly. 526 */ 527 while (err == -ETIME && 528 total_delay < IXGBE_ACI_RELEASE_RES_TIMEOUT) { 529 usleep_range(1000, 1500); 530 err = ixgbe_aci_release_res(hw, res, 0); 531 total_delay++; 532 } 533} 534 535/** 536 * ixgbe_parse_e610_caps - Parse common device/function capabilities 537 * @hw: pointer to the HW struct 538 * @caps: pointer to common capabilities structure 539 * @elem: the capability element to parse 540 * @prefix: message prefix for tracing capabilities 541 * 542 * Given a capability element, extract relevant details into the common 543 * capability structure. 544 * 545 * Return: true if the capability matches one of the common capability ids, 546 * false otherwise. 547 */ 548static bool ixgbe_parse_e610_caps(struct ixgbe_hw *hw, 549 struct ixgbe_hw_caps *caps, 550 struct libie_aqc_list_caps_elem *elem, 551 const char *prefix) 552{ 553 u32 logical_id = le32_to_cpu(elem->logical_id); 554 u32 phys_id = le32_to_cpu(elem->phys_id); 555 u32 number = le32_to_cpu(elem->number); 556 u16 cap = le16_to_cpu(elem->cap); 557 558 switch (cap) { 559 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 560 caps->valid_functions = number; 561 break; 562 case LIBIE_AQC_CAPS_SRIOV: 563 caps->sr_iov_1_1 = (number == 1); 564 break; 565 case LIBIE_AQC_CAPS_VMDQ: 566 caps->vmdq = (number == 1); 567 break; 568 case LIBIE_AQC_CAPS_DCB: 569 caps->dcb = (number == 1); 570 caps->active_tc_bitmap = logical_id; 571 caps->maxtc = phys_id; 572 break; 573 case LIBIE_AQC_CAPS_RSS: 574 caps->rss_table_size = number; 575 caps->rss_table_entry_width = logical_id; 576 break; 577 case LIBIE_AQC_CAPS_RXQS: 578 caps->num_rxq = number; 579 caps->rxq_first_id = phys_id; 580 break; 581 case LIBIE_AQC_CAPS_TXQS: 582 caps->num_txq = number; 583 caps->txq_first_id = phys_id; 584 break; 585 case LIBIE_AQC_CAPS_MSIX: 586 caps->num_msix_vectors = number; 587 caps->msix_vector_first_id = phys_id; 588 break; 589 case LIBIE_AQC_CAPS_NVM_VER: 590 break; 591 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 592 caps->nvm_update_pending_nvm = true; 593 break; 594 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 595 caps->nvm_update_pending_orom = true; 596 break; 597 case LIBIE_AQC_CAPS_PENDING_NET_VER: 598 caps->nvm_update_pending_netlist = true; 599 break; 600 case LIBIE_AQC_CAPS_NVM_MGMT: 601 caps->nvm_unified_update = 602 (number & IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 603 true : false; 604 break; 605 case LIBIE_AQC_CAPS_MAX_MTU: 606 caps->max_mtu = number; 607 break; 608 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 609 caps->pcie_reset_avoidance = (number > 0); 610 break; 611 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 612 caps->reset_restrict_support = (number == 1); 613 break; 614 case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0: 615 case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG1: 616 case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG2: 617 case LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG3: 618 { 619 u8 index = cap - LIBIE_AQC_CAPS_EXT_TOPO_DEV_IMG0; 620 621 caps->ext_topo_dev_img_ver_high[index] = number; 622 caps->ext_topo_dev_img_ver_low[index] = logical_id; 623 caps->ext_topo_dev_img_part_num[index] = 624 FIELD_GET(IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M, phys_id); 625 caps->ext_topo_dev_img_load_en[index] = 626 (phys_id & IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0; 627 caps->ext_topo_dev_img_prog_en[index] = 628 (phys_id & IXGBE_EXT_TOPO_DEV_IMG_PROG_EN) != 0; 629 break; 630 } 631 default: 632 /* Not one of the recognized common capabilities */ 633 return false; 634 } 635 636 return true; 637} 638 639/** 640 * ixgbe_parse_valid_functions_cap - Parse LIBIE_AQC_CAPS_VALID_FUNCTIONS caps 641 * @hw: pointer to the HW struct 642 * @dev_p: pointer to device capabilities structure 643 * @cap: capability element to parse 644 * 645 * Parse LIBIE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 646 */ 647static void 648ixgbe_parse_valid_functions_cap(struct ixgbe_hw *hw, 649 struct ixgbe_hw_dev_caps *dev_p, 650 struct libie_aqc_list_caps_elem *cap) 651{ 652 dev_p->num_funcs = hweight32(le32_to_cpu(cap->number)); 653} 654 655/** 656 * ixgbe_parse_vf_dev_caps - Parse LIBIE_AQC_CAPS_VF device caps 657 * @hw: pointer to the HW struct 658 * @dev_p: pointer to device capabilities structure 659 * @cap: capability element to parse 660 * 661 * Parse LIBIE_AQC_CAPS_VF for device capabilities. 662 */ 663static void ixgbe_parse_vf_dev_caps(struct ixgbe_hw *hw, 664 struct ixgbe_hw_dev_caps *dev_p, 665 struct libie_aqc_list_caps_elem *cap) 666{ 667 dev_p->num_vfs_exposed = le32_to_cpu(cap->number); 668} 669 670/** 671 * ixgbe_parse_vsi_dev_caps - Parse LIBIE_AQC_CAPS_VSI device caps 672 * @hw: pointer to the HW struct 673 * @dev_p: pointer to device capabilities structure 674 * @cap: capability element to parse 675 * 676 * Parse LIBIE_AQC_CAPS_VSI for device capabilities. 677 */ 678static void ixgbe_parse_vsi_dev_caps(struct ixgbe_hw *hw, 679 struct ixgbe_hw_dev_caps *dev_p, 680 struct libie_aqc_list_caps_elem *cap) 681{ 682 dev_p->num_vsi_allocd_to_host = le32_to_cpu(cap->number); 683} 684 685/** 686 * ixgbe_parse_fdir_dev_caps - Parse LIBIE_AQC_CAPS_FD device caps 687 * @hw: pointer to the HW struct 688 * @dev_p: pointer to device capabilities structure 689 * @cap: capability element to parse 690 * 691 * Parse LIBIE_AQC_CAPS_FD for device capabilities. 692 */ 693static void ixgbe_parse_fdir_dev_caps(struct ixgbe_hw *hw, 694 struct ixgbe_hw_dev_caps *dev_p, 695 struct libie_aqc_list_caps_elem *cap) 696{ 697 dev_p->num_flow_director_fltr = le32_to_cpu(cap->number); 698} 699 700/** 701 * ixgbe_parse_dev_caps - Parse device capabilities 702 * @hw: pointer to the HW struct 703 * @dev_p: pointer to device capabilities structure 704 * @buf: buffer containing the device capability records 705 * @cap_count: the number of capabilities 706 * 707 * Helper device to parse device (0x000B) capabilities list. For 708 * capabilities shared between device and function, this relies on 709 * ixgbe_parse_e610_caps. 710 * 711 * Loop through the list of provided capabilities and extract the relevant 712 * data into the device capabilities structured. 713 */ 714static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw, 715 struct ixgbe_hw_dev_caps *dev_p, 716 void *buf, u32 cap_count) 717{ 718 struct libie_aqc_list_caps_elem *cap_resp; 719 u32 i; 720 721 cap_resp = (struct libie_aqc_list_caps_elem *)buf; 722 723 memset(dev_p, 0, sizeof(*dev_p)); 724 725 for (i = 0; i < cap_count; i++) { 726 u16 cap = le16_to_cpu(cap_resp[i].cap); 727 728 ixgbe_parse_e610_caps(hw, &dev_p->common_cap, &cap_resp[i], 729 "dev caps"); 730 731 switch (cap) { 732 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 733 ixgbe_parse_valid_functions_cap(hw, dev_p, 734 &cap_resp[i]); 735 break; 736 case LIBIE_AQC_CAPS_VF: 737 ixgbe_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 738 break; 739 case LIBIE_AQC_CAPS_VSI: 740 ixgbe_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 741 break; 742 case LIBIE_AQC_CAPS_FD: 743 ixgbe_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 744 break; 745 default: 746 /* Don't list common capabilities as unknown */ 747 break; 748 } 749 } 750} 751 752/** 753 * ixgbe_parse_vf_func_caps - Parse LIBIE_AQC_CAPS_VF function caps 754 * @hw: pointer to the HW struct 755 * @func_p: pointer to function capabilities structure 756 * @cap: pointer to the capability element to parse 757 * 758 * Extract function capabilities for LIBIE_AQC_CAPS_VF. 759 */ 760static void ixgbe_parse_vf_func_caps(struct ixgbe_hw *hw, 761 struct ixgbe_hw_func_caps *func_p, 762 struct libie_aqc_list_caps_elem *cap) 763{ 764 func_p->num_allocd_vfs = le32_to_cpu(cap->number); 765 func_p->vf_base_id = le32_to_cpu(cap->logical_id); 766} 767 768/** 769 * ixgbe_get_num_per_func - determine number of resources per PF 770 * @hw: pointer to the HW structure 771 * @max: value to be evenly split between each PF 772 * 773 * Determine the number of valid functions by going through the bitmap returned 774 * from parsing capabilities and use this to calculate the number of resources 775 * per PF based on the max value passed in. 776 * 777 * Return: the number of resources per PF or 0, if no PFs are available. 778 */ 779static u32 ixgbe_get_num_per_func(struct ixgbe_hw *hw, u32 max) 780{ 781#define IXGBE_CAPS_VALID_FUNCS_M GENMASK(7, 0) 782 u8 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 783 IXGBE_CAPS_VALID_FUNCS_M); 784 785 return funcs ? (max / funcs) : 0; 786} 787 788/** 789 * ixgbe_parse_vsi_func_caps - Parse LIBIE_AQC_CAPS_VSI function caps 790 * @hw: pointer to the HW struct 791 * @func_p: pointer to function capabilities structure 792 * @cap: pointer to the capability element to parse 793 * 794 * Extract function capabilities for LIBIE_AQC_CAPS_VSI. 795 */ 796static void ixgbe_parse_vsi_func_caps(struct ixgbe_hw *hw, 797 struct ixgbe_hw_func_caps *func_p, 798 struct libie_aqc_list_caps_elem *cap) 799{ 800 func_p->guar_num_vsi = ixgbe_get_num_per_func(hw, IXGBE_MAX_VSI); 801} 802 803/** 804 * ixgbe_parse_func_caps - Parse function capabilities 805 * @hw: pointer to the HW struct 806 * @func_p: pointer to function capabilities structure 807 * @buf: buffer containing the function capability records 808 * @cap_count: the number of capabilities 809 * 810 * Helper function to parse function (0x000A) capabilities list. For 811 * capabilities shared between device and function, this relies on 812 * ixgbe_parse_e610_caps. 813 * 814 * Loop through the list of provided capabilities and extract the relevant 815 * data into the function capabilities structured. 816 */ 817static void ixgbe_parse_func_caps(struct ixgbe_hw *hw, 818 struct ixgbe_hw_func_caps *func_p, 819 void *buf, u32 cap_count) 820{ 821 struct libie_aqc_list_caps_elem *cap_resp; 822 u32 i; 823 824 cap_resp = (struct libie_aqc_list_caps_elem *)buf; 825 826 memset(func_p, 0, sizeof(*func_p)); 827 828 for (i = 0; i < cap_count; i++) { 829 u16 cap = le16_to_cpu(cap_resp[i].cap); 830 831 ixgbe_parse_e610_caps(hw, &func_p->common_cap, 832 &cap_resp[i], "func caps"); 833 834 switch (cap) { 835 case LIBIE_AQC_CAPS_VF: 836 ixgbe_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 837 break; 838 case LIBIE_AQC_CAPS_VSI: 839 ixgbe_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 840 break; 841 default: 842 /* Don't list common capabilities as unknown */ 843 break; 844 } 845 } 846} 847 848/** 849 * ixgbe_aci_list_caps - query function/device capabilities 850 * @hw: pointer to the HW struct 851 * @buf: a buffer to hold the capabilities 852 * @buf_size: size of the buffer 853 * @cap_count: if not NULL, set to the number of capabilities reported 854 * @opc: capabilities type to discover, device or function 855 * 856 * Get the function (0x000A) or device (0x000B) capabilities description from 857 * firmware and store it in the buffer. 858 * 859 * If the cap_count pointer is not NULL, then it is set to the number of 860 * capabilities firmware will report. Note that if the buffer size is too 861 * small, it is possible the command will return -ENOMEM. The 862 * cap_count will still be updated in this case. It is recommended that the 863 * buffer size be set to IXGBE_ACI_MAX_BUFFER_SIZE (the largest possible 864 * buffer that firmware could return) to avoid this. 865 * 866 * Return: the exit code of the operation. 867 * Exit code of -ENOMEM means the buffer size is too small. 868 */ 869int ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size, 870 u32 *cap_count, enum ixgbe_aci_opc opc) 871{ 872 struct libie_aqc_list_caps *cmd; 873 struct libie_aq_desc desc; 874 int err; 875 876 cmd = &desc.params.get_cap; 877 878 if (opc != ixgbe_aci_opc_list_func_caps && 879 opc != ixgbe_aci_opc_list_dev_caps) 880 return -EINVAL; 881 882 ixgbe_fill_dflt_direct_cmd_desc(&desc, opc); 883 err = ixgbe_aci_send_cmd(hw, &desc, buf, buf_size); 884 885 if (cap_count) 886 *cap_count = le32_to_cpu(cmd->count); 887 888 return err; 889} 890 891/** 892 * ixgbe_discover_dev_caps - Read and extract device capabilities 893 * @hw: pointer to the hardware structure 894 * @dev_caps: pointer to device capabilities structure 895 * 896 * Read the device capabilities and extract them into the dev_caps structure 897 * for later use. 898 * 899 * Return: the exit code of the operation. 900 */ 901int ixgbe_discover_dev_caps(struct ixgbe_hw *hw, 902 struct ixgbe_hw_dev_caps *dev_caps) 903{ 904 u32 cap_count; 905 u8 *cbuf; 906 int err; 907 908 cbuf = kzalloc(IXGBE_ACI_MAX_BUFFER_SIZE, GFP_KERNEL); 909 if (!cbuf) 910 return -ENOMEM; 911 912 /* Although the driver doesn't know the number of capabilities the 913 * device will return, we can simply send a 4KB buffer, the maximum 914 * possible size that firmware can return. 915 */ 916 cap_count = IXGBE_ACI_MAX_BUFFER_SIZE / 917 sizeof(struct libie_aqc_list_caps_elem); 918 919 err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE, 920 &cap_count, 921 ixgbe_aci_opc_list_dev_caps); 922 if (!err) 923 ixgbe_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 924 925 kfree(cbuf); 926 927 return 0; 928} 929 930/** 931 * ixgbe_discover_func_caps - Read and extract function capabilities 932 * @hw: pointer to the hardware structure 933 * @func_caps: pointer to function capabilities structure 934 * 935 * Read the function capabilities and extract them into the func_caps structure 936 * for later use. 937 * 938 * Return: the exit code of the operation. 939 */ 940int ixgbe_discover_func_caps(struct ixgbe_hw *hw, 941 struct ixgbe_hw_func_caps *func_caps) 942{ 943 u32 cap_count; 944 u8 *cbuf; 945 int err; 946 947 cbuf = kzalloc(IXGBE_ACI_MAX_BUFFER_SIZE, GFP_KERNEL); 948 if (!cbuf) 949 return -ENOMEM; 950 951 /* Although the driver doesn't know the number of capabilities the 952 * device will return, we can simply send a 4KB buffer, the maximum 953 * possible size that firmware can return. 954 */ 955 cap_count = IXGBE_ACI_MAX_BUFFER_SIZE / 956 sizeof(struct libie_aqc_list_caps_elem); 957 958 err = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE, 959 &cap_count, 960 ixgbe_aci_opc_list_func_caps); 961 if (!err) 962 ixgbe_parse_func_caps(hw, func_caps, cbuf, cap_count); 963 964 kfree(cbuf); 965 966 return 0; 967} 968 969/** 970 * ixgbe_get_caps - get info about the HW 971 * @hw: pointer to the hardware structure 972 * 973 * Retrieve both device and function capabilities. 974 * 975 * Return: the exit code of the operation. 976 */ 977int ixgbe_get_caps(struct ixgbe_hw *hw) 978{ 979 int err; 980 981 err = ixgbe_discover_dev_caps(hw, &hw->dev_caps); 982 if (err) 983 return err; 984 985 return ixgbe_discover_func_caps(hw, &hw->func_caps); 986} 987 988/** 989 * ixgbe_aci_disable_rxen - disable RX 990 * @hw: pointer to the HW struct 991 * 992 * Request a safe disable of Receive Enable using ACI command (0x000C). 993 * 994 * Return: the exit code of the operation. 995 */ 996int ixgbe_aci_disable_rxen(struct ixgbe_hw *hw) 997{ 998 struct ixgbe_aci_cmd_disable_rxen *cmd; 999 struct libie_aq_desc desc; 1000 1001 cmd = libie_aq_raw(&desc); 1002 1003 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_disable_rxen); 1004 1005 cmd->lport_num = hw->bus.func; 1006 1007 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1008} 1009 1010/** 1011 * ixgbe_aci_get_phy_caps - returns PHY capabilities 1012 * @hw: pointer to the HW struct 1013 * @qual_mods: report qualified modules 1014 * @report_mode: report mode capabilities 1015 * @pcaps: structure for PHY capabilities to be filled 1016 * 1017 * Returns the various PHY capabilities supported on the Port 1018 * using ACI command (0x0600). 1019 * 1020 * Return: the exit code of the operation. 1021 */ 1022int ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode, 1023 struct ixgbe_aci_cmd_get_phy_caps_data *pcaps) 1024{ 1025 struct ixgbe_aci_cmd_get_phy_caps *cmd; 1026 u16 pcaps_size = sizeof(*pcaps); 1027 struct libie_aq_desc desc; 1028 int err; 1029 1030 cmd = libie_aq_raw(&desc); 1031 1032 if (!pcaps || (report_mode & ~IXGBE_ACI_REPORT_MODE_M)) 1033 return -EINVAL; 1034 1035 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_phy_caps); 1036 1037 if (qual_mods) 1038 cmd->param0 |= cpu_to_le16(IXGBE_ACI_GET_PHY_RQM); 1039 1040 cmd->param0 |= cpu_to_le16(report_mode); 1041 err = ixgbe_aci_send_cmd(hw, &desc, pcaps, pcaps_size); 1042 if (!err && report_mode == IXGBE_ACI_REPORT_TOPO_CAP_MEDIA) { 1043 hw->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 1044 hw->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 1045 memcpy(hw->link.link_info.module_type, &pcaps->module_type, 1046 sizeof(hw->link.link_info.module_type)); 1047 } 1048 1049 return err; 1050} 1051 1052/** 1053 * ixgbe_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 1054 * @caps: PHY ability structure to copy data from 1055 * @cfg: PHY configuration structure to copy data to 1056 * 1057 * Helper function to copy data from PHY capabilities data structure 1058 * to PHY configuration data structure 1059 */ 1060void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps, 1061 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg) 1062{ 1063 if (!caps || !cfg) 1064 return; 1065 1066 memset(cfg, 0, sizeof(*cfg)); 1067 cfg->phy_type_low = caps->phy_type_low; 1068 cfg->phy_type_high = caps->phy_type_high; 1069 cfg->caps = caps->caps; 1070 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 1071 cfg->eee_cap = caps->eee_cap; 1072 cfg->eeer_value = caps->eeer_value; 1073 cfg->link_fec_opt = caps->link_fec_options; 1074 cfg->module_compliance_enforcement = 1075 caps->module_compliance_enforcement; 1076} 1077 1078/** 1079 * ixgbe_aci_set_phy_cfg - set PHY configuration 1080 * @hw: pointer to the HW struct 1081 * @cfg: structure with PHY configuration data to be set 1082 * 1083 * Set the various PHY configuration parameters supported on the Port 1084 * using ACI command (0x0601). 1085 * One or more of the Set PHY config parameters may be ignored in an MFP 1086 * mode as the PF may not have the privilege to set some of the PHY Config 1087 * parameters. 1088 * 1089 * Return: the exit code of the operation. 1090 */ 1091int ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw, 1092 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg) 1093{ 1094 struct ixgbe_aci_cmd_set_phy_cfg *cmd; 1095 struct libie_aq_desc desc; 1096 int err; 1097 1098 if (!cfg) 1099 return -EINVAL; 1100 1101 cmd = libie_aq_raw(&desc); 1102 /* Ensure that only valid bits of cfg->caps can be turned on. */ 1103 cfg->caps &= IXGBE_ACI_PHY_ENA_VALID_MASK; 1104 1105 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_phy_cfg); 1106 cmd->lport_num = hw->bus.func; 1107 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 1108 1109 err = ixgbe_aci_send_cmd(hw, &desc, cfg, sizeof(*cfg)); 1110 if (!err) 1111 hw->phy.curr_user_phy_cfg = *cfg; 1112 1113 return err; 1114} 1115 1116/** 1117 * ixgbe_aci_set_link_restart_an - set up link and restart AN 1118 * @hw: pointer to the HW struct 1119 * @ena_link: if true: enable link, if false: disable link 1120 * 1121 * Function sets up the link and restarts the Auto-Negotiation over the link. 1122 * 1123 * Return: the exit code of the operation. 1124 */ 1125int ixgbe_aci_set_link_restart_an(struct ixgbe_hw *hw, bool ena_link) 1126{ 1127 struct ixgbe_aci_cmd_restart_an *cmd; 1128 struct libie_aq_desc desc; 1129 1130 cmd = libie_aq_raw(&desc); 1131 1132 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_restart_an); 1133 1134 cmd->cmd_flags = IXGBE_ACI_RESTART_AN_LINK_RESTART; 1135 cmd->lport_num = hw->bus.func; 1136 if (ena_link) 1137 cmd->cmd_flags |= IXGBE_ACI_RESTART_AN_LINK_ENABLE; 1138 else 1139 cmd->cmd_flags &= ~IXGBE_ACI_RESTART_AN_LINK_ENABLE; 1140 1141 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1142} 1143 1144/** 1145 * ixgbe_is_media_cage_present - check if media cage is present 1146 * @hw: pointer to the HW struct 1147 * 1148 * Identify presence of media cage using the ACI command (0x06E0). 1149 * 1150 * Return: true if media cage is present, else false. If no cage, then 1151 * media type is backplane or BASE-T. 1152 */ 1153static bool ixgbe_is_media_cage_present(struct ixgbe_hw *hw) 1154{ 1155 struct ixgbe_aci_cmd_get_link_topo *cmd; 1156 struct libie_aq_desc desc; 1157 1158 cmd = libie_aq_raw(&desc); 1159 1160 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo); 1161 1162 cmd->addr.topo_params.node_type_ctx = 1163 FIELD_PREP(IXGBE_ACI_LINK_TOPO_NODE_CTX_M, 1164 IXGBE_ACI_LINK_TOPO_NODE_CTX_PORT); 1165 1166 /* Set node type. */ 1167 cmd->addr.topo_params.node_type_ctx |= 1168 FIELD_PREP(IXGBE_ACI_LINK_TOPO_NODE_TYPE_M, 1169 IXGBE_ACI_LINK_TOPO_NODE_TYPE_CAGE); 1170 1171 /* Node type cage can be used to determine if cage is present. If AQC 1172 * returns error (ENOENT), then no cage present. If no cage present then 1173 * connection type is backplane or BASE-T. 1174 */ 1175 return !ixgbe_aci_get_netlist_node(hw, cmd, NULL, NULL); 1176} 1177 1178/** 1179 * ixgbe_get_media_type_from_phy_type - Gets media type based on phy type 1180 * @hw: pointer to the HW struct 1181 * 1182 * Try to identify the media type based on the phy type. 1183 * If more than one media type, the ixgbe_media_type_unknown is returned. 1184 * First, phy_type_low is checked, then phy_type_high. 1185 * If none are identified, the ixgbe_media_type_unknown is returned 1186 * 1187 * Return: type of a media based on phy type in form of enum. 1188 */ 1189static enum ixgbe_media_type 1190ixgbe_get_media_type_from_phy_type(struct ixgbe_hw *hw) 1191{ 1192 struct ixgbe_link_status *hw_link_info; 1193 1194 if (!hw) 1195 return ixgbe_media_type_unknown; 1196 1197 hw_link_info = &hw->link.link_info; 1198 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 1199 /* If more than one media type is selected, report unknown */ 1200 return ixgbe_media_type_unknown; 1201 1202 if (hw_link_info->phy_type_low) { 1203 /* 1G SGMII is a special case where some DA cable PHYs 1204 * may show this as an option when it really shouldn't 1205 * be since SGMII is meant to be between a MAC and a PHY 1206 * in a backplane. Try to detect this case and handle it 1207 */ 1208 if (hw_link_info->phy_type_low == IXGBE_PHY_TYPE_LOW_1G_SGMII && 1209 (hw_link_info->module_type[IXGBE_ACI_MOD_TYPE_IDENT] == 1210 IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 1211 hw_link_info->module_type[IXGBE_ACI_MOD_TYPE_IDENT] == 1212 IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 1213 return ixgbe_media_type_da; 1214 1215 switch (hw_link_info->phy_type_low) { 1216 case IXGBE_PHY_TYPE_LOW_1000BASE_SX: 1217 case IXGBE_PHY_TYPE_LOW_1000BASE_LX: 1218 case IXGBE_PHY_TYPE_LOW_10GBASE_SR: 1219 case IXGBE_PHY_TYPE_LOW_10GBASE_LR: 1220 case IXGBE_PHY_TYPE_LOW_25GBASE_SR: 1221 case IXGBE_PHY_TYPE_LOW_25GBASE_LR: 1222 return ixgbe_media_type_fiber; 1223 case IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 1224 case IXGBE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 1225 return ixgbe_media_type_fiber; 1226 case IXGBE_PHY_TYPE_LOW_100BASE_TX: 1227 case IXGBE_PHY_TYPE_LOW_1000BASE_T: 1228 case IXGBE_PHY_TYPE_LOW_2500BASE_T: 1229 case IXGBE_PHY_TYPE_LOW_5GBASE_T: 1230 case IXGBE_PHY_TYPE_LOW_10GBASE_T: 1231 case IXGBE_PHY_TYPE_LOW_25GBASE_T: 1232 return ixgbe_media_type_copper; 1233 case IXGBE_PHY_TYPE_LOW_10G_SFI_DA: 1234 case IXGBE_PHY_TYPE_LOW_25GBASE_CR: 1235 case IXGBE_PHY_TYPE_LOW_25GBASE_CR_S: 1236 case IXGBE_PHY_TYPE_LOW_25GBASE_CR1: 1237 return ixgbe_media_type_da; 1238 case IXGBE_PHY_TYPE_LOW_25G_AUI_C2C: 1239 if (ixgbe_is_media_cage_present(hw)) 1240 return ixgbe_media_type_aui; 1241 fallthrough; 1242 case IXGBE_PHY_TYPE_LOW_1000BASE_KX: 1243 case IXGBE_PHY_TYPE_LOW_2500BASE_KX: 1244 case IXGBE_PHY_TYPE_LOW_2500BASE_X: 1245 case IXGBE_PHY_TYPE_LOW_5GBASE_KR: 1246 case IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1: 1247 case IXGBE_PHY_TYPE_LOW_10G_SFI_C2C: 1248 case IXGBE_PHY_TYPE_LOW_25GBASE_KR: 1249 case IXGBE_PHY_TYPE_LOW_25GBASE_KR1: 1250 case IXGBE_PHY_TYPE_LOW_25GBASE_KR_S: 1251 return ixgbe_media_type_backplane; 1252 } 1253 } else { 1254 switch (hw_link_info->phy_type_high) { 1255 case IXGBE_PHY_TYPE_HIGH_10BASE_T: 1256 return ixgbe_media_type_copper; 1257 } 1258 } 1259 return ixgbe_media_type_unknown; 1260} 1261 1262/** 1263 * ixgbe_update_link_info - update status of the HW network link 1264 * @hw: pointer to the HW struct 1265 * 1266 * Update the status of the HW network link. 1267 * 1268 * Return: the exit code of the operation. 1269 */ 1270int ixgbe_update_link_info(struct ixgbe_hw *hw) 1271{ 1272 struct ixgbe_aci_cmd_get_phy_caps_data *pcaps; 1273 struct ixgbe_link_status *li; 1274 int err; 1275 1276 if (!hw) 1277 return -EINVAL; 1278 1279 li = &hw->link.link_info; 1280 1281 err = ixgbe_aci_get_link_info(hw, true, NULL); 1282 if (err) 1283 return err; 1284 1285 if (!(li->link_info & IXGBE_ACI_MEDIA_AVAILABLE)) 1286 return 0; 1287 1288 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1289 if (!pcaps) 1290 return -ENOMEM; 1291 1292 err = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_TOPO_CAP_MEDIA, 1293 pcaps); 1294 1295 if (!err) 1296 memcpy(li->module_type, &pcaps->module_type, 1297 sizeof(li->module_type)); 1298 1299 kfree(pcaps); 1300 1301 return err; 1302} 1303 1304/** 1305 * ixgbe_get_link_status - get status of the HW network link 1306 * @hw: pointer to the HW struct 1307 * @link_up: pointer to bool (true/false = linkup/linkdown) 1308 * 1309 * Variable link_up is true if link is up, false if link is down. 1310 * The variable link_up is invalid if status is non zero. As a 1311 * result of this call, link status reporting becomes enabled 1312 * 1313 * Return: the exit code of the operation. 1314 */ 1315int ixgbe_get_link_status(struct ixgbe_hw *hw, bool *link_up) 1316{ 1317 if (!hw || !link_up) 1318 return -EINVAL; 1319 1320 if (hw->link.get_link_info) { 1321 int err = ixgbe_update_link_info(hw); 1322 1323 if (err) 1324 return err; 1325 } 1326 1327 *link_up = hw->link.link_info.link_info & IXGBE_ACI_LINK_UP; 1328 1329 return 0; 1330} 1331 1332/** 1333 * ixgbe_aci_get_link_info - get the link status 1334 * @hw: pointer to the HW struct 1335 * @ena_lse: enable/disable LinkStatusEvent reporting 1336 * @link: pointer to link status structure - optional 1337 * 1338 * Get the current Link Status using ACI command (0x607). 1339 * The current link can be optionally provided to update 1340 * the status. 1341 * 1342 * Return: the link status of the adapter. 1343 */ 1344int ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse, 1345 struct ixgbe_link_status *link) 1346{ 1347 struct ixgbe_aci_cmd_get_link_status_data link_data = {}; 1348 struct ixgbe_aci_cmd_get_link_status *resp; 1349 struct ixgbe_link_status *li_old, *li; 1350 struct ixgbe_fc_info *hw_fc_info; 1351 struct libie_aq_desc desc; 1352 bool tx_pause, rx_pause; 1353 u8 cmd_flags; 1354 int err; 1355 1356 if (!hw) 1357 return -EINVAL; 1358 1359 li_old = &hw->link.link_info_old; 1360 li = &hw->link.link_info; 1361 hw_fc_info = &hw->fc; 1362 1363 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_status); 1364 cmd_flags = (ena_lse) ? IXGBE_ACI_LSE_ENA : IXGBE_ACI_LSE_DIS; 1365 resp = libie_aq_raw(&desc); 1366 resp->cmd_flags = cpu_to_le16(cmd_flags); 1367 resp->lport_num = hw->bus.func; 1368 1369 err = ixgbe_aci_send_cmd(hw, &desc, &link_data, sizeof(link_data)); 1370 if (err) 1371 return err; 1372 1373 /* Save off old link status information. */ 1374 *li_old = *li; 1375 1376 /* Update current link status information. */ 1377 li->link_speed = le16_to_cpu(link_data.link_speed); 1378 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 1379 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 1380 li->link_info = link_data.link_info; 1381 li->link_cfg_err = link_data.link_cfg_err; 1382 li->an_info = link_data.an_info; 1383 li->ext_info = link_data.ext_info; 1384 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 1385 li->fec_info = link_data.cfg & IXGBE_ACI_FEC_MASK; 1386 li->topo_media_conflict = link_data.topo_media_conflict; 1387 li->pacing = link_data.cfg & (IXGBE_ACI_CFG_PACING_M | 1388 IXGBE_ACI_CFG_PACING_TYPE_M); 1389 1390 /* Update fc info. */ 1391 tx_pause = !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_TX); 1392 rx_pause = !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_RX); 1393 if (tx_pause && rx_pause) 1394 hw_fc_info->current_mode = ixgbe_fc_full; 1395 else if (tx_pause) 1396 hw_fc_info->current_mode = ixgbe_fc_tx_pause; 1397 else if (rx_pause) 1398 hw_fc_info->current_mode = ixgbe_fc_rx_pause; 1399 else 1400 hw_fc_info->current_mode = ixgbe_fc_none; 1401 1402 li->lse_ena = !!(le16_to_cpu(resp->cmd_flags) & 1403 IXGBE_ACI_LSE_IS_ENABLED); 1404 1405 /* Save link status information. */ 1406 if (link) 1407 *link = *li; 1408 1409 /* Flag cleared so calling functions don't call AQ again. */ 1410 hw->link.get_link_info = false; 1411 1412 return 0; 1413} 1414 1415/** 1416 * ixgbe_aci_set_event_mask - set event mask 1417 * @hw: pointer to the HW struct 1418 * @port_num: port number of the physical function 1419 * @mask: event mask to be set 1420 * 1421 * Set the event mask using ACI command (0x0613). 1422 * 1423 * Return: the exit code of the operation. 1424 */ 1425int ixgbe_aci_set_event_mask(struct ixgbe_hw *hw, u8 port_num, u16 mask) 1426{ 1427 struct ixgbe_aci_cmd_set_event_mask *cmd; 1428 struct libie_aq_desc desc; 1429 1430 cmd = libie_aq_raw(&desc); 1431 1432 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_event_mask); 1433 1434 cmd->lport_num = port_num; 1435 1436 cmd->event_mask = cpu_to_le16(mask); 1437 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1438} 1439 1440/** 1441 * ixgbe_configure_lse - enable/disable link status events 1442 * @hw: pointer to the HW struct 1443 * @activate: true for enable lse, false otherwise 1444 * @mask: event mask to be set; a set bit means deactivation of the 1445 * corresponding event 1446 * 1447 * Set the event mask and then enable or disable link status events 1448 * 1449 * Return: the exit code of the operation. 1450 */ 1451int ixgbe_configure_lse(struct ixgbe_hw *hw, bool activate, u16 mask) 1452{ 1453 int err; 1454 1455 err = ixgbe_aci_set_event_mask(hw, (u8)hw->bus.func, mask); 1456 if (err) 1457 return err; 1458 1459 /* Enabling link status events generation by fw. */ 1460 return ixgbe_aci_get_link_info(hw, activate, NULL); 1461} 1462 1463/** 1464 * ixgbe_start_hw_e610 - Prepare hardware for Tx/Rx 1465 * @hw: pointer to hardware structure 1466 * 1467 * Get firmware version and start the hardware using the generic 1468 * start_hw() and ixgbe_start_hw_gen2() functions. 1469 * 1470 * Return: the exit code of the operation. 1471 */ 1472static int ixgbe_start_hw_e610(struct ixgbe_hw *hw) 1473{ 1474 int err; 1475 1476 err = ixgbe_aci_get_fw_ver(hw); 1477 if (err) 1478 return err; 1479 1480 err = ixgbe_start_hw_generic(hw); 1481 if (err) 1482 return err; 1483 1484 ixgbe_start_hw_gen2(hw); 1485 1486 return 0; 1487} 1488 1489/** 1490 * ixgbe_aci_set_port_id_led - set LED value for the given port 1491 * @hw: pointer to the HW struct 1492 * @orig_mode: set LED original mode 1493 * 1494 * Set LED value for the given port (0x06E9) 1495 * 1496 * Return: the exit code of the operation. 1497 */ 1498int ixgbe_aci_set_port_id_led(struct ixgbe_hw *hw, bool orig_mode) 1499{ 1500 struct ixgbe_aci_cmd_set_port_id_led *cmd; 1501 struct libie_aq_desc desc; 1502 1503 cmd = libie_aq_raw(&desc); 1504 1505 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_port_id_led); 1506 1507 cmd->lport_num = (u8)hw->bus.func; 1508 cmd->lport_num_valid = IXGBE_ACI_PORT_ID_PORT_NUM_VALID; 1509 1510 if (orig_mode) 1511 cmd->ident_mode = IXGBE_ACI_PORT_IDENT_LED_ORIG; 1512 else 1513 cmd->ident_mode = IXGBE_ACI_PORT_IDENT_LED_BLINK; 1514 1515 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 1516} 1517 1518/** 1519 * ixgbe_get_media_type_e610 - Gets media type 1520 * @hw: pointer to the HW struct 1521 * 1522 * In order to get the media type, the function gets PHY 1523 * capabilities and later on use them to identify the PHY type 1524 * checking phy_type_high and phy_type_low. 1525 * 1526 * Return: the type of media in form of ixgbe_media_type enum 1527 * or ixgbe_media_type_unknown in case of an error. 1528 */ 1529enum ixgbe_media_type ixgbe_get_media_type_e610(struct ixgbe_hw *hw) 1530{ 1531 struct ixgbe_aci_cmd_get_phy_caps_data pcaps; 1532 int rc; 1533 1534 rc = ixgbe_update_link_info(hw); 1535 if (rc) 1536 return ixgbe_media_type_unknown; 1537 1538 /* If there is no link but PHY (dongle) is available SW should use 1539 * Get PHY Caps admin command instead of Get Link Status, find most 1540 * significant bit that is set in PHY types reported by the command 1541 * and use it to discover media type. 1542 */ 1543 if (!(hw->link.link_info.link_info & IXGBE_ACI_LINK_UP) && 1544 (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) { 1545 int highest_bit; 1546 1547 /* Get PHY Capabilities */ 1548 rc = ixgbe_aci_get_phy_caps(hw, false, 1549 IXGBE_ACI_REPORT_TOPO_CAP_MEDIA, 1550 &pcaps); 1551 if (rc) 1552 return ixgbe_media_type_unknown; 1553 1554 highest_bit = fls64(le64_to_cpu(pcaps.phy_type_high)); 1555 if (highest_bit) { 1556 hw->link.link_info.phy_type_high = 1557 BIT_ULL(highest_bit - 1); 1558 hw->link.link_info.phy_type_low = 0; 1559 } else { 1560 highest_bit = fls64(le64_to_cpu(pcaps.phy_type_low)); 1561 if (highest_bit) { 1562 hw->link.link_info.phy_type_low = 1563 BIT_ULL(highest_bit - 1); 1564 hw->link.link_info.phy_type_high = 0; 1565 } 1566 } 1567 } 1568 1569 /* Based on link status or search above try to discover media type. */ 1570 hw->phy.media_type = ixgbe_get_media_type_from_phy_type(hw); 1571 1572 return hw->phy.media_type; 1573} 1574 1575/** 1576 * ixgbe_setup_link_e610 - Set up link 1577 * @hw: pointer to hardware structure 1578 * @speed: new link speed 1579 * @autoneg_wait: true when waiting for completion is needed 1580 * 1581 * Set up the link with the specified speed. 1582 * 1583 * Return: the exit code of the operation. 1584 */ 1585int ixgbe_setup_link_e610(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1586 bool autoneg_wait) 1587{ 1588 /* Simply request FW to perform proper PHY setup */ 1589 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1590} 1591 1592/** 1593 * ixgbe_check_link_e610 - Determine link and speed status 1594 * @hw: pointer to hardware structure 1595 * @speed: pointer to link speed 1596 * @link_up: true when link is up 1597 * @link_up_wait_to_complete: bool used to wait for link up or not 1598 * 1599 * Determine if the link is up and the current link speed 1600 * using ACI command (0x0607). 1601 * 1602 * Return: the exit code of the operation. 1603 */ 1604int ixgbe_check_link_e610(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1605 bool *link_up, bool link_up_wait_to_complete) 1606{ 1607 int err; 1608 u32 i; 1609 1610 if (!speed || !link_up) 1611 return -EINVAL; 1612 1613 /* Set get_link_info flag to ensure that fresh 1614 * link information will be obtained from FW 1615 * by sending Get Link Status admin command. 1616 */ 1617 hw->link.get_link_info = true; 1618 1619 /* Update link information in adapter context. */ 1620 err = ixgbe_get_link_status(hw, link_up); 1621 if (err) 1622 return err; 1623 1624 /* Wait for link up if it was requested. */ 1625 if (link_up_wait_to_complete && !(*link_up)) { 1626 for (i = 0; i < hw->mac.max_link_up_time; i++) { 1627 msleep(100); 1628 hw->link.get_link_info = true; 1629 err = ixgbe_get_link_status(hw, link_up); 1630 if (err) 1631 return err; 1632 if (*link_up) 1633 break; 1634 } 1635 } 1636 1637 /* Use link information in adapter context updated by the call 1638 * to ixgbe_get_link_status() to determine current link speed. 1639 * Link speed information is valid only when link up was 1640 * reported by FW. 1641 */ 1642 if (*link_up) { 1643 switch (hw->link.link_info.link_speed) { 1644 case IXGBE_ACI_LINK_SPEED_10MB: 1645 *speed = IXGBE_LINK_SPEED_10_FULL; 1646 break; 1647 case IXGBE_ACI_LINK_SPEED_100MB: 1648 *speed = IXGBE_LINK_SPEED_100_FULL; 1649 break; 1650 case IXGBE_ACI_LINK_SPEED_1000MB: 1651 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1652 break; 1653 case IXGBE_ACI_LINK_SPEED_2500MB: 1654 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 1655 break; 1656 case IXGBE_ACI_LINK_SPEED_5GB: 1657 *speed = IXGBE_LINK_SPEED_5GB_FULL; 1658 break; 1659 case IXGBE_ACI_LINK_SPEED_10GB: 1660 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1661 break; 1662 default: 1663 *speed = IXGBE_LINK_SPEED_UNKNOWN; 1664 break; 1665 } 1666 } else { 1667 *speed = IXGBE_LINK_SPEED_UNKNOWN; 1668 } 1669 1670 return 0; 1671} 1672 1673/** 1674 * ixgbe_get_link_capabilities_e610 - Determine link capabilities 1675 * @hw: pointer to hardware structure 1676 * @speed: pointer to link speed 1677 * @autoneg: true when autoneg or autotry is enabled 1678 * 1679 * Determine speed and AN parameters of a link. 1680 * 1681 * Return: the exit code of the operation. 1682 */ 1683int ixgbe_get_link_capabilities_e610(struct ixgbe_hw *hw, 1684 ixgbe_link_speed *speed, 1685 bool *autoneg) 1686{ 1687 if (!speed || !autoneg) 1688 return -EINVAL; 1689 1690 *autoneg = true; 1691 *speed = hw->phy.speeds_supported; 1692 1693 return 0; 1694} 1695 1696/** 1697 * ixgbe_cfg_phy_fc - Configure PHY Flow Control (FC) data based on FC mode 1698 * @hw: pointer to hardware structure 1699 * @cfg: PHY configuration data to set FC mode 1700 * @req_mode: FC mode to configure 1701 * 1702 * Configures PHY Flow Control according to the provided configuration. 1703 * 1704 * Return: the exit code of the operation. 1705 */ 1706int ixgbe_cfg_phy_fc(struct ixgbe_hw *hw, 1707 struct ixgbe_aci_cmd_set_phy_cfg_data *cfg, 1708 enum ixgbe_fc_mode req_mode) 1709{ 1710 u8 pause_mask = 0x0; 1711 1712 if (!cfg) 1713 return -EINVAL; 1714 1715 switch (req_mode) { 1716 case ixgbe_fc_full: 1717 pause_mask |= IXGBE_ACI_PHY_EN_TX_LINK_PAUSE; 1718 pause_mask |= IXGBE_ACI_PHY_EN_RX_LINK_PAUSE; 1719 break; 1720 case ixgbe_fc_rx_pause: 1721 pause_mask |= IXGBE_ACI_PHY_EN_RX_LINK_PAUSE; 1722 break; 1723 case ixgbe_fc_tx_pause: 1724 pause_mask |= IXGBE_ACI_PHY_EN_TX_LINK_PAUSE; 1725 break; 1726 default: 1727 break; 1728 } 1729 1730 /* Clear the old pause settings. */ 1731 cfg->caps &= ~(IXGBE_ACI_PHY_EN_TX_LINK_PAUSE | 1732 IXGBE_ACI_PHY_EN_RX_LINK_PAUSE); 1733 1734 /* Set the new capabilities. */ 1735 cfg->caps |= pause_mask; 1736 1737 return 0; 1738} 1739 1740/** 1741 * ixgbe_setup_fc_e610 - Set up flow control 1742 * @hw: pointer to hardware structure 1743 * 1744 * Set up flow control. This has to be done during init time. 1745 * 1746 * Return: the exit code of the operation. 1747 */ 1748int ixgbe_setup_fc_e610(struct ixgbe_hw *hw) 1749{ 1750 struct ixgbe_aci_cmd_get_phy_caps_data pcaps = {}; 1751 struct ixgbe_aci_cmd_set_phy_cfg_data cfg = {}; 1752 int err; 1753 1754 /* Get the current PHY config */ 1755 err = ixgbe_aci_get_phy_caps(hw, false, 1756 IXGBE_ACI_REPORT_ACTIVE_CFG, &pcaps); 1757 if (err) 1758 return err; 1759 1760 ixgbe_copy_phy_caps_to_cfg(&pcaps, &cfg); 1761 1762 /* Configure the set PHY data */ 1763 err = ixgbe_cfg_phy_fc(hw, &cfg, hw->fc.requested_mode); 1764 if (err) 1765 return err; 1766 1767 /* If the capabilities have changed, then set the new config */ 1768 if (cfg.caps != pcaps.caps) { 1769 cfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT; 1770 1771 err = ixgbe_aci_set_phy_cfg(hw, &cfg); 1772 if (err) 1773 return err; 1774 } 1775 1776 return err; 1777} 1778 1779/** 1780 * ixgbe_fc_autoneg_e610 - Configure flow control 1781 * @hw: pointer to hardware structure 1782 * 1783 * Configure Flow Control. 1784 */ 1785void ixgbe_fc_autoneg_e610(struct ixgbe_hw *hw) 1786{ 1787 int err; 1788 1789 /* Get current link err. 1790 * Current FC mode will be stored in the hw context. 1791 */ 1792 err = ixgbe_aci_get_link_info(hw, false, NULL); 1793 if (err) 1794 goto no_autoneg; 1795 1796 /* Check if the link is up */ 1797 if (!(hw->link.link_info.link_info & IXGBE_ACI_LINK_UP)) 1798 goto no_autoneg; 1799 1800 /* Check if auto-negotiation has completed */ 1801 if (!(hw->link.link_info.an_info & IXGBE_ACI_AN_COMPLETED)) 1802 goto no_autoneg; 1803 1804 hw->fc.fc_was_autonegged = true; 1805 return; 1806 1807no_autoneg: 1808 hw->fc.fc_was_autonegged = false; 1809 hw->fc.current_mode = hw->fc.requested_mode; 1810} 1811 1812/** 1813 * ixgbe_disable_rx_e610 - Disable RX unit 1814 * @hw: pointer to hardware structure 1815 * 1816 * Disable RX DMA unit on E610 with use of ACI command (0x000C). 1817 * 1818 * Return: the exit code of the operation. 1819 */ 1820void ixgbe_disable_rx_e610(struct ixgbe_hw *hw) 1821{ 1822 u32 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1823 u32 pfdtxgswc; 1824 int err; 1825 1826 if (!(rxctrl & IXGBE_RXCTRL_RXEN)) 1827 return; 1828 1829 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1830 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1831 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1832 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1833 hw->mac.set_lben = true; 1834 } else { 1835 hw->mac.set_lben = false; 1836 } 1837 1838 err = ixgbe_aci_disable_rxen(hw); 1839 1840 /* If we fail - disable RX using register write */ 1841 if (err) { 1842 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1843 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1844 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1845 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1846 } 1847 } 1848} 1849 1850/** 1851 * ixgbe_fw_recovery_mode_e610 - Check FW NVM recovery mode 1852 * @hw: pointer to hardware structure 1853 * 1854 * Check FW NVM recovery mode by reading the value of 1855 * the dedicated register. 1856 * 1857 * Return: true if FW is in recovery mode, otherwise false. 1858 */ 1859static bool ixgbe_fw_recovery_mode_e610(struct ixgbe_hw *hw) 1860{ 1861 u32 fwsm = IXGBE_READ_REG(hw, IXGBE_GL_MNG_FWSM); 1862 1863 return !!(fwsm & IXGBE_GL_MNG_FWSM_RECOVERY_M); 1864} 1865 1866/** 1867 * ixgbe_fw_rollback_mode_e610 - Check FW NVM rollback mode 1868 * @hw: pointer to hardware structure 1869 * 1870 * Check FW NVM rollback mode by reading the value of 1871 * the dedicated register. 1872 * 1873 * Return: true if FW is in rollback mode, otherwise false. 1874 */ 1875static bool ixgbe_fw_rollback_mode_e610(struct ixgbe_hw *hw) 1876{ 1877 u32 fwsm = IXGBE_READ_REG(hw, IXGBE_GL_MNG_FWSM); 1878 1879 return !!(fwsm & IXGBE_GL_MNG_FWSM_ROLLBACK_M); 1880} 1881 1882/** 1883 * ixgbe_init_phy_ops_e610 - PHY specific init 1884 * @hw: pointer to hardware structure 1885 * 1886 * Initialize any function pointers that were not able to be 1887 * set during init_shared_code because the PHY type was not known. 1888 * 1889 * Return: the exit code of the operation. 1890 */ 1891int ixgbe_init_phy_ops_e610(struct ixgbe_hw *hw) 1892{ 1893 struct ixgbe_mac_info *mac = &hw->mac; 1894 struct ixgbe_phy_info *phy = &hw->phy; 1895 1896 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 1897 phy->ops.set_phy_power = ixgbe_set_phy_power_e610; 1898 else 1899 phy->ops.set_phy_power = NULL; 1900 1901 /* Identify the PHY */ 1902 return phy->ops.identify(hw); 1903} 1904 1905/** 1906 * ixgbe_identify_phy_e610 - Identify PHY 1907 * @hw: pointer to hardware structure 1908 * 1909 * Determine PHY type, supported speeds and PHY ID. 1910 * 1911 * Return: the exit code of the operation. 1912 */ 1913int ixgbe_identify_phy_e610(struct ixgbe_hw *hw) 1914{ 1915 struct ixgbe_aci_cmd_get_phy_caps_data pcaps; 1916 u64 phy_type_low, phy_type_high; 1917 int err; 1918 1919 /* Set PHY type */ 1920 hw->phy.type = ixgbe_phy_fw; 1921 1922 err = ixgbe_aci_get_phy_caps(hw, false, 1923 IXGBE_ACI_REPORT_TOPO_CAP_MEDIA, &pcaps); 1924 if (err) 1925 return err; 1926 1927 if (!(pcaps.module_compliance_enforcement & 1928 IXGBE_ACI_MOD_ENFORCE_STRICT_MODE)) { 1929 /* Handle lenient mode */ 1930 err = ixgbe_aci_get_phy_caps(hw, false, 1931 IXGBE_ACI_REPORT_TOPO_CAP_NO_MEDIA, 1932 &pcaps); 1933 if (err) 1934 return err; 1935 } 1936 1937 /* Determine supported speeds */ 1938 hw->phy.speeds_supported = IXGBE_LINK_SPEED_UNKNOWN; 1939 phy_type_high = le64_to_cpu(pcaps.phy_type_high); 1940 phy_type_low = le64_to_cpu(pcaps.phy_type_low); 1941 1942 if (phy_type_high & IXGBE_PHY_TYPE_HIGH_10BASE_T || 1943 phy_type_high & IXGBE_PHY_TYPE_HIGH_10M_SGMII) 1944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10_FULL; 1945 if (phy_type_low & IXGBE_PHY_TYPE_LOW_100BASE_TX || 1946 phy_type_low & IXGBE_PHY_TYPE_LOW_100M_SGMII || 1947 phy_type_high & IXGBE_PHY_TYPE_HIGH_100M_USXGMII) 1948 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 1949 if (phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_T || 1950 phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_SX || 1951 phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_LX || 1952 phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_KX || 1953 phy_type_low & IXGBE_PHY_TYPE_LOW_1G_SGMII || 1954 phy_type_high & IXGBE_PHY_TYPE_HIGH_1G_USXGMII) 1955 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 1956 if (phy_type_low & IXGBE_PHY_TYPE_LOW_2500BASE_T || 1957 phy_type_low & IXGBE_PHY_TYPE_LOW_2500BASE_X || 1958 phy_type_low & IXGBE_PHY_TYPE_LOW_2500BASE_KX || 1959 phy_type_high & IXGBE_PHY_TYPE_HIGH_2500M_SGMII || 1960 phy_type_high & IXGBE_PHY_TYPE_HIGH_2500M_USXGMII) 1961 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 1962 if (phy_type_low & IXGBE_PHY_TYPE_LOW_5GBASE_T || 1963 phy_type_low & IXGBE_PHY_TYPE_LOW_5GBASE_KR || 1964 phy_type_high & IXGBE_PHY_TYPE_HIGH_5G_USXGMII) 1965 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 1966 if (phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_T || 1967 phy_type_low & IXGBE_PHY_TYPE_LOW_10G_SFI_DA || 1968 phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_SR || 1969 phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_LR || 1970 phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1 || 1971 phy_type_low & IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC || 1972 phy_type_low & IXGBE_PHY_TYPE_LOW_10G_SFI_C2C || 1973 phy_type_high & IXGBE_PHY_TYPE_HIGH_10G_USXGMII) 1974 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 1975 1976 /* Initialize autoneg speeds */ 1977 if (!hw->phy.autoneg_advertised) 1978 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 1979 1980 /* Set PHY ID */ 1981 memcpy(&hw->phy.id, pcaps.phy_id_oui, sizeof(u32)); 1982 1983 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_10_FULL | 1984 IXGBE_LINK_SPEED_100_FULL | 1985 IXGBE_LINK_SPEED_1GB_FULL; 1986 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 1987 1988 return 0; 1989} 1990 1991/** 1992 * ixgbe_identify_module_e610 - Identify SFP module type 1993 * @hw: pointer to hardware structure 1994 * 1995 * Identify the SFP module type. 1996 * 1997 * Return: the exit code of the operation. 1998 */ 1999int ixgbe_identify_module_e610(struct ixgbe_hw *hw) 2000{ 2001 bool media_available; 2002 u8 module_type; 2003 int err; 2004 2005 err = ixgbe_update_link_info(hw); 2006 if (err) 2007 return err; 2008 2009 media_available = 2010 (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE); 2011 2012 if (media_available) { 2013 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 2014 2015 /* Get module type from hw context updated by 2016 * ixgbe_update_link_info() 2017 */ 2018 module_type = hw->link.link_info.module_type[IXGBE_ACI_MOD_TYPE_IDENT]; 2019 2020 if ((module_type & IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE) || 2021 (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE)) { 2022 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 2023 } else if (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR) { 2024 hw->phy.sfp_type = ixgbe_sfp_type_sr; 2025 } else if ((module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR) || 2026 (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM)) { 2027 hw->phy.sfp_type = ixgbe_sfp_type_lr; 2028 } 2029 } else { 2030 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 2031 return -ENOENT; 2032 } 2033 2034 return 0; 2035} 2036 2037/** 2038 * ixgbe_setup_phy_link_e610 - Sets up firmware-controlled PHYs 2039 * @hw: pointer to hardware structure 2040 * 2041 * Set the parameters for the firmware-controlled PHYs. 2042 * 2043 * Return: the exit code of the operation. 2044 */ 2045int ixgbe_setup_phy_link_e610(struct ixgbe_hw *hw) 2046{ 2047 struct ixgbe_aci_cmd_get_phy_caps_data pcaps; 2048 struct ixgbe_aci_cmd_set_phy_cfg_data pcfg; 2049 u8 rmode = IXGBE_ACI_REPORT_TOPO_CAP_MEDIA; 2050 u64 sup_phy_type_low, sup_phy_type_high; 2051 u64 phy_type_low = 0, phy_type_high = 0; 2052 int err; 2053 2054 err = ixgbe_aci_get_link_info(hw, false, NULL); 2055 if (err) 2056 return err; 2057 2058 /* If media is not available get default config. */ 2059 if (!(hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) 2060 rmode = IXGBE_ACI_REPORT_DFLT_CFG; 2061 2062 err = ixgbe_aci_get_phy_caps(hw, false, rmode, &pcaps); 2063 if (err) 2064 return err; 2065 2066 sup_phy_type_low = le64_to_cpu(pcaps.phy_type_low); 2067 sup_phy_type_high = le64_to_cpu(pcaps.phy_type_high); 2068 2069 /* Get Active configuration to avoid unintended changes. */ 2070 err = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_ACTIVE_CFG, 2071 &pcaps); 2072 if (err) 2073 return err; 2074 2075 ixgbe_copy_phy_caps_to_cfg(&pcaps, &pcfg); 2076 2077 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) { 2078 phy_type_high |= IXGBE_PHY_TYPE_HIGH_10BASE_T; 2079 phy_type_high |= IXGBE_PHY_TYPE_HIGH_10M_SGMII; 2080 } 2081 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) { 2082 phy_type_low |= IXGBE_PHY_TYPE_LOW_100BASE_TX; 2083 phy_type_low |= IXGBE_PHY_TYPE_LOW_100M_SGMII; 2084 phy_type_high |= IXGBE_PHY_TYPE_HIGH_100M_USXGMII; 2085 } 2086 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 2087 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_T; 2088 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_SX; 2089 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_LX; 2090 phy_type_low |= IXGBE_PHY_TYPE_LOW_1000BASE_KX; 2091 phy_type_low |= IXGBE_PHY_TYPE_LOW_1G_SGMII; 2092 phy_type_high |= IXGBE_PHY_TYPE_HIGH_1G_USXGMII; 2093 } 2094 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) { 2095 phy_type_low |= IXGBE_PHY_TYPE_LOW_2500BASE_T; 2096 phy_type_low |= IXGBE_PHY_TYPE_LOW_2500BASE_X; 2097 phy_type_low |= IXGBE_PHY_TYPE_LOW_2500BASE_KX; 2098 phy_type_high |= IXGBE_PHY_TYPE_HIGH_2500M_SGMII; 2099 phy_type_high |= IXGBE_PHY_TYPE_HIGH_2500M_USXGMII; 2100 } 2101 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) { 2102 phy_type_low |= IXGBE_PHY_TYPE_LOW_5GBASE_T; 2103 phy_type_low |= IXGBE_PHY_TYPE_LOW_5GBASE_KR; 2104 phy_type_high |= IXGBE_PHY_TYPE_HIGH_5G_USXGMII; 2105 } 2106 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) { 2107 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_T; 2108 phy_type_low |= IXGBE_PHY_TYPE_LOW_10G_SFI_DA; 2109 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_SR; 2110 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_LR; 2111 phy_type_low |= IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1; 2112 phy_type_low |= IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC; 2113 phy_type_low |= IXGBE_PHY_TYPE_LOW_10G_SFI_C2C; 2114 phy_type_high |= IXGBE_PHY_TYPE_HIGH_10G_USXGMII; 2115 } 2116 2117 /* Mask the set values to avoid requesting unsupported link types. */ 2118 phy_type_low &= sup_phy_type_low; 2119 pcfg.phy_type_low = cpu_to_le64(phy_type_low); 2120 phy_type_high &= sup_phy_type_high; 2121 pcfg.phy_type_high = cpu_to_le64(phy_type_high); 2122 2123 if (pcfg.phy_type_high != pcaps.phy_type_high || 2124 pcfg.phy_type_low != pcaps.phy_type_low || 2125 pcfg.caps != pcaps.caps) { 2126 pcfg.caps |= IXGBE_ACI_PHY_ENA_LINK; 2127 pcfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT; 2128 2129 err = ixgbe_aci_set_phy_cfg(hw, &pcfg); 2130 if (err) 2131 return err; 2132 } 2133 2134 return 0; 2135} 2136 2137/** 2138 * ixgbe_set_phy_power_e610 - Control power for copper PHY 2139 * @hw: pointer to hardware structure 2140 * @on: true for on, false for off 2141 * 2142 * Set the power on/off of the PHY 2143 * by getting its capabilities and setting the appropriate 2144 * configuration parameters. 2145 * 2146 * Return: the exit code of the operation. 2147 */ 2148int ixgbe_set_phy_power_e610(struct ixgbe_hw *hw, bool on) 2149{ 2150 struct ixgbe_aci_cmd_get_phy_caps_data phy_caps = {}; 2151 struct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = {}; 2152 int err; 2153 2154 err = ixgbe_aci_get_phy_caps(hw, false, 2155 IXGBE_ACI_REPORT_ACTIVE_CFG, 2156 &phy_caps); 2157 if (err) 2158 return err; 2159 2160 ixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg); 2161 2162 if (on) 2163 phy_cfg.caps &= ~IXGBE_ACI_PHY_ENA_LOW_POWER; 2164 else 2165 phy_cfg.caps |= IXGBE_ACI_PHY_ENA_LOW_POWER; 2166 2167 /* PHY is already in requested power mode. */ 2168 if (phy_caps.caps == phy_cfg.caps) 2169 return 0; 2170 2171 phy_cfg.caps |= IXGBE_ACI_PHY_ENA_LINK; 2172 phy_cfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT; 2173 2174 return ixgbe_aci_set_phy_cfg(hw, &phy_cfg); 2175} 2176 2177/** 2178 * ixgbe_enter_lplu_e610 - Transition to low power states 2179 * @hw: pointer to hardware structure 2180 * 2181 * Configures Low Power Link Up on transition to low power states 2182 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 2183 * X557 PHY immediately prior to entering LPLU. 2184 * 2185 * Return: the exit code of the operation. 2186 */ 2187int ixgbe_enter_lplu_e610(struct ixgbe_hw *hw) 2188{ 2189 struct ixgbe_aci_cmd_get_phy_caps_data phy_caps = {}; 2190 struct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = {}; 2191 int err; 2192 2193 err = ixgbe_aci_get_phy_caps(hw, false, 2194 IXGBE_ACI_REPORT_ACTIVE_CFG, 2195 &phy_caps); 2196 if (err) 2197 return err; 2198 2199 ixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg); 2200 2201 phy_cfg.low_power_ctrl_an |= IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG; 2202 2203 return ixgbe_aci_set_phy_cfg(hw, &phy_cfg); 2204} 2205 2206/** 2207 * ixgbe_init_eeprom_params_e610 - Initialize EEPROM params 2208 * @hw: pointer to hardware structure 2209 * 2210 * Initialize the EEPROM parameters ixgbe_eeprom_info within the ixgbe_hw 2211 * struct in order to set up EEPROM access. 2212 * 2213 * Return: the operation exit code. 2214 */ 2215int ixgbe_init_eeprom_params_e610(struct ixgbe_hw *hw) 2216{ 2217 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2218 u32 gens_stat; 2219 u8 sr_size; 2220 2221 if (eeprom->type != ixgbe_eeprom_uninitialized) 2222 return 0; 2223 2224 eeprom->type = ixgbe_flash; 2225 2226 gens_stat = IXGBE_READ_REG(hw, GLNVM_GENS); 2227 sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat); 2228 2229 /* Switching to words (sr_size contains power of 2). */ 2230 eeprom->word_size = BIT(sr_size) * IXGBE_SR_WORDS_IN_1KB; 2231 2232 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", eeprom->type, 2233 eeprom->word_size); 2234 2235 return 0; 2236} 2237 2238/** 2239 * ixgbe_aci_get_netlist_node - get a node handle 2240 * @hw: pointer to the hw struct 2241 * @cmd: get_link_topo AQ structure 2242 * @node_part_number: output node part number if node found 2243 * @node_handle: output node handle parameter if node found 2244 * 2245 * Get the netlist node and assigns it to 2246 * the provided handle using ACI command (0x06E0). 2247 * 2248 * Return: the exit code of the operation. 2249 */ 2250int ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw, 2251 struct ixgbe_aci_cmd_get_link_topo *cmd, 2252 u8 *node_part_number, u16 *node_handle) 2253{ 2254 struct ixgbe_aci_cmd_get_link_topo *resp; 2255 struct libie_aq_desc desc; 2256 2257 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo); 2258 resp = libie_aq_raw(&desc); 2259 *resp = *cmd; 2260 2261 if (ixgbe_aci_send_cmd(hw, &desc, NULL, 0)) 2262 return -EOPNOTSUPP; 2263 2264 if (node_handle) 2265 *node_handle = le16_to_cpu(resp->addr.handle); 2266 if (node_part_number) 2267 *node_part_number = resp->node_part_num; 2268 2269 return 0; 2270} 2271 2272/** 2273 * ixgbe_acquire_nvm - Generic request for acquiring the NVM ownership 2274 * @hw: pointer to the HW structure 2275 * @access: NVM access type (read or write) 2276 * 2277 * Request NVM ownership. 2278 * 2279 * Return: the exit code of the operation. 2280 */ 2281int ixgbe_acquire_nvm(struct ixgbe_hw *hw, enum libie_aq_res_access_type access) 2282{ 2283 u32 fla; 2284 2285 /* Skip if we are in blank NVM programming mode */ 2286 fla = IXGBE_READ_REG(hw, IXGBE_GLNVM_FLA); 2287 if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0) 2288 return 0; 2289 2290 return ixgbe_acquire_res(hw, LIBIE_AQC_RES_ID_NVM, access, 2291 IXGBE_NVM_TIMEOUT); 2292} 2293 2294/** 2295 * ixgbe_release_nvm - Generic request for releasing the NVM ownership 2296 * @hw: pointer to the HW structure 2297 * 2298 * Release NVM ownership. 2299 */ 2300void ixgbe_release_nvm(struct ixgbe_hw *hw) 2301{ 2302 u32 fla; 2303 2304 /* Skip if we are in blank NVM programming mode */ 2305 fla = IXGBE_READ_REG(hw, IXGBE_GLNVM_FLA); 2306 if ((fla & IXGBE_GLNVM_FLA_LOCKED_M) == 0) 2307 return; 2308 2309 ixgbe_release_res(hw, LIBIE_AQC_RES_ID_NVM); 2310} 2311 2312/** 2313 * ixgbe_aci_read_nvm - read NVM 2314 * @hw: pointer to the HW struct 2315 * @module_typeid: module pointer location in words from the NVM beginning 2316 * @offset: byte offset from the module beginning 2317 * @length: length of the section to be read (in bytes from the offset) 2318 * @data: command buffer (size [bytes] = length) 2319 * @last_command: tells if this is the last command in a series 2320 * @read_shadow_ram: tell if this is a shadow RAM read 2321 * 2322 * Read the NVM using ACI command (0x0701). 2323 * 2324 * Return: the exit code of the operation. 2325 */ 2326int ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset, 2327 u16 length, void *data, bool last_command, 2328 bool read_shadow_ram) 2329{ 2330 struct ixgbe_aci_cmd_nvm *cmd; 2331 struct libie_aq_desc desc; 2332 2333 if (offset > IXGBE_ACI_NVM_MAX_OFFSET) 2334 return -EINVAL; 2335 2336 cmd = libie_aq_raw(&desc); 2337 2338 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_read); 2339 2340 if (!read_shadow_ram && module_typeid == IXGBE_ACI_NVM_START_POINT) 2341 cmd->cmd_flags |= IXGBE_ACI_NVM_FLASH_ONLY; 2342 2343 /* If this is the last command in a series, set the proper flag. */ 2344 if (last_command) 2345 cmd->cmd_flags |= IXGBE_ACI_NVM_LAST_CMD; 2346 cmd->module_typeid = cpu_to_le16(module_typeid); 2347 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 2348 cmd->offset_high = (offset >> 16) & 0xFF; 2349 cmd->length = cpu_to_le16(length); 2350 2351 return ixgbe_aci_send_cmd(hw, &desc, data, length); 2352} 2353 2354/** 2355 * ixgbe_aci_erase_nvm - erase NVM sector 2356 * @hw: pointer to the HW struct 2357 * @module_typeid: module pointer location in words from the NVM beginning 2358 * 2359 * Erase the NVM sector using the ACI command (0x0702). 2360 * 2361 * Return: the exit code of the operation. 2362 */ 2363int ixgbe_aci_erase_nvm(struct ixgbe_hw *hw, u16 module_typeid) 2364{ 2365 struct ixgbe_aci_cmd_nvm *cmd; 2366 struct libie_aq_desc desc; 2367 __le16 len; 2368 int err; 2369 2370 /* Read a length value from SR, so module_typeid is equal to 0, 2371 * calculate offset where module size is placed from bytes to words 2372 * set last command and read from SR values to true. 2373 */ 2374 err = ixgbe_aci_read_nvm(hw, 0, 2 * module_typeid + 2, 2, &len, true, 2375 true); 2376 if (err) 2377 return err; 2378 2379 cmd = libie_aq_raw(&desc); 2380 2381 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_erase); 2382 2383 cmd->module_typeid = cpu_to_le16(module_typeid); 2384 cmd->length = len; 2385 cmd->offset_low = 0; 2386 cmd->offset_high = 0; 2387 2388 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 2389} 2390 2391/** 2392 * ixgbe_aci_update_nvm - update NVM 2393 * @hw: pointer to the HW struct 2394 * @module_typeid: module pointer location in words from the NVM beginning 2395 * @offset: byte offset from the module beginning 2396 * @length: length of the section to be written (in bytes from the offset) 2397 * @data: command buffer (size [bytes] = length) 2398 * @last_command: tells if this is the last command in a series 2399 * @command_flags: command parameters 2400 * 2401 * Update the NVM using the ACI command (0x0703). 2402 * 2403 * Return: the exit code of the operation. 2404 */ 2405int ixgbe_aci_update_nvm(struct ixgbe_hw *hw, u16 module_typeid, 2406 u32 offset, u16 length, void *data, 2407 bool last_command, u8 command_flags) 2408{ 2409 struct ixgbe_aci_cmd_nvm *cmd; 2410 struct libie_aq_desc desc; 2411 2412 cmd = libie_aq_raw(&desc); 2413 2414 /* In offset the highest byte must be zeroed. */ 2415 if (offset & 0xFF000000) 2416 return -EINVAL; 2417 2418 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_write); 2419 2420 cmd->cmd_flags |= command_flags; 2421 2422 /* If this is the last command in a series, set the proper flag. */ 2423 if (last_command) 2424 cmd->cmd_flags |= IXGBE_ACI_NVM_LAST_CMD; 2425 cmd->module_typeid = cpu_to_le16(module_typeid); 2426 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 2427 cmd->offset_high = FIELD_GET(IXGBE_ACI_NVM_OFFSET_HI_U_MASK, offset); 2428 cmd->length = cpu_to_le16(length); 2429 2430 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2431 2432 return ixgbe_aci_send_cmd(hw, &desc, data, length); 2433} 2434 2435/** 2436 * ixgbe_nvm_write_activate - NVM activate write 2437 * @hw: pointer to the HW struct 2438 * @cmd_flags: flags for write activate command 2439 * @response_flags: response indicators from firmware 2440 * 2441 * Update the control word with the required banks' validity bits 2442 * and dumps the Shadow RAM to flash using ACI command (0x0707). 2443 * 2444 * cmd_flags controls which banks to activate, the preservation level to use 2445 * when activating the NVM bank, and whether an EMP reset is required for 2446 * activation. 2447 * 2448 * Note that the 16bit cmd_flags value is split between two separate 1 byte 2449 * flag values in the descriptor. 2450 * 2451 * On successful return of the firmware command, the response_flags variable 2452 * is updated with the flags reported by firmware indicating certain status, 2453 * such as whether EMP reset is enabled. 2454 * 2455 * Return: the exit code of the operation. 2456 */ 2457int ixgbe_nvm_write_activate(struct ixgbe_hw *hw, u16 cmd_flags, 2458 u8 *response_flags) 2459{ 2460 struct ixgbe_aci_cmd_nvm *cmd; 2461 struct libie_aq_desc desc; 2462 s32 err; 2463 2464 cmd = libie_aq_raw(&desc); 2465 ixgbe_fill_dflt_direct_cmd_desc(&desc, 2466 ixgbe_aci_opc_nvm_write_activate); 2467 2468 cmd->cmd_flags = (u8)(cmd_flags & 0xFF); 2469 cmd->offset_high = (u8)FIELD_GET(IXGBE_ACI_NVM_OFFSET_HI_A_MASK, 2470 cmd_flags); 2471 2472 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 2473 if (!err && response_flags) 2474 *response_flags = cmd->cmd_flags; 2475 2476 return err; 2477} 2478 2479/** 2480 * ixgbe_nvm_validate_checksum - validate checksum 2481 * @hw: pointer to the HW struct 2482 * 2483 * Verify NVM PFA checksum validity using ACI command (0x0706). 2484 * If the checksum verification failed, IXGBE_ERR_NVM_CHECKSUM is returned. 2485 * The function acquires and then releases the NVM ownership. 2486 * 2487 * Return: the exit code of the operation. 2488 */ 2489int ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw) 2490{ 2491 struct ixgbe_aci_cmd_nvm_checksum *cmd; 2492 struct libie_aq_desc desc; 2493 int err; 2494 2495 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 2496 if (err) 2497 return err; 2498 2499 cmd = libie_aq_raw(&desc); 2500 2501 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_checksum); 2502 cmd->flags = IXGBE_ACI_NVM_CHECKSUM_VERIFY; 2503 2504 err = ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 2505 2506 ixgbe_release_nvm(hw); 2507 2508 if (!err && cmd->checksum != 2509 cpu_to_le16(IXGBE_ACI_NVM_CHECKSUM_CORRECT)) { 2510 struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, 2511 hw); 2512 2513 err = -EIO; 2514 netdev_err(adapter->netdev, "Invalid Shadow Ram checksum"); 2515 } 2516 2517 return err; 2518} 2519 2520/** 2521 * ixgbe_discover_flash_size - Discover the available flash size 2522 * @hw: pointer to the HW struct 2523 * 2524 * The device flash could be up to 16MB in size. However, it is possible that 2525 * the actual size is smaller. Use bisection to determine the accessible size 2526 * of flash memory. 2527 * 2528 * Return: the exit code of the operation. 2529 */ 2530static int ixgbe_discover_flash_size(struct ixgbe_hw *hw) 2531{ 2532 u32 min_size = 0, max_size = IXGBE_ACI_NVM_MAX_OFFSET + 1; 2533 int err; 2534 2535 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 2536 if (err) 2537 return err; 2538 2539 while ((max_size - min_size) > 1) { 2540 u32 offset = (max_size + min_size) / 2; 2541 u32 len = 1; 2542 u8 data; 2543 2544 err = ixgbe_read_flat_nvm(hw, offset, &len, &data, false); 2545 if (err == -EIO && 2546 hw->aci.last_status == LIBIE_AQ_RC_EINVAL) { 2547 err = 0; 2548 max_size = offset; 2549 } else if (!err) { 2550 min_size = offset; 2551 } else { 2552 /* an unexpected error occurred */ 2553 goto err_read_flat_nvm; 2554 } 2555 } 2556 2557 hw->flash.flash_size = max_size; 2558 2559err_read_flat_nvm: 2560 ixgbe_release_nvm(hw); 2561 2562 return err; 2563} 2564 2565/** 2566 * ixgbe_read_sr_base_address - Read the value of a Shadow RAM pointer word 2567 * @hw: pointer to the HW structure 2568 * @offset: the word offset of the Shadow RAM word to read 2569 * @pointer: pointer value read from Shadow RAM 2570 * 2571 * Read the given Shadow RAM word, and convert it to a pointer value specified 2572 * in bytes. This function assumes the specified offset is a valid pointer 2573 * word. 2574 * 2575 * Each pointer word specifies whether it is stored in word size or 4KB 2576 * sector size by using the highest bit. The reported pointer value will be in 2577 * bytes, intended for flat NVM reads. 2578 * 2579 * Return: the exit code of the operation. 2580 */ 2581static int ixgbe_read_sr_base_address(struct ixgbe_hw *hw, u16 offset, 2582 u32 *pointer) 2583{ 2584 u16 value; 2585 int err; 2586 2587 err = ixgbe_read_ee_aci_e610(hw, offset, &value); 2588 if (err) 2589 return err; 2590 2591 /* Determine if the pointer is in 4KB or word units */ 2592 if (value & IXGBE_SR_NVM_PTR_4KB_UNITS) 2593 *pointer = (value & ~IXGBE_SR_NVM_PTR_4KB_UNITS) * SZ_4K; 2594 else 2595 *pointer = value * sizeof(u16); 2596 2597 return 0; 2598} 2599 2600/** 2601 * ixgbe_read_sr_area_size - Read an area size from a Shadow RAM word 2602 * @hw: pointer to the HW structure 2603 * @offset: the word offset of the Shadow RAM to read 2604 * @size: size value read from the Shadow RAM 2605 * 2606 * Read the given Shadow RAM word, and convert it to an area size value 2607 * specified in bytes. This function assumes the specified offset is a valid 2608 * area size word. 2609 * 2610 * Each area size word is specified in 4KB sector units. This function reports 2611 * the size in bytes, intended for flat NVM reads. 2612 * 2613 * Return: the exit code of the operation. 2614 */ 2615static int ixgbe_read_sr_area_size(struct ixgbe_hw *hw, u16 offset, u32 *size) 2616{ 2617 u16 value; 2618 int err; 2619 2620 err = ixgbe_read_ee_aci_e610(hw, offset, &value); 2621 if (err) 2622 return err; 2623 2624 /* Area sizes are always specified in 4KB units */ 2625 *size = value * SZ_4K; 2626 2627 return 0; 2628} 2629 2630/** 2631 * ixgbe_determine_active_flash_banks - Discover active bank for each module 2632 * @hw: pointer to the HW struct 2633 * 2634 * Read the Shadow RAM control word and determine which banks are active for 2635 * the NVM, OROM, and Netlist modules. Also read and calculate the associated 2636 * pointer and size. These values are then cached into the ixgbe_flash_info 2637 * structure for later use in order to calculate the correct offset to read 2638 * from the active module. 2639 * 2640 * Return: the exit code of the operation. 2641 */ 2642static int ixgbe_determine_active_flash_banks(struct ixgbe_hw *hw) 2643{ 2644 struct ixgbe_bank_info *banks = &hw->flash.banks; 2645 u16 ctrl_word; 2646 int err; 2647 2648 err = ixgbe_read_ee_aci_e610(hw, IXGBE_E610_SR_NVM_CTRL_WORD, 2649 &ctrl_word); 2650 if (err) 2651 return err; 2652 2653 if (FIELD_GET(IXGBE_SR_CTRL_WORD_1_M, ctrl_word) != 2654 IXGBE_SR_CTRL_WORD_VALID) 2655 return -ENODATA; 2656 2657 if (!(ctrl_word & IXGBE_SR_CTRL_WORD_NVM_BANK)) 2658 banks->nvm_bank = IXGBE_1ST_FLASH_BANK; 2659 else 2660 banks->nvm_bank = IXGBE_2ND_FLASH_BANK; 2661 2662 if (!(ctrl_word & IXGBE_SR_CTRL_WORD_OROM_BANK)) 2663 banks->orom_bank = IXGBE_1ST_FLASH_BANK; 2664 else 2665 banks->orom_bank = IXGBE_2ND_FLASH_BANK; 2666 2667 if (!(ctrl_word & IXGBE_SR_CTRL_WORD_NETLIST_BANK)) 2668 banks->netlist_bank = IXGBE_1ST_FLASH_BANK; 2669 else 2670 banks->netlist_bank = IXGBE_2ND_FLASH_BANK; 2671 2672 err = ixgbe_read_sr_base_address(hw, IXGBE_E610_SR_1ST_NVM_BANK_PTR, 2673 &banks->nvm_ptr); 2674 if (err) 2675 return err; 2676 2677 err = ixgbe_read_sr_area_size(hw, IXGBE_E610_SR_NVM_BANK_SIZE, 2678 &banks->nvm_size); 2679 if (err) 2680 return err; 2681 2682 err = ixgbe_read_sr_base_address(hw, IXGBE_E610_SR_1ST_OROM_BANK_PTR, 2683 &banks->orom_ptr); 2684 if (err) 2685 return err; 2686 2687 err = ixgbe_read_sr_area_size(hw, IXGBE_E610_SR_OROM_BANK_SIZE, 2688 &banks->orom_size); 2689 if (err) 2690 return err; 2691 2692 err = ixgbe_read_sr_base_address(hw, IXGBE_E610_SR_NETLIST_BANK_PTR, 2693 &banks->netlist_ptr); 2694 if (err) 2695 return err; 2696 2697 err = ixgbe_read_sr_area_size(hw, IXGBE_E610_SR_NETLIST_BANK_SIZE, 2698 &banks->netlist_size); 2699 2700 return err; 2701} 2702 2703/** 2704 * ixgbe_get_flash_bank_offset - Get offset into requested flash bank 2705 * @hw: pointer to the HW structure 2706 * @bank: whether to read from the active or inactive flash bank 2707 * @module: the module to read from 2708 * 2709 * Based on the module, lookup the module offset from the beginning of the 2710 * flash. 2711 * 2712 * Return: the flash offset. Note that a value of zero is invalid and must be 2713 * treated as an error. 2714 */ 2715static int ixgbe_get_flash_bank_offset(struct ixgbe_hw *hw, 2716 enum ixgbe_bank_select bank, 2717 u16 module) 2718{ 2719 struct ixgbe_bank_info *banks = &hw->flash.banks; 2720 enum ixgbe_flash_bank active_bank; 2721 bool second_bank_active; 2722 u32 offset, size; 2723 2724 switch (module) { 2725 case IXGBE_E610_SR_1ST_NVM_BANK_PTR: 2726 offset = banks->nvm_ptr; 2727 size = banks->nvm_size; 2728 active_bank = banks->nvm_bank; 2729 break; 2730 case IXGBE_E610_SR_1ST_OROM_BANK_PTR: 2731 offset = banks->orom_ptr; 2732 size = banks->orom_size; 2733 active_bank = banks->orom_bank; 2734 break; 2735 case IXGBE_E610_SR_NETLIST_BANK_PTR: 2736 offset = banks->netlist_ptr; 2737 size = banks->netlist_size; 2738 active_bank = banks->netlist_bank; 2739 break; 2740 default: 2741 return 0; 2742 } 2743 2744 switch (active_bank) { 2745 case IXGBE_1ST_FLASH_BANK: 2746 second_bank_active = false; 2747 break; 2748 case IXGBE_2ND_FLASH_BANK: 2749 second_bank_active = true; 2750 break; 2751 default: 2752 return 0; 2753 } 2754 2755 /* The second flash bank is stored immediately following the first 2756 * bank. Based on whether the 1st or 2nd bank is active, and whether 2757 * we want the active or inactive bank, calculate the desired offset. 2758 */ 2759 switch (bank) { 2760 case IXGBE_ACTIVE_FLASH_BANK: 2761 return offset + (second_bank_active ? size : 0); 2762 case IXGBE_INACTIVE_FLASH_BANK: 2763 return offset + (second_bank_active ? 0 : size); 2764 } 2765 2766 return 0; 2767} 2768 2769/** 2770 * ixgbe_read_flash_module - Read a word from one of the main NVM modules 2771 * @hw: pointer to the HW structure 2772 * @bank: which bank of the module to read 2773 * @module: the module to read 2774 * @offset: the offset into the module in bytes 2775 * @data: storage for the word read from the flash 2776 * @length: bytes of data to read 2777 * 2778 * Read data from the specified flash module. The bank parameter indicates 2779 * whether or not to read from the active bank or the inactive bank of that 2780 * module. 2781 * 2782 * The word will be read using flat NVM access, and relies on the 2783 * hw->flash.banks data being setup by ixgbe_determine_active_flash_banks() 2784 * during initialization. 2785 * 2786 * Return: the exit code of the operation. 2787 */ 2788static int ixgbe_read_flash_module(struct ixgbe_hw *hw, 2789 enum ixgbe_bank_select bank, 2790 u16 module, u32 offset, u8 *data, u32 length) 2791{ 2792 u32 start; 2793 int err; 2794 2795 start = ixgbe_get_flash_bank_offset(hw, bank, module); 2796 if (!start) 2797 return -EINVAL; 2798 2799 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 2800 if (err) 2801 return err; 2802 2803 err = ixgbe_read_flat_nvm(hw, start + offset, &length, data, false); 2804 2805 ixgbe_release_nvm(hw); 2806 2807 return err; 2808} 2809 2810/** 2811 * ixgbe_read_nvm_module - Read from the active main NVM module 2812 * @hw: pointer to the HW structure 2813 * @bank: whether to read from active or inactive NVM module 2814 * @offset: offset into the NVM module to read, in words 2815 * @data: storage for returned word value 2816 * 2817 * Read the specified word from the active NVM module. This includes the CSS 2818 * header at the start of the NVM module. 2819 * 2820 * Return: the exit code of the operation. 2821 */ 2822static int ixgbe_read_nvm_module(struct ixgbe_hw *hw, 2823 enum ixgbe_bank_select bank, 2824 u32 offset, u16 *data) 2825{ 2826 __le16 data_local; 2827 int err; 2828 2829 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_1ST_NVM_BANK_PTR, 2830 offset * sizeof(data_local), 2831 (u8 *)&data_local, 2832 sizeof(data_local)); 2833 if (!err) 2834 *data = le16_to_cpu(data_local); 2835 2836 return err; 2837} 2838 2839/** 2840 * ixgbe_read_netlist_module - Read data from the netlist module area 2841 * @hw: pointer to the HW structure 2842 * @bank: whether to read from the active or inactive module 2843 * @offset: offset into the netlist to read from 2844 * @data: storage for returned word value 2845 * 2846 * Read a word from the specified netlist bank. 2847 * 2848 * Return: the exit code of the operation. 2849 */ 2850static int ixgbe_read_netlist_module(struct ixgbe_hw *hw, 2851 enum ixgbe_bank_select bank, 2852 u32 offset, u16 *data) 2853{ 2854 __le16 data_local; 2855 int err; 2856 2857 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_NETLIST_BANK_PTR, 2858 offset * sizeof(data_local), 2859 (u8 *)&data_local, sizeof(data_local)); 2860 if (!err) 2861 *data = le16_to_cpu(data_local); 2862 2863 return err; 2864} 2865 2866/** 2867 * ixgbe_read_orom_module - Read from the active Option ROM module 2868 * @hw: pointer to the HW structure 2869 * @bank: whether to read from active or inactive OROM module 2870 * @offset: offset into the OROM module to read, in words 2871 * @data: storage for returned word value 2872 * 2873 * Read the specified word from the active Option ROM module of the flash. 2874 * Note that unlike the NVM module, the CSS data is stored at the end of the 2875 * module instead of at the beginning. 2876 * 2877 * Return: the exit code of the operation. 2878 */ 2879static int ixgbe_read_orom_module(struct ixgbe_hw *hw, 2880 enum ixgbe_bank_select bank, 2881 u32 offset, u16 *data) 2882{ 2883 __le16 data_local; 2884 int err; 2885 2886 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_1ST_OROM_BANK_PTR, 2887 offset * sizeof(data_local), 2888 (u8 *)&data_local, sizeof(data_local)); 2889 if (!err) 2890 *data = le16_to_cpu(data_local); 2891 2892 return err; 2893} 2894 2895/** 2896 * ixgbe_get_nvm_css_hdr_len - Read the CSS header length 2897 * @hw: pointer to the HW struct 2898 * @bank: whether to read from the active or inactive flash bank 2899 * @hdr_len: storage for header length in words 2900 * 2901 * Read the CSS header length from the NVM CSS header and add the 2902 * Authentication header size, and then convert to words. 2903 * 2904 * Return: the exit code of the operation. 2905 */ 2906static int ixgbe_get_nvm_css_hdr_len(struct ixgbe_hw *hw, 2907 enum ixgbe_bank_select bank, 2908 u32 *hdr_len) 2909{ 2910 u16 hdr_len_l, hdr_len_h; 2911 u32 hdr_len_dword; 2912 int err; 2913 2914 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_L, 2915 &hdr_len_l); 2916 if (err) 2917 return err; 2918 2919 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_H, 2920 &hdr_len_h); 2921 if (err) 2922 return err; 2923 2924 /* CSS header length is in DWORD, so convert to words and add 2925 * authentication header size. 2926 */ 2927 hdr_len_dword = (hdr_len_h << 16) | hdr_len_l; 2928 *hdr_len = hdr_len_dword * 2 + IXGBE_NVM_AUTH_HEADER_LEN; 2929 2930 return 0; 2931} 2932 2933/** 2934 * ixgbe_read_nvm_sr_copy - Read a word from the Shadow RAM copy 2935 * @hw: pointer to the HW structure 2936 * @bank: whether to read from the active or inactive NVM module 2937 * @offset: offset into the Shadow RAM copy to read, in words 2938 * @data: storage for returned word value 2939 * 2940 * Read the specified word from the copy of the Shadow RAM found in the 2941 * specified NVM module. 2942 * 2943 * Return: the exit code of the operation. 2944 */ 2945static int ixgbe_read_nvm_sr_copy(struct ixgbe_hw *hw, 2946 enum ixgbe_bank_select bank, 2947 u32 offset, u16 *data) 2948{ 2949 u32 hdr_len; 2950 int err; 2951 2952 err = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len); 2953 if (err) 2954 return err; 2955 2956 hdr_len = round_up(hdr_len, IXGBE_HDR_LEN_ROUNDUP); 2957 2958 return ixgbe_read_nvm_module(hw, bank, hdr_len + offset, data); 2959} 2960 2961/** 2962 * ixgbe_get_nvm_srev - Read the security revision from the NVM CSS header 2963 * @hw: pointer to the HW struct 2964 * @bank: whether to read from the active or inactive flash bank 2965 * @srev: storage for security revision 2966 * 2967 * Read the security revision out of the CSS header of the active NVM module 2968 * bank. 2969 * 2970 * Return: the exit code of the operation. 2971 */ 2972static int ixgbe_get_nvm_srev(struct ixgbe_hw *hw, 2973 enum ixgbe_bank_select bank, u32 *srev) 2974{ 2975 u16 srev_l, srev_h; 2976 int err; 2977 2978 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_L, &srev_l); 2979 if (err) 2980 return err; 2981 2982 err = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_H, &srev_h); 2983 if (err) 2984 return err; 2985 2986 *srev = (srev_h << 16) | srev_l; 2987 2988 return 0; 2989} 2990 2991/** 2992 * ixgbe_get_orom_civd_data - Get the combo version information from Option ROM 2993 * @hw: pointer to the HW struct 2994 * @bank: whether to read from the active or inactive flash module 2995 * @civd: storage for the Option ROM CIVD data. 2996 * 2997 * Searches through the Option ROM flash contents to locate the CIVD data for 2998 * the image. 2999 * 3000 * Return: -ENOMEM when cannot allocate memory, -EDOM for checksum violation, 3001 * -ENODATA when cannot find proper data, -EIO for faulty read or 3002 * 0 on success. 3003 * 3004 * On success @civd stores collected data. 3005 */ 3006static int 3007ixgbe_get_orom_civd_data(struct ixgbe_hw *hw, enum ixgbe_bank_select bank, 3008 struct ixgbe_orom_civd_info *civd) 3009{ 3010 u32 orom_size = hw->flash.banks.orom_size; 3011 u8 *orom_data; 3012 u32 offset; 3013 int err; 3014 3015 orom_data = kzalloc(orom_size, GFP_KERNEL); 3016 if (!orom_data) 3017 return -ENOMEM; 3018 3019 err = ixgbe_read_flash_module(hw, bank, 3020 IXGBE_E610_SR_1ST_OROM_BANK_PTR, 0, 3021 orom_data, orom_size); 3022 if (err) { 3023 err = -EIO; 3024 goto cleanup; 3025 } 3026 3027 /* The CIVD section is located in the Option ROM aligned to 512 bytes. 3028 * The first 4 bytes must contain the ASCII characters "$CIV". 3029 * A simple modulo 256 sum of all of the bytes of the structure must 3030 * equal 0. 3031 */ 3032 for (offset = 0; offset + SZ_512 <= orom_size; offset += SZ_512) { 3033 struct ixgbe_orom_civd_info *tmp; 3034 u8 sum = 0; 3035 u32 i; 3036 3037 BUILD_BUG_ON(sizeof(*tmp) > SZ_512); 3038 3039 tmp = (struct ixgbe_orom_civd_info *)&orom_data[offset]; 3040 3041 /* Skip forward until we find a matching signature */ 3042 if (memcmp(IXGBE_OROM_CIV_SIGNATURE, tmp->signature, 3043 sizeof(tmp->signature))) 3044 continue; 3045 3046 /* Verify that the simple checksum is zero */ 3047 for (i = 0; i < sizeof(*tmp); i++) 3048 sum += ((u8 *)tmp)[i]; 3049 3050 if (sum) { 3051 err = -EDOM; 3052 goto cleanup; 3053 } 3054 3055 *civd = *tmp; 3056 err = 0; 3057 3058 goto cleanup; 3059 } 3060 3061 err = -ENODATA; 3062cleanup: 3063 kfree(orom_data); 3064 return err; 3065} 3066 3067/** 3068 * ixgbe_get_orom_srev - Read the security revision from the OROM CSS header 3069 * @hw: pointer to the HW struct 3070 * @bank: whether to read from active or inactive flash module 3071 * @srev: storage for security revision 3072 * 3073 * Read the security revision out of the CSS header of the active OROM module 3074 * bank. 3075 * 3076 * Return: the exit code of the operation. 3077 */ 3078static int ixgbe_get_orom_srev(struct ixgbe_hw *hw, 3079 enum ixgbe_bank_select bank, 3080 u32 *srev) 3081{ 3082 u32 orom_size_word = hw->flash.banks.orom_size / 2; 3083 u32 css_start, hdr_len; 3084 u16 srev_l, srev_h; 3085 int err; 3086 3087 err = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len); 3088 if (err) 3089 return err; 3090 3091 if (orom_size_word < hdr_len) 3092 return -EINVAL; 3093 3094 /* Calculate how far into the Option ROM the CSS header starts. Note 3095 * that ixgbe_read_orom_module takes a word offset. 3096 */ 3097 css_start = orom_size_word - hdr_len; 3098 err = ixgbe_read_orom_module(hw, bank, 3099 css_start + IXGBE_NVM_CSS_SREV_L, 3100 &srev_l); 3101 if (err) 3102 return err; 3103 3104 err = ixgbe_read_orom_module(hw, bank, 3105 css_start + IXGBE_NVM_CSS_SREV_H, 3106 &srev_h); 3107 if (err) 3108 return err; 3109 3110 *srev = srev_h << 16 | srev_l; 3111 3112 return 0; 3113} 3114 3115/** 3116 * ixgbe_get_orom_ver_info - Read Option ROM version information 3117 * @hw: pointer to the HW struct 3118 * @bank: whether to read from the active or inactive flash module 3119 * @orom: pointer to Option ROM info structure 3120 * 3121 * Read Option ROM version and security revision from the Option ROM flash 3122 * section. 3123 * 3124 * Return: the exit code of the operation. 3125 */ 3126static int ixgbe_get_orom_ver_info(struct ixgbe_hw *hw, 3127 enum ixgbe_bank_select bank, 3128 struct ixgbe_orom_info *orom) 3129{ 3130 struct ixgbe_orom_civd_info civd; 3131 u32 combo_ver; 3132 int err; 3133 3134 err = ixgbe_get_orom_civd_data(hw, bank, &civd); 3135 if (err) 3136 return err; 3137 3138 combo_ver = get_unaligned_le32(&civd.combo_ver); 3139 3140 orom->major = (u8)FIELD_GET(IXGBE_OROM_VER_MASK, combo_ver); 3141 orom->patch = (u8)FIELD_GET(IXGBE_OROM_VER_PATCH_MASK, combo_ver); 3142 orom->build = (u16)FIELD_GET(IXGBE_OROM_VER_BUILD_MASK, combo_ver); 3143 3144 return ixgbe_get_orom_srev(hw, bank, &orom->srev); 3145} 3146 3147/** 3148 * ixgbe_get_inactive_orom_ver - Read Option ROM version from the inactive bank 3149 * @hw: pointer to the HW structure 3150 * @orom: storage for Option ROM version information 3151 * 3152 * Read the Option ROM version and security revision data for the inactive 3153 * section of flash. Used to access version data for a pending update that has 3154 * not yet been activated. 3155 * 3156 * Return: the exit code of the operation. 3157 */ 3158int ixgbe_get_inactive_orom_ver(struct ixgbe_hw *hw, 3159 struct ixgbe_orom_info *orom) 3160{ 3161 return ixgbe_get_orom_ver_info(hw, IXGBE_INACTIVE_FLASH_BANK, orom); 3162} 3163 3164/** 3165 * ixgbe_get_nvm_ver_info - Read NVM version information 3166 * @hw: pointer to the HW struct 3167 * @bank: whether to read from the active or inactive flash bank 3168 * @nvm: pointer to NVM info structure 3169 * 3170 * Read the NVM EETRACK ID and map version of the main NVM image bank, filling 3171 * in the nvm info structure. 3172 * 3173 * Return: the exit code of the operation. 3174 */ 3175static int ixgbe_get_nvm_ver_info(struct ixgbe_hw *hw, 3176 enum ixgbe_bank_select bank, 3177 struct ixgbe_nvm_info *nvm) 3178{ 3179 u16 eetrack_lo, eetrack_hi, ver; 3180 int err; 3181 3182 err = ixgbe_read_nvm_sr_copy(hw, bank, 3183 IXGBE_E610_SR_NVM_DEV_STARTER_VER, &ver); 3184 if (err) 3185 return err; 3186 3187 nvm->major = FIELD_GET(IXGBE_E610_NVM_VER_HI_MASK, ver); 3188 nvm->minor = FIELD_GET(IXGBE_E610_NVM_VER_LO_MASK, ver); 3189 3190 err = ixgbe_read_nvm_sr_copy(hw, bank, IXGBE_E610_SR_NVM_EETRACK_LO, 3191 &eetrack_lo); 3192 if (err) 3193 return err; 3194 3195 err = ixgbe_read_nvm_sr_copy(hw, bank, IXGBE_E610_SR_NVM_EETRACK_HI, 3196 &eetrack_hi); 3197 if (err) 3198 return err; 3199 3200 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo; 3201 3202 ixgbe_get_nvm_srev(hw, bank, &nvm->srev); 3203 3204 return 0; 3205} 3206 3207/** 3208 * ixgbe_get_inactive_nvm_ver - Read Option ROM version from the inactive bank 3209 * @hw: pointer to the HW structure 3210 * @nvm: storage for Option ROM version information 3211 * 3212 * Read the NVM EETRACK ID, Map version, and security revision of the 3213 * inactive NVM bank. Used to access version data for a pending update that 3214 * has not yet been activated. 3215 * 3216 * Return: the exit code of the operation. 3217 */ 3218int ixgbe_get_inactive_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm) 3219{ 3220 return ixgbe_get_nvm_ver_info(hw, IXGBE_INACTIVE_FLASH_BANK, nvm); 3221} 3222 3223/** 3224 * ixgbe_get_active_nvm_ver - Read Option ROM version from the active bank 3225 * @hw: pointer to the HW structure 3226 * @nvm: storage for Option ROM version information 3227 * 3228 * Reads the NVM EETRACK ID, Map version, and security revision of the 3229 * active NVM bank. 3230 * 3231 * Return: the exit code of the operation. 3232 */ 3233static int ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, 3234 struct ixgbe_nvm_info *nvm) 3235{ 3236 return ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, nvm); 3237} 3238 3239/** 3240 * ixgbe_get_netlist_info - Read the netlist version information 3241 * @hw: pointer to the HW struct 3242 * @bank: whether to read from the active or inactive flash bank 3243 * @netlist: pointer to netlist version info structure 3244 * 3245 * Get the netlist version information from the requested bank. Reads the Link 3246 * Topology section to find the Netlist ID block and extract the relevant 3247 * information into the netlist version structure. 3248 * 3249 * Return: the exit code of the operation. 3250 */ 3251static int ixgbe_get_netlist_info(struct ixgbe_hw *hw, 3252 enum ixgbe_bank_select bank, 3253 struct ixgbe_netlist_info *netlist) 3254{ 3255 u16 module_id, length, node_count, i; 3256 u16 *id_blk; 3257 int err; 3258 3259 err = ixgbe_read_netlist_module(hw, bank, IXGBE_NETLIST_TYPE_OFFSET, 3260 &module_id); 3261 if (err) 3262 return err; 3263 3264 if (module_id != IXGBE_NETLIST_LINK_TOPO_MOD_ID) 3265 return -EIO; 3266 3267 err = ixgbe_read_netlist_module(hw, bank, IXGBE_LINK_TOPO_MODULE_LEN, 3268 &length); 3269 if (err) 3270 return err; 3271 3272 /* Sanity check that we have at least enough words to store the 3273 * netlist ID block. 3274 */ 3275 if (length < IXGBE_NETLIST_ID_BLK_SIZE) 3276 return -EIO; 3277 3278 err = ixgbe_read_netlist_module(hw, bank, IXGBE_LINK_TOPO_NODE_COUNT, 3279 &node_count); 3280 if (err) 3281 return err; 3282 3283 node_count &= IXGBE_LINK_TOPO_NODE_COUNT_M; 3284 3285 id_blk = kcalloc(IXGBE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk), GFP_KERNEL); 3286 if (!id_blk) 3287 return -ENOMEM; 3288 3289 /* Read out the entire Netlist ID Block at once. */ 3290 err = ixgbe_read_flash_module(hw, bank, IXGBE_E610_SR_NETLIST_BANK_PTR, 3291 IXGBE_NETLIST_ID_BLK_OFFSET(node_count) * 3292 sizeof(*id_blk), (u8 *)id_blk, 3293 IXGBE_NETLIST_ID_BLK_SIZE * 3294 sizeof(*id_blk)); 3295 if (err) 3296 goto free_id_blk; 3297 3298 for (i = 0; i < IXGBE_NETLIST_ID_BLK_SIZE; i++) 3299 id_blk[i] = le16_to_cpu(((__le16 *)id_blk)[i]); 3300 3301 netlist->major = id_blk[IXGBE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 | 3302 id_blk[IXGBE_NETLIST_ID_BLK_MAJOR_VER_LOW]; 3303 netlist->minor = id_blk[IXGBE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 | 3304 id_blk[IXGBE_NETLIST_ID_BLK_MINOR_VER_LOW]; 3305 netlist->type = id_blk[IXGBE_NETLIST_ID_BLK_TYPE_HIGH] << 16 | 3306 id_blk[IXGBE_NETLIST_ID_BLK_TYPE_LOW]; 3307 netlist->rev = id_blk[IXGBE_NETLIST_ID_BLK_REV_HIGH] << 16 | 3308 id_blk[IXGBE_NETLIST_ID_BLK_REV_LOW]; 3309 netlist->cust_ver = id_blk[IXGBE_NETLIST_ID_BLK_CUST_VER]; 3310 /* Read the left most 4 bytes of SHA */ 3311 netlist->hash = id_blk[IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 | 3312 id_blk[IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(14)]; 3313 3314free_id_blk: 3315 kfree(id_blk); 3316 return err; 3317} 3318 3319/** 3320 * ixgbe_get_inactive_netlist_ver - Read netlist version from the inactive bank 3321 * @hw: pointer to the HW struct 3322 * @netlist: pointer to netlist version info structure 3323 * 3324 * Read the netlist version data from the inactive netlist bank. Used to 3325 * extract version data of a pending flash update in order to display the 3326 * version data. 3327 * 3328 * Return: the exit code of the operation. 3329 */ 3330int ixgbe_get_inactive_netlist_ver(struct ixgbe_hw *hw, 3331 struct ixgbe_netlist_info *netlist) 3332{ 3333 return ixgbe_get_netlist_info(hw, IXGBE_INACTIVE_FLASH_BANK, netlist); 3334} 3335 3336/** 3337 * ixgbe_get_flash_data - get flash data 3338 * @hw: pointer to the HW struct 3339 * 3340 * Read and populate flash data such as Shadow RAM size, 3341 * max_timeout and blank_nvm_mode 3342 * 3343 * Return: the exit code of the operation. 3344 */ 3345int ixgbe_get_flash_data(struct ixgbe_hw *hw) 3346{ 3347 struct ixgbe_flash_info *flash = &hw->flash; 3348 u32 fla, gens_stat; 3349 u8 sr_size; 3350 int err; 3351 3352 /* The SR size is stored regardless of the NVM programming mode 3353 * as the blank mode may be used in the factory line. 3354 */ 3355 gens_stat = IXGBE_READ_REG(hw, GLNVM_GENS); 3356 sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat); 3357 3358 /* Switching to words (sr_size contains power of 2) */ 3359 flash->sr_words = BIT(sr_size) * (SZ_1K / sizeof(u16)); 3360 3361 /* Check if we are in the normal or blank NVM programming mode */ 3362 fla = IXGBE_READ_REG(hw, IXGBE_GLNVM_FLA); 3363 if (fla & IXGBE_GLNVM_FLA_LOCKED_M) { 3364 flash->blank_nvm_mode = false; 3365 } else { 3366 flash->blank_nvm_mode = true; 3367 return -EIO; 3368 } 3369 3370 err = ixgbe_discover_flash_size(hw); 3371 if (err) 3372 return err; 3373 3374 err = ixgbe_determine_active_flash_banks(hw); 3375 if (err) 3376 return err; 3377 3378 err = ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, 3379 &flash->nvm); 3380 if (err) 3381 return err; 3382 3383 err = ixgbe_get_orom_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, 3384 &flash->orom); 3385 if (err) 3386 return err; 3387 3388 err = ixgbe_get_netlist_info(hw, IXGBE_ACTIVE_FLASH_BANK, 3389 &flash->netlist); 3390 return err; 3391} 3392 3393/** 3394 * ixgbe_aci_nvm_update_empr - update NVM using EMPR 3395 * @hw: pointer to the HW struct 3396 * 3397 * Force EMP reset using ACI command (0x0709). This command allows SW to 3398 * request an EMPR to activate new FW. 3399 * 3400 * Return: the exit code of the operation. 3401 */ 3402int ixgbe_aci_nvm_update_empr(struct ixgbe_hw *hw) 3403{ 3404 struct libie_aq_desc desc; 3405 3406 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_update_empr); 3407 3408 return ixgbe_aci_send_cmd(hw, &desc, NULL, 0); 3409} 3410 3411/* ixgbe_nvm_set_pkg_data - NVM set package data 3412 * @hw: pointer to the HW struct 3413 * @del_pkg_data_flag: If is set then the current pkg_data store by FW 3414 * is deleted. 3415 * If bit is set to 1, then buffer should be size 0. 3416 * @data: pointer to buffer 3417 * @length: length of the buffer 3418 * 3419 * Set package data using ACI command (0x070A). 3420 * This command is equivalent to the reception of 3421 * a PLDM FW Update GetPackageData cmd. This command should be sent 3422 * as part of the NVM update as the first cmd in the flow. 3423 * 3424 * Return: the exit code of the operation. 3425 */ 3426int ixgbe_nvm_set_pkg_data(struct ixgbe_hw *hw, bool del_pkg_data_flag, 3427 u8 *data, u16 length) 3428{ 3429 struct ixgbe_aci_cmd_nvm_pkg_data *cmd; 3430 struct libie_aq_desc desc; 3431 3432 if (length != 0 && !data) 3433 return -EINVAL; 3434 3435 cmd = libie_aq_raw(&desc); 3436 3437 ixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_pkg_data); 3438 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3439 3440 if (del_pkg_data_flag) 3441 cmd->cmd_flags |= IXGBE_ACI_NVM_PKG_DELETE; 3442 3443 return ixgbe_aci_send_cmd(hw, &desc, data, length); 3444} 3445 3446/* ixgbe_nvm_pass_component_tbl - NVM pass component table 3447 * @hw: pointer to the HW struct 3448 * @data: pointer to buffer 3449 * @length: length of the buffer 3450 * @transfer_flag: parameter for determining stage of the update 3451 * @comp_response: a pointer to the response from the 0x070B ACI. 3452 * @comp_response_code: a pointer to the response code from the 0x070B ACI. 3453 * 3454 * Pass component table using ACI command (0x070B). This command is equivalent 3455 * to the reception of a PLDM FW Update PassComponentTable cmd. 3456 * This command should be sent once per component. It can be only sent after 3457 * Set Package Data cmd and before actual update. FW will assume these 3458 * commands are going to be sent until the TransferFlag is set to End or 3459 * StartAndEnd. 3460 * 3461 * Return: the exit code of the operation. 3462 */ 3463int ixgbe_nvm_pass_component_tbl(struct ixgbe_hw *hw, u8 *data, u16 length, 3464 u8 transfer_flag, u8 *comp_response, 3465 u8 *comp_response_code) 3466{ 3467 struct ixgbe_aci_cmd_nvm_pass_comp_tbl *cmd; 3468 struct libie_aq_desc desc; 3469 int err; 3470 3471 if (!data || !comp_response || !comp_response_code) 3472 return -EINVAL; 3473 3474 cmd = libie_aq_raw(&desc); 3475 3476 ixgbe_fill_dflt_direct_cmd_desc(&desc, 3477 ixgbe_aci_opc_nvm_pass_component_tbl); 3478 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3479 3480 cmd->transfer_flag = transfer_flag; 3481 err = ixgbe_aci_send_cmd(hw, &desc, data, length); 3482 if (!err) { 3483 *comp_response = cmd->component_response; 3484 *comp_response_code = cmd->component_response_code; 3485 } 3486 3487 return err; 3488} 3489 3490/** 3491 * ixgbe_read_sr_word_aci - Reads Shadow RAM via ACI 3492 * @hw: pointer to the HW structure 3493 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 3494 * @data: word read from the Shadow RAM 3495 * 3496 * Reads one 16 bit word from the Shadow RAM using ixgbe_read_flat_nvm. 3497 * 3498 * Return: the exit code of the operation. 3499 */ 3500int ixgbe_read_sr_word_aci(struct ixgbe_hw *hw, u16 offset, u16 *data) 3501{ 3502 u32 bytes = sizeof(u16); 3503 u16 data_local; 3504 int err; 3505 3506 err = ixgbe_read_flat_nvm(hw, offset * sizeof(u16), &bytes, 3507 (u8 *)&data_local, true); 3508 if (err) 3509 return err; 3510 3511 *data = data_local; 3512 return 0; 3513} 3514 3515/** 3516 * ixgbe_read_flat_nvm - Read portion of NVM by flat offset 3517 * @hw: pointer to the HW struct 3518 * @offset: offset from beginning of NVM 3519 * @length: (in) number of bytes to read; (out) number of bytes actually read 3520 * @data: buffer to return data in (sized to fit the specified length) 3521 * @read_shadow_ram: if true, read from shadow RAM instead of NVM 3522 * 3523 * Reads a portion of the NVM, as a flat memory space. This function correctly 3524 * breaks read requests across Shadow RAM sectors, prevents Shadow RAM size 3525 * from being exceeded in case of Shadow RAM read requests and ensures that no 3526 * single read request exceeds the maximum 4KB read for a single admin command. 3527 * 3528 * Returns an error code on failure. Note that the data pointer may be 3529 * partially updated if some reads succeed before a failure. 3530 * 3531 * Return: the exit code of the operation. 3532 */ 3533int ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length, 3534 u8 *data, bool read_shadow_ram) 3535{ 3536 u32 inlen = *length; 3537 u32 bytes_read = 0; 3538 bool last_cmd; 3539 int err; 3540 3541 /* Verify the length of the read if this is for the Shadow RAM */ 3542 if (read_shadow_ram && ((offset + inlen) > 3543 (hw->eeprom.word_size * 2u))) 3544 return -EINVAL; 3545 3546 do { 3547 u32 read_size, sector_offset; 3548 3549 /* ixgbe_aci_read_nvm cannot read more than 4KB at a time. 3550 * Additionally, a read from the Shadow RAM may not cross over 3551 * a sector boundary. Conveniently, the sector size is also 4KB. 3552 */ 3553 sector_offset = offset % IXGBE_ACI_MAX_BUFFER_SIZE; 3554 read_size = min_t(u32, 3555 IXGBE_ACI_MAX_BUFFER_SIZE - sector_offset, 3556 inlen - bytes_read); 3557 3558 last_cmd = !(bytes_read + read_size < inlen); 3559 3560 /* ixgbe_aci_read_nvm takes the length as a u16. Our read_size 3561 * is calculated using a u32, but the IXGBE_ACI_MAX_BUFFER_SIZE 3562 * maximum size guarantees that it will fit within the 2 bytes. 3563 */ 3564 err = ixgbe_aci_read_nvm(hw, IXGBE_ACI_NVM_START_POINT, 3565 offset, (u16)read_size, 3566 data + bytes_read, last_cmd, 3567 read_shadow_ram); 3568 if (err) 3569 break; 3570 3571 bytes_read += read_size; 3572 offset += read_size; 3573 } while (!last_cmd); 3574 3575 *length = bytes_read; 3576 return err; 3577} 3578 3579/** 3580 * ixgbe_read_sr_buf_aci - Read Shadow RAM buffer via ACI 3581 * @hw: pointer to the HW structure 3582 * @offset: offset of the Shadow RAM words to read (0x000000 - 0x001FFF) 3583 * @words: (in) number of words to read; (out) number of words actually read 3584 * @data: words read from the Shadow RAM 3585 * 3586 * Read 16 bit words (data buf) from the Shadow RAM. Acquire/release the NVM 3587 * ownership. 3588 * 3589 * Return: the operation exit code. 3590 */ 3591int ixgbe_read_sr_buf_aci(struct ixgbe_hw *hw, u16 offset, u16 *words, 3592 u16 *data) 3593{ 3594 u32 bytes = *words * 2; 3595 int err; 3596 3597 err = ixgbe_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true); 3598 if (err) 3599 return err; 3600 3601 *words = bytes / 2; 3602 3603 for (int i = 0; i < *words; i++) 3604 data[i] = le16_to_cpu(((__le16 *)data)[i]); 3605 3606 return 0; 3607} 3608 3609/** 3610 * ixgbe_read_ee_aci_e610 - Read EEPROM word using the admin command. 3611 * @hw: pointer to hardware structure 3612 * @offset: offset of word in the EEPROM to read 3613 * @data: word read from the EEPROM 3614 * 3615 * Reads a 16 bit word from the EEPROM using the ACI. 3616 * If the EEPROM params are not initialized, the function 3617 * initialize them before proceeding with reading. 3618 * The function acquires and then releases the NVM ownership. 3619 * 3620 * Return: the exit code of the operation. 3621 */ 3622int ixgbe_read_ee_aci_e610(struct ixgbe_hw *hw, u16 offset, u16 *data) 3623{ 3624 int err; 3625 3626 if (hw->eeprom.type == ixgbe_eeprom_uninitialized) { 3627 err = hw->eeprom.ops.init_params(hw); 3628 if (err) 3629 return err; 3630 } 3631 3632 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 3633 if (err) 3634 return err; 3635 3636 err = ixgbe_read_sr_word_aci(hw, offset, data); 3637 ixgbe_release_nvm(hw); 3638 3639 return err; 3640} 3641 3642/** 3643 * ixgbe_read_ee_aci_buffer_e610 - Read EEPROM words via ACI 3644 * @hw: pointer to hardware structure 3645 * @offset: offset of words in the EEPROM to read 3646 * @words: number of words to read 3647 * @data: words to read from the EEPROM 3648 * 3649 * Read 16 bit words from the EEPROM via the ACI. Initialize the EEPROM params 3650 * prior to the read. Acquire/release the NVM ownership. 3651 * 3652 * Return: the operation exit code. 3653 */ 3654int ixgbe_read_ee_aci_buffer_e610(struct ixgbe_hw *hw, u16 offset, 3655 u16 words, u16 *data) 3656{ 3657 int err; 3658 3659 if (hw->eeprom.type == ixgbe_eeprom_uninitialized) { 3660 err = hw->eeprom.ops.init_params(hw); 3661 if (err) 3662 return err; 3663 } 3664 3665 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 3666 if (err) 3667 return err; 3668 3669 err = ixgbe_read_sr_buf_aci(hw, offset, &words, data); 3670 ixgbe_release_nvm(hw); 3671 3672 return err; 3673} 3674 3675/** 3676 * ixgbe_validate_eeprom_checksum_e610 - Validate EEPROM checksum 3677 * @hw: pointer to hardware structure 3678 * @checksum_val: calculated checksum 3679 * 3680 * Performs checksum calculation and validates the EEPROM checksum. If the 3681 * caller does not need checksum_val, the value can be NULL. 3682 * If the EEPROM params are not initialized, the function 3683 * initialize them before proceeding. 3684 * The function acquires and then releases the NVM ownership. 3685 * 3686 * Return: the exit code of the operation. 3687 */ 3688int ixgbe_validate_eeprom_checksum_e610(struct ixgbe_hw *hw, u16 *checksum_val) 3689{ 3690 int err; 3691 3692 if (hw->eeprom.type == ixgbe_eeprom_uninitialized) { 3693 err = hw->eeprom.ops.init_params(hw); 3694 if (err) 3695 return err; 3696 } 3697 3698 err = ixgbe_nvm_validate_checksum(hw); 3699 if (err) 3700 return err; 3701 3702 if (checksum_val) { 3703 u16 tmp_checksum; 3704 3705 err = ixgbe_acquire_nvm(hw, LIBIE_AQC_RES_ACCESS_READ); 3706 if (err) 3707 return err; 3708 3709 err = ixgbe_read_sr_word_aci(hw, IXGBE_E610_SR_SW_CHECKSUM_WORD, 3710 &tmp_checksum); 3711 ixgbe_release_nvm(hw); 3712 3713 if (!err) 3714 *checksum_val = tmp_checksum; 3715 } 3716 3717 return err; 3718} 3719 3720/** 3721 * ixgbe_reset_hw_e610 - Perform hardware reset 3722 * @hw: pointer to hardware structure 3723 * 3724 * Resets the hardware by resetting the transmit and receive units, masks 3725 * and clears all interrupts, and performs a reset. 3726 * 3727 * Return: the exit code of the operation. 3728 */ 3729int ixgbe_reset_hw_e610(struct ixgbe_hw *hw) 3730{ 3731 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3732 u32 ctrl, i; 3733 int err; 3734 3735 /* Call adapter stop to disable tx/rx and clear interrupts */ 3736 err = hw->mac.ops.stop_adapter(hw); 3737 if (err) 3738 goto reset_hw_out; 3739 3740 /* Flush pending Tx transactions. */ 3741 ixgbe_clear_tx_pending(hw); 3742 3743 hw->phy.ops.init(hw); 3744mac_reset_top: 3745 err = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3746 if (err) 3747 return -EBUSY; 3748 ctrl = IXGBE_CTRL_RST; 3749 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3750 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3751 IXGBE_WRITE_FLUSH(hw); 3752 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3753 3754 /* Poll for reset bit to self-clear indicating reset is complete */ 3755 for (i = 0; i < 10; i++) { 3756 udelay(1); 3757 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3758 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3759 break; 3760 } 3761 3762 if (ctrl & IXGBE_CTRL_RST_MASK) { 3763 struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, 3764 hw); 3765 3766 err = -EIO; 3767 netdev_err(adapter->netdev, "Reset polling failed to complete."); 3768 } 3769 3770 /* Double resets are required for recovery from certain error 3771 * conditions. Between resets, it is necessary to stall to allow time 3772 * for any pending HW events to complete. 3773 */ 3774 msleep(100); 3775 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3776 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3777 goto mac_reset_top; 3778 } 3779 3780 /* Set the Rx packet buffer size. */ 3781 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), GENMASK(18, 17)); 3782 3783 /* Store the permanent mac address */ 3784 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3785 3786 /* Maximum number of Receive Address Registers. */ 3787#define IXGBE_MAX_NUM_RAR 128 3788 3789 /* Store MAC address from RAR0, clear receive address registers, and 3790 * clear the multicast table. Also reset num_rar_entries to the 3791 * maximum number of Receive Address Registers, since we modify this 3792 * value when programming the SAN MAC address. 3793 */ 3794 hw->mac.num_rar_entries = IXGBE_MAX_NUM_RAR; 3795 hw->mac.ops.init_rx_addrs(hw); 3796 3797 /* Initialize bus function number */ 3798 hw->mac.ops.set_lan_id(hw); 3799 3800reset_hw_out: 3801 return err; 3802} 3803 3804/** 3805 * ixgbe_get_pfa_module_tlv - Read sub module TLV from NVM PFA 3806 * @hw: pointer to hardware structure 3807 * @module_tlv: pointer to module TLV to return 3808 * @module_tlv_len: pointer to module TLV length to return 3809 * @module_type: module type requested 3810 * 3811 * Find the requested sub module TLV type from the Preserved Field 3812 * Area (PFA) and returns the TLV pointer and length. The caller can 3813 * use these to read the variable length TLV value. 3814 * 3815 * Return: the exit code of the operation. 3816 */ 3817static int ixgbe_get_pfa_module_tlv(struct ixgbe_hw *hw, u16 *module_tlv, 3818 u16 *module_tlv_len, u16 module_type) 3819{ 3820 u16 pfa_len, pfa_ptr, pfa_end_ptr; 3821 u16 next_tlv; 3822 int err; 3823 3824 err = ixgbe_read_ee_aci_e610(hw, IXGBE_E610_SR_PFA_PTR, &pfa_ptr); 3825 if (err) 3826 return err; 3827 3828 err = ixgbe_read_ee_aci_e610(hw, pfa_ptr, &pfa_len); 3829 if (err) 3830 return err; 3831 3832 /* Starting with first TLV after PFA length, iterate through the list 3833 * of TLVs to find the requested one. 3834 */ 3835 next_tlv = pfa_ptr + 1; 3836 pfa_end_ptr = pfa_ptr + pfa_len; 3837 while (next_tlv < pfa_end_ptr) { 3838 u16 tlv_sub_module_type, tlv_len; 3839 3840 /* Read TLV type */ 3841 err = ixgbe_read_ee_aci_e610(hw, next_tlv, 3842 &tlv_sub_module_type); 3843 if (err) 3844 break; 3845 3846 /* Read TLV length */ 3847 err = ixgbe_read_ee_aci_e610(hw, next_tlv + 1, &tlv_len); 3848 if (err) 3849 break; 3850 3851 if (tlv_sub_module_type == module_type) { 3852 if (tlv_len) { 3853 *module_tlv = next_tlv; 3854 *module_tlv_len = tlv_len; 3855 return 0; 3856 } 3857 return -EIO; 3858 } 3859 /* Check next TLV, i.e. current TLV pointer + length + 2 words 3860 * (for current TLV's type and length). 3861 */ 3862 next_tlv = next_tlv + tlv_len + 2; 3863 } 3864 /* Module does not exist */ 3865 return -ENODATA; 3866} 3867 3868/** 3869 * ixgbe_read_pba_string_e610 - Read PBA string from NVM 3870 * @hw: pointer to hardware structure 3871 * @pba_num: stores the part number string from the NVM 3872 * @pba_num_size: part number string buffer length 3873 * 3874 * Read the part number string from the NVM. 3875 * 3876 * Return: the exit code of the operation. 3877 */ 3878static int ixgbe_read_pba_string_e610(struct ixgbe_hw *hw, u8 *pba_num, 3879 u32 pba_num_size) 3880{ 3881 u16 pba_tlv, pba_tlv_len; 3882 u16 pba_word, pba_size; 3883 int err; 3884 3885 *pba_num = '\0'; 3886 3887 err = ixgbe_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len, 3888 IXGBE_E610_SR_PBA_BLOCK_PTR); 3889 if (err) 3890 return err; 3891 3892 /* pba_size is the next word */ 3893 err = ixgbe_read_ee_aci_e610(hw, (pba_tlv + 2), &pba_size); 3894 if (err) 3895 return err; 3896 3897 if (pba_tlv_len < pba_size) 3898 return -EINVAL; 3899 3900 /* Subtract one to get PBA word count (PBA Size word is included in 3901 * total size). 3902 */ 3903 pba_size--; 3904 3905 if (pba_num_size < (((u32)pba_size * 2) + 1)) 3906 return -EINVAL; 3907 3908 for (u16 i = 0; i < pba_size; i++) { 3909 err = ixgbe_read_ee_aci_e610(hw, (pba_tlv + 2 + 1) + i, 3910 &pba_word); 3911 if (err) 3912 return err; 3913 3914 pba_num[(i * 2)] = FIELD_GET(IXGBE_E610_SR_PBA_BLOCK_MASK, 3915 pba_word); 3916 pba_num[(i * 2) + 1] = pba_word & 0xFF; 3917 } 3918 3919 pba_num[(pba_size * 2)] = '\0'; 3920 3921 return err; 3922} 3923 3924static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 3925 u16 size) 3926{ 3927 struct ixgbe_hw *hw = priv; 3928 3929 return ixgbe_aci_send_cmd(hw, desc, buf, size); 3930} 3931 3932int ixgbe_fwlog_init(struct ixgbe_hw *hw) 3933{ 3934 struct ixgbe_adapter *adapter = hw->back; 3935 struct libie_fwlog_api api = { 3936 .pdev = adapter->pdev, 3937 .send_cmd = __fwlog_send_cmd, 3938 .debugfs_root = adapter->ixgbe_dbg_adapter, 3939 .priv = hw, 3940 }; 3941 3942 if (hw->mac.type != ixgbe_mac_e610) 3943 return -EOPNOTSUPP; 3944 3945 return libie_fwlog_init(&hw->fwlog, &api); 3946} 3947 3948void ixgbe_fwlog_deinit(struct ixgbe_hw *hw) 3949{ 3950 if (hw->mac.type != ixgbe_mac_e610) 3951 return; 3952 3953 libie_fwlog_deinit(&hw->fwlog); 3954} 3955 3956static const struct ixgbe_mac_operations mac_ops_e610 = { 3957 .init_hw = ixgbe_init_hw_generic, 3958 .start_hw = ixgbe_start_hw_e610, 3959 .clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic, 3960 .enable_rx_dma = ixgbe_enable_rx_dma_generic, 3961 .get_mac_addr = ixgbe_get_mac_addr_generic, 3962 .get_device_caps = ixgbe_get_device_caps_generic, 3963 .stop_adapter = ixgbe_stop_adapter_generic, 3964 .set_lan_id = ixgbe_set_lan_id_multi_port_pcie, 3965 .set_rxpba = ixgbe_set_rxpba_generic, 3966 .check_link = ixgbe_check_link_e610, 3967 .blink_led_start = ixgbe_blink_led_start_X540, 3968 .blink_led_stop = ixgbe_blink_led_stop_X540, 3969 .set_rar = ixgbe_set_rar_generic, 3970 .clear_rar = ixgbe_clear_rar_generic, 3971 .set_vmdq = ixgbe_set_vmdq_generic, 3972 .set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic, 3973 .clear_vmdq = ixgbe_clear_vmdq_generic, 3974 .init_rx_addrs = ixgbe_init_rx_addrs_generic, 3975 .update_mc_addr_list = ixgbe_update_mc_addr_list_generic, 3976 .enable_mc = ixgbe_enable_mc_generic, 3977 .disable_mc = ixgbe_disable_mc_generic, 3978 .clear_vfta = ixgbe_clear_vfta_generic, 3979 .set_vfta = ixgbe_set_vfta_generic, 3980 .fc_enable = ixgbe_fc_enable_generic, 3981 .set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550, 3982 .init_uta_tables = ixgbe_init_uta_tables_generic, 3983 .set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing, 3984 .set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing, 3985 .set_source_address_pruning = 3986 ixgbe_set_source_address_pruning_x550, 3987 .set_ethertype_anti_spoofing = 3988 ixgbe_set_ethertype_anti_spoofing_x550, 3989 .disable_rx_buff = ixgbe_disable_rx_buff_generic, 3990 .enable_rx_buff = ixgbe_enable_rx_buff_generic, 3991 .enable_rx = ixgbe_enable_rx_generic, 3992 .disable_rx = ixgbe_disable_rx_e610, 3993 .led_on = ixgbe_led_on_generic, 3994 .led_off = ixgbe_led_off_generic, 3995 .init_led_link_act = ixgbe_init_led_link_act_generic, 3996 .reset_hw = ixgbe_reset_hw_e610, 3997 .get_fw_ver = ixgbe_aci_get_fw_ver, 3998 .get_media_type = ixgbe_get_media_type_e610, 3999 .setup_link = ixgbe_setup_link_e610, 4000 .fw_recovery_mode = ixgbe_fw_recovery_mode_e610, 4001 .fw_rollback_mode = ixgbe_fw_rollback_mode_e610, 4002 .get_nvm_ver = ixgbe_get_active_nvm_ver, 4003 .get_link_capabilities = ixgbe_get_link_capabilities_e610, 4004 .get_bus_info = ixgbe_get_bus_info_generic, 4005 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540, 4006 .release_swfw_sync = ixgbe_release_swfw_sync_X540, 4007 .init_swfw_sync = ixgbe_init_swfw_sync_X540, 4008 .prot_autoc_read = prot_autoc_read_generic, 4009 .prot_autoc_write = prot_autoc_write_generic, 4010 .setup_fc = ixgbe_setup_fc_e610, 4011 .fc_autoneg = ixgbe_fc_autoneg_e610, 4012 .enable_mdd = ixgbe_enable_mdd_x550, 4013 .disable_mdd = ixgbe_disable_mdd_x550, 4014 .restore_mdd_vf = ixgbe_restore_mdd_vf_x550, 4015 .handle_mdd = ixgbe_handle_mdd_x550, 4016}; 4017 4018static const struct ixgbe_phy_operations phy_ops_e610 = { 4019 .init = ixgbe_init_phy_ops_e610, 4020 .identify = ixgbe_identify_phy_e610, 4021 .identify_sfp = ixgbe_identify_module_e610, 4022 .setup_link_speed = ixgbe_setup_phy_link_speed_generic, 4023 .setup_link = ixgbe_setup_phy_link_e610, 4024 .enter_lplu = ixgbe_enter_lplu_e610, 4025}; 4026 4027static const struct ixgbe_eeprom_operations eeprom_ops_e610 = { 4028 .read = ixgbe_read_ee_aci_e610, 4029 .read_buffer = ixgbe_read_ee_aci_buffer_e610, 4030 .validate_checksum = ixgbe_validate_eeprom_checksum_e610, 4031 .read_pba_string = ixgbe_read_pba_string_e610, 4032 .init_params = ixgbe_init_eeprom_params_e610, 4033}; 4034 4035const struct ixgbe_info ixgbe_e610_info = { 4036 .mac = ixgbe_mac_e610, 4037 .get_invariants = ixgbe_get_invariants_X540, 4038 .mac_ops = &mac_ops_e610, 4039 .eeprom_ops = &eeprom_ops_e610, 4040 .phy_ops = &phy_ops_e610, 4041 .mbx_ops = &mbx_ops_generic, 4042 .mvals = ixgbe_mvals_x550em_a, 4043};
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