igc.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c)  2018 Intel Corporation */
  3
  4#ifndef _IGC_H_
  5#define _IGC_H_
  6
  7#include <linux/kobject.h>
  8#include <linux/pci.h>
  9#include <linux/netdevice.h>
 10#include <linux/vmalloc.h>
 11#include <linux/ethtool.h>
 12#include <linux/sctp.h>
 13#include <linux/ptp_clock_kernel.h>
 14#include <linux/timecounter.h>
 15#include <linux/net_tstamp.h>
 16#include <linux/bitfield.h>
 17#include <linux/hrtimer.h>
 18#include <net/xdp.h>
 19
 20#include "igc_hw.h"
 21
 22void igc_ethtool_set_ops(struct net_device *);
 23
 24/* Transmit and receive queues */
 25#define IGC_MAX_RX_QUEUES		4
 26#define IGC_MAX_TX_QUEUES		4
 27
 28#define MAX_Q_VECTORS			8
 29#define MAX_STD_JUMBO_FRAME_SIZE	9216
 30
 31#define MAX_ETYPE_FILTER		8
 32#define IGC_RETA_SIZE			128
 33
 34/* SDP support */
 35#define IGC_N_EXTTS	2
 36#define IGC_N_PEROUT	2
 37#define IGC_N_SDP	4
 38
 39#define MAX_FLEX_FILTER			32
 40
 41#define IGC_MAX_TX_TSTAMP_REGS		4
 42
 43struct igc_fpe_t {
 44	struct ethtool_mmsv mmsv;
 45	u32 tx_min_frag_size;
 46	bool tx_enabled;
 47};
 48
 49enum igc_mac_filter_type {
 50	IGC_MAC_FILTER_TYPE_DST = 0,
 51	IGC_MAC_FILTER_TYPE_SRC
 52};
 53
 54struct igc_tx_queue_stats {
 55	u64 packets;
 56	u64 bytes;
 57	u64 restart_queue;
 58	u64 restart_queue2;
 59};
 60
 61struct igc_rx_queue_stats {
 62	u64 packets;
 63	u64 bytes;
 64	u64 drops;
 65	u64 csum_err;
 66	u64 alloc_failed;
 67};
 68
 69struct igc_rx_packet_stats {
 70	u64 ipv4_packets;      /* IPv4 headers processed */
 71	u64 ipv4e_packets;     /* IPv4E headers with extensions processed */
 72	u64 ipv6_packets;      /* IPv6 headers processed */
 73	u64 ipv6e_packets;     /* IPv6E headers with extensions processed */
 74	u64 tcp_packets;       /* TCP headers processed */
 75	u64 udp_packets;       /* UDP headers processed */
 76	u64 sctp_packets;      /* SCTP headers processed */
 77	u64 nfs_packets;       /* NFS headers processe */
 78	u64 other_packets;
 79};
 80
 81enum igc_tx_buffer_type {
 82	IGC_TX_BUFFER_TYPE_SKB,
 83	IGC_TX_BUFFER_TYPE_XDP,
 84	IGC_TX_BUFFER_TYPE_XSK,
 85};
 86
 87/* wrapper around a pointer to a socket buffer,
 88 * so a DMA handle can be stored along with the buffer
 89 */
 90struct igc_tx_buffer {
 91	union igc_adv_tx_desc *next_to_watch;
 92	unsigned long time_stamp;
 93	enum igc_tx_buffer_type type;
 94	union {
 95		struct sk_buff *skb;
 96		struct xdp_frame *xdpf;
 97	};
 98	unsigned int bytecount;
 99	u16 gso_segs;
100	__be16 protocol;
101
102	DEFINE_DMA_UNMAP_ADDR(dma);
103	DEFINE_DMA_UNMAP_LEN(len);
104	u32 tx_flags;
105	bool xsk_pending_ts;
106};
107
108struct igc_tx_timestamp_request {
109	union {                /* reference to the packet being timestamped */
110		struct sk_buff *skb;
111		struct igc_tx_buffer *xsk_tx_buffer;
112	};
113	enum igc_tx_buffer_type buffer_type;
114	unsigned long start;   /* when the tstamp request started (jiffies) */
115	u32 mask;              /* _TSYNCTXCTL_TXTT_{X} bit for this request */
116	u32 regl;              /* which TXSTMPL_{X} register should be used */
117	u32 regh;              /* which TXSTMPH_{X} register should be used */
118	u32 flags;             /* flags that should be added to the tx_buffer */
119	u8 xsk_queue_index;    /* Tx queue which requesting timestamp */
120	struct xsk_tx_metadata_compl xsk_meta;	/* ref to xsk Tx metadata */
121};
122
123struct igc_inline_rx_tstamps {
124	/* Timestamps are saved in little endian at the beginning of the packet
125	 * buffer following the layout:
126	 *
127	 * DWORD: | 0              | 1              | 2              | 3              |
128	 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
129	 *
130	 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
131	 * part of the timestamp.
132	 *
133	 */
134	__le32 timer1[2];
135	__le32 timer0[2];
136};
137
138struct igc_ring_container {
139	struct igc_ring *ring;          /* pointer to linked list of rings */
140	unsigned int total_bytes;       /* total bytes processed this int */
141	unsigned int total_packets;     /* total packets processed this int */
142	u16 work_limit;                 /* total work allowed per interrupt */
143	u8 count;                       /* total number of rings in vector */
144	u8 itr;                         /* current ITR setting for ring */
145};
146
147struct igc_ring {
148	struct igc_q_vector *q_vector;  /* backlink to q_vector */
149	struct net_device *netdev;      /* back pointer to net_device */
150	struct device *dev;             /* device for dma mapping */
151	union {                         /* array of buffer info structs */
152		struct igc_tx_buffer *tx_buffer_info;
153		struct igc_rx_buffer *rx_buffer_info;
154	};
155	void *desc;                     /* descriptor ring memory */
156	unsigned long flags;            /* ring specific flags */
157	void __iomem *tail;             /* pointer to ring tail register */
158	dma_addr_t dma;                 /* phys address of the ring */
159	unsigned int size;              /* length of desc. ring in bytes */
160
161	u16 count;                      /* number of desc. in the ring */
162	u8 queue_index;                 /* logical index of the ring*/
163	u8 reg_idx;                     /* physical index of the ring */
164	bool launchtime_enable;         /* true if LaunchTime is enabled */
165	ktime_t last_tx_cycle;          /* end of the cycle with a launchtime transmission */
166	ktime_t last_ff_cycle;          /* Last cycle with an active first flag */
167	bool preemptible;		/* True if preemptible queue, false if express queue */
168
169	u32 start_time;
170	u32 end_time;
171	u32 max_sdu;
172	bool oper_gate_closed;		/* Operating gate. True if the TX Queue is closed */
173	bool admin_gate_closed;		/* Future gate. True if the TX Queue will be closed */
174
175	/* CBS parameters */
176	bool cbs_enable;                /* indicates if CBS is enabled */
177	s32 idleslope;                  /* idleSlope in kbps */
178	s32 sendslope;                  /* sendSlope in kbps */
179	s32 hicredit;                   /* hiCredit in bytes */
180	s32 locredit;                   /* loCredit in bytes */
181
182	/* everything past this point are written often */
183	u16 next_to_clean;
184	u16 next_to_use;
185	u16 next_to_alloc;
186
187	union {
188		/* TX */
189		struct {
190			struct igc_tx_queue_stats tx_stats;
191			struct u64_stats_sync tx_syncp;
192			struct u64_stats_sync tx_syncp2;
193		};
194		/* RX */
195		struct {
196			struct igc_rx_queue_stats rx_stats;
197			struct igc_rx_packet_stats pkt_stats;
198			struct u64_stats_sync rx_syncp;
199			struct sk_buff *skb;
200		};
201	};
202
203	struct xdp_rxq_info xdp_rxq;
204	struct xsk_buff_pool *xsk_pool;
205} ____cacheline_internodealigned_in_smp;
206
207/* Board specific private data structure */
208struct igc_adapter {
209	struct net_device *netdev;
210
211	struct ethtool_keee eee;
212
213	unsigned long state;
214	unsigned int flags;
215	unsigned int num_q_vectors;
216
217	struct msix_entry *msix_entries;
218
219	/* TX */
220	u16 tx_work_limit;
221	u32 tx_timeout_count;
222	int num_tx_queues;
223	struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
224
225	/* RX */
226	int num_rx_queues;
227	struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
228
229	struct timer_list watchdog_timer;
230	struct timer_list dma_err_timer;
231	struct timer_list phy_info_timer;
232	struct hrtimer hrtimer;
233
234	u32 wol;
235	u32 en_mng_pt;
236	u16 link_speed;
237	u16 link_duplex;
238
239	u8 port_num;
240
241	u8 __iomem *io_addr;
242	/* Interrupt Throttle Rate */
243	u32 rx_itr_setting;
244	u32 tx_itr_setting;
245
246	struct work_struct reset_task;
247	struct work_struct watchdog_task;
248	struct work_struct dma_err_task;
249	bool fc_autoneg;
250
251	u8 tx_timeout_factor;
252
253	int msg_enable;
254	u32 max_frame_size;
255	u32 min_frame_size;
256
257	int tc_setup_type;
258	ktime_t base_time;
259	ktime_t cycle_time;
260	bool taprio_offload_enable;
261	u32 qbv_config_change_errors;
262	bool qbv_transition;
263	unsigned int qbv_count;
264	/* Access to oper_gate_closed, admin_gate_closed and qbv_transition
265	 * are protected by the qbv_tx_lock.
266	 */
267	spinlock_t qbv_tx_lock;
268
269	bool strict_priority_enable;
270	u8 num_tc;
271	u16 queue_per_tc[IGC_MAX_TX_QUEUES];
272
273	/* OS defined structs */
274	struct pci_dev *pdev;
275	/* lock for statistics */
276	spinlock_t stats64_lock;
277	struct rtnl_link_stats64 stats64;
278
279	/* structs defined in igc_hw.h */
280	struct igc_hw hw;
281	struct igc_hw_stats stats;
282
283	struct igc_q_vector *q_vector[MAX_Q_VECTORS];
284	u32 eims_enable_mask;
285	u32 eims_other;
286
287	u16 tx_ring_count;
288	u16 rx_ring_count;
289
290	u32 tx_hwtstamp_timeouts;
291	u32 tx_hwtstamp_skipped;
292	u32 rx_hwtstamp_cleared;
293
294	u32 rss_queues;
295	u32 rss_indir_tbl_init;
296
297	/* Any access to elements in nfc_rule_list is protected by the
298	 * nfc_rule_lock.
299	 */
300	struct mutex nfc_rule_lock;
301	struct list_head nfc_rule_list;
302	unsigned int nfc_rule_count;
303
304	u8 rss_indir_tbl[IGC_RETA_SIZE];
305
306	unsigned long link_check_timeout;
307	struct igc_info ei;
308
309	u32 test_icr;
310
311	struct ptp_clock *ptp_clock;
312	struct ptp_clock_info ptp_caps;
313	/* Access to ptp_tx_skb and ptp_tx_start are protected by the
314	 * ptp_tx_lock.
315	 */
316	spinlock_t ptp_tx_lock;
317	struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS];
318	struct kernel_hwtstamp_config tstamp_config;
319	unsigned int ptp_flags;
320	/* System time value lock */
321	spinlock_t tmreg_lock;
322	/* Free-running timer lock */
323	spinlock_t free_timer_lock;
324	struct cyclecounter cc;
325	struct timecounter tc;
326	struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
327	ktime_t ptp_reset_start; /* Reset time in clock mono */
328	struct system_time_snapshot snapshot;
329	struct mutex ptm_lock; /* Only allow one PTM transaction at a time */
330
331	char fw_version[32];
332
333	struct bpf_prog *xdp_prog;
334
335	bool pps_sys_wrap_on;
336
337	struct ptp_pin_desc sdp_config[IGC_N_SDP];
338	struct {
339		struct timespec64 start;
340		struct timespec64 period;
341	} perout[IGC_N_PEROUT];
342
343	struct igc_fpe_t fpe;
344
345	/* LEDs */
346	struct mutex led_mutex;
347	struct igc_led_classdev *leds;
348	bool leds_available;
349};
350
351void igc_up(struct igc_adapter *adapter);
352void igc_down(struct igc_adapter *adapter);
353int igc_open(struct net_device *netdev);
354int igc_close(struct net_device *netdev);
355int igc_setup_tx_resources(struct igc_ring *ring);
356int igc_setup_rx_resources(struct igc_ring *ring);
357void igc_free_tx_resources(struct igc_ring *ring);
358void igc_free_rx_resources(struct igc_ring *ring);
359unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
360void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
361			      const u32 max_rss_queues);
362int igc_reinit_queues(struct igc_adapter *adapter);
363void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
364bool igc_has_link(struct igc_adapter *adapter);
365void igc_reset(struct igc_adapter *adapter);
366void igc_update_stats(struct igc_adapter *adapter);
367void igc_disable_rx_ring(struct igc_ring *ring);
368void igc_enable_rx_ring(struct igc_ring *ring);
369void igc_disable_tx_ring(struct igc_ring *ring);
370void igc_enable_tx_ring(struct igc_ring *ring);
371int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
372
373/* AF_XDP TX metadata operations */
374extern const struct xsk_tx_metadata_ops igc_xsk_tx_metadata_ops;
375
376/* igc_dump declarations */
377void igc_rings_dump(struct igc_adapter *adapter);
378void igc_regs_dump(struct igc_adapter *adapter);
379
380extern char igc_driver_name[];
381
382#define IGC_REGS_LEN			740
383
384/* flags controlling PTP/1588 function */
385#define IGC_PTP_ENABLED		BIT(0)
386
387/* Flags definitions */
388#define IGC_FLAG_HAS_MSI		BIT(0)
389#define IGC_FLAG_QUEUE_PAIRS		BIT(3)
390#define IGC_FLAG_DMAC			BIT(4)
391#define IGC_FLAG_PTP			BIT(8)
392#define IGC_FLAG_WOL_SUPPORTED		BIT(8)
393#define IGC_FLAG_NEED_LINK_UPDATE	BIT(9)
394#define IGC_FLAG_HAS_MSIX		BIT(13)
395#define IGC_FLAG_EEE			BIT(14)
396#define IGC_FLAG_VLAN_PROMISC		BIT(15)
397#define IGC_FLAG_RX_LEGACY		BIT(16)
398#define IGC_FLAG_TSN_QBV_ENABLED	BIT(17)
399#define IGC_FLAG_TSN_QAV_ENABLED	BIT(18)
400#define IGC_FLAG_TSN_PREEMPT_ENABLED	BIT(19)
401#define IGC_FLAG_TSN_REVERSE_TXQ_PRIO	BIT(20)
402
403#define IGC_FLAG_TSN_ANY_ENABLED				\
404	(IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED |	\
405	 IGC_FLAG_TSN_PREEMPT_ENABLED)
406
407#define IGC_FLAG_RSS_FIELD_IPV4_UDP	BIT(6)
408#define IGC_FLAG_RSS_FIELD_IPV6_UDP	BIT(7)
409
410/* RX-desc Write-Back format RSS Type's */
411enum igc_rss_type_num {
412	IGC_RSS_TYPE_NO_HASH		= 0,
413	IGC_RSS_TYPE_HASH_TCP_IPV4	= 1,
414	IGC_RSS_TYPE_HASH_IPV4		= 2,
415	IGC_RSS_TYPE_HASH_TCP_IPV6	= 3,
416	IGC_RSS_TYPE_HASH_IPV6_EX	= 4,
417	IGC_RSS_TYPE_HASH_IPV6		= 5,
418	IGC_RSS_TYPE_HASH_TCP_IPV6_EX	= 6,
419	IGC_RSS_TYPE_HASH_UDP_IPV4	= 7,
420	IGC_RSS_TYPE_HASH_UDP_IPV6	= 8,
421	IGC_RSS_TYPE_HASH_UDP_IPV6_EX	= 9,
422	IGC_RSS_TYPE_MAX		= 10,
423};
424#define IGC_RSS_TYPE_MAX_TABLE		16
425#define IGC_RSS_TYPE_MASK		GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */
426
427/* igc_rss_type - Rx descriptor RSS type field */
428static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
429{
430	/* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved)
431	 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info)
432	 * is slightly slower than via u32 (wb.lower.lo_dword.data)
433	 */
434	return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK);
435}
436
437/* Interrupt defines */
438#define IGC_START_ITR			648 /* ~6000 ints/sec */
439#define IGC_4K_ITR			980
440#define IGC_20K_ITR			196
441#define IGC_70K_ITR			56
442
443#define IGC_DEFAULT_ITR		3 /* dynamic */
444#define IGC_MAX_ITR_USECS	10000
445#define IGC_MIN_ITR_USECS	10
446#define NON_Q_VECTORS		1
447#define MAX_MSIX_ENTRIES	10
448
449/* TX/RX descriptor defines */
450#define IGC_DEFAULT_TXD		256
451#define IGC_DEFAULT_TX_WORK	128
452#define IGC_MIN_TXD		64
453#define IGC_MAX_TXD		4096
454
455#define IGC_DEFAULT_RXD		256
456#define IGC_MIN_RXD		64
457#define IGC_MAX_RXD		4096
458
459/* Supported Rx Buffer Sizes */
460#define IGC_RXBUFFER_256		256
461#define IGC_RXBUFFER_2048		2048
462#define IGC_RXBUFFER_3072		3072
463
464#define AUTO_ALL_MODES		0
465#define IGC_RX_HDR_LEN			IGC_RXBUFFER_256
466
467/* Transmit and receive latency (for PTP timestamps) */
468#define IGC_I225_TX_LATENCY_10		240
469#define IGC_I225_TX_LATENCY_100		58
470#define IGC_I225_TX_LATENCY_1000	80
471#define IGC_I225_TX_LATENCY_2500	1325
472#define IGC_I225_RX_LATENCY_10		6450
473#define IGC_I225_RX_LATENCY_100		185
474#define IGC_I225_RX_LATENCY_1000	300
475#define IGC_I225_RX_LATENCY_2500	1485
476
477/* RX and TX descriptor control thresholds.
478 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
479 *           descriptors available in its onboard memory.
480 *           Setting this to 0 disables RX descriptor prefetch.
481 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
482 *           available in host memory.
483 *           If PTHRESH is 0, this should also be 0.
484 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
485 *           descriptors until either it has this many to write back, or the
486 *           ITR timer expires.
487 */
488#define IGC_RXDCTL_PTHRESH		8
489#define IGC_RXDCTL_HTHRESH		8
490#define IGC_RXDCTL_WTHRESH		4
491/* Ena specific Rx Queue */
492#define IGC_RXDCTL_QUEUE_ENABLE		0x02000000
493/* Receive Software Flush */
494#define IGC_RXDCTL_SWFLUSH		0x04000000
495
496#define IGC_TXDCTL_PTHRESH_MASK		GENMASK(4, 0)
497#define IGC_TXDCTL_HTHRESH_MASK		GENMASK(12, 8)
498#define IGC_TXDCTL_WTHRESH_MASK		GENMASK(20, 16)
499#define IGC_TXDCTL_QUEUE_ENABLE_MASK	GENMASK(25, 25)
500#define IGC_TXDCTL_SWFLUSH_MASK		GENMASK(26, 26)
501#define IGC_TXDCTL_PRIORITY_MASK	GENMASK(27, 27)
502
503#define IGC_TXDCTL_PTHRESH(x)		FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x))
504#define IGC_TXDCTL_HTHRESH(x)		FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x))
505#define IGC_TXDCTL_WTHRESH(x)		FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x))
506/* Ena specific Tx Queue */
507#define IGC_TXDCTL_QUEUE_ENABLE		FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, 1)
508/* Transmit Software Flush */
509#define IGC_TXDCTL_SWFLUSH		FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1)
510#define IGC_TXDCTL_PRIORITY(x)		FIELD_PREP(IGC_TXDCTL_PRIORITY_MASK, (x))
511#define IGC_TXDCTL_PRIORITY_HIGH	IGC_TXDCTL_PRIORITY(1)
512
513#define IGC_RX_DMA_ATTR \
514	(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
515
516#define IGC_TS_HDR_LEN			16
517
518#define IGC_SKB_PAD			(NET_SKB_PAD + NET_IP_ALIGN)
519
520#if (PAGE_SIZE < 8192)
521#define IGC_MAX_FRAME_BUILD_SKB \
522	(SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
523#else
524#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
525#endif
526
527/* How many Rx Buffers do we bundle into one write to the hardware ? */
528#define IGC_RX_BUFFER_WRITE	16 /* Must be power of 2 */
529
530/* VLAN info */
531#define IGC_TX_FLAGS_VLAN_MASK	0xffff0000
532#define IGC_TX_FLAGS_VLAN_SHIFT	16
533
534/* igc_test_staterr - tests bits within Rx descriptor status and error fields */
535static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
536				      const u32 stat_err_bits)
537{
538	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
539}
540
541enum igc_state_t {
542	__IGC_TESTING,
543	__IGC_RESETTING,
544	__IGC_DOWN,
545};
546
547enum igc_tx_flags {
548	/* cmd_type flags */
549	IGC_TX_FLAGS_VLAN	= 0x01,
550	IGC_TX_FLAGS_TSO	= 0x02,
551	IGC_TX_FLAGS_TSTAMP	= 0x04,
552
553	/* olinfo flags */
554	IGC_TX_FLAGS_IPV4	= 0x10,
555	IGC_TX_FLAGS_CSUM	= 0x20,
556
557	IGC_TX_FLAGS_TSTAMP_1	= 0x100,
558	IGC_TX_FLAGS_TSTAMP_2	= 0x200,
559	IGC_TX_FLAGS_TSTAMP_3	= 0x400,
560
561	IGC_TX_FLAGS_TSTAMP_TIMER_1 = 0x800,
562};
563
564enum igc_boards {
565	board_base,
566};
567
568/* The largest size we can write to the descriptor is 65535.  In order to
569 * maintain a power of two alignment we have to limit ourselves to 32K.
570 */
571#define IGC_MAX_TXD_PWR		15
572#define IGC_MAX_DATA_PER_TXD	BIT(IGC_MAX_TXD_PWR)
573
574/* Tx Descriptors needed, worst case */
575#define TXD_USE_COUNT(S)	DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
576#define DESC_NEEDED	(MAX_SKB_FRAGS + 4)
577
578struct igc_rx_buffer {
579	union {
580		struct {
581			dma_addr_t dma;
582			struct page *page;
583#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
584			__u32 page_offset;
585#else
586			__u16 page_offset;
587#endif
588			__u16 pagecnt_bias;
589		};
590		struct xdp_buff *xdp;
591	};
592};
593
594/* context wrapper around xdp_buff to provide access to descriptor metadata */
595struct igc_xdp_buff {
596	struct xdp_buff xdp;
597	union igc_adv_rx_desc *rx_desc;
598	struct igc_inline_rx_tstamps *rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */
599};
600
601struct igc_metadata_request {
602	struct igc_tx_buffer *tx_buffer;
603	struct xsk_tx_metadata *meta;
604	struct igc_ring *tx_ring;
605	u32 cmd_type;
606	u16 used_desc;
607};
608
609struct igc_q_vector {
610	struct igc_adapter *adapter;    /* backlink */
611	void __iomem *itr_register;
612	u32 eims_value;                 /* EIMS mask value */
613
614	u16 itr_val;
615	u8 set_itr;
616
617	struct igc_ring_container rx, tx;
618
619	struct napi_struct napi;
620
621	struct rcu_head rcu;    /* to avoid race with update stats on free */
622	char name[IFNAMSIZ + 9];
623
624	/* for dynamic allocation of rings associated with this q_vector */
625	struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
626};
627
628enum igc_filter_match_flags {
629	IGC_FILTER_FLAG_ETHER_TYPE =	BIT(0),
630	IGC_FILTER_FLAG_VLAN_TCI   =	BIT(1),
631	IGC_FILTER_FLAG_SRC_MAC_ADDR =	BIT(2),
632	IGC_FILTER_FLAG_DST_MAC_ADDR =	BIT(3),
633	IGC_FILTER_FLAG_USER_DATA =	BIT(4),
634	IGC_FILTER_FLAG_VLAN_ETYPE =	BIT(5),
635	IGC_FILTER_FLAG_DEFAULT_QUEUE = BIT(6),
636};
637
638struct igc_nfc_filter {
639	u8 match_flags;
640	u16 etype;
641	u16 vlan_etype;
642	u16 vlan_tci;
643	u16 vlan_tci_mask;
644	u8 src_addr[ETH_ALEN];
645	u8 dst_addr[ETH_ALEN];
646	u8 user_data[8];
647	u8 user_mask[8];
648	u8 flex_index;
649	u8 rx_queue;
650	u8 prio;
651	u8 immediate_irq;
652	u8 drop;
653};
654
655struct igc_nfc_rule {
656	struct list_head list;
657	struct igc_nfc_filter filter;
658	u32 location;
659	u16 action;
660	bool flex;
661};
662
663/* IGC supports a total of 65 NFC rules, listed below in order of priority:
664 *  - 16 MAC address based filtering rules (highest priority)
665 *  - 8 ethertype based filtering rules
666 *  - 32 Flex filter based filtering rules
667 *  - 8 VLAN priority based filtering rules
668 *  - 1 default queue rule (lowest priority)
669 */
670#define IGC_MAX_RXNFC_RULES		65
671
672struct igc_flex_filter {
673	u8 index;
674	u8 data[128];
675	u8 mask[16];
676	u8 length;
677	u8 rx_queue;
678	u8 prio;
679	u8 immediate_irq;
680	u8 drop;
681};
682
683/* igc_desc_unused - calculate if we have unused descriptors */
684static inline u16 igc_desc_unused(const struct igc_ring *ring)
685{
686	u16 ntc = ring->next_to_clean;
687	u16 ntu = ring->next_to_use;
688
689	return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
690}
691
692static inline s32 igc_get_phy_info(struct igc_hw *hw)
693{
694	if (hw->phy.ops.get_phy_info)
695		return hw->phy.ops.get_phy_info(hw);
696
697	return 0;
698}
699
700static inline s32 igc_reset_phy(struct igc_hw *hw)
701{
702	if (hw->phy.ops.reset)
703		return hw->phy.ops.reset(hw);
704
705	return 0;
706}
707
708static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
709{
710	return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
711}
712
713enum igc_ring_flags_t {
714	IGC_RING_FLAG_RX_3K_BUFFER,
715	IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
716	IGC_RING_FLAG_RX_SCTP_CSUM,
717	IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
718	IGC_RING_FLAG_TX_CTX_IDX,
719	IGC_RING_FLAG_TX_DETECT_HANG,
720	IGC_RING_FLAG_AF_XDP_ZC,
721	IGC_RING_FLAG_TX_HWTSTAMP,
722	IGC_RING_FLAG_RX_ALLOC_FAILED,
723};
724
725#define ring_uses_large_buffer(ring) \
726	test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
727#define set_ring_uses_large_buffer(ring) \
728	set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
729#define clear_ring_uses_large_buffer(ring) \
730	clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
731
732#define ring_uses_build_skb(ring) \
733	test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
734
735static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
736{
737#if (PAGE_SIZE < 8192)
738	if (ring_uses_large_buffer(ring))
739		return IGC_RXBUFFER_3072;
740
741	if (ring_uses_build_skb(ring))
742		return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
743#endif
744	return IGC_RXBUFFER_2048;
745}
746
747static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
748{
749#if (PAGE_SIZE < 8192)
750	if (ring_uses_large_buffer(ring))
751		return 1;
752#endif
753	return 0;
754}
755
756static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
757{
758	if (hw->phy.ops.read_reg)
759		return hw->phy.ops.read_reg(hw, offset, data);
760
761	return -EOPNOTSUPP;
762}
763
764void igc_reinit_locked(struct igc_adapter *);
765struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
766				      u32 location);
767int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
768void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
769void igc_disable_empty_addr_recv(struct igc_adapter *adapter);
770int igc_enable_empty_addr_recv(struct igc_adapter *adapter);
771struct igc_ring *igc_get_tx_ring(struct igc_adapter *adapter, int cpu);
772void igc_flush_tx_descriptors(struct igc_ring *ring);
773void igc_ptp_init(struct igc_adapter *adapter);
774void igc_ptp_reset(struct igc_adapter *adapter);
775void igc_ptp_suspend(struct igc_adapter *adapter);
776void igc_ptp_stop(struct igc_adapter *adapter);
777ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
778int igc_ptp_hwtstamp_get(struct net_device *netdev,
779			 struct kernel_hwtstamp_config *config);
780int igc_ptp_hwtstamp_set(struct net_device *netdev,
781			 struct kernel_hwtstamp_config *config,
782			 struct netlink_ext_ack *extack);
783void igc_ptp_tx_hang(struct igc_adapter *adapter);
784void igc_ptp_clear_xsk_tx_tstamp_queue(struct igc_adapter *adapter,
785				       u16 queue_id);
786void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
787void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter);
788
789int igc_led_setup(struct igc_adapter *adapter);
790void igc_led_free(struct igc_adapter *adapter);
791
792#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
793
794#define IGC_TXD_DCMD	(IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
795
796#define IGC_RX_DESC(R, i)       \
797	(&(((union igc_adv_rx_desc *)((R)->desc))[i]))
798#define IGC_TX_DESC(R, i)       \
799	(&(((union igc_adv_tx_desc *)((R)->desc))[i]))
800#define IGC_TX_CTXTDESC(R, i)   \
801	(&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
802
803#endif /* _IGC_H_ */