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igb_main.c
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linux-6.19.14/drivers/net/ethernet/intel/igb/igb_main.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6#include <linux/module.h> 7#include <linux/types.h> 8#include <linux/init.h> 9#include <linux/bitops.h> 10#include <linux/vmalloc.h> 11#include <linux/pagemap.h> 12#include <linux/netdevice.h> 13#include <linux/ipv6.h> 14#include <linux/slab.h> 15#include <net/checksum.h> 16#include <net/ip6_checksum.h> 17#include <net/pkt_sched.h> 18#include <net/pkt_cls.h> 19#include <linux/net_tstamp.h> 20#include <linux/mii.h> 21#include <linux/ethtool.h> 22#include <linux/if.h> 23#include <linux/if_vlan.h> 24#include <linux/pci.h> 25#include <linux/delay.h> 26#include <linux/interrupt.h> 27#include <linux/ip.h> 28#include <linux/tcp.h> 29#include <linux/sctp.h> 30#include <linux/if_ether.h> 31#include <linux/prefetch.h> 32#include <linux/bpf.h> 33#include <linux/bpf_trace.h> 34#include <linux/pm_runtime.h> 35#include <linux/etherdevice.h> 36#ifdef CONFIG_IGB_DCA 37#include <linux/dca.h> 38#endif 39#include <linux/i2c.h> 40#include "igb.h" 41 42enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45}; 46 47enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50}; 51 52char igb_driver_name[] = "igb"; 53static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60}; 61 62static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100}; 101 102MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104static int igb_setup_all_tx_resources(struct igb_adapter *); 105static int igb_setup_all_rx_resources(struct igb_adapter *); 106static void igb_free_all_tx_resources(struct igb_adapter *); 107static void igb_free_all_rx_resources(struct igb_adapter *); 108static void igb_setup_mrqc(struct igb_adapter *); 109static void igb_init_queue_configuration(struct igb_adapter *adapter); 110static int igb_sw_init(struct igb_adapter *); 111int igb_open(struct net_device *); 112int igb_close(struct net_device *); 113static void igb_configure(struct igb_adapter *); 114static void igb_configure_tx(struct igb_adapter *); 115static void igb_configure_rx(struct igb_adapter *); 116static void igb_clean_all_tx_rings(struct igb_adapter *); 117static void igb_clean_all_rx_rings(struct igb_adapter *); 118static void igb_set_rx_mode(struct net_device *); 119static void igb_update_phy_info(struct timer_list *); 120static void igb_watchdog(struct timer_list *); 121static void igb_watchdog_task(struct work_struct *); 122static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 123static void igb_get_stats64(struct net_device *dev, 124 struct rtnl_link_stats64 *stats); 125static int igb_change_mtu(struct net_device *, int); 126static int igb_set_mac(struct net_device *, void *); 127static void igb_set_uta(struct igb_adapter *adapter, bool set); 128static irqreturn_t igb_intr(int irq, void *); 129static irqreturn_t igb_intr_msi(int irq, void *); 130static irqreturn_t igb_msix_other(int irq, void *); 131static irqreturn_t igb_msix_ring(int irq, void *); 132#ifdef CONFIG_IGB_DCA 133static void igb_update_dca(struct igb_q_vector *); 134static void igb_setup_dca(struct igb_adapter *); 135#endif /* CONFIG_IGB_DCA */ 136static int igb_poll(struct napi_struct *, int); 137static bool igb_clean_tx_irq(struct igb_q_vector *, int); 138static int igb_clean_rx_irq(struct igb_q_vector *, int); 139static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 140static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 141static void igb_reset_task(struct work_struct *); 142static void igb_vlan_mode(struct net_device *netdev, 143 netdev_features_t features); 144static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 145static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 146static void igb_restore_vlan(struct igb_adapter *); 147static void igb_rar_set_index(struct igb_adapter *, u32); 148static void igb_ping_all_vfs(struct igb_adapter *); 149static void igb_msg_task(struct igb_adapter *); 150static void igb_vmm_control(struct igb_adapter *); 151static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 152static void igb_flush_mac_table(struct igb_adapter *); 153static int igb_available_rars(struct igb_adapter *, u8); 154static void igb_set_default_mac_filter(struct igb_adapter *); 155static int igb_uc_sync(struct net_device *, const unsigned char *); 156static int igb_uc_unsync(struct net_device *, const unsigned char *); 157static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 158static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 159static int igb_ndo_set_vf_vlan(struct net_device *netdev, 160 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 161static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 162static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 163 bool setting); 164static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 165 bool setting); 166static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 167 struct ifla_vf_info *ivi); 168static void igb_check_vf_rate_limit(struct igb_adapter *); 169static void igb_nfc_filter_exit(struct igb_adapter *adapter); 170static void igb_nfc_filter_restore(struct igb_adapter *adapter); 171 172#ifdef CONFIG_PCI_IOV 173static int igb_vf_configure(struct igb_adapter *adapter, int vf); 174static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 175#endif 176 177#ifdef CONFIG_IGB_DCA 178static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 179static struct notifier_block dca_notifier = { 180 .notifier_call = igb_notify_dca, 181 .next = NULL, 182 .priority = 0 183}; 184#endif 185#ifdef CONFIG_PCI_IOV 186static unsigned int max_vfs; 187module_param(max_vfs, uint, 0444); 188MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 189#endif /* CONFIG_PCI_IOV */ 190 191static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 192 pci_channel_state_t); 193static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 194static void igb_io_resume(struct pci_dev *); 195 196static const struct pci_error_handlers igb_err_handler = { 197 .error_detected = igb_io_error_detected, 198 .slot_reset = igb_io_slot_reset, 199 .resume = igb_io_resume, 200}; 201 202static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 203 204MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 205MODULE_LICENSE("GPL v2"); 206 207#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 208static int debug = -1; 209module_param(debug, int, 0); 210MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 211 212struct igb_reg_info { 213 u32 ofs; 214 char *name; 215}; 216 217static const struct igb_reg_info igb_reg_info_tbl[] = { 218 219 /* General Registers */ 220 {E1000_CTRL, "CTRL"}, 221 {E1000_STATUS, "STATUS"}, 222 {E1000_CTRL_EXT, "CTRL_EXT"}, 223 224 /* Interrupt Registers */ 225 {E1000_ICR, "ICR"}, 226 227 /* RX Registers */ 228 {E1000_RCTL, "RCTL"}, 229 {E1000_RDLEN(0), "RDLEN"}, 230 {E1000_RDH(0), "RDH"}, 231 {E1000_RDT(0), "RDT"}, 232 {E1000_RXDCTL(0), "RXDCTL"}, 233 {E1000_RDBAL(0), "RDBAL"}, 234 {E1000_RDBAH(0), "RDBAH"}, 235 236 /* TX Registers */ 237 {E1000_TCTL, "TCTL"}, 238 {E1000_TDBAL(0), "TDBAL"}, 239 {E1000_TDBAH(0), "TDBAH"}, 240 {E1000_TDLEN(0), "TDLEN"}, 241 {E1000_TDH(0), "TDH"}, 242 {E1000_TDT(0), "TDT"}, 243 {E1000_TXDCTL(0), "TXDCTL"}, 244 {E1000_TDFH, "TDFH"}, 245 {E1000_TDFT, "TDFT"}, 246 {E1000_TDFHS, "TDFHS"}, 247 {E1000_TDFPC, "TDFPC"}, 248 249 /* List Terminator */ 250 {} 251}; 252 253/* igb_regdump - register printout routine */ 254static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 255{ 256 int n = 0; 257 char rname[16]; 258 u32 regs[8]; 259 260 switch (reginfo->ofs) { 261 case E1000_RDLEN(0): 262 for (n = 0; n < 4; n++) 263 regs[n] = rd32(E1000_RDLEN(n)); 264 break; 265 case E1000_RDH(0): 266 for (n = 0; n < 4; n++) 267 regs[n] = rd32(E1000_RDH(n)); 268 break; 269 case E1000_RDT(0): 270 for (n = 0; n < 4; n++) 271 regs[n] = rd32(E1000_RDT(n)); 272 break; 273 case E1000_RXDCTL(0): 274 for (n = 0; n < 4; n++) 275 regs[n] = rd32(E1000_RXDCTL(n)); 276 break; 277 case E1000_RDBAL(0): 278 for (n = 0; n < 4; n++) 279 regs[n] = rd32(E1000_RDBAL(n)); 280 break; 281 case E1000_RDBAH(0): 282 for (n = 0; n < 4; n++) 283 regs[n] = rd32(E1000_RDBAH(n)); 284 break; 285 case E1000_TDBAL(0): 286 for (n = 0; n < 4; n++) 287 regs[n] = rd32(E1000_TDBAL(n)); 288 break; 289 case E1000_TDBAH(0): 290 for (n = 0; n < 4; n++) 291 regs[n] = rd32(E1000_TDBAH(n)); 292 break; 293 case E1000_TDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_TDLEN(n)); 296 break; 297 case E1000_TDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_TDH(n)); 300 break; 301 case E1000_TDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_TDT(n)); 304 break; 305 case E1000_TXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_TXDCTL(n)); 308 break; 309 default: 310 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 311 return; 312 } 313 314 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 315 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 316 regs[2], regs[3]); 317} 318 319/* igb_dump - Print registers, Tx-rings and Rx-rings */ 320static void igb_dump(struct igb_adapter *adapter) 321{ 322 struct net_device *netdev = adapter->netdev; 323 struct e1000_hw *hw = &adapter->hw; 324 struct igb_reg_info *reginfo; 325 struct igb_ring *tx_ring; 326 union e1000_adv_tx_desc *tx_desc; 327 struct my_u0 { __le64 a; __le64 b; } *u0; 328 struct igb_ring *rx_ring; 329 union e1000_adv_rx_desc *rx_desc; 330 u32 staterr; 331 u16 i, n; 332 333 if (!netif_msg_hw(adapter)) 334 return; 335 336 /* Print netdevice Info */ 337 if (netdev) { 338 dev_info(&adapter->pdev->dev, "Net device Info\n"); 339 pr_info("Device Name state trans_start\n"); 340 pr_info("%-15s %016lX %016lX\n", netdev->name, 341 netdev->state, dev_trans_start(netdev)); 342 } 343 344 /* Print Registers */ 345 dev_info(&adapter->pdev->dev, "Register Dump\n"); 346 pr_info(" Register Name Value\n"); 347 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 348 reginfo->name; reginfo++) { 349 igb_regdump(hw, reginfo); 350 } 351 352 /* Print TX Ring Summary */ 353 if (!netdev || !netif_running(netdev)) 354 goto exit; 355 356 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 357 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 358 for (n = 0; n < adapter->num_tx_queues; n++) { 359 struct igb_tx_buffer *buffer_info; 360 tx_ring = adapter->tx_ring[n]; 361 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 362 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 363 n, tx_ring->next_to_use, tx_ring->next_to_clean, 364 (u64)dma_unmap_addr(buffer_info, dma), 365 dma_unmap_len(buffer_info, len), 366 buffer_info->next_to_watch, 367 (u64)buffer_info->time_stamp); 368 } 369 370 /* Print TX Rings */ 371 if (!netif_msg_tx_done(adapter)) 372 goto rx_ring_summary; 373 374 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 375 376 /* Transmit Descriptor Formats 377 * 378 * Advanced Transmit Descriptor 379 * +--------------------------------------------------------------+ 380 * 0 | Buffer Address [63:0] | 381 * +--------------------------------------------------------------+ 382 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 383 * +--------------------------------------------------------------+ 384 * 63 46 45 40 39 38 36 35 32 31 24 15 0 385 */ 386 387 for (n = 0; n < adapter->num_tx_queues; n++) { 388 tx_ring = adapter->tx_ring[n]; 389 pr_info("------------------------------------\n"); 390 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 391 pr_info("------------------------------------\n"); 392 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 393 394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 395 const char *next_desc; 396 struct igb_tx_buffer *buffer_info; 397 tx_desc = IGB_TX_DESC(tx_ring, i); 398 buffer_info = &tx_ring->tx_buffer_info[i]; 399 u0 = (struct my_u0 *)tx_desc; 400 if (i == tx_ring->next_to_use && 401 i == tx_ring->next_to_clean) 402 next_desc = " NTC/U"; 403 else if (i == tx_ring->next_to_use) 404 next_desc = " NTU"; 405 else if (i == tx_ring->next_to_clean) 406 next_desc = " NTC"; 407 else 408 next_desc = ""; 409 410 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 411 i, le64_to_cpu(u0->a), 412 le64_to_cpu(u0->b), 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp, 417 buffer_info->skb, next_desc); 418 419 if (netif_msg_pktdata(adapter) && buffer_info->skb) 420 print_hex_dump(KERN_INFO, "", 421 DUMP_PREFIX_ADDRESS, 422 16, 1, buffer_info->skb->data, 423 dma_unmap_len(buffer_info, len), 424 true); 425 } 426 } 427 428 /* Print RX Rings Summary */ 429rx_ring_summary: 430 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 431 pr_info("Queue [NTU] [NTC]\n"); 432 for (n = 0; n < adapter->num_rx_queues; n++) { 433 rx_ring = adapter->rx_ring[n]; 434 pr_info(" %5d %5X %5X\n", 435 n, rx_ring->next_to_use, rx_ring->next_to_clean); 436 } 437 438 /* Print RX Rings */ 439 if (!netif_msg_rx_status(adapter)) 440 goto exit; 441 442 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 443 444 /* Advanced Receive Descriptor (Read) Format 445 * 63 1 0 446 * +-----------------------------------------------------+ 447 * 0 | Packet Buffer Address [63:1] |A0/NSE| 448 * +----------------------------------------------+------+ 449 * 8 | Header Buffer Address [63:1] | DD | 450 * +-----------------------------------------------------+ 451 * 452 * 453 * Advanced Receive Descriptor (Write-Back) Format 454 * 455 * 63 48 47 32 31 30 21 20 17 16 4 3 0 456 * +------------------------------------------------------+ 457 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 458 * | Checksum Ident | | | | Type | Type | 459 * +------------------------------------------------------+ 460 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 461 * +------------------------------------------------------+ 462 * 63 48 47 32 31 20 19 0 463 */ 464 465 for (n = 0; n < adapter->num_rx_queues; n++) { 466 rx_ring = adapter->rx_ring[n]; 467 pr_info("------------------------------------\n"); 468 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 469 pr_info("------------------------------------\n"); 470 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 471 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 472 473 for (i = 0; i < rx_ring->count; i++) { 474 const char *next_desc; 475 dma_addr_t dma = (dma_addr_t)0; 476 struct igb_rx_buffer *buffer_info = NULL; 477 rx_desc = IGB_RX_DESC(rx_ring, i); 478 u0 = (struct my_u0 *)rx_desc; 479 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 480 481 if (!rx_ring->xsk_pool) { 482 buffer_info = &rx_ring->rx_buffer_info[i]; 483 dma = buffer_info->dma; 484 } 485 486 if (i == rx_ring->next_to_use) 487 next_desc = " NTU"; 488 else if (i == rx_ring->next_to_clean) 489 next_desc = " NTC"; 490 else 491 next_desc = ""; 492 493 if (staterr & E1000_RXD_STAT_DD) { 494 /* Descriptor Done */ 495 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 496 "RWB", i, 497 le64_to_cpu(u0->a), 498 le64_to_cpu(u0->b), 499 next_desc); 500 } else { 501 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 502 "R ", i, 503 le64_to_cpu(u0->a), 504 le64_to_cpu(u0->b), 505 (u64)dma, 506 next_desc); 507 508 if (netif_msg_pktdata(adapter) && 509 buffer_info && dma && buffer_info->page) { 510 print_hex_dump(KERN_INFO, "", 511 DUMP_PREFIX_ADDRESS, 512 16, 1, 513 page_address(buffer_info->page) + 514 buffer_info->page_offset, 515 igb_rx_bufsz(rx_ring), true); 516 } 517 } 518 } 519 } 520 521exit: 522 return; 523} 524 525/** 526 * igb_get_i2c_data - Reads the I2C SDA data bit 527 * @data: opaque pointer to adapter struct 528 * 529 * Returns the I2C data bit value 530 **/ 531static int igb_get_i2c_data(void *data) 532{ 533 struct igb_adapter *adapter = (struct igb_adapter *)data; 534 struct e1000_hw *hw = &adapter->hw; 535 s32 i2cctl = rd32(E1000_I2CPARAMS); 536 537 return !!(i2cctl & E1000_I2C_DATA_IN); 538} 539 540/** 541 * igb_set_i2c_data - Sets the I2C data bit 542 * @data: pointer to hardware structure 543 * @state: I2C data value (0 or 1) to set 544 * 545 * Sets the I2C data bit 546 **/ 547static void igb_set_i2c_data(void *data, int state) 548{ 549 struct igb_adapter *adapter = (struct igb_adapter *)data; 550 struct e1000_hw *hw = &adapter->hw; 551 s32 i2cctl = rd32(E1000_I2CPARAMS); 552 553 if (state) { 554 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 555 } else { 556 i2cctl &= ~E1000_I2C_DATA_OE_N; 557 i2cctl &= ~E1000_I2C_DATA_OUT; 558 } 559 560 wr32(E1000_I2CPARAMS, i2cctl); 561 wrfl(); 562} 563 564/** 565 * igb_set_i2c_clk - Sets the I2C SCL clock 566 * @data: pointer to hardware structure 567 * @state: state to set clock 568 * 569 * Sets the I2C clock line to state 570 **/ 571static void igb_set_i2c_clk(void *data, int state) 572{ 573 struct igb_adapter *adapter = (struct igb_adapter *)data; 574 struct e1000_hw *hw = &adapter->hw; 575 s32 i2cctl = rd32(E1000_I2CPARAMS); 576 577 if (state) { 578 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 579 } else { 580 i2cctl &= ~E1000_I2C_CLK_OUT; 581 i2cctl &= ~E1000_I2C_CLK_OE_N; 582 } 583 wr32(E1000_I2CPARAMS, i2cctl); 584 wrfl(); 585} 586 587/** 588 * igb_get_i2c_clk - Gets the I2C SCL clock state 589 * @data: pointer to hardware structure 590 * 591 * Gets the I2C clock state 592 **/ 593static int igb_get_i2c_clk(void *data) 594{ 595 struct igb_adapter *adapter = (struct igb_adapter *)data; 596 struct e1000_hw *hw = &adapter->hw; 597 s32 i2cctl = rd32(E1000_I2CPARAMS); 598 599 return !!(i2cctl & E1000_I2C_CLK_IN); 600} 601 602static const struct i2c_algo_bit_data igb_i2c_algo = { 603 .setsda = igb_set_i2c_data, 604 .setscl = igb_set_i2c_clk, 605 .getsda = igb_get_i2c_data, 606 .getscl = igb_get_i2c_clk, 607 .udelay = 5, 608 .timeout = 20, 609}; 610 611/** 612 * igb_get_hw_dev - return device 613 * @hw: pointer to hardware structure 614 * 615 * used by hardware layer to print debugging information 616 **/ 617struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 618{ 619 struct igb_adapter *adapter = hw->back; 620 return adapter->netdev; 621} 622 623static struct pci_driver igb_driver; 624 625/** 626 * igb_init_module - Driver Registration Routine 627 * 628 * igb_init_module is the first routine called when the driver is 629 * loaded. All it does is register with the PCI subsystem. 630 **/ 631static int __init igb_init_module(void) 632{ 633 int ret; 634 635 pr_info("%s\n", igb_driver_string); 636 pr_info("%s\n", igb_copyright); 637 638#ifdef CONFIG_IGB_DCA 639 dca_register_notify(&dca_notifier); 640#endif 641 ret = pci_register_driver(&igb_driver); 642#ifdef CONFIG_IGB_DCA 643 if (ret) 644 dca_unregister_notify(&dca_notifier); 645#endif 646 return ret; 647} 648 649module_init(igb_init_module); 650 651/** 652 * igb_exit_module - Driver Exit Cleanup Routine 653 * 654 * igb_exit_module is called just before the driver is removed 655 * from memory. 656 **/ 657static void __exit igb_exit_module(void) 658{ 659#ifdef CONFIG_IGB_DCA 660 dca_unregister_notify(&dca_notifier); 661#endif 662 pci_unregister_driver(&igb_driver); 663} 664 665module_exit(igb_exit_module); 666 667#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 668/** 669 * igb_cache_ring_register - Descriptor ring to register mapping 670 * @adapter: board private structure to initialize 671 * 672 * Once we know the feature-set enabled for the device, we'll cache 673 * the register offset the descriptor ring is assigned to. 674 **/ 675static void igb_cache_ring_register(struct igb_adapter *adapter) 676{ 677 int i = 0, j = 0; 678 u32 rbase_offset = adapter->vfs_allocated_count; 679 680 switch (adapter->hw.mac.type) { 681 case e1000_82576: 682 /* The queues are allocated for virtualization such that VF 0 683 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 684 * In order to avoid collision we start at the first free queue 685 * and continue consuming queues in the same sequence 686 */ 687 if (adapter->vfs_allocated_count) { 688 for (; i < adapter->rss_queues; i++) 689 adapter->rx_ring[i]->reg_idx = rbase_offset + 690 Q_IDX_82576(i); 691 } 692 fallthrough; 693 case e1000_82575: 694 case e1000_82580: 695 case e1000_i350: 696 case e1000_i354: 697 case e1000_i210: 698 case e1000_i211: 699 default: 700 for (; i < adapter->num_rx_queues; i++) 701 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 702 for (; j < adapter->num_tx_queues; j++) 703 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 704 break; 705 } 706} 707 708u32 igb_rd32(struct e1000_hw *hw, u32 reg) 709{ 710 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 711 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 712 u32 value = 0; 713 714 if (E1000_REMOVED(hw_addr)) 715 return ~value; 716 717 value = readl(&hw_addr[reg]); 718 719 /* reads should not return all F's */ 720 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 721 struct net_device *netdev = igb->netdev; 722 hw->hw_addr = NULL; 723 netdev_err(netdev, "PCIe link lost\n"); 724 WARN(pci_device_is_present(igb->pdev), 725 "igb: Failed to read reg 0x%x!\n", reg); 726 } 727 728 return value; 729} 730 731/** 732 * igb_write_ivar - configure ivar for given MSI-X vector 733 * @hw: pointer to the HW structure 734 * @msix_vector: vector number we are allocating to a given ring 735 * @index: row index of IVAR register to write within IVAR table 736 * @offset: column offset of in IVAR, should be multiple of 8 737 * 738 * This function is intended to handle the writing of the IVAR register 739 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 740 * each containing an cause allocation for an Rx and Tx ring, and a 741 * variable number of rows depending on the number of queues supported. 742 **/ 743static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 744 int index, int offset) 745{ 746 u32 ivar = array_rd32(E1000_IVAR0, index); 747 748 /* clear any bits that are currently set */ 749 ivar &= ~((u32)0xFF << offset); 750 751 /* write vector and valid bit */ 752 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 753 754 array_wr32(E1000_IVAR0, index, ivar); 755} 756 757#define IGB_N0_QUEUE -1 758static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 759{ 760 struct igb_adapter *adapter = q_vector->adapter; 761 struct e1000_hw *hw = &adapter->hw; 762 int rx_queue = IGB_N0_QUEUE; 763 int tx_queue = IGB_N0_QUEUE; 764 u32 msixbm = 0; 765 766 if (q_vector->rx.ring) 767 rx_queue = q_vector->rx.ring->reg_idx; 768 if (q_vector->tx.ring) 769 tx_queue = q_vector->tx.ring->reg_idx; 770 771 switch (hw->mac.type) { 772 case e1000_82575: 773 /* The 82575 assigns vectors using a bitmask, which matches the 774 * bitmask for the EICR/EIMS/EIMC registers. To assign one 775 * or more queues to a vector, we write the appropriate bits 776 * into the MSIXBM register for that vector. 777 */ 778 if (rx_queue > IGB_N0_QUEUE) 779 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 780 if (tx_queue > IGB_N0_QUEUE) 781 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 782 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 783 msixbm |= E1000_EIMS_OTHER; 784 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 785 q_vector->eims_value = msixbm; 786 break; 787 case e1000_82576: 788 /* 82576 uses a table that essentially consists of 2 columns 789 * with 8 rows. The ordering is column-major so we use the 790 * lower 3 bits as the row index, and the 4th bit as the 791 * column offset. 792 */ 793 if (rx_queue > IGB_N0_QUEUE) 794 igb_write_ivar(hw, msix_vector, 795 rx_queue & 0x7, 796 (rx_queue & 0x8) << 1); 797 if (tx_queue > IGB_N0_QUEUE) 798 igb_write_ivar(hw, msix_vector, 799 tx_queue & 0x7, 800 ((tx_queue & 0x8) << 1) + 8); 801 q_vector->eims_value = BIT(msix_vector); 802 break; 803 case e1000_82580: 804 case e1000_i350: 805 case e1000_i354: 806 case e1000_i210: 807 case e1000_i211: 808 /* On 82580 and newer adapters the scheme is similar to 82576 809 * however instead of ordering column-major we have things 810 * ordered row-major. So we traverse the table by using 811 * bit 0 as the column offset, and the remaining bits as the 812 * row index. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue >> 1, 817 (rx_queue & 0x1) << 4); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue >> 1, 821 ((tx_queue & 0x1) << 4) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 default: 825 BUG(); 826 break; 827 } 828 829 /* add q_vector eims value to global eims_enable_mask */ 830 adapter->eims_enable_mask |= q_vector->eims_value; 831 832 /* configure q_vector to set itr on first interrupt */ 833 q_vector->set_itr = 1; 834} 835 836/** 837 * igb_configure_msix - Configure MSI-X hardware 838 * @adapter: board private structure to initialize 839 * 840 * igb_configure_msix sets up the hardware to properly 841 * generate MSI-X interrupts. 842 **/ 843static void igb_configure_msix(struct igb_adapter *adapter) 844{ 845 u32 tmp; 846 int i, vector = 0; 847 struct e1000_hw *hw = &adapter->hw; 848 849 adapter->eims_enable_mask = 0; 850 851 /* set vector for other causes, i.e. link changes */ 852 switch (hw->mac.type) { 853 case e1000_82575: 854 tmp = rd32(E1000_CTRL_EXT); 855 /* enable MSI-X PBA support*/ 856 tmp |= E1000_CTRL_EXT_PBA_CLR; 857 858 /* Auto-Mask interrupts upon ICR read. */ 859 tmp |= E1000_CTRL_EXT_EIAME; 860 tmp |= E1000_CTRL_EXT_IRCA; 861 862 wr32(E1000_CTRL_EXT, tmp); 863 864 /* enable msix_other interrupt */ 865 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 866 adapter->eims_other = E1000_EIMS_OTHER; 867 868 break; 869 870 case e1000_82576: 871 case e1000_82580: 872 case e1000_i350: 873 case e1000_i354: 874 case e1000_i210: 875 case e1000_i211: 876 /* Turn on MSI-X capability first, or our settings 877 * won't stick. And it will take days to debug. 878 */ 879 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 880 E1000_GPIE_PBA | E1000_GPIE_EIAME | 881 E1000_GPIE_NSICR); 882 883 /* enable msix_other interrupt */ 884 adapter->eims_other = BIT(vector); 885 tmp = (vector++ | E1000_IVAR_VALID) << 8; 886 887 wr32(E1000_IVAR_MISC, tmp); 888 break; 889 default: 890 /* do nothing, since nothing else supports MSI-X */ 891 break; 892 } /* switch (hw->mac.type) */ 893 894 adapter->eims_enable_mask |= adapter->eims_other; 895 896 for (i = 0; i < adapter->num_q_vectors; i++) 897 igb_assign_vector(adapter->q_vector[i], vector++); 898 899 wrfl(); 900} 901 902/** 903 * igb_request_msix - Initialize MSI-X interrupts 904 * @adapter: board private structure to initialize 905 * 906 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 907 * kernel. 908 **/ 909static int igb_request_msix(struct igb_adapter *adapter) 910{ 911 unsigned int num_q_vectors = adapter->num_q_vectors; 912 struct net_device *netdev = adapter->netdev; 913 int i, err = 0, vector = 0, free_vector = 0; 914 915 err = request_irq(adapter->msix_entries[vector].vector, 916 igb_msix_other, 0, netdev->name, adapter); 917 if (err) 918 goto err_out; 919 920 if (num_q_vectors > MAX_Q_VECTORS) { 921 num_q_vectors = MAX_Q_VECTORS; 922 dev_warn(&adapter->pdev->dev, 923 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 924 adapter->num_q_vectors, MAX_Q_VECTORS); 925 } 926 for (i = 0; i < num_q_vectors; i++) { 927 struct igb_q_vector *q_vector = adapter->q_vector[i]; 928 929 vector++; 930 931 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 932 933 if (q_vector->rx.ring && q_vector->tx.ring) 934 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 935 q_vector->rx.ring->queue_index); 936 else if (q_vector->tx.ring) 937 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 938 q_vector->tx.ring->queue_index); 939 else if (q_vector->rx.ring) 940 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 941 q_vector->rx.ring->queue_index); 942 else 943 sprintf(q_vector->name, "%s-unused", netdev->name); 944 945 err = request_irq(adapter->msix_entries[vector].vector, 946 igb_msix_ring, 0, q_vector->name, 947 q_vector); 948 if (err) 949 goto err_free; 950 951 netif_napi_set_irq(&q_vector->napi, 952 adapter->msix_entries[vector].vector); 953 } 954 955 igb_configure_msix(adapter); 956 return 0; 957 958err_free: 959 /* free already assigned IRQs */ 960 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 961 962 vector--; 963 for (i = 0; i < vector; i++) { 964 free_irq(adapter->msix_entries[free_vector++].vector, 965 adapter->q_vector[i]); 966 } 967err_out: 968 return err; 969} 970 971/** 972 * igb_free_q_vector - Free memory allocated for specific interrupt vector 973 * @adapter: board private structure to initialize 974 * @v_idx: Index of vector to be freed 975 * 976 * This function frees the memory allocated to the q_vector. 977 **/ 978static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 979{ 980 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 981 982 adapter->q_vector[v_idx] = NULL; 983 984 /* igb_get_stats64() might access the rings on this vector, 985 * we must wait a grace period before freeing it. 986 */ 987 if (q_vector) 988 kfree_rcu(q_vector, rcu); 989} 990 991/** 992 * igb_reset_q_vector - Reset config for interrupt vector 993 * @adapter: board private structure to initialize 994 * @v_idx: Index of vector to be reset 995 * 996 * If NAPI is enabled it will delete any references to the 997 * NAPI struct. This is preparation for igb_free_q_vector. 998 **/ 999static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1000{ 1001 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1002 1003 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1004 * allocated. So, q_vector is NULL so we should stop here. 1005 */ 1006 if (!q_vector) 1007 return; 1008 1009 if (q_vector->tx.ring) 1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1011 1012 if (q_vector->rx.ring) 1013 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1014 1015 netif_napi_del(&q_vector->napi); 1016 1017} 1018 1019static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1020{ 1021 int v_idx = adapter->num_q_vectors; 1022 1023 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1024 pci_disable_msix(adapter->pdev); 1025 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1026 pci_disable_msi(adapter->pdev); 1027 1028 while (v_idx--) 1029 igb_reset_q_vector(adapter, v_idx); 1030} 1031 1032/** 1033 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1034 * @adapter: board private structure to initialize 1035 * 1036 * This function frees the memory allocated to the q_vectors. In addition if 1037 * NAPI is enabled it will delete any references to the NAPI struct prior 1038 * to freeing the q_vector. 1039 **/ 1040static void igb_free_q_vectors(struct igb_adapter *adapter) 1041{ 1042 int v_idx = adapter->num_q_vectors; 1043 1044 adapter->num_tx_queues = 0; 1045 adapter->num_rx_queues = 0; 1046 adapter->num_q_vectors = 0; 1047 1048 while (v_idx--) { 1049 igb_reset_q_vector(adapter, v_idx); 1050 igb_free_q_vector(adapter, v_idx); 1051 } 1052} 1053 1054/** 1055 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1056 * @adapter: board private structure to initialize 1057 * 1058 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1059 * MSI-X interrupts allocated. 1060 */ 1061static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1062{ 1063 igb_free_q_vectors(adapter); 1064 igb_reset_interrupt_capability(adapter); 1065} 1066 1067/** 1068 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1069 * @adapter: board private structure to initialize 1070 * @msix: boolean value of MSIX capability 1071 * 1072 * Attempt to configure interrupts using the best available 1073 * capabilities of the hardware and kernel. 1074 **/ 1075static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1076{ 1077 int err; 1078 int numvecs, i; 1079 1080 if (!msix) 1081 goto msi_only; 1082 adapter->flags |= IGB_FLAG_HAS_MSIX; 1083 1084 /* Number of supported queues. */ 1085 adapter->num_rx_queues = adapter->rss_queues; 1086 if (adapter->vfs_allocated_count) 1087 adapter->num_tx_queues = 1; 1088 else 1089 adapter->num_tx_queues = adapter->rss_queues; 1090 1091 /* start with one vector for every Rx queue */ 1092 numvecs = adapter->num_rx_queues; 1093 1094 /* if Tx handler is separate add 1 for every Tx queue */ 1095 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1096 numvecs += adapter->num_tx_queues; 1097 1098 /* store the number of vectors reserved for queues */ 1099 adapter->num_q_vectors = numvecs; 1100 1101 /* add 1 vector for link status interrupts */ 1102 numvecs++; 1103 for (i = 0; i < numvecs; i++) 1104 adapter->msix_entries[i].entry = i; 1105 1106 err = pci_enable_msix_range(adapter->pdev, 1107 adapter->msix_entries, 1108 numvecs, 1109 numvecs); 1110 if (err > 0) 1111 return; 1112 1113 igb_reset_interrupt_capability(adapter); 1114 1115 /* If we can't do MSI-X, try MSI */ 1116msi_only: 1117 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1118#ifdef CONFIG_PCI_IOV 1119 /* disable SR-IOV for non MSI-X configurations */ 1120 if (adapter->vf_data) { 1121 struct e1000_hw *hw = &adapter->hw; 1122 /* disable iov and allow time for transactions to clear */ 1123 pci_disable_sriov(adapter->pdev); 1124 msleep(500); 1125 1126 kfree(adapter->vf_mac_list); 1127 adapter->vf_mac_list = NULL; 1128 kfree(adapter->vf_data); 1129 adapter->vf_data = NULL; 1130 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1131 wrfl(); 1132 msleep(100); 1133 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1134 } 1135#endif 1136 adapter->vfs_allocated_count = 0; 1137 adapter->rss_queues = 1; 1138 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1139 adapter->num_rx_queues = 1; 1140 adapter->num_tx_queues = 1; 1141 adapter->num_q_vectors = 1; 1142 if (!pci_enable_msi(adapter->pdev)) 1143 adapter->flags |= IGB_FLAG_HAS_MSI; 1144} 1145 1146static void igb_add_ring(struct igb_ring *ring, 1147 struct igb_ring_container *head) 1148{ 1149 head->ring = ring; 1150 head->count++; 1151} 1152 1153/** 1154 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1155 * @adapter: board private structure to initialize 1156 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1157 * @v_idx: index of vector in adapter struct 1158 * @txr_count: total number of Tx rings to allocate 1159 * @txr_idx: index of first Tx ring to allocate 1160 * @rxr_count: total number of Rx rings to allocate 1161 * @rxr_idx: index of first Rx ring to allocate 1162 * 1163 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1164 **/ 1165static int igb_alloc_q_vector(struct igb_adapter *adapter, 1166 int v_count, int v_idx, 1167 int txr_count, int txr_idx, 1168 int rxr_count, int rxr_idx) 1169{ 1170 struct igb_q_vector *q_vector; 1171 struct igb_ring *ring; 1172 int ring_count; 1173 size_t size; 1174 1175 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1176 if (txr_count > 1 || rxr_count > 1) 1177 return -ENOMEM; 1178 1179 ring_count = txr_count + rxr_count; 1180 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1181 1182 /* allocate q_vector and rings */ 1183 q_vector = adapter->q_vector[v_idx]; 1184 if (!q_vector) { 1185 q_vector = kzalloc(size, GFP_KERNEL); 1186 } else if (size > ksize(q_vector)) { 1187 struct igb_q_vector *new_q_vector; 1188 1189 new_q_vector = kzalloc(size, GFP_KERNEL); 1190 if (new_q_vector) 1191 kfree_rcu(q_vector, rcu); 1192 q_vector = new_q_vector; 1193 } else { 1194 memset(q_vector, 0, size); 1195 } 1196 if (!q_vector) 1197 return -ENOMEM; 1198 1199 /* initialize NAPI */ 1200 netif_napi_add_config(adapter->netdev, &q_vector->napi, igb_poll, 1201 v_idx); 1202 1203 /* tie q_vector and adapter together */ 1204 adapter->q_vector[v_idx] = q_vector; 1205 q_vector->adapter = adapter; 1206 1207 /* initialize work limits */ 1208 q_vector->tx.work_limit = adapter->tx_work_limit; 1209 1210 /* initialize ITR configuration */ 1211 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1212 q_vector->itr_val = IGB_START_ITR; 1213 1214 /* initialize pointer to rings */ 1215 ring = q_vector->ring; 1216 1217 /* initialize ITR */ 1218 if (rxr_count) { 1219 /* rx or rx/tx vector */ 1220 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1221 q_vector->itr_val = adapter->rx_itr_setting; 1222 } else { 1223 /* tx only vector */ 1224 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1225 q_vector->itr_val = adapter->tx_itr_setting; 1226 } 1227 1228 if (txr_count) { 1229 /* assign generic ring traits */ 1230 ring->dev = &adapter->pdev->dev; 1231 ring->netdev = adapter->netdev; 1232 1233 /* configure backlink on ring */ 1234 ring->q_vector = q_vector; 1235 1236 /* update q_vector Tx values */ 1237 igb_add_ring(ring, &q_vector->tx); 1238 1239 /* For 82575, context index must be unique per ring. */ 1240 if (adapter->hw.mac.type == e1000_82575) 1241 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1242 1243 /* apply Tx specific ring traits */ 1244 ring->count = adapter->tx_ring_count; 1245 ring->queue_index = txr_idx; 1246 1247 ring->cbs_enable = false; 1248 ring->idleslope = 0; 1249 ring->sendslope = 0; 1250 ring->hicredit = 0; 1251 ring->locredit = 0; 1252 1253 u64_stats_init(&ring->tx_syncp); 1254 u64_stats_init(&ring->tx_syncp2); 1255 1256 /* assign ring to adapter */ 1257 adapter->tx_ring[txr_idx] = ring; 1258 1259 /* push pointer to next ring */ 1260 ring++; 1261 } 1262 1263 if (rxr_count) { 1264 /* assign generic ring traits */ 1265 ring->dev = &adapter->pdev->dev; 1266 ring->netdev = adapter->netdev; 1267 1268 /* configure backlink on ring */ 1269 ring->q_vector = q_vector; 1270 1271 /* update q_vector Rx values */ 1272 igb_add_ring(ring, &q_vector->rx); 1273 1274 /* set flag indicating ring supports SCTP checksum offload */ 1275 if (adapter->hw.mac.type >= e1000_82576) 1276 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1277 1278 /* On i350, i354, i210, and i211, loopback VLAN packets 1279 * have the tag byte-swapped. 1280 */ 1281 if (adapter->hw.mac.type >= e1000_i350) 1282 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1283 1284 /* apply Rx specific ring traits */ 1285 ring->count = adapter->rx_ring_count; 1286 ring->queue_index = rxr_idx; 1287 1288 u64_stats_init(&ring->rx_syncp); 1289 1290 /* assign ring to adapter */ 1291 adapter->rx_ring[rxr_idx] = ring; 1292 } 1293 1294 return 0; 1295} 1296 1297 1298/** 1299 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1300 * @adapter: board private structure to initialize 1301 * 1302 * We allocate one q_vector per queue interrupt. If allocation fails we 1303 * return -ENOMEM. 1304 **/ 1305static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1306{ 1307 int q_vectors = adapter->num_q_vectors; 1308 int rxr_remaining = adapter->num_rx_queues; 1309 int txr_remaining = adapter->num_tx_queues; 1310 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1311 int err; 1312 1313 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1314 for (; rxr_remaining; v_idx++) { 1315 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1316 0, 0, 1, rxr_idx); 1317 1318 if (err) 1319 goto err_out; 1320 1321 /* update counts and index */ 1322 rxr_remaining--; 1323 rxr_idx++; 1324 } 1325 } 1326 1327 for (; v_idx < q_vectors; v_idx++) { 1328 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1329 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1330 1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1332 tqpv, txr_idx, rqpv, rxr_idx); 1333 1334 if (err) 1335 goto err_out; 1336 1337 /* update counts and index */ 1338 rxr_remaining -= rqpv; 1339 txr_remaining -= tqpv; 1340 rxr_idx++; 1341 txr_idx++; 1342 } 1343 1344 return 0; 1345 1346err_out: 1347 adapter->num_tx_queues = 0; 1348 adapter->num_rx_queues = 0; 1349 adapter->num_q_vectors = 0; 1350 1351 while (v_idx--) 1352 igb_free_q_vector(adapter, v_idx); 1353 1354 return -ENOMEM; 1355} 1356 1357/** 1358 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1359 * @adapter: board private structure to initialize 1360 * @msix: boolean value of MSIX capability 1361 * 1362 * This function initializes the interrupts and allocates all of the queues. 1363 **/ 1364static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1365{ 1366 struct pci_dev *pdev = adapter->pdev; 1367 int err; 1368 1369 igb_set_interrupt_capability(adapter, msix); 1370 1371 err = igb_alloc_q_vectors(adapter); 1372 if (err) { 1373 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1374 goto err_alloc_q_vectors; 1375 } 1376 1377 igb_cache_ring_register(adapter); 1378 1379 return 0; 1380 1381err_alloc_q_vectors: 1382 igb_reset_interrupt_capability(adapter); 1383 return err; 1384} 1385 1386/** 1387 * igb_request_irq - initialize interrupts 1388 * @adapter: board private structure to initialize 1389 * 1390 * Attempts to configure interrupts using the best available 1391 * capabilities of the hardware and kernel. 1392 **/ 1393static int igb_request_irq(struct igb_adapter *adapter) 1394{ 1395 struct net_device *netdev = adapter->netdev; 1396 struct pci_dev *pdev = adapter->pdev; 1397 int err = 0; 1398 1399 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1400 err = igb_request_msix(adapter); 1401 if (!err) 1402 goto request_done; 1403 /* fall back to MSI */ 1404 igb_free_all_tx_resources(adapter); 1405 igb_free_all_rx_resources(adapter); 1406 1407 igb_clear_interrupt_scheme(adapter); 1408 err = igb_init_interrupt_scheme(adapter, false); 1409 if (err) 1410 goto request_done; 1411 1412 igb_setup_all_tx_resources(adapter); 1413 igb_setup_all_rx_resources(adapter); 1414 igb_configure(adapter); 1415 } 1416 1417 igb_assign_vector(adapter->q_vector[0], 0); 1418 1419 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1420 err = request_irq(pdev->irq, igb_intr_msi, 0, 1421 netdev->name, adapter); 1422 if (!err) 1423 goto request_done; 1424 1425 /* fall back to legacy interrupts */ 1426 igb_reset_interrupt_capability(adapter); 1427 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1428 } 1429 1430 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1431 netdev->name, adapter); 1432 1433 if (err) 1434 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1435 err); 1436 1437request_done: 1438 return err; 1439} 1440 1441static void igb_free_irq(struct igb_adapter *adapter) 1442{ 1443 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1444 int vector = 0, i; 1445 1446 free_irq(adapter->msix_entries[vector++].vector, adapter); 1447 1448 for (i = 0; i < adapter->num_q_vectors; i++) 1449 free_irq(adapter->msix_entries[vector++].vector, 1450 adapter->q_vector[i]); 1451 } else { 1452 free_irq(adapter->pdev->irq, adapter); 1453 } 1454} 1455 1456/** 1457 * igb_irq_disable - Mask off interrupt generation on the NIC 1458 * @adapter: board private structure 1459 **/ 1460static void igb_irq_disable(struct igb_adapter *adapter) 1461{ 1462 struct e1000_hw *hw = &adapter->hw; 1463 1464 /* we need to be careful when disabling interrupts. The VFs are also 1465 * mapped into these registers and so clearing the bits can cause 1466 * issues on the VF drivers so we only need to clear what we set 1467 */ 1468 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1469 u32 regval = rd32(E1000_EIAM); 1470 1471 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1472 wr32(E1000_EIMC, adapter->eims_enable_mask); 1473 regval = rd32(E1000_EIAC); 1474 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1475 } 1476 1477 wr32(E1000_IAM, 0); 1478 wr32(E1000_IMC, ~0); 1479 wrfl(); 1480 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1481 int i; 1482 1483 for (i = 0; i < adapter->num_q_vectors; i++) 1484 synchronize_irq(adapter->msix_entries[i].vector); 1485 } else { 1486 synchronize_irq(adapter->pdev->irq); 1487 } 1488} 1489 1490/** 1491 * igb_irq_enable - Enable default interrupt generation settings 1492 * @adapter: board private structure 1493 **/ 1494static void igb_irq_enable(struct igb_adapter *adapter) 1495{ 1496 struct e1000_hw *hw = &adapter->hw; 1497 1498 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1499 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1500 u32 regval = rd32(E1000_EIAC); 1501 1502 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1503 regval = rd32(E1000_EIAM); 1504 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1505 wr32(E1000_EIMS, adapter->eims_enable_mask); 1506 if (adapter->vfs_allocated_count) { 1507 wr32(E1000_MBVFIMR, 0xFF); 1508 ims |= E1000_IMS_VMMB; 1509 } 1510 wr32(E1000_IMS, ims); 1511 } else { 1512 wr32(E1000_IMS, IMS_ENABLE_MASK | 1513 E1000_IMS_DRSTA); 1514 wr32(E1000_IAM, IMS_ENABLE_MASK | 1515 E1000_IMS_DRSTA); 1516 } 1517} 1518 1519static void igb_update_mng_vlan(struct igb_adapter *adapter) 1520{ 1521 struct e1000_hw *hw = &adapter->hw; 1522 u16 pf_id = adapter->vfs_allocated_count; 1523 u16 vid = adapter->hw.mng_cookie.vlan_id; 1524 u16 old_vid = adapter->mng_vlan_id; 1525 1526 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1527 /* add VID to filter table */ 1528 igb_vfta_set(hw, vid, pf_id, true, true); 1529 adapter->mng_vlan_id = vid; 1530 } else { 1531 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1532 } 1533 1534 if (old_vid != IGB_MNG_VLAN_NONE && vid != old_vid && 1535 !test_bit(old_vid, adapter->active_vlans)) { 1536 /* remove VID from filter table */ 1537 igb_vfta_set(hw, vid, pf_id, false, true); 1538 } 1539} 1540 1541/** 1542 * igb_release_hw_control - release control of the h/w to f/w 1543 * @adapter: address of board private structure 1544 * 1545 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1546 * For ASF and Pass Through versions of f/w this means that the 1547 * driver is no longer loaded. 1548 **/ 1549static void igb_release_hw_control(struct igb_adapter *adapter) 1550{ 1551 struct e1000_hw *hw = &adapter->hw; 1552 u32 ctrl_ext; 1553 1554 /* Let firmware take over control of h/w */ 1555 ctrl_ext = rd32(E1000_CTRL_EXT); 1556 wr32(E1000_CTRL_EXT, 1557 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1558} 1559 1560/** 1561 * igb_get_hw_control - get control of the h/w from f/w 1562 * @adapter: address of board private structure 1563 * 1564 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1565 * For ASF and Pass Through versions of f/w this means that 1566 * the driver is loaded. 1567 **/ 1568static void igb_get_hw_control(struct igb_adapter *adapter) 1569{ 1570 struct e1000_hw *hw = &adapter->hw; 1571 u32 ctrl_ext; 1572 1573 /* Let firmware know the driver has taken over */ 1574 ctrl_ext = rd32(E1000_CTRL_EXT); 1575 wr32(E1000_CTRL_EXT, 1576 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1577} 1578 1579static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1580{ 1581 struct net_device *netdev = adapter->netdev; 1582 struct e1000_hw *hw = &adapter->hw; 1583 1584 WARN_ON(hw->mac.type != e1000_i210); 1585 1586 if (enable) 1587 adapter->flags |= IGB_FLAG_FQTSS; 1588 else 1589 adapter->flags &= ~IGB_FLAG_FQTSS; 1590 1591 if (netif_running(netdev)) 1592 schedule_work(&adapter->reset_task); 1593} 1594 1595static bool is_fqtss_enabled(struct igb_adapter *adapter) 1596{ 1597 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1598} 1599 1600static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1601 enum tx_queue_prio prio) 1602{ 1603 u32 val; 1604 1605 WARN_ON(hw->mac.type != e1000_i210); 1606 WARN_ON(queue < 0 || queue > 4); 1607 1608 val = rd32(E1000_I210_TXDCTL(queue)); 1609 1610 if (prio == TX_QUEUE_PRIO_HIGH) 1611 val |= E1000_TXDCTL_PRIORITY; 1612 else 1613 val &= ~E1000_TXDCTL_PRIORITY; 1614 1615 wr32(E1000_I210_TXDCTL(queue), val); 1616} 1617 1618static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1619{ 1620 u32 val; 1621 1622 WARN_ON(hw->mac.type != e1000_i210); 1623 WARN_ON(queue < 0 || queue > 1); 1624 1625 val = rd32(E1000_I210_TQAVCC(queue)); 1626 1627 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1628 val |= E1000_TQAVCC_QUEUEMODE; 1629 else 1630 val &= ~E1000_TQAVCC_QUEUEMODE; 1631 1632 wr32(E1000_I210_TQAVCC(queue), val); 1633} 1634 1635static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1636{ 1637 int i; 1638 1639 for (i = 0; i < adapter->num_tx_queues; i++) { 1640 if (adapter->tx_ring[i]->cbs_enable) 1641 return true; 1642 } 1643 1644 return false; 1645} 1646 1647static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1648{ 1649 int i; 1650 1651 for (i = 0; i < adapter->num_tx_queues; i++) { 1652 if (adapter->tx_ring[i]->launchtime_enable) 1653 return true; 1654 } 1655 1656 return false; 1657} 1658 1659/** 1660 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1661 * @adapter: pointer to adapter struct 1662 * @queue: queue number 1663 * 1664 * Configure CBS and Launchtime for a given hardware queue. 1665 * Parameters are retrieved from the correct Tx ring, so 1666 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1667 * for setting those correctly prior to this function being called. 1668 **/ 1669static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1670{ 1671 struct net_device *netdev = adapter->netdev; 1672 struct e1000_hw *hw = &adapter->hw; 1673 struct igb_ring *ring; 1674 u32 tqavcc, tqavctrl; 1675 u16 value; 1676 1677 WARN_ON(hw->mac.type != e1000_i210); 1678 WARN_ON(queue < 0 || queue > 1); 1679 ring = adapter->tx_ring[queue]; 1680 1681 /* If any of the Qav features is enabled, configure queues as SR and 1682 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1683 * as SP. 1684 */ 1685 if (ring->cbs_enable || ring->launchtime_enable) { 1686 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1687 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1688 } else { 1689 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1690 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1691 } 1692 1693 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1694 if (ring->cbs_enable || queue == 0) { 1695 /* i210 does not allow the queue 0 to be in the Strict 1696 * Priority mode while the Qav mode is enabled, so, 1697 * instead of disabling strict priority mode, we give 1698 * queue 0 the maximum of credits possible. 1699 * 1700 * See section 8.12.19 of the i210 datasheet, "Note: 1701 * Queue0 QueueMode must be set to 1b when 1702 * TransmitMode is set to Qav." 1703 */ 1704 if (queue == 0 && !ring->cbs_enable) { 1705 /* max "linkspeed" idleslope in kbps */ 1706 ring->idleslope = 1000000; 1707 ring->hicredit = ETH_FRAME_LEN; 1708 } 1709 1710 /* Always set data transfer arbitration to credit-based 1711 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1712 * the queues. 1713 */ 1714 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1715 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1716 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1717 1718 /* According to i210 datasheet section 7.2.7.7, we should set 1719 * the 'idleSlope' field from TQAVCC register following the 1720 * equation: 1721 * 1722 * For 100 Mbps link speed: 1723 * 1724 * value = BW * 0x7735 * 0.2 (E1) 1725 * 1726 * For 1000Mbps link speed: 1727 * 1728 * value = BW * 0x7735 * 2 (E2) 1729 * 1730 * E1 and E2 can be merged into one equation as shown below. 1731 * Note that 'link-speed' is in Mbps. 1732 * 1733 * value = BW * 0x7735 * 2 * link-speed 1734 * -------------- (E3) 1735 * 1000 1736 * 1737 * 'BW' is the percentage bandwidth out of full link speed 1738 * which can be found with the following equation. Note that 1739 * idleSlope here is the parameter from this function which 1740 * is in kbps. 1741 * 1742 * BW = idleSlope 1743 * ----------------- (E4) 1744 * link-speed * 1000 1745 * 1746 * That said, we can come up with a generic equation to 1747 * calculate the value we should set it TQAVCC register by 1748 * replacing 'BW' in E3 by E4. The resulting equation is: 1749 * 1750 * value = idleSlope * 0x7735 * 2 * link-speed 1751 * ----------------- -------------- (E5) 1752 * link-speed * 1000 1000 1753 * 1754 * 'link-speed' is present in both sides of the fraction so 1755 * it is canceled out. The final equation is the following: 1756 * 1757 * value = idleSlope * 61034 1758 * ----------------- (E6) 1759 * 1000000 1760 * 1761 * NOTE: For i210, given the above, we can see that idleslope 1762 * is represented in 16.38431 kbps units by the value at 1763 * the TQAVCC register (1Gbps / 61034), which reduces 1764 * the granularity for idleslope increments. 1765 * For instance, if you want to configure a 2576kbps 1766 * idleslope, the value to be written on the register 1767 * would have to be 157.23. If rounded down, you end 1768 * up with less bandwidth available than originally 1769 * required (~2572 kbps). If rounded up, you end up 1770 * with a higher bandwidth (~2589 kbps). Below the 1771 * approach we take is to always round up the 1772 * calculated value, so the resulting bandwidth might 1773 * be slightly higher for some configurations. 1774 */ 1775 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1776 1777 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1778 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1779 tqavcc |= value; 1780 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1781 1782 wr32(E1000_I210_TQAVHC(queue), 1783 0x80000000 + ring->hicredit * 0x7735); 1784 } else { 1785 1786 /* Set idleSlope to zero. */ 1787 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1788 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1789 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1790 1791 /* Set hiCredit to zero. */ 1792 wr32(E1000_I210_TQAVHC(queue), 0); 1793 1794 /* If CBS is not enabled for any queues anymore, then return to 1795 * the default state of Data Transmission Arbitration on 1796 * TQAVCTRL. 1797 */ 1798 if (!is_any_cbs_enabled(adapter)) { 1799 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1800 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1801 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1802 } 1803 } 1804 1805 /* If LaunchTime is enabled, set DataTranTIM. */ 1806 if (ring->launchtime_enable) { 1807 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1808 * for any of the SR queues, and configure fetchtime delta. 1809 * XXX NOTE: 1810 * - LaunchTime will be enabled for all SR queues. 1811 * - A fixed offset can be added relative to the launch 1812 * time of all packets if configured at reg LAUNCH_OS0. 1813 * We are keeping it as 0 for now (default value). 1814 */ 1815 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1816 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1817 E1000_TQAVCTRL_FETCHTIME_DELTA; 1818 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1819 } else { 1820 /* If Launchtime is not enabled for any SR queues anymore, 1821 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1822 * effectively disabling Launchtime. 1823 */ 1824 if (!is_any_txtime_enabled(adapter)) { 1825 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1826 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1827 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1828 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1829 } 1830 } 1831 1832 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1833 * CBS are not configurable by software so we don't do any 'controller 1834 * configuration' in respect to these parameters. 1835 */ 1836 1837 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1838 ring->cbs_enable ? "enabled" : "disabled", 1839 ring->launchtime_enable ? "enabled" : "disabled", 1840 queue, 1841 ring->idleslope, ring->sendslope, 1842 ring->hicredit, ring->locredit); 1843} 1844 1845static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1846 bool enable) 1847{ 1848 struct igb_ring *ring; 1849 1850 if (queue < 0 || queue > adapter->num_tx_queues) 1851 return -EINVAL; 1852 1853 ring = adapter->tx_ring[queue]; 1854 ring->launchtime_enable = enable; 1855 1856 return 0; 1857} 1858 1859static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1860 bool enable, int idleslope, int sendslope, 1861 int hicredit, int locredit) 1862{ 1863 struct igb_ring *ring; 1864 1865 if (queue < 0 || queue > adapter->num_tx_queues) 1866 return -EINVAL; 1867 1868 ring = adapter->tx_ring[queue]; 1869 1870 ring->cbs_enable = enable; 1871 ring->idleslope = idleslope; 1872 ring->sendslope = sendslope; 1873 ring->hicredit = hicredit; 1874 ring->locredit = locredit; 1875 1876 return 0; 1877} 1878 1879/** 1880 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1881 * @adapter: pointer to adapter struct 1882 * 1883 * Configure TQAVCTRL register switching the controller's Tx mode 1884 * if FQTSS mode is enabled or disabled. Additionally, will issue 1885 * a call to igb_config_tx_modes() per queue so any previously saved 1886 * Tx parameters are applied. 1887 **/ 1888static void igb_setup_tx_mode(struct igb_adapter *adapter) 1889{ 1890 struct net_device *netdev = adapter->netdev; 1891 struct e1000_hw *hw = &adapter->hw; 1892 u32 val; 1893 1894 /* Only i210 controller supports changing the transmission mode. */ 1895 if (hw->mac.type != e1000_i210) 1896 return; 1897 1898 if (is_fqtss_enabled(adapter)) { 1899 int i, max_queue; 1900 1901 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1902 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1903 * so SP queues wait for SR ones. 1904 */ 1905 val = rd32(E1000_I210_TQAVCTRL); 1906 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1907 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1908 wr32(E1000_I210_TQAVCTRL, val); 1909 1910 /* Configure Tx and Rx packet buffers sizes as described in 1911 * i210 datasheet section 7.2.7.7. 1912 */ 1913 val = rd32(E1000_TXPBS); 1914 val &= ~I210_TXPBSIZE_MASK; 1915 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1916 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1917 wr32(E1000_TXPBS, val); 1918 1919 val = rd32(E1000_RXPBS); 1920 val &= ~I210_RXPBSIZE_MASK; 1921 val |= I210_RXPBSIZE_PB_30KB; 1922 wr32(E1000_RXPBS, val); 1923 1924 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1925 * register should not exceed the buffer size programmed in 1926 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1927 * so according to the datasheet we should set MAX_TPKT_SIZE to 1928 * 4kB / 64. 1929 * 1930 * However, when we do so, no frame from queue 2 and 3 are 1931 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1932 * or _equal_ to the buffer size programmed in TXPBS. For this 1933 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1934 */ 1935 val = (4096 - 1) / 64; 1936 wr32(E1000_I210_DTXMXPKTSZ, val); 1937 1938 /* Since FQTSS mode is enabled, apply any CBS configuration 1939 * previously set. If no previous CBS configuration has been 1940 * done, then the initial configuration is applied, which means 1941 * CBS is disabled. 1942 */ 1943 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1944 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1945 1946 for (i = 0; i < max_queue; i++) { 1947 igb_config_tx_modes(adapter, i); 1948 } 1949 } else { 1950 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1951 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1952 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1953 1954 val = rd32(E1000_I210_TQAVCTRL); 1955 /* According to Section 8.12.21, the other flags we've set when 1956 * enabling FQTSS are not relevant when disabling FQTSS so we 1957 * don't set they here. 1958 */ 1959 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1960 wr32(E1000_I210_TQAVCTRL, val); 1961 } 1962 1963 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1964 "enabled" : "disabled"); 1965} 1966 1967/** 1968 * igb_configure - configure the hardware for RX and TX 1969 * @adapter: private board structure 1970 **/ 1971static void igb_configure(struct igb_adapter *adapter) 1972{ 1973 struct net_device *netdev = adapter->netdev; 1974 int i; 1975 1976 igb_get_hw_control(adapter); 1977 igb_set_rx_mode(netdev); 1978 igb_setup_tx_mode(adapter); 1979 1980 igb_restore_vlan(adapter); 1981 1982 igb_setup_tctl(adapter); 1983 igb_setup_mrqc(adapter); 1984 igb_setup_rctl(adapter); 1985 1986 igb_nfc_filter_restore(adapter); 1987 igb_configure_tx(adapter); 1988 igb_configure_rx(adapter); 1989 1990 igb_rx_fifo_flush_82575(&adapter->hw); 1991 1992 /* call igb_desc_unused which always leaves 1993 * at least 1 descriptor unused to make sure 1994 * next_to_use != next_to_clean 1995 */ 1996 for (i = 0; i < adapter->num_rx_queues; i++) { 1997 struct igb_ring *ring = adapter->rx_ring[i]; 1998 if (ring->xsk_pool) 1999 igb_alloc_rx_buffers_zc(ring, ring->xsk_pool, 2000 igb_desc_unused(ring)); 2001 else 2002 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2003 } 2004} 2005 2006/** 2007 * igb_power_up_link - Power up the phy/serdes link 2008 * @adapter: address of board private structure 2009 **/ 2010void igb_power_up_link(struct igb_adapter *adapter) 2011{ 2012 igb_reset_phy(&adapter->hw); 2013 2014 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2015 igb_power_up_phy_copper(&adapter->hw); 2016 else 2017 igb_power_up_serdes_link_82575(&adapter->hw); 2018 2019 igb_setup_link(&adapter->hw); 2020} 2021 2022/** 2023 * igb_power_down_link - Power down the phy/serdes link 2024 * @adapter: address of board private structure 2025 */ 2026static void igb_power_down_link(struct igb_adapter *adapter) 2027{ 2028 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2029 igb_power_down_phy_copper_82575(&adapter->hw); 2030 else 2031 igb_shutdown_serdes_link_82575(&adapter->hw); 2032} 2033 2034/** 2035 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2036 * @adapter: address of the board private structure 2037 **/ 2038static void igb_check_swap_media(struct igb_adapter *adapter) 2039{ 2040 struct e1000_hw *hw = &adapter->hw; 2041 u32 ctrl_ext, connsw; 2042 bool swap_now = false; 2043 2044 ctrl_ext = rd32(E1000_CTRL_EXT); 2045 connsw = rd32(E1000_CONNSW); 2046 2047 /* need to live swap if current media is copper and we have fiber/serdes 2048 * to go to. 2049 */ 2050 2051 if ((hw->phy.media_type == e1000_media_type_copper) && 2052 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2053 swap_now = true; 2054 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2055 !(connsw & E1000_CONNSW_SERDESD)) { 2056 /* copper signal takes time to appear */ 2057 if (adapter->copper_tries < 4) { 2058 adapter->copper_tries++; 2059 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2060 wr32(E1000_CONNSW, connsw); 2061 return; 2062 } else { 2063 adapter->copper_tries = 0; 2064 if ((connsw & E1000_CONNSW_PHYSD) && 2065 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2066 swap_now = true; 2067 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2068 wr32(E1000_CONNSW, connsw); 2069 } 2070 } 2071 } 2072 2073 if (!swap_now) 2074 return; 2075 2076 switch (hw->phy.media_type) { 2077 case e1000_media_type_copper: 2078 netdev_info(adapter->netdev, 2079 "MAS: changing media to fiber/serdes\n"); 2080 ctrl_ext |= 2081 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2082 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2083 adapter->copper_tries = 0; 2084 break; 2085 case e1000_media_type_internal_serdes: 2086 case e1000_media_type_fiber: 2087 netdev_info(adapter->netdev, 2088 "MAS: changing media to copper\n"); 2089 ctrl_ext &= 2090 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2091 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2092 break; 2093 default: 2094 /* shouldn't get here during regular operation */ 2095 netdev_err(adapter->netdev, 2096 "AMS: Invalid media type found, returning\n"); 2097 break; 2098 } 2099 wr32(E1000_CTRL_EXT, ctrl_ext); 2100} 2101 2102void igb_set_queue_napi(struct igb_adapter *adapter, int vector, 2103 struct napi_struct *napi) 2104{ 2105 struct igb_q_vector *q_vector = adapter->q_vector[vector]; 2106 2107 if (q_vector->rx.ring) 2108 netif_queue_set_napi(adapter->netdev, 2109 q_vector->rx.ring->queue_index, 2110 NETDEV_QUEUE_TYPE_RX, napi); 2111 2112 if (q_vector->tx.ring) 2113 netif_queue_set_napi(adapter->netdev, 2114 q_vector->tx.ring->queue_index, 2115 NETDEV_QUEUE_TYPE_TX, napi); 2116} 2117 2118/** 2119 * igb_up - Open the interface and prepare it to handle traffic 2120 * @adapter: board private structure 2121 **/ 2122int igb_up(struct igb_adapter *adapter) 2123{ 2124 struct e1000_hw *hw = &adapter->hw; 2125 struct napi_struct *napi; 2126 int i; 2127 2128 /* hardware has been reset, we need to reload some things */ 2129 igb_configure(adapter); 2130 2131 clear_bit(__IGB_DOWN, &adapter->state); 2132 2133 for (i = 0; i < adapter->num_q_vectors; i++) { 2134 napi = &adapter->q_vector[i]->napi; 2135 napi_enable(napi); 2136 igb_set_queue_napi(adapter, i, napi); 2137 } 2138 2139 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2140 igb_configure_msix(adapter); 2141 else 2142 igb_assign_vector(adapter->q_vector[0], 0); 2143 2144 /* Clear any pending interrupts. */ 2145 rd32(E1000_TSICR); 2146 rd32(E1000_ICR); 2147 igb_irq_enable(adapter); 2148 2149 /* notify VFs that reset has been completed */ 2150 if (adapter->vfs_allocated_count) { 2151 u32 reg_data = rd32(E1000_CTRL_EXT); 2152 2153 reg_data |= E1000_CTRL_EXT_PFRSTD; 2154 wr32(E1000_CTRL_EXT, reg_data); 2155 } 2156 2157 netif_tx_start_all_queues(adapter->netdev); 2158 2159 /* start the watchdog. */ 2160 hw->mac.get_link_status = 1; 2161 schedule_work(&adapter->watchdog_task); 2162 2163 if ((adapter->flags & IGB_FLAG_EEE) && 2164 (!hw->dev_spec._82575.eee_disable)) 2165 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2166 2167 return 0; 2168} 2169 2170void igb_down(struct igb_adapter *adapter) 2171{ 2172 struct net_device *netdev = adapter->netdev; 2173 struct e1000_hw *hw = &adapter->hw; 2174 u32 tctl, rctl; 2175 int i; 2176 2177 /* signal that we're down so the interrupt handler does not 2178 * reschedule our watchdog timer 2179 */ 2180 set_bit(__IGB_DOWN, &adapter->state); 2181 2182 /* disable receives in the hardware */ 2183 rctl = rd32(E1000_RCTL); 2184 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2185 /* flush and sleep below */ 2186 2187 igb_nfc_filter_exit(adapter); 2188 2189 netif_carrier_off(netdev); 2190 netif_tx_stop_all_queues(netdev); 2191 2192 /* disable transmits in the hardware */ 2193 tctl = rd32(E1000_TCTL); 2194 tctl &= ~E1000_TCTL_EN; 2195 wr32(E1000_TCTL, tctl); 2196 /* flush both disables and wait for them to finish */ 2197 wrfl(); 2198 usleep_range(10000, 11000); 2199 2200 igb_irq_disable(adapter); 2201 2202 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2203 2204 for (i = 0; i < adapter->num_q_vectors; i++) { 2205 if (adapter->q_vector[i]) { 2206 napi_disable(&adapter->q_vector[i]->napi); 2207 igb_set_queue_napi(adapter, i, NULL); 2208 } 2209 } 2210 2211 timer_delete_sync(&adapter->watchdog_timer); 2212 timer_delete_sync(&adapter->phy_info_timer); 2213 2214 /* record the stats before reset*/ 2215 spin_lock(&adapter->stats64_lock); 2216 igb_update_stats(adapter); 2217 spin_unlock(&adapter->stats64_lock); 2218 2219 adapter->link_speed = 0; 2220 adapter->link_duplex = 0; 2221 2222 if (!pci_channel_offline(adapter->pdev)) 2223 igb_reset(adapter); 2224 2225 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2226 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2227 2228 igb_clean_all_tx_rings(adapter); 2229 igb_clean_all_rx_rings(adapter); 2230#ifdef CONFIG_IGB_DCA 2231 2232 /* since we reset the hardware DCA settings were cleared */ 2233 igb_setup_dca(adapter); 2234#endif 2235} 2236 2237void igb_reinit_locked(struct igb_adapter *adapter) 2238{ 2239 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2240 usleep_range(1000, 2000); 2241 igb_down(adapter); 2242 igb_up(adapter); 2243 clear_bit(__IGB_RESETTING, &adapter->state); 2244} 2245 2246/** igb_enable_mas - Media Autosense re-enable after swap 2247 * 2248 * @adapter: adapter struct 2249 **/ 2250static void igb_enable_mas(struct igb_adapter *adapter) 2251{ 2252 struct e1000_hw *hw = &adapter->hw; 2253 u32 connsw = rd32(E1000_CONNSW); 2254 2255 /* configure for SerDes media detect */ 2256 if ((hw->phy.media_type == e1000_media_type_copper) && 2257 (!(connsw & E1000_CONNSW_SERDESD))) { 2258 connsw |= E1000_CONNSW_ENRGSRC; 2259 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2260 wr32(E1000_CONNSW, connsw); 2261 wrfl(); 2262 } 2263} 2264 2265#ifdef CONFIG_IGB_HWMON 2266/** 2267 * igb_set_i2c_bb - Init I2C interface 2268 * @hw: pointer to hardware structure 2269 **/ 2270static void igb_set_i2c_bb(struct e1000_hw *hw) 2271{ 2272 u32 ctrl_ext; 2273 s32 i2cctl; 2274 2275 ctrl_ext = rd32(E1000_CTRL_EXT); 2276 ctrl_ext |= E1000_CTRL_I2C_ENA; 2277 wr32(E1000_CTRL_EXT, ctrl_ext); 2278 wrfl(); 2279 2280 i2cctl = rd32(E1000_I2CPARAMS); 2281 i2cctl |= E1000_I2CBB_EN 2282 | E1000_I2C_CLK_OE_N 2283 | E1000_I2C_DATA_OE_N; 2284 wr32(E1000_I2CPARAMS, i2cctl); 2285 wrfl(); 2286} 2287#endif 2288 2289void igb_reset(struct igb_adapter *adapter) 2290{ 2291 struct pci_dev *pdev = adapter->pdev; 2292 struct e1000_hw *hw = &adapter->hw; 2293 struct e1000_mac_info *mac = &hw->mac; 2294 struct e1000_fc_info *fc = &hw->fc; 2295 u32 pba, hwm; 2296 2297 /* Repartition Pba for greater than 9k mtu 2298 * To take effect CTRL.RST is required. 2299 */ 2300 switch (mac->type) { 2301 case e1000_i350: 2302 case e1000_i354: 2303 case e1000_82580: 2304 pba = rd32(E1000_RXPBS); 2305 pba = igb_rxpbs_adjust_82580(pba); 2306 break; 2307 case e1000_82576: 2308 pba = rd32(E1000_RXPBS); 2309 pba &= E1000_RXPBS_SIZE_MASK_82576; 2310 break; 2311 case e1000_82575: 2312 case e1000_i210: 2313 case e1000_i211: 2314 default: 2315 pba = E1000_PBA_34K; 2316 break; 2317 } 2318 2319 if (mac->type == e1000_82575) { 2320 u32 min_rx_space, min_tx_space, needed_tx_space; 2321 2322 /* write Rx PBA so that hardware can report correct Tx PBA */ 2323 wr32(E1000_PBA, pba); 2324 2325 /* To maintain wire speed transmits, the Tx FIFO should be 2326 * large enough to accommodate two full transmit packets, 2327 * rounded up to the next 1KB and expressed in KB. Likewise, 2328 * the Rx FIFO should be large enough to accommodate at least 2329 * one full receive packet and is similarly rounded up and 2330 * expressed in KB. 2331 */ 2332 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2333 2334 /* The Tx FIFO also stores 16 bytes of information about the Tx 2335 * but don't include Ethernet FCS because hardware appends it. 2336 * We only need to round down to the nearest 512 byte block 2337 * count since the value we care about is 2 frames, not 1. 2338 */ 2339 min_tx_space = adapter->max_frame_size; 2340 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2341 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2342 2343 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2344 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2345 2346 /* If current Tx allocation is less than the min Tx FIFO size, 2347 * and the min Tx FIFO size is less than the current Rx FIFO 2348 * allocation, take space away from current Rx allocation. 2349 */ 2350 if (needed_tx_space < pba) { 2351 pba -= needed_tx_space; 2352 2353 /* if short on Rx space, Rx wins and must trump Tx 2354 * adjustment 2355 */ 2356 if (pba < min_rx_space) 2357 pba = min_rx_space; 2358 } 2359 2360 /* adjust PBA for jumbo frames */ 2361 wr32(E1000_PBA, pba); 2362 } 2363 2364 /* flow control settings 2365 * The high water mark must be low enough to fit one full frame 2366 * after transmitting the pause frame. As such we must have enough 2367 * space to allow for us to complete our current transmit and then 2368 * receive the frame that is in progress from the link partner. 2369 * Set it to: 2370 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2371 */ 2372 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2373 2374 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2375 fc->low_water = fc->high_water - 16; 2376 fc->pause_time = 0xFFFF; 2377 fc->send_xon = 1; 2378 fc->current_mode = fc->requested_mode; 2379 2380 /* disable receive for all VFs and wait one second */ 2381 if (adapter->vfs_allocated_count) { 2382 int i; 2383 2384 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2385 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2386 2387 /* ping all the active vfs to let them know we are going down */ 2388 igb_ping_all_vfs(adapter); 2389 2390 /* disable transmits and receives */ 2391 wr32(E1000_VFRE, 0); 2392 wr32(E1000_VFTE, 0); 2393 } 2394 2395 /* Allow time for pending master requests to run */ 2396 hw->mac.ops.reset_hw(hw); 2397 wr32(E1000_WUC, 0); 2398 2399 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2400 /* need to resetup here after media swap */ 2401 adapter->ei.get_invariants(hw); 2402 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2403 } 2404 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2405 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2406 igb_enable_mas(adapter); 2407 } 2408 if (hw->mac.ops.init_hw(hw)) 2409 dev_err(&pdev->dev, "Hardware Error\n"); 2410 2411 /* RAR registers were cleared during init_hw, clear mac table */ 2412 igb_flush_mac_table(adapter); 2413 __dev_uc_unsync(adapter->netdev, NULL); 2414 2415 /* Recover default RAR entry */ 2416 igb_set_default_mac_filter(adapter); 2417 2418 /* Flow control settings reset on hardware reset, so guarantee flow 2419 * control is off when forcing speed. 2420 */ 2421 if (!hw->mac.autoneg) 2422 igb_force_mac_fc(hw); 2423 2424 igb_init_dmac(adapter, pba); 2425#ifdef CONFIG_IGB_HWMON 2426 /* Re-initialize the thermal sensor on i350 devices. */ 2427 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2428 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2429 /* If present, re-initialize the external thermal sensor 2430 * interface. 2431 */ 2432 if (adapter->ets) 2433 igb_set_i2c_bb(hw); 2434 mac->ops.init_thermal_sensor_thresh(hw); 2435 } 2436 } 2437#endif 2438 /* Re-establish EEE setting */ 2439 if (hw->phy.media_type == e1000_media_type_copper) { 2440 switch (mac->type) { 2441 case e1000_i350: 2442 case e1000_i210: 2443 case e1000_i211: 2444 igb_set_eee_i350(hw, true, true); 2445 break; 2446 case e1000_i354: 2447 igb_set_eee_i354(hw, true, true); 2448 break; 2449 default: 2450 break; 2451 } 2452 } 2453 if (!netif_running(adapter->netdev)) 2454 igb_power_down_link(adapter); 2455 2456 igb_update_mng_vlan(adapter); 2457 2458 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2459 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2460 2461 /* Re-enable PTP, where applicable. */ 2462 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2463 igb_ptp_reset(adapter); 2464 2465 igb_get_phy_info(hw); 2466} 2467 2468static netdev_features_t igb_fix_features(struct net_device *netdev, 2469 netdev_features_t features) 2470{ 2471 /* Since there is no support for separate Rx/Tx vlan accel 2472 * enable/disable make sure Tx flag is always in same state as Rx. 2473 */ 2474 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2475 features |= NETIF_F_HW_VLAN_CTAG_TX; 2476 else 2477 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2478 2479 return features; 2480} 2481 2482static int igb_set_features(struct net_device *netdev, 2483 netdev_features_t features) 2484{ 2485 netdev_features_t changed = netdev->features ^ features; 2486 struct igb_adapter *adapter = netdev_priv(netdev); 2487 2488 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2489 igb_vlan_mode(netdev, features); 2490 2491 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2492 return 0; 2493 2494 if (!(features & NETIF_F_NTUPLE)) { 2495 struct hlist_node *node2; 2496 struct igb_nfc_filter *rule; 2497 2498 spin_lock(&adapter->nfc_lock); 2499 hlist_for_each_entry_safe(rule, node2, 2500 &adapter->nfc_filter_list, nfc_node) { 2501 igb_erase_filter(adapter, rule); 2502 hlist_del(&rule->nfc_node); 2503 kfree(rule); 2504 } 2505 spin_unlock(&adapter->nfc_lock); 2506 adapter->nfc_filter_count = 0; 2507 } 2508 2509 netdev->features = features; 2510 2511 if (netif_running(netdev)) 2512 igb_reinit_locked(adapter); 2513 else 2514 igb_reset(adapter); 2515 2516 return 1; 2517} 2518 2519static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2520 struct net_device *dev, 2521 const unsigned char *addr, u16 vid, 2522 u16 flags, bool *notified, 2523 struct netlink_ext_ack *extack) 2524{ 2525 /* guarantee we can provide a unique filter for the unicast address */ 2526 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2527 struct igb_adapter *adapter = netdev_priv(dev); 2528 int vfn = adapter->vfs_allocated_count; 2529 2530 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2531 return -ENOMEM; 2532 } 2533 2534 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2535} 2536 2537#define IGB_MAX_MAC_HDR_LEN 127 2538#define IGB_MAX_NETWORK_HDR_LEN 511 2539 2540static netdev_features_t 2541igb_features_check(struct sk_buff *skb, struct net_device *dev, 2542 netdev_features_t features) 2543{ 2544 unsigned int network_hdr_len, mac_hdr_len; 2545 2546 /* Make certain the headers can be described by a context descriptor */ 2547 mac_hdr_len = skb_network_offset(skb); 2548 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2549 return features & ~(NETIF_F_HW_CSUM | 2550 NETIF_F_SCTP_CRC | 2551 NETIF_F_GSO_UDP_L4 | 2552 NETIF_F_HW_VLAN_CTAG_TX | 2553 NETIF_F_TSO | 2554 NETIF_F_TSO6); 2555 2556 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2557 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2558 return features & ~(NETIF_F_HW_CSUM | 2559 NETIF_F_SCTP_CRC | 2560 NETIF_F_GSO_UDP_L4 | 2561 NETIF_F_TSO | 2562 NETIF_F_TSO6); 2563 2564 /* We can only support IPV4 TSO in tunnels if we can mangle the 2565 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2566 */ 2567 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2568 features &= ~NETIF_F_TSO; 2569 2570 return features; 2571} 2572 2573static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2574{ 2575 if (!is_fqtss_enabled(adapter)) { 2576 enable_fqtss(adapter, true); 2577 return; 2578 } 2579 2580 igb_config_tx_modes(adapter, queue); 2581 2582 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2583 enable_fqtss(adapter, false); 2584} 2585 2586static int igb_offload_cbs(struct igb_adapter *adapter, 2587 struct tc_cbs_qopt_offload *qopt) 2588{ 2589 struct e1000_hw *hw = &adapter->hw; 2590 int err; 2591 2592 /* CBS offloading is only supported by i210 controller. */ 2593 if (hw->mac.type != e1000_i210) 2594 return -EOPNOTSUPP; 2595 2596 /* CBS offloading is only supported by queue 0 and queue 1. */ 2597 if (qopt->queue < 0 || qopt->queue > 1) 2598 return -EINVAL; 2599 2600 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2601 qopt->idleslope, qopt->sendslope, 2602 qopt->hicredit, qopt->locredit); 2603 if (err) 2604 return err; 2605 2606 igb_offload_apply(adapter, qopt->queue); 2607 2608 return 0; 2609} 2610 2611#define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2612#define VLAN_PRIO_FULL_MASK (0x07) 2613 2614static int igb_parse_cls_flower(struct igb_adapter *adapter, 2615 struct flow_cls_offload *f, 2616 int traffic_class, 2617 struct igb_nfc_filter *input) 2618{ 2619 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2620 struct flow_dissector *dissector = rule->match.dissector; 2621 struct netlink_ext_ack *extack = f->common.extack; 2622 2623 if (dissector->used_keys & 2624 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 2625 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 2626 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2627 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) { 2628 NL_SET_ERR_MSG_MOD(extack, 2629 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2630 return -EOPNOTSUPP; 2631 } 2632 2633 if (flow_rule_match_has_control_flags(rule, extack)) 2634 return -EOPNOTSUPP; 2635 2636 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2637 struct flow_match_eth_addrs match; 2638 2639 flow_rule_match_eth_addrs(rule, &match); 2640 if (!is_zero_ether_addr(match.mask->dst)) { 2641 if (!is_broadcast_ether_addr(match.mask->dst)) { 2642 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2643 return -EINVAL; 2644 } 2645 2646 input->filter.match_flags |= 2647 IGB_FILTER_FLAG_DST_MAC_ADDR; 2648 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2649 } 2650 2651 if (!is_zero_ether_addr(match.mask->src)) { 2652 if (!is_broadcast_ether_addr(match.mask->src)) { 2653 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2654 return -EINVAL; 2655 } 2656 2657 input->filter.match_flags |= 2658 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2659 ether_addr_copy(input->filter.src_addr, match.key->src); 2660 } 2661 } 2662 2663 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2664 struct flow_match_basic match; 2665 2666 flow_rule_match_basic(rule, &match); 2667 if (match.mask->n_proto) { 2668 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2669 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2670 return -EINVAL; 2671 } 2672 2673 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2674 input->filter.etype = match.key->n_proto; 2675 } 2676 } 2677 2678 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2679 struct flow_match_vlan match; 2680 2681 flow_rule_match_vlan(rule, &match); 2682 if (match.mask->vlan_priority) { 2683 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2684 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2685 return -EINVAL; 2686 } 2687 2688 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2689 input->filter.vlan_tci = 2690 (__force __be16)match.key->vlan_priority; 2691 } 2692 } 2693 2694 input->action = traffic_class; 2695 input->cookie = f->cookie; 2696 2697 return 0; 2698} 2699 2700static int igb_configure_clsflower(struct igb_adapter *adapter, 2701 struct flow_cls_offload *cls_flower) 2702{ 2703 struct netlink_ext_ack *extack = cls_flower->common.extack; 2704 struct igb_nfc_filter *filter, *f; 2705 int err, tc; 2706 2707 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2708 if (tc < 0) { 2709 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2710 return -EINVAL; 2711 } 2712 2713 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2714 if (!filter) 2715 return -ENOMEM; 2716 2717 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2718 if (err < 0) 2719 goto err_parse; 2720 2721 spin_lock(&adapter->nfc_lock); 2722 2723 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2724 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2725 err = -EEXIST; 2726 NL_SET_ERR_MSG_MOD(extack, 2727 "This filter is already set in ethtool"); 2728 goto err_locked; 2729 } 2730 } 2731 2732 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2733 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2734 err = -EEXIST; 2735 NL_SET_ERR_MSG_MOD(extack, 2736 "This filter is already set in cls_flower"); 2737 goto err_locked; 2738 } 2739 } 2740 2741 err = igb_add_filter(adapter, filter); 2742 if (err < 0) { 2743 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2744 goto err_locked; 2745 } 2746 2747 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2748 2749 spin_unlock(&adapter->nfc_lock); 2750 2751 return 0; 2752 2753err_locked: 2754 spin_unlock(&adapter->nfc_lock); 2755 2756err_parse: 2757 kfree(filter); 2758 2759 return err; 2760} 2761 2762static int igb_delete_clsflower(struct igb_adapter *adapter, 2763 struct flow_cls_offload *cls_flower) 2764{ 2765 struct igb_nfc_filter *filter; 2766 int err; 2767 2768 spin_lock(&adapter->nfc_lock); 2769 2770 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2771 if (filter->cookie == cls_flower->cookie) 2772 break; 2773 2774 if (!filter) { 2775 err = -ENOENT; 2776 goto out; 2777 } 2778 2779 err = igb_erase_filter(adapter, filter); 2780 if (err < 0) 2781 goto out; 2782 2783 hlist_del(&filter->nfc_node); 2784 kfree(filter); 2785 2786out: 2787 spin_unlock(&adapter->nfc_lock); 2788 2789 return err; 2790} 2791 2792static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2793 struct flow_cls_offload *cls_flower) 2794{ 2795 switch (cls_flower->command) { 2796 case FLOW_CLS_REPLACE: 2797 return igb_configure_clsflower(adapter, cls_flower); 2798 case FLOW_CLS_DESTROY: 2799 return igb_delete_clsflower(adapter, cls_flower); 2800 case FLOW_CLS_STATS: 2801 return -EOPNOTSUPP; 2802 default: 2803 return -EOPNOTSUPP; 2804 } 2805} 2806 2807static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2808 void *cb_priv) 2809{ 2810 struct igb_adapter *adapter = cb_priv; 2811 2812 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2813 return -EOPNOTSUPP; 2814 2815 switch (type) { 2816 case TC_SETUP_CLSFLOWER: 2817 return igb_setup_tc_cls_flower(adapter, type_data); 2818 2819 default: 2820 return -EOPNOTSUPP; 2821 } 2822} 2823 2824static int igb_offload_txtime(struct igb_adapter *adapter, 2825 struct tc_etf_qopt_offload *qopt) 2826{ 2827 struct e1000_hw *hw = &adapter->hw; 2828 int err; 2829 2830 /* Launchtime offloading is only supported by i210 controller. */ 2831 if (hw->mac.type != e1000_i210) 2832 return -EOPNOTSUPP; 2833 2834 /* Launchtime offloading is only supported by queues 0 and 1. */ 2835 if (qopt->queue < 0 || qopt->queue > 1) 2836 return -EINVAL; 2837 2838 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2839 if (err) 2840 return err; 2841 2842 igb_offload_apply(adapter, qopt->queue); 2843 2844 return 0; 2845} 2846 2847static int igb_tc_query_caps(struct igb_adapter *adapter, 2848 struct tc_query_caps_base *base) 2849{ 2850 switch (base->type) { 2851 case TC_SETUP_QDISC_TAPRIO: { 2852 struct tc_taprio_caps *caps = base->caps; 2853 2854 caps->broken_mqprio = true; 2855 2856 return 0; 2857 } 2858 default: 2859 return -EOPNOTSUPP; 2860 } 2861} 2862 2863static LIST_HEAD(igb_block_cb_list); 2864 2865static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2866 void *type_data) 2867{ 2868 struct igb_adapter *adapter = netdev_priv(dev); 2869 2870 switch (type) { 2871 case TC_QUERY_CAPS: 2872 return igb_tc_query_caps(adapter, type_data); 2873 case TC_SETUP_QDISC_CBS: 2874 return igb_offload_cbs(adapter, type_data); 2875 case TC_SETUP_BLOCK: 2876 return flow_block_cb_setup_simple(type_data, 2877 &igb_block_cb_list, 2878 igb_setup_tc_block_cb, 2879 adapter, adapter, true); 2880 2881 case TC_SETUP_QDISC_ETF: 2882 return igb_offload_txtime(adapter, type_data); 2883 2884 default: 2885 return -EOPNOTSUPP; 2886 } 2887} 2888 2889static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2890{ 2891 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2892 struct igb_adapter *adapter = netdev_priv(dev); 2893 struct bpf_prog *prog = bpf->prog, *old_prog; 2894 bool running = netif_running(dev); 2895 bool need_reset; 2896 2897 /* verify igb ring attributes are sufficient for XDP */ 2898 for (i = 0; i < adapter->num_rx_queues; i++) { 2899 struct igb_ring *ring = adapter->rx_ring[i]; 2900 2901 if (frame_size > igb_rx_bufsz(ring)) { 2902 NL_SET_ERR_MSG_MOD(bpf->extack, 2903 "The RX buffer size is too small for the frame size"); 2904 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2905 igb_rx_bufsz(ring), frame_size); 2906 return -EINVAL; 2907 } 2908 } 2909 2910 old_prog = xchg(&adapter->xdp_prog, prog); 2911 need_reset = (!!prog != !!old_prog); 2912 2913 /* device is up and bpf is added/removed, must setup the RX queues */ 2914 if (need_reset && running) { 2915 igb_close(dev); 2916 } else { 2917 for (i = 0; i < adapter->num_rx_queues; i++) 2918 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2919 adapter->xdp_prog); 2920 } 2921 2922 if (old_prog) 2923 bpf_prog_put(old_prog); 2924 2925 /* bpf is just replaced, RXQ and MTU are already setup */ 2926 if (!need_reset) { 2927 return 0; 2928 } else { 2929 if (prog) 2930 xdp_features_set_redirect_target(dev, true); 2931 else 2932 xdp_features_clear_redirect_target(dev); 2933 } 2934 2935 if (running) 2936 igb_open(dev); 2937 2938 return 0; 2939} 2940 2941static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2942{ 2943 struct igb_adapter *adapter = netdev_priv(dev); 2944 2945 switch (xdp->command) { 2946 case XDP_SETUP_PROG: 2947 return igb_xdp_setup(dev, xdp); 2948 case XDP_SETUP_XSK_POOL: 2949 return igb_xsk_pool_setup(adapter, xdp->xsk.pool, 2950 xdp->xsk.queue_id); 2951 default: 2952 return -EINVAL; 2953 } 2954} 2955 2956int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2957{ 2958 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2959 int cpu = smp_processor_id(); 2960 struct igb_ring *tx_ring; 2961 struct netdev_queue *nq; 2962 u32 ret; 2963 2964 if (unlikely(!xdpf)) 2965 return IGB_XDP_CONSUMED; 2966 2967 /* During program transitions its possible adapter->xdp_prog is assigned 2968 * but ring has not been configured yet. In this case simply abort xmit. 2969 */ 2970 tx_ring = igb_xdp_is_enabled(adapter) ? 2971 igb_xdp_tx_queue_mapping(adapter) : NULL; 2972 if (unlikely(!tx_ring)) 2973 return IGB_XDP_CONSUMED; 2974 2975 nq = txring_txq(tx_ring); 2976 __netif_tx_lock(nq, cpu); 2977 /* Avoid transmit queue timeout since we share it with the slow path */ 2978 txq_trans_cond_update(nq); 2979 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2980 __netif_tx_unlock(nq); 2981 2982 return ret; 2983} 2984 2985static int igb_xdp_xmit(struct net_device *dev, int n, 2986 struct xdp_frame **frames, u32 flags) 2987{ 2988 struct igb_adapter *adapter = netdev_priv(dev); 2989 int cpu = smp_processor_id(); 2990 struct igb_ring *tx_ring; 2991 struct netdev_queue *nq; 2992 int nxmit = 0; 2993 int i; 2994 2995 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2996 return -ENETDOWN; 2997 2998 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2999 return -EINVAL; 3000 3001 /* During program transitions its possible adapter->xdp_prog is assigned 3002 * but ring has not been configured yet. In this case simply abort xmit. 3003 */ 3004 tx_ring = igb_xdp_is_enabled(adapter) ? 3005 igb_xdp_tx_queue_mapping(adapter) : NULL; 3006 if (unlikely(!tx_ring)) 3007 return -ENXIO; 3008 3009 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 3010 return -ENXIO; 3011 3012 nq = txring_txq(tx_ring); 3013 __netif_tx_lock(nq, cpu); 3014 3015 /* Avoid transmit queue timeout since we share it with the slow path */ 3016 txq_trans_cond_update(nq); 3017 3018 for (i = 0; i < n; i++) { 3019 struct xdp_frame *xdpf = frames[i]; 3020 int err; 3021 3022 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3023 if (err != IGB_XDP_TX) 3024 break; 3025 nxmit++; 3026 } 3027 3028 if (unlikely(flags & XDP_XMIT_FLUSH)) 3029 igb_xdp_ring_update_tail(tx_ring); 3030 3031 __netif_tx_unlock(nq); 3032 3033 return nxmit; 3034} 3035 3036static const struct net_device_ops igb_netdev_ops = { 3037 .ndo_open = igb_open, 3038 .ndo_stop = igb_close, 3039 .ndo_start_xmit = igb_xmit_frame, 3040 .ndo_get_stats64 = igb_get_stats64, 3041 .ndo_set_rx_mode = igb_set_rx_mode, 3042 .ndo_set_mac_address = igb_set_mac, 3043 .ndo_change_mtu = igb_change_mtu, 3044 .ndo_eth_ioctl = igb_ioctl, 3045 .ndo_tx_timeout = igb_tx_timeout, 3046 .ndo_validate_addr = eth_validate_addr, 3047 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3048 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3049 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3050 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3051 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3052 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3053 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3054 .ndo_get_vf_config = igb_ndo_get_vf_config, 3055 .ndo_fix_features = igb_fix_features, 3056 .ndo_set_features = igb_set_features, 3057 .ndo_fdb_add = igb_ndo_fdb_add, 3058 .ndo_features_check = igb_features_check, 3059 .ndo_setup_tc = igb_setup_tc, 3060 .ndo_bpf = igb_xdp, 3061 .ndo_xdp_xmit = igb_xdp_xmit, 3062 .ndo_xsk_wakeup = igb_xsk_wakeup, 3063 .ndo_hwtstamp_get = igb_ptp_hwtstamp_get, 3064 .ndo_hwtstamp_set = igb_ptp_hwtstamp_set, 3065}; 3066 3067/** 3068 * igb_set_fw_version - Configure version string for ethtool 3069 * @adapter: adapter struct 3070 **/ 3071void igb_set_fw_version(struct igb_adapter *adapter) 3072{ 3073 struct e1000_hw *hw = &adapter->hw; 3074 struct e1000_fw_version fw; 3075 3076 igb_get_fw_version(hw, &fw); 3077 3078 switch (hw->mac.type) { 3079 case e1000_i210: 3080 case e1000_i211: 3081 if (!(igb_get_flash_presence_i210(hw))) { 3082 snprintf(adapter->fw_version, 3083 sizeof(adapter->fw_version), 3084 "%2d.%2d-%d", 3085 fw.invm_major, fw.invm_minor, 3086 fw.invm_img_type); 3087 break; 3088 } 3089 fallthrough; 3090 default: 3091 /* if option rom is valid, display its version too */ 3092 if (fw.or_valid) { 3093 snprintf(adapter->fw_version, 3094 sizeof(adapter->fw_version), 3095 "%d.%d, 0x%08x, %d.%d.%d", 3096 fw.eep_major, fw.eep_minor, fw.etrack_id, 3097 fw.or_major, fw.or_build, fw.or_patch); 3098 /* no option rom */ 3099 } else if (fw.etrack_id != 0X0000) { 3100 snprintf(adapter->fw_version, 3101 sizeof(adapter->fw_version), 3102 "%d.%d, 0x%08x", 3103 fw.eep_major, fw.eep_minor, fw.etrack_id); 3104 } else { 3105 snprintf(adapter->fw_version, 3106 sizeof(adapter->fw_version), 3107 "%d.%d.%d", 3108 fw.eep_major, fw.eep_minor, fw.eep_build); 3109 } 3110 break; 3111 } 3112} 3113 3114/** 3115 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3116 * 3117 * @adapter: adapter struct 3118 **/ 3119static void igb_init_mas(struct igb_adapter *adapter) 3120{ 3121 struct e1000_hw *hw = &adapter->hw; 3122 u16 eeprom_data; 3123 3124 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3125 switch (hw->bus.func) { 3126 case E1000_FUNC_0: 3127 if (eeprom_data & IGB_MAS_ENABLE_0) { 3128 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3129 netdev_info(adapter->netdev, 3130 "MAS: Enabling Media Autosense for port %d\n", 3131 hw->bus.func); 3132 } 3133 break; 3134 case E1000_FUNC_1: 3135 if (eeprom_data & IGB_MAS_ENABLE_1) { 3136 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3137 netdev_info(adapter->netdev, 3138 "MAS: Enabling Media Autosense for port %d\n", 3139 hw->bus.func); 3140 } 3141 break; 3142 case E1000_FUNC_2: 3143 if (eeprom_data & IGB_MAS_ENABLE_2) { 3144 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3145 netdev_info(adapter->netdev, 3146 "MAS: Enabling Media Autosense for port %d\n", 3147 hw->bus.func); 3148 } 3149 break; 3150 case E1000_FUNC_3: 3151 if (eeprom_data & IGB_MAS_ENABLE_3) { 3152 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3153 netdev_info(adapter->netdev, 3154 "MAS: Enabling Media Autosense for port %d\n", 3155 hw->bus.func); 3156 } 3157 break; 3158 default: 3159 /* Shouldn't get here */ 3160 netdev_err(adapter->netdev, 3161 "MAS: Invalid port configuration, returning\n"); 3162 break; 3163 } 3164} 3165 3166/** 3167 * igb_init_i2c - Init I2C interface 3168 * @adapter: pointer to adapter structure 3169 **/ 3170static s32 igb_init_i2c(struct igb_adapter *adapter) 3171{ 3172 s32 status = 0; 3173 3174 /* I2C interface supported on i350 devices */ 3175 if (adapter->hw.mac.type != e1000_i350) 3176 return 0; 3177 3178 /* Initialize the i2c bus which is controlled by the registers. 3179 * This bus will use the i2c_algo_bit structure that implements 3180 * the protocol through toggling of the 4 bits in the register. 3181 */ 3182 adapter->i2c_adap.owner = THIS_MODULE; 3183 adapter->i2c_algo = igb_i2c_algo; 3184 adapter->i2c_algo.data = adapter; 3185 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3186 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3187 strscpy(adapter->i2c_adap.name, "igb BB", 3188 sizeof(adapter->i2c_adap.name)); 3189 status = i2c_bit_add_bus(&adapter->i2c_adap); 3190 return status; 3191} 3192 3193/** 3194 * igb_probe - Device Initialization Routine 3195 * @pdev: PCI device information struct 3196 * @ent: entry in igb_pci_tbl 3197 * 3198 * Returns 0 on success, negative on failure 3199 * 3200 * igb_probe initializes an adapter identified by a pci_dev structure. 3201 * The OS initialization, configuring of the adapter private structure, 3202 * and a hardware reset occur. 3203 **/ 3204static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3205{ 3206 struct net_device *netdev; 3207 struct igb_adapter *adapter; 3208 struct e1000_hw *hw; 3209 u16 eeprom_data = 0; 3210 s32 ret_val; 3211 static int global_quad_port_a; /* global quad port a indication */ 3212 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3213 u8 part_str[E1000_PBANUM_LENGTH]; 3214 int err; 3215 3216 /* Catch broken hardware that put the wrong VF device ID in 3217 * the PCIe SR-IOV capability. 3218 */ 3219 if (pdev->is_virtfn) { 3220 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3221 pci_name(pdev), pdev->vendor, pdev->device); 3222 return -EINVAL; 3223 } 3224 3225 err = pci_enable_device_mem(pdev); 3226 if (err) 3227 return err; 3228 3229 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3230 if (err) { 3231 dev_err(&pdev->dev, 3232 "No usable DMA configuration, aborting\n"); 3233 goto err_dma; 3234 } 3235 3236 err = pci_request_mem_regions(pdev, igb_driver_name); 3237 if (err) 3238 goto err_pci_reg; 3239 3240 pci_set_master(pdev); 3241 pci_save_state(pdev); 3242 3243 err = -ENOMEM; 3244 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3245 IGB_MAX_TX_QUEUES); 3246 if (!netdev) 3247 goto err_alloc_etherdev; 3248 3249 SET_NETDEV_DEV(netdev, &pdev->dev); 3250 3251 pci_set_drvdata(pdev, netdev); 3252 adapter = netdev_priv(netdev); 3253 adapter->netdev = netdev; 3254 adapter->pdev = pdev; 3255 hw = &adapter->hw; 3256 hw->back = adapter; 3257 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3258 3259 err = -EIO; 3260 adapter->io_addr = pci_iomap(pdev, 0, 0); 3261 if (!adapter->io_addr) 3262 goto err_ioremap; 3263 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3264 hw->hw_addr = adapter->io_addr; 3265 3266 netdev->netdev_ops = &igb_netdev_ops; 3267 igb_set_ethtool_ops(netdev); 3268 netdev->watchdog_timeo = 5 * HZ; 3269 3270 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 3271 3272 netdev->mem_start = pci_resource_start(pdev, 0); 3273 netdev->mem_end = pci_resource_end(pdev, 0); 3274 3275 /* PCI config space info */ 3276 hw->vendor_id = pdev->vendor; 3277 hw->device_id = pdev->device; 3278 hw->revision_id = pdev->revision; 3279 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3280 hw->subsystem_device_id = pdev->subsystem_device; 3281 3282 /* Copy the default MAC, PHY and NVM function pointers */ 3283 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3284 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3285 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3286 /* Initialize skew-specific constants */ 3287 err = ei->get_invariants(hw); 3288 if (err) 3289 goto err_sw_init; 3290 3291 /* setup the private structure */ 3292 err = igb_sw_init(adapter); 3293 if (err) 3294 goto err_sw_init; 3295 3296 igb_get_bus_info_pcie(hw); 3297 3298 hw->phy.autoneg_wait_to_complete = false; 3299 3300 /* Copper options */ 3301 if (hw->phy.media_type == e1000_media_type_copper) { 3302 hw->phy.mdix = AUTO_ALL_MODES; 3303 hw->phy.disable_polarity_correction = false; 3304 hw->phy.ms_type = e1000_ms_hw_default; 3305 } 3306 3307 if (igb_check_reset_block(hw)) 3308 dev_info(&pdev->dev, 3309 "PHY reset is blocked due to SOL/IDER session.\n"); 3310 3311 /* features is initialized to 0 in allocation, it might have bits 3312 * set by igb_sw_init so we should use an or instead of an 3313 * assignment. 3314 */ 3315 netdev->features |= NETIF_F_SG | 3316 NETIF_F_TSO | 3317 NETIF_F_TSO6 | 3318 NETIF_F_RXHASH | 3319 NETIF_F_RXCSUM | 3320 NETIF_F_HW_CSUM; 3321 3322 if (hw->mac.type >= e1000_82576) 3323 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3324 3325 if (hw->mac.type >= e1000_i350) 3326 netdev->features |= NETIF_F_HW_TC; 3327 3328#define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3329 NETIF_F_GSO_GRE_CSUM | \ 3330 NETIF_F_GSO_IPXIP4 | \ 3331 NETIF_F_GSO_IPXIP6 | \ 3332 NETIF_F_GSO_UDP_TUNNEL | \ 3333 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3334 3335 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3336 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3337 3338 /* copy netdev features into list of user selectable features */ 3339 netdev->hw_features |= netdev->features | 3340 NETIF_F_HW_VLAN_CTAG_RX | 3341 NETIF_F_HW_VLAN_CTAG_TX | 3342 NETIF_F_RXALL; 3343 3344 if (hw->mac.type >= e1000_i350) 3345 netdev->hw_features |= NETIF_F_NTUPLE; 3346 3347 netdev->features |= NETIF_F_HIGHDMA; 3348 3349 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3350 netdev->mpls_features |= NETIF_F_HW_CSUM; 3351 netdev->hw_enc_features |= netdev->vlan_features; 3352 3353 /* set this bit last since it cannot be part of vlan_features */ 3354 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3355 NETIF_F_HW_VLAN_CTAG_RX | 3356 NETIF_F_HW_VLAN_CTAG_TX; 3357 3358 netdev->priv_flags |= IFF_SUPP_NOFCS; 3359 3360 netdev->priv_flags |= IFF_UNICAST_FLT; 3361 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 3362 NETDEV_XDP_ACT_XSK_ZEROCOPY; 3363 3364 /* MTU range: 68 - 9216 */ 3365 netdev->min_mtu = ETH_MIN_MTU; 3366 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3367 3368 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3369 3370 /* before reading the NVM, reset the controller to put the device in a 3371 * known good starting state 3372 */ 3373 hw->mac.ops.reset_hw(hw); 3374 3375 /* make sure the NVM is good , i211/i210 parts can have special NVM 3376 * that doesn't contain a checksum 3377 */ 3378 switch (hw->mac.type) { 3379 case e1000_i210: 3380 case e1000_i211: 3381 if (igb_get_flash_presence_i210(hw)) { 3382 if (hw->nvm.ops.validate(hw) < 0) { 3383 dev_err(&pdev->dev, 3384 "The NVM Checksum Is Not Valid\n"); 3385 err = -EIO; 3386 goto err_eeprom; 3387 } 3388 } 3389 break; 3390 default: 3391 if (hw->nvm.ops.validate(hw) < 0) { 3392 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3393 err = -EIO; 3394 goto err_eeprom; 3395 } 3396 break; 3397 } 3398 3399 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3400 /* copy the MAC address out of the NVM */ 3401 if (hw->mac.ops.read_mac_addr(hw)) 3402 dev_err(&pdev->dev, "NVM Read Error\n"); 3403 } 3404 3405 eth_hw_addr_set(netdev, hw->mac.addr); 3406 3407 if (!is_valid_ether_addr(netdev->dev_addr)) { 3408 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3409 err = -EIO; 3410 goto err_eeprom; 3411 } 3412 3413 igb_set_default_mac_filter(adapter); 3414 3415 /* get firmware version for ethtool -i */ 3416 igb_set_fw_version(adapter); 3417 3418 /* configure RXPBSIZE and TXPBSIZE */ 3419 if (hw->mac.type == e1000_i210) { 3420 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3421 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3422 } 3423 3424 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3425 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3426 3427 INIT_WORK(&adapter->reset_task, igb_reset_task); 3428 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3429 3430 /* Initialize link properties that are user-changeable */ 3431 adapter->fc_autoneg = true; 3432 hw->mac.autoneg = true; 3433 hw->phy.autoneg_advertised = 0x2f; 3434 3435 hw->fc.requested_mode = e1000_fc_default; 3436 hw->fc.current_mode = e1000_fc_default; 3437 3438 igb_validate_mdi_setting(hw); 3439 3440 /* By default, support wake on port A */ 3441 if (hw->bus.func == 0) 3442 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3443 3444 /* Check the NVM for wake support on non-port A ports */ 3445 if (hw->mac.type >= e1000_82580) 3446 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3447 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3448 &eeprom_data); 3449 else if (hw->bus.func == 1) 3450 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3451 3452 if (eeprom_data & IGB_EEPROM_APME) 3453 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3454 3455 /* now that we have the eeprom settings, apply the special cases where 3456 * the eeprom may be wrong or the board simply won't support wake on 3457 * lan on a particular port 3458 */ 3459 switch (pdev->device) { 3460 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3461 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3462 break; 3463 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3464 case E1000_DEV_ID_82576_FIBER: 3465 case E1000_DEV_ID_82576_SERDES: 3466 /* Wake events only supported on port A for dual fiber 3467 * regardless of eeprom setting 3468 */ 3469 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3470 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3471 break; 3472 case E1000_DEV_ID_82576_QUAD_COPPER: 3473 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3474 /* if quad port adapter, disable WoL on all but port A */ 3475 if (global_quad_port_a != 0) 3476 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3477 else 3478 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3479 /* Reset for multiple quad port adapters */ 3480 if (++global_quad_port_a == 4) 3481 global_quad_port_a = 0; 3482 break; 3483 default: 3484 /* If the device can't wake, don't set software support */ 3485 if (!device_can_wakeup(&adapter->pdev->dev)) 3486 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3487 } 3488 3489 /* initialize the wol settings based on the eeprom settings */ 3490 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3491 adapter->wol |= E1000_WUFC_MAG; 3492 3493 /* Some vendors want WoL disabled by default, but still supported */ 3494 if ((hw->mac.type == e1000_i350) && 3495 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3496 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3497 adapter->wol = 0; 3498 } 3499 3500 /* Some vendors want the ability to Use the EEPROM setting as 3501 * enable/disable only, and not for capability 3502 */ 3503 if (((hw->mac.type == e1000_i350) || 3504 (hw->mac.type == e1000_i354)) && 3505 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3506 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3507 adapter->wol = 0; 3508 } 3509 if (hw->mac.type == e1000_i350) { 3510 if (((pdev->subsystem_device == 0x5001) || 3511 (pdev->subsystem_device == 0x5002)) && 3512 (hw->bus.func == 0)) { 3513 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3514 adapter->wol = 0; 3515 } 3516 if (pdev->subsystem_device == 0x1F52) 3517 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3518 } 3519 3520 device_set_wakeup_enable(&adapter->pdev->dev, 3521 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3522 3523 /* reset the hardware with the new settings */ 3524 igb_reset(adapter); 3525 3526 /* Init the I2C interface */ 3527 err = igb_init_i2c(adapter); 3528 if (err) { 3529 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3530 goto err_eeprom; 3531 } 3532 3533 /* let the f/w know that the h/w is now under the control of the 3534 * driver. 3535 */ 3536 igb_get_hw_control(adapter); 3537 3538 strcpy(netdev->name, "eth%d"); 3539 err = register_netdev(netdev); 3540 if (err) 3541 goto err_register; 3542 3543 /* carrier off reporting is important to ethtool even BEFORE open */ 3544 netif_carrier_off(netdev); 3545 3546#ifdef CONFIG_IGB_DCA 3547 if (dca_add_requester(&pdev->dev) == 0) { 3548 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3549 dev_info(&pdev->dev, "DCA enabled\n"); 3550 igb_setup_dca(adapter); 3551 } 3552 3553#endif 3554#ifdef CONFIG_IGB_HWMON 3555 /* Initialize the thermal sensor on i350 devices. */ 3556 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3557 u16 ets_word; 3558 3559 /* Read the NVM to determine if this i350 device supports an 3560 * external thermal sensor. 3561 */ 3562 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3563 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3564 adapter->ets = true; 3565 else 3566 adapter->ets = false; 3567 /* Only enable I2C bit banging if an external thermal 3568 * sensor is supported. 3569 */ 3570 if (adapter->ets) 3571 igb_set_i2c_bb(hw); 3572 hw->mac.ops.init_thermal_sensor_thresh(hw); 3573 if (igb_sysfs_init(adapter)) 3574 dev_err(&pdev->dev, 3575 "failed to allocate sysfs resources\n"); 3576 } else { 3577 adapter->ets = false; 3578 } 3579#endif 3580 /* Check if Media Autosense is enabled */ 3581 adapter->ei = *ei; 3582 if (hw->dev_spec._82575.mas_capable) 3583 igb_init_mas(adapter); 3584 3585 /* do hw tstamp init after resetting */ 3586 igb_ptp_init(adapter); 3587 3588 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3589 /* print bus type/speed/width info, not applicable to i354 */ 3590 if (hw->mac.type != e1000_i354) { 3591 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3592 netdev->name, 3593 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3594 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3595 "unknown"), 3596 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3597 "Width x4" : 3598 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3599 "Width x2" : 3600 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3601 "Width x1" : "unknown"), netdev->dev_addr); 3602 } 3603 3604 if ((hw->mac.type == e1000_82576 && 3605 rd32(E1000_EECD) & E1000_EECD_PRES) || 3606 (hw->mac.type >= e1000_i210 || 3607 igb_get_flash_presence_i210(hw))) { 3608 ret_val = igb_read_part_string(hw, part_str, 3609 E1000_PBANUM_LENGTH); 3610 } else { 3611 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3612 } 3613 3614 if (ret_val) 3615 strcpy(part_str, "Unknown"); 3616 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3617 dev_info(&pdev->dev, 3618 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3619 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3620 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3621 adapter->num_rx_queues, adapter->num_tx_queues); 3622 if (hw->phy.media_type == e1000_media_type_copper) { 3623 switch (hw->mac.type) { 3624 case e1000_i350: 3625 case e1000_i210: 3626 case e1000_i211: 3627 /* Enable EEE for internal copper PHY devices */ 3628 err = igb_set_eee_i350(hw, true, true); 3629 if ((!err) && 3630 (!hw->dev_spec._82575.eee_disable)) { 3631 adapter->eee_advert = 3632 MDIO_EEE_100TX | MDIO_EEE_1000T; 3633 adapter->flags |= IGB_FLAG_EEE; 3634 } 3635 break; 3636 case e1000_i354: 3637 if ((rd32(E1000_CTRL_EXT) & 3638 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3639 err = igb_set_eee_i354(hw, true, true); 3640 if ((!err) && 3641 (!hw->dev_spec._82575.eee_disable)) { 3642 adapter->eee_advert = 3643 MDIO_EEE_100TX | MDIO_EEE_1000T; 3644 adapter->flags |= IGB_FLAG_EEE; 3645 } 3646 } 3647 break; 3648 default: 3649 break; 3650 } 3651 } 3652 3653 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3654 3655 pm_runtime_put_noidle(&pdev->dev); 3656 return 0; 3657 3658err_register: 3659 igb_release_hw_control(adapter); 3660 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3661err_eeprom: 3662 if (!igb_check_reset_block(hw)) 3663 igb_reset_phy(hw); 3664 3665 if (hw->flash_address) 3666 iounmap(hw->flash_address); 3667err_sw_init: 3668 kfree(adapter->mac_table); 3669 kfree(adapter->shadow_vfta); 3670 igb_clear_interrupt_scheme(adapter); 3671#ifdef CONFIG_PCI_IOV 3672 igb_disable_sriov(pdev, false); 3673#endif 3674 pci_iounmap(pdev, adapter->io_addr); 3675err_ioremap: 3676 free_netdev(netdev); 3677err_alloc_etherdev: 3678 pci_release_mem_regions(pdev); 3679err_pci_reg: 3680err_dma: 3681 pci_disable_device(pdev); 3682 return err; 3683} 3684 3685#ifdef CONFIG_PCI_IOV 3686static int igb_sriov_reinit(struct pci_dev *dev) 3687{ 3688 struct net_device *netdev = pci_get_drvdata(dev); 3689 struct igb_adapter *adapter = netdev_priv(netdev); 3690 struct pci_dev *pdev = adapter->pdev; 3691 3692 rtnl_lock(); 3693 3694 if (netif_running(netdev)) 3695 igb_close(netdev); 3696 else 3697 igb_reset(adapter); 3698 3699 igb_clear_interrupt_scheme(adapter); 3700 3701 igb_init_queue_configuration(adapter); 3702 3703 if (igb_init_interrupt_scheme(adapter, true)) { 3704 rtnl_unlock(); 3705 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3706 return -ENOMEM; 3707 } 3708 3709 if (netif_running(netdev)) 3710 igb_open(netdev); 3711 3712 rtnl_unlock(); 3713 3714 return 0; 3715} 3716 3717static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3718{ 3719 struct net_device *netdev = pci_get_drvdata(pdev); 3720 struct igb_adapter *adapter = netdev_priv(netdev); 3721 struct e1000_hw *hw = &adapter->hw; 3722 unsigned long flags; 3723 3724 /* reclaim resources allocated to VFs */ 3725 if (adapter->vf_data) { 3726 /* disable iov and allow time for transactions to clear */ 3727 if (pci_vfs_assigned(pdev)) { 3728 dev_warn(&pdev->dev, 3729 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3730 return -EPERM; 3731 } else { 3732 pci_disable_sriov(pdev); 3733 msleep(500); 3734 } 3735 spin_lock_irqsave(&adapter->vfs_lock, flags); 3736 kfree(adapter->vf_mac_list); 3737 adapter->vf_mac_list = NULL; 3738 kfree(adapter->vf_data); 3739 adapter->vf_data = NULL; 3740 adapter->vfs_allocated_count = 0; 3741 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3742 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3743 wrfl(); 3744 msleep(100); 3745 dev_info(&pdev->dev, "IOV Disabled\n"); 3746 3747 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3748 adapter->flags |= IGB_FLAG_DMAC; 3749 } 3750 3751 return reinit ? igb_sriov_reinit(pdev) : 0; 3752} 3753 3754static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3755{ 3756 struct net_device *netdev = pci_get_drvdata(pdev); 3757 struct igb_adapter *adapter = netdev_priv(netdev); 3758 int old_vfs = pci_num_vf(pdev); 3759 struct vf_mac_filter *mac_list; 3760 int err = 0; 3761 int num_vf_mac_filters, i; 3762 3763 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3764 err = -EPERM; 3765 goto out; 3766 } 3767 if (!num_vfs) 3768 goto out; 3769 3770 if (old_vfs) { 3771 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3772 old_vfs, max_vfs); 3773 adapter->vfs_allocated_count = old_vfs; 3774 } else 3775 adapter->vfs_allocated_count = num_vfs; 3776 3777 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3778 sizeof(struct vf_data_storage), GFP_KERNEL); 3779 3780 /* if allocation failed then we do not support SR-IOV */ 3781 if (!adapter->vf_data) { 3782 adapter->vfs_allocated_count = 0; 3783 err = -ENOMEM; 3784 goto out; 3785 } 3786 3787 /* Due to the limited number of RAR entries calculate potential 3788 * number of MAC filters available for the VFs. Reserve entries 3789 * for PF default MAC, PF MAC filters and at least one RAR entry 3790 * for each VF for VF MAC. 3791 */ 3792 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3793 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3794 adapter->vfs_allocated_count); 3795 3796 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3797 sizeof(struct vf_mac_filter), 3798 GFP_KERNEL); 3799 3800 mac_list = adapter->vf_mac_list; 3801 INIT_LIST_HEAD(&adapter->vf_macs.l); 3802 3803 if (adapter->vf_mac_list) { 3804 /* Initialize list of VF MAC filters */ 3805 for (i = 0; i < num_vf_mac_filters; i++) { 3806 mac_list->vf = -1; 3807 mac_list->free = true; 3808 list_add(&mac_list->l, &adapter->vf_macs.l); 3809 mac_list++; 3810 } 3811 } else { 3812 /* If we could not allocate memory for the VF MAC filters 3813 * we can continue without this feature but warn user. 3814 */ 3815 dev_err(&pdev->dev, 3816 "Unable to allocate memory for VF MAC filter list\n"); 3817 } 3818 3819 dev_info(&pdev->dev, "%d VFs allocated\n", 3820 adapter->vfs_allocated_count); 3821 for (i = 0; i < adapter->vfs_allocated_count; i++) 3822 igb_vf_configure(adapter, i); 3823 3824 /* DMA Coalescing is not supported in IOV mode. */ 3825 adapter->flags &= ~IGB_FLAG_DMAC; 3826 3827 if (reinit) { 3828 err = igb_sriov_reinit(pdev); 3829 if (err) 3830 goto err_out; 3831 } 3832 3833 /* only call pci_enable_sriov() if no VFs are allocated already */ 3834 if (!old_vfs) { 3835 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3836 if (err) 3837 goto err_out; 3838 } 3839 3840 goto out; 3841 3842err_out: 3843 kfree(adapter->vf_mac_list); 3844 adapter->vf_mac_list = NULL; 3845 kfree(adapter->vf_data); 3846 adapter->vf_data = NULL; 3847 adapter->vfs_allocated_count = 0; 3848out: 3849 return err; 3850} 3851 3852#endif 3853/** 3854 * igb_remove_i2c - Cleanup I2C interface 3855 * @adapter: pointer to adapter structure 3856 **/ 3857static void igb_remove_i2c(struct igb_adapter *adapter) 3858{ 3859 /* free the adapter bus structure */ 3860 i2c_del_adapter(&adapter->i2c_adap); 3861} 3862 3863/** 3864 * igb_remove - Device Removal Routine 3865 * @pdev: PCI device information struct 3866 * 3867 * igb_remove is called by the PCI subsystem to alert the driver 3868 * that it should release a PCI device. The could be caused by a 3869 * Hot-Plug event, or because the driver is going to be removed from 3870 * memory. 3871 **/ 3872static void igb_remove(struct pci_dev *pdev) 3873{ 3874 struct net_device *netdev = pci_get_drvdata(pdev); 3875 struct igb_adapter *adapter = netdev_priv(netdev); 3876 struct e1000_hw *hw = &adapter->hw; 3877 3878 pm_runtime_get_noresume(&pdev->dev); 3879#ifdef CONFIG_IGB_HWMON 3880 igb_sysfs_exit(adapter); 3881#endif 3882 igb_remove_i2c(adapter); 3883 igb_ptp_stop(adapter); 3884 /* The watchdog timer may be rescheduled, so explicitly 3885 * disable watchdog from being rescheduled. 3886 */ 3887 set_bit(__IGB_DOWN, &adapter->state); 3888 timer_delete_sync(&adapter->watchdog_timer); 3889 timer_delete_sync(&adapter->phy_info_timer); 3890 3891 cancel_work_sync(&adapter->reset_task); 3892 cancel_work_sync(&adapter->watchdog_task); 3893 3894#ifdef CONFIG_IGB_DCA 3895 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3896 dev_info(&pdev->dev, "DCA disabled\n"); 3897 dca_remove_requester(&pdev->dev); 3898 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3899 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3900 } 3901#endif 3902 3903 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3904 * would have already happened in close and is redundant. 3905 */ 3906 igb_release_hw_control(adapter); 3907 3908#ifdef CONFIG_PCI_IOV 3909 igb_disable_sriov(pdev, false); 3910#endif 3911 3912 unregister_netdev(netdev); 3913 3914 igb_clear_interrupt_scheme(adapter); 3915 3916 pci_iounmap(pdev, adapter->io_addr); 3917 if (hw->flash_address) 3918 iounmap(hw->flash_address); 3919 pci_release_mem_regions(pdev); 3920 3921 kfree(adapter->mac_table); 3922 kfree(adapter->shadow_vfta); 3923 free_netdev(netdev); 3924 3925 pci_disable_device(pdev); 3926} 3927 3928/** 3929 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3930 * @adapter: board private structure to initialize 3931 * 3932 * This function initializes the vf specific data storage and then attempts to 3933 * allocate the VFs. The reason for ordering it this way is because it is much 3934 * more expensive time wise to disable SR-IOV than it is to allocate and free 3935 * the memory for the VFs. 3936 **/ 3937static void igb_probe_vfs(struct igb_adapter *adapter) 3938{ 3939#ifdef CONFIG_PCI_IOV 3940 struct pci_dev *pdev = adapter->pdev; 3941 struct e1000_hw *hw = &adapter->hw; 3942 3943 /* Virtualization features not supported on i210 and 82580 family. */ 3944 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3945 (hw->mac.type == e1000_82580)) 3946 return; 3947 3948 /* Of the below we really only want the effect of getting 3949 * IGB_FLAG_HAS_MSIX set (if available), without which 3950 * igb_enable_sriov() has no effect. 3951 */ 3952 igb_set_interrupt_capability(adapter, true); 3953 igb_reset_interrupt_capability(adapter); 3954 3955 pci_sriov_set_totalvfs(pdev, 7); 3956 igb_enable_sriov(pdev, max_vfs, false); 3957 3958#endif /* CONFIG_PCI_IOV */ 3959} 3960 3961unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3962{ 3963 struct e1000_hw *hw = &adapter->hw; 3964 unsigned int max_rss_queues; 3965 3966 /* Determine the maximum number of RSS queues supported. */ 3967 switch (hw->mac.type) { 3968 case e1000_i211: 3969 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3970 break; 3971 case e1000_82575: 3972 case e1000_i210: 3973 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3974 break; 3975 case e1000_i350: 3976 /* I350 cannot do RSS and SR-IOV at the same time */ 3977 if (!!adapter->vfs_allocated_count) { 3978 max_rss_queues = 1; 3979 break; 3980 } 3981 fallthrough; 3982 case e1000_82576: 3983 if (!!adapter->vfs_allocated_count) { 3984 max_rss_queues = 2; 3985 break; 3986 } 3987 fallthrough; 3988 case e1000_82580: 3989 case e1000_i354: 3990 default: 3991 max_rss_queues = IGB_MAX_RX_QUEUES; 3992 break; 3993 } 3994 3995 return max_rss_queues; 3996} 3997 3998static void igb_init_queue_configuration(struct igb_adapter *adapter) 3999{ 4000 u32 max_rss_queues; 4001 4002 max_rss_queues = igb_get_max_rss_queues(adapter); 4003 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 4004 4005 igb_set_flag_queue_pairs(adapter, max_rss_queues); 4006} 4007 4008void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 4009 const u32 max_rss_queues) 4010{ 4011 struct e1000_hw *hw = &adapter->hw; 4012 4013 /* Determine if we need to pair queues. */ 4014 switch (hw->mac.type) { 4015 case e1000_82575: 4016 case e1000_i211: 4017 /* Device supports enough interrupts without queue pairing. */ 4018 break; 4019 case e1000_82576: 4020 case e1000_82580: 4021 case e1000_i350: 4022 case e1000_i354: 4023 case e1000_i210: 4024 default: 4025 /* If rss_queues > half of max_rss_queues, pair the queues in 4026 * order to conserve interrupts due to limited supply. 4027 */ 4028 if (adapter->rss_queues > (max_rss_queues / 2)) 4029 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4030 else 4031 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4032 break; 4033 } 4034} 4035 4036/** 4037 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4038 * @adapter: board private structure to initialize 4039 * 4040 * igb_sw_init initializes the Adapter private data structure. 4041 * Fields are initialized based on PCI device information and 4042 * OS network device settings (MTU size). 4043 **/ 4044static int igb_sw_init(struct igb_adapter *adapter) 4045{ 4046 struct e1000_hw *hw = &adapter->hw; 4047 struct net_device *netdev = adapter->netdev; 4048 struct pci_dev *pdev = adapter->pdev; 4049 4050 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4051 4052 /* set default ring sizes */ 4053 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4054 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4055 4056 /* set default ITR values */ 4057 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4058 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4059 4060 /* set default work limits */ 4061 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4062 4063 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4064 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4065 4066 spin_lock_init(&adapter->nfc_lock); 4067 spin_lock_init(&adapter->stats64_lock); 4068 4069 /* init spinlock to avoid concurrency of VF resources */ 4070 spin_lock_init(&adapter->vfs_lock); 4071#ifdef CONFIG_PCI_IOV 4072 switch (hw->mac.type) { 4073 case e1000_82576: 4074 case e1000_i350: 4075 if (max_vfs > 7) { 4076 dev_warn(&pdev->dev, 4077 "Maximum of 7 VFs per PF, using max\n"); 4078 max_vfs = adapter->vfs_allocated_count = 7; 4079 } else 4080 adapter->vfs_allocated_count = max_vfs; 4081 if (adapter->vfs_allocated_count) 4082 dev_warn(&pdev->dev, 4083 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4084 break; 4085 default: 4086 break; 4087 } 4088#endif /* CONFIG_PCI_IOV */ 4089 4090 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4091 adapter->flags |= IGB_FLAG_HAS_MSIX; 4092 4093 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4094 sizeof(struct igb_mac_addr), 4095 GFP_KERNEL); 4096 if (!adapter->mac_table) 4097 return -ENOMEM; 4098 4099 igb_probe_vfs(adapter); 4100 4101 igb_init_queue_configuration(adapter); 4102 4103 /* Setup and initialize a copy of the hw vlan table array */ 4104 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4105 GFP_KERNEL); 4106 if (!adapter->shadow_vfta) 4107 return -ENOMEM; 4108 4109 /* This call may decrease the number of queues */ 4110 if (igb_init_interrupt_scheme(adapter, true)) { 4111 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4112 return -ENOMEM; 4113 } 4114 4115 /* Explicitly disable IRQ since the NIC can be in any state. */ 4116 igb_irq_disable(adapter); 4117 4118 if (hw->mac.type >= e1000_i350) 4119 adapter->flags &= ~IGB_FLAG_DMAC; 4120 4121 set_bit(__IGB_DOWN, &adapter->state); 4122 return 0; 4123} 4124 4125/** 4126 * __igb_open - Called when a network interface is made active 4127 * @netdev: network interface device structure 4128 * @resuming: indicates whether we are in a resume call 4129 * 4130 * Returns 0 on success, negative value on failure 4131 * 4132 * The open entry point is called when a network interface is made 4133 * active by the system (IFF_UP). At this point all resources needed 4134 * for transmit and receive operations are allocated, the interrupt 4135 * handler is registered with the OS, the watchdog timer is started, 4136 * and the stack is notified that the interface is ready. 4137 **/ 4138static int __igb_open(struct net_device *netdev, bool resuming) 4139{ 4140 struct igb_adapter *adapter = netdev_priv(netdev); 4141 struct pci_dev *pdev = adapter->pdev; 4142 struct e1000_hw *hw = &adapter->hw; 4143 struct napi_struct *napi; 4144 int err; 4145 int i; 4146 4147 /* disallow open during test */ 4148 if (test_bit(__IGB_TESTING, &adapter->state)) { 4149 WARN_ON(resuming); 4150 return -EBUSY; 4151 } 4152 4153 if (!resuming) 4154 pm_runtime_get_sync(&pdev->dev); 4155 4156 netif_carrier_off(netdev); 4157 4158 /* allocate transmit descriptors */ 4159 err = igb_setup_all_tx_resources(adapter); 4160 if (err) 4161 goto err_setup_tx; 4162 4163 /* allocate receive descriptors */ 4164 err = igb_setup_all_rx_resources(adapter); 4165 if (err) 4166 goto err_setup_rx; 4167 4168 igb_power_up_link(adapter); 4169 4170 /* before we allocate an interrupt, we must be ready to handle it. 4171 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4172 * as soon as we call pci_request_irq, so we have to setup our 4173 * clean_rx handler before we do so. 4174 */ 4175 igb_configure(adapter); 4176 4177 err = igb_request_irq(adapter); 4178 if (err) 4179 goto err_req_irq; 4180 4181 /* Notify the stack of the actual queue counts. */ 4182 err = netif_set_real_num_tx_queues(adapter->netdev, 4183 adapter->num_tx_queues); 4184 if (err) 4185 goto err_set_queues; 4186 4187 err = netif_set_real_num_rx_queues(adapter->netdev, 4188 adapter->num_rx_queues); 4189 if (err) 4190 goto err_set_queues; 4191 4192 /* From here on the code is the same as igb_up() */ 4193 clear_bit(__IGB_DOWN, &adapter->state); 4194 4195 for (i = 0; i < adapter->num_q_vectors; i++) { 4196 napi = &adapter->q_vector[i]->napi; 4197 napi_enable(napi); 4198 igb_set_queue_napi(adapter, i, napi); 4199 } 4200 4201 /* Clear any pending interrupts. */ 4202 rd32(E1000_TSICR); 4203 rd32(E1000_ICR); 4204 4205 igb_irq_enable(adapter); 4206 4207 /* notify VFs that reset has been completed */ 4208 if (adapter->vfs_allocated_count) { 4209 u32 reg_data = rd32(E1000_CTRL_EXT); 4210 4211 reg_data |= E1000_CTRL_EXT_PFRSTD; 4212 wr32(E1000_CTRL_EXT, reg_data); 4213 } 4214 4215 netif_tx_start_all_queues(netdev); 4216 4217 if (!resuming) 4218 pm_runtime_put(&pdev->dev); 4219 4220 /* start the watchdog. */ 4221 hw->mac.get_link_status = 1; 4222 schedule_work(&adapter->watchdog_task); 4223 4224 return 0; 4225 4226err_set_queues: 4227 igb_free_irq(adapter); 4228err_req_irq: 4229 igb_release_hw_control(adapter); 4230 igb_power_down_link(adapter); 4231 igb_free_all_rx_resources(adapter); 4232err_setup_rx: 4233 igb_free_all_tx_resources(adapter); 4234err_setup_tx: 4235 igb_reset(adapter); 4236 if (!resuming) 4237 pm_runtime_put(&pdev->dev); 4238 4239 return err; 4240} 4241 4242int igb_open(struct net_device *netdev) 4243{ 4244 return __igb_open(netdev, false); 4245} 4246 4247/** 4248 * __igb_close - Disables a network interface 4249 * @netdev: network interface device structure 4250 * @suspending: indicates we are in a suspend call 4251 * 4252 * Returns 0, this is not allowed to fail 4253 * 4254 * The close entry point is called when an interface is de-activated 4255 * by the OS. The hardware is still under the driver's control, but 4256 * needs to be disabled. A global MAC reset is issued to stop the 4257 * hardware, and all transmit and receive resources are freed. 4258 **/ 4259static int __igb_close(struct net_device *netdev, bool suspending) 4260{ 4261 struct igb_adapter *adapter = netdev_priv(netdev); 4262 struct pci_dev *pdev = adapter->pdev; 4263 4264 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4265 4266 if (!suspending) 4267 pm_runtime_get_sync(&pdev->dev); 4268 4269 igb_down(adapter); 4270 igb_free_irq(adapter); 4271 4272 igb_free_all_tx_resources(adapter); 4273 igb_free_all_rx_resources(adapter); 4274 4275 if (!suspending) 4276 pm_runtime_put_sync(&pdev->dev); 4277 return 0; 4278} 4279 4280int igb_close(struct net_device *netdev) 4281{ 4282 if (netif_device_present(netdev) || netdev->dismantle) 4283 return __igb_close(netdev, false); 4284 return 0; 4285} 4286 4287/** 4288 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4289 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4290 * 4291 * Return 0 on success, negative on failure 4292 **/ 4293int igb_setup_tx_resources(struct igb_ring *tx_ring) 4294{ 4295 struct device *dev = tx_ring->dev; 4296 int size; 4297 4298 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4299 4300 tx_ring->tx_buffer_info = vmalloc(size); 4301 if (!tx_ring->tx_buffer_info) 4302 goto err; 4303 4304 /* round up to nearest 4K */ 4305 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4306 tx_ring->size = ALIGN(tx_ring->size, 4096); 4307 4308 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4309 &tx_ring->dma, GFP_KERNEL); 4310 if (!tx_ring->desc) 4311 goto err; 4312 4313 tx_ring->next_to_use = 0; 4314 tx_ring->next_to_clean = 0; 4315 4316 return 0; 4317 4318err: 4319 vfree(tx_ring->tx_buffer_info); 4320 tx_ring->tx_buffer_info = NULL; 4321 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4322 return -ENOMEM; 4323} 4324 4325/** 4326 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4327 * (Descriptors) for all queues 4328 * @adapter: board private structure 4329 * 4330 * Return 0 on success, negative on failure 4331 **/ 4332static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4333{ 4334 struct pci_dev *pdev = adapter->pdev; 4335 int i, err = 0; 4336 4337 for (i = 0; i < adapter->num_tx_queues; i++) { 4338 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4339 if (err) { 4340 dev_err(&pdev->dev, 4341 "Allocation for Tx Queue %u failed\n", i); 4342 for (i--; i >= 0; i--) 4343 igb_free_tx_resources(adapter->tx_ring[i]); 4344 break; 4345 } 4346 } 4347 4348 return err; 4349} 4350 4351/** 4352 * igb_setup_tctl - configure the transmit control registers 4353 * @adapter: Board private structure 4354 **/ 4355void igb_setup_tctl(struct igb_adapter *adapter) 4356{ 4357 struct e1000_hw *hw = &adapter->hw; 4358 u32 tctl; 4359 4360 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4361 wr32(E1000_TXDCTL(0), 0); 4362 4363 /* Program the Transmit Control Register */ 4364 tctl = rd32(E1000_TCTL); 4365 tctl &= ~E1000_TCTL_CT; 4366 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4367 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4368 4369 igb_config_collision_dist(hw); 4370 4371 /* Enable transmits */ 4372 tctl |= E1000_TCTL_EN; 4373 4374 wr32(E1000_TCTL, tctl); 4375} 4376 4377/** 4378 * igb_configure_tx_ring - Configure transmit ring after Reset 4379 * @adapter: board private structure 4380 * @ring: tx ring to configure 4381 * 4382 * Configure a transmit ring after a reset. 4383 **/ 4384void igb_configure_tx_ring(struct igb_adapter *adapter, 4385 struct igb_ring *ring) 4386{ 4387 struct e1000_hw *hw = &adapter->hw; 4388 u32 txdctl = 0; 4389 u64 tdba = ring->dma; 4390 int reg_idx = ring->reg_idx; 4391 4392 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4393 4394 wr32(E1000_TDLEN(reg_idx), 4395 ring->count * sizeof(union e1000_adv_tx_desc)); 4396 wr32(E1000_TDBAL(reg_idx), 4397 tdba & 0x00000000ffffffffULL); 4398 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4399 4400 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4401 wr32(E1000_TDH(reg_idx), 0); 4402 writel(0, ring->tail); 4403 4404 txdctl |= IGB_TX_PTHRESH; 4405 txdctl |= IGB_TX_HTHRESH << 8; 4406 txdctl |= IGB_TX_WTHRESH << 16; 4407 4408 /* reinitialize tx_buffer_info */ 4409 memset(ring->tx_buffer_info, 0, 4410 sizeof(struct igb_tx_buffer) * ring->count); 4411 4412 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4413 wr32(E1000_TXDCTL(reg_idx), txdctl); 4414} 4415 4416/** 4417 * igb_configure_tx - Configure transmit Unit after Reset 4418 * @adapter: board private structure 4419 * 4420 * Configure the Tx unit of the MAC after a reset. 4421 **/ 4422static void igb_configure_tx(struct igb_adapter *adapter) 4423{ 4424 struct e1000_hw *hw = &adapter->hw; 4425 int i; 4426 4427 /* disable the queues */ 4428 for (i = 0; i < adapter->num_tx_queues; i++) 4429 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4430 4431 wrfl(); 4432 usleep_range(10000, 20000); 4433 4434 for (i = 0; i < adapter->num_tx_queues; i++) 4435 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4436} 4437 4438/** 4439 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4440 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4441 * 4442 * Returns 0 on success, negative on failure 4443 **/ 4444int igb_setup_rx_resources(struct igb_ring *rx_ring) 4445{ 4446 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4447 struct device *dev = rx_ring->dev; 4448 int size, res; 4449 4450 /* XDP RX-queue info */ 4451 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4452 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4453 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4454 rx_ring->queue_index, 0); 4455 if (res < 0) { 4456 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4457 rx_ring->queue_index); 4458 return res; 4459 } 4460 4461 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4462 4463 rx_ring->rx_buffer_info = vmalloc(size); 4464 if (!rx_ring->rx_buffer_info) 4465 goto err; 4466 4467 /* Round up to nearest 4K */ 4468 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4469 rx_ring->size = ALIGN(rx_ring->size, 4096); 4470 4471 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4472 &rx_ring->dma, GFP_KERNEL); 4473 if (!rx_ring->desc) 4474 goto err; 4475 4476 rx_ring->next_to_alloc = 0; 4477 rx_ring->next_to_clean = 0; 4478 rx_ring->next_to_use = 0; 4479 4480 rx_ring->xdp_prog = adapter->xdp_prog; 4481 4482 return 0; 4483 4484err: 4485 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4486 vfree(rx_ring->rx_buffer_info); 4487 rx_ring->rx_buffer_info = NULL; 4488 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4489 return -ENOMEM; 4490} 4491 4492/** 4493 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4494 * (Descriptors) for all queues 4495 * @adapter: board private structure 4496 * 4497 * Return 0 on success, negative on failure 4498 **/ 4499static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4500{ 4501 struct pci_dev *pdev = adapter->pdev; 4502 int i, err = 0; 4503 4504 for (i = 0; i < adapter->num_rx_queues; i++) { 4505 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4506 if (err) { 4507 dev_err(&pdev->dev, 4508 "Allocation for Rx Queue %u failed\n", i); 4509 for (i--; i >= 0; i--) 4510 igb_free_rx_resources(adapter->rx_ring[i]); 4511 break; 4512 } 4513 } 4514 4515 return err; 4516} 4517 4518/** 4519 * igb_setup_mrqc - configure the multiple receive queue control registers 4520 * @adapter: Board private structure 4521 **/ 4522static void igb_setup_mrqc(struct igb_adapter *adapter) 4523{ 4524 struct e1000_hw *hw = &adapter->hw; 4525 u32 mrqc, rxcsum; 4526 u32 j, num_rx_queues; 4527 u32 rss_key[10]; 4528 4529 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4530 for (j = 0; j < 10; j++) 4531 wr32(E1000_RSSRK(j), rss_key[j]); 4532 4533 num_rx_queues = adapter->rss_queues; 4534 4535 switch (hw->mac.type) { 4536 case e1000_82576: 4537 /* 82576 supports 2 RSS queues for SR-IOV */ 4538 if (adapter->vfs_allocated_count) 4539 num_rx_queues = 2; 4540 break; 4541 default: 4542 break; 4543 } 4544 4545 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4546 for (j = 0; j < IGB_RETA_SIZE; j++) 4547 adapter->rss_indir_tbl[j] = 4548 (j * num_rx_queues) / IGB_RETA_SIZE; 4549 adapter->rss_indir_tbl_init = num_rx_queues; 4550 } 4551 igb_write_rss_indir_tbl(adapter); 4552 4553 /* Disable raw packet checksumming so that RSS hash is placed in 4554 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4555 * offloads as they are enabled by default 4556 */ 4557 rxcsum = rd32(E1000_RXCSUM); 4558 rxcsum |= E1000_RXCSUM_PCSD; 4559 4560 if (adapter->hw.mac.type >= e1000_82576) 4561 /* Enable Receive Checksum Offload for SCTP */ 4562 rxcsum |= E1000_RXCSUM_CRCOFL; 4563 4564 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4565 wr32(E1000_RXCSUM, rxcsum); 4566 4567 /* Generate RSS hash based on packet types, TCP/UDP 4568 * port numbers and/or IPv4/v6 src and dst addresses 4569 */ 4570 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4571 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4572 E1000_MRQC_RSS_FIELD_IPV6 | 4573 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4574 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4575 4576 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4577 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4578 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4579 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4580 4581 /* If VMDq is enabled then we set the appropriate mode for that, else 4582 * we default to RSS so that an RSS hash is calculated per packet even 4583 * if we are only using one queue 4584 */ 4585 if (adapter->vfs_allocated_count) { 4586 if (hw->mac.type > e1000_82575) { 4587 /* Set the default pool for the PF's first queue */ 4588 u32 vtctl = rd32(E1000_VT_CTL); 4589 4590 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4591 E1000_VT_CTL_DISABLE_DEF_POOL); 4592 vtctl |= adapter->vfs_allocated_count << 4593 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4594 wr32(E1000_VT_CTL, vtctl); 4595 } 4596 if (adapter->rss_queues > 1) 4597 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4598 else 4599 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4600 } else { 4601 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4602 } 4603 igb_vmm_control(adapter); 4604 4605 wr32(E1000_MRQC, mrqc); 4606} 4607 4608/** 4609 * igb_setup_rctl - configure the receive control registers 4610 * @adapter: Board private structure 4611 **/ 4612void igb_setup_rctl(struct igb_adapter *adapter) 4613{ 4614 struct e1000_hw *hw = &adapter->hw; 4615 u32 rctl; 4616 4617 rctl = rd32(E1000_RCTL); 4618 4619 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4620 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4621 4622 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4623 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4624 4625 /* enable stripping of CRC. It's unlikely this will break BMC 4626 * redirection as it did with e1000. Newer features require 4627 * that the HW strips the CRC. 4628 */ 4629 rctl |= E1000_RCTL_SECRC; 4630 4631 /* disable store bad packets and clear size bits. */ 4632 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4633 4634 /* enable LPE to allow for reception of jumbo frames */ 4635 rctl |= E1000_RCTL_LPE; 4636 4637 /* disable queue 0 to prevent tail write w/o re-config */ 4638 wr32(E1000_RXDCTL(0), 0); 4639 4640 /* Attention!!! For SR-IOV PF driver operations you must enable 4641 * queue drop for all VF and PF queues to prevent head of line blocking 4642 * if an un-trusted VF does not provide descriptors to hardware. 4643 */ 4644 if (adapter->vfs_allocated_count) { 4645 /* set all queue drop enable bits */ 4646 wr32(E1000_QDE, ALL_QUEUES); 4647 } 4648 4649 /* This is useful for sniffing bad packets. */ 4650 if (adapter->netdev->features & NETIF_F_RXALL) { 4651 /* UPE and MPE will be handled by normal PROMISC logic 4652 * in e1000e_set_rx_mode 4653 */ 4654 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4655 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4656 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4657 4658 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4659 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4660 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4661 * and that breaks VLANs. 4662 */ 4663 } 4664 4665 wr32(E1000_RCTL, rctl); 4666} 4667 4668static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4669 int vfn) 4670{ 4671 struct e1000_hw *hw = &adapter->hw; 4672 u32 vmolr; 4673 4674 if (size > MAX_JUMBO_FRAME_SIZE) 4675 size = MAX_JUMBO_FRAME_SIZE; 4676 4677 vmolr = rd32(E1000_VMOLR(vfn)); 4678 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4679 vmolr |= size | E1000_VMOLR_LPE; 4680 wr32(E1000_VMOLR(vfn), vmolr); 4681 4682 return 0; 4683} 4684 4685static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4686 int vfn, bool enable) 4687{ 4688 struct e1000_hw *hw = &adapter->hw; 4689 u32 val, reg; 4690 4691 if (hw->mac.type < e1000_82576) 4692 return; 4693 4694 if (hw->mac.type == e1000_i350) 4695 reg = E1000_DVMOLR(vfn); 4696 else 4697 reg = E1000_VMOLR(vfn); 4698 4699 val = rd32(reg); 4700 if (enable) 4701 val |= E1000_VMOLR_STRVLAN; 4702 else 4703 val &= ~(E1000_VMOLR_STRVLAN); 4704 wr32(reg, val); 4705} 4706 4707static inline void igb_set_vmolr(struct igb_adapter *adapter, 4708 int vfn, bool aupe) 4709{ 4710 struct e1000_hw *hw = &adapter->hw; 4711 u32 vmolr; 4712 4713 /* This register exists only on 82576 and newer so if we are older then 4714 * we should exit and do nothing 4715 */ 4716 if (hw->mac.type < e1000_82576) 4717 return; 4718 4719 vmolr = rd32(E1000_VMOLR(vfn)); 4720 if (aupe) 4721 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4722 else 4723 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4724 4725 /* clear all bits that might not be set */ 4726 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4727 4728 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4729 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4730 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4731 * multicast packets 4732 */ 4733 if (vfn <= adapter->vfs_allocated_count) 4734 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4735 4736 wr32(E1000_VMOLR(vfn), vmolr); 4737} 4738 4739/** 4740 * igb_setup_srrctl - configure the split and replication receive control 4741 * registers 4742 * @adapter: Board private structure 4743 * @ring: receive ring to be configured 4744 **/ 4745void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4746{ 4747 struct e1000_hw *hw = &adapter->hw; 4748 int reg_idx = ring->reg_idx; 4749 u32 srrctl = 0; 4750 u32 buf_size; 4751 4752 if (ring->xsk_pool) 4753 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4754 else if (ring_uses_large_buffer(ring)) 4755 buf_size = IGB_RXBUFFER_3072; 4756 else 4757 buf_size = IGB_RXBUFFER_2048; 4758 4759 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4760 srrctl |= buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4761 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4762 if (hw->mac.type >= e1000_82580) 4763 srrctl |= E1000_SRRCTL_TIMESTAMP; 4764 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4765 * queues and rx flow control is disabled 4766 */ 4767 if (adapter->vfs_allocated_count || 4768 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4769 adapter->num_rx_queues > 1)) 4770 srrctl |= E1000_SRRCTL_DROP_EN; 4771 4772 wr32(E1000_SRRCTL(reg_idx), srrctl); 4773} 4774 4775/** 4776 * igb_configure_rx_ring - Configure a receive ring after Reset 4777 * @adapter: board private structure 4778 * @ring: receive ring to be configured 4779 * 4780 * Configure the Rx unit of the MAC after a reset. 4781 **/ 4782void igb_configure_rx_ring(struct igb_adapter *adapter, 4783 struct igb_ring *ring) 4784{ 4785 struct e1000_hw *hw = &adapter->hw; 4786 union e1000_adv_rx_desc *rx_desc; 4787 u64 rdba = ring->dma; 4788 int reg_idx = ring->reg_idx; 4789 u32 rxdctl = 0; 4790 4791 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4792 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4793 if (ring->xsk_pool) { 4794 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4795 MEM_TYPE_XSK_BUFF_POOL, 4796 NULL)); 4797 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4798 } else { 4799 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4800 MEM_TYPE_PAGE_SHARED, 4801 NULL)); 4802 } 4803 4804 /* disable the queue */ 4805 wr32(E1000_RXDCTL(reg_idx), 0); 4806 4807 /* Set DMA base address registers */ 4808 wr32(E1000_RDBAL(reg_idx), 4809 rdba & 0x00000000ffffffffULL); 4810 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4811 wr32(E1000_RDLEN(reg_idx), 4812 ring->count * sizeof(union e1000_adv_rx_desc)); 4813 4814 /* initialize head and tail */ 4815 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4816 wr32(E1000_RDH(reg_idx), 0); 4817 writel(0, ring->tail); 4818 4819 /* set descriptor configuration */ 4820 igb_setup_srrctl(adapter, ring); 4821 4822 /* set filtering for VMDQ pools */ 4823 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4824 4825 rxdctl |= IGB_RX_PTHRESH; 4826 rxdctl |= IGB_RX_HTHRESH << 8; 4827 rxdctl |= IGB_RX_WTHRESH << 16; 4828 4829 if (ring->xsk_pool) 4830 memset(ring->rx_buffer_info_zc, 0, 4831 sizeof(*ring->rx_buffer_info_zc) * ring->count); 4832 else 4833 memset(ring->rx_buffer_info, 0, 4834 sizeof(*ring->rx_buffer_info) * ring->count); 4835 4836 /* initialize Rx descriptor 0 */ 4837 rx_desc = IGB_RX_DESC(ring, 0); 4838 rx_desc->wb.upper.length = 0; 4839 4840 /* enable receive descriptor fetching */ 4841 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4842 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4843} 4844 4845static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4846 struct igb_ring *rx_ring) 4847{ 4848#if (PAGE_SIZE < 8192) 4849 struct e1000_hw *hw = &adapter->hw; 4850#endif 4851 4852 /* set build_skb and buffer size flags */ 4853 clear_ring_build_skb_enabled(rx_ring); 4854 clear_ring_uses_large_buffer(rx_ring); 4855 4856 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4857 return; 4858 4859 set_ring_build_skb_enabled(rx_ring); 4860 4861#if (PAGE_SIZE < 8192) 4862 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4863 IGB_2K_TOO_SMALL_WITH_PADDING || 4864 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4865 set_ring_uses_large_buffer(rx_ring); 4866#endif 4867} 4868 4869/** 4870 * igb_configure_rx - Configure receive Unit after Reset 4871 * @adapter: board private structure 4872 * 4873 * Configure the Rx unit of the MAC after a reset. 4874 **/ 4875static void igb_configure_rx(struct igb_adapter *adapter) 4876{ 4877 int i; 4878 4879 /* set the correct pool for the PF default MAC address in entry 0 */ 4880 igb_set_default_mac_filter(adapter); 4881 4882 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4883 * the Base and Length of the Rx Descriptor Ring 4884 */ 4885 for (i = 0; i < adapter->num_rx_queues; i++) { 4886 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4887 4888 igb_set_rx_buffer_len(adapter, rx_ring); 4889 igb_configure_rx_ring(adapter, rx_ring); 4890 } 4891} 4892 4893/** 4894 * igb_free_tx_resources - Free Tx Resources per Queue 4895 * @tx_ring: Tx descriptor ring for a specific queue 4896 * 4897 * Free all transmit software resources 4898 **/ 4899void igb_free_tx_resources(struct igb_ring *tx_ring) 4900{ 4901 igb_clean_tx_ring(tx_ring); 4902 4903 vfree(tx_ring->tx_buffer_info); 4904 tx_ring->tx_buffer_info = NULL; 4905 4906 /* if not set, then don't free */ 4907 if (!tx_ring->desc) 4908 return; 4909 4910 dma_free_coherent(tx_ring->dev, tx_ring->size, 4911 tx_ring->desc, tx_ring->dma); 4912 4913 tx_ring->desc = NULL; 4914} 4915 4916/** 4917 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4918 * @adapter: board private structure 4919 * 4920 * Free all transmit software resources 4921 **/ 4922static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4923{ 4924 int i; 4925 4926 for (i = 0; i < adapter->num_tx_queues; i++) 4927 if (adapter->tx_ring[i]) 4928 igb_free_tx_resources(adapter->tx_ring[i]); 4929} 4930 4931/** 4932 * igb_clean_tx_ring - Free Tx Buffers 4933 * @tx_ring: ring to be cleaned 4934 **/ 4935void igb_clean_tx_ring(struct igb_ring *tx_ring) 4936{ 4937 u16 i = tx_ring->next_to_clean; 4938 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4939 u32 xsk_frames = 0; 4940 4941 while (i != tx_ring->next_to_use) { 4942 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4943 4944 /* Free all the Tx ring sk_buffs or xdp frames */ 4945 if (tx_buffer->type == IGB_TYPE_SKB) { 4946 dev_kfree_skb_any(tx_buffer->skb); 4947 } else if (tx_buffer->type == IGB_TYPE_XDP) { 4948 xdp_return_frame(tx_buffer->xdpf); 4949 } else if (tx_buffer->type == IGB_TYPE_XSK) { 4950 xsk_frames++; 4951 goto skip_for_xsk; 4952 } 4953 4954 /* unmap skb header data */ 4955 dma_unmap_single(tx_ring->dev, 4956 dma_unmap_addr(tx_buffer, dma), 4957 dma_unmap_len(tx_buffer, len), 4958 DMA_TO_DEVICE); 4959 4960 /* check for eop_desc to determine the end of the packet */ 4961 eop_desc = tx_buffer->next_to_watch; 4962 tx_desc = IGB_TX_DESC(tx_ring, i); 4963 4964 /* unmap remaining buffers */ 4965 while (tx_desc != eop_desc) { 4966 tx_buffer++; 4967 tx_desc++; 4968 i++; 4969 if (unlikely(i == tx_ring->count)) { 4970 i = 0; 4971 tx_buffer = tx_ring->tx_buffer_info; 4972 tx_desc = IGB_TX_DESC(tx_ring, 0); 4973 } 4974 4975 /* unmap any remaining paged data */ 4976 if (dma_unmap_len(tx_buffer, len)) 4977 dma_unmap_page(tx_ring->dev, 4978 dma_unmap_addr(tx_buffer, dma), 4979 dma_unmap_len(tx_buffer, len), 4980 DMA_TO_DEVICE); 4981 } 4982 4983skip_for_xsk: 4984 tx_buffer->next_to_watch = NULL; 4985 4986 /* move us one more past the eop_desc for start of next pkt */ 4987 tx_buffer++; 4988 i++; 4989 if (unlikely(i == tx_ring->count)) { 4990 i = 0; 4991 tx_buffer = tx_ring->tx_buffer_info; 4992 } 4993 } 4994 4995 /* reset BQL for queue */ 4996 netdev_tx_reset_queue(txring_txq(tx_ring)); 4997 4998 if (tx_ring->xsk_pool && xsk_frames) 4999 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 5000 5001 /* reset next_to_use and next_to_clean */ 5002 tx_ring->next_to_use = 0; 5003 tx_ring->next_to_clean = 0; 5004} 5005 5006/** 5007 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 5008 * @adapter: board private structure 5009 **/ 5010static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 5011{ 5012 int i; 5013 5014 for (i = 0; i < adapter->num_tx_queues; i++) 5015 if (adapter->tx_ring[i]) 5016 igb_clean_tx_ring(adapter->tx_ring[i]); 5017} 5018 5019/** 5020 * igb_free_rx_resources - Free Rx Resources 5021 * @rx_ring: ring to clean the resources from 5022 * 5023 * Free all receive software resources 5024 **/ 5025void igb_free_rx_resources(struct igb_ring *rx_ring) 5026{ 5027 igb_clean_rx_ring(rx_ring); 5028 5029 rx_ring->xdp_prog = NULL; 5030 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 5031 if (rx_ring->xsk_pool) { 5032 vfree(rx_ring->rx_buffer_info_zc); 5033 rx_ring->rx_buffer_info_zc = NULL; 5034 } else { 5035 vfree(rx_ring->rx_buffer_info); 5036 rx_ring->rx_buffer_info = NULL; 5037 } 5038 5039 /* if not set, then don't free */ 5040 if (!rx_ring->desc) 5041 return; 5042 5043 dma_free_coherent(rx_ring->dev, rx_ring->size, 5044 rx_ring->desc, rx_ring->dma); 5045 5046 rx_ring->desc = NULL; 5047} 5048 5049/** 5050 * igb_free_all_rx_resources - Free Rx Resources for All Queues 5051 * @adapter: board private structure 5052 * 5053 * Free all receive software resources 5054 **/ 5055static void igb_free_all_rx_resources(struct igb_adapter *adapter) 5056{ 5057 int i; 5058 5059 for (i = 0; i < adapter->num_rx_queues; i++) 5060 if (adapter->rx_ring[i]) 5061 igb_free_rx_resources(adapter->rx_ring[i]); 5062} 5063 5064/** 5065 * igb_clean_rx_ring - Free Rx Buffers per Queue 5066 * @rx_ring: ring to free buffers from 5067 **/ 5068void igb_clean_rx_ring(struct igb_ring *rx_ring) 5069{ 5070 u16 i = rx_ring->next_to_clean; 5071 5072 dev_kfree_skb(rx_ring->skb); 5073 rx_ring->skb = NULL; 5074 5075 if (rx_ring->xsk_pool) { 5076 igb_clean_rx_ring_zc(rx_ring); 5077 goto skip_for_xsk; 5078 } 5079 5080 /* Free all the Rx ring sk_buffs */ 5081 while (i != rx_ring->next_to_alloc) { 5082 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5083 5084 /* Invalidate cache lines that may have been written to by 5085 * device so that we avoid corrupting memory. 5086 */ 5087 dma_sync_single_range_for_cpu(rx_ring->dev, 5088 buffer_info->dma, 5089 buffer_info->page_offset, 5090 igb_rx_bufsz(rx_ring), 5091 DMA_FROM_DEVICE); 5092 5093 /* free resources associated with mapping */ 5094 dma_unmap_page_attrs(rx_ring->dev, 5095 buffer_info->dma, 5096 igb_rx_pg_size(rx_ring), 5097 DMA_FROM_DEVICE, 5098 IGB_RX_DMA_ATTR); 5099 __page_frag_cache_drain(buffer_info->page, 5100 buffer_info->pagecnt_bias); 5101 5102 i++; 5103 if (i == rx_ring->count) 5104 i = 0; 5105 } 5106 5107skip_for_xsk: 5108 rx_ring->next_to_alloc = 0; 5109 rx_ring->next_to_clean = 0; 5110 rx_ring->next_to_use = 0; 5111} 5112 5113/** 5114 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5115 * @adapter: board private structure 5116 **/ 5117static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5118{ 5119 int i; 5120 5121 for (i = 0; i < adapter->num_rx_queues; i++) 5122 if (adapter->rx_ring[i]) 5123 igb_clean_rx_ring(adapter->rx_ring[i]); 5124} 5125 5126/** 5127 * igb_set_mac - Change the Ethernet Address of the NIC 5128 * @netdev: network interface device structure 5129 * @p: pointer to an address structure 5130 * 5131 * Returns 0 on success, negative on failure 5132 **/ 5133static int igb_set_mac(struct net_device *netdev, void *p) 5134{ 5135 struct igb_adapter *adapter = netdev_priv(netdev); 5136 struct e1000_hw *hw = &adapter->hw; 5137 struct sockaddr *addr = p; 5138 5139 if (!is_valid_ether_addr(addr->sa_data)) 5140 return -EADDRNOTAVAIL; 5141 5142 eth_hw_addr_set(netdev, addr->sa_data); 5143 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5144 5145 /* set the correct pool for the new PF MAC address in entry 0 */ 5146 igb_set_default_mac_filter(adapter); 5147 5148 return 0; 5149} 5150 5151/** 5152 * igb_write_mc_addr_list - write multicast addresses to MTA 5153 * @netdev: network interface device structure 5154 * 5155 * Writes multicast address list to the MTA hash table. 5156 * Returns: -ENOMEM on failure 5157 * 0 on no addresses written 5158 * X on writing X addresses to MTA 5159 **/ 5160static int igb_write_mc_addr_list(struct net_device *netdev) 5161{ 5162 struct igb_adapter *adapter = netdev_priv(netdev); 5163 struct e1000_hw *hw = &adapter->hw; 5164 struct netdev_hw_addr *ha; 5165 u8 *mta_list; 5166 int i; 5167 5168 if (netdev_mc_empty(netdev)) { 5169 /* nothing to program, so clear mc list */ 5170 igb_update_mc_addr_list(hw, NULL, 0); 5171 igb_restore_vf_multicasts(adapter); 5172 return 0; 5173 } 5174 5175 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5176 if (!mta_list) 5177 return -ENOMEM; 5178 5179 /* The shared function expects a packed array of only addresses. */ 5180 i = 0; 5181 netdev_for_each_mc_addr(ha, netdev) 5182 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5183 5184 igb_update_mc_addr_list(hw, mta_list, i); 5185 kfree(mta_list); 5186 5187 return netdev_mc_count(netdev); 5188} 5189 5190static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5191{ 5192 struct e1000_hw *hw = &adapter->hw; 5193 u32 i, pf_id; 5194 5195 switch (hw->mac.type) { 5196 case e1000_i210: 5197 case e1000_i211: 5198 case e1000_i350: 5199 /* VLAN filtering needed for VLAN prio filter */ 5200 if (adapter->netdev->features & NETIF_F_NTUPLE) 5201 break; 5202 fallthrough; 5203 case e1000_82576: 5204 case e1000_82580: 5205 case e1000_i354: 5206 /* VLAN filtering needed for pool filtering */ 5207 if (adapter->vfs_allocated_count) 5208 break; 5209 fallthrough; 5210 default: 5211 return 1; 5212 } 5213 5214 /* We are already in VLAN promisc, nothing to do */ 5215 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5216 return 0; 5217 5218 if (!adapter->vfs_allocated_count) 5219 goto set_vfta; 5220 5221 /* Add PF to all active pools */ 5222 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5223 5224 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5225 u32 vlvf = rd32(E1000_VLVF(i)); 5226 5227 vlvf |= BIT(pf_id); 5228 wr32(E1000_VLVF(i), vlvf); 5229 } 5230 5231set_vfta: 5232 /* Set all bits in the VLAN filter table array */ 5233 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5234 hw->mac.ops.write_vfta(hw, i, ~0U); 5235 5236 /* Set flag so we don't redo unnecessary work */ 5237 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5238 5239 return 0; 5240} 5241 5242#define VFTA_BLOCK_SIZE 8 5243static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5244{ 5245 struct e1000_hw *hw = &adapter->hw; 5246 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5247 u32 vid_start = vfta_offset * 32; 5248 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5249 u32 i, vid, word, bits, pf_id; 5250 5251 /* guarantee that we don't scrub out management VLAN */ 5252 vid = adapter->mng_vlan_id; 5253 if (vid >= vid_start && vid < vid_end) 5254 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5255 5256 if (!adapter->vfs_allocated_count) 5257 goto set_vfta; 5258 5259 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5260 5261 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5262 u32 vlvf = rd32(E1000_VLVF(i)); 5263 5264 /* pull VLAN ID from VLVF */ 5265 vid = vlvf & VLAN_VID_MASK; 5266 5267 /* only concern ourselves with a certain range */ 5268 if (vid < vid_start || vid >= vid_end) 5269 continue; 5270 5271 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5272 /* record VLAN ID in VFTA */ 5273 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5274 5275 /* if PF is part of this then continue */ 5276 if (test_bit(vid, adapter->active_vlans)) 5277 continue; 5278 } 5279 5280 /* remove PF from the pool */ 5281 bits = ~BIT(pf_id); 5282 bits &= rd32(E1000_VLVF(i)); 5283 wr32(E1000_VLVF(i), bits); 5284 } 5285 5286set_vfta: 5287 /* extract values from active_vlans and write back to VFTA */ 5288 for (i = VFTA_BLOCK_SIZE; i--;) { 5289 vid = (vfta_offset + i) * 32; 5290 word = vid / BITS_PER_LONG; 5291 bits = vid % BITS_PER_LONG; 5292 5293 vfta[i] |= adapter->active_vlans[word] >> bits; 5294 5295 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5296 } 5297} 5298 5299static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5300{ 5301 u32 i; 5302 5303 /* We are not in VLAN promisc, nothing to do */ 5304 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5305 return; 5306 5307 /* Set flag so we don't redo unnecessary work */ 5308 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5309 5310 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5311 igb_scrub_vfta(adapter, i); 5312} 5313 5314/** 5315 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5316 * @netdev: network interface device structure 5317 * 5318 * The set_rx_mode entry point is called whenever the unicast or multicast 5319 * address lists or the network interface flags are updated. This routine is 5320 * responsible for configuring the hardware for proper unicast, multicast, 5321 * promiscuous mode, and all-multi behavior. 5322 **/ 5323static void igb_set_rx_mode(struct net_device *netdev) 5324{ 5325 struct igb_adapter *adapter = netdev_priv(netdev); 5326 struct e1000_hw *hw = &adapter->hw; 5327 unsigned int vfn = adapter->vfs_allocated_count; 5328 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5329 int count; 5330 5331 /* Check for Promiscuous and All Multicast modes */ 5332 if (netdev->flags & IFF_PROMISC) { 5333 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5334 vmolr |= E1000_VMOLR_MPME; 5335 5336 /* enable use of UTA filter to force packets to default pool */ 5337 if (hw->mac.type == e1000_82576) 5338 vmolr |= E1000_VMOLR_ROPE; 5339 } else { 5340 if (netdev->flags & IFF_ALLMULTI) { 5341 rctl |= E1000_RCTL_MPE; 5342 vmolr |= E1000_VMOLR_MPME; 5343 } else { 5344 /* Write addresses to the MTA, if the attempt fails 5345 * then we should just turn on promiscuous mode so 5346 * that we can at least receive multicast traffic 5347 */ 5348 count = igb_write_mc_addr_list(netdev); 5349 if (count < 0) { 5350 rctl |= E1000_RCTL_MPE; 5351 vmolr |= E1000_VMOLR_MPME; 5352 } else if (count) { 5353 vmolr |= E1000_VMOLR_ROMPE; 5354 } 5355 } 5356 } 5357 5358 /* Write addresses to available RAR registers, if there is not 5359 * sufficient space to store all the addresses then enable 5360 * unicast promiscuous mode 5361 */ 5362 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5363 rctl |= E1000_RCTL_UPE; 5364 vmolr |= E1000_VMOLR_ROPE; 5365 } 5366 5367 /* enable VLAN filtering by default */ 5368 rctl |= E1000_RCTL_VFE; 5369 5370 /* disable VLAN filtering for modes that require it */ 5371 if ((netdev->flags & IFF_PROMISC) || 5372 (netdev->features & NETIF_F_RXALL)) { 5373 /* if we fail to set all rules then just clear VFE */ 5374 if (igb_vlan_promisc_enable(adapter)) 5375 rctl &= ~E1000_RCTL_VFE; 5376 } else { 5377 igb_vlan_promisc_disable(adapter); 5378 } 5379 5380 /* update state of unicast, multicast, and VLAN filtering modes */ 5381 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5382 E1000_RCTL_VFE); 5383 wr32(E1000_RCTL, rctl); 5384 5385#if (PAGE_SIZE < 8192) 5386 if (!adapter->vfs_allocated_count) { 5387 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5388 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5389 } 5390#endif 5391 wr32(E1000_RLPML, rlpml); 5392 5393 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5394 * the VMOLR to enable the appropriate modes. Without this workaround 5395 * we will have issues with VLAN tag stripping not being done for frames 5396 * that are only arriving because we are the default pool 5397 */ 5398 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5399 return; 5400 5401 /* set UTA to appropriate mode */ 5402 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5403 5404 vmolr |= rd32(E1000_VMOLR(vfn)) & 5405 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5406 5407 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5408 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5409#if (PAGE_SIZE < 8192) 5410 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5411 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5412 else 5413#endif 5414 vmolr |= MAX_JUMBO_FRAME_SIZE; 5415 vmolr |= E1000_VMOLR_LPE; 5416 5417 wr32(E1000_VMOLR(vfn), vmolr); 5418 5419 igb_restore_vf_multicasts(adapter); 5420} 5421 5422static void igb_check_wvbr(struct igb_adapter *adapter) 5423{ 5424 struct e1000_hw *hw = &adapter->hw; 5425 u32 wvbr = 0; 5426 5427 switch (hw->mac.type) { 5428 case e1000_82576: 5429 case e1000_i350: 5430 wvbr = rd32(E1000_WVBR); 5431 if (!wvbr) 5432 return; 5433 break; 5434 default: 5435 break; 5436 } 5437 5438 adapter->wvbr |= wvbr; 5439} 5440 5441#define IGB_STAGGERED_QUEUE_OFFSET 8 5442 5443static void igb_spoof_check(struct igb_adapter *adapter) 5444{ 5445 int j; 5446 5447 if (!adapter->wvbr) 5448 return; 5449 5450 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5451 if (adapter->wvbr & BIT(j) || 5452 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5453 dev_warn(&adapter->pdev->dev, 5454 "Spoof event(s) detected on VF %d\n", j); 5455 adapter->wvbr &= 5456 ~(BIT(j) | 5457 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5458 } 5459 } 5460} 5461 5462/* Need to wait a few seconds after link up to get diagnostic information from 5463 * the phy 5464 */ 5465static void igb_update_phy_info(struct timer_list *t) 5466{ 5467 struct igb_adapter *adapter = timer_container_of(adapter, t, 5468 phy_info_timer); 5469 igb_get_phy_info(&adapter->hw); 5470} 5471 5472/** 5473 * igb_has_link - check shared code for link and determine up/down 5474 * @adapter: pointer to driver private info 5475 **/ 5476bool igb_has_link(struct igb_adapter *adapter) 5477{ 5478 struct e1000_hw *hw = &adapter->hw; 5479 bool link_active = false; 5480 5481 /* get_link_status is set on LSC (link status) interrupt or 5482 * rx sequence error interrupt. get_link_status will stay 5483 * false until the e1000_check_for_link establishes link 5484 * for copper adapters ONLY 5485 */ 5486 switch (hw->phy.media_type) { 5487 case e1000_media_type_copper: 5488 if (!hw->mac.get_link_status) 5489 return true; 5490 fallthrough; 5491 case e1000_media_type_internal_serdes: 5492 hw->mac.ops.check_for_link(hw); 5493 link_active = !hw->mac.get_link_status; 5494 break; 5495 default: 5496 case e1000_media_type_unknown: 5497 break; 5498 } 5499 5500 if (((hw->mac.type == e1000_i210) || 5501 (hw->mac.type == e1000_i211)) && 5502 (hw->phy.id == I210_I_PHY_ID)) { 5503 if (!netif_carrier_ok(adapter->netdev)) { 5504 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5505 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5506 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5507 adapter->link_check_timeout = jiffies; 5508 } 5509 } 5510 5511 return link_active; 5512} 5513 5514static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5515{ 5516 bool ret = false; 5517 u32 ctrl_ext, thstat; 5518 5519 /* check for thermal sensor event on i350 copper only */ 5520 if (hw->mac.type == e1000_i350) { 5521 thstat = rd32(E1000_THSTAT); 5522 ctrl_ext = rd32(E1000_CTRL_EXT); 5523 5524 if ((hw->phy.media_type == e1000_media_type_copper) && 5525 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5526 ret = !!(thstat & event); 5527 } 5528 5529 return ret; 5530} 5531 5532/** 5533 * igb_check_lvmmc - check for malformed packets received 5534 * and indicated in LVMMC register 5535 * @adapter: pointer to adapter 5536 **/ 5537static void igb_check_lvmmc(struct igb_adapter *adapter) 5538{ 5539 struct e1000_hw *hw = &adapter->hw; 5540 u32 lvmmc; 5541 5542 lvmmc = rd32(E1000_LVMMC); 5543 if (lvmmc) { 5544 if (unlikely(net_ratelimit())) { 5545 netdev_warn(adapter->netdev, 5546 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5547 lvmmc); 5548 } 5549 } 5550} 5551 5552/** 5553 * igb_watchdog - Timer Call-back 5554 * @t: pointer to timer_list containing our private info pointer 5555 **/ 5556static void igb_watchdog(struct timer_list *t) 5557{ 5558 struct igb_adapter *adapter = timer_container_of(adapter, t, 5559 watchdog_timer); 5560 /* Do the rest outside of interrupt context */ 5561 schedule_work(&adapter->watchdog_task); 5562} 5563 5564static void igb_watchdog_task(struct work_struct *work) 5565{ 5566 struct igb_adapter *adapter = container_of(work, 5567 struct igb_adapter, 5568 watchdog_task); 5569 struct e1000_hw *hw = &adapter->hw; 5570 struct e1000_phy_info *phy = &hw->phy; 5571 struct net_device *netdev = adapter->netdev; 5572 u32 link; 5573 int i; 5574 u32 connsw; 5575 u16 phy_data, retry_count = 20; 5576 5577 link = igb_has_link(adapter); 5578 5579 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5580 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5581 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5582 else 5583 link = false; 5584 } 5585 5586 /* Force link down if we have fiber to swap to */ 5587 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5588 if (hw->phy.media_type == e1000_media_type_copper) { 5589 connsw = rd32(E1000_CONNSW); 5590 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5591 link = 0; 5592 } 5593 } 5594 if (link) { 5595 /* Perform a reset if the media type changed. */ 5596 if (hw->dev_spec._82575.media_changed) { 5597 hw->dev_spec._82575.media_changed = false; 5598 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5599 igb_reset(adapter); 5600 } 5601 /* Cancel scheduled suspend requests. */ 5602 pm_runtime_resume(netdev->dev.parent); 5603 5604 if (!netif_carrier_ok(netdev)) { 5605 u32 ctrl; 5606 5607 hw->mac.ops.get_speed_and_duplex(hw, 5608 &adapter->link_speed, 5609 &adapter->link_duplex); 5610 5611 ctrl = rd32(E1000_CTRL); 5612 /* Links status message must follow this format */ 5613 netdev_info(netdev, 5614 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5615 netdev->name, 5616 adapter->link_speed, 5617 adapter->link_duplex == FULL_DUPLEX ? 5618 "Full" : "Half", 5619 (ctrl & E1000_CTRL_TFCE) && 5620 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5621 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5622 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5623 5624 /* disable EEE if enabled */ 5625 if ((adapter->flags & IGB_FLAG_EEE) && 5626 (adapter->link_duplex == HALF_DUPLEX)) { 5627 dev_info(&adapter->pdev->dev, 5628 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5629 adapter->hw.dev_spec._82575.eee_disable = true; 5630 adapter->flags &= ~IGB_FLAG_EEE; 5631 } 5632 5633 /* check if SmartSpeed worked */ 5634 igb_check_downshift(hw); 5635 if (phy->speed_downgraded) 5636 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5637 5638 /* check for thermal sensor event */ 5639 if (igb_thermal_sensor_event(hw, 5640 E1000_THSTAT_LINK_THROTTLE)) 5641 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5642 5643 /* adjust timeout factor according to speed/duplex */ 5644 adapter->tx_timeout_factor = 1; 5645 switch (adapter->link_speed) { 5646 case SPEED_10: 5647 adapter->tx_timeout_factor = 14; 5648 break; 5649 case SPEED_100: 5650 /* maybe add some timeout factor ? */ 5651 break; 5652 } 5653 5654 if (adapter->link_speed != SPEED_1000 || 5655 !hw->phy.ops.read_reg) 5656 goto no_wait; 5657 5658 /* wait for Remote receiver status OK */ 5659retry_read_status: 5660 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5661 &phy_data)) { 5662 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5663 retry_count) { 5664 msleep(100); 5665 retry_count--; 5666 goto retry_read_status; 5667 } else if (!retry_count) { 5668 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5669 } 5670 } else { 5671 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5672 } 5673no_wait: 5674 netif_carrier_on(netdev); 5675 5676 igb_ping_all_vfs(adapter); 5677 igb_check_vf_rate_limit(adapter); 5678 5679 /* link state has changed, schedule phy info update */ 5680 if (!test_bit(__IGB_DOWN, &adapter->state)) 5681 mod_timer(&adapter->phy_info_timer, 5682 round_jiffies(jiffies + 2 * HZ)); 5683 } 5684 } else { 5685 if (netif_carrier_ok(netdev)) { 5686 adapter->link_speed = 0; 5687 adapter->link_duplex = 0; 5688 5689 /* check for thermal sensor event */ 5690 if (igb_thermal_sensor_event(hw, 5691 E1000_THSTAT_PWR_DOWN)) { 5692 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5693 } 5694 5695 /* Links status message must follow this format */ 5696 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5697 netdev->name); 5698 netif_carrier_off(netdev); 5699 5700 igb_ping_all_vfs(adapter); 5701 5702 /* link state has changed, schedule phy info update */ 5703 if (!test_bit(__IGB_DOWN, &adapter->state)) 5704 mod_timer(&adapter->phy_info_timer, 5705 round_jiffies(jiffies + 2 * HZ)); 5706 5707 /* link is down, time to check for alternate media */ 5708 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5709 igb_check_swap_media(adapter); 5710 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5711 schedule_work(&adapter->reset_task); 5712 /* return immediately */ 5713 return; 5714 } 5715 } 5716 pm_schedule_suspend(netdev->dev.parent, 5717 MSEC_PER_SEC * 5); 5718 5719 /* also check for alternate media here */ 5720 } else if (!netif_carrier_ok(netdev) && 5721 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5722 igb_check_swap_media(adapter); 5723 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5724 schedule_work(&adapter->reset_task); 5725 /* return immediately */ 5726 return; 5727 } 5728 } 5729 } 5730 5731 spin_lock(&adapter->stats64_lock); 5732 igb_update_stats(adapter); 5733 spin_unlock(&adapter->stats64_lock); 5734 5735 for (i = 0; i < adapter->num_tx_queues; i++) { 5736 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5737 if (!netif_carrier_ok(netdev)) { 5738 /* We've lost link, so the controller stops DMA, 5739 * but we've got queued Tx work that's never going 5740 * to get done, so reset controller to flush Tx. 5741 * (Do the reset outside of interrupt context). 5742 */ 5743 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5744 adapter->tx_timeout_count++; 5745 schedule_work(&adapter->reset_task); 5746 /* return immediately since reset is imminent */ 5747 return; 5748 } 5749 } 5750 5751 /* Force detection of hung controller every watchdog period */ 5752 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5753 } 5754 5755 /* Cause software interrupt to ensure Rx ring is cleaned */ 5756 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5757 u32 eics = 0; 5758 5759 for (i = 0; i < adapter->num_q_vectors; i++) { 5760 struct igb_q_vector *q_vector = adapter->q_vector[i]; 5761 struct igb_ring *rx_ring; 5762 5763 if (!q_vector->rx.ring) 5764 continue; 5765 5766 rx_ring = adapter->rx_ring[q_vector->rx.ring->queue_index]; 5767 5768 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5769 eics |= q_vector->eims_value; 5770 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5771 } 5772 } 5773 if (eics) 5774 wr32(E1000_EICS, eics); 5775 } else { 5776 struct igb_ring *rx_ring = adapter->rx_ring[0]; 5777 5778 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5779 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5780 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5781 } 5782 } 5783 5784 igb_spoof_check(adapter); 5785 igb_ptp_rx_hang(adapter); 5786 igb_ptp_tx_hang(adapter); 5787 5788 /* Check LVMMC register on i350/i354 only */ 5789 if ((adapter->hw.mac.type == e1000_i350) || 5790 (adapter->hw.mac.type == e1000_i354)) 5791 igb_check_lvmmc(adapter); 5792 5793 /* Reset the timer */ 5794 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5795 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5796 mod_timer(&adapter->watchdog_timer, 5797 round_jiffies(jiffies + HZ)); 5798 else 5799 mod_timer(&adapter->watchdog_timer, 5800 round_jiffies(jiffies + 2 * HZ)); 5801 } 5802} 5803 5804enum latency_range { 5805 lowest_latency = 0, 5806 low_latency = 1, 5807 bulk_latency = 2, 5808 latency_invalid = 255 5809}; 5810 5811/** 5812 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5813 * @q_vector: pointer to q_vector 5814 * 5815 * Stores a new ITR value based on strictly on packet size. This 5816 * algorithm is less sophisticated than that used in igb_update_itr, 5817 * due to the difficulty of synchronizing statistics across multiple 5818 * receive rings. The divisors and thresholds used by this function 5819 * were determined based on theoretical maximum wire speed and testing 5820 * data, in order to minimize response time while increasing bulk 5821 * throughput. 5822 * This functionality is controlled by ethtool's coalescing settings. 5823 * NOTE: This function is called only when operating in a multiqueue 5824 * receive environment. 5825 **/ 5826static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5827{ 5828 int new_val = q_vector->itr_val; 5829 int avg_wire_size = 0; 5830 struct igb_adapter *adapter = q_vector->adapter; 5831 unsigned int packets; 5832 5833 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5834 * ints/sec - ITR timer value of 120 ticks. 5835 */ 5836 if (adapter->link_speed != SPEED_1000) { 5837 new_val = IGB_4K_ITR; 5838 goto set_itr_val; 5839 } 5840 5841 packets = q_vector->rx.total_packets; 5842 if (packets) 5843 avg_wire_size = q_vector->rx.total_bytes / packets; 5844 5845 packets = q_vector->tx.total_packets; 5846 if (packets) 5847 avg_wire_size = max_t(u32, avg_wire_size, 5848 q_vector->tx.total_bytes / packets); 5849 5850 /* if avg_wire_size isn't set no work was done */ 5851 if (!avg_wire_size) 5852 goto clear_counts; 5853 5854 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5855 avg_wire_size += 24; 5856 5857 /* Don't starve jumbo frames */ 5858 avg_wire_size = min(avg_wire_size, 3000); 5859 5860 /* Give a little boost to mid-size frames */ 5861 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5862 new_val = avg_wire_size / 3; 5863 else 5864 new_val = avg_wire_size / 2; 5865 5866 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5867 if (new_val < IGB_20K_ITR && 5868 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5869 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5870 new_val = IGB_20K_ITR; 5871 5872set_itr_val: 5873 if (new_val != q_vector->itr_val) { 5874 q_vector->itr_val = new_val; 5875 q_vector->set_itr = 1; 5876 } 5877clear_counts: 5878 q_vector->rx.total_bytes = 0; 5879 q_vector->rx.total_packets = 0; 5880 q_vector->tx.total_bytes = 0; 5881 q_vector->tx.total_packets = 0; 5882} 5883 5884/** 5885 * igb_update_itr - update the dynamic ITR value based on statistics 5886 * @q_vector: pointer to q_vector 5887 * @ring_container: ring info to update the itr for 5888 * 5889 * Stores a new ITR value based on packets and byte 5890 * counts during the last interrupt. The advantage of per interrupt 5891 * computation is faster updates and more accurate ITR for the current 5892 * traffic pattern. Constants in this function were computed 5893 * based on theoretical maximum wire speed and thresholds were set based 5894 * on testing data as well as attempting to minimize response time 5895 * while increasing bulk throughput. 5896 * This functionality is controlled by ethtool's coalescing settings. 5897 * NOTE: These calculations are only valid when operating in a single- 5898 * queue environment. 5899 **/ 5900static void igb_update_itr(struct igb_q_vector *q_vector, 5901 struct igb_ring_container *ring_container) 5902{ 5903 unsigned int packets = ring_container->total_packets; 5904 unsigned int bytes = ring_container->total_bytes; 5905 u8 itrval = ring_container->itr; 5906 5907 /* no packets, exit with status unchanged */ 5908 if (packets == 0) 5909 return; 5910 5911 switch (itrval) { 5912 case lowest_latency: 5913 /* handle TSO and jumbo frames */ 5914 if (bytes/packets > 8000) 5915 itrval = bulk_latency; 5916 else if ((packets < 5) && (bytes > 512)) 5917 itrval = low_latency; 5918 break; 5919 case low_latency: /* 50 usec aka 20000 ints/s */ 5920 if (bytes > 10000) { 5921 /* this if handles the TSO accounting */ 5922 if (bytes/packets > 8000) 5923 itrval = bulk_latency; 5924 else if ((packets < 10) || ((bytes/packets) > 1200)) 5925 itrval = bulk_latency; 5926 else if ((packets > 35)) 5927 itrval = lowest_latency; 5928 } else if (bytes/packets > 2000) { 5929 itrval = bulk_latency; 5930 } else if (packets <= 2 && bytes < 512) { 5931 itrval = lowest_latency; 5932 } 5933 break; 5934 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5935 if (bytes > 25000) { 5936 if (packets > 35) 5937 itrval = low_latency; 5938 } else if (bytes < 1500) { 5939 itrval = low_latency; 5940 } 5941 break; 5942 } 5943 5944 /* clear work counters since we have the values we need */ 5945 ring_container->total_bytes = 0; 5946 ring_container->total_packets = 0; 5947 5948 /* write updated itr to ring container */ 5949 ring_container->itr = itrval; 5950} 5951 5952static void igb_set_itr(struct igb_q_vector *q_vector) 5953{ 5954 struct igb_adapter *adapter = q_vector->adapter; 5955 u32 new_itr = q_vector->itr_val; 5956 u8 current_itr = 0; 5957 5958 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5959 if (adapter->link_speed != SPEED_1000) { 5960 current_itr = 0; 5961 new_itr = IGB_4K_ITR; 5962 goto set_itr_now; 5963 } 5964 5965 igb_update_itr(q_vector, &q_vector->tx); 5966 igb_update_itr(q_vector, &q_vector->rx); 5967 5968 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5969 5970 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5971 if (current_itr == lowest_latency && 5972 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5973 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5974 current_itr = low_latency; 5975 5976 switch (current_itr) { 5977 /* counts and packets in update_itr are dependent on these numbers */ 5978 case lowest_latency: 5979 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5980 break; 5981 case low_latency: 5982 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5983 break; 5984 case bulk_latency: 5985 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5986 break; 5987 default: 5988 break; 5989 } 5990 5991set_itr_now: 5992 if (new_itr != q_vector->itr_val) { 5993 /* this attempts to bias the interrupt rate towards Bulk 5994 * by adding intermediate steps when interrupt rate is 5995 * increasing 5996 */ 5997 new_itr = new_itr > q_vector->itr_val ? 5998 max((new_itr * q_vector->itr_val) / 5999 (new_itr + (q_vector->itr_val >> 2)), 6000 new_itr) : new_itr; 6001 /* Don't write the value here; it resets the adapter's 6002 * internal timer, and causes us to delay far longer than 6003 * we should between interrupts. Instead, we write the ITR 6004 * value at the beginning of the next interrupt so the timing 6005 * ends up being correct. 6006 */ 6007 q_vector->itr_val = new_itr; 6008 q_vector->set_itr = 1; 6009 } 6010} 6011 6012static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 6013 struct igb_tx_buffer *first, 6014 u32 vlan_macip_lens, u32 type_tucmd, 6015 u32 mss_l4len_idx) 6016{ 6017 struct e1000_adv_tx_context_desc *context_desc; 6018 u16 i = tx_ring->next_to_use; 6019 struct timespec64 ts; 6020 6021 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 6022 6023 i++; 6024 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 6025 6026 /* set bits to identify this as an advanced context descriptor */ 6027 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 6028 6029 /* For 82575, context index must be unique per ring. */ 6030 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6031 mss_l4len_idx |= tx_ring->reg_idx << 4; 6032 6033 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 6034 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 6035 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 6036 6037 /* We assume there is always a valid tx time available. Invalid times 6038 * should have been handled by the upper layers. 6039 */ 6040 if (tx_ring->launchtime_enable) { 6041 ts = ktime_to_timespec64(first->skb->tstamp); 6042 skb_txtime_consumed(first->skb); 6043 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 6044 } else { 6045 context_desc->seqnum_seed = 0; 6046 } 6047} 6048 6049static int igb_tso(struct igb_ring *tx_ring, 6050 struct igb_tx_buffer *first, 6051 u8 *hdr_len) 6052{ 6053 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 6054 struct sk_buff *skb = first->skb; 6055 union { 6056 struct iphdr *v4; 6057 struct ipv6hdr *v6; 6058 unsigned char *hdr; 6059 } ip; 6060 union { 6061 struct tcphdr *tcp; 6062 struct udphdr *udp; 6063 unsigned char *hdr; 6064 } l4; 6065 u32 paylen, l4_offset; 6066 int err; 6067 6068 if (skb->ip_summed != CHECKSUM_PARTIAL) 6069 return 0; 6070 6071 if (!skb_is_gso(skb)) 6072 return 0; 6073 6074 err = skb_cow_head(skb, 0); 6075 if (err < 0) 6076 return err; 6077 6078 ip.hdr = skb_network_header(skb); 6079 l4.hdr = skb_checksum_start(skb); 6080 6081 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6082 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 6083 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 6084 6085 /* initialize outer IP header fields */ 6086 if (ip.v4->version == 4) { 6087 unsigned char *csum_start = skb_checksum_start(skb); 6088 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6089 6090 /* IP header will have to cancel out any data that 6091 * is not a part of the outer IP header 6092 */ 6093 ip.v4->check = csum_fold(csum_partial(trans_start, 6094 csum_start - trans_start, 6095 0)); 6096 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6097 6098 ip.v4->tot_len = 0; 6099 first->tx_flags |= IGB_TX_FLAGS_TSO | 6100 IGB_TX_FLAGS_CSUM | 6101 IGB_TX_FLAGS_IPV4; 6102 } else { 6103 ip.v6->payload_len = 0; 6104 first->tx_flags |= IGB_TX_FLAGS_TSO | 6105 IGB_TX_FLAGS_CSUM; 6106 } 6107 6108 /* determine offset of inner transport header */ 6109 l4_offset = l4.hdr - skb->data; 6110 6111 /* remove payload length from inner checksum */ 6112 paylen = skb->len - l4_offset; 6113 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6114 /* compute length of segmentation header */ 6115 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6116 csum_replace_by_diff(&l4.tcp->check, 6117 (__force __wsum)htonl(paylen)); 6118 } else { 6119 /* compute length of segmentation header */ 6120 *hdr_len = sizeof(*l4.udp) + l4_offset; 6121 csum_replace_by_diff(&l4.udp->check, 6122 (__force __wsum)htonl(paylen)); 6123 } 6124 6125 /* update gso size and bytecount with header size */ 6126 first->gso_segs = skb_shinfo(skb)->gso_segs; 6127 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6128 6129 /* MSS L4LEN IDX */ 6130 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6131 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6132 6133 /* VLAN MACLEN IPLEN */ 6134 vlan_macip_lens = l4.hdr - ip.hdr; 6135 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6136 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6137 6138 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6139 type_tucmd, mss_l4len_idx); 6140 6141 return 1; 6142} 6143 6144static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6145{ 6146 struct sk_buff *skb = first->skb; 6147 u32 vlan_macip_lens = 0; 6148 u32 type_tucmd = 0; 6149 6150 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6151csum_failed: 6152 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6153 !tx_ring->launchtime_enable) 6154 return; 6155 goto no_csum; 6156 } 6157 6158 switch (skb->csum_offset) { 6159 case offsetof(struct tcphdr, check): 6160 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6161 fallthrough; 6162 case offsetof(struct udphdr, check): 6163 break; 6164 case offsetof(struct sctphdr, checksum): 6165 /* validate that this is actually an SCTP request */ 6166 if (skb_csum_is_sctp(skb)) { 6167 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6168 break; 6169 } 6170 fallthrough; 6171 default: 6172 skb_checksum_help(skb); 6173 goto csum_failed; 6174 } 6175 6176 /* update TX checksum flag */ 6177 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6178 vlan_macip_lens = skb_checksum_start_offset(skb) - 6179 skb_network_offset(skb); 6180no_csum: 6181 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6182 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6183 6184 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6185} 6186 6187#define IGB_SET_FLAG(_input, _flag, _result) \ 6188 ((_flag <= _result) ? \ 6189 ((u32)(_input & _flag) * (_result / _flag)) : \ 6190 ((u32)(_input & _flag) / (_flag / _result))) 6191 6192static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6193{ 6194 /* set type for advanced descriptor with frame checksum insertion */ 6195 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6196 E1000_ADVTXD_DCMD_DEXT | 6197 E1000_ADVTXD_DCMD_IFCS; 6198 6199 /* set HW vlan bit if vlan is present */ 6200 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6201 (E1000_ADVTXD_DCMD_VLE)); 6202 6203 /* set segmentation bits for TSO */ 6204 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6205 (E1000_ADVTXD_DCMD_TSE)); 6206 6207 /* set timestamp bit if present */ 6208 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6209 (E1000_ADVTXD_MAC_TSTAMP)); 6210 6211 /* insert frame checksum */ 6212 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6213 6214 return cmd_type; 6215} 6216 6217static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6218 union e1000_adv_tx_desc *tx_desc, 6219 u32 tx_flags, unsigned int paylen) 6220{ 6221 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6222 6223 /* 82575 requires a unique index per ring */ 6224 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6225 olinfo_status |= tx_ring->reg_idx << 4; 6226 6227 /* insert L4 checksum */ 6228 olinfo_status |= IGB_SET_FLAG(tx_flags, 6229 IGB_TX_FLAGS_CSUM, 6230 (E1000_TXD_POPTS_TXSM << 8)); 6231 6232 /* insert IPv4 checksum */ 6233 olinfo_status |= IGB_SET_FLAG(tx_flags, 6234 IGB_TX_FLAGS_IPV4, 6235 (E1000_TXD_POPTS_IXSM << 8)); 6236 6237 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6238} 6239 6240static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6241{ 6242 struct net_device *netdev = tx_ring->netdev; 6243 6244 netif_stop_subqueue(netdev, tx_ring->queue_index); 6245 6246 /* Herbert's original patch had: 6247 * smp_mb__after_netif_stop_queue(); 6248 * but since that doesn't exist yet, just open code it. 6249 */ 6250 smp_mb(); 6251 6252 /* We need to check again in a case another CPU has just 6253 * made room available. 6254 */ 6255 if (igb_desc_unused(tx_ring) < size) 6256 return -EBUSY; 6257 6258 /* A reprieve! */ 6259 netif_wake_subqueue(netdev, tx_ring->queue_index); 6260 6261 u64_stats_update_begin(&tx_ring->tx_syncp2); 6262 tx_ring->tx_stats.restart_queue2++; 6263 u64_stats_update_end(&tx_ring->tx_syncp2); 6264 6265 return 0; 6266} 6267 6268static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6269{ 6270 if (igb_desc_unused(tx_ring) >= size) 6271 return 0; 6272 return __igb_maybe_stop_tx(tx_ring, size); 6273} 6274 6275static int igb_tx_map(struct igb_ring *tx_ring, 6276 struct igb_tx_buffer *first, 6277 const u8 hdr_len) 6278{ 6279 struct sk_buff *skb = first->skb; 6280 struct igb_tx_buffer *tx_buffer; 6281 union e1000_adv_tx_desc *tx_desc; 6282 skb_frag_t *frag; 6283 dma_addr_t dma; 6284 unsigned int data_len, size; 6285 u32 tx_flags = first->tx_flags; 6286 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6287 u16 i = tx_ring->next_to_use; 6288 6289 tx_desc = IGB_TX_DESC(tx_ring, i); 6290 6291 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6292 6293 size = skb_headlen(skb); 6294 data_len = skb->data_len; 6295 6296 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6297 6298 tx_buffer = first; 6299 6300 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6301 if (dma_mapping_error(tx_ring->dev, dma)) 6302 goto dma_error; 6303 6304 /* record length, and DMA address */ 6305 dma_unmap_len_set(tx_buffer, len, size); 6306 dma_unmap_addr_set(tx_buffer, dma, dma); 6307 6308 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6309 6310 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6311 tx_desc->read.cmd_type_len = 6312 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6313 6314 i++; 6315 tx_desc++; 6316 if (i == tx_ring->count) { 6317 tx_desc = IGB_TX_DESC(tx_ring, 0); 6318 i = 0; 6319 } 6320 tx_desc->read.olinfo_status = 0; 6321 6322 dma += IGB_MAX_DATA_PER_TXD; 6323 size -= IGB_MAX_DATA_PER_TXD; 6324 6325 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6326 } 6327 6328 if (likely(!data_len)) 6329 break; 6330 6331 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6332 6333 i++; 6334 tx_desc++; 6335 if (i == tx_ring->count) { 6336 tx_desc = IGB_TX_DESC(tx_ring, 0); 6337 i = 0; 6338 } 6339 tx_desc->read.olinfo_status = 0; 6340 6341 size = skb_frag_size(frag); 6342 data_len -= size; 6343 6344 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6345 size, DMA_TO_DEVICE); 6346 6347 tx_buffer = &tx_ring->tx_buffer_info[i]; 6348 } 6349 6350 /* write last descriptor with RS and EOP bits */ 6351 cmd_type |= size | IGB_TXD_DCMD; 6352 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6353 6354 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6355 6356 /* set the timestamp */ 6357 first->time_stamp = jiffies; 6358 6359 skb_tx_timestamp(skb); 6360 6361 /* Force memory writes to complete before letting h/w know there 6362 * are new descriptors to fetch. (Only applicable for weak-ordered 6363 * memory model archs, such as IA-64). 6364 * 6365 * We also need this memory barrier to make certain all of the 6366 * status bits have been updated before next_to_watch is written. 6367 */ 6368 dma_wmb(); 6369 6370 /* set next_to_watch value indicating a packet is present */ 6371 first->next_to_watch = tx_desc; 6372 6373 i++; 6374 if (i == tx_ring->count) 6375 i = 0; 6376 6377 tx_ring->next_to_use = i; 6378 6379 /* Make sure there is space in the ring for the next send. */ 6380 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6381 6382 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6383 writel(i, tx_ring->tail); 6384 } 6385 return 0; 6386 6387dma_error: 6388 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6389 tx_buffer = &tx_ring->tx_buffer_info[i]; 6390 6391 /* clear dma mappings for failed tx_buffer_info map */ 6392 while (tx_buffer != first) { 6393 if (dma_unmap_len(tx_buffer, len)) 6394 dma_unmap_page(tx_ring->dev, 6395 dma_unmap_addr(tx_buffer, dma), 6396 dma_unmap_len(tx_buffer, len), 6397 DMA_TO_DEVICE); 6398 dma_unmap_len_set(tx_buffer, len, 0); 6399 6400 if (i-- == 0) 6401 i += tx_ring->count; 6402 tx_buffer = &tx_ring->tx_buffer_info[i]; 6403 } 6404 6405 if (dma_unmap_len(tx_buffer, len)) 6406 dma_unmap_single(tx_ring->dev, 6407 dma_unmap_addr(tx_buffer, dma), 6408 dma_unmap_len(tx_buffer, len), 6409 DMA_TO_DEVICE); 6410 dma_unmap_len_set(tx_buffer, len, 0); 6411 6412 dev_kfree_skb_any(tx_buffer->skb); 6413 tx_buffer->skb = NULL; 6414 6415 tx_ring->next_to_use = i; 6416 6417 return -1; 6418} 6419 6420int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6421 struct igb_ring *tx_ring, 6422 struct xdp_frame *xdpf) 6423{ 6424 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6425 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6426 u16 count, i, index = tx_ring->next_to_use; 6427 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6428 struct igb_tx_buffer *tx_buffer = tx_head; 6429 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6430 u32 len = xdpf->len, cmd_type, olinfo_status; 6431 void *data = xdpf->data; 6432 6433 count = TXD_USE_COUNT(len); 6434 for (i = 0; i < nr_frags; i++) 6435 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6436 6437 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6438 return IGB_XDP_CONSUMED; 6439 6440 i = 0; 6441 /* record the location of the first descriptor for this packet */ 6442 tx_head->bytecount = xdp_get_frame_len(xdpf); 6443 tx_head->type = IGB_TYPE_XDP; 6444 tx_head->gso_segs = 1; 6445 tx_head->xdpf = xdpf; 6446 6447 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6448 /* 82575 requires a unique index per ring */ 6449 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6450 olinfo_status |= tx_ring->reg_idx << 4; 6451 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6452 6453 for (;;) { 6454 dma_addr_t dma; 6455 6456 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6457 if (dma_mapping_error(tx_ring->dev, dma)) 6458 goto unmap; 6459 6460 /* record length, and DMA address */ 6461 dma_unmap_len_set(tx_buffer, len, len); 6462 dma_unmap_addr_set(tx_buffer, dma, dma); 6463 6464 /* put descriptor type bits */ 6465 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6466 E1000_ADVTXD_DCMD_IFCS | len; 6467 6468 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6469 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6470 6471 tx_buffer->protocol = 0; 6472 6473 if (++index == tx_ring->count) 6474 index = 0; 6475 6476 if (i == nr_frags) 6477 break; 6478 6479 tx_buffer = &tx_ring->tx_buffer_info[index]; 6480 tx_desc = IGB_TX_DESC(tx_ring, index); 6481 tx_desc->read.olinfo_status = 0; 6482 6483 data = skb_frag_address(&sinfo->frags[i]); 6484 len = skb_frag_size(&sinfo->frags[i]); 6485 i++; 6486 } 6487 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6488 6489 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6490 /* set the timestamp */ 6491 tx_head->time_stamp = jiffies; 6492 6493 /* Avoid any potential race with xdp_xmit and cleanup */ 6494 smp_wmb(); 6495 6496 /* set next_to_watch value indicating a packet is present */ 6497 tx_head->next_to_watch = tx_desc; 6498 tx_ring->next_to_use = index; 6499 6500 /* Make sure there is space in the ring for the next send. */ 6501 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6502 6503 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6504 writel(index, tx_ring->tail); 6505 6506 return IGB_XDP_TX; 6507 6508unmap: 6509 for (;;) { 6510 tx_buffer = &tx_ring->tx_buffer_info[index]; 6511 if (dma_unmap_len(tx_buffer, len)) 6512 dma_unmap_page(tx_ring->dev, 6513 dma_unmap_addr(tx_buffer, dma), 6514 dma_unmap_len(tx_buffer, len), 6515 DMA_TO_DEVICE); 6516 dma_unmap_len_set(tx_buffer, len, 0); 6517 if (tx_buffer == tx_head) 6518 break; 6519 6520 if (!index) 6521 index += tx_ring->count; 6522 index--; 6523 } 6524 6525 return IGB_XDP_CONSUMED; 6526} 6527 6528netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6529 struct igb_ring *tx_ring) 6530{ 6531 struct igb_tx_buffer *first; 6532 int tso; 6533 u32 tx_flags = 0; 6534 unsigned short f; 6535 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6536 __be16 protocol = vlan_get_protocol(skb); 6537 u8 hdr_len = 0; 6538 6539 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6540 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6541 * + 2 desc gap to keep tail from touching head, 6542 * + 1 desc for context descriptor, 6543 * otherwise try next time 6544 */ 6545 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6546 count += TXD_USE_COUNT(skb_frag_size( 6547 &skb_shinfo(skb)->frags[f])); 6548 6549 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6550 /* this is a hard error */ 6551 return NETDEV_TX_BUSY; 6552 } 6553 6554 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 6555 return NETDEV_TX_BUSY; 6556 6557 /* record the location of the first descriptor for this packet */ 6558 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6559 first->type = IGB_TYPE_SKB; 6560 first->skb = skb; 6561 first->bytecount = skb->len; 6562 first->gso_segs = 1; 6563 6564 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6565 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6566 6567 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6568 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6569 &adapter->state)) { 6570 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6571 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6572 6573 adapter->ptp_tx_skb = skb_get(skb); 6574 adapter->ptp_tx_start = jiffies; 6575 if (adapter->hw.mac.type == e1000_82576) 6576 schedule_work(&adapter->ptp_tx_work); 6577 } else { 6578 adapter->tx_hwtstamp_skipped++; 6579 } 6580 } 6581 6582 if (skb_vlan_tag_present(skb)) { 6583 tx_flags |= IGB_TX_FLAGS_VLAN; 6584 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6585 } 6586 6587 /* record initial flags and protocol */ 6588 first->tx_flags = tx_flags; 6589 first->protocol = protocol; 6590 6591 tso = igb_tso(tx_ring, first, &hdr_len); 6592 if (tso < 0) 6593 goto out_drop; 6594 else if (!tso) 6595 igb_tx_csum(tx_ring, first); 6596 6597 if (igb_tx_map(tx_ring, first, hdr_len)) 6598 goto cleanup_tx_tstamp; 6599 6600 return NETDEV_TX_OK; 6601 6602out_drop: 6603 dev_kfree_skb_any(first->skb); 6604 first->skb = NULL; 6605cleanup_tx_tstamp: 6606 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6607 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6608 6609 dev_kfree_skb_any(adapter->ptp_tx_skb); 6610 adapter->ptp_tx_skb = NULL; 6611 if (adapter->hw.mac.type == e1000_82576) 6612 cancel_work_sync(&adapter->ptp_tx_work); 6613 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6614 } 6615 6616 return NETDEV_TX_OK; 6617} 6618 6619static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6620 struct sk_buff *skb) 6621{ 6622 unsigned int r_idx = skb->queue_mapping; 6623 6624 if (r_idx >= adapter->num_tx_queues) 6625 r_idx = r_idx % adapter->num_tx_queues; 6626 6627 return adapter->tx_ring[r_idx]; 6628} 6629 6630static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6631 struct net_device *netdev) 6632{ 6633 struct igb_adapter *adapter = netdev_priv(netdev); 6634 6635 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6636 * in order to meet this minimum size requirement. 6637 */ 6638 if (skb_put_padto(skb, 17)) 6639 return NETDEV_TX_OK; 6640 6641 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6642} 6643 6644/** 6645 * igb_tx_timeout - Respond to a Tx Hang 6646 * @netdev: network interface device structure 6647 * @txqueue: number of the Tx queue that hung (unused) 6648 **/ 6649static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6650{ 6651 struct igb_adapter *adapter = netdev_priv(netdev); 6652 struct e1000_hw *hw = &adapter->hw; 6653 6654 /* Do the reset outside of interrupt context */ 6655 adapter->tx_timeout_count++; 6656 6657 if (hw->mac.type >= e1000_82580) 6658 hw->dev_spec._82575.global_device_reset = true; 6659 6660 schedule_work(&adapter->reset_task); 6661 wr32(E1000_EICS, 6662 (adapter->eims_enable_mask & ~adapter->eims_other)); 6663} 6664 6665static void igb_reset_task(struct work_struct *work) 6666{ 6667 struct igb_adapter *adapter; 6668 adapter = container_of(work, struct igb_adapter, reset_task); 6669 6670 rtnl_lock(); 6671 /* If we're already down or resetting, just bail */ 6672 if (test_bit(__IGB_DOWN, &adapter->state) || 6673 test_bit(__IGB_RESETTING, &adapter->state)) { 6674 rtnl_unlock(); 6675 return; 6676 } 6677 6678 igb_dump(adapter); 6679 netdev_err(adapter->netdev, "Reset adapter\n"); 6680 igb_reinit_locked(adapter); 6681 rtnl_unlock(); 6682} 6683 6684/** 6685 * igb_get_stats64 - Get System Network Statistics 6686 * @netdev: network interface device structure 6687 * @stats: rtnl_link_stats64 pointer 6688 **/ 6689static void igb_get_stats64(struct net_device *netdev, 6690 struct rtnl_link_stats64 *stats) 6691{ 6692 struct igb_adapter *adapter = netdev_priv(netdev); 6693 6694 spin_lock(&adapter->stats64_lock); 6695 igb_update_stats(adapter); 6696 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6697 spin_unlock(&adapter->stats64_lock); 6698} 6699 6700/** 6701 * igb_change_mtu - Change the Maximum Transfer Unit 6702 * @netdev: network interface device structure 6703 * @new_mtu: new value for maximum frame size 6704 * 6705 * Returns 0 on success, negative on failure 6706 **/ 6707static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6708{ 6709 struct igb_adapter *adapter = netdev_priv(netdev); 6710 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6711 6712 if (igb_xdp_is_enabled(adapter)) { 6713 int i; 6714 6715 for (i = 0; i < adapter->num_rx_queues; i++) { 6716 struct igb_ring *ring = adapter->rx_ring[i]; 6717 6718 if (max_frame > igb_rx_bufsz(ring)) { 6719 netdev_warn(adapter->netdev, 6720 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6721 max_frame); 6722 return -EINVAL; 6723 } 6724 } 6725 } 6726 6727 /* adjust max frame to be at least the size of a standard frame */ 6728 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6729 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6730 6731 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6732 usleep_range(1000, 2000); 6733 6734 /* igb_down has a dependency on max_frame_size */ 6735 adapter->max_frame_size = max_frame; 6736 6737 if (netif_running(netdev)) 6738 igb_down(adapter); 6739 6740 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6741 netdev->mtu, new_mtu); 6742 WRITE_ONCE(netdev->mtu, new_mtu); 6743 6744 if (netif_running(netdev)) 6745 igb_up(adapter); 6746 else 6747 igb_reset(adapter); 6748 6749 clear_bit(__IGB_RESETTING, &adapter->state); 6750 6751 return 0; 6752} 6753 6754/** 6755 * igb_update_stats - Update the board statistics counters 6756 * @adapter: board private structure 6757 **/ 6758void igb_update_stats(struct igb_adapter *adapter) 6759{ 6760 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6761 struct e1000_hw *hw = &adapter->hw; 6762 struct pci_dev *pdev = adapter->pdev; 6763 u32 reg, mpc; 6764 int i; 6765 u64 bytes, packets; 6766 unsigned int start; 6767 u64 _bytes, _packets; 6768 6769 /* Prevent stats update while adapter is being reset, or if the pci 6770 * connection is down. 6771 */ 6772 if (adapter->link_speed == 0) 6773 return; 6774 if (pci_channel_offline(pdev)) 6775 return; 6776 6777 bytes = 0; 6778 packets = 0; 6779 6780 rcu_read_lock(); 6781 for (i = 0; i < adapter->num_rx_queues; i++) { 6782 struct igb_ring *ring = adapter->rx_ring[i]; 6783 u32 rqdpc = rd32(E1000_RQDPC(i)); 6784 if (hw->mac.type >= e1000_i210) 6785 wr32(E1000_RQDPC(i), 0); 6786 6787 if (rqdpc) { 6788 ring->rx_stats.drops += rqdpc; 6789 net_stats->rx_fifo_errors += rqdpc; 6790 } 6791 6792 do { 6793 start = u64_stats_fetch_begin(&ring->rx_syncp); 6794 _bytes = ring->rx_stats.bytes; 6795 _packets = ring->rx_stats.packets; 6796 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6797 bytes += _bytes; 6798 packets += _packets; 6799 } 6800 6801 net_stats->rx_bytes = bytes; 6802 net_stats->rx_packets = packets; 6803 6804 bytes = 0; 6805 packets = 0; 6806 for (i = 0; i < adapter->num_tx_queues; i++) { 6807 struct igb_ring *ring = adapter->tx_ring[i]; 6808 do { 6809 start = u64_stats_fetch_begin(&ring->tx_syncp); 6810 _bytes = ring->tx_stats.bytes; 6811 _packets = ring->tx_stats.packets; 6812 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6813 bytes += _bytes; 6814 packets += _packets; 6815 } 6816 net_stats->tx_bytes = bytes; 6817 net_stats->tx_packets = packets; 6818 rcu_read_unlock(); 6819 6820 /* read stats registers */ 6821 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6822 adapter->stats.gprc += rd32(E1000_GPRC); 6823 adapter->stats.gorc += rd32(E1000_GORCL); 6824 rd32(E1000_GORCH); /* clear GORCL */ 6825 adapter->stats.bprc += rd32(E1000_BPRC); 6826 adapter->stats.mprc += rd32(E1000_MPRC); 6827 adapter->stats.roc += rd32(E1000_ROC); 6828 6829 adapter->stats.prc64 += rd32(E1000_PRC64); 6830 adapter->stats.prc127 += rd32(E1000_PRC127); 6831 adapter->stats.prc255 += rd32(E1000_PRC255); 6832 adapter->stats.prc511 += rd32(E1000_PRC511); 6833 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6834 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6835 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6836 adapter->stats.sec += rd32(E1000_SEC); 6837 6838 mpc = rd32(E1000_MPC); 6839 adapter->stats.mpc += mpc; 6840 net_stats->rx_fifo_errors += mpc; 6841 adapter->stats.scc += rd32(E1000_SCC); 6842 adapter->stats.ecol += rd32(E1000_ECOL); 6843 adapter->stats.mcc += rd32(E1000_MCC); 6844 adapter->stats.latecol += rd32(E1000_LATECOL); 6845 adapter->stats.dc += rd32(E1000_DC); 6846 adapter->stats.rlec += rd32(E1000_RLEC); 6847 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6848 adapter->stats.xontxc += rd32(E1000_XONTXC); 6849 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6850 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6851 adapter->stats.fcruc += rd32(E1000_FCRUC); 6852 adapter->stats.gptc += rd32(E1000_GPTC); 6853 adapter->stats.gotc += rd32(E1000_GOTCL); 6854 rd32(E1000_GOTCH); /* clear GOTCL */ 6855 adapter->stats.rnbc += rd32(E1000_RNBC); 6856 adapter->stats.ruc += rd32(E1000_RUC); 6857 adapter->stats.rfc += rd32(E1000_RFC); 6858 adapter->stats.rjc += rd32(E1000_RJC); 6859 adapter->stats.tor += rd32(E1000_TORH); 6860 adapter->stats.tot += rd32(E1000_TOTH); 6861 adapter->stats.tpr += rd32(E1000_TPR); 6862 6863 adapter->stats.ptc64 += rd32(E1000_PTC64); 6864 adapter->stats.ptc127 += rd32(E1000_PTC127); 6865 adapter->stats.ptc255 += rd32(E1000_PTC255); 6866 adapter->stats.ptc511 += rd32(E1000_PTC511); 6867 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6868 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6869 6870 adapter->stats.mptc += rd32(E1000_MPTC); 6871 adapter->stats.bptc += rd32(E1000_BPTC); 6872 6873 adapter->stats.tpt += rd32(E1000_TPT); 6874 adapter->stats.colc += rd32(E1000_COLC); 6875 6876 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6877 /* read internal phy specific stats */ 6878 reg = rd32(E1000_CTRL_EXT); 6879 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6880 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6881 6882 /* this stat has invalid values on i210/i211 */ 6883 if ((hw->mac.type != e1000_i210) && 6884 (hw->mac.type != e1000_i211)) 6885 adapter->stats.tncrs += rd32(E1000_TNCRS); 6886 } 6887 6888 adapter->stats.tsctc += rd32(E1000_TSCTC); 6889 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6890 6891 adapter->stats.iac += rd32(E1000_IAC); 6892 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6893 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6894 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6895 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6896 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6897 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6898 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6899 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6900 6901 /* Fill out the OS statistics structure */ 6902 net_stats->multicast = adapter->stats.mprc; 6903 net_stats->collisions = adapter->stats.colc; 6904 6905 /* Rx Errors */ 6906 6907 /* RLEC on some newer hardware can be incorrect so build 6908 * our own version based on RUC and ROC 6909 */ 6910 net_stats->rx_errors = adapter->stats.rxerrc + 6911 adapter->stats.crcerrs + adapter->stats.algnerrc + 6912 adapter->stats.ruc + adapter->stats.roc + 6913 adapter->stats.cexterr; 6914 net_stats->rx_length_errors = adapter->stats.ruc + 6915 adapter->stats.roc; 6916 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6917 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6918 net_stats->rx_missed_errors = adapter->stats.mpc; 6919 6920 /* Tx Errors */ 6921 net_stats->tx_errors = adapter->stats.ecol + 6922 adapter->stats.latecol; 6923 net_stats->tx_aborted_errors = adapter->stats.ecol; 6924 net_stats->tx_window_errors = adapter->stats.latecol; 6925 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6926 6927 /* Tx Dropped needs to be maintained elsewhere */ 6928 6929 /* Management Stats */ 6930 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6931 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6932 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6933 6934 /* OS2BMC Stats */ 6935 reg = rd32(E1000_MANC); 6936 if (reg & E1000_MANC_EN_BMC2OS) { 6937 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6938 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6939 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6940 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6941 } 6942} 6943 6944static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6945{ 6946 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6947 struct e1000_hw *hw = &adapter->hw; 6948 struct timespec64 ts; 6949 u32 tsauxc; 6950 6951 if (pin < 0 || pin >= IGB_N_SDP) 6952 return; 6953 6954 spin_lock(&adapter->tmreg_lock); 6955 6956 if (hw->mac.type == e1000_82580 || 6957 hw->mac.type == e1000_i354 || 6958 hw->mac.type == e1000_i350) { 6959 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6960 u32 systiml, systimh, level_mask, level, rem; 6961 u64 systim, now; 6962 6963 /* read systim registers in sequence */ 6964 rd32(E1000_SYSTIMR); 6965 systiml = rd32(E1000_SYSTIML); 6966 systimh = rd32(E1000_SYSTIMH); 6967 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6968 now = timecounter_cyc2time(&adapter->tc, systim); 6969 6970 if (pin < 2) { 6971 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6972 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6973 } else { 6974 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6975 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6976 } 6977 6978 div_u64_rem(now, ns, &rem); 6979 systim = systim + (ns - rem); 6980 6981 /* synchronize pin level with rising/falling edges */ 6982 div_u64_rem(now, ns << 1, &rem); 6983 if (rem < ns) { 6984 /* first half of period */ 6985 if (level == 0) { 6986 /* output is already low, skip this period */ 6987 systim += ns; 6988 pr_notice("igb: periodic output on %s missed falling edge\n", 6989 adapter->sdp_config[pin].name); 6990 } 6991 } else { 6992 /* second half of period */ 6993 if (level == 1) { 6994 /* output is already high, skip this period */ 6995 systim += ns; 6996 pr_notice("igb: periodic output on %s missed rising edge\n", 6997 adapter->sdp_config[pin].name); 6998 } 6999 } 7000 7001 /* for this chip family tv_sec is the upper part of the binary value, 7002 * so not seconds 7003 */ 7004 ts.tv_nsec = (u32)systim; 7005 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 7006 } else { 7007 ts = timespec64_add(adapter->perout[tsintr_tt].start, 7008 adapter->perout[tsintr_tt].period); 7009 } 7010 7011 /* u32 conversion of tv_sec is safe until y2106 */ 7012 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 7013 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 7014 tsauxc = rd32(E1000_TSAUXC); 7015 tsauxc |= TSAUXC_EN_TT0; 7016 wr32(E1000_TSAUXC, tsauxc); 7017 adapter->perout[tsintr_tt].start = ts; 7018 7019 spin_unlock(&adapter->tmreg_lock); 7020} 7021 7022static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 7023{ 7024 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 7025 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 7026 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 7027 struct e1000_hw *hw = &adapter->hw; 7028 struct ptp_clock_event event; 7029 struct timespec64 ts; 7030 unsigned long flags; 7031 7032 if (pin < 0 || pin >= IGB_N_SDP) 7033 return; 7034 7035 if (hw->mac.type == e1000_82580 || 7036 hw->mac.type == e1000_i354 || 7037 hw->mac.type == e1000_i350) { 7038 u64 ns = rd32(auxstmpl); 7039 7040 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 7041 spin_lock_irqsave(&adapter->tmreg_lock, flags); 7042 ns = timecounter_cyc2time(&adapter->tc, ns); 7043 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 7044 ts = ns_to_timespec64(ns); 7045 } else { 7046 ts.tv_nsec = rd32(auxstmpl); 7047 ts.tv_sec = rd32(auxstmph); 7048 } 7049 7050 event.type = PTP_CLOCK_EXTTS; 7051 event.index = tsintr_tt; 7052 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 7053 ptp_clock_event(adapter->ptp_clock, &event); 7054} 7055 7056static void igb_tsync_interrupt(struct igb_adapter *adapter) 7057{ 7058 const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS | 7059 TSINTR_TT0 | TSINTR_TT1 | 7060 TSINTR_AUTT0 | TSINTR_AUTT1); 7061 struct e1000_hw *hw = &adapter->hw; 7062 u32 tsicr = rd32(E1000_TSICR); 7063 struct ptp_clock_event event; 7064 7065 if (hw->mac.type == e1000_82580) { 7066 /* 82580 has a hardware bug that requires an explicit 7067 * write to clear the TimeSync interrupt cause. 7068 */ 7069 wr32(E1000_TSICR, tsicr & mask); 7070 } 7071 7072 if (tsicr & TSINTR_SYS_WRAP) { 7073 event.type = PTP_CLOCK_PPS; 7074 if (adapter->ptp_caps.pps) 7075 ptp_clock_event(adapter->ptp_clock, &event); 7076 } 7077 7078 if (tsicr & E1000_TSICR_TXTS) { 7079 /* retrieve hardware timestamp */ 7080 schedule_work(&adapter->ptp_tx_work); 7081 } 7082 7083 if (tsicr & TSINTR_TT0) 7084 igb_perout(adapter, 0); 7085 7086 if (tsicr & TSINTR_TT1) 7087 igb_perout(adapter, 1); 7088 7089 if (tsicr & TSINTR_AUTT0) 7090 igb_extts(adapter, 0); 7091 7092 if (tsicr & TSINTR_AUTT1) 7093 igb_extts(adapter, 1); 7094} 7095 7096static irqreturn_t igb_msix_other(int irq, void *data) 7097{ 7098 struct igb_adapter *adapter = data; 7099 struct e1000_hw *hw = &adapter->hw; 7100 u32 icr = rd32(E1000_ICR); 7101 /* reading ICR causes bit 31 of EICR to be cleared */ 7102 7103 if (icr & E1000_ICR_DRSTA) 7104 schedule_work(&adapter->reset_task); 7105 7106 if (icr & E1000_ICR_DOUTSYNC) { 7107 /* HW is reporting DMA is out of sync */ 7108 adapter->stats.doosync++; 7109 /* The DMA Out of Sync is also indication of a spoof event 7110 * in IOV mode. Check the Wrong VM Behavior register to 7111 * see if it is really a spoof event. 7112 */ 7113 igb_check_wvbr(adapter); 7114 } 7115 7116 /* Check for a mailbox event */ 7117 if (icr & E1000_ICR_VMMB) 7118 igb_msg_task(adapter); 7119 7120 if (icr & E1000_ICR_LSC) { 7121 hw->mac.get_link_status = 1; 7122 /* guard against interrupt when we're going down */ 7123 if (!test_bit(__IGB_DOWN, &adapter->state)) 7124 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7125 } 7126 7127 if (icr & E1000_ICR_TS) 7128 igb_tsync_interrupt(adapter); 7129 7130 wr32(E1000_EIMS, adapter->eims_other); 7131 7132 return IRQ_HANDLED; 7133} 7134 7135static void igb_write_itr(struct igb_q_vector *q_vector) 7136{ 7137 struct igb_adapter *adapter = q_vector->adapter; 7138 u32 itr_val = q_vector->itr_val & 0x7FFC; 7139 7140 if (!q_vector->set_itr) 7141 return; 7142 7143 if (!itr_val) 7144 itr_val = 0x4; 7145 7146 if (adapter->hw.mac.type == e1000_82575) 7147 itr_val |= itr_val << 16; 7148 else 7149 itr_val |= E1000_EITR_CNT_IGNR; 7150 7151 writel(itr_val, q_vector->itr_register); 7152 q_vector->set_itr = 0; 7153} 7154 7155static irqreturn_t igb_msix_ring(int irq, void *data) 7156{ 7157 struct igb_q_vector *q_vector = data; 7158 7159 /* Write the ITR value calculated from the previous interrupt. */ 7160 igb_write_itr(q_vector); 7161 7162 napi_schedule(&q_vector->napi); 7163 7164 return IRQ_HANDLED; 7165} 7166 7167#ifdef CONFIG_IGB_DCA 7168static void igb_update_tx_dca(struct igb_adapter *adapter, 7169 struct igb_ring *tx_ring, 7170 int cpu) 7171{ 7172 struct e1000_hw *hw = &adapter->hw; 7173 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7174 7175 if (hw->mac.type != e1000_82575) 7176 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7177 7178 /* We can enable relaxed ordering for reads, but not writes when 7179 * DCA is enabled. This is due to a known issue in some chipsets 7180 * which will cause the DCA tag to be cleared. 7181 */ 7182 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7183 E1000_DCA_TXCTRL_DATA_RRO_EN | 7184 E1000_DCA_TXCTRL_DESC_DCA_EN; 7185 7186 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7187} 7188 7189static void igb_update_rx_dca(struct igb_adapter *adapter, 7190 struct igb_ring *rx_ring, 7191 int cpu) 7192{ 7193 struct e1000_hw *hw = &adapter->hw; 7194 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7195 7196 if (hw->mac.type != e1000_82575) 7197 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7198 7199 /* We can enable relaxed ordering for reads, but not writes when 7200 * DCA is enabled. This is due to a known issue in some chipsets 7201 * which will cause the DCA tag to be cleared. 7202 */ 7203 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7204 E1000_DCA_RXCTRL_DESC_DCA_EN; 7205 7206 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7207} 7208 7209static void igb_update_dca(struct igb_q_vector *q_vector) 7210{ 7211 struct igb_adapter *adapter = q_vector->adapter; 7212 int cpu = get_cpu(); 7213 7214 if (q_vector->cpu == cpu) 7215 goto out_no_update; 7216 7217 if (q_vector->tx.ring) 7218 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7219 7220 if (q_vector->rx.ring) 7221 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7222 7223 q_vector->cpu = cpu; 7224out_no_update: 7225 put_cpu(); 7226} 7227 7228static void igb_setup_dca(struct igb_adapter *adapter) 7229{ 7230 struct e1000_hw *hw = &adapter->hw; 7231 int i; 7232 7233 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7234 return; 7235 7236 /* Always use CB2 mode, difference is masked in the CB driver. */ 7237 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7238 7239 for (i = 0; i < adapter->num_q_vectors; i++) { 7240 adapter->q_vector[i]->cpu = -1; 7241 igb_update_dca(adapter->q_vector[i]); 7242 } 7243} 7244 7245static int __igb_notify_dca(struct device *dev, void *data) 7246{ 7247 struct net_device *netdev = dev_get_drvdata(dev); 7248 struct igb_adapter *adapter = netdev_priv(netdev); 7249 struct pci_dev *pdev = adapter->pdev; 7250 struct e1000_hw *hw = &adapter->hw; 7251 unsigned long event = *(unsigned long *)data; 7252 7253 switch (event) { 7254 case DCA_PROVIDER_ADD: 7255 /* if already enabled, don't do it again */ 7256 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7257 break; 7258 if (dca_add_requester(dev) == 0) { 7259 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7260 dev_info(&pdev->dev, "DCA enabled\n"); 7261 igb_setup_dca(adapter); 7262 break; 7263 } 7264 fallthrough; /* since DCA is disabled. */ 7265 case DCA_PROVIDER_REMOVE: 7266 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7267 /* without this a class_device is left 7268 * hanging around in the sysfs model 7269 */ 7270 dca_remove_requester(dev); 7271 dev_info(&pdev->dev, "DCA disabled\n"); 7272 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7273 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7274 } 7275 break; 7276 } 7277 7278 return 0; 7279} 7280 7281static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7282 void *p) 7283{ 7284 int ret_val; 7285 7286 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7287 __igb_notify_dca); 7288 7289 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7290} 7291#endif /* CONFIG_IGB_DCA */ 7292 7293#ifdef CONFIG_PCI_IOV 7294static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7295{ 7296 unsigned char mac_addr[ETH_ALEN]; 7297 7298 eth_zero_addr(mac_addr); 7299 igb_set_vf_mac(adapter, vf, mac_addr); 7300 7301 /* By default spoof check is enabled for all VFs */ 7302 adapter->vf_data[vf].spoofchk_enabled = true; 7303 7304 /* By default VFs are not trusted */ 7305 adapter->vf_data[vf].trusted = false; 7306 7307 return 0; 7308} 7309 7310#endif 7311static void igb_ping_all_vfs(struct igb_adapter *adapter) 7312{ 7313 struct e1000_hw *hw = &adapter->hw; 7314 u32 ping; 7315 int i; 7316 7317 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7318 ping = E1000_PF_CONTROL_MSG; 7319 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7320 ping |= E1000_VT_MSGTYPE_CTS; 7321 igb_write_mbx(hw, &ping, 1, i); 7322 } 7323} 7324 7325static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7326{ 7327 struct e1000_hw *hw = &adapter->hw; 7328 u32 vmolr = rd32(E1000_VMOLR(vf)); 7329 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7330 7331 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7332 IGB_VF_FLAG_MULTI_PROMISC); 7333 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7334 7335 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7336 vmolr |= E1000_VMOLR_MPME; 7337 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7338 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7339 } else { 7340 /* if we have hashes and we are clearing a multicast promisc 7341 * flag we need to write the hashes to the MTA as this step 7342 * was previously skipped 7343 */ 7344 if (vf_data->num_vf_mc_hashes > 30) { 7345 vmolr |= E1000_VMOLR_MPME; 7346 } else if (vf_data->num_vf_mc_hashes) { 7347 int j; 7348 7349 vmolr |= E1000_VMOLR_ROMPE; 7350 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7351 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7352 } 7353 } 7354 7355 wr32(E1000_VMOLR(vf), vmolr); 7356 7357 /* there are flags left unprocessed, likely not supported */ 7358 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7359 return -EINVAL; 7360 7361 return 0; 7362} 7363 7364static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7365 u32 *msgbuf, u32 vf) 7366{ 7367 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7368 u16 *hash_list = (u16 *)&msgbuf[1]; 7369 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7370 int i; 7371 7372 /* salt away the number of multicast addresses assigned 7373 * to this VF for later use to restore when the PF multi cast 7374 * list changes 7375 */ 7376 vf_data->num_vf_mc_hashes = n; 7377 7378 /* only up to 30 hash values supported */ 7379 if (n > 30) 7380 n = 30; 7381 7382 /* store the hashes for later use */ 7383 for (i = 0; i < n; i++) 7384 vf_data->vf_mc_hashes[i] = hash_list[i]; 7385 7386 /* Flush and reset the mta with the new values */ 7387 igb_set_rx_mode(adapter->netdev); 7388 7389 return 0; 7390} 7391 7392static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7393{ 7394 struct e1000_hw *hw = &adapter->hw; 7395 struct vf_data_storage *vf_data; 7396 int i, j; 7397 7398 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7399 u32 vmolr = rd32(E1000_VMOLR(i)); 7400 7401 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7402 7403 vf_data = &adapter->vf_data[i]; 7404 7405 if ((vf_data->num_vf_mc_hashes > 30) || 7406 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7407 vmolr |= E1000_VMOLR_MPME; 7408 } else if (vf_data->num_vf_mc_hashes) { 7409 vmolr |= E1000_VMOLR_ROMPE; 7410 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7411 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7412 } 7413 wr32(E1000_VMOLR(i), vmolr); 7414 } 7415} 7416 7417static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7418{ 7419 struct e1000_hw *hw = &adapter->hw; 7420 u32 pool_mask, vlvf_mask, i; 7421 7422 /* create mask for VF and other pools */ 7423 pool_mask = E1000_VLVF_POOLSEL_MASK; 7424 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7425 7426 /* drop PF from pool bits */ 7427 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7428 adapter->vfs_allocated_count); 7429 7430 /* Find the vlan filter for this id */ 7431 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7432 u32 vlvf = rd32(E1000_VLVF(i)); 7433 u32 vfta_mask, vid, vfta; 7434 7435 /* remove the vf from the pool */ 7436 if (!(vlvf & vlvf_mask)) 7437 continue; 7438 7439 /* clear out bit from VLVF */ 7440 vlvf ^= vlvf_mask; 7441 7442 /* if other pools are present, just remove ourselves */ 7443 if (vlvf & pool_mask) 7444 goto update_vlvfb; 7445 7446 /* if PF is present, leave VFTA */ 7447 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7448 goto update_vlvf; 7449 7450 vid = vlvf & E1000_VLVF_VLANID_MASK; 7451 vfta_mask = BIT(vid % 32); 7452 7453 /* clear bit from VFTA */ 7454 vfta = adapter->shadow_vfta[vid / 32]; 7455 if (vfta & vfta_mask) 7456 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7457update_vlvf: 7458 /* clear pool selection enable */ 7459 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7460 vlvf &= E1000_VLVF_POOLSEL_MASK; 7461 else 7462 vlvf = 0; 7463update_vlvfb: 7464 /* clear pool bits */ 7465 wr32(E1000_VLVF(i), vlvf); 7466 } 7467} 7468 7469static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7470{ 7471 u32 vlvf; 7472 int idx; 7473 7474 /* short cut the special case */ 7475 if (vlan == 0) 7476 return 0; 7477 7478 /* Search for the VLAN id in the VLVF entries */ 7479 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7480 vlvf = rd32(E1000_VLVF(idx)); 7481 if ((vlvf & VLAN_VID_MASK) == vlan) 7482 break; 7483 } 7484 7485 return idx; 7486} 7487 7488static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7489{ 7490 struct e1000_hw *hw = &adapter->hw; 7491 u32 bits, pf_id; 7492 int idx; 7493 7494 idx = igb_find_vlvf_entry(hw, vid); 7495 if (!idx) 7496 return; 7497 7498 /* See if any other pools are set for this VLAN filter 7499 * entry other than the PF. 7500 */ 7501 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7502 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7503 bits &= rd32(E1000_VLVF(idx)); 7504 7505 /* Disable the filter so this falls into the default pool. */ 7506 if (!bits) { 7507 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7508 wr32(E1000_VLVF(idx), BIT(pf_id)); 7509 else 7510 wr32(E1000_VLVF(idx), 0); 7511 } 7512} 7513 7514static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7515 bool add, u32 vf) 7516{ 7517 int pf_id = adapter->vfs_allocated_count; 7518 struct e1000_hw *hw = &adapter->hw; 7519 int err; 7520 7521 /* If VLAN overlaps with one the PF is currently monitoring make 7522 * sure that we are able to allocate a VLVF entry. This may be 7523 * redundant but it guarantees PF will maintain visibility to 7524 * the VLAN. 7525 */ 7526 if (add && test_bit(vid, adapter->active_vlans)) { 7527 err = igb_vfta_set(hw, vid, pf_id, true, false); 7528 if (err) 7529 return err; 7530 } 7531 7532 err = igb_vfta_set(hw, vid, vf, add, false); 7533 7534 if (add && !err) 7535 return err; 7536 7537 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7538 * we may need to drop the PF pool bit in order to allow us to free 7539 * up the VLVF resources. 7540 */ 7541 if (test_bit(vid, adapter->active_vlans) || 7542 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7543 igb_update_pf_vlvf(adapter, vid); 7544 7545 return err; 7546} 7547 7548static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7549{ 7550 struct e1000_hw *hw = &adapter->hw; 7551 7552 if (vid) 7553 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7554 else 7555 wr32(E1000_VMVIR(vf), 0); 7556} 7557 7558static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7559 u16 vlan, u8 qos) 7560{ 7561 int err; 7562 7563 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7564 if (err) 7565 return err; 7566 7567 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7568 igb_set_vmolr(adapter, vf, !vlan); 7569 7570 /* revoke access to previous VLAN */ 7571 if (vlan != adapter->vf_data[vf].pf_vlan) 7572 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7573 false, vf); 7574 7575 adapter->vf_data[vf].pf_vlan = vlan; 7576 adapter->vf_data[vf].pf_qos = qos; 7577 igb_set_vf_vlan_strip(adapter, vf, true); 7578 dev_info(&adapter->pdev->dev, 7579 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7580 if (test_bit(__IGB_DOWN, &adapter->state)) { 7581 dev_warn(&adapter->pdev->dev, 7582 "The VF VLAN has been set, but the PF device is not up.\n"); 7583 dev_warn(&adapter->pdev->dev, 7584 "Bring the PF device up before attempting to use the VF device.\n"); 7585 } 7586 7587 return err; 7588} 7589 7590static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7591{ 7592 /* Restore tagless access via VLAN 0 */ 7593 igb_set_vf_vlan(adapter, 0, true, vf); 7594 7595 igb_set_vmvir(adapter, 0, vf); 7596 igb_set_vmolr(adapter, vf, true); 7597 7598 /* Remove any PF assigned VLAN */ 7599 if (adapter->vf_data[vf].pf_vlan) 7600 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7601 false, vf); 7602 7603 adapter->vf_data[vf].pf_vlan = 0; 7604 adapter->vf_data[vf].pf_qos = 0; 7605 igb_set_vf_vlan_strip(adapter, vf, false); 7606 7607 return 0; 7608} 7609 7610static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7611 u16 vlan, u8 qos, __be16 vlan_proto) 7612{ 7613 struct igb_adapter *adapter = netdev_priv(netdev); 7614 7615 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7616 return -EINVAL; 7617 7618 if (vlan_proto != htons(ETH_P_8021Q)) 7619 return -EPROTONOSUPPORT; 7620 7621 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7622 igb_disable_port_vlan(adapter, vf); 7623} 7624 7625static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7626{ 7627 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7628 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7629 int ret; 7630 7631 if (adapter->vf_data[vf].pf_vlan) 7632 return -1; 7633 7634 /* VLAN 0 is a special case, don't allow it to be removed */ 7635 if (!vid && !add) 7636 return 0; 7637 7638 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7639 if (!ret) 7640 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7641 return ret; 7642} 7643 7644static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7645{ 7646 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7647 7648 /* clear flags - except flag that indicates PF has set the MAC */ 7649 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7650 vf_data->last_nack = jiffies; 7651 7652 /* reset vlans for device */ 7653 igb_clear_vf_vfta(adapter, vf); 7654 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7655 igb_set_vmvir(adapter, vf_data->pf_vlan | 7656 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7657 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7658 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7659 7660 /* reset multicast table array for vf */ 7661 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7662 7663 /* Flush and reset the mta with the new values */ 7664 igb_set_rx_mode(adapter->netdev); 7665} 7666 7667static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7668{ 7669 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7670 7671 /* clear mac address as we were hotplug removed/added */ 7672 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7673 eth_zero_addr(vf_mac); 7674 7675 /* process remaining reset events */ 7676 igb_vf_reset(adapter, vf); 7677} 7678 7679static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7680{ 7681 struct e1000_hw *hw = &adapter->hw; 7682 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7683 u32 reg, msgbuf[3] = {}; 7684 u8 *addr = (u8 *)(&msgbuf[1]); 7685 7686 /* process all the same items cleared in a function level reset */ 7687 igb_vf_reset(adapter, vf); 7688 7689 /* set vf mac address */ 7690 igb_set_vf_mac(adapter, vf, vf_mac); 7691 7692 /* enable transmit and receive for vf */ 7693 reg = rd32(E1000_VFTE); 7694 wr32(E1000_VFTE, reg | BIT(vf)); 7695 reg = rd32(E1000_VFRE); 7696 wr32(E1000_VFRE, reg | BIT(vf)); 7697 7698 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7699 7700 /* reply to reset with ack and vf mac address */ 7701 if (!is_zero_ether_addr(vf_mac)) { 7702 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7703 memcpy(addr, vf_mac, ETH_ALEN); 7704 } else { 7705 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7706 } 7707 igb_write_mbx(hw, msgbuf, 3, vf); 7708} 7709 7710static void igb_flush_mac_table(struct igb_adapter *adapter) 7711{ 7712 struct e1000_hw *hw = &adapter->hw; 7713 int i; 7714 7715 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7716 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7717 eth_zero_addr(adapter->mac_table[i].addr); 7718 adapter->mac_table[i].queue = 0; 7719 igb_rar_set_index(adapter, i); 7720 } 7721} 7722 7723static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7724{ 7725 struct e1000_hw *hw = &adapter->hw; 7726 /* do not count rar entries reserved for VFs MAC addresses */ 7727 int rar_entries = hw->mac.rar_entry_count - 7728 adapter->vfs_allocated_count; 7729 int i, count = 0; 7730 7731 for (i = 0; i < rar_entries; i++) { 7732 /* do not count default entries */ 7733 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7734 continue; 7735 7736 /* do not count "in use" entries for different queues */ 7737 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7738 (adapter->mac_table[i].queue != queue)) 7739 continue; 7740 7741 count++; 7742 } 7743 7744 return count; 7745} 7746 7747/* Set default MAC address for the PF in the first RAR entry */ 7748static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7749{ 7750 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7751 7752 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7753 mac_table->queue = adapter->vfs_allocated_count; 7754 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7755 7756 igb_rar_set_index(adapter, 0); 7757} 7758 7759/* If the filter to be added and an already existing filter express 7760 * the same address and address type, it should be possible to only 7761 * override the other configurations, for example the queue to steer 7762 * traffic. 7763 */ 7764static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7765 const u8 *addr, const u8 flags) 7766{ 7767 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7768 return true; 7769 7770 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7771 (flags & IGB_MAC_STATE_SRC_ADDR)) 7772 return false; 7773 7774 if (!ether_addr_equal(addr, entry->addr)) 7775 return false; 7776 7777 return true; 7778} 7779 7780/* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7781 * 'flags' is used to indicate what kind of match is made, match is by 7782 * default for the destination address, if matching by source address 7783 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7784 */ 7785static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7786 const u8 *addr, const u8 queue, 7787 const u8 flags) 7788{ 7789 struct e1000_hw *hw = &adapter->hw; 7790 int rar_entries = hw->mac.rar_entry_count - 7791 adapter->vfs_allocated_count; 7792 int i; 7793 7794 if (is_zero_ether_addr(addr)) 7795 return -EINVAL; 7796 7797 /* Search for the first empty entry in the MAC table. 7798 * Do not touch entries at the end of the table reserved for the VF MAC 7799 * addresses. 7800 */ 7801 for (i = 0; i < rar_entries; i++) { 7802 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7803 addr, flags)) 7804 continue; 7805 7806 ether_addr_copy(adapter->mac_table[i].addr, addr); 7807 adapter->mac_table[i].queue = queue; 7808 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7809 7810 igb_rar_set_index(adapter, i); 7811 return i; 7812 } 7813 7814 return -ENOSPC; 7815} 7816 7817static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7818 const u8 queue) 7819{ 7820 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7821} 7822 7823/* Remove a MAC filter for 'addr' directing matching traffic to 7824 * 'queue', 'flags' is used to indicate what kind of match need to be 7825 * removed, match is by default for the destination address, if 7826 * matching by source address is to be removed the flag 7827 * IGB_MAC_STATE_SRC_ADDR can be used. 7828 */ 7829static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7830 const u8 *addr, const u8 queue, 7831 const u8 flags) 7832{ 7833 struct e1000_hw *hw = &adapter->hw; 7834 int rar_entries = hw->mac.rar_entry_count - 7835 adapter->vfs_allocated_count; 7836 int i; 7837 7838 if (is_zero_ether_addr(addr)) 7839 return -EINVAL; 7840 7841 /* Search for matching entry in the MAC table based on given address 7842 * and queue. Do not touch entries at the end of the table reserved 7843 * for the VF MAC addresses. 7844 */ 7845 for (i = 0; i < rar_entries; i++) { 7846 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7847 continue; 7848 if ((adapter->mac_table[i].state & flags) != flags) 7849 continue; 7850 if (adapter->mac_table[i].queue != queue) 7851 continue; 7852 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7853 continue; 7854 7855 /* When a filter for the default address is "deleted", 7856 * we return it to its initial configuration 7857 */ 7858 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7859 adapter->mac_table[i].state = 7860 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7861 adapter->mac_table[i].queue = 7862 adapter->vfs_allocated_count; 7863 } else { 7864 adapter->mac_table[i].state = 0; 7865 adapter->mac_table[i].queue = 0; 7866 eth_zero_addr(adapter->mac_table[i].addr); 7867 } 7868 7869 igb_rar_set_index(adapter, i); 7870 return 0; 7871 } 7872 7873 return -ENOENT; 7874} 7875 7876static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7877 const u8 queue) 7878{ 7879 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7880} 7881 7882int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7883 const u8 *addr, u8 queue, u8 flags) 7884{ 7885 struct e1000_hw *hw = &adapter->hw; 7886 7887 /* In theory, this should be supported on 82575 as well, but 7888 * that part wasn't easily accessible during development. 7889 */ 7890 if (hw->mac.type != e1000_i210) 7891 return -EOPNOTSUPP; 7892 7893 return igb_add_mac_filter_flags(adapter, addr, queue, 7894 IGB_MAC_STATE_QUEUE_STEERING | flags); 7895} 7896 7897int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7898 const u8 *addr, u8 queue, u8 flags) 7899{ 7900 return igb_del_mac_filter_flags(adapter, addr, queue, 7901 IGB_MAC_STATE_QUEUE_STEERING | flags); 7902} 7903 7904static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7905{ 7906 struct igb_adapter *adapter = netdev_priv(netdev); 7907 int ret; 7908 7909 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7910 7911 return min_t(int, ret, 0); 7912} 7913 7914static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7915{ 7916 struct igb_adapter *adapter = netdev_priv(netdev); 7917 7918 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7919 7920 return 0; 7921} 7922 7923static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7924 const u32 info, const u8 *addr) 7925{ 7926 struct pci_dev *pdev = adapter->pdev; 7927 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7928 struct vf_mac_filter *entry; 7929 bool found = false; 7930 int ret = 0; 7931 7932 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7933 !vf_data->trusted) { 7934 dev_warn(&pdev->dev, 7935 "VF %d requested MAC filter but is administratively denied\n", 7936 vf); 7937 return -EINVAL; 7938 } 7939 if (!is_valid_ether_addr(addr)) { 7940 dev_warn(&pdev->dev, 7941 "VF %d attempted to set invalid MAC filter\n", 7942 vf); 7943 return -EINVAL; 7944 } 7945 7946 switch (info) { 7947 case E1000_VF_MAC_FILTER_CLR: 7948 /* remove all unicast MAC filters related to the current VF */ 7949 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7950 if (entry->vf == vf) { 7951 entry->vf = -1; 7952 entry->free = true; 7953 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7954 } 7955 } 7956 break; 7957 case E1000_VF_MAC_FILTER_ADD: 7958 /* try to find empty slot in the list */ 7959 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7960 if (entry->free) { 7961 found = true; 7962 break; 7963 } 7964 } 7965 7966 if (found) { 7967 entry->free = false; 7968 entry->vf = vf; 7969 ether_addr_copy(entry->vf_mac, addr); 7970 7971 ret = igb_add_mac_filter(adapter, addr, vf); 7972 ret = min_t(int, ret, 0); 7973 } else { 7974 ret = -ENOSPC; 7975 } 7976 7977 if (ret == -ENOSPC) 7978 dev_warn(&pdev->dev, 7979 "VF %d has requested MAC filter but there is no space for it\n", 7980 vf); 7981 break; 7982 default: 7983 ret = -EINVAL; 7984 break; 7985 } 7986 7987 return ret; 7988} 7989 7990static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7991{ 7992 struct pci_dev *pdev = adapter->pdev; 7993 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7994 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7995 7996 /* The VF MAC Address is stored in a packed array of bytes 7997 * starting at the second 32 bit word of the msg array 7998 */ 7999 unsigned char *addr = (unsigned char *)&msg[1]; 8000 int ret = 0; 8001 8002 if (!info) { 8003 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 8004 !vf_data->trusted) { 8005 dev_warn(&pdev->dev, 8006 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 8007 vf); 8008 return -EINVAL; 8009 } 8010 8011 if (!is_valid_ether_addr(addr)) { 8012 dev_warn(&pdev->dev, 8013 "VF %d attempted to set invalid MAC\n", 8014 vf); 8015 return -EINVAL; 8016 } 8017 8018 ret = igb_set_vf_mac(adapter, vf, addr); 8019 } else { 8020 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 8021 } 8022 8023 return ret; 8024} 8025 8026static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 8027{ 8028 struct e1000_hw *hw = &adapter->hw; 8029 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8030 u32 msg = E1000_VT_MSGTYPE_NACK; 8031 8032 /* if device isn't clear to send it shouldn't be reading either */ 8033 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 8034 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 8035 igb_write_mbx(hw, &msg, 1, vf); 8036 vf_data->last_nack = jiffies; 8037 } 8038} 8039 8040static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 8041{ 8042 struct pci_dev *pdev = adapter->pdev; 8043 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 8044 struct e1000_hw *hw = &adapter->hw; 8045 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8046 s32 retval; 8047 8048 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 8049 8050 if (retval) { 8051 /* if receive failed revoke VF CTS stats and restart init */ 8052 dev_err(&pdev->dev, "Error receiving message from VF\n"); 8053 vf_data->flags &= ~IGB_VF_FLAG_CTS; 8054 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8055 goto unlock; 8056 goto out; 8057 } 8058 8059 /* this is a message we already processed, do nothing */ 8060 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 8061 goto unlock; 8062 8063 /* until the vf completes a reset it should not be 8064 * allowed to start any configuration. 8065 */ 8066 if (msgbuf[0] == E1000_VF_RESET) { 8067 /* unlocks mailbox */ 8068 igb_vf_reset_msg(adapter, vf); 8069 return; 8070 } 8071 8072 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 8073 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8074 goto unlock; 8075 retval = -1; 8076 goto out; 8077 } 8078 8079 switch ((msgbuf[0] & 0xFFFF)) { 8080 case E1000_VF_SET_MAC_ADDR: 8081 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 8082 break; 8083 case E1000_VF_SET_PROMISC: 8084 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 8085 break; 8086 case E1000_VF_SET_MULTICAST: 8087 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 8088 break; 8089 case E1000_VF_SET_LPE: 8090 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8091 break; 8092 case E1000_VF_SET_VLAN: 8093 retval = -1; 8094 if (vf_data->pf_vlan) 8095 dev_warn(&pdev->dev, 8096 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8097 vf); 8098 else 8099 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8100 break; 8101 default: 8102 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8103 retval = -1; 8104 break; 8105 } 8106 8107 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8108out: 8109 /* notify the VF of the results of what it sent us */ 8110 if (retval) 8111 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8112 else 8113 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8114 8115 /* unlocks mailbox */ 8116 igb_write_mbx(hw, msgbuf, 1, vf); 8117 return; 8118 8119unlock: 8120 igb_unlock_mbx(hw, vf); 8121} 8122 8123static void igb_msg_task(struct igb_adapter *adapter) 8124{ 8125 struct e1000_hw *hw = &adapter->hw; 8126 unsigned long flags; 8127 u32 vf; 8128 8129 spin_lock_irqsave(&adapter->vfs_lock, flags); 8130 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8131 /* process any reset requests */ 8132 if (!igb_check_for_rst(hw, vf)) 8133 igb_vf_reset_event(adapter, vf); 8134 8135 /* process any messages pending */ 8136 if (!igb_check_for_msg(hw, vf)) 8137 igb_rcv_msg_from_vf(adapter, vf); 8138 8139 /* process any acks */ 8140 if (!igb_check_for_ack(hw, vf)) 8141 igb_rcv_ack_from_vf(adapter, vf); 8142 } 8143 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8144} 8145 8146/** 8147 * igb_set_uta - Set unicast filter table address 8148 * @adapter: board private structure 8149 * @set: boolean indicating if we are setting or clearing bits 8150 * 8151 * The unicast table address is a register array of 32-bit registers. 8152 * The table is meant to be used in a way similar to how the MTA is used 8153 * however due to certain limitations in the hardware it is necessary to 8154 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8155 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8156 **/ 8157static void igb_set_uta(struct igb_adapter *adapter, bool set) 8158{ 8159 struct e1000_hw *hw = &adapter->hw; 8160 u32 uta = set ? ~0 : 0; 8161 int i; 8162 8163 /* we only need to do this if VMDq is enabled */ 8164 if (!adapter->vfs_allocated_count) 8165 return; 8166 8167 for (i = hw->mac.uta_reg_count; i--;) 8168 array_wr32(E1000_UTA, i, uta); 8169} 8170 8171/** 8172 * igb_intr_msi - Interrupt Handler 8173 * @irq: interrupt number 8174 * @data: pointer to a network interface device structure 8175 **/ 8176static irqreturn_t igb_intr_msi(int irq, void *data) 8177{ 8178 struct igb_adapter *adapter = data; 8179 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8180 struct e1000_hw *hw = &adapter->hw; 8181 /* read ICR disables interrupts using IAM */ 8182 u32 icr = rd32(E1000_ICR); 8183 8184 igb_write_itr(q_vector); 8185 8186 if (icr & E1000_ICR_DRSTA) 8187 schedule_work(&adapter->reset_task); 8188 8189 if (icr & E1000_ICR_DOUTSYNC) { 8190 /* HW is reporting DMA is out of sync */ 8191 adapter->stats.doosync++; 8192 } 8193 8194 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8195 hw->mac.get_link_status = 1; 8196 if (!test_bit(__IGB_DOWN, &adapter->state)) 8197 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8198 } 8199 8200 if (icr & E1000_ICR_TS) 8201 igb_tsync_interrupt(adapter); 8202 8203 napi_schedule(&q_vector->napi); 8204 8205 return IRQ_HANDLED; 8206} 8207 8208/** 8209 * igb_intr - Legacy Interrupt Handler 8210 * @irq: interrupt number 8211 * @data: pointer to a network interface device structure 8212 **/ 8213static irqreturn_t igb_intr(int irq, void *data) 8214{ 8215 struct igb_adapter *adapter = data; 8216 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8217 struct e1000_hw *hw = &adapter->hw; 8218 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8219 * need for the IMC write 8220 */ 8221 u32 icr = rd32(E1000_ICR); 8222 8223 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8224 * not set, then the adapter didn't send an interrupt 8225 */ 8226 if (!(icr & E1000_ICR_INT_ASSERTED)) 8227 return IRQ_NONE; 8228 8229 igb_write_itr(q_vector); 8230 8231 if (icr & E1000_ICR_DRSTA) 8232 schedule_work(&adapter->reset_task); 8233 8234 if (icr & E1000_ICR_DOUTSYNC) { 8235 /* HW is reporting DMA is out of sync */ 8236 adapter->stats.doosync++; 8237 } 8238 8239 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8240 hw->mac.get_link_status = 1; 8241 /* guard against interrupt when we're going down */ 8242 if (!test_bit(__IGB_DOWN, &adapter->state)) 8243 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8244 } 8245 8246 if (icr & E1000_ICR_TS) 8247 igb_tsync_interrupt(adapter); 8248 8249 napi_schedule(&q_vector->napi); 8250 8251 return IRQ_HANDLED; 8252} 8253 8254static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8255{ 8256 struct igb_adapter *adapter = q_vector->adapter; 8257 struct e1000_hw *hw = &adapter->hw; 8258 8259 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8260 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8261 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8262 igb_set_itr(q_vector); 8263 else 8264 igb_update_ring_itr(q_vector); 8265 } 8266 8267 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8268 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8269 wr32(E1000_EIMS, q_vector->eims_value); 8270 else 8271 igb_irq_enable(adapter); 8272 } 8273} 8274 8275/** 8276 * igb_poll - NAPI Rx polling callback 8277 * @napi: napi polling structure 8278 * @budget: count of how many packets we should handle 8279 **/ 8280static int igb_poll(struct napi_struct *napi, int budget) 8281{ 8282 struct igb_q_vector *q_vector = container_of(napi, 8283 struct igb_q_vector, 8284 napi); 8285 struct xsk_buff_pool *xsk_pool; 8286 bool clean_complete = true; 8287 int work_done = 0; 8288 8289#ifdef CONFIG_IGB_DCA 8290 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8291 igb_update_dca(q_vector); 8292#endif 8293 if (q_vector->tx.ring) 8294 clean_complete = igb_clean_tx_irq(q_vector, budget); 8295 8296 if (q_vector->rx.ring) { 8297 int cleaned; 8298 8299 xsk_pool = READ_ONCE(q_vector->rx.ring->xsk_pool); 8300 cleaned = xsk_pool ? 8301 igb_clean_rx_irq_zc(q_vector, xsk_pool, budget) : 8302 igb_clean_rx_irq(q_vector, budget); 8303 8304 work_done += cleaned; 8305 if (cleaned >= budget) 8306 clean_complete = false; 8307 } 8308 8309 /* If all work not completed, return budget and keep polling */ 8310 if (!clean_complete) 8311 return budget; 8312 8313 /* Exit the polling mode, but don't re-enable interrupts if stack might 8314 * poll us due to busy-polling 8315 */ 8316 if (likely(napi_complete_done(napi, work_done))) 8317 igb_ring_irq_enable(q_vector); 8318 8319 return work_done; 8320} 8321 8322/** 8323 * igb_clean_tx_irq - Reclaim resources after transmit completes 8324 * @q_vector: pointer to q_vector containing needed info 8325 * @napi_budget: Used to determine if we are in netpoll 8326 * 8327 * returns true if ring is completely cleaned 8328 **/ 8329static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8330{ 8331 unsigned int total_bytes = 0, total_packets = 0; 8332 struct igb_adapter *adapter = q_vector->adapter; 8333 unsigned int budget = q_vector->tx.work_limit; 8334 struct igb_ring *tx_ring = q_vector->tx.ring; 8335 unsigned int i = tx_ring->next_to_clean; 8336 union e1000_adv_tx_desc *tx_desc; 8337 struct igb_tx_buffer *tx_buffer; 8338 struct xsk_buff_pool *xsk_pool; 8339 int cpu = smp_processor_id(); 8340 bool xsk_xmit_done = true; 8341 struct netdev_queue *nq; 8342 u32 xsk_frames = 0; 8343 8344 if (test_bit(__IGB_DOWN, &adapter->state)) 8345 return true; 8346 8347 tx_buffer = &tx_ring->tx_buffer_info[i]; 8348 tx_desc = IGB_TX_DESC(tx_ring, i); 8349 i -= tx_ring->count; 8350 8351 do { 8352 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8353 8354 /* if next_to_watch is not set then there is no work pending */ 8355 if (!eop_desc) 8356 break; 8357 8358 /* prevent any other reads prior to eop_desc */ 8359 smp_rmb(); 8360 8361 /* if DD is not set pending work has not been completed */ 8362 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8363 break; 8364 8365 /* clear next_to_watch to prevent false hangs */ 8366 tx_buffer->next_to_watch = NULL; 8367 8368 /* update the statistics for this packet */ 8369 total_bytes += tx_buffer->bytecount; 8370 total_packets += tx_buffer->gso_segs; 8371 8372 /* free the skb */ 8373 if (tx_buffer->type == IGB_TYPE_SKB) { 8374 napi_consume_skb(tx_buffer->skb, napi_budget); 8375 } else if (tx_buffer->type == IGB_TYPE_XDP) { 8376 xdp_return_frame(tx_buffer->xdpf); 8377 } else if (tx_buffer->type == IGB_TYPE_XSK) { 8378 xsk_frames++; 8379 goto skip_for_xsk; 8380 } 8381 8382 /* unmap skb header data */ 8383 dma_unmap_single(tx_ring->dev, 8384 dma_unmap_addr(tx_buffer, dma), 8385 dma_unmap_len(tx_buffer, len), 8386 DMA_TO_DEVICE); 8387 8388 /* clear tx_buffer data */ 8389 dma_unmap_len_set(tx_buffer, len, 0); 8390 8391 /* clear last DMA location and unmap remaining buffers */ 8392 while (tx_desc != eop_desc) { 8393 tx_buffer++; 8394 tx_desc++; 8395 i++; 8396 if (unlikely(!i)) { 8397 i -= tx_ring->count; 8398 tx_buffer = tx_ring->tx_buffer_info; 8399 tx_desc = IGB_TX_DESC(tx_ring, 0); 8400 } 8401 8402 /* unmap any remaining paged data */ 8403 if (dma_unmap_len(tx_buffer, len)) { 8404 dma_unmap_page(tx_ring->dev, 8405 dma_unmap_addr(tx_buffer, dma), 8406 dma_unmap_len(tx_buffer, len), 8407 DMA_TO_DEVICE); 8408 dma_unmap_len_set(tx_buffer, len, 0); 8409 } 8410 } 8411 8412skip_for_xsk: 8413 /* move us one more past the eop_desc for start of next pkt */ 8414 tx_buffer++; 8415 tx_desc++; 8416 i++; 8417 if (unlikely(!i)) { 8418 i -= tx_ring->count; 8419 tx_buffer = tx_ring->tx_buffer_info; 8420 tx_desc = IGB_TX_DESC(tx_ring, 0); 8421 } 8422 8423 /* issue prefetch for next Tx descriptor */ 8424 prefetch(tx_desc); 8425 8426 /* update budget accounting */ 8427 budget--; 8428 } while (likely(budget)); 8429 8430 netdev_tx_completed_queue(txring_txq(tx_ring), 8431 total_packets, total_bytes); 8432 i += tx_ring->count; 8433 tx_ring->next_to_clean = i; 8434 u64_stats_update_begin(&tx_ring->tx_syncp); 8435 tx_ring->tx_stats.bytes += total_bytes; 8436 tx_ring->tx_stats.packets += total_packets; 8437 u64_stats_update_end(&tx_ring->tx_syncp); 8438 q_vector->tx.total_bytes += total_bytes; 8439 q_vector->tx.total_packets += total_packets; 8440 8441 xsk_pool = READ_ONCE(tx_ring->xsk_pool); 8442 if (xsk_pool) { 8443 if (xsk_frames) 8444 xsk_tx_completed(xsk_pool, xsk_frames); 8445 if (xsk_uses_need_wakeup(xsk_pool)) 8446 xsk_set_tx_need_wakeup(xsk_pool); 8447 8448 nq = txring_txq(tx_ring); 8449 __netif_tx_lock(nq, cpu); 8450 /* Avoid transmit queue timeout since we share it with the slow path */ 8451 txq_trans_cond_update(nq); 8452 xsk_xmit_done = igb_xmit_zc(tx_ring, xsk_pool); 8453 __netif_tx_unlock(nq); 8454 } 8455 8456 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8457 struct e1000_hw *hw = &adapter->hw; 8458 8459 /* Detect a transmit hang in hardware, this serializes the 8460 * check with the clearing of time_stamp and movement of i 8461 */ 8462 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8463 if (tx_buffer->next_to_watch && 8464 time_after(jiffies, tx_buffer->time_stamp + 8465 (adapter->tx_timeout_factor * HZ)) && 8466 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8467 8468 /* detected Tx unit hang */ 8469 dev_err(tx_ring->dev, 8470 "Detected Tx Unit Hang\n" 8471 " Tx Queue <%d>\n" 8472 " TDH <%x>\n" 8473 " TDT <%x>\n" 8474 " next_to_use <%x>\n" 8475 " next_to_clean <%x>\n" 8476 "buffer_info[next_to_clean]\n" 8477 " time_stamp <%lx>\n" 8478 " next_to_watch <%p>\n" 8479 " jiffies <%lx>\n" 8480 " desc.status <%x>\n", 8481 tx_ring->queue_index, 8482 rd32(E1000_TDH(tx_ring->reg_idx)), 8483 readl(tx_ring->tail), 8484 tx_ring->next_to_use, 8485 tx_ring->next_to_clean, 8486 tx_buffer->time_stamp, 8487 tx_buffer->next_to_watch, 8488 jiffies, 8489 tx_buffer->next_to_watch->wb.status); 8490 netif_stop_subqueue(tx_ring->netdev, 8491 tx_ring->queue_index); 8492 8493 /* we are about to reset, no point in enabling stuff */ 8494 return true; 8495 } 8496 } 8497 8498#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8499 if (unlikely(total_packets && 8500 netif_carrier_ok(tx_ring->netdev) && 8501 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8502 /* Make sure that anybody stopping the queue after this 8503 * sees the new next_to_clean. 8504 */ 8505 smp_mb(); 8506 if (__netif_subqueue_stopped(tx_ring->netdev, 8507 tx_ring->queue_index) && 8508 !(test_bit(__IGB_DOWN, &adapter->state))) { 8509 netif_wake_subqueue(tx_ring->netdev, 8510 tx_ring->queue_index); 8511 8512 u64_stats_update_begin(&tx_ring->tx_syncp); 8513 tx_ring->tx_stats.restart_queue++; 8514 u64_stats_update_end(&tx_ring->tx_syncp); 8515 } 8516 } 8517 8518 return !!budget && xsk_xmit_done; 8519} 8520 8521/** 8522 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8523 * @rx_ring: rx descriptor ring to store buffers on 8524 * @old_buff: donor buffer to have page reused 8525 * 8526 * Synchronizes page for reuse by the adapter 8527 **/ 8528static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8529 struct igb_rx_buffer *old_buff) 8530{ 8531 struct igb_rx_buffer *new_buff; 8532 u16 nta = rx_ring->next_to_alloc; 8533 8534 new_buff = &rx_ring->rx_buffer_info[nta]; 8535 8536 /* update, and store next to alloc */ 8537 nta++; 8538 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8539 8540 /* Transfer page from old buffer to new buffer. 8541 * Move each member individually to avoid possible store 8542 * forwarding stalls. 8543 */ 8544 new_buff->dma = old_buff->dma; 8545 new_buff->page = old_buff->page; 8546 new_buff->page_offset = old_buff->page_offset; 8547 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8548} 8549 8550static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8551 int rx_buf_pgcnt) 8552{ 8553 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8554 struct page *page = rx_buffer->page; 8555 8556 /* avoid re-using remote and pfmemalloc pages */ 8557 if (!dev_page_is_reusable(page)) 8558 return false; 8559 8560#if (PAGE_SIZE < 8192) 8561 /* if we are only owner of page we can reuse it */ 8562 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8563 return false; 8564#else 8565#define IGB_LAST_OFFSET \ 8566 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8567 8568 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8569 return false; 8570#endif 8571 8572 /* If we have drained the page fragment pool we need to update 8573 * the pagecnt_bias and page count so that we fully restock the 8574 * number of references the driver holds. 8575 */ 8576 if (unlikely(pagecnt_bias == 1)) { 8577 page_ref_add(page, USHRT_MAX - 1); 8578 rx_buffer->pagecnt_bias = USHRT_MAX; 8579 } 8580 8581 return true; 8582} 8583 8584/** 8585 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8586 * @rx_ring: rx descriptor ring to transact packets on 8587 * @rx_buffer: buffer containing page to add 8588 * @skb: sk_buff to place the data into 8589 * @size: size of buffer to be added 8590 * 8591 * This function will add the data contained in rx_buffer->page to the skb. 8592 **/ 8593static void igb_add_rx_frag(struct igb_ring *rx_ring, 8594 struct igb_rx_buffer *rx_buffer, 8595 struct sk_buff *skb, 8596 unsigned int size) 8597{ 8598#if (PAGE_SIZE < 8192) 8599 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8600#else 8601 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8602 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8603 SKB_DATA_ALIGN(size); 8604#endif 8605 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8606 rx_buffer->page_offset, size, truesize); 8607#if (PAGE_SIZE < 8192) 8608 rx_buffer->page_offset ^= truesize; 8609#else 8610 rx_buffer->page_offset += truesize; 8611#endif 8612} 8613 8614static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8615 struct igb_rx_buffer *rx_buffer, 8616 struct xdp_buff *xdp, 8617 ktime_t timestamp) 8618{ 8619#if (PAGE_SIZE < 8192) 8620 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8621#else 8622 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8623 xdp->data_hard_start); 8624#endif 8625 unsigned int size = xdp->data_end - xdp->data; 8626 unsigned int headlen; 8627 struct sk_buff *skb; 8628 8629 /* prefetch first cache line of first page */ 8630 net_prefetch(xdp->data); 8631 8632 /* allocate a skb to store the frags */ 8633 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8634 if (unlikely(!skb)) 8635 return NULL; 8636 8637 if (timestamp) 8638 skb_hwtstamps(skb)->hwtstamp = timestamp; 8639 8640 /* Determine available headroom for copy */ 8641 headlen = size; 8642 if (headlen > IGB_RX_HDR_LEN) 8643 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8644 8645 /* align pull length to size of long to optimize memcpy performance */ 8646 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8647 8648 /* update all of the pointers */ 8649 size -= headlen; 8650 if (size) { 8651 skb_add_rx_frag(skb, 0, rx_buffer->page, 8652 (xdp->data + headlen) - page_address(rx_buffer->page), 8653 size, truesize); 8654#if (PAGE_SIZE < 8192) 8655 rx_buffer->page_offset ^= truesize; 8656#else 8657 rx_buffer->page_offset += truesize; 8658#endif 8659 } else { 8660 rx_buffer->pagecnt_bias++; 8661 } 8662 8663 return skb; 8664} 8665 8666static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8667 struct igb_rx_buffer *rx_buffer, 8668 struct xdp_buff *xdp, 8669 ktime_t timestamp) 8670{ 8671#if (PAGE_SIZE < 8192) 8672 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8673#else 8674 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8675 SKB_DATA_ALIGN(xdp->data_end - 8676 xdp->data_hard_start); 8677#endif 8678 unsigned int metasize = xdp->data - xdp->data_meta; 8679 struct sk_buff *skb; 8680 8681 /* prefetch first cache line of first page */ 8682 net_prefetch(xdp->data_meta); 8683 8684 /* build an skb around the page buffer */ 8685 skb = napi_build_skb(xdp->data_hard_start, truesize); 8686 if (unlikely(!skb)) 8687 return NULL; 8688 8689 /* update pointers within the skb to store the data */ 8690 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8691 __skb_put(skb, xdp->data_end - xdp->data); 8692 8693 if (metasize) 8694 skb_metadata_set(skb, metasize); 8695 8696 if (timestamp) 8697 skb_hwtstamps(skb)->hwtstamp = timestamp; 8698 8699 /* update buffer offset */ 8700#if (PAGE_SIZE < 8192) 8701 rx_buffer->page_offset ^= truesize; 8702#else 8703 rx_buffer->page_offset += truesize; 8704#endif 8705 8706 return skb; 8707} 8708 8709static int igb_run_xdp(struct igb_adapter *adapter, struct igb_ring *rx_ring, 8710 struct xdp_buff *xdp) 8711{ 8712 int err, result = IGB_XDP_PASS; 8713 struct bpf_prog *xdp_prog; 8714 u32 act; 8715 8716 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8717 8718 if (!xdp_prog) 8719 goto xdp_out; 8720 8721 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8722 8723 act = bpf_prog_run_xdp(xdp_prog, xdp); 8724 switch (act) { 8725 case XDP_PASS: 8726 break; 8727 case XDP_TX: 8728 result = igb_xdp_xmit_back(adapter, xdp); 8729 if (result == IGB_XDP_CONSUMED) 8730 goto out_failure; 8731 break; 8732 case XDP_REDIRECT: 8733 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8734 if (err) 8735 goto out_failure; 8736 result = IGB_XDP_REDIR; 8737 break; 8738 default: 8739 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8740 fallthrough; 8741 case XDP_ABORTED: 8742out_failure: 8743 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8744 fallthrough; 8745 case XDP_DROP: 8746 result = IGB_XDP_CONSUMED; 8747 break; 8748 } 8749xdp_out: 8750 return result; 8751} 8752 8753static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8754 unsigned int size) 8755{ 8756 unsigned int truesize; 8757 8758#if (PAGE_SIZE < 8192) 8759 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8760#else 8761 truesize = ring_uses_build_skb(rx_ring) ? 8762 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8763 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8764 SKB_DATA_ALIGN(size); 8765#endif 8766 return truesize; 8767} 8768 8769static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8770 struct igb_rx_buffer *rx_buffer, 8771 unsigned int size) 8772{ 8773 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8774#if (PAGE_SIZE < 8192) 8775 rx_buffer->page_offset ^= truesize; 8776#else 8777 rx_buffer->page_offset += truesize; 8778#endif 8779} 8780 8781static inline void igb_rx_checksum(struct igb_ring *ring, 8782 union e1000_adv_rx_desc *rx_desc, 8783 struct sk_buff *skb) 8784{ 8785 skb_checksum_none_assert(skb); 8786 8787 /* Ignore Checksum bit is set */ 8788 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8789 return; 8790 8791 /* Rx checksum disabled via ethtool */ 8792 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8793 return; 8794 8795 /* TCP/UDP checksum error bit is set */ 8796 if (igb_test_staterr(rx_desc, 8797 E1000_RXDEXT_STATERR_TCPE | 8798 E1000_RXDEXT_STATERR_IPE)) { 8799 /* work around errata with sctp packets where the TCPE aka 8800 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8801 * packets, (aka let the stack check the crc32c) 8802 */ 8803 if (!((skb->len == 60) && 8804 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8805 u64_stats_update_begin(&ring->rx_syncp); 8806 ring->rx_stats.csum_err++; 8807 u64_stats_update_end(&ring->rx_syncp); 8808 } 8809 /* let the stack verify checksum errors */ 8810 return; 8811 } 8812 /* It must be a TCP or UDP packet with a valid checksum */ 8813 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8814 E1000_RXD_STAT_UDPCS)) 8815 skb->ip_summed = CHECKSUM_UNNECESSARY; 8816 8817 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8818 le32_to_cpu(rx_desc->wb.upper.status_error)); 8819} 8820 8821static inline void igb_rx_hash(struct igb_ring *ring, 8822 union e1000_adv_rx_desc *rx_desc, 8823 struct sk_buff *skb) 8824{ 8825 if (ring->netdev->features & NETIF_F_RXHASH) 8826 skb_set_hash(skb, 8827 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8828 PKT_HASH_TYPE_L3); 8829} 8830 8831/** 8832 * igb_is_non_eop - process handling of non-EOP buffers 8833 * @rx_ring: Rx ring being processed 8834 * @rx_desc: Rx descriptor for current buffer 8835 * 8836 * This function updates next to clean. If the buffer is an EOP buffer 8837 * this function exits returning false, otherwise it will place the 8838 * sk_buff in the next buffer to be chained and return true indicating 8839 * that this is in fact a non-EOP buffer. 8840 **/ 8841static bool igb_is_non_eop(struct igb_ring *rx_ring, 8842 union e1000_adv_rx_desc *rx_desc) 8843{ 8844 u32 ntc = rx_ring->next_to_clean + 1; 8845 8846 /* fetch, update, and store next to clean */ 8847 ntc = (ntc < rx_ring->count) ? ntc : 0; 8848 rx_ring->next_to_clean = ntc; 8849 8850 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8851 8852 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8853 return false; 8854 8855 return true; 8856} 8857 8858/** 8859 * igb_cleanup_headers - Correct corrupted or empty headers 8860 * @rx_ring: rx descriptor ring packet is being transacted on 8861 * @rx_desc: pointer to the EOP Rx descriptor 8862 * @skb: pointer to current skb being fixed 8863 * 8864 * Address the case where we are pulling data in on pages only 8865 * and as such no data is present in the skb header. 8866 * 8867 * In addition if skb is not at least 60 bytes we need to pad it so that 8868 * it is large enough to qualify as a valid Ethernet frame. 8869 * 8870 * Returns true if an error was encountered and skb was freed. 8871 **/ 8872static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8873 union e1000_adv_rx_desc *rx_desc, 8874 struct sk_buff *skb) 8875{ 8876 if (unlikely((igb_test_staterr(rx_desc, 8877 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8878 struct net_device *netdev = rx_ring->netdev; 8879 if (!(netdev->features & NETIF_F_RXALL)) { 8880 dev_kfree_skb_any(skb); 8881 return true; 8882 } 8883 } 8884 8885 /* if eth_skb_pad returns an error the skb was freed */ 8886 if (eth_skb_pad(skb)) 8887 return true; 8888 8889 return false; 8890} 8891 8892/** 8893 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8894 * @rx_ring: rx descriptor ring packet is being transacted on 8895 * @rx_desc: pointer to the EOP Rx descriptor 8896 * @skb: pointer to current skb being populated 8897 * 8898 * This function checks the ring, descriptor, and packet information in 8899 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8900 * other fields within the skb. 8901 **/ 8902void igb_process_skb_fields(struct igb_ring *rx_ring, 8903 union e1000_adv_rx_desc *rx_desc, 8904 struct sk_buff *skb) 8905{ 8906 struct net_device *dev = rx_ring->netdev; 8907 8908 igb_rx_hash(rx_ring, rx_desc, skb); 8909 8910 igb_rx_checksum(rx_ring, rx_desc, skb); 8911 8912 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8913 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8914 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8915 8916 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8917 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8918 u16 vid; 8919 8920 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8921 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8922 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8923 else 8924 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8925 8926 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8927 } 8928 8929 skb_record_rx_queue(skb, rx_ring->queue_index); 8930 8931 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8932} 8933 8934static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8935{ 8936 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8937} 8938 8939static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8940 const unsigned int size, int *rx_buf_pgcnt) 8941{ 8942 struct igb_rx_buffer *rx_buffer; 8943 8944 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8945 *rx_buf_pgcnt = 8946#if (PAGE_SIZE < 8192) 8947 page_count(rx_buffer->page); 8948#else 8949 0; 8950#endif 8951 prefetchw(rx_buffer->page); 8952 8953 /* we are reusing so sync this buffer for CPU use */ 8954 dma_sync_single_range_for_cpu(rx_ring->dev, 8955 rx_buffer->dma, 8956 rx_buffer->page_offset, 8957 size, 8958 DMA_FROM_DEVICE); 8959 8960 rx_buffer->pagecnt_bias--; 8961 8962 return rx_buffer; 8963} 8964 8965static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8966 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8967{ 8968 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8969 /* hand second half of page back to the ring */ 8970 igb_reuse_rx_page(rx_ring, rx_buffer); 8971 } else { 8972 /* We are not reusing the buffer so unmap it and free 8973 * any references we are holding to it 8974 */ 8975 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8976 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8977 IGB_RX_DMA_ATTR); 8978 __page_frag_cache_drain(rx_buffer->page, 8979 rx_buffer->pagecnt_bias); 8980 } 8981 8982 /* clear contents of rx_buffer */ 8983 rx_buffer->page = NULL; 8984} 8985 8986void igb_finalize_xdp(struct igb_adapter *adapter, unsigned int status) 8987{ 8988 int cpu = smp_processor_id(); 8989 struct netdev_queue *nq; 8990 8991 if (status & IGB_XDP_REDIR) 8992 xdp_do_flush(); 8993 8994 if (status & IGB_XDP_TX) { 8995 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8996 8997 nq = txring_txq(tx_ring); 8998 __netif_tx_lock(nq, cpu); 8999 igb_xdp_ring_update_tail(tx_ring); 9000 __netif_tx_unlock(nq); 9001 } 9002} 9003 9004void igb_update_rx_stats(struct igb_q_vector *q_vector, unsigned int packets, 9005 unsigned int bytes) 9006{ 9007 struct igb_ring *ring = q_vector->rx.ring; 9008 9009 u64_stats_update_begin(&ring->rx_syncp); 9010 ring->rx_stats.packets += packets; 9011 ring->rx_stats.bytes += bytes; 9012 u64_stats_update_end(&ring->rx_syncp); 9013 9014 q_vector->rx.total_packets += packets; 9015 q_vector->rx.total_bytes += bytes; 9016} 9017 9018static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 9019{ 9020 unsigned int total_bytes = 0, total_packets = 0; 9021 struct igb_adapter *adapter = q_vector->adapter; 9022 struct igb_ring *rx_ring = q_vector->rx.ring; 9023 u16 cleaned_count = igb_desc_unused(rx_ring); 9024 struct sk_buff *skb = rx_ring->skb; 9025 unsigned int xdp_xmit = 0; 9026 struct xdp_buff xdp; 9027 u32 frame_sz = 0; 9028 int rx_buf_pgcnt; 9029 int xdp_res = 0; 9030 9031 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 9032#if (PAGE_SIZE < 8192) 9033 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 9034#endif 9035 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 9036 9037 while (likely(total_packets < budget)) { 9038 union e1000_adv_rx_desc *rx_desc; 9039 struct igb_rx_buffer *rx_buffer; 9040 ktime_t timestamp = 0; 9041 int pkt_offset = 0; 9042 unsigned int size; 9043 void *pktbuf; 9044 9045 /* return some buffers to hardware, one at a time is too slow */ 9046 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 9047 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9048 cleaned_count = 0; 9049 } 9050 9051 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 9052 size = le16_to_cpu(rx_desc->wb.upper.length); 9053 if (!size) 9054 break; 9055 9056 /* This memory barrier is needed to keep us from reading 9057 * any other fields out of the rx_desc until we know the 9058 * descriptor has been written back 9059 */ 9060 dma_rmb(); 9061 9062 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 9063 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 9064 9065 /* pull rx packet timestamp if available and valid */ 9066 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 9067 int ts_hdr_len; 9068 9069 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 9070 pktbuf, ×tamp); 9071 9072 pkt_offset += ts_hdr_len; 9073 size -= ts_hdr_len; 9074 } 9075 9076 /* retrieve a buffer from the ring */ 9077 if (!skb) { 9078 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 9079 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 9080 9081 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 9082 xdp_buff_clear_frags_flag(&xdp); 9083#if (PAGE_SIZE > 4096) 9084 /* At larger PAGE_SIZE, frame_sz depend on len size */ 9085 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 9086#endif 9087 xdp_res = igb_run_xdp(adapter, rx_ring, &xdp); 9088 } 9089 9090 if (xdp_res) { 9091 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 9092 xdp_xmit |= xdp_res; 9093 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 9094 } else { 9095 rx_buffer->pagecnt_bias++; 9096 } 9097 total_packets++; 9098 total_bytes += size; 9099 } else if (skb) 9100 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 9101 else if (ring_uses_build_skb(rx_ring)) 9102 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 9103 timestamp); 9104 else 9105 skb = igb_construct_skb(rx_ring, rx_buffer, 9106 &xdp, timestamp); 9107 9108 /* exit if we failed to retrieve a buffer */ 9109 if (!xdp_res && !skb) { 9110 rx_ring->rx_stats.alloc_failed++; 9111 rx_buffer->pagecnt_bias++; 9112 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9113 break; 9114 } 9115 9116 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 9117 cleaned_count++; 9118 9119 /* fetch next buffer in frame if non-eop */ 9120 if (igb_is_non_eop(rx_ring, rx_desc)) 9121 continue; 9122 9123 /* verify the packet layout is correct */ 9124 if (xdp_res || igb_cleanup_headers(rx_ring, rx_desc, skb)) { 9125 skb = NULL; 9126 continue; 9127 } 9128 9129 /* probably a little skewed due to removing CRC */ 9130 total_bytes += skb->len; 9131 9132 /* populate checksum, timestamp, VLAN, and protocol */ 9133 igb_process_skb_fields(rx_ring, rx_desc, skb); 9134 9135 napi_gro_receive(&q_vector->napi, skb); 9136 9137 /* reset skb pointer */ 9138 skb = NULL; 9139 9140 /* update budget accounting */ 9141 total_packets++; 9142 } 9143 9144 /* place incomplete frames back on ring for completion */ 9145 rx_ring->skb = skb; 9146 9147 if (xdp_xmit) 9148 igb_finalize_xdp(adapter, xdp_xmit); 9149 9150 igb_update_rx_stats(q_vector, total_packets, total_bytes); 9151 9152 if (cleaned_count) 9153 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9154 9155 return total_packets; 9156} 9157 9158static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9159 struct igb_rx_buffer *bi) 9160{ 9161 struct page *page = bi->page; 9162 dma_addr_t dma; 9163 9164 /* since we are recycling buffers we should seldom need to alloc */ 9165 if (likely(page)) 9166 return true; 9167 9168 /* alloc new page for storage */ 9169 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9170 if (unlikely(!page)) { 9171 rx_ring->rx_stats.alloc_failed++; 9172 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9173 return false; 9174 } 9175 9176 /* map page for use */ 9177 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9178 igb_rx_pg_size(rx_ring), 9179 DMA_FROM_DEVICE, 9180 IGB_RX_DMA_ATTR); 9181 9182 /* if mapping failed free memory back to system since 9183 * there isn't much point in holding memory we can't use 9184 */ 9185 if (dma_mapping_error(rx_ring->dev, dma)) { 9186 __free_pages(page, igb_rx_pg_order(rx_ring)); 9187 9188 rx_ring->rx_stats.alloc_failed++; 9189 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9190 return false; 9191 } 9192 9193 bi->dma = dma; 9194 bi->page = page; 9195 bi->page_offset = igb_rx_offset(rx_ring); 9196 page_ref_add(page, USHRT_MAX - 1); 9197 bi->pagecnt_bias = USHRT_MAX; 9198 9199 return true; 9200} 9201 9202/** 9203 * igb_alloc_rx_buffers - Replace used receive buffers 9204 * @rx_ring: rx descriptor ring to allocate new receive buffers 9205 * @cleaned_count: count of buffers to allocate 9206 **/ 9207void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9208{ 9209 union e1000_adv_rx_desc *rx_desc; 9210 struct igb_rx_buffer *bi; 9211 u16 i = rx_ring->next_to_use; 9212 u16 bufsz; 9213 9214 /* nothing to do */ 9215 if (!cleaned_count) 9216 return; 9217 9218 rx_desc = IGB_RX_DESC(rx_ring, i); 9219 bi = &rx_ring->rx_buffer_info[i]; 9220 i -= rx_ring->count; 9221 9222 bufsz = igb_rx_bufsz(rx_ring); 9223 9224 do { 9225 if (!igb_alloc_mapped_page(rx_ring, bi)) 9226 break; 9227 9228 /* sync the buffer for use by the device */ 9229 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9230 bi->page_offset, bufsz, 9231 DMA_FROM_DEVICE); 9232 9233 /* Refresh the desc even if buffer_addrs didn't change 9234 * because each write-back erases this info. 9235 */ 9236 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9237 9238 rx_desc++; 9239 bi++; 9240 i++; 9241 if (unlikely(!i)) { 9242 rx_desc = IGB_RX_DESC(rx_ring, 0); 9243 bi = rx_ring->rx_buffer_info; 9244 i -= rx_ring->count; 9245 } 9246 9247 /* clear the length for the next_to_use descriptor */ 9248 rx_desc->wb.upper.length = 0; 9249 9250 cleaned_count--; 9251 } while (cleaned_count); 9252 9253 i += rx_ring->count; 9254 9255 if (rx_ring->next_to_use != i) { 9256 /* record the next descriptor to use */ 9257 rx_ring->next_to_use = i; 9258 9259 /* update next to alloc since we have filled the ring */ 9260 rx_ring->next_to_alloc = i; 9261 9262 /* Force memory writes to complete before letting h/w 9263 * know there are new descriptors to fetch. (Only 9264 * applicable for weak-ordered memory model archs, 9265 * such as IA-64). 9266 */ 9267 dma_wmb(); 9268 writel(i, rx_ring->tail); 9269 } 9270} 9271 9272/** 9273 * igb_mii_ioctl - 9274 * @netdev: pointer to netdev struct 9275 * @ifr: interface structure 9276 * @cmd: ioctl command to execute 9277 **/ 9278static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9279{ 9280 struct igb_adapter *adapter = netdev_priv(netdev); 9281 struct mii_ioctl_data *data = if_mii(ifr); 9282 9283 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9284 return -EOPNOTSUPP; 9285 9286 switch (cmd) { 9287 case SIOCGMIIPHY: 9288 data->phy_id = adapter->hw.phy.addr; 9289 break; 9290 case SIOCGMIIREG: 9291 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9292 &data->val_out)) 9293 return -EIO; 9294 break; 9295 case SIOCSMIIREG: 9296 if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9297 data->val_in)) 9298 return -EIO; 9299 break; 9300 default: 9301 return -EOPNOTSUPP; 9302 } 9303 return 0; 9304} 9305 9306/** 9307 * igb_ioctl - 9308 * @netdev: pointer to netdev struct 9309 * @ifr: interface structure 9310 * @cmd: ioctl command to execute 9311 **/ 9312static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9313{ 9314 switch (cmd) { 9315 case SIOCGMIIPHY: 9316 case SIOCGMIIREG: 9317 case SIOCSMIIREG: 9318 return igb_mii_ioctl(netdev, ifr, cmd); 9319 default: 9320 return -EOPNOTSUPP; 9321 } 9322} 9323 9324void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9325{ 9326 struct igb_adapter *adapter = hw->back; 9327 9328 pci_read_config_word(adapter->pdev, reg, value); 9329} 9330 9331void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9332{ 9333 struct igb_adapter *adapter = hw->back; 9334 9335 pci_write_config_word(adapter->pdev, reg, *value); 9336} 9337 9338s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9339{ 9340 struct igb_adapter *adapter = hw->back; 9341 9342 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9343 return -E1000_ERR_CONFIG; 9344 9345 return 0; 9346} 9347 9348s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9349{ 9350 struct igb_adapter *adapter = hw->back; 9351 9352 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9353 return -E1000_ERR_CONFIG; 9354 9355 return 0; 9356} 9357 9358static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9359{ 9360 struct igb_adapter *adapter = netdev_priv(netdev); 9361 struct e1000_hw *hw = &adapter->hw; 9362 u32 ctrl, rctl; 9363 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9364 9365 if (enable) { 9366 /* enable VLAN tag insert/strip */ 9367 ctrl = rd32(E1000_CTRL); 9368 ctrl |= E1000_CTRL_VME; 9369 wr32(E1000_CTRL, ctrl); 9370 9371 /* Disable CFI check */ 9372 rctl = rd32(E1000_RCTL); 9373 rctl &= ~E1000_RCTL_CFIEN; 9374 wr32(E1000_RCTL, rctl); 9375 } else { 9376 /* disable VLAN tag insert/strip */ 9377 ctrl = rd32(E1000_CTRL); 9378 ctrl &= ~E1000_CTRL_VME; 9379 wr32(E1000_CTRL, ctrl); 9380 } 9381 9382 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9383} 9384 9385static int igb_vlan_rx_add_vid(struct net_device *netdev, 9386 __be16 proto, u16 vid) 9387{ 9388 struct igb_adapter *adapter = netdev_priv(netdev); 9389 struct e1000_hw *hw = &adapter->hw; 9390 int pf_id = adapter->vfs_allocated_count; 9391 9392 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9393 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9394 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9395 9396 set_bit(vid, adapter->active_vlans); 9397 9398 return 0; 9399} 9400 9401static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9402 __be16 proto, u16 vid) 9403{ 9404 struct igb_adapter *adapter = netdev_priv(netdev); 9405 int pf_id = adapter->vfs_allocated_count; 9406 struct e1000_hw *hw = &adapter->hw; 9407 9408 /* remove VID from filter table */ 9409 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9410 igb_vfta_set(hw, vid, pf_id, false, true); 9411 9412 clear_bit(vid, adapter->active_vlans); 9413 9414 return 0; 9415} 9416 9417static void igb_restore_vlan(struct igb_adapter *adapter) 9418{ 9419 u16 vid = 1; 9420 9421 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9422 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9423 9424 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9425 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9426} 9427 9428int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9429{ 9430 struct pci_dev *pdev = adapter->pdev; 9431 struct e1000_mac_info *mac = &adapter->hw.mac; 9432 9433 mac->autoneg = 0; 9434 9435 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9436 * for the switch() below to work 9437 */ 9438 if ((spd & 1) || (dplx & ~1)) 9439 goto err_inval; 9440 9441 /* Fiber NIC's only allow 1000 gbps Full duplex 9442 * and 100Mbps Full duplex for 100baseFx sfp 9443 */ 9444 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9445 switch (spd + dplx) { 9446 case SPEED_10 + DUPLEX_HALF: 9447 case SPEED_10 + DUPLEX_FULL: 9448 case SPEED_100 + DUPLEX_HALF: 9449 goto err_inval; 9450 default: 9451 break; 9452 } 9453 } 9454 9455 switch (spd + dplx) { 9456 case SPEED_10 + DUPLEX_HALF: 9457 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9458 break; 9459 case SPEED_10 + DUPLEX_FULL: 9460 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9461 break; 9462 case SPEED_100 + DUPLEX_HALF: 9463 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9464 break; 9465 case SPEED_100 + DUPLEX_FULL: 9466 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9467 break; 9468 case SPEED_1000 + DUPLEX_FULL: 9469 mac->autoneg = 1; 9470 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9471 break; 9472 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9473 default: 9474 goto err_inval; 9475 } 9476 9477 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9478 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9479 9480 return 0; 9481 9482err_inval: 9483 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9484 return -EINVAL; 9485} 9486 9487static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9488 bool runtime) 9489{ 9490 struct net_device *netdev = pci_get_drvdata(pdev); 9491 struct igb_adapter *adapter = netdev_priv(netdev); 9492 struct e1000_hw *hw = &adapter->hw; 9493 u32 ctrl, rctl, status; 9494 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9495 bool wake; 9496 9497 rtnl_lock(); 9498 netif_device_detach(netdev); 9499 9500 if (netif_running(netdev)) 9501 __igb_close(netdev, true); 9502 9503 igb_ptp_suspend(adapter); 9504 9505 igb_clear_interrupt_scheme(adapter); 9506 rtnl_unlock(); 9507 9508 status = rd32(E1000_STATUS); 9509 if (status & E1000_STATUS_LU) 9510 wufc &= ~E1000_WUFC_LNKC; 9511 9512 if (wufc) { 9513 igb_setup_rctl(adapter); 9514 igb_set_rx_mode(netdev); 9515 9516 /* turn on all-multi mode if wake on multicast is enabled */ 9517 if (wufc & E1000_WUFC_MC) { 9518 rctl = rd32(E1000_RCTL); 9519 rctl |= E1000_RCTL_MPE; 9520 wr32(E1000_RCTL, rctl); 9521 } 9522 9523 ctrl = rd32(E1000_CTRL); 9524 ctrl |= E1000_CTRL_ADVD3WUC; 9525 wr32(E1000_CTRL, ctrl); 9526 9527 /* Allow time for pending master requests to run */ 9528 igb_disable_pcie_master(hw); 9529 9530 wr32(E1000_WUC, E1000_WUC_PME_EN); 9531 wr32(E1000_WUFC, wufc); 9532 } else { 9533 wr32(E1000_WUC, 0); 9534 wr32(E1000_WUFC, 0); 9535 } 9536 9537 wake = wufc || adapter->en_mng_pt; 9538 if (!wake) 9539 igb_power_down_link(adapter); 9540 else 9541 igb_power_up_link(adapter); 9542 9543 if (enable_wake) 9544 *enable_wake = wake; 9545 9546 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9547 * would have already happened in close and is redundant. 9548 */ 9549 igb_release_hw_control(adapter); 9550 9551 pci_disable_device(pdev); 9552 9553 return 0; 9554} 9555 9556static void igb_deliver_wake_packet(struct net_device *netdev) 9557{ 9558 struct igb_adapter *adapter = netdev_priv(netdev); 9559 struct e1000_hw *hw = &adapter->hw; 9560 struct sk_buff *skb; 9561 u32 wupl; 9562 9563 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9564 9565 /* WUPM stores only the first 128 bytes of the wake packet. 9566 * Read the packet only if we have the whole thing. 9567 */ 9568 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9569 return; 9570 9571 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9572 if (!skb) 9573 return; 9574 9575 skb_put(skb, wupl); 9576 9577 /* Ensure reads are 32-bit aligned */ 9578 wupl = roundup(wupl, 4); 9579 9580 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9581 9582 skb->protocol = eth_type_trans(skb, netdev); 9583 netif_rx(skb); 9584} 9585 9586static int igb_suspend(struct device *dev) 9587{ 9588 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9589} 9590 9591static int __igb_resume(struct device *dev, bool rpm) 9592{ 9593 struct pci_dev *pdev = to_pci_dev(dev); 9594 struct net_device *netdev = pci_get_drvdata(pdev); 9595 struct igb_adapter *adapter = netdev_priv(netdev); 9596 struct e1000_hw *hw = &adapter->hw; 9597 u32 err, val; 9598 9599 pci_set_power_state(pdev, PCI_D0); 9600 pci_restore_state(pdev); 9601 9602 if (!pci_device_is_present(pdev)) 9603 return -ENODEV; 9604 err = pci_enable_device_mem(pdev); 9605 if (err) { 9606 dev_err(&pdev->dev, 9607 "igb: Cannot enable PCI device from suspend\n"); 9608 return err; 9609 } 9610 pci_set_master(pdev); 9611 9612 pci_enable_wake(pdev, PCI_D3hot, 0); 9613 pci_enable_wake(pdev, PCI_D3cold, 0); 9614 9615 if (igb_init_interrupt_scheme(adapter, true)) { 9616 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9617 return -ENOMEM; 9618 } 9619 9620 igb_reset(adapter); 9621 9622 /* let the f/w know that the h/w is now under the control of the 9623 * driver. 9624 */ 9625 igb_get_hw_control(adapter); 9626 9627 val = rd32(E1000_WUS); 9628 if (val & WAKE_PKT_WUS) 9629 igb_deliver_wake_packet(netdev); 9630 9631 wr32(E1000_WUS, ~0); 9632 9633 if (!rpm) 9634 rtnl_lock(); 9635 if (!err && netif_running(netdev)) 9636 err = __igb_open(netdev, true); 9637 9638 if (!err) 9639 netif_device_attach(netdev); 9640 if (!rpm) 9641 rtnl_unlock(); 9642 9643 return err; 9644} 9645 9646static int igb_resume(struct device *dev) 9647{ 9648 return __igb_resume(dev, false); 9649} 9650 9651static int igb_runtime_idle(struct device *dev) 9652{ 9653 struct net_device *netdev = dev_get_drvdata(dev); 9654 struct igb_adapter *adapter = netdev_priv(netdev); 9655 9656 if (!igb_has_link(adapter)) 9657 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9658 9659 return -EBUSY; 9660} 9661 9662static int igb_runtime_suspend(struct device *dev) 9663{ 9664 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9665} 9666 9667static int igb_runtime_resume(struct device *dev) 9668{ 9669 return __igb_resume(dev, true); 9670} 9671 9672static void igb_shutdown(struct pci_dev *pdev) 9673{ 9674 bool wake; 9675 9676 __igb_shutdown(pdev, &wake, 0); 9677 9678 if (system_state == SYSTEM_POWER_OFF) { 9679 pci_wake_from_d3(pdev, wake); 9680 pci_set_power_state(pdev, PCI_D3hot); 9681 } 9682} 9683 9684static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9685{ 9686#ifdef CONFIG_PCI_IOV 9687 int err; 9688 9689 if (num_vfs == 0) { 9690 return igb_disable_sriov(dev, true); 9691 } else { 9692 err = igb_enable_sriov(dev, num_vfs, true); 9693 return err ? err : num_vfs; 9694 } 9695#endif 9696 return 0; 9697} 9698 9699/** 9700 * igb_io_error_detected - called when PCI error is detected 9701 * @pdev: Pointer to PCI device 9702 * @state: The current pci connection state 9703 * 9704 * This function is called after a PCI bus error affecting 9705 * this device has been detected. 9706 **/ 9707static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9708 pci_channel_state_t state) 9709{ 9710 struct net_device *netdev = pci_get_drvdata(pdev); 9711 struct igb_adapter *adapter = netdev_priv(netdev); 9712 9713 if (state == pci_channel_io_normal) { 9714 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9715 return PCI_ERS_RESULT_CAN_RECOVER; 9716 } 9717 9718 netif_device_detach(netdev); 9719 9720 if (state == pci_channel_io_perm_failure) 9721 return PCI_ERS_RESULT_DISCONNECT; 9722 9723 rtnl_lock(); 9724 if (netif_running(netdev)) 9725 igb_down(adapter); 9726 rtnl_unlock(); 9727 9728 pci_disable_device(pdev); 9729 9730 /* Request a slot reset. */ 9731 return PCI_ERS_RESULT_NEED_RESET; 9732} 9733 9734/** 9735 * igb_io_slot_reset - called after the pci bus has been reset. 9736 * @pdev: Pointer to PCI device 9737 * 9738 * Restart the card from scratch, as if from a cold-boot. Implementation 9739 * resembles the first-half of the __igb_resume routine. 9740 **/ 9741static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9742{ 9743 struct net_device *netdev = pci_get_drvdata(pdev); 9744 struct igb_adapter *adapter = netdev_priv(netdev); 9745 struct e1000_hw *hw = &adapter->hw; 9746 pci_ers_result_t result; 9747 9748 if (pci_enable_device_mem(pdev)) { 9749 dev_err(&pdev->dev, 9750 "Cannot re-enable PCI device after reset.\n"); 9751 result = PCI_ERS_RESULT_DISCONNECT; 9752 } else { 9753 pci_set_master(pdev); 9754 pci_restore_state(pdev); 9755 9756 pci_enable_wake(pdev, PCI_D3hot, 0); 9757 pci_enable_wake(pdev, PCI_D3cold, 0); 9758 9759 /* In case of PCI error, adapter lose its HW address 9760 * so we should re-assign it here. 9761 */ 9762 hw->hw_addr = adapter->io_addr; 9763 9764 igb_reset(adapter); 9765 wr32(E1000_WUS, ~0); 9766 result = PCI_ERS_RESULT_RECOVERED; 9767 } 9768 9769 return result; 9770} 9771 9772/** 9773 * igb_io_resume - called when traffic can start flowing again. 9774 * @pdev: Pointer to PCI device 9775 * 9776 * This callback is called when the error recovery driver tells us that 9777 * its OK to resume normal operation. Implementation resembles the 9778 * second-half of the __igb_resume routine. 9779 */ 9780static void igb_io_resume(struct pci_dev *pdev) 9781{ 9782 struct net_device *netdev = pci_get_drvdata(pdev); 9783 struct igb_adapter *adapter = netdev_priv(netdev); 9784 9785 rtnl_lock(); 9786 if (netif_running(netdev)) { 9787 if (!test_bit(__IGB_DOWN, &adapter->state)) { 9788 dev_dbg(&pdev->dev, "Resuming from non-fatal error, do nothing.\n"); 9789 rtnl_unlock(); 9790 return; 9791 } 9792 9793 if (igb_up(adapter)) { 9794 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9795 rtnl_unlock(); 9796 return; 9797 } 9798 } 9799 rtnl_unlock(); 9800 9801 netif_device_attach(netdev); 9802 9803 /* let the f/w know that the h/w is now under the control of the 9804 * driver. 9805 */ 9806 igb_get_hw_control(adapter); 9807} 9808 9809/** 9810 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9811 * @adapter: Pointer to adapter structure 9812 * @index: Index of the RAR entry which need to be synced with MAC table 9813 **/ 9814static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9815{ 9816 struct e1000_hw *hw = &adapter->hw; 9817 u32 rar_low, rar_high; 9818 u8 *addr = adapter->mac_table[index].addr; 9819 9820 /* HW expects these to be in network order when they are plugged 9821 * into the registers which are little endian. In order to guarantee 9822 * that ordering we need to do an leXX_to_cpup here in order to be 9823 * ready for the byteswap that occurs with writel 9824 */ 9825 rar_low = le32_to_cpup((__le32 *)(addr)); 9826 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9827 9828 /* Indicate to hardware the Address is Valid. */ 9829 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9830 if (is_valid_ether_addr(addr)) 9831 rar_high |= E1000_RAH_AV; 9832 9833 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9834 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9835 9836 switch (hw->mac.type) { 9837 case e1000_82575: 9838 case e1000_i210: 9839 if (adapter->mac_table[index].state & 9840 IGB_MAC_STATE_QUEUE_STEERING) 9841 rar_high |= E1000_RAH_QSEL_ENABLE; 9842 9843 rar_high |= E1000_RAH_POOL_1 * 9844 adapter->mac_table[index].queue; 9845 break; 9846 default: 9847 rar_high |= E1000_RAH_POOL_1 << 9848 adapter->mac_table[index].queue; 9849 break; 9850 } 9851 } 9852 9853 wr32(E1000_RAL(index), rar_low); 9854 wrfl(); 9855 wr32(E1000_RAH(index), rar_high); 9856 wrfl(); 9857} 9858 9859static int igb_set_vf_mac(struct igb_adapter *adapter, 9860 int vf, unsigned char *mac_addr) 9861{ 9862 struct e1000_hw *hw = &adapter->hw; 9863 /* VF MAC addresses start at end of receive addresses and moves 9864 * towards the first, as a result a collision should not be possible 9865 */ 9866 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9867 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9868 9869 ether_addr_copy(vf_mac_addr, mac_addr); 9870 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9871 adapter->mac_table[rar_entry].queue = vf; 9872 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9873 igb_rar_set_index(adapter, rar_entry); 9874 9875 return 0; 9876} 9877 9878static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9879{ 9880 struct igb_adapter *adapter = netdev_priv(netdev); 9881 9882 if (vf >= adapter->vfs_allocated_count) 9883 return -EINVAL; 9884 9885 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9886 * flag and allows to overwrite the MAC via VF netdev. This 9887 * is necessary to allow libvirt a way to restore the original 9888 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9889 * down a VM. 9890 */ 9891 if (is_zero_ether_addr(mac)) { 9892 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9893 dev_info(&adapter->pdev->dev, 9894 "remove administratively set MAC on VF %d\n", 9895 vf); 9896 } else if (is_valid_ether_addr(mac)) { 9897 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9898 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9899 mac, vf); 9900 dev_info(&adapter->pdev->dev, 9901 "Reload the VF driver to make this change effective."); 9902 /* Generate additional warning if PF is down */ 9903 if (test_bit(__IGB_DOWN, &adapter->state)) { 9904 dev_warn(&adapter->pdev->dev, 9905 "The VF MAC address has been set, but the PF device is not up.\n"); 9906 dev_warn(&adapter->pdev->dev, 9907 "Bring the PF device up before attempting to use the VF device.\n"); 9908 } 9909 } else { 9910 return -EINVAL; 9911 } 9912 return igb_set_vf_mac(adapter, vf, mac); 9913} 9914 9915static int igb_link_mbps(int internal_link_speed) 9916{ 9917 switch (internal_link_speed) { 9918 case SPEED_100: 9919 return 100; 9920 case SPEED_1000: 9921 return 1000; 9922 default: 9923 return 0; 9924 } 9925} 9926 9927static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9928 int link_speed) 9929{ 9930 int rf_dec, rf_int; 9931 u32 bcnrc_val; 9932 9933 if (tx_rate != 0) { 9934 /* Calculate the rate factor values to set */ 9935 rf_int = link_speed / tx_rate; 9936 rf_dec = (link_speed - (rf_int * tx_rate)); 9937 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9938 tx_rate; 9939 9940 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9941 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9942 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9943 } else { 9944 bcnrc_val = 0; 9945 } 9946 9947 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9948 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9949 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9950 */ 9951 wr32(E1000_RTTBCNRM, 0x14); 9952 wr32(E1000_RTTBCNRC, bcnrc_val); 9953} 9954 9955static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9956{ 9957 int actual_link_speed, i; 9958 bool reset_rate = false; 9959 9960 /* VF TX rate limit was not set or not supported */ 9961 if ((adapter->vf_rate_link_speed == 0) || 9962 (adapter->hw.mac.type != e1000_82576)) 9963 return; 9964 9965 actual_link_speed = igb_link_mbps(adapter->link_speed); 9966 if (actual_link_speed != adapter->vf_rate_link_speed) { 9967 reset_rate = true; 9968 adapter->vf_rate_link_speed = 0; 9969 dev_info(&adapter->pdev->dev, 9970 "Link speed has been changed. VF Transmit rate is disabled\n"); 9971 } 9972 9973 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9974 if (reset_rate) 9975 adapter->vf_data[i].tx_rate = 0; 9976 9977 igb_set_vf_rate_limit(&adapter->hw, i, 9978 adapter->vf_data[i].tx_rate, 9979 actual_link_speed); 9980 } 9981} 9982 9983static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9984 int min_tx_rate, int max_tx_rate) 9985{ 9986 struct igb_adapter *adapter = netdev_priv(netdev); 9987 struct e1000_hw *hw = &adapter->hw; 9988 int actual_link_speed; 9989 9990 if (hw->mac.type != e1000_82576) 9991 return -EOPNOTSUPP; 9992 9993 if (min_tx_rate) 9994 return -EINVAL; 9995 9996 actual_link_speed = igb_link_mbps(adapter->link_speed); 9997 if ((vf >= adapter->vfs_allocated_count) || 9998 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9999 (max_tx_rate < 0) || 10000 (max_tx_rate > actual_link_speed)) 10001 return -EINVAL; 10002 10003 adapter->vf_rate_link_speed = actual_link_speed; 10004 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 10005 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 10006 10007 return 0; 10008} 10009 10010static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 10011 bool setting) 10012{ 10013 struct igb_adapter *adapter = netdev_priv(netdev); 10014 struct e1000_hw *hw = &adapter->hw; 10015 u32 reg_val, reg_offset; 10016 10017 if (!adapter->vfs_allocated_count) 10018 return -EOPNOTSUPP; 10019 10020 if (vf >= adapter->vfs_allocated_count) 10021 return -EINVAL; 10022 10023 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 10024 reg_val = rd32(reg_offset); 10025 if (setting) 10026 reg_val |= (BIT(vf) | 10027 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10028 else 10029 reg_val &= ~(BIT(vf) | 10030 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10031 wr32(reg_offset, reg_val); 10032 10033 adapter->vf_data[vf].spoofchk_enabled = setting; 10034 return 0; 10035} 10036 10037static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 10038{ 10039 struct igb_adapter *adapter = netdev_priv(netdev); 10040 10041 if (vf >= adapter->vfs_allocated_count) 10042 return -EINVAL; 10043 if (adapter->vf_data[vf].trusted == setting) 10044 return 0; 10045 10046 adapter->vf_data[vf].trusted = setting; 10047 10048 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 10049 vf, setting ? "" : "not "); 10050 return 0; 10051} 10052 10053static int igb_ndo_get_vf_config(struct net_device *netdev, 10054 int vf, struct ifla_vf_info *ivi) 10055{ 10056 struct igb_adapter *adapter = netdev_priv(netdev); 10057 if (vf >= adapter->vfs_allocated_count) 10058 return -EINVAL; 10059 ivi->vf = vf; 10060 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 10061 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 10062 ivi->min_tx_rate = 0; 10063 ivi->vlan = adapter->vf_data[vf].pf_vlan; 10064 ivi->qos = adapter->vf_data[vf].pf_qos; 10065 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 10066 ivi->trusted = adapter->vf_data[vf].trusted; 10067 return 0; 10068} 10069 10070static void igb_vmm_control(struct igb_adapter *adapter) 10071{ 10072 struct e1000_hw *hw = &adapter->hw; 10073 u32 reg; 10074 10075 switch (hw->mac.type) { 10076 case e1000_82575: 10077 case e1000_i210: 10078 case e1000_i211: 10079 case e1000_i354: 10080 default: 10081 /* replication is not supported for 82575 */ 10082 return; 10083 case e1000_82576: 10084 /* notify HW that the MAC is adding vlan tags */ 10085 reg = rd32(E1000_DTXCTL); 10086 reg |= E1000_DTXCTL_VLAN_ADDED; 10087 wr32(E1000_DTXCTL, reg); 10088 fallthrough; 10089 case e1000_82580: 10090 /* enable replication vlan tag stripping */ 10091 reg = rd32(E1000_RPLOLR); 10092 reg |= E1000_RPLOLR_STRVLAN; 10093 wr32(E1000_RPLOLR, reg); 10094 fallthrough; 10095 case e1000_i350: 10096 /* none of the above registers are supported by i350 */ 10097 break; 10098 } 10099 10100 if (adapter->vfs_allocated_count) { 10101 igb_vmdq_set_loopback_pf(hw, true); 10102 igb_vmdq_set_replication_pf(hw, true); 10103 igb_vmdq_set_anti_spoofing_pf(hw, true, 10104 adapter->vfs_allocated_count); 10105 } else { 10106 igb_vmdq_set_loopback_pf(hw, false); 10107 igb_vmdq_set_replication_pf(hw, false); 10108 } 10109} 10110 10111static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 10112{ 10113 struct e1000_hw *hw = &adapter->hw; 10114 u32 dmac_thr; 10115 u16 hwm; 10116 u32 reg; 10117 10118 if (hw->mac.type > e1000_82580) { 10119 if (adapter->flags & IGB_FLAG_DMAC) { 10120 /* force threshold to 0. */ 10121 wr32(E1000_DMCTXTH, 0); 10122 10123 /* DMA Coalescing high water mark needs to be greater 10124 * than the Rx threshold. Set hwm to PBA - max frame 10125 * size in 16B units, capping it at PBA - 6KB. 10126 */ 10127 hwm = 64 * (pba - 6); 10128 reg = rd32(E1000_FCRTC); 10129 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 10130 reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 10131 wr32(E1000_FCRTC, reg); 10132 10133 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 10134 * frame size, capping it at PBA - 10KB. 10135 */ 10136 dmac_thr = pba - 10; 10137 reg = rd32(E1000_DMACR); 10138 reg &= ~E1000_DMACR_DMACTHR_MASK; 10139 reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 10140 10141 /* transition to L0x or L1 if available..*/ 10142 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10143 10144 /* watchdog timer= +-1000 usec in 32usec intervals */ 10145 reg |= (1000 >> 5); 10146 10147 /* Disable BMC-to-OS Watchdog Enable */ 10148 if (hw->mac.type != e1000_i354) 10149 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10150 wr32(E1000_DMACR, reg); 10151 10152 /* no lower threshold to disable 10153 * coalescing(smart fifb)-UTRESH=0 10154 */ 10155 wr32(E1000_DMCRTRH, 0); 10156 10157 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10158 10159 wr32(E1000_DMCTLX, reg); 10160 10161 /* free space in tx packet buffer to wake from 10162 * DMA coal 10163 */ 10164 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10165 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10166 } 10167 10168 if (hw->mac.type >= e1000_i210 || 10169 (adapter->flags & IGB_FLAG_DMAC)) { 10170 reg = rd32(E1000_PCIEMISC); 10171 reg |= E1000_PCIEMISC_LX_DECISION; 10172 wr32(E1000_PCIEMISC, reg); 10173 } /* endif adapter->dmac is not disabled */ 10174 } else if (hw->mac.type == e1000_82580) { 10175 u32 reg = rd32(E1000_PCIEMISC); 10176 10177 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10178 wr32(E1000_DMACR, 0); 10179 } 10180} 10181 10182/** 10183 * igb_read_i2c_byte - Reads 8 bit word over I2C 10184 * @hw: pointer to hardware structure 10185 * @byte_offset: byte offset to read 10186 * @dev_addr: device address 10187 * @data: value read 10188 * 10189 * Performs byte read operation over I2C interface at 10190 * a specified device address. 10191 **/ 10192s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10193 u8 dev_addr, u8 *data) 10194{ 10195 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10196 struct i2c_client *this_client = adapter->i2c_client; 10197 s32 status; 10198 u16 swfw_mask = 0; 10199 10200 if (!this_client) 10201 return E1000_ERR_I2C; 10202 10203 swfw_mask = E1000_SWFW_PHY0_SM; 10204 10205 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10206 return E1000_ERR_SWFW_SYNC; 10207 10208 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10209 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10210 10211 if (status < 0) 10212 return E1000_ERR_I2C; 10213 else { 10214 *data = status; 10215 return 0; 10216 } 10217} 10218 10219/** 10220 * igb_write_i2c_byte - Writes 8 bit word over I2C 10221 * @hw: pointer to hardware structure 10222 * @byte_offset: byte offset to write 10223 * @dev_addr: device address 10224 * @data: value to write 10225 * 10226 * Performs byte write operation over I2C interface at 10227 * a specified device address. 10228 **/ 10229s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10230 u8 dev_addr, u8 data) 10231{ 10232 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10233 struct i2c_client *this_client = adapter->i2c_client; 10234 s32 status; 10235 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10236 10237 if (!this_client) 10238 return E1000_ERR_I2C; 10239 10240 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10241 return E1000_ERR_SWFW_SYNC; 10242 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10243 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10244 10245 if (status) 10246 return E1000_ERR_I2C; 10247 else 10248 return 0; 10249 10250} 10251 10252int igb_reinit_queues(struct igb_adapter *adapter) 10253{ 10254 struct net_device *netdev = adapter->netdev; 10255 struct pci_dev *pdev = adapter->pdev; 10256 int err = 0; 10257 10258 if (netif_running(netdev)) 10259 igb_close(netdev); 10260 10261 igb_reset_interrupt_capability(adapter); 10262 10263 if (igb_init_interrupt_scheme(adapter, true)) { 10264 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10265 return -ENOMEM; 10266 } 10267 10268 if (netif_running(netdev)) 10269 err = igb_open(netdev); 10270 10271 return err; 10272} 10273 10274static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10275{ 10276 struct igb_nfc_filter *rule; 10277 10278 spin_lock(&adapter->nfc_lock); 10279 10280 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10281 igb_erase_filter(adapter, rule); 10282 10283 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10284 igb_erase_filter(adapter, rule); 10285 10286 spin_unlock(&adapter->nfc_lock); 10287} 10288 10289static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10290{ 10291 struct igb_nfc_filter *rule; 10292 10293 spin_lock(&adapter->nfc_lock); 10294 10295 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10296 igb_add_filter(adapter, rule); 10297 10298 spin_unlock(&adapter->nfc_lock); 10299} 10300 10301static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10302 igb_runtime_suspend, igb_runtime_resume, 10303 igb_runtime_idle); 10304 10305static struct pci_driver igb_driver = { 10306 .name = igb_driver_name, 10307 .id_table = igb_pci_tbl, 10308 .probe = igb_probe, 10309 .remove = igb_remove, 10310 .driver.pm = pm_ptr(&igb_pm_ops), 10311 .shutdown = igb_shutdown, 10312 .sriov_configure = igb_pci_sriov_configure, 10313 .err_handler = &igb_err_handler 10314}; 10315 10316/* igb_main.c */
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