idpf_lan_txrx.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (C) 2023 Intel Corporation */
  3
  4#ifndef _IDPF_LAN_TXRX_H_
  5#define _IDPF_LAN_TXRX_H_
  6
  7#include <linux/bits.h>
  8
  9enum idpf_rss_hash {
 10	IDPF_HASH_INVALID			= 0,
 11	/* Values 1 - 28 are reserved for future use */
 12	IDPF_HASH_NONF_UNICAST_IPV4_UDP		= 29,
 13	IDPF_HASH_NONF_MULTICAST_IPV4_UDP,
 14	IDPF_HASH_NONF_IPV4_UDP,
 15	IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK,
 16	IDPF_HASH_NONF_IPV4_TCP,
 17	IDPF_HASH_NONF_IPV4_SCTP,
 18	IDPF_HASH_NONF_IPV4_OTHER,
 19	IDPF_HASH_FRAG_IPV4,
 20	/* Values 37-38 are reserved */
 21	IDPF_HASH_NONF_UNICAST_IPV6_UDP		= 39,
 22	IDPF_HASH_NONF_MULTICAST_IPV6_UDP,
 23	IDPF_HASH_NONF_IPV6_UDP,
 24	IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK,
 25	IDPF_HASH_NONF_IPV6_TCP,
 26	IDPF_HASH_NONF_IPV6_SCTP,
 27	IDPF_HASH_NONF_IPV6_OTHER,
 28	IDPF_HASH_FRAG_IPV6,
 29	IDPF_HASH_NONF_RSVD47,
 30	IDPF_HASH_NONF_FCOE_OX,
 31	IDPF_HASH_NONF_FCOE_RX,
 32	IDPF_HASH_NONF_FCOE_OTHER,
 33	/* Values 51-62 are reserved */
 34	IDPF_HASH_L2_PAYLOAD			= 63,
 35
 36	IDPF_HASH_MAX
 37};
 38
 39/* Supported RSS offloads */
 40#define IDPF_DEFAULT_RSS_HASH			\
 41	(BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) |	\
 42	BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) |	\
 43	BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) |	\
 44	BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) |	\
 45	BIT_ULL(IDPF_HASH_FRAG_IPV4) |		\
 46	BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) |	\
 47	BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) |	\
 48	BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) |	\
 49	BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) |	\
 50	BIT_ULL(IDPF_HASH_FRAG_IPV6) |		\
 51	BIT_ULL(IDPF_HASH_L2_PAYLOAD))
 52
 53#define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \
 54	BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) |		\
 55	BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) |		\
 56	BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) |		\
 57	BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) |		\
 58	BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) |		\
 59	BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP))
 60
 61/* For idpf_splitq_base_tx_compl_desc */
 62#define IDPF_TXD_COMPLQ_GEN_S		15
 63#define IDPF_TXD_COMPLQ_GEN_M		BIT_ULL(IDPF_TXD_COMPLQ_GEN_S)
 64#define IDPF_TXD_COMPLQ_COMPL_TYPE_S	11
 65#define IDPF_TXD_COMPLQ_COMPL_TYPE_M	GENMASK_ULL(13, 11)
 66#define IDPF_TXD_COMPLQ_QID_S		0
 67#define IDPF_TXD_COMPLQ_QID_M		GENMASK_ULL(9, 0)
 68
 69/* For base mode TX descriptors */
 70
 71#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S	23
 72#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M	BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S)
 73#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S	19
 74#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M	\
 75	(0xFULL << IDPF_TXD_CTX_QW0_TUNN_DECTTL_S)
 76#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S	12
 77#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M	\
 78	(0X7FULL << IDPF_TXD_CTX_QW0_TUNN_NATLEN_S)
 79#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S	11
 80#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M    \
 81	BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S)
 82#define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST	\
 83	IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M
 84#define IDPF_TXD_CTX_QW0_TUNN_NATT_S	        9
 85#define IDPF_TXD_CTX_QW0_TUNN_NATT_M	(0x3ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
 86#define IDPF_TXD_CTX_UDP_TUNNELING	BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S)
 87#define IDPF_TXD_CTX_GRE_TUNNELING	(0x2ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
 88#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S	2
 89#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M	\
 90	(0x3FULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S)
 91#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S	0
 92#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M	\
 93	(0x3ULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S)
 94
 95#define IDPF_TXD_CTX_QW1_MSS_S		50
 96#define IDPF_TXD_CTX_QW1_MSS_M		GENMASK_ULL(63, 50)
 97#define IDPF_TXD_CTX_QW1_TSO_LEN_S	30
 98#define IDPF_TXD_CTX_QW1_TSO_LEN_M	GENMASK_ULL(47, 30)
 99#define IDPF_TXD_CTX_QW1_CMD_S		4
100#define IDPF_TXD_CTX_QW1_CMD_M		GENMASK_ULL(15, 4)
101#define IDPF_TXD_CTX_QW1_DTYPE_S	0
102#define IDPF_TXD_CTX_QW1_DTYPE_M	GENMASK_ULL(3, 0)
103#define IDPF_TXD_QW1_L2TAG1_S		48
104#define IDPF_TXD_QW1_L2TAG1_M		GENMASK_ULL(63, 48)
105#define IDPF_TXD_QW1_TX_BUF_SZ_S	34
106#define IDPF_TXD_QW1_TX_BUF_SZ_M	GENMASK_ULL(47, 34)
107#define IDPF_TXD_QW1_OFFSET_S		16
108#define IDPF_TXD_QW1_OFFSET_M		GENMASK_ULL(33, 16)
109#define IDPF_TXD_QW1_CMD_S		4
110#define IDPF_TXD_QW1_CMD_M		GENMASK_ULL(15, 4)
111#define IDPF_TXD_QW1_DTYPE_S		0
112#define IDPF_TXD_QW1_DTYPE_M		GENMASK_ULL(3, 0)
113
114/* TX Completion Descriptor Completion Types */
115#define IDPF_TXD_COMPLT_ITR_FLUSH	0
116/* Descriptor completion type 1 is reserved */
117#define IDPF_TXD_COMPLT_RS		2
118/* Descriptor completion type 3 is reserved */
119#define IDPF_TXD_COMPLT_RE		4
120#define IDPF_TXD_COMPLT_SW_MARKER	5
121
122enum idpf_tx_desc_dtype_value {
123	IDPF_TX_DESC_DTYPE_DATA				= 0,
124	IDPF_TX_DESC_DTYPE_CTX				= 1,
125	/* DTYPE 2 is reserved
126	 * DTYPE 3 is free for future use
127	 * DTYPE 4 is reserved
128	 */
129	IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX			= 5,
130	/* DTYPE 6 is reserved */
131	IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2		= 7,
132	/* DTYPE 8, 9 are free for future use
133	 * DTYPE 10 is reserved
134	 * DTYPE 11 is free for future use
135	 */
136	IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE		= 12,
137	/* DTYPE 13, 14 are free for future use */
138
139	/* DESC_DONE - HW has completed write-back of descriptor */
140	IDPF_TX_DESC_DTYPE_DESC_DONE			= 15,
141};
142
143enum idpf_tx_ctx_desc_cmd_bits {
144	IDPF_TX_CTX_DESC_TSO		= 0x01,
145	IDPF_TX_CTX_DESC_TSYN		= 0x02,
146	IDPF_TX_CTX_DESC_IL2TAG2	= 0x04,
147	IDPF_TX_CTX_DESC_RSVD		= 0x08,
148	IDPF_TX_CTX_DESC_SWTCH_NOTAG	= 0x00,
149	IDPF_TX_CTX_DESC_SWTCH_UPLINK	= 0x10,
150	IDPF_TX_CTX_DESC_SWTCH_LOCAL	= 0x20,
151	IDPF_TX_CTX_DESC_SWTCH_VSI	= 0x30,
152	IDPF_TX_CTX_DESC_FILT_AU_EN	= 0x40,
153	IDPF_TX_CTX_DESC_FILT_AU_EVICT	= 0x80,
154	IDPF_TX_CTX_DESC_RSVD1		= 0xF00
155};
156
157enum idpf_tx_desc_len_fields {
158	/* Note: These are predefined bit offsets */
159	IDPF_TX_DESC_LEN_MACLEN_S	= 0, /* 7 BITS */
160	IDPF_TX_DESC_LEN_IPLEN_S	= 7, /* 7 BITS */
161	IDPF_TX_DESC_LEN_L4_LEN_S	= 14 /* 4 BITS */
162};
163
164enum idpf_tx_base_desc_cmd_bits {
165	IDPF_TX_DESC_CMD_EOP			= BIT(0),
166	IDPF_TX_DESC_CMD_RS			= BIT(1),
167	 /* only on VFs else RSVD */
168	IDPF_TX_DESC_CMD_ICRC			= BIT(2),
169	IDPF_TX_DESC_CMD_IL2TAG1		= BIT(3),
170	IDPF_TX_DESC_CMD_RSVD1			= BIT(4),
171	IDPF_TX_DESC_CMD_IIPT_IPV6		= BIT(5),
172	IDPF_TX_DESC_CMD_IIPT_IPV4		= BIT(6),
173	IDPF_TX_DESC_CMD_IIPT_IPV4_CSUM		= GENMASK(6, 5),
174	IDPF_TX_DESC_CMD_RSVD2			= BIT(7),
175	IDPF_TX_DESC_CMD_L4T_EOFT_TCP		= BIT(8),
176	IDPF_TX_DESC_CMD_L4T_EOFT_SCTP		= BIT(9),
177	IDPF_TX_DESC_CMD_L4T_EOFT_UDP		= GENMASK(9, 8),
178	IDPF_TX_DESC_CMD_RSVD3			= BIT(10),
179	IDPF_TX_DESC_CMD_RSVD4			= BIT(11),
180};
181
182/* Transmit descriptors  */
183/* splitq tx buf, singleq tx buf and singleq compl desc */
184struct idpf_base_tx_desc {
185	__le64 buf_addr; /* Address of descriptor's data buf */
186	__le64 qw1; /* type_cmd_offset_bsz_l2tag1 */
187}; /* read used with buffer queues */
188
189struct idpf_splitq_4b_tx_compl_desc {
190	/* qid=[10:0] comptype=[13:11] rsvd=[14] gen=[15] */
191	__le16 qid_comptype_gen;
192	union {
193		__le16 q_head; /* Queue head */
194		__le16 compl_tag; /* Completion tag */
195	} q_head_compl_tag;
196}; /* writeback used with completion queues */
197
198struct idpf_splitq_tx_compl_desc {
199	struct idpf_splitq_4b_tx_compl_desc common;
200	u8 ts[3];
201	u8 rsvd; /* Reserved */
202}; /* writeback used with completion queues */
203
204/* Context descriptors */
205struct idpf_base_tx_ctx_desc {
206	struct {
207		__le32 tunneling_params;
208		__le16 l2tag2;
209		__le16 rsvd1;
210	} qw0;
211	__le64 qw1; /* type_cmd_tlen_mss/rt_hint */
212};
213
214/* Common cmd field defines for all desc except Flex Flow Scheduler (0x0C) */
215enum idpf_tx_flex_desc_cmd_bits {
216	IDPF_TX_FLEX_DESC_CMD_EOP			= BIT(0),
217	IDPF_TX_FLEX_DESC_CMD_RS			= BIT(1),
218	IDPF_TX_FLEX_DESC_CMD_RE			= BIT(2),
219	IDPF_TX_FLEX_DESC_CMD_IL2TAG1			= BIT(3),
220	IDPF_TX_FLEX_DESC_CMD_DUMMY			= BIT(4),
221	IDPF_TX_FLEX_DESC_CMD_CS_EN			= BIT(5),
222	IDPF_TX_FLEX_DESC_CMD_FILT_AU_EN		= BIT(6),
223	IDPF_TX_FLEX_DESC_CMD_FILT_AU_EVICT		= BIT(7),
224};
225
226struct idpf_flex_tx_desc {
227	__le64 buf_addr;	/* Packet buffer address */
228	struct {
229#define IDPF_FLEX_TXD_QW1_DTYPE_S	0
230#define IDPF_FLEX_TXD_QW1_DTYPE_M	GENMASK(4, 0)
231#define IDPF_FLEX_TXD_QW1_CMD_S		5
232#define IDPF_FLEX_TXD_QW1_CMD_M		GENMASK(15, 5)
233		__le16 cmd_dtype;
234		/* DTYPE=IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 (0x07) */
235		struct {
236			__le16 l2tag1;
237			__le16 l2tag2;
238		} l2tags;
239		__le16 buf_size;
240	} qw1;
241};
242
243struct idpf_flex_tx_sched_desc {
244	__le64 buf_addr;	/* Packet buffer address */
245
246	/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE_16B (0x0C) */
247	struct {
248		u8 cmd_dtype;
249#define IDPF_TXD_FLEX_FLOW_DTYPE_M	GENMASK(4, 0)
250#define IDPF_TXD_FLEX_FLOW_CMD_EOP	BIT(5)
251#define IDPF_TXD_FLEX_FLOW_CMD_CS_EN	BIT(6)
252#define IDPF_TXD_FLEX_FLOW_CMD_RE	BIT(7)
253
254		/* [23:23] Horizon Overflow bit, [22:0] timestamp */
255		u8 ts[3];
256#define IDPF_TXD_FLOW_SCH_HORIZON_OVERFLOW_M	BIT(7)
257
258		__le16 compl_tag;
259		__le16 rxr_bufsize;
260#define IDPF_TXD_FLEX_FLOW_RXR		BIT(14)
261#define IDPF_TXD_FLEX_FLOW_BUFSIZE_M	GENMASK(13, 0)
262	} qw1;
263};
264
265/* Common cmd fields for all flex context descriptors
266 * Note: these defines already account for the 5 bit dtype in the cmd_dtype
267 * field
268 */
269enum idpf_tx_flex_ctx_desc_cmd_bits {
270	IDPF_TX_FLEX_CTX_DESC_CMD_TSO			= BIT(5),
271	IDPF_TX_FLEX_CTX_DESC_CMD_TSYN_EN		= BIT(6),
272	IDPF_TX_FLEX_CTX_DESC_CMD_L2TAG2		= BIT(7),
273	IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_UPLNK		= BIT(9),
274	IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_LOCAL		= BIT(10),
275	IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_TARGETVSI	= GENMASK(10, 9),
276};
277
278/* Standard flex descriptor TSO context quad word */
279struct idpf_flex_tx_tso_ctx_qw {
280	__le32 flex_tlen;
281#define IDPF_TXD_FLEX_CTX_TLEN_M	GENMASK(17, 0)
282#define IDPF_TXD_FLEX_TSO_CTX_FLEX_S	24
283	__le16 mss_rt;
284#define IDPF_TXD_FLEX_CTX_MSS_RT_M	GENMASK(13, 0)
285	u8 hdr_len;
286	u8 flex;
287};
288
289union idpf_flex_tx_ctx_desc {
290	/* DTYPE = IDPF_TX_DESC_DTYPE_CTX (0x01) */
291	struct {
292		__le64 qw0;
293#define IDPF_TX_CTX_L2TAG2_M	GENMASK_ULL(47, 32)
294		__le64 qw1;
295#define IDPF_TX_CTX_DTYPE_M	GENMASK_ULL(3, 0)
296#define IDPF_TX_CTX_CMD_M	GENMASK_ULL(15, 4)
297#define IDPF_TX_CTX_TSYN_REG_M	GENMASK_ULL(47, 30)
298#define IDPF_TX_CTX_MSS_M	GENMASK_ULL(50, 63)
299	} tsyn;
300
301	/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX (0x05) */
302	struct {
303		struct idpf_flex_tx_tso_ctx_qw qw0;
304		struct {
305			__le16 cmd_dtype;
306			u8 flex[6];
307		} qw1;
308	} tso;
309};
310#endif /* _IDPF_LAN_TXRX_H_ */