idpf_lan_pf_regs.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (C) 2023 Intel Corporation */
  3
  4#ifndef _IDPF_LAN_PF_REGS_H_
  5#define _IDPF_LAN_PF_REGS_H_
  6
  7/* Receive queues */
  8#define PF_QRX_BASE			0x00000000
  9#define PF_QRX_TAIL(_QRX)		(PF_QRX_BASE + (((_QRX) * 0x1000)))
 10#define PF_QRX_BUFFQ_BASE		0x03000000
 11#define PF_QRX_BUFFQ_TAIL(_QRX)		(PF_QRX_BUFFQ_BASE + (((_QRX) * 0x1000)))
 12
 13/* Transmit queues */
 14#define PF_QTX_BASE			0x05000000
 15#define PF_QTX_COMM_DBELL(_DBQM)	(PF_QTX_BASE + ((_DBQM) * 0x1000))
 16
 17/* Control(PF Mailbox) Queue */
 18#define PF_FW_BASE			0x08400000
 19
 20#define PF_FW_ARQBAL			(PF_FW_BASE)
 21#define PF_FW_ARQBAH			(PF_FW_BASE + 0x4)
 22#define PF_FW_ARQLEN			(PF_FW_BASE + 0x8)
 23#define PF_FW_ARQLEN_ARQLEN_S		0
 24#define PF_FW_ARQLEN_ARQLEN_M		GENMASK(12, 0)
 25#define PF_FW_ARQLEN_ARQVFE_S		28
 26#define PF_FW_ARQLEN_ARQVFE_M		BIT(PF_FW_ARQLEN_ARQVFE_S)
 27#define PF_FW_ARQLEN_ARQOVFL_S		29
 28#define PF_FW_ARQLEN_ARQOVFL_M		BIT(PF_FW_ARQLEN_ARQOVFL_S)
 29#define PF_FW_ARQLEN_ARQCRIT_S		30
 30#define PF_FW_ARQLEN_ARQCRIT_M		BIT(PF_FW_ARQLEN_ARQCRIT_S)
 31#define PF_FW_ARQLEN_ARQENABLE_S	31
 32#define PF_FW_ARQLEN_ARQENABLE_M	BIT(PF_FW_ARQLEN_ARQENABLE_S)
 33#define PF_FW_ARQH			(PF_FW_BASE + 0xC)
 34#define PF_FW_ARQH_ARQH_S		0
 35#define PF_FW_ARQH_ARQH_M		GENMASK(12, 0)
 36#define PF_FW_ARQT			(PF_FW_BASE + 0x10)
 37
 38#define PF_FW_ATQBAL			(PF_FW_BASE + 0x14)
 39#define PF_FW_ATQBAH			(PF_FW_BASE + 0x18)
 40#define PF_FW_ATQLEN			(PF_FW_BASE + 0x1C)
 41#define PF_FW_ATQLEN_ATQLEN_S		0
 42#define PF_FW_ATQLEN_ATQLEN_M		GENMASK(9, 0)
 43#define PF_FW_ATQLEN_ATQVFE_S		28
 44#define PF_FW_ATQLEN_ATQVFE_M		BIT(PF_FW_ATQLEN_ATQVFE_S)
 45#define PF_FW_ATQLEN_ATQOVFL_S		29
 46#define PF_FW_ATQLEN_ATQOVFL_M		BIT(PF_FW_ATQLEN_ATQOVFL_S)
 47#define PF_FW_ATQLEN_ATQCRIT_S		30
 48#define PF_FW_ATQLEN_ATQCRIT_M		BIT(PF_FW_ATQLEN_ATQCRIT_S)
 49#define PF_FW_ATQLEN_ATQENABLE_S	31
 50#define PF_FW_ATQLEN_ATQENABLE_M	BIT(PF_FW_ATQLEN_ATQENABLE_S)
 51#define PF_FW_ATQH			(PF_FW_BASE + 0x20)
 52#define PF_FW_ATQH_ATQH_S		0
 53#define PF_FW_ATQH_ATQH_M		GENMASK(9, 0)
 54#define PF_FW_ATQT			(PF_FW_BASE + 0x24)
 55
 56/* Timesync registers */
 57#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M	GENMASK(1, 0)
 58#define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M	BIT(2)
 59
 60/* Interrupts */
 61#define PF_GLINT_BASE			0x08900000
 62#define PF_GLINT_DYN_CTL(_INT)		(PF_GLINT_BASE + ((_INT) * 0x1000))
 63#define PF_GLINT_DYN_CTL_INTENA_S	0
 64#define PF_GLINT_DYN_CTL_INTENA_M	BIT(PF_GLINT_DYN_CTL_INTENA_S)
 65#define PF_GLINT_DYN_CTL_CLEARPBA_S	1
 66#define PF_GLINT_DYN_CTL_CLEARPBA_M	BIT(PF_GLINT_DYN_CTL_CLEARPBA_S)
 67#define PF_GLINT_DYN_CTL_SWINT_TRIG_S	2
 68#define PF_GLINT_DYN_CTL_SWINT_TRIG_M	BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S)
 69#define PF_GLINT_DYN_CTL_ITR_INDX_S	3
 70#define PF_GLINT_DYN_CTL_ITR_INDX_M	GENMASK(4, 3)
 71#define PF_GLINT_DYN_CTL_INTERVAL_S	5
 72#define PF_GLINT_DYN_CTL_INTERVAL_M	BIT(PF_GLINT_DYN_CTL_INTERVAL_S)
 73#define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S	24
 74#define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S)
 75#define PF_GLINT_DYN_CTL_SW_ITR_INDX_S	25
 76#define PF_GLINT_DYN_CTL_SW_ITR_INDX_M	BIT(PF_GLINT_DYN_CTL_SW_ITR_INDX_S)
 77#define PF_GLINT_DYN_CTL_WB_ON_ITR_S	30
 78#define PF_GLINT_DYN_CTL_WB_ON_ITR_M	BIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S)
 79#define PF_GLINT_DYN_CTL_INTENA_MSK_S	31
 80#define PF_GLINT_DYN_CTL_INTENA_MSK_M	BIT(PF_GLINT_DYN_CTL_INTENA_MSK_S)
 81/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is
 82 * spacing b/w itrn registers of the same vector.
 83 */
 84#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing)	\
 85	((_reg_start) + ((_ITR) * (_itrn_indx_spacing)))
 86/* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */
 87#define PF_GLINT_ITR(_ITR, _INT)	\
 88	(PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))
 89#define PF_GLINT_ITR_MAX_INDEX		2
 90#define PF_GLINT_ITR_INTERVAL_S		0
 91#define PF_GLINT_ITR_INTERVAL_M		GENMASK(11, 0)
 92
 93/* Generic registers */
 94#define PF_INT_DIR_OICR_ENA		0x08406000
 95#define PF_INT_DIR_OICR_ENA_S		0
 96#define PF_INT_DIR_OICR_ENA_M		GENMASK(31, 0)
 97#define PF_INT_DIR_OICR			0x08406004
 98#define PF_INT_DIR_OICR_TSYN_EVNT	0
 99#define PF_INT_DIR_OICR_PHY_TS_0	BIT(1)
100#define PF_INT_DIR_OICR_PHY_TS_1	BIT(2)
101#define PF_INT_DIR_OICR_CAUSE		0x08406008
102#define PF_INT_DIR_OICR_CAUSE_CAUSE_S	0
103#define PF_INT_DIR_OICR_CAUSE_CAUSE_M	GENMASK(31, 0)
104#define PF_INT_PBA_CLEAR		0x0840600C
105
106#define PF_FUNC_RID			0x08406010
107#define PF_FUNC_RID_FUNCTION_NUMBER_S	0
108#define PF_FUNC_RID_FUNCTION_NUMBER_M	GENMASK(2, 0)
109#define PF_FUNC_RID_DEVICE_NUMBER_S	3
110#define PF_FUNC_RID_DEVICE_NUMBER_M	GENMASK(7, 3)
111#define PF_FUNC_RID_BUS_NUMBER_S	8
112#define PF_FUNC_RID_BUS_NUMBER_M	GENMASK(15, 8)
113
114/* Reset registers */
115#define PFGEN_RTRIG			0x08407000
116#define PFGEN_RTRIG_CORER_S		0
117#define PFGEN_RTRIG_CORER_M		BIT(0)
118#define PFGEN_RTRIG_LINKR_S		1
119#define PFGEN_RTRIG_LINKR_M		BIT(1)
120#define PFGEN_RTRIG_IMCR_S		2
121#define PFGEN_RTRIG_IMCR_M		BIT(2)
122#define PFGEN_RSTAT			0x08407008 /* PFR Status */
123#define PFGEN_RSTAT_PFR_STATE_S		0
124#define PFGEN_RSTAT_PFR_STATE_M		GENMASK(1, 0)
125#define PFGEN_CTRL			0x0840700C
126#define PFGEN_CTRL_PFSWR		BIT(0)
127
128#endif