ice_type.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2018-2023, Intel Corporation. */
   3
   4#ifndef _ICE_TYPE_H_
   5#define _ICE_TYPE_H_
   6
   7#define ICE_BYTES_PER_WORD	2
   8#define ICE_BYTES_PER_DWORD	4
   9#define ICE_CHNL_MAX_TC		16
  10
  11#include "ice_hw_autogen.h"
  12#include "ice_devids.h"
  13#include "ice_osdep.h"
  14#include "ice_controlq.h"
  15#include "ice_lan_tx_rx.h"
  16#include "ice_flex_type.h"
  17#include "ice_protocol_type.h"
  18#include "ice_sbq_cmd.h"
  19#include "ice_vlan_mode.h"
  20#include <linux/net/intel/libie/fwlog.h>
  21#include <linux/wait.h>
  22#include <net/dscp.h>
  23
  24static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
  25{
  26	return test_bit(tc, &bitmap);
  27}
  28
  29static inline u64 round_up_64bit(u64 a, u32 b)
  30{
  31	return div64_long(((a) + (b) / 2), (b));
  32}
  33
  34static inline u32 ice_round_to_num(u32 N, u32 R)
  35{
  36	return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
  37		((((N) + (R) - 1) / (R)) * (R)));
  38}
  39
  40/* Driver always calls main vsi_handle first */
  41#define ICE_MAIN_VSI_HANDLE		0
  42
  43/* debug masks - set these bits in hw->debug_mask to control output */
  44#define ICE_DBG_INIT		BIT_ULL(1)
  45#define ICE_DBG_FW_LOG		BIT_ULL(3)
  46#define ICE_DBG_LINK		BIT_ULL(4)
  47#define ICE_DBG_PHY		BIT_ULL(5)
  48#define ICE_DBG_QCTX		BIT_ULL(6)
  49#define ICE_DBG_NVM		BIT_ULL(7)
  50#define ICE_DBG_LAN		BIT_ULL(8)
  51#define ICE_DBG_FLOW		BIT_ULL(9)
  52#define ICE_DBG_SW		BIT_ULL(13)
  53#define ICE_DBG_SCHED		BIT_ULL(14)
  54#define ICE_DBG_RDMA		BIT_ULL(15)
  55#define ICE_DBG_PKG		BIT_ULL(16)
  56#define ICE_DBG_RES		BIT_ULL(17)
  57#define ICE_DBG_PTP		BIT_ULL(19)
  58#define ICE_DBG_AQ_MSG		BIT_ULL(24)
  59#define ICE_DBG_AQ_DESC		BIT_ULL(25)
  60#define ICE_DBG_AQ_DESC_BUF	BIT_ULL(26)
  61#define ICE_DBG_AQ_CMD		BIT_ULL(27)
  62#define ICE_DBG_AQ		(ICE_DBG_AQ_MSG		| \
  63				 ICE_DBG_AQ_DESC	| \
  64				 ICE_DBG_AQ_DESC_BUF	| \
  65				 ICE_DBG_AQ_CMD)
  66#define ICE_DBG_PARSER		BIT_ULL(28)
  67
  68#define ICE_DBG_USER		BIT_ULL(31)
  69
  70enum ice_aq_res_ids {
  71	ICE_NVM_RES_ID = 1,
  72	ICE_SPD_RES_ID,
  73	ICE_CHANGE_LOCK_RES_ID,
  74	ICE_GLOBAL_CFG_LOCK_RES_ID
  75};
  76
  77enum ice_fec_stats_types {
  78	ICE_FEC_CORR_LOW,
  79	ICE_FEC_CORR_HIGH,
  80	ICE_FEC_UNCORR_LOW,
  81	ICE_FEC_UNCORR_HIGH,
  82	ICE_FEC_MAX
  83};
  84
  85/* FW update timeout definitions are in milliseconds */
  86#define ICE_NVM_TIMEOUT			180000
  87#define ICE_CHANGE_LOCK_TIMEOUT		1000
  88#define ICE_GLOBAL_CFG_LOCK_TIMEOUT	5000
  89
  90enum ice_aq_res_access_type {
  91	ICE_RES_READ = 1,
  92	ICE_RES_WRITE
  93};
  94
  95struct ice_driver_ver {
  96	u8 major_ver;
  97	u8 minor_ver;
  98	u8 build_ver;
  99	u8 subbuild_ver;
 100	u8 driver_string[32];
 101};
 102
 103enum ice_fc_mode {
 104	ICE_FC_NONE = 0,
 105	ICE_FC_RX_PAUSE,
 106	ICE_FC_TX_PAUSE,
 107	ICE_FC_FULL,
 108	ICE_FC_PFC,
 109	ICE_FC_DFLT
 110};
 111
 112enum ice_phy_cache_mode {
 113	ICE_FC_MODE = 0,
 114	ICE_SPEED_MODE,
 115	ICE_FEC_MODE
 116};
 117
 118enum ice_fec_mode {
 119	ICE_FEC_NONE = 0,
 120	ICE_FEC_RS,
 121	ICE_FEC_BASER,
 122	ICE_FEC_AUTO
 123};
 124
 125struct ice_phy_cache_mode_data {
 126	union {
 127		enum ice_fec_mode curr_user_fec_req;
 128		enum ice_fc_mode curr_user_fc_req;
 129		u16 curr_user_speed_req;
 130	} data;
 131};
 132
 133enum ice_set_fc_aq_failures {
 134	ICE_SET_FC_AQ_FAIL_NONE = 0,
 135	ICE_SET_FC_AQ_FAIL_GET,
 136	ICE_SET_FC_AQ_FAIL_SET,
 137	ICE_SET_FC_AQ_FAIL_UPDATE
 138};
 139
 140/* Various MAC types */
 141enum ice_mac_type {
 142	ICE_MAC_UNKNOWN = 0,
 143	ICE_MAC_E810,
 144	ICE_MAC_E830,
 145	ICE_MAC_GENERIC,
 146	ICE_MAC_GENERIC_3K_E825,
 147};
 148
 149/* Media Types */
 150enum ice_media_type {
 151	ICE_MEDIA_UNKNOWN = 0,
 152	ICE_MEDIA_FIBER,
 153	ICE_MEDIA_BASET,
 154	ICE_MEDIA_BACKPLANE,
 155	ICE_MEDIA_DA,
 156};
 157
 158enum ice_vsi_type {
 159	ICE_VSI_PF = 0,
 160	ICE_VSI_VF = 1,
 161	ICE_VSI_CTRL = 3,	/* equates to ICE_VSI_PF with 1 queue pair */
 162	ICE_VSI_CHNL = 4,
 163	ICE_VSI_LB = 6,
 164	ICE_VSI_SF = 9,
 165};
 166
 167struct ice_link_status {
 168	/* Refer to ice_aq_phy_type for bits definition */
 169	u64 phy_type_low;
 170	u64 phy_type_high;
 171	u8 topo_media_conflict;
 172	u16 max_frame_size;
 173	u16 link_speed;
 174	u16 req_speeds;
 175	u8 link_cfg_err;
 176	u8 lse_ena;	/* Link Status Event notification */
 177	u8 link_info;
 178	u8 an_info;
 179	u8 ext_info;
 180	u8 fec_info;
 181	u8 pacing;
 182	/* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
 183	 * ice_aqc_get_phy_caps structure
 184	 */
 185	u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
 186};
 187
 188/* Different reset sources for which a disable queue AQ call has to be made in
 189 * order to clean the Tx scheduler as a part of the reset
 190 */
 191enum ice_disq_rst_src {
 192	ICE_NO_RESET = 0,
 193	ICE_VM_RESET,
 194	ICE_VF_RESET,
 195};
 196
 197/* PHY info such as phy_type, etc... */
 198struct ice_phy_info {
 199	struct ice_link_status link_info;
 200	struct ice_link_status link_info_old;
 201	u64 phy_type_low;
 202	u64 phy_type_high;
 203	enum ice_media_type media_type;
 204	u8 get_link_info;
 205	/* Please refer to struct ice_aqc_get_link_status_data to get
 206	 * detail of enable bit in curr_user_speed_req
 207	 */
 208	u16 curr_user_speed_req;
 209	enum ice_fec_mode curr_user_fec_req;
 210	enum ice_fc_mode curr_user_fc_req;
 211	struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
 212};
 213
 214/* protocol enumeration for filters */
 215enum ice_fltr_ptype {
 216	/* NONE - used for undef/error */
 217	ICE_FLTR_PTYPE_NONF_NONE = 0,
 218	ICE_FLTR_PTYPE_NONF_ETH,
 219	ICE_FLTR_PTYPE_NONF_IPV4_UDP,
 220	ICE_FLTR_PTYPE_NONF_IPV4_TCP,
 221	ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
 222	ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
 223	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
 224	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
 225	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
 226	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
 227	ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
 228	ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
 229	ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
 230	ICE_FLTR_PTYPE_NONF_IPV4_ESP,
 231	ICE_FLTR_PTYPE_NONF_IPV6_ESP,
 232	ICE_FLTR_PTYPE_NONF_IPV4_AH,
 233	ICE_FLTR_PTYPE_NONF_IPV6_AH,
 234	ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
 235	ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
 236	ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
 237	ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
 238	ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
 239	ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
 240	ICE_FLTR_PTYPE_NON_IP_L2,
 241	ICE_FLTR_PTYPE_FRAG_IPV4,
 242	ICE_FLTR_PTYPE_NONF_IPV6_UDP,
 243	ICE_FLTR_PTYPE_NONF_IPV6_TCP,
 244	ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
 245	ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
 246	ICE_FLTR_PTYPE_MAX,
 247};
 248
 249enum ice_fd_hw_seg {
 250	ICE_FD_HW_SEG_NON_TUN = 0,
 251	ICE_FD_HW_SEG_TUN,
 252	ICE_FD_HW_SEG_MAX,
 253};
 254
 255/* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */
 256#define ICE_MAX_FDIR_VSI_PER_FILTER	(2 + ICE_CHNL_MAX_TC)
 257
 258struct ice_fd_hw_prof {
 259	struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
 260	int cnt;
 261	u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
 262	u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
 263	u64 prof_id[ICE_FD_HW_SEG_MAX];
 264};
 265
 266/* Common HW capabilities for SW use */
 267struct ice_hw_common_caps {
 268	u32 valid_functions;
 269	/* DCB capabilities */
 270	u32 active_tc_bitmap;
 271	u32 maxtc;
 272
 273	/* Tx/Rx queues */
 274	u16 num_rxq;		/* Number/Total Rx queues */
 275	u16 rxq_first_id;	/* First queue ID for Rx queues */
 276	u16 num_txq;		/* Number/Total Tx queues */
 277	u16 txq_first_id;	/* First queue ID for Tx queues */
 278
 279	/* MSI-X vectors */
 280	u16 num_msix_vectors;
 281	u16 msix_vector_first_id;
 282
 283	/* Max MTU for function or device */
 284	u16 max_mtu;
 285
 286	/* Virtualization support */
 287	u8 sr_iov_1_1;			/* SR-IOV enabled */
 288
 289	/* RSS related capabilities */
 290	u16 rss_table_size;		/* 512 for PFs and 64 for VFs */
 291	u8 rss_table_entry_width;	/* RSS Entry width in bits */
 292
 293	u8 dcb;
 294	u8 ieee_1588;
 295	u8 rdma;
 296
 297	bool roce_lag;
 298	bool sriov_lag;
 299	bool sriov_aa_lag;
 300
 301	bool nvm_update_pending_nvm;
 302	bool nvm_update_pending_orom;
 303	bool nvm_update_pending_netlist;
 304#define ICE_NVM_PENDING_NVM_IMAGE		BIT(0)
 305#define ICE_NVM_PENDING_OROM			BIT(1)
 306#define ICE_NVM_PENDING_NETLIST			BIT(2)
 307	bool nvm_unified_update;
 308#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT	BIT(3)
 309	/* PCIe reset avoidance */
 310	bool pcie_reset_avoidance;
 311	/* Post update reset restriction */
 312	bool reset_restrict_support;
 313	bool tx_sched_topo_comp_mode_en;
 314};
 315
 316/* IEEE 1588 TIME_SYNC specific info */
 317/* Function specific definitions */
 318#define ICE_TS_FUNC_ENA_M		BIT(0)
 319#define ICE_TS_SRC_TMR_OWND_M		BIT(1)
 320#define ICE_TS_TMR_ENA_M		BIT(2)
 321#define ICE_TS_TMR_IDX_OWND_S		4
 322#define ICE_TS_TMR_IDX_OWND_M		BIT(4)
 323#define ICE_TS_CLK_FREQ_S		16
 324#define ICE_TS_CLK_FREQ_M		ICE_M(0x7, ICE_TS_CLK_FREQ_S)
 325#define ICE_TS_CLK_SRC_S		20
 326#define ICE_TS_CLK_SRC_M		BIT(20)
 327#define ICE_TS_TMR_IDX_ASSOC_S		24
 328#define ICE_TS_TMR_IDX_ASSOC_M		BIT(24)
 329
 330/* TIME_REF clock rate specification */
 331enum ice_tspll_freq {
 332	ICE_TSPLL_FREQ_25_000	= 0,
 333	ICE_TSPLL_FREQ_122_880	= 1,
 334	ICE_TSPLL_FREQ_125_000	= 2,
 335	ICE_TSPLL_FREQ_153_600	= 3,
 336	ICE_TSPLL_FREQ_156_250	= 4,
 337	ICE_TSPLL_FREQ_245_760	= 5,
 338
 339	NUM_ICE_TSPLL_FREQ,
 340
 341	ICE_TSPLL_FREQ_INVALID	= -1,
 342};
 343
 344/* Clock source specification */
 345enum ice_clk_src {
 346	ICE_CLK_SRC_TCXO	= 0, /* Temperature compensated oscillator */
 347	ICE_CLK_SRC_TIME_REF	= 1, /* Use TIME_REF reference clock */
 348
 349	NUM_ICE_CLK_SRC
 350};
 351
 352struct ice_ts_func_info {
 353	/* Function specific info */
 354	enum ice_tspll_freq time_ref;
 355	u8 clk_freq;
 356	u8 clk_src;
 357	u8 tmr_index_assoc;
 358	u8 ena;
 359	u8 tmr_index_owned;
 360	u8 src_tmr_owned;
 361	u8 tmr_ena;
 362};
 363
 364/* Device specific definitions */
 365#define ICE_TS_TMR0_OWNR_M		0x7
 366#define ICE_TS_TMR0_OWND_M		BIT(3)
 367#define ICE_TS_TMR1_OWNR_S		4
 368#define ICE_TS_TMR1_OWNR_M		ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
 369#define ICE_TS_TMR1_OWND_M		BIT(7)
 370#define ICE_TS_DEV_ENA_M		BIT(24)
 371#define ICE_TS_TMR0_ENA_M		BIT(25)
 372#define ICE_TS_TMR1_ENA_M		BIT(26)
 373#define ICE_TS_LL_TX_TS_READ_M		BIT(28)
 374#define ICE_TS_LL_TX_TS_INT_READ_M	BIT(29)
 375#define ICE_TS_LL_PHY_TMR_UPDATE_M	BIT(30)
 376
 377struct ice_ts_dev_info {
 378	/* Device specific info */
 379	u32 ena_ports;
 380	u32 tmr_own_map;
 381	u32 tmr0_owner;
 382	u32 tmr1_owner;
 383	u8 tmr0_owned;
 384	u8 tmr1_owned;
 385	u8 ena;
 386	u8 tmr0_ena;
 387	u8 tmr1_ena;
 388	u8 ts_ll_read;
 389	u8 ts_ll_int_read;
 390	u8 ll_phy_tmr_update;
 391};
 392
 393#define ICE_NAC_TOPO_PRIMARY_M	BIT(0)
 394#define ICE_NAC_TOPO_DUAL_M	BIT(1)
 395#define ICE_NAC_TOPO_ID_M	GENMASK(0xF, 0)
 396
 397struct ice_nac_topology {
 398	u32 mode;
 399	u8 id;
 400};
 401
 402/* Function specific capabilities */
 403struct ice_hw_func_caps {
 404	struct ice_hw_common_caps common_cap;
 405	u32 num_allocd_vfs;		/* Number of allocated VFs */
 406	u32 vf_base_id;			/* Logical ID of the first VF */
 407	u32 guar_num_vsi;
 408	u32 fd_fltr_guar;		/* Number of filters guaranteed */
 409	u32 fd_fltr_best_effort;	/* Number of best effort filters */
 410	struct ice_ts_func_info ts_func_info;
 411};
 412
 413#define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT	0
 414
 415/* Device wide capabilities */
 416struct ice_hw_dev_caps {
 417	struct ice_hw_common_caps common_cap;
 418	u32 num_vfs_exposed;		/* Total number of VFs exposed */
 419	u32 num_vsi_allocd_to_host;	/* Excluding EMP VSI */
 420	u32 num_flow_director_fltr;	/* Number of FD filters available */
 421	struct ice_ts_dev_info ts_dev_info;
 422	u32 num_funcs;
 423	struct ice_nac_topology nac_topo;
 424	/* bitmap of supported sensors
 425	 * bit 0 - internal temperature sensor
 426	 * bit 31:1 - Reserved
 427	 */
 428	u32 supported_sensors;
 429};
 430
 431/* MAC info */
 432struct ice_mac_info {
 433	u8 lan_addr[ETH_ALEN];
 434	u8 perm_addr[ETH_ALEN];
 435};
 436
 437/* Reset types used to determine which kind of reset was requested. These
 438 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
 439 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
 440 * because its reset source is different than the other types listed.
 441 */
 442enum ice_reset_req {
 443	ICE_RESET_POR	= 0,
 444	ICE_RESET_INVAL	= 0,
 445	ICE_RESET_CORER	= 1,
 446	ICE_RESET_GLOBR	= 2,
 447	ICE_RESET_EMPR	= 3,
 448	ICE_RESET_PFR	= 4,
 449};
 450
 451/* Bus parameters */
 452struct ice_bus_info {
 453	u16 device;
 454	u8 func;
 455};
 456
 457/* Flow control (FC) parameters */
 458struct ice_fc_info {
 459	enum ice_fc_mode current_mode;	/* FC mode in effect */
 460	enum ice_fc_mode req_mode;	/* FC mode requested by caller */
 461};
 462
 463/* Option ROM version information */
 464struct ice_orom_info {
 465	u8 major;			/* Major version of OROM */
 466	u8 patch;			/* Patch version of OROM */
 467	u16 build;			/* Build version of OROM */
 468};
 469
 470/* NVM version information */
 471struct ice_nvm_info {
 472	u32 eetrack;
 473	u8 major;
 474	u8 minor;
 475};
 476
 477/* netlist version information */
 478struct ice_netlist_info {
 479	u32 major;			/* major high/low */
 480	u32 minor;			/* minor high/low */
 481	u32 type;			/* type high/low */
 482	u32 rev;			/* revision high/low */
 483	u32 hash;			/* SHA-1 hash word */
 484	u16 cust_ver;			/* customer version */
 485};
 486
 487/* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
 488 * of the flash image.
 489 */
 490enum ice_flash_bank {
 491	ICE_INVALID_FLASH_BANK,
 492	ICE_1ST_FLASH_BANK,
 493	ICE_2ND_FLASH_BANK,
 494};
 495
 496/* Enumeration of which flash bank is desired to read from, either the active
 497 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
 498 * code which just wants to read the active or inactive flash bank.
 499 */
 500enum ice_bank_select {
 501	ICE_ACTIVE_FLASH_BANK,
 502	ICE_INACTIVE_FLASH_BANK,
 503};
 504
 505/* information for accessing NVM, OROM, and Netlist flash banks */
 506struct ice_bank_info {
 507	u32 nvm_ptr;				/* Pointer to 1st NVM bank */
 508	u32 nvm_size;				/* Size of NVM bank */
 509	u32 orom_ptr;				/* Pointer to 1st OROM bank */
 510	u32 orom_size;				/* Size of OROM bank */
 511	u32 netlist_ptr;			/* Pointer to 1st Netlist bank */
 512	u32 netlist_size;			/* Size of Netlist bank */
 513	u32 active_css_hdr_len;			/* Active CSS header length */
 514	u32 inactive_css_hdr_len;		/* Inactive CSS header length */
 515	enum ice_flash_bank nvm_bank;		/* Active NVM bank */
 516	enum ice_flash_bank orom_bank;		/* Active OROM bank */
 517	enum ice_flash_bank netlist_bank;	/* Active Netlist bank */
 518};
 519
 520/* Flash Chip Information */
 521struct ice_flash_info {
 522	struct ice_orom_info orom;	/* Option ROM version info */
 523	struct ice_nvm_info nvm;	/* NVM version information */
 524	struct ice_netlist_info netlist;/* Netlist version info */
 525	struct ice_bank_info banks;	/* Flash Bank information */
 526	u16 sr_words;			/* Shadow RAM size in words */
 527	u32 flash_size;			/* Size of available flash in bytes */
 528	u8 blank_nvm_mode;		/* is NVM empty (no FW present) */
 529};
 530
 531struct ice_link_default_override_tlv {
 532	u8 options;
 533#define ICE_LINK_OVERRIDE_OPT_M		0x3F
 534#define ICE_LINK_OVERRIDE_STRICT_MODE	BIT(0)
 535#define ICE_LINK_OVERRIDE_EPCT_DIS	BIT(1)
 536#define ICE_LINK_OVERRIDE_PORT_DIS	BIT(2)
 537#define ICE_LINK_OVERRIDE_EN		BIT(3)
 538#define ICE_LINK_OVERRIDE_AUTO_LINK_DIS	BIT(4)
 539#define ICE_LINK_OVERRIDE_EEE_EN	BIT(5)
 540	u8 phy_config;
 541#define ICE_LINK_OVERRIDE_PHY_CFG_S	8
 542#define ICE_LINK_OVERRIDE_PHY_CFG_M	(0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
 543#define ICE_LINK_OVERRIDE_PAUSE_M	0x3
 544#define ICE_LINK_OVERRIDE_LESM_EN	BIT(6)
 545#define ICE_LINK_OVERRIDE_AUTO_FEC_EN	BIT(7)
 546	u8 fec_options;
 547#define ICE_LINK_OVERRIDE_FEC_OPT_M	0xFF
 548	u8 rsvd1;
 549	u64 phy_type_low;
 550	u64 phy_type_high;
 551};
 552
 553#define ICE_NVM_VER_LEN	32
 554
 555/* Max number of port to queue branches w.r.t topology */
 556#define ICE_MAX_TRAFFIC_CLASS 8
 557#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
 558
 559#define ice_for_each_traffic_class(_i)	\
 560	for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
 561
 562/* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
 563 * to driver defined policy for default aggregator
 564 */
 565#define ICE_INVAL_TEID 0xFFFFFFFF
 566#define ICE_DFLT_AGG_ID 0
 567
 568struct ice_sched_node {
 569	struct ice_sched_node *parent;
 570	struct ice_sched_node *sibling; /* next sibling in the same layer */
 571	struct ice_sched_node **children;
 572	struct ice_aqc_txsched_elem_data info;
 573	char *name;
 574	struct devlink_rate *rate_node;
 575	u64 tx_max;
 576	u64 tx_share;
 577	u32 agg_id;			/* aggregator group ID */
 578	u32 id;
 579	u32 tx_priority;
 580	u32 tx_weight;
 581	u16 vsi_handle;
 582	u8 in_use;			/* suspended or in use */
 583	u8 tx_sched_layer;		/* Logical Layer (1-9) */
 584	u8 num_children;
 585	u8 tc_num;
 586	u8 owner;
 587#define ICE_SCHED_NODE_OWNER_LAN	0
 588#define ICE_SCHED_NODE_OWNER_RDMA	2
 589};
 590
 591/* Access Macros for Tx Sched Elements data */
 592#define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
 593
 594/* The aggregator type determines if identifier is for a VSI group,
 595 * aggregator group, aggregator of queues, or queue group.
 596 */
 597enum ice_agg_type {
 598	ICE_AGG_TYPE_UNKNOWN = 0,
 599	ICE_AGG_TYPE_VSI,
 600	ICE_AGG_TYPE_AGG, /* aggregator */
 601	ICE_AGG_TYPE_Q,
 602	ICE_AGG_TYPE_QG
 603};
 604
 605/* Rate limit types */
 606enum ice_rl_type {
 607	ICE_UNKNOWN_BW = 0,
 608	ICE_MIN_BW,		/* for CIR profile */
 609	ICE_MAX_BW,		/* for EIR profile */
 610	ICE_SHARED_BW		/* for shared profile */
 611};
 612
 613#define ICE_SCHED_MIN_BW		500		/* in Kbps */
 614#define ICE_SCHED_MAX_BW		100000000	/* in Kbps */
 615#define ICE_SCHED_DFLT_BW		0xFFFFFFFF	/* unlimited */
 616#define ICE_SCHED_DFLT_RL_PROF_ID	0
 617#define ICE_SCHED_NO_SHARED_RL_PROF_ID	0xFFFF
 618#define ICE_SCHED_DFLT_BW_WT		4
 619#define ICE_SCHED_INVAL_PROF_ID		0xFFFF
 620#define ICE_SCHED_DFLT_BURST_SIZE	(15 * 1024)	/* in bytes (15k) */
 621
 622#define ICE_MAX_PORT_PER_PCI_DEV 8
 623
 624 /* Data structure for saving BW information */
 625enum ice_bw_type {
 626	ICE_BW_TYPE_PRIO,
 627	ICE_BW_TYPE_CIR,
 628	ICE_BW_TYPE_CIR_WT,
 629	ICE_BW_TYPE_EIR,
 630	ICE_BW_TYPE_EIR_WT,
 631	ICE_BW_TYPE_SHARED,
 632	ICE_BW_TYPE_CNT		/* This must be last */
 633};
 634
 635struct ice_bw {
 636	u32 bw;
 637	u16 bw_alloc;
 638};
 639
 640struct ice_bw_type_info {
 641	DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
 642	u8 generic;
 643	struct ice_bw cir_bw;
 644	struct ice_bw eir_bw;
 645	u32 shared_bw;
 646};
 647
 648/* VSI queue context structure for given TC */
 649struct ice_q_ctx {
 650	u16  q_handle;
 651	u32  q_teid;
 652	/* bw_t_info saves queue BW information */
 653	struct ice_bw_type_info bw_t_info;
 654};
 655
 656/* VSI type list entry to locate corresponding VSI/aggregator nodes */
 657struct ice_sched_vsi_info {
 658	struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
 659	struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
 660	struct list_head list_entry;
 661	u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
 662	u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
 663	/* bw_t_info saves VSI BW information */
 664	struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
 665};
 666
 667/* driver defines the policy */
 668struct ice_sched_tx_policy {
 669	u16 max_num_vsis;
 670	u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
 671	u8 rdma_ena;
 672};
 673
 674/* CEE or IEEE 802.1Qaz ETS Configuration data */
 675struct ice_dcb_ets_cfg {
 676	u8 willing;
 677	u8 cbs;
 678	u8 maxtcs;
 679	u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
 680	u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
 681	u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
 682};
 683
 684/* CEE or IEEE 802.1Qaz PFC Configuration data */
 685struct ice_dcb_pfc_cfg {
 686	u8 willing;
 687	u8 mbc;
 688	u8 pfccap;
 689	u8 pfcena;
 690};
 691
 692/* CEE or IEEE 802.1Qaz Application Priority data */
 693struct ice_dcb_app_priority_table {
 694	u16 prot_id;
 695	u8 priority;
 696	u8 selector;
 697};
 698
 699#define ICE_MAX_USER_PRIORITY	8
 700#define ICE_DCBX_MAX_APPS	64
 701#define ICE_LLDPDU_SIZE		1500
 702#define ICE_TLV_STATUS_OPER	0x1
 703#define ICE_TLV_STATUS_SYNC	0x2
 704#define ICE_TLV_STATUS_ERR	0x4
 705#define ICE_APP_PROT_ID_ISCSI_860 0x035c
 706#define ICE_APP_SEL_ETHTYPE	0x1
 707#define ICE_APP_SEL_TCPIP	0x2
 708#define ICE_CEE_APP_SEL_ETHTYPE	0x0
 709#define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR	0x134
 710#define ICE_CEE_APP_SEL_TCPIP	0x1
 711
 712struct ice_dcbx_cfg {
 713	u32 numapps;
 714	u32 tlv_status; /* CEE mode TLV status */
 715	struct ice_dcb_ets_cfg etscfg;
 716	struct ice_dcb_ets_cfg etsrec;
 717	struct ice_dcb_pfc_cfg pfc;
 718#define ICE_QOS_MODE_VLAN	0x0
 719#define ICE_QOS_MODE_DSCP	0x1
 720	u8 pfc_mode;
 721	struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
 722	/* when DSCP mapping defined by user set its bit to 1 */
 723	DECLARE_BITMAP(dscp_mapped, DSCP_MAX);
 724	/* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
 725	u8 dscp_map[DSCP_MAX];
 726	u8 dcbx_mode;
 727#define ICE_DCBX_MODE_CEE	0x1
 728#define ICE_DCBX_MODE_IEEE	0x2
 729	u8 app_mode;
 730#define ICE_DCBX_APPS_NON_WILLING	0x1
 731};
 732
 733struct ice_qos_cfg {
 734	struct ice_dcbx_cfg local_dcbx_cfg;	/* Oper/Local Cfg */
 735	struct ice_dcbx_cfg desired_dcbx_cfg;	/* CEE Desired Cfg */
 736	struct ice_dcbx_cfg remote_dcbx_cfg;	/* Peer Cfg */
 737	u8 dcbx_status : 3;			/* see ICE_DCBX_STATUS_DIS */
 738	u8 is_sw_lldp : 1;
 739};
 740
 741struct ice_port_info {
 742	struct ice_sched_node *root;	/* Root Node per Port */
 743	struct ice_hw *hw;		/* back pointer to HW instance */
 744	u32 last_node_teid;		/* scheduler last node info */
 745	u16 sw_id;			/* Initial switch ID belongs to port */
 746	u16 pf_vf_num;
 747	u8 port_state;
 748	u8 local_fwd_mode;
 749#define ICE_SCHED_PORT_STATE_INIT	0x0
 750#define ICE_SCHED_PORT_STATE_READY	0x1
 751	u8 lport;
 752#define ICE_LPORT_MASK			0xff
 753	struct ice_fc_info fc;
 754	struct ice_mac_info mac;
 755	struct ice_phy_info phy;
 756	struct mutex sched_lock;	/* protect access to TXSched tree */
 757	struct ice_sched_node *
 758		sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
 759	/* List contain profile ID(s) and other params per layer */
 760	struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
 761	struct ice_qos_cfg qos_cfg;
 762	struct xarray sched_node_ids;
 763	u8 is_vf:1;
 764	u8 is_custom_tx_enabled:1;
 765};
 766
 767struct ice_switch_info {
 768	struct list_head vsi_list_map_head;
 769	struct ice_sw_recipe *recp_list;
 770	u16 prof_res_bm_init;
 771	u16 max_used_prof_index;
 772	u16 rule_cnt;
 773	u8 recp_cnt;
 774
 775	DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
 776};
 777
 778/* Enum defining the different states of the mailbox snapshot in the
 779 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
 780 * states:
 781 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
 782 * within the mailbox buffer.
 783 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
 784 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
 785 * mailbox and mark any VFs sending more messages than the threshold limit set.
 786 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
 787 */
 788enum ice_mbx_snapshot_state {
 789	ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
 790	ICE_MAL_VF_DETECT_STATE_TRAVERSE,
 791	ICE_MAL_VF_DETECT_STATE_DETECT,
 792	ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
 793};
 794
 795/* Structure to hold information of the static snapshot and the mailbox
 796 * buffer data used to generate and track the snapshot.
 797 * 1. state: the state of the mailbox snapshot in the malicious VF
 798 * detection state handler ice_mbx_vf_state_handler()
 799 * 2. head: head of the mailbox snapshot in a circular mailbox buffer
 800 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
 801 * 4. num_iterations: number of messages traversed in circular mailbox buffer
 802 * 5. num_msg_proc: number of messages processed in mailbox
 803 * 6. num_pending_arq: number of pending asynchronous messages
 804 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
 805 * serviced work item or interrupt.
 806 */
 807struct ice_mbx_snap_buffer_data {
 808	enum ice_mbx_snapshot_state state;
 809	u32 head;
 810	u32 tail;
 811	u32 num_iterations;
 812	u16 num_msg_proc;
 813	u16 num_pending_arq;
 814	u16 max_num_msgs_mbx;
 815};
 816
 817/* Structure used to track a single VF's messages on the mailbox:
 818 * 1. list_entry: linked list entry node
 819 * 2. msg_count: the number of asynchronous messages sent by this VF
 820 * 3. malicious: whether this VF has been detected as malicious before
 821 */
 822struct ice_mbx_vf_info {
 823	struct list_head list_entry;
 824	u32 msg_count;
 825	u8 malicious : 1;
 826};
 827
 828/* Structure to hold data relevant to the captured static snapshot
 829 * of the PF-VF mailbox.
 830 */
 831struct ice_mbx_snapshot {
 832	struct ice_mbx_snap_buffer_data mbx_buf;
 833	struct list_head mbx_vf;
 834};
 835
 836/* Structure to hold data to be used for capturing or updating a
 837 * static snapshot.
 838 * 1. num_msg_proc: number of messages processed in mailbox
 839 * 2. num_pending_arq: number of pending asynchronous messages
 840 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
 841 * serviced work item or interrupt.
 842 * 4. async_watermark_val: An upper threshold set by caller to determine
 843 * if the pending arq count is large enough to assume that there is
 844 * the possibility of a mailicious VF.
 845 */
 846struct ice_mbx_data {
 847	u16 num_msg_proc;
 848	u16 num_pending_arq;
 849	u16 max_num_msgs_mbx;
 850	u16 async_watermark_val;
 851};
 852
 853#define ICE_PORTS_PER_QUAD	4
 854#define ICE_GET_QUAD_NUM(port) ((port) / ICE_PORTS_PER_QUAD)
 855
 856#define ATQBAL_FLAGS_INTR_IN_PROGRESS	BIT(0)
 857
 858struct ice_e810_params {
 859	/* The wait queue lock also protects the low latency interface */
 860	wait_queue_head_t atqbal_wq;
 861	unsigned int atqbal_flags;
 862};
 863
 864struct ice_eth56g_params {
 865	u8 num_phys;
 866	bool onestep_ena;
 867	bool sfd_ena;
 868	u32 peer_delay;
 869};
 870
 871union ice_phy_params {
 872	struct ice_e810_params e810;
 873	struct ice_eth56g_params eth56g;
 874};
 875
 876/* Global Link Topology */
 877enum ice_global_link_topo {
 878	ICE_LINK_TOPO_UP_TO_2_LINKS,
 879	ICE_LINK_TOPO_UP_TO_4_LINKS,
 880	ICE_LINK_TOPO_UP_TO_8_LINKS,
 881	ICE_LINK_TOPO_RESERVED,
 882};
 883
 884struct ice_ptp_hw {
 885	union ice_phy_params phy;
 886	u8 num_lports;
 887	u8 ports_per_phy;
 888};
 889
 890/* Port hardware description */
 891struct ice_hw {
 892	u8 __iomem *hw_addr;
 893	void *back;
 894	struct ice_aqc_layer_props *layer_info;
 895	struct ice_port_info *port_info;
 896	/* PSM clock frequency for calculating RL profile params */
 897	u32 psm_clk_freq;
 898	u64 debug_mask;		/* bitmap for debug mask */
 899	enum ice_mac_type mac_type;
 900
 901	u16 fd_ctr_base;	/* FD counter base index */
 902
 903	/* pci info */
 904	u16 device_id;
 905	u16 vendor_id;
 906	u16 subsystem_device_id;
 907	u16 subsystem_vendor_id;
 908	u8 revision_id;
 909
 910	u8 pf_id;		/* device profile info */
 911	u8 logical_pf_id;
 912
 913	u16 max_burst_size;	/* driver sets this value */
 914
 915	u8 recp_reuse:1;	/* indicates whether FW supports recipe reuse */
 916
 917	/* Tx Scheduler values */
 918	u8 num_tx_sched_layers;
 919	u8 num_tx_sched_phys_layers;
 920	u8 flattened_layers;
 921	u8 max_cgds;
 922	u8 sw_entry_point_layer;
 923	u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
 924	struct list_head agg_list;	/* lists all aggregator */
 925
 926	struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
 927	u8 evb_veb;		/* true for VEB, false for VEPA */
 928	u8 reset_ongoing;	/* true if HW is in reset, false otherwise */
 929	struct ice_bus_info bus;
 930	struct ice_flash_info flash;
 931	struct ice_hw_dev_caps dev_caps;	/* device capabilities */
 932	struct ice_hw_func_caps func_caps;	/* function capabilities */
 933
 934	struct ice_switch_info *switch_info;	/* switch filter lists */
 935
 936	/* Control Queue info */
 937	struct ice_ctl_q_info adminq;
 938	struct ice_ctl_q_info sbq;
 939	struct ice_ctl_q_info mailboxq;
 940
 941	u8 api_branch;		/* API branch version */
 942	u8 api_maj_ver;		/* API major version */
 943	u8 api_min_ver;		/* API minor version */
 944	u8 api_patch;		/* API patch version */
 945	u8 fw_branch;		/* firmware branch version */
 946	u8 fw_maj_ver;		/* firmware major version */
 947	u8 fw_min_ver;		/* firmware minor version */
 948	u8 fw_patch;		/* firmware patch version */
 949	u32 fw_build;		/* firmware build number */
 950
 951	struct libie_fwlog fwlog;
 952
 953/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
 954 * register. Used for determining the ITR/INTRL granularity during
 955 * initialization.
 956 */
 957#define ICE_MAX_AGG_BW_200G	0x0
 958#define ICE_MAX_AGG_BW_100G	0X1
 959#define ICE_MAX_AGG_BW_50G	0x2
 960#define ICE_MAX_AGG_BW_25G	0x3
 961	/* ITR granularity for different speeds */
 962#define ICE_ITR_GRAN_ABOVE_25	2
 963#define ICE_ITR_GRAN_MAX_25	4
 964	/* ITR granularity in 1 us */
 965	u8 itr_gran;
 966	/* INTRL granularity for different speeds */
 967#define ICE_INTRL_GRAN_ABOVE_25	4
 968#define ICE_INTRL_GRAN_MAX_25	8
 969	/* INTRL granularity in 1 us */
 970	u8 intrl_gran;
 971
 972	struct ice_ptp_hw ptp;
 973	s8 lane_num;
 974
 975	/* Active package version (currently active) */
 976	struct ice_pkg_ver active_pkg_ver;
 977	u32 pkg_seg_id;
 978	u32 pkg_sign_type;
 979	u32 active_track_id;
 980	u8 pkg_has_signing_seg:1;
 981	u8 active_pkg_name[ICE_PKG_NAME_SIZE];
 982	u8 active_pkg_in_nvm;
 983
 984	/* Driver's package ver - (from the Ice Metadata section) */
 985	struct ice_pkg_ver pkg_ver;
 986	u8 pkg_name[ICE_PKG_NAME_SIZE];
 987
 988	/* Driver's Ice segment format version and ID (from the Ice seg) */
 989	struct ice_pkg_ver ice_seg_fmt_ver;
 990	u8 ice_seg_id[ICE_SEG_ID_SIZE];
 991
 992	/* Pointer to the ice segment */
 993	struct ice_seg *seg;
 994
 995	/* Pointer to allocated copy of pkg memory */
 996	u8 *pkg_copy;
 997	u32 pkg_size;
 998
 999	/* tunneling info */
1000	struct mutex tnl_lock;
1001	struct ice_tunnel_table tnl;
1002
1003	struct udp_tunnel_nic_shared udp_tunnel_shared;
1004	struct udp_tunnel_nic_info udp_tunnel_nic;
1005
1006	/* dvm boost update information */
1007	struct ice_dvm_table dvm_upd;
1008
1009	/* HW block tables */
1010	struct ice_blk_info blk[ICE_BLK_COUNT];
1011	struct mutex fl_profs_locks[ICE_BLK_COUNT];	/* lock fltr profiles */
1012	struct list_head fl_profs[ICE_BLK_COUNT];
1013
1014	/* Flow Director filter info */
1015	int fdir_active_fltr;
1016
1017	struct mutex fdir_fltr_lock;	/* protect Flow Director */
1018	struct list_head fdir_list_head;
1019
1020	/* Book-keeping of side-band filter count per flow-type.
1021	 * This is used to detect and handle input set changes for
1022	 * respective flow-type.
1023	 */
1024	u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1025
1026	struct ice_fd_hw_prof **fdir_prof;
1027	DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
1028	struct mutex rss_locks;	/* protect RSS configuration */
1029	struct list_head rss_list_head;
1030	struct ice_mbx_snapshot mbx_snapshot;
1031	DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX);
1032	u8 dvm_ena;
1033	u16 io_expander_handle;
1034	u8 cgu_part_number;
1035};
1036
1037/* Statistics collected by each port, VSI, VEB, and S-channel */
1038struct ice_eth_stats {
1039	u64 rx_bytes;			/* gorc */
1040	u64 rx_unicast;			/* uprc */
1041	u64 rx_multicast;		/* mprc */
1042	u64 rx_broadcast;		/* bprc */
1043	u64 rx_discards;		/* rdpc */
1044	u64 rx_unknown_protocol;	/* rupp */
1045	u64 tx_bytes;			/* gotc */
1046	u64 tx_unicast;			/* uptc */
1047	u64 tx_multicast;		/* mptc */
1048	u64 tx_broadcast;		/* bptc */
1049	u64 tx_discards;		/* tdpc */
1050	u64 tx_errors;			/* tepc */
1051};
1052
1053#define ICE_MAX_UP	8
1054
1055/* Statistics collected by the MAC */
1056struct ice_hw_port_stats {
1057	/* eth stats collected by the port */
1058	struct ice_eth_stats eth;
1059	/* additional port specific stats */
1060	u64 tx_dropped_link_down;	/* tdold */
1061	u64 crc_errors;			/* crcerrs */
1062	u64 illegal_bytes;		/* illerrc */
1063	u64 error_bytes;		/* errbc */
1064	u64 mac_local_faults;		/* mlfc */
1065	u64 mac_remote_faults;		/* mrfc */
1066	u64 rx_len_errors;		/* rlec */
1067	u64 link_xon_rx;		/* lxonrxc */
1068	u64 link_xoff_rx;		/* lxoffrxc */
1069	u64 link_xon_tx;		/* lxontxc */
1070	u64 link_xoff_tx;		/* lxofftxc */
1071	u64 priority_xon_rx[8];		/* pxonrxc[8] */
1072	u64 priority_xoff_rx[8];	/* pxoffrxc[8] */
1073	u64 priority_xon_tx[8];		/* pxontxc[8] */
1074	u64 priority_xoff_tx[8];	/* pxofftxc[8] */
1075	u64 priority_xon_2_xoff[8];	/* pxon2offc[8] */
1076	u64 rx_size_64;			/* prc64 */
1077	u64 rx_size_127;		/* prc127 */
1078	u64 rx_size_255;		/* prc255 */
1079	u64 rx_size_511;		/* prc511 */
1080	u64 rx_size_1023;		/* prc1023 */
1081	u64 rx_size_1522;		/* prc1522 */
1082	u64 rx_size_big;		/* prc9522 */
1083	u64 rx_undersize;		/* ruc */
1084	u64 rx_fragments;		/* rfc */
1085	u64 rx_oversize;		/* roc */
1086	u64 rx_jabber;			/* rjc */
1087	u64 tx_size_64;			/* ptc64 */
1088	u64 tx_size_127;		/* ptc127 */
1089	u64 tx_size_255;		/* ptc255 */
1090	u64 tx_size_511;		/* ptc511 */
1091	u64 tx_size_1023;		/* ptc1023 */
1092	u64 tx_size_1522;		/* ptc1522 */
1093	u64 tx_size_big;		/* ptc9522 */
1094	/* flow director stats */
1095	u32 fd_sb_status;
1096	u64 fd_sb_match;
1097};
1098
1099enum ice_sw_fwd_act_type {
1100	ICE_FWD_TO_VSI = 0,
1101	ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1102	ICE_FWD_TO_Q,
1103	ICE_FWD_TO_QGRP,
1104	ICE_DROP_PACKET,
1105	ICE_MIRROR_PACKET,
1106	ICE_NOP,
1107	ICE_INVAL_ACT
1108};
1109
1110struct ice_aq_get_set_rss_lut_params {
1111	u8 *lut;		/* input RSS LUT for set and output RSS LUT for get */
1112	enum ice_lut_size lut_size; /* size of the LUT buffer */
1113	enum ice_lut_type lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1114	u16 vsi_handle;		/* software VSI handle */
1115	u8 global_lut_id;	/* only valid when lut_type is global */
1116};
1117
1118/* Checksum and Shadow RAM pointers */
1119#define ICE_SR_NVM_CTRL_WORD		0x00
1120#define ICE_SR_BOOT_CFG_PTR		0x132
1121#define ICE_SR_NVM_WOL_CFG		0x19
1122#define ICE_NVM_OROM_VER_OFF		0x02
1123#define ICE_SR_PBA_BLOCK_PTR		0x16
1124#define ICE_SR_NVM_DEV_STARTER_VER	0x18
1125#define ICE_SR_NVM_EETRACK_LO		0x2D
1126#define ICE_SR_NVM_EETRACK_HI		0x2E
1127#define ICE_NVM_VER_LO_SHIFT		0
1128#define ICE_NVM_VER_LO_MASK		(0xff << ICE_NVM_VER_LO_SHIFT)
1129#define ICE_NVM_VER_HI_SHIFT		12
1130#define ICE_NVM_VER_HI_MASK		(0xf << ICE_NVM_VER_HI_SHIFT)
1131#define ICE_OROM_VER_PATCH_SHIFT	0
1132#define ICE_OROM_VER_PATCH_MASK		(0xff << ICE_OROM_VER_PATCH_SHIFT)
1133#define ICE_OROM_VER_BUILD_SHIFT	8
1134#define ICE_OROM_VER_BUILD_MASK		(0xffff << ICE_OROM_VER_BUILD_SHIFT)
1135#define ICE_OROM_VER_SHIFT		24
1136#define ICE_OROM_VER_MASK		(0xffU << ICE_OROM_VER_SHIFT)
1137#define ICE_SR_PFA_PTR			0x40
1138#define ICE_SR_1ST_NVM_BANK_PTR		0x42
1139#define ICE_SR_NVM_BANK_SIZE		0x43
1140#define ICE_SR_1ST_OROM_BANK_PTR	0x44
1141#define ICE_SR_OROM_BANK_SIZE		0x45
1142#define ICE_SR_NETLIST_BANK_PTR		0x46
1143#define ICE_SR_NETLIST_BANK_SIZE	0x47
1144#define ICE_SR_SECTOR_SIZE_IN_WORDS	0x800
1145
1146/* CSS Header words */
1147#define ICE_NVM_CSS_HDR_LEN_L			0x02
1148#define ICE_NVM_CSS_HDR_LEN_H			0x03
1149#define ICE_NVM_CSS_SREV_L			0x14
1150#define ICE_NVM_CSS_SREV_H			0x15
1151
1152/* Length of Authentication header section in words */
1153#define ICE_NVM_AUTH_HEADER_LEN			0x08
1154
1155/* The Link Topology Netlist section is stored as a series of words. It is
1156 * stored in the NVM as a TLV, with the first two words containing the type
1157 * and length.
1158 */
1159#define ICE_NETLIST_LINK_TOPO_MOD_ID		0x011B
1160#define ICE_NETLIST_TYPE_OFFSET			0x0000
1161#define ICE_NETLIST_LEN_OFFSET			0x0001
1162
1163/* The Link Topology section follows the TLV header. When reading the netlist
1164 * using ice_read_netlist_module, we need to account for the 2-word TLV
1165 * header.
1166 */
1167#define ICE_NETLIST_LINK_TOPO_OFFSET(n)		((n) + 2)
1168
1169#define ICE_LINK_TOPO_MODULE_LEN		ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1170#define ICE_LINK_TOPO_NODE_COUNT		ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1171
1172#define ICE_LINK_TOPO_NODE_COUNT_M		ICE_M(0x3FF, 0)
1173
1174/* The Netlist ID Block is located after all of the Link Topology nodes. */
1175#define ICE_NETLIST_ID_BLK_SIZE			0x30
1176#define ICE_NETLIST_ID_BLK_OFFSET(n)		ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1177
1178/* netlist ID block field offsets (word offsets) */
1179#define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW	0x02
1180#define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH	0x03
1181#define ICE_NETLIST_ID_BLK_MINOR_VER_LOW	0x04
1182#define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH	0x05
1183#define ICE_NETLIST_ID_BLK_TYPE_LOW		0x06
1184#define ICE_NETLIST_ID_BLK_TYPE_HIGH		0x07
1185#define ICE_NETLIST_ID_BLK_REV_LOW		0x08
1186#define ICE_NETLIST_ID_BLK_REV_HIGH		0x09
1187#define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n)	(0x0A + (n))
1188#define ICE_NETLIST_ID_BLK_CUST_VER		0x2F
1189
1190/* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
1191#define ICE_SR_CTRL_WORD_1_S		0x06
1192#define ICE_SR_CTRL_WORD_1_M		(0x03 << ICE_SR_CTRL_WORD_1_S)
1193#define ICE_SR_CTRL_WORD_VALID		0x1
1194#define ICE_SR_CTRL_WORD_OROM_BANK	BIT(3)
1195#define ICE_SR_CTRL_WORD_NETLIST_BANK	BIT(4)
1196#define ICE_SR_CTRL_WORD_NVM_BANK	BIT(5)
1197
1198#define ICE_SR_NVM_PTR_4KB_UNITS	BIT(15)
1199
1200/* Link override related */
1201#define ICE_SR_PFA_LINK_OVERRIDE_WORDS		10
1202#define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS	4
1203#define ICE_SR_PFA_LINK_OVERRIDE_OFFSET		2
1204#define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET	1
1205#define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET	2
1206#define ICE_FW_API_LINK_OVERRIDE_MAJ		1
1207#define ICE_FW_API_LINK_OVERRIDE_MIN		5
1208#define ICE_FW_API_LINK_OVERRIDE_PATCH		2
1209
1210#define ICE_SR_WORDS_IN_1KB		512
1211
1212/* AQ API version for LLDP_FILTER_CONTROL */
1213#define ICE_FW_API_LLDP_FLTR_MAJ	1
1214#define ICE_FW_API_LLDP_FLTR_MIN	7
1215#define ICE_FW_API_LLDP_FLTR_PATCH	1
1216
1217/* AQ API version for report default configuration */
1218#define ICE_FW_API_REPORT_DFLT_CFG_MAJ		1
1219#define ICE_FW_API_REPORT_DFLT_CFG_MIN		7
1220#define ICE_FW_API_REPORT_DFLT_CFG_PATCH	3
1221
1222/* AQ API version for Health Status support */
1223#define ICE_FW_API_HEALTH_REPORT_MAJ		1
1224#define ICE_FW_API_HEALTH_REPORT_MIN		7
1225#define ICE_FW_API_HEALTH_REPORT_PATCH		6
1226
1227#endif /* _ICE_TYPE_H_ */