ice_ptp_hw.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (C) 2021, Intel Corporation. */
  3
  4#ifndef _ICE_PTP_HW_H_
  5#define _ICE_PTP_HW_H_
  6#include <linux/dpll.h>
  7
  8enum ice_ptp_tmr_cmd {
  9	ICE_PTP_INIT_TIME,
 10	ICE_PTP_INIT_INCVAL,
 11	ICE_PTP_ADJ_TIME,
 12	ICE_PTP_ADJ_TIME_AT_TIME,
 13	ICE_PTP_READ_TIME,
 14	ICE_PTP_NOP,
 15};
 16
 17enum ice_ptp_serdes {
 18	ICE_PTP_SERDES_1G,
 19	ICE_PTP_SERDES_10G,
 20	ICE_PTP_SERDES_25G,
 21	ICE_PTP_SERDES_40G,
 22	ICE_PTP_SERDES_50G,
 23	ICE_PTP_SERDES_100G
 24};
 25
 26enum ice_ptp_link_spd {
 27	ICE_PTP_LNK_SPD_1G,
 28	ICE_PTP_LNK_SPD_10G,
 29	ICE_PTP_LNK_SPD_25G,
 30	ICE_PTP_LNK_SPD_25G_RS,
 31	ICE_PTP_LNK_SPD_40G,
 32	ICE_PTP_LNK_SPD_50G,
 33	ICE_PTP_LNK_SPD_50G_RS,
 34	ICE_PTP_LNK_SPD_100G_RS,
 35	NUM_ICE_PTP_LNK_SPD /* Must be last */
 36};
 37
 38enum ice_ptp_fec_mode {
 39	ICE_PTP_FEC_MODE_NONE,
 40	ICE_PTP_FEC_MODE_CLAUSE74,
 41	ICE_PTP_FEC_MODE_RS_FEC
 42};
 43
 44enum eth56g_res_type {
 45	ETH56G_PHY_REG_PTP,
 46	ETH56G_PHY_MEM_PTP,
 47	ETH56G_PHY_REG_XPCS,
 48	ETH56G_PHY_REG_MAC,
 49	ETH56G_PHY_REG_GPCS,
 50	NUM_ETH56G_PHY_RES
 51};
 52
 53enum ice_eth56g_link_spd {
 54	ICE_ETH56G_LNK_SPD_1G,
 55	ICE_ETH56G_LNK_SPD_2_5G,
 56	ICE_ETH56G_LNK_SPD_10G,
 57	ICE_ETH56G_LNK_SPD_25G,
 58	ICE_ETH56G_LNK_SPD_40G,
 59	ICE_ETH56G_LNK_SPD_50G,
 60	ICE_ETH56G_LNK_SPD_50G2,
 61	ICE_ETH56G_LNK_SPD_100G,
 62	ICE_ETH56G_LNK_SPD_100G2,
 63	NUM_ICE_ETH56G_LNK_SPD /* Must be last */
 64};
 65
 66/**
 67 * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
 68 * @base_addr: base address for each PHY block
 69 * @step: step between PHY lanes
 70 *
 71 * Characteristic information for the various PHY register parameters in the
 72 * ETH56G devices
 73 */
 74struct ice_phy_reg_info_eth56g {
 75	u32 base_addr;
 76	u32 step;
 77};
 78
 79/**
 80 * struct ice_time_ref_info_e82x
 81 * @pll_freq: Frequency of PLL that drives timer ticks in Hz
 82 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
 83 *
 84 * Characteristic information for the various TIME_REF sources possible in the
 85 * E822 devices
 86 */
 87struct ice_time_ref_info_e82x {
 88	u64 pll_freq;
 89	u64 nominal_incval;
 90};
 91
 92/**
 93 * struct ice_vernier_info_e82x
 94 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
 95 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
 96 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
 97 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
 98 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
 99 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
100 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
101 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
102 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
103 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
104 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
105 *
106 * Table of constants used during as part of the Vernier calibration of the Tx
107 * and Rx timestamps. This includes frequency values used to compute TUs per
108 * PAR/PCS clock cycle, and static delay values measured during hardware
109 * design.
110 *
111 * Note that some values are not used for all link speeds, and the
112 * P_REG_DESK_PAR* registers may represent different clock markers at
113 * different link speeds, either the deskew marker for multi-lane link speeds
114 * or the Reed Solomon gearbox marker for RS-FEC.
115 */
116struct ice_vernier_info_e82x {
117	u32 tx_par_clk;
118	u32 rx_par_clk;
119	u32 tx_pcs_clk;
120	u32 rx_pcs_clk;
121	u32 tx_desk_rsgb_par;
122	u32 rx_desk_rsgb_par;
123	u32 tx_desk_rsgb_pcs;
124	u32 rx_desk_rsgb_pcs;
125	u32 tx_fixed_delay;
126	u32 pmd_adj_divisor;
127	u32 rx_fixed_delay;
128};
129
130#define ICE_ETH56G_MAC_CFG_RX_OFFSET_INT	GENMASK(19, 9)
131#define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC	GENMASK(8, 0)
132#define ICE_ETH56G_MAC_CFG_FRAC_W		9
133/**
134 * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
135 * @tx_mode: Tx timestamp compensation mode
136 * @tx_mk_dly: Tx timestamp marker start strobe delay
137 * @tx_cw_dly: Tx timestamp codeword start strobe delay
138 * @rx_mode: Rx timestamp compensation mode
139 * @rx_mk_dly: Rx timestamp marker start strobe delay
140 * @rx_cw_dly: Rx timestamp codeword start strobe delay
141 * @blks_per_clk: number of blocks transferred per clock cycle
142 * @blktime: block time, fixed point
143 * @mktime: marker time, fixed point
144 * @tx_offset: total Tx offset, fixed point
145 * @rx_offset: total Rx offset, contains value for bitslip/deskew, fixed point
146 *
147 * All fixed point registers except Rx offset are 23 bit unsigned ints with
148 * a 9 bit fractional.
149 * Rx offset is 11 bit unsigned int with a 9 bit fractional.
150 */
151struct ice_eth56g_mac_reg_cfg {
152	struct {
153		u8 def;
154		u8 rs;
155	} tx_mode;
156	u8 tx_mk_dly;
157	struct {
158		u8 def;
159		u8 onestep;
160	} tx_cw_dly;
161	struct {
162		u8 def;
163		u8 rs;
164	} rx_mode;
165	struct {
166		u8 def;
167		u8 rs;
168	} rx_mk_dly;
169	struct {
170		u8 def;
171		u8 rs;
172	} rx_cw_dly;
173	u8 blks_per_clk;
174	u16 blktime;
175	u16 mktime;
176	struct {
177		u32 serdes;
178		u32 no_fec;
179		u32 fc;
180		u32 rs;
181		u32 sfd;
182		u32 onestep;
183	} tx_offset;
184	struct {
185		u32 serdes;
186		u32 no_fec;
187		u32 fc;
188		u32 rs;
189		u32 sfd;
190		u32 bs_ds;
191	} rx_offset;
192};
193
194extern
195const struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD];
196
197#define E810C_QSFP_C827_0_HANDLE	2
198#define E810C_QSFP_C827_1_HANDLE	3
199enum ice_e810_c827_idx {
200	C827_0,
201	C827_1
202};
203
204enum ice_phy_rclk_pins {
205	ICE_RCLKA_PIN = 0,		/* SCL pin */
206	ICE_RCLKB_PIN,			/* SDA pin */
207};
208
209#define ICE_E810_RCLK_PINS_NUM		(ICE_RCLKB_PIN + 1)
210#define ICE_E82X_RCLK_PINS_NUM		(ICE_RCLKA_PIN + 1)
211#define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \
212					  (_pin) + ZL_REF1P)
213
214enum ice_zl_cgu_in_pins {
215	ZL_REF0P = 0,
216	ZL_REF0N,
217	ZL_REF1P,
218	ZL_REF1N,
219	ZL_REF2P,
220	ZL_REF2N,
221	ZL_REF3P,
222	ZL_REF3N,
223	ZL_REF4P,
224	ZL_REF4N,
225	NUM_ZL_CGU_INPUT_PINS
226};
227
228enum ice_zl_cgu_out_pins {
229	ZL_OUT0 = 0,
230	ZL_OUT1,
231	ZL_OUT2,
232	ZL_OUT3,
233	ZL_OUT4,
234	ZL_OUT5,
235	ZL_OUT6,
236	NUM_ZL_CGU_OUTPUT_PINS
237};
238
239enum ice_si_cgu_in_pins {
240	SI_REF0P = 0,
241	SI_REF0N,
242	SI_REF1P,
243	SI_REF1N,
244	SI_REF2P,
245	SI_REF2N,
246	SI_REF3,
247	SI_REF4,
248	NUM_SI_CGU_INPUT_PINS
249};
250
251enum ice_si_cgu_out_pins {
252	SI_OUT0 = 0,
253	SI_OUT1,
254	SI_OUT2,
255	SI_OUT3,
256	SI_OUT4,
257	NUM_SI_CGU_OUTPUT_PINS
258};
259
260struct ice_cgu_pin_desc {
261	char *name;
262	u8 index;
263	enum dpll_pin_type type;
264	u32 freq_supp_num;
265	struct dpll_pin_frequency *freq_supp;
266};
267
268#define E810C_QSFP_C827_0_HANDLE 2
269#define E810C_QSFP_C827_1_HANDLE 3
270
271/* Table of constants related to possible ETH56G PHY resources */
272extern const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES];
273
274/* Table of constants related to possible TIME_REF sources */
275extern const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TSPLL_FREQ];
276
277/* Table of constants for Vernier calibration on E822 */
278extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
279
280/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
281 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
282 */
283#define ICE_E810_PLL_FREQ		812500000
284#define ICE_PTP_NOMINAL_INCVAL_E810	0x13b13b13bULL
285#define ICE_E810_E830_SYNC_DELAY	0
286
287/* Device agnostic functions */
288u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
289bool ice_ptp_lock(struct ice_hw *hw);
290void ice_ptp_unlock(struct ice_hw *hw);
291void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
292int ice_ptp_init_time(struct ice_hw *hw, u64 time);
293int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
294int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
295int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
296int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw);
297int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
298int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
299void ice_ptp_reset_ts_memory(struct ice_hw *hw);
300int ice_ptp_init_phc(struct ice_hw *hw);
301void ice_ptp_init_hw(struct ice_hw *hw);
302int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
303int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
304			 enum ice_ptp_tmr_cmd configured_cmd);
305
306/* E822 family functions */
307int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
308int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
309void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);
310
311/**
312 * ice_e82x_time_ref - Get the current TIME_REF from capabilities
313 * @hw: pointer to the HW structure
314 *
315 * Returns the current TIME_REF from the capabilities structure.
316 */
317
318static inline enum ice_tspll_freq ice_e82x_time_ref(const struct ice_hw *hw)
319{
320	return hw->func_caps.ts_func_info.time_ref;
321}
322
323/**
324 * ice_set_e82x_time_ref - Set new TIME_REF
325 * @hw: pointer to the HW structure
326 * @time_ref: new TIME_REF to set
327 *
328 * Update the TIME_REF in the capabilities structure in response to some
329 * change, such as an update to the CGU registers.
330 */
331static inline void
332ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_tspll_freq time_ref)
333{
334	hw->func_caps.ts_func_info.time_ref = time_ref;
335}
336
337static inline u64 ice_e82x_pll_freq(enum ice_tspll_freq time_ref)
338{
339	return e82x_time_ref[time_ref].pll_freq;
340}
341
342static inline u64 ice_e82x_nominal_incval(enum ice_tspll_freq time_ref)
343{
344	return e82x_time_ref[time_ref].nominal_incval;
345}
346
347/* E822 Vernier calibration functions */
348int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);
349int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
350int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);
351int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
352int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);
353
354/* E810 family functions */
355int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data);
356int ice_write_sma_ctrl(struct ice_hw *hw, u8 data);
357int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries);
358int ice_cgu_get_num_pins(struct ice_hw *hw, bool input);
359enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
360struct dpll_pin_frequency *
361ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
362const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);
363int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
364		      enum dpll_lock_status last_dpll_state, u8 *pin,
365		      u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
366		      enum dpll_lock_status *dpll_state);
367int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
368int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
369				      unsigned long *caps);
370
371/* ETH56G family functions */
372int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);
373int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);
374int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);
375int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);
376int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);
377
378#define ICE_ETH56G_NOMINAL_INCVAL	0x140000000ULL
379#define ICE_ETH56G_NOMINAL_PCS_REF_TUS	0x100000000ULL
380#define ICE_ETH56G_NOMINAL_PCS_REF_INC	0x300000000ULL
381#define ICE_ETH56G_NOMINAL_THRESH4	0x7777
382#define ICE_ETH56G_NOMINAL_TX_THRESH	0x6
383
384/**
385 * ice_get_base_incval - Get base clock increment value
386 * @hw: pointer to the HW struct
387 *
388 * Return: base clock increment value for supported PHYs, 0 otherwise
389 */
390static inline u64 ice_get_base_incval(struct ice_hw *hw)
391{
392	switch (hw->mac_type) {
393	case ICE_MAC_E810:
394	case ICE_MAC_E830:
395		return ICE_PTP_NOMINAL_INCVAL_E810;
396	case ICE_MAC_GENERIC:
397		return ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
398	case ICE_MAC_GENERIC_3K_E825:
399		return ICE_ETH56G_NOMINAL_INCVAL;
400	default:
401		return 0;
402	}
403}
404
405#define PFTSYN_SEM_BYTES	4
406
407#define ICE_PTP_CLOCK_INDEX_0	0x00
408#define ICE_PTP_CLOCK_INDEX_1	0x01
409
410/* PHY timer commands */
411#define SEL_CPK_SRC	8
412#define SEL_PHY_SRC	3
413
414/* Time Sync command Definitions */
415#define GLTSYN_CMD_INIT_TIME		BIT(0)
416#define GLTSYN_CMD_INIT_INCVAL		BIT(1)
417#define GLTSYN_CMD_INIT_TIME_INCVAL	(BIT(0) | BIT(1))
418#define GLTSYN_CMD_ADJ_TIME		BIT(2)
419#define GLTSYN_CMD_ADJ_INIT_TIME	(BIT(2) | BIT(3))
420#define GLTSYN_CMD_READ_TIME		BIT(7)
421
422/* PHY port Time Sync command definitions */
423#define PHY_CMD_INIT_TIME		BIT(0)
424#define PHY_CMD_INIT_INCVAL		BIT(1)
425#define PHY_CMD_ADJ_TIME		(BIT(0) | BIT(1))
426#define PHY_CMD_ADJ_TIME_AT_TIME	(BIT(0) | BIT(2))
427#define PHY_CMD_READ_TIME		(BIT(0) | BIT(1) | BIT(2))
428
429#define TS_CMD_MASK_E810		0xFF
430#define TS_CMD_MASK			0xF
431#define SYNC_EXEC_CMD			0x3
432#define TS_CMD_RX_TYPE			ICE_M(0x18, 0x4)
433
434/* Macros to derive port low and high addresses on both quads */
435#define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
436#define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
437#define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
438#define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
439
440/* PHY QUAD register base addresses */
441#define Q_0_BASE			0x94000
442#define Q_1_BASE			0x114000
443
444/* Timestamp memory reset registers */
445#define Q_REG_TS_CTRL			0x618
446#define Q_REG_TS_CTRL_S			0
447#define Q_REG_TS_CTRL_M			BIT(0)
448
449/* Timestamp availability status registers */
450#define Q_REG_TX_MEMORY_STATUS_L	0xCF0
451#define Q_REG_TX_MEMORY_STATUS_U	0xCF4
452
453/* Tx FIFO status registers */
454#define Q_REG_FIFO23_STATUS		0xCF8
455#define Q_REG_FIFO01_STATUS		0xCFC
456#define Q_REG_FIFO02_S			0
457#define Q_REG_FIFO02_M			ICE_M(0x3FF, 0)
458#define Q_REG_FIFO13_S			10
459#define Q_REG_FIFO13_M			ICE_M(0x3FF, 10)
460
461/* Interrupt control Config registers */
462#define Q_REG_TX_MEM_GBL_CFG		0xC08
463#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S	0
464#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M	BIT(0)
465#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M	ICE_M(0xFF, 1)
466#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
467#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M	BIT(15)
468
469/* Tx Timestamp data registers */
470#define Q_REG_TX_MEMORY_BANK_START	0xA00
471
472/* PHY port register base addresses */
473#define P_0_BASE			0x80000
474#define P_4_BASE			0x106000
475
476/* Timestamp init registers */
477#define P_REG_RX_TIMER_INC_PRE_L	0x46C
478#define P_REG_RX_TIMER_INC_PRE_U	0x470
479#define P_REG_TX_TIMER_INC_PRE_L	0x44C
480#define P_REG_TX_TIMER_INC_PRE_U	0x450
481
482/* Timestamp match and adjust target registers */
483#define P_REG_RX_TIMER_CNT_ADJ_L	0x474
484#define P_REG_RX_TIMER_CNT_ADJ_U	0x478
485#define P_REG_TX_TIMER_CNT_ADJ_L	0x454
486#define P_REG_TX_TIMER_CNT_ADJ_U	0x458
487
488/* Timestamp capture registers */
489#define P_REG_RX_CAPTURE_L		0x4D8
490#define P_REG_RX_CAPTURE_U		0x4DC
491#define P_REG_TX_CAPTURE_L		0x4B4
492#define P_REG_TX_CAPTURE_U		0x4B8
493
494/* Timestamp PHY incval registers */
495#define P_REG_TIMETUS_L			0x410
496#define P_REG_TIMETUS_U			0x414
497
498#define P_REG_40B_LOW_M			GENMASK(7, 0)
499#define P_REG_40B_HIGH_S		8
500
501/* PHY window length registers */
502#define P_REG_WL			0x40C
503
504#define PTP_VERNIER_WL			0x111ed
505
506/* PHY start registers */
507#define P_REG_PS			0x408
508#define P_REG_PS_START_S		0
509#define P_REG_PS_START_M		BIT(0)
510#define P_REG_PS_BYPASS_MODE_S		1
511#define P_REG_PS_BYPASS_MODE_M		BIT(1)
512#define P_REG_PS_ENA_CLK_S		2
513#define P_REG_PS_ENA_CLK_M		BIT(2)
514#define P_REG_PS_LOAD_OFFSET_S		3
515#define P_REG_PS_LOAD_OFFSET_M		BIT(3)
516#define P_REG_PS_SFT_RESET_S		11
517#define P_REG_PS_SFT_RESET_M		BIT(11)
518
519/* PHY offset valid registers */
520#define P_REG_TX_OV_STATUS		0x4D4
521#define P_REG_TX_OV_STATUS_OV_S		0
522#define P_REG_TX_OV_STATUS_OV_M		BIT(0)
523#define P_REG_RX_OV_STATUS		0x4F8
524#define P_REG_RX_OV_STATUS_OV_S		0
525#define P_REG_RX_OV_STATUS_OV_M		BIT(0)
526
527/* PHY offset ready registers */
528#define P_REG_TX_OR			0x45C
529#define P_REG_RX_OR			0x47C
530
531/* PHY total offset registers */
532#define P_REG_TOTAL_RX_OFFSET_L		0x460
533#define P_REG_TOTAL_RX_OFFSET_U		0x464
534#define P_REG_TOTAL_TX_OFFSET_L		0x440
535#define P_REG_TOTAL_TX_OFFSET_U		0x444
536
537/* Timestamp PAR/PCS registers */
538#define P_REG_UIX66_10G_40G_L		0x480
539#define P_REG_UIX66_10G_40G_U		0x484
540#define P_REG_UIX66_25G_100G_L		0x488
541#define P_REG_UIX66_25G_100G_U		0x48C
542#define P_REG_DESK_PAR_RX_TUS_L		0x490
543#define P_REG_DESK_PAR_RX_TUS_U		0x494
544#define P_REG_DESK_PAR_TX_TUS_L		0x498
545#define P_REG_DESK_PAR_TX_TUS_U		0x49C
546#define P_REG_DESK_PCS_RX_TUS_L		0x4A0
547#define P_REG_DESK_PCS_RX_TUS_U		0x4A4
548#define P_REG_DESK_PCS_TX_TUS_L		0x4A8
549#define P_REG_DESK_PCS_TX_TUS_U		0x4AC
550#define P_REG_PAR_RX_TUS_L		0x420
551#define P_REG_PAR_RX_TUS_U		0x424
552#define P_REG_PAR_TX_TUS_L		0x428
553#define P_REG_PAR_TX_TUS_U		0x42C
554#define P_REG_PCS_RX_TUS_L		0x430
555#define P_REG_PCS_RX_TUS_U		0x434
556#define P_REG_PCS_TX_TUS_L		0x438
557#define P_REG_PCS_TX_TUS_U		0x43C
558#define P_REG_PAR_RX_TIME_L		0x4F0
559#define P_REG_PAR_RX_TIME_U		0x4F4
560#define P_REG_PAR_TX_TIME_L		0x4CC
561#define P_REG_PAR_TX_TIME_U		0x4D0
562#define P_REG_PAR_PCS_RX_OFFSET_L	0x4E8
563#define P_REG_PAR_PCS_RX_OFFSET_U	0x4EC
564#define P_REG_PAR_PCS_TX_OFFSET_L	0x4C4
565#define P_REG_PAR_PCS_TX_OFFSET_U	0x4C8
566#define P_REG_LINK_SPEED		0x4FC
567#define P_REG_LINK_SPEED_SERDES_S	0
568#define P_REG_LINK_SPEED_SERDES_M	ICE_M(0x7, 0)
569#define P_REG_LINK_SPEED_FEC_MODE_S	3
570#define P_REG_LINK_SPEED_FEC_MODE_M	ICE_M(0x3, 3)
571#define P_REG_LINK_SPEED_FEC_MODE(reg)			\
572	(((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >>	\
573	 P_REG_LINK_SPEED_FEC_MODE_S)
574
575/* PHY timestamp related registers */
576#define P_REG_PMD_ALIGNMENT		0x0FC
577#define P_REG_RX_80_TO_160_CNT		0x6FC
578#define P_REG_RX_80_TO_160_CNT_RXCYC_S	0
579#define P_REG_RX_80_TO_160_CNT_RXCYC_M	BIT(0)
580#define P_REG_RX_40_TO_160_CNT		0x8FC
581#define P_REG_RX_40_TO_160_CNT_RXCYC_S	0
582#define P_REG_RX_40_TO_160_CNT_RXCYC_M	ICE_M(0x3, 0)
583
584/* Rx FIFO status registers */
585#define P_REG_RX_OV_FS			0x4F8
586#define P_REG_RX_OV_FS_FIFO_STATUS_S	2
587#define P_REG_RX_OV_FS_FIFO_STATUS_M	ICE_M(0x3FF, 2)
588
589/* Timestamp command registers */
590#define P_REG_TX_TMR_CMD		0x448
591#define P_REG_RX_TMR_CMD		0x468
592
593/* E810 timesync enable register */
594#define ETH_GLTSYN_ENA(_i)		(0x03000348 + ((_i) * 4))
595
596/* E810 shadow init time registers */
597#define ETH_GLTSYN_SHTIME_0(i)		(0x03000368 + ((i) * 32))
598#define ETH_GLTSYN_SHTIME_L(i)		(0x0300036C + ((i) * 32))
599
600/* E810 shadow time adjust registers */
601#define ETH_GLTSYN_SHADJ_L(_i)		(0x03000378 + ((_i) * 32))
602#define ETH_GLTSYN_SHADJ_H(_i)		(0x0300037C + ((_i) * 32))
603
604/* E810 timer command register */
605#define E810_ETH_GLTSYN_CMD		0x03000344
606
607/* E830 timer command register */
608#define E830_ETH_GLTSYN_CMD		0x00088814
609
610/* E810 PHC time register */
611#define E830_GLTSYN_TIME_L(_tmr_idx)	(0x0008A000 + 0x1000 * (_tmr_idx))
612
613/* Source timer incval macros */
614#define INCVAL_HIGH_M			0xFF
615
616/* PHY 40b registers macros */
617#define PHY_EXT_40B_LOW_M		GENMASK(31, 0)
618#define PHY_EXT_40B_HIGH_M		GENMASK_ULL(39, 32)
619#define PHY_40B_LOW_M			GENMASK(7, 0)
620#define PHY_40B_HIGH_M			GENMASK_ULL(39, 8)
621#define TS_VALID			BIT(0)
622#define TS_LOW_M			0xFFFFFFFF
623#define TS_HIGH_M			0xFF
624#define TS_HIGH_S			32
625
626#define BYTES_PER_IDX_ADDR_L_U		8
627#define BYTES_PER_IDX_ADDR_L		4
628
629/* Tx timestamp low latency read definitions */
630#define REG_LL_PROXY_H_TIMEOUT_US	2000
631#define REG_LL_PROXY_H_PHY_TMR_CMD_M	GENMASK(7, 6)
632#define REG_LL_PROXY_H_PHY_TMR_CMD_ADJ	0x1
633#define REG_LL_PROXY_H_PHY_TMR_CMD_FREQ	0x2
634#define REG_LL_PROXY_H_TS_HIGH		GENMASK(23, 16)
635#define REG_LL_PROXY_H_PHY_TMR_IDX_M	BIT(24)
636#define REG_LL_PROXY_H_TS_IDX		GENMASK(29, 24)
637#define REG_LL_PROXY_H_TS_INTR_ENA	BIT(30)
638#define REG_LL_PROXY_H_EXEC		BIT(31)
639
640#define REG_LL_PROXY_L			PF_SB_ATQBAH
641#define REG_LL_PROXY_H			PF_SB_ATQBAL
642
643/* Internal PHY timestamp address */
644#define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
645#define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U +		\
646			     BYTES_PER_IDX_ADDR_L))
647
648/* External PHY timestamp address */
649#define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) +			\
650				 ((idx) * BYTES_PER_IDX_ADDR_L_U))
651
652#define LOW_TX_MEMORY_BANK_START	0x03090000
653#define HIGH_TX_MEMORY_BANK_START	0x03090004
654
655/* SMA controller pin control */
656#define ICE_SMA1_DIR_EN		BIT(4)
657#define ICE_SMA1_TX_EN		BIT(5)
658#define ICE_SMA2_UFL2_RX_DIS	BIT(3)
659#define ICE_SMA2_DIR_EN		BIT(6)
660#define ICE_SMA2_TX_EN		BIT(7)
661
662#define ICE_SMA1_MASK		(ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)
663#define ICE_SMA2_MASK		(ICE_SMA2_UFL2_RX_DIS | ICE_SMA2_DIR_EN | \
664				 ICE_SMA2_TX_EN)
665#define ICE_SMA2_INACTIVE_MASK	(ICE_SMA2_DIR_EN | ICE_SMA2_TX_EN)
666#define ICE_ALL_SMA_MASK	(ICE_SMA1_MASK | ICE_SMA2_MASK)
667
668#define ICE_SMA_MIN_BIT		3
669#define ICE_SMA_MAX_BIT		7
670#define ICE_PCA9575_P1_OFFSET	8
671
672/* PCA9575 IO controller registers */
673#define ICE_PCA9575_P0_IN	0x0
674
675/*  PCA9575 IO controller pin control */
676#define ICE_P0_GNSS_PRSNT_N	BIT(4)
677
678/* ETH56G PHY register addresses */
679/* Timestamp PHY incval registers */
680#define PHY_REG_TIMETUS_L		0x8
681#define PHY_REG_TIMETUS_U		0xC
682
683/* Timestamp PCS registers */
684#define PHY_PCS_REF_TUS_L		0x18
685#define PHY_PCS_REF_TUS_U		0x1C
686
687/* Timestamp PCS ref incval registers */
688#define PHY_PCS_REF_INC_L		0x20
689#define PHY_PCS_REF_INC_U		0x24
690
691/* Timestamp init registers */
692#define PHY_REG_RX_TIMER_INC_PRE_L	0x64
693#define PHY_REG_RX_TIMER_INC_PRE_U	0x68
694#define PHY_REG_TX_TIMER_INC_PRE_L	0x44
695#define PHY_REG_TX_TIMER_INC_PRE_U	0x48
696
697/* Timestamp match and adjust target registers */
698#define PHY_REG_RX_TIMER_CNT_ADJ_L	0x6C
699#define PHY_REG_RX_TIMER_CNT_ADJ_U	0x70
700#define PHY_REG_TX_TIMER_CNT_ADJ_L	0x4C
701#define PHY_REG_TX_TIMER_CNT_ADJ_U	0x50
702
703/* Timestamp command registers */
704#define PHY_REG_TX_TMR_CMD		0x40
705#define PHY_REG_RX_TMR_CMD		0x60
706
707/* Phy offset ready registers */
708#define PHY_REG_TX_OFFSET_READY		0x54
709#define PHY_REG_RX_OFFSET_READY		0x74
710
711/* Phy total offset registers */
712#define PHY_REG_TOTAL_TX_OFFSET_L	0x38
713#define PHY_REG_TOTAL_TX_OFFSET_U	0x3C
714#define PHY_REG_TOTAL_RX_OFFSET_L	0x58
715#define PHY_REG_TOTAL_RX_OFFSET_U	0x5C
716
717/* Timestamp capture registers */
718#define PHY_REG_TX_CAPTURE_L		0x78
719#define PHY_REG_TX_CAPTURE_U		0x7C
720#define PHY_REG_RX_CAPTURE_L		0x8C
721#define PHY_REG_RX_CAPTURE_U		0x90
722
723/* Memory status registers */
724#define PHY_REG_TX_MEMORY_STATUS_L	0x80
725#define PHY_REG_TX_MEMORY_STATUS_U	0x84
726
727/* Interrupt config register */
728#define PHY_REG_TS_INT_CONFIG		0x88
729
730/* XIF mode config register */
731#define PHY_MAC_XIF_MODE		0x24
732#define PHY_MAC_XIF_1STEP_ENA_M		ICE_M(0x1, 5)
733#define PHY_MAC_XIF_TS_BIN_MODE_M	ICE_M(0x1, 11)
734#define PHY_MAC_XIF_TS_SFD_ENA_M	ICE_M(0x1, 20)
735#define PHY_MAC_XIF_GMII_TS_SEL_M	ICE_M(0x1, 21)
736
737#define PHY_TS_INT_CONFIG_THRESHOLD_M	ICE_M(0x3F, 0)
738#define PHY_TS_INT_CONFIG_ENA_M		BIT(6)
739
740/* Macros to derive offsets for TimeStampLow and TimeStampHigh */
741#define PHY_TSTAMP_L(x) (((x) * 8) + 0)
742#define PHY_TSTAMP_U(x) (((x) * 8) + 4)
743
744#define PHY_REG_DESKEW_0		0x94
745#define PHY_REG_DESKEW_0_RLEVEL		GENMASK(6, 0)
746#define PHY_REG_DESKEW_0_RLEVEL_FRAC	GENMASK(9, 7)
747#define PHY_REG_DESKEW_0_RLEVEL_FRAC_W	3
748#define PHY_REG_DESKEW_0_VALID		GENMASK(10, 10)
749
750#define PHY_REG_SD_BIT_SLIP(_port_offset)	(0x29C + 4 * (_port_offset))
751#define PHY_REVISION_ETH56G		0x10200
752#define PHY_VENDOR_TXLANE_THRESH	0x2000C
753
754#define PHY_MAC_TSU_CONFIG		0x40
755#define PHY_MAC_TSU_CFG_RX_MODE_M	ICE_M(0x7, 0)
756#define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M	ICE_M(0x7, 4)
757#define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M	ICE_M(0x7, 8)
758#define PHY_MAC_TSU_CFG_TX_MODE_M	ICE_M(0x7, 12)
759#define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M	ICE_M(0x1F, 16)
760#define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M	ICE_M(0x1F, 21)
761#define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M	ICE_M(0x1, 28)
762#define PHY_MAC_RX_MODULO		0x44
763#define PHY_MAC_RX_OFFSET		0x48
764#define PHY_MAC_RX_OFFSET_M		ICE_M(0xFFFFFF, 0)
765#define PHY_MAC_TX_MODULO		0x4C
766#define PHY_MAC_BLOCKTIME		0x50
767#define PHY_MAC_MARKERTIME		0x54
768#define PHY_MAC_TX_OFFSET		0x58
769#define PHY_GPCS_BITSLIP		0x5C
770
771#define PHY_PTP_INT_STATUS		0x7FD140
772
773/* ETH56G registers shared per quad */
774/* GPCS config register */
775#define PHY_GPCS_CONFIG_REG0		0x268
776#define PHY_GPCS_CONFIG_REG0_TX_THR_M	GENMASK(27, 24)
777/* 1-step PTP config */
778#define PHY_PTP_1STEP_CONFIG		0x270
779#define PHY_PTP_1STEP_T1S_UP64_M	GENMASK(7, 4)
780#define PHY_PTP_1STEP_T1S_DELTA_M	GENMASK(11, 8)
781#define PHY_PTP_1STEP_PEER_DELAY(_quad_lane)	(0x274 + 4 * (_quad_lane))
782#define PHY_PTP_1STEP_PD_ADD_PD_M	BIT(0)
783#define PHY_PTP_1STEP_PD_DELAY_M	GENMASK(30, 1)
784#define PHY_PTP_1STEP_PD_DLY_V_M	BIT(31)
785
786#endif /* _ICE_PTP_HW_H_ */