FILE
ice_ptp_hw.c
File preview with syntax highlighting.
linux-6.19.14/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (C) 2021, Intel Corporation. */ 3 4#include <linux/delay.h> 5#include <linux/iopoll.h> 6#include "ice_common.h" 7#include "ice_ptp_hw.h" 8#include "ice_ptp_consts.h" 9 10static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = { 11 DPLL_PIN_FREQUENCY_1PPS, 12 DPLL_PIN_FREQUENCY_10MHZ, 13}; 14 15static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = { 16 DPLL_PIN_FREQUENCY_1PPS, 17}; 18 19static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = { 20 DPLL_PIN_FREQUENCY_10MHZ, 21}; 22 23static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = { 24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 25 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 27 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, 29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, 30 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 31 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 32 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 33 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 35 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 36}; 37 38static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = { 39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 40 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 42 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, 44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, 45 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, }, 46 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, }, 47 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 48 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 49 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 50 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 51 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 52 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 53}; 54 55static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = { 56 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 57 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 58 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 59 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 60 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 61 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 62 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT, 63 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 64 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT, 65 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 66}; 67 68static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = { 69 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 70 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 71 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 72 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 73 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 74 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 75 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 76 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT, 77 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 78 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT, 79 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 80}; 81 82static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = { 83 { "NONE", SI_REF0P, 0, 0 }, 84 { "NONE", SI_REF0N, 0, 0 }, 85 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 86 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 87 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT, 88 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 89 { "NONE", SI_REF2N, 0, 0 }, 90 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT, 91 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 92 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT, 93 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 94}; 95 96static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = { 97 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT, 98 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 99 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 100 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT, 101 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 102 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT, 103 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 104}; 105 106static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = { 107 { "NONE", ZL_REF0P, 0, 0 }, 108 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT, 109 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 110 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 111 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 112 { "NONE", ZL_REF2P, 0, 0 }, 113 { "NONE", ZL_REF2N, 0, 0 }, 114 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT, 115 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 116 { "NONE", ZL_REF3N, 0, 0 }, 117 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT, 118 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 119 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 }, 120}; 121 122static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = { 123 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 124 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 125 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 126 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 127 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 128 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 129 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT, 130 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 131 { "NONE", ZL_OUT5, 0, 0 }, 132}; 133 134/* Low level functions for interacting with and managing the device clock used 135 * for the Precision Time Protocol. 136 * 137 * The ice hardware represents the current time using three registers: 138 * 139 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 140 * +---------------+ +---------------+ +---------------+ 141 * | 32 bits | | 32 bits | | 32 bits | 142 * +---------------+ +---------------+ +---------------+ 143 * 144 * The registers are incremented every clock tick using a 40bit increment 145 * value defined over two registers: 146 * 147 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 148 * +---------------+ +---------------+ 149 * | 8 bit s | | 32 bits | 150 * +---------------+ +---------------+ 151 * 152 * The increment value is added to the GLTSYN_TIME_R and GLTSYN_TIME_L 153 * registers every clock source tick. Depending on the specific device 154 * configuration, the clock source frequency could be one of a number of 155 * values. 156 * 157 * For E810 devices, the increment frequency is 812.5 MHz 158 * 159 * For E822 devices the clock can be derived from different sources, and the 160 * increment has an effective frequency of one of the following: 161 * - 823.4375 MHz 162 * - 783.36 MHz 163 * - 796.875 MHz 164 * - 816 MHz 165 * - 830.078125 MHz 166 * - 783.36 MHz 167 * 168 * The hardware captures timestamps in the PHY for incoming packets, and for 169 * outgoing packets on request. To support this, the PHY maintains a timer 170 * that matches the lower 64 bits of the global source timer. 171 * 172 * In order to ensure that the PHY timers and the source timer are equivalent, 173 * shadow registers are used to prepare the desired initial values. A special 174 * sync command is issued to trigger copying from the shadow registers into 175 * the appropriate source and PHY registers simultaneously. 176 * 177 * The driver supports devices which have different PHYs with subtly different 178 * mechanisms to program and control the timers. We divide the devices into 179 * families named after the first major device, E810 and similar devices, and 180 * E822 and similar devices. 181 * 182 * - E822 based devices have additional support for fine grained Vernier 183 * calibration which requires significant setup 184 * - The layout of timestamp data in the PHY register blocks is different 185 * - The way timer synchronization commands are issued is different. 186 * 187 * To support this, very low level functions have an e810 or e822 suffix 188 * indicating what type of device they work on. Higher level abstractions for 189 * tasks that can be done on both devices do not have the suffix and will 190 * correctly look up the appropriate low level function when running. 191 * 192 * Functions which only make sense on a single device family may not have 193 * a suitable generic implementation 194 */ 195 196/** 197 * ice_get_ptp_src_clock_index - determine source clock index 198 * @hw: pointer to HW struct 199 * 200 * Determine the source clock index currently in use, based on device 201 * capabilities reported during initialization. 202 */ 203u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 204{ 205 return hw->func_caps.ts_func_info.tmr_index_assoc; 206} 207 208/** 209 * ice_ptp_read_src_incval - Read source timer increment value 210 * @hw: pointer to HW struct 211 * 212 * Read the increment value of the source timer and return it. 213 */ 214static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 215{ 216 u32 lo, hi; 217 u8 tmr_idx; 218 219 tmr_idx = ice_get_ptp_src_clock_index(hw); 220 221 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 222 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 223 224 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 225} 226 227/** 228 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value 229 * @hw: pointer to HW struct 230 * @cmd: Timer command 231 * 232 * Return: the source timer command register value for the given PTP timer 233 * command. 234 */ 235static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw, 236 enum ice_ptp_tmr_cmd cmd) 237{ 238 u32 cmd_val, tmr_idx; 239 240 switch (cmd) { 241 case ICE_PTP_INIT_TIME: 242 cmd_val = GLTSYN_CMD_INIT_TIME; 243 break; 244 case ICE_PTP_INIT_INCVAL: 245 cmd_val = GLTSYN_CMD_INIT_INCVAL; 246 break; 247 case ICE_PTP_ADJ_TIME: 248 cmd_val = GLTSYN_CMD_ADJ_TIME; 249 break; 250 case ICE_PTP_ADJ_TIME_AT_TIME: 251 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 252 break; 253 case ICE_PTP_NOP: 254 case ICE_PTP_READ_TIME: 255 cmd_val = GLTSYN_CMD_READ_TIME; 256 break; 257 default: 258 dev_warn(ice_hw_to_dev(hw), 259 "Ignoring unrecognized timer command %u\n", cmd); 260 cmd_val = 0; 261 } 262 263 tmr_idx = ice_get_ptp_src_clock_index(hw); 264 265 return tmr_idx << SEL_CPK_SRC | cmd_val; 266} 267 268/** 269 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value 270 * @hw: pointer to HW struct 271 * @cmd: Timer command 272 * 273 * Note that some hardware families use a different command register value for 274 * the PHY ports, while other hardware families use the same register values 275 * as the source timer. 276 * 277 * Return: the PHY port timer command register value for the given PTP timer 278 * command. 279 */ 280static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, 281 enum ice_ptp_tmr_cmd cmd) 282{ 283 u32 cmd_val, tmr_idx; 284 285 /* Certain hardware families share the same register values for the 286 * port register and source timer register. 287 */ 288 switch (hw->mac_type) { 289 case ICE_MAC_E810: 290 case ICE_MAC_E830: 291 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810; 292 default: 293 break; 294 } 295 296 switch (cmd) { 297 case ICE_PTP_INIT_TIME: 298 cmd_val = PHY_CMD_INIT_TIME; 299 break; 300 case ICE_PTP_INIT_INCVAL: 301 cmd_val = PHY_CMD_INIT_INCVAL; 302 break; 303 case ICE_PTP_ADJ_TIME: 304 cmd_val = PHY_CMD_ADJ_TIME; 305 break; 306 case ICE_PTP_ADJ_TIME_AT_TIME: 307 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME; 308 break; 309 case ICE_PTP_READ_TIME: 310 cmd_val = PHY_CMD_READ_TIME; 311 break; 312 case ICE_PTP_NOP: 313 cmd_val = 0; 314 break; 315 default: 316 dev_warn(ice_hw_to_dev(hw), 317 "Ignoring unrecognized timer command %u\n", cmd); 318 cmd_val = 0; 319 } 320 321 tmr_idx = ice_get_ptp_src_clock_index(hw); 322 323 return tmr_idx << SEL_PHY_SRC | cmd_val; 324} 325 326/** 327 * ice_ptp_src_cmd - Prepare source timer for a timer command 328 * @hw: pointer to HW structure 329 * @cmd: Timer command 330 * 331 * Prepare the source timer for an upcoming timer sync command. 332 */ 333void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 334{ 335 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 336 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd); 337 338 if (!ice_is_primary(hw)) 339 hw = ice_get_primary_hw(pf); 340 341 wr32(hw, GLTSYN_CMD, cmd_val); 342} 343 344/** 345 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 346 * @hw: pointer to HW struct 347 * 348 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 349 * write immediately. This triggers the hardware to begin executing all of the 350 * source and PHY timer commands synchronously. 351 */ 352static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 353{ 354 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 355 356 if (!ice_is_primary(hw)) 357 hw = ice_get_primary_hw(pf); 358 359 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); 360 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 361 ice_flush(hw); 362} 363 364/** 365 * ice_ptp_cfg_sync_delay - Configure PHC to PHY synchronization delay 366 * @hw: pointer to HW struct 367 * @delay: delay between PHC and PHY SYNC command execution in nanoseconds 368 */ 369static void ice_ptp_cfg_sync_delay(const struct ice_hw *hw, u32 delay) 370{ 371 wr32(hw, GLTSYN_SYNC_DLAY, delay); 372 ice_flush(hw); 373} 374 375/* 56G PHY device functions 376 * 377 * The following functions operate on devices with the ETH 56G PHY. 378 */ 379 380/** 381 * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number 382 * @hw: pointer to the HW struct 383 * @port: destination port 384 * 385 * Return: destination sideband queue PHY device. 386 */ 387static enum ice_sbq_dev_id ice_ptp_get_dest_dev_e825(struct ice_hw *hw, 388 u8 port) 389{ 390 u8 curr_phy, tgt_phy; 391 392 tgt_phy = port >= hw->ptp.ports_per_phy; 393 curr_phy = hw->lane_num >= hw->ptp.ports_per_phy; 394 /* In the driver, lanes 4..7 are in fact 0..3 on a second PHY. 395 * On a single complex E825C, PHY 0 is always destination device phy_0 396 * and PHY 1 is phy_0_peer. 397 * On dual complex E825C, device phy_0 points to PHY on a current 398 * complex and phy_0_peer to PHY on a different complex. 399 */ 400 if ((!ice_is_dual(hw) && tgt_phy == 1) || 401 (ice_is_dual(hw) && tgt_phy != curr_phy)) 402 return ice_sbq_dev_phy_0_peer; 403 else 404 return ice_sbq_dev_phy_0; 405} 406 407/** 408 * ice_write_phy_eth56g - Write a PHY port register 409 * @hw: pointer to the HW struct 410 * @port: destination port 411 * @addr: PHY register address 412 * @val: Value to write 413 * 414 * Return: 0 on success, other error codes when failed to write to PHY 415 */ 416static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val) 417{ 418 struct ice_sbq_msg_input msg = { 419 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 420 .opcode = ice_sbq_msg_wr, 421 .msg_addr_low = lower_16_bits(addr), 422 .msg_addr_high = upper_16_bits(addr), 423 .data = val 424 }; 425 int err; 426 427 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 428 if (err) 429 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 430 err); 431 432 return err; 433} 434 435/** 436 * ice_read_phy_eth56g - Read a PHY port register 437 * @hw: pointer to the HW struct 438 * @port: destination port 439 * @addr: PHY register address 440 * @val: Value to write 441 * 442 * Return: 0 on success, other error codes when failed to read from PHY 443 */ 444static int ice_read_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 *val) 445{ 446 struct ice_sbq_msg_input msg = { 447 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 448 .opcode = ice_sbq_msg_rd, 449 .msg_addr_low = lower_16_bits(addr), 450 .msg_addr_high = upper_16_bits(addr) 451 }; 452 int err; 453 454 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 455 if (err) 456 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 457 err); 458 else 459 *val = msg.data; 460 461 return err; 462} 463 464/** 465 * ice_phy_res_address_eth56g - Calculate a PHY port register address 466 * @hw: pointer to the HW struct 467 * @lane: Lane number to be written 468 * @res_type: resource type (register/memory) 469 * @offset: Offset from PHY port register base 470 * @addr: The result address 471 * 472 * Return: 473 * * %0 - success 474 * * %EINVAL - invalid port number or resource type 475 */ 476static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane, 477 enum eth56g_res_type res_type, 478 u32 offset, 479 u32 *addr) 480{ 481 if (res_type >= NUM_ETH56G_PHY_RES) 482 return -EINVAL; 483 484 /* Lanes 4..7 are in fact 0..3 on a second PHY */ 485 lane %= hw->ptp.ports_per_phy; 486 *addr = eth56g_phy_res[res_type].base_addr + 487 lane * eth56g_phy_res[res_type].step + offset; 488 489 return 0; 490} 491 492/** 493 * ice_write_port_eth56g - Write a PHY port register 494 * @hw: pointer to the HW struct 495 * @offset: PHY register offset 496 * @port: Port number 497 * @val: Value to write 498 * @res_type: resource type (register/memory) 499 * 500 * Return: 501 * * %0 - success 502 * * %EINVAL - invalid port number or resource type 503 * * %other - failed to write to PHY 504 */ 505static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 506 u32 val, enum eth56g_res_type res_type) 507{ 508 u32 addr; 509 int err; 510 511 if (port >= hw->ptp.num_lports) 512 return -EINVAL; 513 514 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 515 if (err) 516 return err; 517 518 return ice_write_phy_eth56g(hw, port, addr, val); 519} 520 521/** 522 * ice_read_port_eth56g - Read a PHY port register 523 * @hw: pointer to the HW struct 524 * @offset: PHY register offset 525 * @port: Port number 526 * @val: Value to write 527 * @res_type: resource type (register/memory) 528 * 529 * Return: 530 * * %0 - success 531 * * %EINVAL - invalid port number or resource type 532 * * %other - failed to read from PHY 533 */ 534static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 535 u32 *val, enum eth56g_res_type res_type) 536{ 537 u32 addr; 538 int err; 539 540 if (port >= hw->ptp.num_lports) 541 return -EINVAL; 542 543 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 544 if (err) 545 return err; 546 547 return ice_read_phy_eth56g(hw, port, addr, val); 548} 549 550/** 551 * ice_write_ptp_reg_eth56g - Write a PHY port register 552 * @hw: pointer to the HW struct 553 * @port: Port number to be written 554 * @offset: Offset from PHY port register base 555 * @val: Value to write 556 * 557 * Return: 558 * * %0 - success 559 * * %EINVAL - invalid port number or resource type 560 * * %other - failed to write to PHY 561 */ 562static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 563 u32 val) 564{ 565 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 566} 567 568/** 569 * ice_write_mac_reg_eth56g - Write a MAC PHY port register 570 * parameter 571 * @hw: pointer to the HW struct 572 * @port: Port number to be written 573 * @offset: Offset from PHY port register base 574 * @val: Value to write 575 * 576 * Return: 577 * * %0 - success 578 * * %EINVAL - invalid port number or resource type 579 * * %other - failed to write to PHY 580 */ 581static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 582 u32 val) 583{ 584 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 585} 586 587/** 588 * ice_write_xpcs_reg_eth56g - Write a PHY port register 589 * @hw: pointer to the HW struct 590 * @port: Port number to be written 591 * @offset: Offset from PHY port register base 592 * @val: Value to write 593 * 594 * Return: 595 * * %0 - success 596 * * %EINVAL - invalid port number or resource type 597 * * %other - failed to write to PHY 598 */ 599static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 600 u32 val) 601{ 602 return ice_write_port_eth56g(hw, port, offset, val, 603 ETH56G_PHY_REG_XPCS); 604} 605 606/** 607 * ice_read_ptp_reg_eth56g - Read a PHY port register 608 * @hw: pointer to the HW struct 609 * @port: Port number to be read 610 * @offset: Offset from PHY port register base 611 * @val: Pointer to the value to read (out param) 612 * 613 * Return: 614 * * %0 - success 615 * * %EINVAL - invalid port number or resource type 616 * * %other - failed to read from PHY 617 */ 618static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 619 u32 *val) 620{ 621 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 622} 623 624/** 625 * ice_read_mac_reg_eth56g - Read a PHY port register 626 * @hw: pointer to the HW struct 627 * @port: Port number to be read 628 * @offset: Offset from PHY port register base 629 * @val: Pointer to the value to read (out param) 630 * 631 * Return: 632 * * %0 - success 633 * * %EINVAL - invalid port number or resource type 634 * * %other - failed to read from PHY 635 */ 636static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 637 u32 *val) 638{ 639 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 640} 641 642/** 643 * ice_read_gpcs_reg_eth56g - Read a PHY port register 644 * @hw: pointer to the HW struct 645 * @port: Port number to be read 646 * @offset: Offset from PHY port register base 647 * @val: Pointer to the value to read (out param) 648 * 649 * Return: 650 * * %0 - success 651 * * %EINVAL - invalid port number or resource type 652 * * %other - failed to read from PHY 653 */ 654static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 655 u32 *val) 656{ 657 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS); 658} 659 660/** 661 * ice_read_port_mem_eth56g - Read a PHY port memory location 662 * @hw: pointer to the HW struct 663 * @port: Port number to be read 664 * @offset: Offset from PHY port register base 665 * @val: Pointer to the value to read (out param) 666 * 667 * Return: 668 * * %0 - success 669 * * %EINVAL - invalid port number or resource type 670 * * %other - failed to read from PHY 671 */ 672static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 673 u32 *val) 674{ 675 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 676} 677 678/** 679 * ice_write_port_mem_eth56g - Write a PHY port memory location 680 * @hw: pointer to the HW struct 681 * @port: Port number to be read 682 * @offset: Offset from PHY port register base 683 * @val: Pointer to the value to read (out param) 684 * 685 * Return: 686 * * %0 - success 687 * * %EINVAL - invalid port number or resource type 688 * * %other - failed to write to PHY 689 */ 690static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 691 u32 val) 692{ 693 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 694} 695 696/** 697 * ice_write_quad_ptp_reg_eth56g - Write a PHY quad register 698 * @hw: pointer to the HW struct 699 * @offset: PHY register offset 700 * @port: Port number 701 * @val: Value to write 702 * 703 * Return: 704 * * %0 - success 705 * * %EIO - invalid port number or resource type 706 * * %other - failed to write to PHY 707 */ 708static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 709 u32 offset, u32 val) 710{ 711 u32 addr; 712 713 if (port >= hw->ptp.num_lports) 714 return -EIO; 715 716 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; 717 718 return ice_write_phy_eth56g(hw, port, addr, val); 719} 720 721/** 722 * ice_read_quad_ptp_reg_eth56g - Read a PHY quad register 723 * @hw: pointer to the HW struct 724 * @offset: PHY register offset 725 * @port: Port number 726 * @val: Value to read 727 * 728 * Return: 729 * * %0 - success 730 * * %EIO - invalid port number or resource type 731 * * %other - failed to read from PHY 732 */ 733static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 734 u32 offset, u32 *val) 735{ 736 u32 addr; 737 738 if (port >= hw->ptp.num_lports) 739 return -EIO; 740 741 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; 742 743 return ice_read_phy_eth56g(hw, port, addr, val); 744} 745 746/** 747 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register 748 * @low_addr: the low address to check 749 * @high_addr: on return, contains the high address of the 64bit register 750 * 751 * Write the appropriate high register offset to use. 752 * 753 * Return: true if the provided low address is one of the known 64bit PHY values 754 * represented as two 32bit registers, false otherwise. 755 */ 756static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 757{ 758 switch (low_addr) { 759 case PHY_REG_TX_TIMER_INC_PRE_L: 760 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U; 761 return true; 762 case PHY_REG_RX_TIMER_INC_PRE_L: 763 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U; 764 return true; 765 case PHY_REG_TX_CAPTURE_L: 766 *high_addr = PHY_REG_TX_CAPTURE_U; 767 return true; 768 case PHY_REG_RX_CAPTURE_L: 769 *high_addr = PHY_REG_RX_CAPTURE_U; 770 return true; 771 case PHY_REG_TOTAL_TX_OFFSET_L: 772 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U; 773 return true; 774 case PHY_REG_TOTAL_RX_OFFSET_L: 775 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U; 776 return true; 777 case PHY_REG_TX_MEMORY_STATUS_L: 778 *high_addr = PHY_REG_TX_MEMORY_STATUS_U; 779 return true; 780 default: 781 return false; 782 } 783} 784 785/** 786 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register 787 * @low_addr: the low address to check 788 * @high_addr: on return, contains the high address of the 40bit value 789 * 790 * Write the appropriate high register offset to use. 791 * 792 * Return: true if the provided low address is one of the known 40bit PHY 793 * values split into two registers with the lower 8 bits in the low register and 794 * the upper 32 bits in the high register, false otherwise. 795 */ 796static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 797{ 798 switch (low_addr) { 799 case PHY_REG_TIMETUS_L: 800 *high_addr = PHY_REG_TIMETUS_U; 801 return true; 802 case PHY_PCS_REF_TUS_L: 803 *high_addr = PHY_PCS_REF_TUS_U; 804 return true; 805 case PHY_PCS_REF_INC_L: 806 *high_addr = PHY_PCS_REF_INC_U; 807 return true; 808 default: 809 return false; 810 } 811} 812 813/** 814 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers 815 * @hw: pointer to the HW struct 816 * @port: PHY port to read from 817 * @low_addr: offset of the lower register to read from 818 * @val: on return, the contents of the 64bit value from the PHY registers 819 * @res_type: resource type 820 * 821 * Check if the caller has specified a known 40 bit register offset and read 822 * the two registers associated with a 40bit value and return it in the val 823 * pointer. 824 * 825 * Return: 826 * * %0 - success 827 * * %EINVAL - not a 64 bit register 828 * * %other - failed to read from PHY 829 */ 830static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 831 u64 *val, enum eth56g_res_type res_type) 832{ 833 u16 high_addr; 834 u32 lo, hi; 835 int err; 836 837 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 838 return -EINVAL; 839 840 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type); 841 if (err) { 842 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d", 843 low_addr, err); 844 return err; 845 } 846 847 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type); 848 if (err) { 849 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d", 850 high_addr, err); 851 return err; 852 } 853 854 *val = ((u64)hi << 32) | lo; 855 856 return 0; 857} 858 859/** 860 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers 861 * @hw: pointer to the HW struct 862 * @port: PHY port to read from 863 * @low_addr: offset of the lower register to read from 864 * @val: on return, the contents of the 64bit value from the PHY registers 865 * 866 * Check if the caller has specified a known 40 bit register offset and read 867 * the two registers associated with a 40bit value and return it in the val 868 * pointer. 869 * 870 * Return: 871 * * %0 - success 872 * * %EINVAL - not a 64 bit register 873 * * %other - failed to read from PHY 874 */ 875static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 876 u64 *val) 877{ 878 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val, 879 ETH56G_PHY_REG_PTP); 880} 881 882/** 883 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY 884 * @hw: pointer to the HW struct 885 * @port: port to write to 886 * @low_addr: offset of the low register 887 * @val: 40b value to write 888 * @res_type: resource type 889 * 890 * Check if the caller has specified a known 40 bit register offset and write 891 * provided 40b value to the two associated registers by splitting it up into 892 * two chunks, the lower 8 bits and the upper 32 bits. 893 * 894 * Return: 895 * * %0 - success 896 * * %EINVAL - not a 40 bit register 897 * * %other - failed to write to PHY 898 */ 899static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 900 u16 low_addr, u64 val, 901 enum eth56g_res_type res_type) 902{ 903 u16 high_addr; 904 u32 lo, hi; 905 int err; 906 907 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) 908 return -EINVAL; 909 910 lo = FIELD_GET(P_REG_40B_LOW_M, val); 911 hi = (u32)(val >> P_REG_40B_HIGH_S); 912 913 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 914 if (err) { 915 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 916 low_addr, err); 917 return err; 918 } 919 920 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 921 if (err) { 922 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 923 high_addr, err); 924 return err; 925 } 926 927 return 0; 928} 929 930/** 931 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY 932 * @hw: pointer to the HW struct 933 * @port: port to write to 934 * @low_addr: offset of the low register 935 * @val: 40b value to write 936 * 937 * Check if the caller has specified a known 40 bit register offset and write 938 * provided 40b value to the two associated registers by splitting it up into 939 * two chunks, the lower 8 bits and the upper 32 bits. 940 * 941 * Return: 942 * * %0 - success 943 * * %EINVAL - not a 40 bit register 944 * * %other - failed to write to PHY 945 */ 946static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 947 u16 low_addr, u64 val) 948{ 949 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val, 950 ETH56G_PHY_REG_PTP); 951} 952 953/** 954 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers 955 * @hw: pointer to the HW struct 956 * @port: PHY port to read from 957 * @low_addr: offset of the lower register to read from 958 * @val: the contents of the 64bit value to write to PHY 959 * @res_type: resource type 960 * 961 * Check if the caller has specified a known 64 bit register offset and write 962 * the 64bit value to the two associated 32bit PHY registers. 963 * 964 * Return: 965 * * %0 - success 966 * * %EINVAL - not a 64 bit register 967 * * %other - failed to write to PHY 968 */ 969static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 970 u16 low_addr, u64 val, 971 enum eth56g_res_type res_type) 972{ 973 u16 high_addr; 974 u32 lo, hi; 975 int err; 976 977 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 978 return -EINVAL; 979 980 lo = lower_32_bits(val); 981 hi = upper_32_bits(val); 982 983 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 984 if (err) { 985 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 986 low_addr, err); 987 return err; 988 } 989 990 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 991 if (err) { 992 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 993 high_addr, err); 994 return err; 995 } 996 997 return 0; 998} 999 1000/** 1001 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers 1002 * @hw: pointer to the HW struct 1003 * @port: PHY port to read from 1004 * @low_addr: offset of the lower register to read from 1005 * @val: the contents of the 64bit value to write to PHY 1006 * 1007 * Check if the caller has specified a known 64 bit register offset and write 1008 * the 64bit value to the two associated 32bit PHY registers. 1009 * 1010 * Return: 1011 * * %0 - success 1012 * * %EINVAL - not a 64 bit register 1013 * * %other - failed to write to PHY 1014 */ 1015static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1016 u16 low_addr, u64 val) 1017{ 1018 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val, 1019 ETH56G_PHY_REG_PTP); 1020} 1021 1022/** 1023 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory 1024 * @hw: pointer to the HW struct 1025 * @port: the port to read from 1026 * @idx: the timestamp index to read 1027 * @tstamp: on return, the 40bit timestamp value 1028 * 1029 * Read a 40bit timestamp value out of the two associated entries in the 1030 * port memory block of the internal PHYs of the 56G devices. 1031 * 1032 * Return: 1033 * * %0 - success 1034 * * %other - failed to read from PHY 1035 */ 1036static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, 1037 u64 *tstamp) 1038{ 1039 u16 lo_addr, hi_addr; 1040 u32 lo, hi; 1041 int err; 1042 1043 lo_addr = (u16)PHY_TSTAMP_L(idx); 1044 hi_addr = (u16)PHY_TSTAMP_U(idx); 1045 1046 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo); 1047 if (err) { 1048 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 1049 err); 1050 return err; 1051 } 1052 1053 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi); 1054 if (err) { 1055 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 1056 err); 1057 return err; 1058 } 1059 1060 /* For 56G based internal PHYs, the timestamp is reported with the 1061 * lower 8 bits in the low register, and the upper 32 bits in the high 1062 * register. 1063 */ 1064 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 1065 FIELD_PREP(PHY_40B_LOW_M, lo); 1066 return 0; 1067} 1068 1069/** 1070 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block 1071 * @hw: pointer to the HW struct 1072 * @port: the quad to read from 1073 * @idx: the timestamp index to reset 1074 * 1075 * Read and then forcibly clear the timestamp index to ensure the valid bit is 1076 * cleared and the timestamp status bit is reset in the PHY port memory of 1077 * internal PHYs of the 56G devices. 1078 * 1079 * To directly clear the contents of the timestamp block entirely, discarding 1080 * all timestamp data at once, software should instead use 1081 * ice_ptp_reset_ts_memory_quad_eth56g(). 1082 * 1083 * This function should only be called on an idx whose bit is set according to 1084 * ice_get_phy_tx_tstamp_ready(). 1085 * 1086 * Return: 1087 * * %0 - success 1088 * * %other - failed to write to PHY 1089 */ 1090static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) 1091{ 1092 u64 unused_tstamp; 1093 u16 lo_addr; 1094 int err; 1095 1096 /* Read the timestamp register to ensure the timestamp status bit is 1097 * cleared. 1098 */ 1099 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp); 1100 if (err) { 1101 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", 1102 port, idx, err); 1103 } 1104 1105 lo_addr = (u16)PHY_TSTAMP_L(idx); 1106 1107 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0); 1108 if (err) { 1109 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n", 1110 port, idx, err); 1111 return err; 1112 } 1113 1114 return 0; 1115} 1116 1117/** 1118 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block 1119 * @hw: pointer to the HW struct 1120 */ 1121static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) 1122{ 1123 unsigned int port; 1124 1125 for (port = 0; port < hw->ptp.num_lports; port++) { 1126 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 1127 0); 1128 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, 1129 0); 1130 } 1131} 1132 1133/** 1134 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time 1135 * @hw: pointer to the HW struct 1136 * @port: port number 1137 * @time: time to initialize the PHY port clocks to 1138 * 1139 * Write a new initial time value into registers of a specific PHY port. 1140 * 1141 * Return: 1142 * * %0 - success 1143 * * %other - failed to write to PHY 1144 */ 1145static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port, 1146 u64 time) 1147{ 1148 int err; 1149 1150 /* Tx case */ 1151 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1152 time); 1153 if (err) 1154 return err; 1155 1156 /* Rx case */ 1157 return ice_write_64b_ptp_reg_eth56g(hw, port, 1158 PHY_REG_RX_TIMER_INC_PRE_L, time); 1159} 1160 1161/** 1162 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time 1163 * @hw: pointer to the HW struct 1164 * @time: Time to initialize the PHY port clocks to 1165 * 1166 * Program the PHY port registers with a new initial time value. The port 1167 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 1168 * command. The time value is the upper 32 bits of the PHY timer, usually in 1169 * units of nominal nanoseconds. 1170 * 1171 * Return: 1172 * * %0 - success 1173 * * %other - failed to write to PHY 1174 */ 1175static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) 1176{ 1177 u64 phy_time; 1178 u8 port; 1179 1180 /* The time represents the upper 32 bits of the PHY timer, so we need 1181 * to shift to account for this when programming. 1182 */ 1183 phy_time = (u64)time << 32; 1184 1185 for (port = 0; port < hw->ptp.num_lports; port++) { 1186 int err; 1187 1188 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time); 1189 if (err) { 1190 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1191 port, err); 1192 return err; 1193 } 1194 } 1195 1196 return 0; 1197} 1198 1199/** 1200 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust 1201 * @hw: pointer to HW struct 1202 * @port: Port number to be programmed 1203 * @time: time in cycles to adjust the port clocks 1204 * 1205 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1206 * registers. The atomic adjustment won't be completed until the driver issues 1207 * an ICE_PTP_ADJ_TIME command. 1208 * 1209 * Note that time is not in units of nanoseconds. It is in clock time 1210 * including the lower sub-nanosecond portion of the port timer. 1211 * 1212 * Negative adjustments are supported using 2s complement arithmetic. 1213 * 1214 * Return: 1215 * * %0 - success 1216 * * %other - failed to write to PHY 1217 */ 1218static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time) 1219{ 1220 u32 l_time, u_time; 1221 int err; 1222 1223 l_time = lower_32_bits(time); 1224 u_time = upper_32_bits(time); 1225 1226 /* Tx case */ 1227 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1228 l_time); 1229 if (err) 1230 goto exit_err; 1231 1232 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U, 1233 u_time); 1234 if (err) 1235 goto exit_err; 1236 1237 /* Rx case */ 1238 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L, 1239 l_time); 1240 if (err) 1241 goto exit_err; 1242 1243 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U, 1244 u_time); 1245 if (err) 1246 goto exit_err; 1247 1248 return 0; 1249 1250exit_err: 1251 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1252 port, err); 1253 return err; 1254} 1255 1256/** 1257 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment 1258 * @hw: pointer to HW struct 1259 * @adj: adjustment in nanoseconds 1260 * 1261 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1262 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1263 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 1264 * 1265 * Return: 1266 * * %0 - success 1267 * * %other - failed to write to PHY 1268 */ 1269static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj) 1270{ 1271 s64 cycles; 1272 u8 port; 1273 1274 /* The port clock supports adjustment of the sub-nanosecond portion of 1275 * the clock (lowest 32 bits). We shift the provided adjustment in 1276 * nanoseconds by 32 to calculate the appropriate adjustment to program 1277 * into the PHY ports. 1278 */ 1279 cycles = (s64)adj << 32; 1280 1281 for (port = 0; port < hw->ptp.num_lports; port++) { 1282 int err; 1283 1284 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles); 1285 if (err) 1286 return err; 1287 } 1288 1289 return 0; 1290} 1291 1292/** 1293 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment 1294 * @hw: pointer to HW struct 1295 * @incval: new increment value to prepare 1296 * 1297 * Prepare each of the PHY ports for a new increment value by programming the 1298 * port's TIMETUS registers. The new increment value will be updated after 1299 * issuing an ICE_PTP_INIT_INCVAL command. 1300 * 1301 * Return: 1302 * * %0 - success 1303 * * %other - failed to write to PHY 1304 */ 1305static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) 1306{ 1307 u8 port; 1308 1309 for (port = 0; port < hw->ptp.num_lports; port++) { 1310 int err; 1311 1312 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, 1313 incval); 1314 if (err) { 1315 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1316 port, err); 1317 return err; 1318 } 1319 } 1320 1321 return 0; 1322} 1323 1324/** 1325 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture 1326 * @hw: pointer to HW struct 1327 * @port: Port number to read 1328 * @tx_ts: on return, the Tx port time capture 1329 * @rx_ts: on return, the Rx port time capture 1330 * 1331 * Read the port's Tx and Rx local time capture values. 1332 * 1333 * Return: 1334 * * %0 - success 1335 * * %other - failed to read from PHY 1336 */ 1337static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, 1338 u64 *tx_ts, u64 *rx_ts) 1339{ 1340 int err; 1341 1342 /* Tx case */ 1343 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L, 1344 tx_ts); 1345 if (err) { 1346 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1347 err); 1348 return err; 1349 } 1350 1351 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts); 1352 1353 /* Rx case */ 1354 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L, 1355 rx_ts); 1356 if (err) { 1357 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1358 err); 1359 return err; 1360 } 1361 1362 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts); 1363 1364 return 0; 1365} 1366 1367/** 1368 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command 1369 * @hw: pointer to HW struct 1370 * @port: Port to which cmd has to be sent 1371 * @cmd: Command to be sent to the port 1372 * 1373 * Prepare the requested port for an upcoming timer sync command. 1374 * 1375 * Return: 1376 * * %0 - success 1377 * * %other - failed to write to PHY 1378 */ 1379static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port, 1380 enum ice_ptp_tmr_cmd cmd) 1381{ 1382 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 1383 int err; 1384 1385 /* Tx case */ 1386 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val); 1387 if (err) { 1388 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1389 err); 1390 return err; 1391 } 1392 1393 /* Rx case */ 1394 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val); 1395 if (err) { 1396 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1397 err); 1398 return err; 1399 } 1400 1401 return 0; 1402} 1403 1404/** 1405 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type 1406 * @li: pointer to link information struct 1407 * 1408 * Return: simplified ETH56G PHY speed 1409 */ 1410static enum ice_eth56g_link_spd 1411ice_phy_get_speed_eth56g(struct ice_link_status *li) 1412{ 1413 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, 1414 li->phy_type_high); 1415 1416 switch (speed) { 1417 case ICE_AQ_LINK_SPEED_1000MB: 1418 return ICE_ETH56G_LNK_SPD_1G; 1419 case ICE_AQ_LINK_SPEED_2500MB: 1420 return ICE_ETH56G_LNK_SPD_2_5G; 1421 case ICE_AQ_LINK_SPEED_10GB: 1422 return ICE_ETH56G_LNK_SPD_10G; 1423 case ICE_AQ_LINK_SPEED_25GB: 1424 return ICE_ETH56G_LNK_SPD_25G; 1425 case ICE_AQ_LINK_SPEED_40GB: 1426 return ICE_ETH56G_LNK_SPD_40G; 1427 case ICE_AQ_LINK_SPEED_50GB: 1428 switch (li->phy_type_low) { 1429 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1430 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1431 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1432 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1433 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1434 case ICE_PHY_TYPE_LOW_50G_AUI1: 1435 return ICE_ETH56G_LNK_SPD_50G; 1436 default: 1437 return ICE_ETH56G_LNK_SPD_50G2; 1438 } 1439 case ICE_AQ_LINK_SPEED_100GB: 1440 if (li->phy_type_high || 1441 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) 1442 return ICE_ETH56G_LNK_SPD_100G2; 1443 else 1444 return ICE_ETH56G_LNK_SPD_100G; 1445 default: 1446 return ICE_ETH56G_LNK_SPD_1G; 1447 } 1448} 1449 1450/** 1451 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle 1452 * @hw: pointer to the HW struct 1453 * @port: port to configure 1454 * 1455 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1456 * timestamp calibration process. 1457 * 1458 * Return: 1459 * * %0 - success 1460 * * %other - PHY read/write failed 1461 */ 1462static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port) 1463{ 1464 u32 val; 1465 int err; 1466 1467 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH, 1468 ICE_ETH56G_NOMINAL_THRESH4); 1469 if (err) { 1470 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d", 1471 err); 1472 return err; 1473 } 1474 1475 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 1476 case ICE_ETH56G_LNK_SPD_1G: 1477 case ICE_ETH56G_LNK_SPD_2_5G: 1478 err = ice_read_quad_ptp_reg_eth56g(hw, port, 1479 PHY_GPCS_CONFIG_REG0, &val); 1480 if (err) { 1481 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d", 1482 err); 1483 return err; 1484 } 1485 1486 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M; 1487 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M, 1488 ICE_ETH56G_NOMINAL_TX_THRESH); 1489 1490 err = ice_write_quad_ptp_reg_eth56g(hw, port, 1491 PHY_GPCS_CONFIG_REG0, val); 1492 if (err) { 1493 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d", 1494 err); 1495 return err; 1496 } 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L, 1503 ICE_ETH56G_NOMINAL_PCS_REF_TUS); 1504 if (err) { 1505 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d", 1506 err); 1507 return err; 1508 } 1509 1510 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L, 1511 ICE_ETH56G_NOMINAL_PCS_REF_INC); 1512 if (err) { 1513 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d", 1514 err); 1515 return err; 1516 } 1517 1518 return 0; 1519} 1520 1521/** 1522 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings 1523 * @hw: Pointer to the HW struct 1524 * @port: Port to configure 1525 * 1526 * Return: 1527 * * %0 - success 1528 * * %other - PHY read/write failed 1529 */ 1530int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port) 1531{ 1532 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 1533 u32 addr, val, peer_delay; 1534 bool enable, sfd_ena; 1535 int err; 1536 1537 enable = hw->ptp.phy.eth56g.onestep_ena; 1538 peer_delay = hw->ptp.phy.eth56g.peer_delay; 1539 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; 1540 1541 addr = PHY_PTP_1STEP_CONFIG; 1542 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &val); 1543 if (err) 1544 return err; 1545 1546 if (enable) 1547 val |= BIT(quad_lane); 1548 else 1549 val &= ~BIT(quad_lane); 1550 1551 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M); 1552 1553 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 1554 if (err) 1555 return err; 1556 1557 addr = PHY_PTP_1STEP_PEER_DELAY(quad_lane); 1558 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay); 1559 if (peer_delay) 1560 val |= PHY_PTP_1STEP_PD_ADD_PD_M; 1561 val |= PHY_PTP_1STEP_PD_DLY_V_M; 1562 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 1563 if (err) 1564 return err; 1565 1566 val &= ~PHY_PTP_1STEP_PD_DLY_V_M; 1567 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 1568 if (err) 1569 return err; 1570 1571 addr = PHY_MAC_XIF_MODE; 1572 err = ice_read_mac_reg_eth56g(hw, port, addr, &val); 1573 if (err) 1574 return err; 1575 1576 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M | 1577 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M); 1578 1579 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 1580 case ICE_ETH56G_LNK_SPD_1G: 1581 case ICE_ETH56G_LNK_SPD_2_5G: 1582 val |= PHY_MAC_XIF_GMII_TS_SEL_M; 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) | 1589 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) | 1590 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena); 1591 1592 return ice_write_mac_reg_eth56g(hw, port, addr, val); 1593} 1594 1595/** 1596 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values 1597 * @a: multiplier value 1598 * @b: multiplicand value 1599 * 1600 * Return: result of multiplication 1601 */ 1602static u32 mul_u32_u32_fx_q9(u32 a, u32 b) 1603{ 1604 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W); 1605} 1606 1607/** 1608 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow 1609 * @a: first value 1610 * @b: second value 1611 * 1612 * Return: result of addition 1613 */ 1614static u32 add_u32_u32_fx(u32 a, u32 b) 1615{ 1616 return lower_32_bits(((u64)a + b)); 1617} 1618 1619/** 1620 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value 1621 * @hw: pointer to the HW struct 1622 * @port: port to configure 1623 * @bs: bitslip multiplier 1624 * @fc: FC-FEC enabled 1625 * @rs: RS-FEC enabled 1626 * @spd: link speed 1627 * 1628 * Return: calculated bitslip value 1629 */ 1630static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, 1631 bool fc, bool rs, 1632 enum ice_eth56g_link_spd spd) 1633{ 1634 u32 bitslip; 1635 int err; 1636 1637 if (!bs || rs) 1638 return 0; 1639 1640 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) { 1641 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP, 1642 &bitslip); 1643 } else { 1644 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 1645 u32 addr; 1646 1647 addr = PHY_REG_SD_BIT_SLIP(quad_lane); 1648 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &bitslip); 1649 } 1650 if (err) 1651 return 0; 1652 1653 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) { 1654 /* Bitslip register value of 0 corresponds to 10 so substitute 1655 * it for calculations 1656 */ 1657 bitslip = 10; 1658 } else if (spd == ICE_ETH56G_LNK_SPD_10G || 1659 spd == ICE_ETH56G_LNK_SPD_25G) { 1660 if (fc) 1661 bitslip = bitslip * 2 + 32; 1662 else 1663 bitslip = (u32)((s32)bitslip * -1 + 20); 1664 } 1665 1666 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W; 1667 return mul_u32_u32_fx_q9(bitslip, bs); 1668} 1669 1670/** 1671 * ice_ptp_calc_deskew_eth56g - Calculate deskew value 1672 * @hw: pointer to the HW struct 1673 * @port: port to configure 1674 * @ds: deskew multiplier 1675 * @rs: RS-FEC enabled 1676 * @spd: link speed 1677 * 1678 * Return: calculated deskew value 1679 */ 1680static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, 1681 bool rs, enum ice_eth56g_link_spd spd) 1682{ 1683 u32 deskew_i, deskew_f; 1684 int err; 1685 1686 if (!ds) 1687 return 0; 1688 1689 read_poll_timeout(ice_read_ptp_reg_eth56g, err, 1690 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500, 1691 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0, 1692 &deskew_i); 1693 if (err) 1694 return err; 1695 1696 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i); 1697 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i); 1698 1699 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2) 1700 ds = 0x633; /* 3.1 */ 1701 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G) 1702 ds = 0x31b; /* 1.552 */ 1703 1704 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i); 1705 /* Shift 3 fractional bits to the end of the integer part */ 1706 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; 1707 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); 1708} 1709 1710/** 1711 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values 1712 * @hw: pointer to the HW struct 1713 * @port: port to configure 1714 * @spd: link speed 1715 * @cfg: structure to store output values 1716 * @fc: FC-FEC enabled 1717 * @rs: RS-FEC enabled 1718 * 1719 * Return: 1720 * * %0 - success 1721 * * %other - failed to write to PHY 1722 */ 1723static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, 1724 enum ice_eth56g_link_spd spd, 1725 const struct ice_eth56g_mac_reg_cfg *cfg, 1726 bool fc, bool rs) 1727{ 1728 u32 rx_offset, tx_offset, bs_ds; 1729 bool onestep, sfd; 1730 1731 onestep = hw->ptp.phy.eth56g.onestep_ena; 1732 sfd = hw->ptp.phy.eth56g.sfd_ena; 1733 bs_ds = cfg->rx_offset.bs_ds; 1734 1735 if (fc) 1736 rx_offset = cfg->rx_offset.fc; 1737 else if (rs) 1738 rx_offset = cfg->rx_offset.rs; 1739 else 1740 rx_offset = cfg->rx_offset.no_fec; 1741 1742 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); 1743 if (sfd) 1744 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); 1745 1746 if (spd < ICE_ETH56G_LNK_SPD_40G) 1747 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs, 1748 spd); 1749 else 1750 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd); 1751 rx_offset = add_u32_u32_fx(rx_offset, bs_ds); 1752 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT | 1753 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC; 1754 1755 if (fc) 1756 tx_offset = cfg->tx_offset.fc; 1757 else if (rs) 1758 tx_offset = cfg->tx_offset.rs; 1759 else 1760 tx_offset = cfg->tx_offset.no_fec; 1761 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + 1762 cfg->tx_offset.onestep * onestep; 1763 1764 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset); 1765 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset); 1766} 1767 1768/** 1769 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP 1770 * @hw: Pointer to the HW struct 1771 * @port: Port to configure 1772 * 1773 * Return: 1774 * * %0 - success 1775 * * %other - failed to write to PHY 1776 */ 1777static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port) 1778{ 1779 const struct ice_eth56g_mac_reg_cfg *cfg; 1780 enum ice_eth56g_link_spd spd; 1781 struct ice_link_status *li; 1782 bool fc = false; 1783 bool rs = false; 1784 bool onestep; 1785 u32 val; 1786 int err; 1787 1788 onestep = hw->ptp.phy.eth56g.onestep_ena; 1789 li = &hw->port_info->phy.link_info; 1790 spd = ice_phy_get_speed_eth56g(li); 1791 if (!!(li->an_info & ICE_AQ_FEC_EN)) { 1792 if (spd == ICE_ETH56G_LNK_SPD_10G) { 1793 fc = true; 1794 } else { 1795 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); 1796 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); 1797 } 1798 } 1799 cfg = ð56g_mac_cfg[spd]; 1800 1801 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0); 1802 if (err) 1803 return err; 1804 1805 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0); 1806 if (err) 1807 return err; 1808 1809 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M, 1810 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | 1811 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | 1812 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M, 1813 cfg->tx_cw_dly.def + 1814 onestep * cfg->tx_cw_dly.onestep) | 1815 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M, 1816 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | 1817 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M, 1818 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | 1819 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M, 1820 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | 1821 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); 1822 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val); 1823 if (err) 1824 return err; 1825 1826 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME, 1827 cfg->blktime); 1828 if (err) 1829 return err; 1830 1831 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs); 1832 if (err) 1833 return err; 1834 1835 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs) 1836 val = 0; 1837 else 1838 val = cfg->mktime; 1839 1840 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val); 1841} 1842 1843/** 1844 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt 1845 * @hw: pointer to the HW struct 1846 * @port: the timestamp port 1847 * @ena: enable or disable interrupt 1848 * @threshold: interrupt threshold 1849 * 1850 * Configure TX timestamp interrupt for the specified port 1851 * 1852 * Return: 1853 * * %0 - success 1854 * * %other - PHY read/write failed 1855 */ 1856int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) 1857{ 1858 int err; 1859 u32 val; 1860 1861 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val); 1862 if (err) 1863 return err; 1864 1865 if (ena) { 1866 val |= PHY_TS_INT_CONFIG_ENA_M; 1867 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M; 1868 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold); 1869 } else { 1870 val &= ~PHY_TS_INT_CONFIG_ENA_M; 1871 } 1872 1873 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val); 1874} 1875 1876/** 1877 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time 1878 * @hw: pointer to the HW struct 1879 * @port: the PHY port to read 1880 * @phy_time: on return, the 64bit PHY timer value 1881 * @phc_time: on return, the lower 64bits of PHC time 1882 * 1883 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 1884 * and PHC timer values. 1885 * 1886 * Return: 1887 * * %0 - success 1888 * * %other - PHY read/write failed 1889 */ 1890static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, 1891 u64 *phy_time, u64 *phc_time) 1892{ 1893 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1894 u64 tx_time, rx_time; 1895 u32 zo, lo; 1896 u8 tmr_idx; 1897 int err; 1898 1899 tmr_idx = ice_get_ptp_src_clock_index(hw); 1900 1901 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 1902 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 1903 1904 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 1905 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 1906 if (err) 1907 return err; 1908 1909 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 1910 ice_ptp_exec_tmr_cmd(hw); 1911 1912 /* Read the captured PHC time from the shadow time registers */ 1913 if (ice_is_primary(hw)) { 1914 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 1915 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 1916 } else { 1917 zo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_0(tmr_idx)); 1918 lo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_L(tmr_idx)); 1919 } 1920 *phc_time = (u64)lo << 32 | zo; 1921 1922 /* Read the captured PHY time from the PHY shadow registers */ 1923 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time); 1924 if (err) 1925 return err; 1926 1927 /* If the PHY Tx and Rx timers don't match, log a warning message. 1928 * Note that this should not happen in normal circumstances since the 1929 * driver always programs them together. 1930 */ 1931 if (tx_time != rx_time) 1932 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 1933 port, tx_time, rx_time); 1934 1935 *phy_time = tx_time; 1936 1937 return 0; 1938} 1939 1940/** 1941 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer 1942 * @hw: pointer to the HW struct 1943 * @port: the PHY port to synchronize 1944 * 1945 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 1946 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 1947 * simultaneous read of the PHY timer and PHC timer. Then we use the 1948 * difference to calculate an appropriate 2s complement addition to add 1949 * to the PHY timer in order to ensure it reads the same value as the 1950 * primary PHC timer. 1951 * 1952 * Return: 1953 * * %0 - success 1954 * * %-EBUSY- failed to acquire PTP semaphore 1955 * * %other - PHY read/write failed 1956 */ 1957static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) 1958{ 1959 u64 phc_time, phy_time, difference; 1960 int err; 1961 1962 if (!ice_ptp_lock(hw)) { 1963 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 1964 return -EBUSY; 1965 } 1966 1967 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 1968 if (err) 1969 goto err_unlock; 1970 1971 /* Calculate the amount required to add to the port time in order for 1972 * it to match the PHC time. 1973 * 1974 * Note that the port adjustment is done using 2s complement 1975 * arithmetic. This is convenient since it means that we can simply 1976 * calculate the difference between the PHC time and the port time, 1977 * and it will be interpreted correctly. 1978 */ 1979 1980 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 1981 difference = phc_time - phy_time; 1982 1983 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference); 1984 if (err) 1985 goto err_unlock; 1986 1987 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 1988 if (err) 1989 goto err_unlock; 1990 1991 /* Issue the sync to activate the time adjustment */ 1992 ice_ptp_exec_tmr_cmd(hw); 1993 1994 /* Re-capture the timer values to flush the command registers and 1995 * verify that the time was properly adjusted. 1996 */ 1997 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 1998 if (err) 1999 goto err_unlock; 2000 2001 dev_info(ice_hw_to_dev(hw), 2002 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 2003 port, phy_time, phc_time); 2004 2005err_unlock: 2006 ice_ptp_unlock(hw); 2007 return err; 2008} 2009 2010/** 2011 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer 2012 * @hw: pointer to the HW struct 2013 * @port: the PHY port to stop 2014 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS 2015 * 2016 * Stop the clock of a PHY port. This must be done as part of the flow to 2017 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2018 * initialized or when link speed changes. 2019 * 2020 * Return: 2021 * * %0 - success 2022 * * %other - failed to write to PHY 2023 */ 2024int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) 2025{ 2026 int err; 2027 2028 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0); 2029 if (err) 2030 return err; 2031 2032 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0); 2033 if (err) 2034 return err; 2035 2036 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 2037 2038 return 0; 2039} 2040 2041/** 2042 * ice_start_phy_timer_eth56g - Start the PHY clock timer 2043 * @hw: pointer to the HW struct 2044 * @port: the PHY port to start 2045 * 2046 * Start the clock of a PHY port. This must be done as part of the flow to 2047 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2048 * initialized or when link speed changes. 2049 * 2050 * Return: 2051 * * %0 - success 2052 * * %other - PHY read/write failed 2053 */ 2054int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2055{ 2056 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 2057 u32 lo, hi; 2058 u64 incval; 2059 u8 tmr_idx; 2060 int err; 2061 2062 tmr_idx = ice_get_ptp_src_clock_index(hw); 2063 2064 err = ice_stop_phy_timer_eth56g(hw, port, false); 2065 if (err) 2066 return err; 2067 2068 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2069 2070 err = ice_phy_cfg_parpcs_eth56g(hw, port); 2071 if (err) 2072 return err; 2073 2074 err = ice_phy_cfg_ptp_1step_eth56g(hw, port); 2075 if (err) 2076 return err; 2077 2078 err = ice_phy_cfg_mac_eth56g(hw, port); 2079 if (err) 2080 return err; 2081 2082 if (ice_is_primary(hw)) { 2083 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2084 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2085 } else { 2086 lo = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_L(tmr_idx)); 2087 hi = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_H(tmr_idx)); 2088 } 2089 incval = (u64)hi << 32 | lo; 2090 2091 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval); 2092 if (err) 2093 return err; 2094 2095 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 2096 if (err) 2097 return err; 2098 2099 ice_ptp_exec_tmr_cmd(hw); 2100 2101 err = ice_sync_phy_timer_eth56g(hw, port); 2102 if (err) 2103 return err; 2104 2105 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); 2106 if (err) 2107 return err; 2108 2109 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); 2110 if (err) 2111 return err; 2112 2113 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2114 2115 return 0; 2116} 2117 2118/** 2119 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status 2120 * @hw: pointer to the HW struct 2121 * @ts_status: the timestamp mask pointer 2122 * 2123 * Read the PHY Tx timestamp status mask indicating which ports have Tx 2124 * timestamps available. 2125 * 2126 * Return: 2127 * * %0 - success 2128 * * %other - failed to read from PHY 2129 */ 2130int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) 2131{ 2132 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; 2133 u8 phy, mask; 2134 u32 status; 2135 2136 mask = (1 << hw->ptp.ports_per_phy) - 1; 2137 *ts_status = 0; 2138 2139 for (phy = 0; phy < params->num_phys; phy++) { 2140 int err; 2141 2142 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status); 2143 if (err) 2144 return err; 2145 2146 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy); 2147 } 2148 2149 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status); 2150 2151 return 0; 2152} 2153 2154/** 2155 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register 2156 * @hw: pointer to the HW struct 2157 * @port: the PHY port to read from 2158 * @tstamp_ready: contents of the Tx memory status register 2159 * 2160 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in 2161 * the PHY are ready. A set bit means the corresponding timestamp is valid and 2162 * ready to be captured from the PHY timestamp block. 2163 * 2164 * Return: 2165 * * %0 - success 2166 * * %other - failed to read from PHY 2167 */ 2168static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, 2169 u64 *tstamp_ready) 2170{ 2171 int err; 2172 2173 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 2174 tstamp_ready); 2175 if (err) { 2176 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n", 2177 port, err); 2178 return err; 2179 } 2180 2181 return 0; 2182} 2183 2184/** 2185 * ice_ptp_init_phy_e825 - initialize PHY parameters 2186 * @hw: pointer to the HW struct 2187 */ 2188static void ice_ptp_init_phy_e825(struct ice_hw *hw) 2189{ 2190 struct ice_ptp_hw *ptp = &hw->ptp; 2191 struct ice_eth56g_params *params; 2192 2193 params = &ptp->phy.eth56g; 2194 params->onestep_ena = false; 2195 params->peer_delay = 0; 2196 params->sfd_ena = false; 2197 params->num_phys = 2; 2198 ptp->ports_per_phy = 4; 2199 ptp->num_lports = params->num_phys * ptp->ports_per_phy; 2200} 2201 2202/* E822 family functions 2203 * 2204 * The following functions operate on the E822 family of devices. 2205 */ 2206 2207/** 2208 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access 2209 * @hw: pointer to the HW struct 2210 * @msg: the PHY message buffer to fill in 2211 * @port: the port to access 2212 * @offset: the register offset 2213 */ 2214static void ice_fill_phy_msg_e82x(struct ice_hw *hw, 2215 struct ice_sbq_msg_input *msg, u8 port, 2216 u16 offset) 2217{ 2218 int phy_port, quadtype; 2219 2220 phy_port = port % hw->ptp.ports_per_phy; 2221 quadtype = ICE_GET_QUAD_NUM(port) % 2222 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); 2223 2224 if (quadtype == 0) { 2225 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 2226 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 2227 } else { 2228 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 2229 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 2230 } 2231 2232 msg->dest_dev = ice_sbq_dev_phy_0; 2233} 2234 2235/** 2236 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register 2237 * @low_addr: the low address to check 2238 * @high_addr: on return, contains the high address of the 64bit register 2239 * 2240 * Checks if the provided low address is one of the known 64bit PHY values 2241 * represented as two 32bit registers. If it is, return the appropriate high 2242 * register offset to use. 2243 */ 2244static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2245{ 2246 switch (low_addr) { 2247 case P_REG_PAR_PCS_TX_OFFSET_L: 2248 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 2249 return true; 2250 case P_REG_PAR_PCS_RX_OFFSET_L: 2251 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 2252 return true; 2253 case P_REG_PAR_TX_TIME_L: 2254 *high_addr = P_REG_PAR_TX_TIME_U; 2255 return true; 2256 case P_REG_PAR_RX_TIME_L: 2257 *high_addr = P_REG_PAR_RX_TIME_U; 2258 return true; 2259 case P_REG_TOTAL_TX_OFFSET_L: 2260 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 2261 return true; 2262 case P_REG_TOTAL_RX_OFFSET_L: 2263 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 2264 return true; 2265 case P_REG_UIX66_10G_40G_L: 2266 *high_addr = P_REG_UIX66_10G_40G_U; 2267 return true; 2268 case P_REG_UIX66_25G_100G_L: 2269 *high_addr = P_REG_UIX66_25G_100G_U; 2270 return true; 2271 case P_REG_TX_CAPTURE_L: 2272 *high_addr = P_REG_TX_CAPTURE_U; 2273 return true; 2274 case P_REG_RX_CAPTURE_L: 2275 *high_addr = P_REG_RX_CAPTURE_U; 2276 return true; 2277 case P_REG_TX_TIMER_INC_PRE_L: 2278 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 2279 return true; 2280 case P_REG_RX_TIMER_INC_PRE_L: 2281 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 2282 return true; 2283 default: 2284 return false; 2285 } 2286} 2287 2288/** 2289 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register 2290 * @low_addr: the low address to check 2291 * @high_addr: on return, contains the high address of the 40bit value 2292 * 2293 * Checks if the provided low address is one of the known 40bit PHY values 2294 * split into two registers with the lower 8 bits in the low register and the 2295 * upper 32 bits in the high register. If it is, return the appropriate high 2296 * register offset to use. 2297 */ 2298static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2299{ 2300 switch (low_addr) { 2301 case P_REG_TIMETUS_L: 2302 *high_addr = P_REG_TIMETUS_U; 2303 return true; 2304 case P_REG_PAR_RX_TUS_L: 2305 *high_addr = P_REG_PAR_RX_TUS_U; 2306 return true; 2307 case P_REG_PAR_TX_TUS_L: 2308 *high_addr = P_REG_PAR_TX_TUS_U; 2309 return true; 2310 case P_REG_PCS_RX_TUS_L: 2311 *high_addr = P_REG_PCS_RX_TUS_U; 2312 return true; 2313 case P_REG_PCS_TX_TUS_L: 2314 *high_addr = P_REG_PCS_TX_TUS_U; 2315 return true; 2316 case P_REG_DESK_PAR_RX_TUS_L: 2317 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 2318 return true; 2319 case P_REG_DESK_PAR_TX_TUS_L: 2320 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 2321 return true; 2322 case P_REG_DESK_PCS_RX_TUS_L: 2323 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 2324 return true; 2325 case P_REG_DESK_PCS_TX_TUS_L: 2326 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 2327 return true; 2328 default: 2329 return false; 2330 } 2331} 2332 2333/** 2334 * ice_read_phy_reg_e82x - Read a PHY register 2335 * @hw: pointer to the HW struct 2336 * @port: PHY port to read from 2337 * @offset: PHY register offset to read 2338 * @val: on return, the contents read from the PHY 2339 * 2340 * Read a PHY register for the given port over the device sideband queue. 2341 */ 2342static int 2343ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 2344{ 2345 struct ice_sbq_msg_input msg = {0}; 2346 int err; 2347 2348 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2349 msg.opcode = ice_sbq_msg_rd; 2350 2351 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2352 if (err) { 2353 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2354 err); 2355 return err; 2356 } 2357 2358 *val = msg.data; 2359 2360 return 0; 2361} 2362 2363/** 2364 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers 2365 * @hw: pointer to the HW struct 2366 * @port: PHY port to read from 2367 * @low_addr: offset of the lower register to read from 2368 * @val: on return, the contents of the 64bit value from the PHY registers 2369 * 2370 * Reads the two registers associated with a 64bit value and returns it in the 2371 * val pointer. The offset always specifies the lower register offset to use. 2372 * The high offset is looked up. This function only operates on registers 2373 * known to be two parts of a 64bit value. 2374 */ 2375static int 2376ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 2377{ 2378 u32 low, high; 2379 u16 high_addr; 2380 int err; 2381 2382 /* Only operate on registers known to be split into two 32bit 2383 * registers. 2384 */ 2385 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2386 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2387 low_addr); 2388 return -EINVAL; 2389 } 2390 2391 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low); 2392 if (err) { 2393 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 2394 low_addr, err); 2395 return err; 2396 } 2397 2398 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high); 2399 if (err) { 2400 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 2401 high_addr, err); 2402 return err; 2403 } 2404 2405 *val = (u64)high << 32 | low; 2406 2407 return 0; 2408} 2409 2410/** 2411 * ice_write_phy_reg_e82x - Write a PHY register 2412 * @hw: pointer to the HW struct 2413 * @port: PHY port to write to 2414 * @offset: PHY register offset to write 2415 * @val: The value to write to the register 2416 * 2417 * Write a PHY register for the given port over the device sideband queue. 2418 */ 2419static int 2420ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val) 2421{ 2422 struct ice_sbq_msg_input msg = {0}; 2423 int err; 2424 2425 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2426 msg.opcode = ice_sbq_msg_wr; 2427 msg.data = val; 2428 2429 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2430 if (err) { 2431 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2432 err); 2433 return err; 2434 } 2435 2436 return 0; 2437} 2438 2439/** 2440 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY 2441 * @hw: pointer to the HW struct 2442 * @port: port to write to 2443 * @low_addr: offset of the low register 2444 * @val: 40b value to write 2445 * 2446 * Write the provided 40b value to the two associated registers by splitting 2447 * it up into two chunks, the lower 8 bits and the upper 32 bits. 2448 */ 2449static int 2450ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 2451{ 2452 u32 low, high; 2453 u16 high_addr; 2454 int err; 2455 2456 /* Only operate on registers known to be split into a lower 8 bit 2457 * register and an upper 32 bit register. 2458 */ 2459 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) { 2460 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 2461 low_addr); 2462 return -EINVAL; 2463 } 2464 low = FIELD_GET(P_REG_40B_LOW_M, val); 2465 high = (u32)(val >> P_REG_40B_HIGH_S); 2466 2467 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 2468 if (err) { 2469 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 2470 low_addr, err); 2471 return err; 2472 } 2473 2474 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 2475 if (err) { 2476 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 2477 high_addr, err); 2478 return err; 2479 } 2480 2481 return 0; 2482} 2483 2484/** 2485 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers 2486 * @hw: pointer to the HW struct 2487 * @port: PHY port to read from 2488 * @low_addr: offset of the lower register to read from 2489 * @val: the contents of the 64bit value to write to PHY 2490 * 2491 * Write the 64bit value to the two associated 32bit PHY registers. The offset 2492 * is always specified as the lower register, and the high address is looked 2493 * up. This function only operates on registers known to be two parts of 2494 * a 64bit value. 2495 */ 2496static int 2497ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 2498{ 2499 u32 low, high; 2500 u16 high_addr; 2501 int err; 2502 2503 /* Only operate on registers known to be split into two 32bit 2504 * registers. 2505 */ 2506 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2507 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2508 low_addr); 2509 return -EINVAL; 2510 } 2511 2512 low = lower_32_bits(val); 2513 high = upper_32_bits(val); 2514 2515 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 2516 if (err) { 2517 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 2518 low_addr, err); 2519 return err; 2520 } 2521 2522 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 2523 if (err) { 2524 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 2525 high_addr, err); 2526 return err; 2527 } 2528 2529 return 0; 2530} 2531 2532/** 2533 * ice_fill_quad_msg_e82x - Fill message data for quad register access 2534 * @hw: pointer to the HW struct 2535 * @msg: the PHY message buffer to fill in 2536 * @quad: the quad to access 2537 * @offset: the register offset 2538 * 2539 * Fill a message buffer for accessing a register in a quad shared between 2540 * multiple PHYs. 2541 * 2542 * Return: 2543 * * %0 - OK 2544 * * %-EINVAL - invalid quad number 2545 */ 2546static int ice_fill_quad_msg_e82x(struct ice_hw *hw, 2547 struct ice_sbq_msg_input *msg, u8 quad, 2548 u16 offset) 2549{ 2550 u32 addr; 2551 2552 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) 2553 return -EINVAL; 2554 2555 msg->dest_dev = ice_sbq_dev_phy_0; 2556 2557 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) 2558 addr = Q_0_BASE + offset; 2559 else 2560 addr = Q_1_BASE + offset; 2561 2562 msg->msg_addr_low = lower_16_bits(addr); 2563 msg->msg_addr_high = upper_16_bits(addr); 2564 2565 return 0; 2566} 2567 2568/** 2569 * ice_read_quad_reg_e82x - Read a PHY quad register 2570 * @hw: pointer to the HW struct 2571 * @quad: quad to read from 2572 * @offset: quad register offset to read 2573 * @val: on return, the contents read from the quad 2574 * 2575 * Read a quad register over the device sideband queue. Quad registers are 2576 * shared between multiple PHYs. 2577 */ 2578int 2579ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 2580{ 2581 struct ice_sbq_msg_input msg = {0}; 2582 int err; 2583 2584 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 2585 if (err) 2586 return err; 2587 2588 msg.opcode = ice_sbq_msg_rd; 2589 2590 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2591 if (err) { 2592 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2593 err); 2594 return err; 2595 } 2596 2597 *val = msg.data; 2598 2599 return 0; 2600} 2601 2602/** 2603 * ice_write_quad_reg_e82x - Write a PHY quad register 2604 * @hw: pointer to the HW struct 2605 * @quad: quad to write to 2606 * @offset: quad register offset to write 2607 * @val: The value to write to the register 2608 * 2609 * Write a quad register over the device sideband queue. Quad registers are 2610 * shared between multiple PHYs. 2611 */ 2612int 2613ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 2614{ 2615 struct ice_sbq_msg_input msg = {0}; 2616 int err; 2617 2618 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 2619 if (err) 2620 return err; 2621 2622 msg.opcode = ice_sbq_msg_wr; 2623 msg.data = val; 2624 2625 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 2626 if (err) { 2627 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2628 err); 2629 return err; 2630 } 2631 2632 return 0; 2633} 2634 2635/** 2636 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block 2637 * @hw: pointer to the HW struct 2638 * @quad: the quad to read from 2639 * @idx: the timestamp index to read 2640 * @tstamp: on return, the 40bit timestamp value 2641 * 2642 * Read a 40bit timestamp value out of the two associated registers in the 2643 * quad memory block that is shared between the internal PHYs of the E822 2644 * family of devices. 2645 */ 2646static int 2647ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 2648{ 2649 u16 lo_addr, hi_addr; 2650 u32 lo, hi; 2651 int err; 2652 2653 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 2654 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 2655 2656 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo); 2657 if (err) { 2658 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 2659 err); 2660 return err; 2661 } 2662 2663 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); 2664 if (err) { 2665 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 2666 err); 2667 return err; 2668 } 2669 2670 /* For E822 based internal PHYs, the timestamp is reported with the 2671 * lower 8 bits in the low register, and the upper 32 bits in the high 2672 * register. 2673 */ 2674 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 2675 FIELD_PREP(PHY_40B_LOW_M, lo); 2676 2677 return 0; 2678} 2679 2680/** 2681 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block 2682 * @hw: pointer to the HW struct 2683 * @quad: the quad to read from 2684 * @idx: the timestamp index to reset 2685 * 2686 * Read the timestamp out of the quad to clear its timestamp status bit from 2687 * the PHY quad block that is shared between the internal PHYs of the E822 2688 * devices. 2689 * 2690 * Note that unlike E810, software cannot directly write to the quad memory 2691 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function 2692 * to determine which timestamps are valid. Reading a timestamp auto-clears 2693 * the valid bit. 2694 * 2695 * To directly clear the contents of the timestamp block entirely, discarding 2696 * all timestamp data at once, software should instead use 2697 * ice_ptp_reset_ts_memory_quad_e82x(). 2698 * 2699 * This function should only be called on an idx whose bit is set according to 2700 * ice_get_phy_tx_tstamp_ready(). 2701 */ 2702static int 2703ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) 2704{ 2705 u64 unused_tstamp; 2706 int err; 2707 2708 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp); 2709 if (err) { 2710 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", 2711 quad, idx, err); 2712 return err; 2713 } 2714 2715 return 0; 2716} 2717 2718/** 2719 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block 2720 * @hw: pointer to the HW struct 2721 * @quad: the quad to read from 2722 * 2723 * Clear all timestamps from the PHY quad block that is shared between the 2724 * internal PHYs on the E822 devices. 2725 */ 2726void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) 2727{ 2728 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); 2729 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); 2730} 2731 2732/** 2733 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks 2734 * @hw: pointer to the HW struct 2735 */ 2736static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw) 2737{ 2738 unsigned int quad; 2739 2740 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) 2741 ice_ptp_reset_ts_memory_quad_e82x(hw, quad); 2742} 2743 2744/** 2745 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 2746 * @hw: pointer to the HW struct 2747 * 2748 * Set the window length used for the vernier port calibration process. 2749 */ 2750static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 2751{ 2752 u8 port; 2753 2754 for (port = 0; port < hw->ptp.num_lports; port++) { 2755 int err; 2756 2757 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL, 2758 PTP_VERNIER_WL); 2759 if (err) { 2760 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 2761 port, err); 2762 return err; 2763 } 2764 } 2765 2766 return 0; 2767} 2768 2769/** 2770 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization 2771 * @hw: pointer to HW struct 2772 * 2773 * Perform PHC initialization steps specific to E822 devices. 2774 */ 2775static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 2776{ 2777 u32 val; 2778 2779 /* Enable reading switch and PHY registers over the sideband queue */ 2780#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 2781#define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 2782 val = rd32(hw, PF_SB_REM_DEV_CTL); 2783 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0); 2784 wr32(hw, PF_SB_REM_DEV_CTL, val); 2785 2786 /* Set window length for all the ports */ 2787 return ice_ptp_set_vernier_wl(hw); 2788} 2789 2790/** 2791 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time 2792 * @hw: pointer to the HW struct 2793 * @time: Time to initialize the PHY port clocks to 2794 * 2795 * Program the PHY port registers with a new initial time value. The port 2796 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 2797 * command. The time value is the upper 32 bits of the PHY timer, usually in 2798 * units of nominal nanoseconds. 2799 */ 2800static int 2801ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time) 2802{ 2803 u64 phy_time; 2804 u8 port; 2805 int err; 2806 2807 /* The time represents the upper 32 bits of the PHY timer, so we need 2808 * to shift to account for this when programming. 2809 */ 2810 phy_time = (u64)time << 32; 2811 2812 for (port = 0; port < hw->ptp.num_lports; port++) { 2813 /* Tx case */ 2814 err = ice_write_64b_phy_reg_e82x(hw, port, 2815 P_REG_TX_TIMER_INC_PRE_L, 2816 phy_time); 2817 if (err) 2818 goto exit_err; 2819 2820 /* Rx case */ 2821 err = ice_write_64b_phy_reg_e82x(hw, port, 2822 P_REG_RX_TIMER_INC_PRE_L, 2823 phy_time); 2824 if (err) 2825 goto exit_err; 2826 } 2827 2828 return 0; 2829 2830exit_err: 2831 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 2832 port, err); 2833 2834 return err; 2835} 2836 2837/** 2838 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust 2839 * @hw: pointer to HW struct 2840 * @port: Port number to be programmed 2841 * @time: time in cycles to adjust the port Tx and Rx clocks 2842 * 2843 * Program the port for an atomic adjustment by writing the Tx and Rx timer 2844 * registers. The atomic adjustment won't be completed until the driver issues 2845 * an ICE_PTP_ADJ_TIME command. 2846 * 2847 * Note that time is not in units of nanoseconds. It is in clock time 2848 * including the lower sub-nanosecond portion of the port timer. 2849 * 2850 * Negative adjustments are supported using 2s complement arithmetic. 2851 */ 2852static int 2853ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time) 2854{ 2855 u32 l_time, u_time; 2856 int err; 2857 2858 l_time = lower_32_bits(time); 2859 u_time = upper_32_bits(time); 2860 2861 /* Tx case */ 2862 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L, 2863 l_time); 2864 if (err) 2865 goto exit_err; 2866 2867 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U, 2868 u_time); 2869 if (err) 2870 goto exit_err; 2871 2872 /* Rx case */ 2873 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L, 2874 l_time); 2875 if (err) 2876 goto exit_err; 2877 2878 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U, 2879 u_time); 2880 if (err) 2881 goto exit_err; 2882 2883 return 0; 2884 2885exit_err: 2886 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 2887 port, err); 2888 return err; 2889} 2890 2891/** 2892 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment 2893 * @hw: pointer to HW struct 2894 * @adj: adjustment in nanoseconds 2895 * 2896 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 2897 * Tx and Rx port registers. The actual adjustment is completed by issuing an 2898 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 2899 */ 2900static int 2901ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj) 2902{ 2903 s64 cycles; 2904 u8 port; 2905 2906 /* The port clock supports adjustment of the sub-nanosecond portion of 2907 * the clock. We shift the provided adjustment in nanoseconds to 2908 * calculate the appropriate adjustment to program into the PHY ports. 2909 */ 2910 if (adj > 0) 2911 cycles = (s64)adj << 32; 2912 else 2913 cycles = -(((s64)-adj) << 32); 2914 2915 for (port = 0; port < hw->ptp.num_lports; port++) { 2916 int err; 2917 2918 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles); 2919 if (err) 2920 return err; 2921 } 2922 2923 return 0; 2924} 2925 2926/** 2927 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment 2928 * @hw: pointer to HW struct 2929 * @incval: new increment value to prepare 2930 * 2931 * Prepare each of the PHY ports for a new increment value by programming the 2932 * port's TIMETUS registers. The new increment value will be updated after 2933 * issuing an ICE_PTP_INIT_INCVAL command. 2934 */ 2935static int 2936ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval) 2937{ 2938 int err; 2939 u8 port; 2940 2941 for (port = 0; port < hw->ptp.num_lports; port++) { 2942 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, 2943 incval); 2944 if (err) 2945 goto exit_err; 2946 } 2947 2948 return 0; 2949 2950exit_err: 2951 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 2952 port, err); 2953 2954 return err; 2955} 2956 2957/** 2958 * ice_ptp_read_port_capture - Read a port's local time capture 2959 * @hw: pointer to HW struct 2960 * @port: Port number to read 2961 * @tx_ts: on return, the Tx port time capture 2962 * @rx_ts: on return, the Rx port time capture 2963 * 2964 * Read the port's Tx and Rx local time capture values. 2965 * 2966 * Note this has no equivalent for the E810 devices. 2967 */ 2968static int 2969ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 2970{ 2971 int err; 2972 2973 /* Tx case */ 2974 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 2975 if (err) { 2976 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 2977 err); 2978 return err; 2979 } 2980 2981 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 2982 (unsigned long long)*tx_ts); 2983 2984 /* Rx case */ 2985 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 2986 if (err) { 2987 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 2988 err); 2989 return err; 2990 } 2991 2992 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 2993 (unsigned long long)*rx_ts); 2994 2995 return 0; 2996} 2997 2998/** 2999 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command 3000 * @hw: pointer to HW struct 3001 * @port: Port to which cmd has to be sent 3002 * @cmd: Command to be sent to the port 3003 * 3004 * Prepare the requested port for an upcoming timer sync command. 3005 * 3006 * Note there is no equivalent of this operation on E810, as that device 3007 * always handles all external PHYs internally. 3008 * 3009 * Return: 3010 * * %0 - success 3011 * * %other - failed to write to PHY 3012 */ 3013static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port, 3014 enum ice_ptp_tmr_cmd cmd) 3015{ 3016 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 3017 int err; 3018 3019 /* Tx case */ 3020 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val); 3021 if (err) { 3022 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 3023 err); 3024 return err; 3025 } 3026 3027 /* Rx case */ 3028 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, 3029 val | TS_CMD_RX_TYPE); 3030 if (err) { 3031 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 3032 err); 3033 return err; 3034 } 3035 3036 return 0; 3037} 3038 3039/* E822 Vernier calibration functions 3040 * 3041 * The following functions are used as part of the vernier calibration of 3042 * a port. This calibration increases the precision of the timestamps on the 3043 * port. 3044 */ 3045 3046/** 3047 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode 3048 * @hw: pointer to HW struct 3049 * @port: the port to read from 3050 * @link_out: if non-NULL, holds link speed on success 3051 * @fec_out: if non-NULL, holds FEC algorithm on success 3052 * 3053 * Read the serdes data for the PHY port and extract the link speed and FEC 3054 * algorithm. 3055 */ 3056static int 3057ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port, 3058 enum ice_ptp_link_spd *link_out, 3059 enum ice_ptp_fec_mode *fec_out) 3060{ 3061 enum ice_ptp_link_spd link; 3062 enum ice_ptp_fec_mode fec; 3063 u32 serdes; 3064 int err; 3065 3066 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes); 3067 if (err) { 3068 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 3069 return err; 3070 } 3071 3072 /* Determine the FEC algorithm */ 3073 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 3074 3075 serdes &= P_REG_LINK_SPEED_SERDES_M; 3076 3077 /* Determine the link speed */ 3078 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 3079 switch (serdes) { 3080 case ICE_PTP_SERDES_25G: 3081 link = ICE_PTP_LNK_SPD_25G_RS; 3082 break; 3083 case ICE_PTP_SERDES_50G: 3084 link = ICE_PTP_LNK_SPD_50G_RS; 3085 break; 3086 case ICE_PTP_SERDES_100G: 3087 link = ICE_PTP_LNK_SPD_100G_RS; 3088 break; 3089 default: 3090 return -EIO; 3091 } 3092 } else { 3093 switch (serdes) { 3094 case ICE_PTP_SERDES_1G: 3095 link = ICE_PTP_LNK_SPD_1G; 3096 break; 3097 case ICE_PTP_SERDES_10G: 3098 link = ICE_PTP_LNK_SPD_10G; 3099 break; 3100 case ICE_PTP_SERDES_25G: 3101 link = ICE_PTP_LNK_SPD_25G; 3102 break; 3103 case ICE_PTP_SERDES_40G: 3104 link = ICE_PTP_LNK_SPD_40G; 3105 break; 3106 case ICE_PTP_SERDES_50G: 3107 link = ICE_PTP_LNK_SPD_50G; 3108 break; 3109 default: 3110 return -EIO; 3111 } 3112 } 3113 3114 if (link_out) 3115 *link_out = link; 3116 if (fec_out) 3117 *fec_out = fec; 3118 3119 return 0; 3120} 3121 3122/** 3123 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp 3124 * @hw: pointer to HW struct 3125 * @port: to configure the quad for 3126 */ 3127static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port) 3128{ 3129 enum ice_ptp_link_spd link_spd; 3130 int err; 3131 u32 val; 3132 u8 quad; 3133 3134 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL); 3135 if (err) { 3136 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 3137 err); 3138 return; 3139 } 3140 3141 quad = ICE_GET_QUAD_NUM(port); 3142 3143 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 3144 if (err) { 3145 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 3146 err); 3147 return; 3148 } 3149 3150 if (link_spd >= ICE_PTP_LNK_SPD_40G) 3151 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3152 else 3153 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3154 3155 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 3156 if (err) { 3157 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 3158 err); 3159 return; 3160 } 3161} 3162 3163/** 3164 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822 3165 * @hw: pointer to the HW structure 3166 * @port: the port to configure 3167 * 3168 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 3169 * hardware clock time units (TUs). That is, determine the number of TUs per 3170 * serdes unit interval, and program the UIX registers with this conversion. 3171 * 3172 * This conversion is used as part of the calibration process when determining 3173 * the additional error of a timestamp vs the real time of transmission or 3174 * receipt of the packet. 3175 * 3176 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 3177 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 3178 * 3179 * To calculate the conversion ratio, we use the following facts: 3180 * 3181 * a) the clock frequency in Hz (cycles per second) 3182 * b) the number of TUs per cycle (the increment value of the clock) 3183 * c) 1 second per 1 billion nanoseconds 3184 * d) the duration of 66 UIs in nanoseconds 3185 * 3186 * Given these facts, we can use the following table to work out what ratios 3187 * to multiply in order to get the number of TUs per 66 UIs: 3188 * 3189 * cycles | 1 second | incval (TUs) | nanoseconds 3190 * -------+--------------+--------------+------------- 3191 * second | 1 billion ns | cycle | 66 UIs 3192 * 3193 * To perform the multiplication using integers without too much loss of 3194 * precision, we can take use the following equation: 3195 * 3196 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 3197 * 3198 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 3199 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 3200 * 3201 * The increment value has a maximum expected range of about 34 bits, while 3202 * the frequency value is about 29 bits. Multiplying these values shouldn't 3203 * overflow the 64 bits. However, we must then further multiply them again by 3204 * the Serdes unit interval duration. To avoid overflow here, we split the 3205 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 3206 * a divide by 390,625,000. This does lose some precision, but avoids 3207 * miscalculation due to arithmetic overflow. 3208 */ 3209static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port) 3210{ 3211 u64 cur_freq, clk_incval, tu_per_sec, uix; 3212 int err; 3213 3214 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3215 clk_incval = ice_ptp_read_src_incval(hw); 3216 3217 /* Calculate TUs per second divided by 256 */ 3218 tu_per_sec = (cur_freq * clk_incval) >> 8; 3219 3220#define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 3221#define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 3222 3223 /* Program the 10Gb/40Gb conversion ratio */ 3224 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 3225 3226 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L, 3227 uix); 3228 if (err) { 3229 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 3230 err); 3231 return err; 3232 } 3233 3234 /* Program the 25Gb/100Gb conversion ratio */ 3235 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 3236 3237 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L, 3238 uix); 3239 if (err) { 3240 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 3241 err); 3242 return err; 3243 } 3244 3245 return 0; 3246} 3247 3248/** 3249 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle 3250 * @hw: pointer to the HW struct 3251 * @port: port to configure 3252 * 3253 * Configure the number of TUs for the PAR and PCS clocks used as part of the 3254 * timestamp calibration process. This depends on the link speed, as the PHY 3255 * uses different markers depending on the speed. 3256 * 3257 * 1Gb/10Gb/25Gb: 3258 * - Tx/Rx PAR/PCS markers 3259 * 3260 * 25Gb RS: 3261 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3262 * 3263 * 40Gb/50Gb: 3264 * - Tx/Rx PAR/PCS markers 3265 * - Rx Deskew PAR/PCS markers 3266 * 3267 * 50G RS and 100GB RS: 3268 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3269 * - Rx Deskew PAR/PCS markers 3270 * - Tx PAR/PCS markers 3271 * 3272 * To calculate the conversion, we use the PHC clock frequency (cycles per 3273 * second), the increment value (TUs per cycle), and the related PHY clock 3274 * frequency to calculate the TUs per unit of the PHY link clock. The 3275 * following table shows how the units convert: 3276 * 3277 * cycles | TUs | second 3278 * -------+-------+-------- 3279 * second | cycle | cycles 3280 * 3281 * For each conversion register, look up the appropriate frequency from the 3282 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 3283 * this to the appropriate register, preparing hardware to perform timestamp 3284 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 3285 * in order to calibrate for the internal PHY delays. 3286 * 3287 * Note that the increment value ranges up to ~34 bits, and the clock 3288 * frequency is ~29 bits, so multiplying them together should fit within the 3289 * 64 bit arithmetic. 3290 */ 3291static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port) 3292{ 3293 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 3294 enum ice_ptp_link_spd link_spd; 3295 enum ice_ptp_fec_mode fec_mode; 3296 int err; 3297 3298 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3299 if (err) 3300 return err; 3301 3302 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3303 clk_incval = ice_ptp_read_src_incval(hw); 3304 3305 /* Calculate TUs per cycle of the PHC clock */ 3306 tu_per_sec = cur_freq * clk_incval; 3307 3308 /* For each PHY conversion register, look up the appropriate link 3309 * speed frequency and determine the TUs per that clock's cycle time. 3310 * Split this into a high and low value and then program the 3311 * appropriate register. If that link speed does not use the 3312 * associated register, write zeros to clear it instead. 3313 */ 3314 3315 /* P_REG_PAR_TX_TUS */ 3316 if (e822_vernier[link_spd].tx_par_clk) 3317 phy_tus = div_u64(tu_per_sec, 3318 e822_vernier[link_spd].tx_par_clk); 3319 else 3320 phy_tus = 0; 3321 3322 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L, 3323 phy_tus); 3324 if (err) 3325 return err; 3326 3327 /* P_REG_PAR_RX_TUS */ 3328 if (e822_vernier[link_spd].rx_par_clk) 3329 phy_tus = div_u64(tu_per_sec, 3330 e822_vernier[link_spd].rx_par_clk); 3331 else 3332 phy_tus = 0; 3333 3334 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L, 3335 phy_tus); 3336 if (err) 3337 return err; 3338 3339 /* P_REG_PCS_TX_TUS */ 3340 if (e822_vernier[link_spd].tx_pcs_clk) 3341 phy_tus = div_u64(tu_per_sec, 3342 e822_vernier[link_spd].tx_pcs_clk); 3343 else 3344 phy_tus = 0; 3345 3346 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L, 3347 phy_tus); 3348 if (err) 3349 return err; 3350 3351 /* P_REG_PCS_RX_TUS */ 3352 if (e822_vernier[link_spd].rx_pcs_clk) 3353 phy_tus = div_u64(tu_per_sec, 3354 e822_vernier[link_spd].rx_pcs_clk); 3355 else 3356 phy_tus = 0; 3357 3358 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L, 3359 phy_tus); 3360 if (err) 3361 return err; 3362 3363 /* P_REG_DESK_PAR_TX_TUS */ 3364 if (e822_vernier[link_spd].tx_desk_rsgb_par) 3365 phy_tus = div_u64(tu_per_sec, 3366 e822_vernier[link_spd].tx_desk_rsgb_par); 3367 else 3368 phy_tus = 0; 3369 3370 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L, 3371 phy_tus); 3372 if (err) 3373 return err; 3374 3375 /* P_REG_DESK_PAR_RX_TUS */ 3376 if (e822_vernier[link_spd].rx_desk_rsgb_par) 3377 phy_tus = div_u64(tu_per_sec, 3378 e822_vernier[link_spd].rx_desk_rsgb_par); 3379 else 3380 phy_tus = 0; 3381 3382 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L, 3383 phy_tus); 3384 if (err) 3385 return err; 3386 3387 /* P_REG_DESK_PCS_TX_TUS */ 3388 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 3389 phy_tus = div_u64(tu_per_sec, 3390 e822_vernier[link_spd].tx_desk_rsgb_pcs); 3391 else 3392 phy_tus = 0; 3393 3394 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L, 3395 phy_tus); 3396 if (err) 3397 return err; 3398 3399 /* P_REG_DESK_PCS_RX_TUS */ 3400 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 3401 phy_tus = div_u64(tu_per_sec, 3402 e822_vernier[link_spd].rx_desk_rsgb_pcs); 3403 else 3404 phy_tus = 0; 3405 3406 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L, 3407 phy_tus); 3408} 3409 3410/** 3411 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port 3412 * @hw: pointer to the HW struct 3413 * @link_spd: the Link speed to calculate for 3414 * 3415 * Calculate the fixed offset due to known static latency data. 3416 */ 3417static u64 3418ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3419{ 3420 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3421 3422 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3423 clk_incval = ice_ptp_read_src_incval(hw); 3424 3425 /* Calculate TUs per second */ 3426 tu_per_sec = cur_freq * clk_incval; 3427 3428 /* Calculate number of TUs to add for the fixed Tx latency. Since the 3429 * latency measurement is in 1/100th of a nanosecond, we need to 3430 * multiply by tu_per_sec and then divide by 1e11. This calculation 3431 * overflows 64 bit integer arithmetic, so break it up into two 3432 * divisions by 1e4 first then by 1e7. 3433 */ 3434 fixed_offset = div_u64(tu_per_sec, 10000); 3435 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 3436 fixed_offset = div_u64(fixed_offset, 10000000); 3437 3438 return fixed_offset; 3439} 3440 3441/** 3442 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset 3443 * @hw: pointer to the HW struct 3444 * @port: the PHY port to configure 3445 * 3446 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to 3447 * adjust Tx timestamps by. This is calculated by combining some known static 3448 * latency along with the Vernier offset computations done by hardware. 3449 * 3450 * This function will not return successfully until the Tx offset calculations 3451 * have been completed, which requires waiting until at least one packet has 3452 * been transmitted by the device. It is safe to call this function 3453 * periodically until calibration succeeds, as it will only program the offset 3454 * once. 3455 * 3456 * To avoid overflow, when calculating the offset based on the known static 3457 * latency values, we use measurements in 1/100th of a nanosecond, and divide 3458 * the TUs per second up front. This avoids overflow while allowing 3459 * calculation of the adjustment using integer arithmetic. 3460 * 3461 * Returns zero on success, -EBUSY if the hardware vernier offset 3462 * calibration has not completed, or another error code on failure. 3463 */ 3464int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port) 3465{ 3466 enum ice_ptp_link_spd link_spd; 3467 enum ice_ptp_fec_mode fec_mode; 3468 u64 total_offset, val; 3469 int err; 3470 u32 reg; 3471 3472 /* Nothing to do if we've already programmed the offset */ 3473 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®); 3474 if (err) { 3475 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", 3476 port, err); 3477 return err; 3478 } 3479 3480 if (reg) 3481 return 0; 3482 3483 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®); 3484 if (err) { 3485 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", 3486 port, err); 3487 return err; 3488 } 3489 3490 if (!(reg & P_REG_TX_OV_STATUS_OV_M)) 3491 return -EBUSY; 3492 3493 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3494 if (err) 3495 return err; 3496 3497 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd); 3498 3499 /* Read the first Vernier offset from the PHY register and add it to 3500 * the total offset. 3501 */ 3502 if (link_spd == ICE_PTP_LNK_SPD_1G || 3503 link_spd == ICE_PTP_LNK_SPD_10G || 3504 link_spd == ICE_PTP_LNK_SPD_25G || 3505 link_spd == ICE_PTP_LNK_SPD_25G_RS || 3506 link_spd == ICE_PTP_LNK_SPD_40G || 3507 link_spd == ICE_PTP_LNK_SPD_50G) { 3508 err = ice_read_64b_phy_reg_e82x(hw, port, 3509 P_REG_PAR_PCS_TX_OFFSET_L, 3510 &val); 3511 if (err) 3512 return err; 3513 3514 total_offset += val; 3515 } 3516 3517 /* For Tx, we only need to use the second Vernier offset for 3518 * multi-lane link speeds with RS-FEC. The lanes will always be 3519 * aligned. 3520 */ 3521 if (link_spd == ICE_PTP_LNK_SPD_50G_RS || 3522 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 3523 err = ice_read_64b_phy_reg_e82x(hw, port, 3524 P_REG_PAR_TX_TIME_L, 3525 &val); 3526 if (err) 3527 return err; 3528 3529 total_offset += val; 3530 } 3531 3532 /* Now that the total offset has been calculated, program it to the 3533 * PHY and indicate that the Tx offset is ready. After this, 3534 * timestamps will be enabled. 3535 */ 3536 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L, 3537 total_offset); 3538 if (err) 3539 return err; 3540 3541 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1); 3542 if (err) 3543 return err; 3544 3545 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n", 3546 port); 3547 3548 return 0; 3549} 3550 3551/** 3552 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx 3553 * @hw: pointer to the HW struct 3554 * @port: the PHY port to adjust for 3555 * @link_spd: the current link speed of the PHY 3556 * @fec_mode: the current FEC mode of the PHY 3557 * @pmd_adj: on return, the amount to adjust the Rx total offset by 3558 * 3559 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. 3560 * This varies by link speed and FEC mode. The value calculated accounts for 3561 * various delays caused when receiving a packet. 3562 */ 3563static int 3564ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port, 3565 enum ice_ptp_link_spd link_spd, 3566 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) 3567{ 3568 u64 cur_freq, clk_incval, tu_per_sec, mult, adj; 3569 u8 pmd_align; 3570 u32 val; 3571 int err; 3572 3573 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val); 3574 if (err) { 3575 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n", 3576 err); 3577 return err; 3578 } 3579 3580 pmd_align = (u8)val; 3581 3582 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3583 clk_incval = ice_ptp_read_src_incval(hw); 3584 3585 /* Calculate TUs per second */ 3586 tu_per_sec = cur_freq * clk_incval; 3587 3588 /* The PMD alignment adjustment measurement depends on the link speed, 3589 * and whether FEC is enabled. For each link speed, the alignment 3590 * adjustment is calculated by dividing a value by the length of 3591 * a Time Unit in nanoseconds. 3592 * 3593 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8 3594 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33) 3595 * 10G w/FEC: align * 0.1 * 32/33 3596 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33) 3597 * 25G w/FEC: align * 0.4 * 32/33 3598 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33) 3599 * 40G w/FEC: align * 0.1 * 32/33 3600 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33) 3601 * 50G w/FEC: align * 0.8 * 32/33 3602 * 3603 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. 3604 * 3605 * To allow for calculating this value using integer arithmetic, we 3606 * instead start with the number of TUs per second, (inverse of the 3607 * length of a Time Unit in nanoseconds), multiply by a value based 3608 * on the PMD alignment register, and then divide by the right value 3609 * calculated based on the table above. To avoid integer overflow this 3610 * division is broken up into a step of dividing by 125 first. 3611 */ 3612 if (link_spd == ICE_PTP_LNK_SPD_1G) { 3613 if (pmd_align == 4) 3614 mult = 10; 3615 else 3616 mult = (pmd_align + 6) % 10; 3617 } else if (link_spd == ICE_PTP_LNK_SPD_10G || 3618 link_spd == ICE_PTP_LNK_SPD_25G || 3619 link_spd == ICE_PTP_LNK_SPD_40G || 3620 link_spd == ICE_PTP_LNK_SPD_50G) { 3621 /* If Clause 74 FEC, always calculate PMD adjust */ 3622 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74) 3623 mult = pmd_align; 3624 else 3625 mult = 0; 3626 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS || 3627 link_spd == ICE_PTP_LNK_SPD_50G_RS || 3628 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 3629 if (pmd_align < 17) 3630 mult = pmd_align + 40; 3631 else 3632 mult = pmd_align; 3633 } else { 3634 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", 3635 link_spd); 3636 mult = 0; 3637 } 3638 3639 /* In some cases, there's no need to adjust for the PMD alignment */ 3640 if (!mult) { 3641 *pmd_adj = 0; 3642 return 0; 3643 } 3644 3645 /* Calculate the adjustment by multiplying TUs per second by the 3646 * appropriate multiplier and divisor. To avoid overflow, we first 3647 * divide by 125, and then handle remaining divisor based on the link 3648 * speed pmd_adj_divisor value. 3649 */ 3650 adj = div_u64(tu_per_sec, 125); 3651 adj *= mult; 3652 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor); 3653 3654 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx 3655 * cycle count is necessary. 3656 */ 3657 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) { 3658 u64 cycle_adj; 3659 u8 rx_cycle; 3660 3661 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT, 3662 &val); 3663 if (err) { 3664 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", 3665 err); 3666 return err; 3667 } 3668 3669 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M; 3670 if (rx_cycle) { 3671 mult = (4 - rx_cycle) * 40; 3672 3673 cycle_adj = div_u64(tu_per_sec, 125); 3674 cycle_adj *= mult; 3675 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 3676 3677 adj += cycle_adj; 3678 } 3679 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) { 3680 u64 cycle_adj; 3681 u8 rx_cycle; 3682 3683 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT, 3684 &val); 3685 if (err) { 3686 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", 3687 err); 3688 return err; 3689 } 3690 3691 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M; 3692 if (rx_cycle) { 3693 mult = rx_cycle * 40; 3694 3695 cycle_adj = div_u64(tu_per_sec, 125); 3696 cycle_adj *= mult; 3697 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 3698 3699 adj += cycle_adj; 3700 } 3701 } 3702 3703 /* Return the calculated adjustment */ 3704 *pmd_adj = adj; 3705 3706 return 0; 3707} 3708 3709/** 3710 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port 3711 * @hw: pointer to HW struct 3712 * @link_spd: The Link speed to calculate for 3713 * 3714 * Determine the fixed Rx latency for a given link speed. 3715 */ 3716static u64 3717ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3718{ 3719 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3720 3721 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3722 clk_incval = ice_ptp_read_src_incval(hw); 3723 3724 /* Calculate TUs per second */ 3725 tu_per_sec = cur_freq * clk_incval; 3726 3727 /* Calculate number of TUs to add for the fixed Rx latency. Since the 3728 * latency measurement is in 1/100th of a nanosecond, we need to 3729 * multiply by tu_per_sec and then divide by 1e11. This calculation 3730 * overflows 64 bit integer arithmetic, so break it up into two 3731 * divisions by 1e4 first then by 1e7. 3732 */ 3733 fixed_offset = div_u64(tu_per_sec, 10000); 3734 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 3735 fixed_offset = div_u64(fixed_offset, 10000000); 3736 3737 return fixed_offset; 3738} 3739 3740/** 3741 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset 3742 * @hw: pointer to the HW struct 3743 * @port: the PHY port to configure 3744 * 3745 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to 3746 * adjust Rx timestamps by. This combines calculations from the Vernier offset 3747 * measurements taken in hardware with some data about known fixed delay as 3748 * well as adjusting for multi-lane alignment delay. 3749 * 3750 * This function will not return successfully until the Rx offset calculations 3751 * have been completed, which requires waiting until at least one packet has 3752 * been received by the device. It is safe to call this function periodically 3753 * until calibration succeeds, as it will only program the offset once. 3754 * 3755 * This function must be called only after the offset registers are valid, 3756 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY 3757 * has measured the offset. 3758 * 3759 * To avoid overflow, when calculating the offset based on the known static 3760 * latency values, we use measurements in 1/100th of a nanosecond, and divide 3761 * the TUs per second up front. This avoids overflow while allowing 3762 * calculation of the adjustment using integer arithmetic. 3763 * 3764 * Returns zero on success, -EBUSY if the hardware vernier offset 3765 * calibration has not completed, or another error code on failure. 3766 */ 3767int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) 3768{ 3769 enum ice_ptp_link_spd link_spd; 3770 enum ice_ptp_fec_mode fec_mode; 3771 u64 total_offset, pmd, val; 3772 int err; 3773 u32 reg; 3774 3775 /* Nothing to do if we've already programmed the offset */ 3776 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®); 3777 if (err) { 3778 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", 3779 port, err); 3780 return err; 3781 } 3782 3783 if (reg) 3784 return 0; 3785 3786 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®); 3787 if (err) { 3788 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", 3789 port, err); 3790 return err; 3791 } 3792 3793 if (!(reg & P_REG_RX_OV_STATUS_OV_M)) 3794 return -EBUSY; 3795 3796 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3797 if (err) 3798 return err; 3799 3800 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd); 3801 3802 /* Read the first Vernier offset from the PHY register and add it to 3803 * the total offset. 3804 */ 3805 err = ice_read_64b_phy_reg_e82x(hw, port, 3806 P_REG_PAR_PCS_RX_OFFSET_L, 3807 &val); 3808 if (err) 3809 return err; 3810 3811 total_offset += val; 3812 3813 /* For Rx, all multi-lane link speeds include a second Vernier 3814 * calibration, because the lanes might not be aligned. 3815 */ 3816 if (link_spd == ICE_PTP_LNK_SPD_40G || 3817 link_spd == ICE_PTP_LNK_SPD_50G || 3818 link_spd == ICE_PTP_LNK_SPD_50G_RS || 3819 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 3820 err = ice_read_64b_phy_reg_e82x(hw, port, 3821 P_REG_PAR_RX_TIME_L, 3822 &val); 3823 if (err) 3824 return err; 3825 3826 total_offset += val; 3827 } 3828 3829 /* In addition, Rx must account for the PMD alignment */ 3830 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd); 3831 if (err) 3832 return err; 3833 3834 /* For RS-FEC, this adjustment adds delay, but for other modes, it 3835 * subtracts delay. 3836 */ 3837 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC) 3838 total_offset += pmd; 3839 else 3840 total_offset -= pmd; 3841 3842 /* Now that the total offset has been calculated, program it to the 3843 * PHY and indicate that the Rx offset is ready. After this, 3844 * timestamps will be enabled. 3845 */ 3846 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L, 3847 total_offset); 3848 if (err) 3849 return err; 3850 3851 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1); 3852 if (err) 3853 return err; 3854 3855 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n", 3856 port); 3857 3858 return 0; 3859} 3860 3861/** 3862 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers 3863 * @hw: pointer to the HW struct 3864 * 3865 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted 3866 * and received timestamps as invalid. 3867 * 3868 * Return: 0 on success, other error codes when failed to write to PHY 3869 */ 3870int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw) 3871{ 3872 u8 port; 3873 3874 for (port = 0; port < hw->ptp.num_lports; port++) { 3875 int err; 3876 3877 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 3878 if (err) { 3879 dev_warn(ice_hw_to_dev(hw), 3880 "Failed to clear PHY TX_OFFSET_READY register\n"); 3881 return err; 3882 } 3883 3884 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 3885 if (err) { 3886 dev_warn(ice_hw_to_dev(hw), 3887 "Failed to clear PHY RX_OFFSET_READY register\n"); 3888 return err; 3889 } 3890 } 3891 3892 return 0; 3893} 3894 3895/** 3896 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time 3897 * @hw: pointer to the HW struct 3898 * @port: the PHY port to read 3899 * @phy_time: on return, the 64bit PHY timer value 3900 * @phc_time: on return, the lower 64bits of PHC time 3901 * 3902 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 3903 * and PHC timer values. 3904 */ 3905static int 3906ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time, 3907 u64 *phc_time) 3908{ 3909 u64 tx_time, rx_time; 3910 u32 zo, lo; 3911 u8 tmr_idx; 3912 int err; 3913 3914 tmr_idx = ice_get_ptp_src_clock_index(hw); 3915 3916 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 3917 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 3918 3919 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 3920 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 3921 if (err) 3922 return err; 3923 3924 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 3925 ice_ptp_exec_tmr_cmd(hw); 3926 3927 /* Read the captured PHC time from the shadow time registers */ 3928 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 3929 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 3930 *phc_time = (u64)lo << 32 | zo; 3931 3932 /* Read the captured PHY time from the PHY shadow registers */ 3933 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 3934 if (err) 3935 return err; 3936 3937 /* If the PHY Tx and Rx timers don't match, log a warning message. 3938 * Note that this should not happen in normal circumstances since the 3939 * driver always programs them together. 3940 */ 3941 if (tx_time != rx_time) 3942 dev_warn(ice_hw_to_dev(hw), 3943 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 3944 port, (unsigned long long)tx_time, 3945 (unsigned long long)rx_time); 3946 3947 *phy_time = tx_time; 3948 3949 return 0; 3950} 3951 3952/** 3953 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer 3954 * @hw: pointer to the HW struct 3955 * @port: the PHY port to synchronize 3956 * 3957 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 3958 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 3959 * simultaneous read of the PHY timer and PHC timer. Then we use the 3960 * difference to calculate an appropriate 2s complement addition to add 3961 * to the PHY timer in order to ensure it reads the same value as the 3962 * primary PHC timer. 3963 */ 3964static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port) 3965{ 3966 u64 phc_time, phy_time, difference; 3967 int err; 3968 3969 if (!ice_ptp_lock(hw)) { 3970 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 3971 return -EBUSY; 3972 } 3973 3974 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 3975 if (err) 3976 goto err_unlock; 3977 3978 /* Calculate the amount required to add to the port time in order for 3979 * it to match the PHC time. 3980 * 3981 * Note that the port adjustment is done using 2s complement 3982 * arithmetic. This is convenient since it means that we can simply 3983 * calculate the difference between the PHC time and the port time, 3984 * and it will be interpreted correctly. 3985 */ 3986 difference = phc_time - phy_time; 3987 3988 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference); 3989 if (err) 3990 goto err_unlock; 3991 3992 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 3993 if (err) 3994 goto err_unlock; 3995 3996 /* Do not perform any action on the main timer */ 3997 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 3998 3999 /* Issue the sync to activate the time adjustment */ 4000 ice_ptp_exec_tmr_cmd(hw); 4001 4002 /* Re-capture the timer values to flush the command registers and 4003 * verify that the time was properly adjusted. 4004 */ 4005 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4006 if (err) 4007 goto err_unlock; 4008 4009 dev_info(ice_hw_to_dev(hw), 4010 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 4011 port, (unsigned long long)phy_time, 4012 (unsigned long long)phc_time); 4013 4014 ice_ptp_unlock(hw); 4015 4016 return 0; 4017 4018err_unlock: 4019 ice_ptp_unlock(hw); 4020 return err; 4021} 4022 4023/** 4024 * ice_stop_phy_timer_e82x - Stop the PHY clock timer 4025 * @hw: pointer to the HW struct 4026 * @port: the PHY port to stop 4027 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 4028 * 4029 * Stop the clock of a PHY port. This must be done as part of the flow to 4030 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4031 * initialized or when link speed changes. 4032 */ 4033int 4034ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset) 4035{ 4036 int err; 4037 u32 val; 4038 4039 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4040 if (err) 4041 return err; 4042 4043 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4044 if (err) 4045 return err; 4046 4047 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4048 if (err) 4049 return err; 4050 4051 val &= ~P_REG_PS_START_M; 4052 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4053 if (err) 4054 return err; 4055 4056 val &= ~P_REG_PS_ENA_CLK_M; 4057 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4058 if (err) 4059 return err; 4060 4061 if (soft_reset) { 4062 val |= P_REG_PS_SFT_RESET_M; 4063 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4064 if (err) 4065 return err; 4066 } 4067 4068 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 4069 4070 return 0; 4071} 4072 4073/** 4074 * ice_start_phy_timer_e82x - Start the PHY clock timer 4075 * @hw: pointer to the HW struct 4076 * @port: the PHY port to start 4077 * 4078 * Start the clock of a PHY port. This must be done as part of the flow to 4079 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4080 * initialized or when link speed changes. 4081 * 4082 * Hardware will take Vernier measurements on Tx or Rx of packets. 4083 */ 4084int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port) 4085{ 4086 u32 lo, hi, val; 4087 u64 incval; 4088 u8 tmr_idx; 4089 int err; 4090 4091 tmr_idx = ice_get_ptp_src_clock_index(hw); 4092 4093 err = ice_stop_phy_timer_e82x(hw, port, false); 4094 if (err) 4095 return err; 4096 4097 ice_phy_cfg_lane_e82x(hw, port); 4098 4099 err = ice_phy_cfg_uix_e82x(hw, port); 4100 if (err) 4101 return err; 4102 4103 err = ice_phy_cfg_parpcs_e82x(hw, port); 4104 if (err) 4105 return err; 4106 4107 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 4108 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 4109 incval = (u64)hi << 32 | lo; 4110 4111 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval); 4112 if (err) 4113 return err; 4114 4115 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4116 if (err) 4117 return err; 4118 4119 /* Do not perform any action on the main timer */ 4120 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4121 4122 ice_ptp_exec_tmr_cmd(hw); 4123 4124 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4125 if (err) 4126 return err; 4127 4128 val |= P_REG_PS_SFT_RESET_M; 4129 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4130 if (err) 4131 return err; 4132 4133 val |= P_REG_PS_START_M; 4134 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4135 if (err) 4136 return err; 4137 4138 val &= ~P_REG_PS_SFT_RESET_M; 4139 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4140 if (err) 4141 return err; 4142 4143 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4144 if (err) 4145 return err; 4146 4147 ice_ptp_exec_tmr_cmd(hw); 4148 4149 val |= P_REG_PS_ENA_CLK_M; 4150 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4151 if (err) 4152 return err; 4153 4154 val |= P_REG_PS_LOAD_OFFSET_M; 4155 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4156 if (err) 4157 return err; 4158 4159 ice_ptp_exec_tmr_cmd(hw); 4160 4161 err = ice_sync_phy_timer_e82x(hw, port); 4162 if (err) 4163 return err; 4164 4165 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 4166 4167 return 0; 4168} 4169 4170/** 4171 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register 4172 * @hw: pointer to the HW struct 4173 * @quad: the timestamp quad to read from 4174 * @tstamp_ready: contents of the Tx memory status register 4175 * 4176 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in 4177 * the PHY are ready. A set bit means the corresponding timestamp is valid and 4178 * ready to be captured from the PHY timestamp block. 4179 */ 4180static int 4181ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 4182{ 4183 u32 hi, lo; 4184 int err; 4185 4186 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); 4187 if (err) { 4188 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", 4189 quad, err); 4190 return err; 4191 } 4192 4193 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); 4194 if (err) { 4195 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", 4196 quad, err); 4197 return err; 4198 } 4199 4200 *tstamp_ready = (u64)hi << 32 | (u64)lo; 4201 4202 return 0; 4203} 4204 4205/** 4206 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt 4207 * @hw: pointer to the HW struct 4208 * @quad: the timestamp quad 4209 * @ena: enable or disable interrupt 4210 * @threshold: interrupt threshold 4211 * 4212 * Configure TX timestamp interrupt for the specified quad 4213 * 4214 * Return: 0 on success, other error codes when failed to read/write quad 4215 */ 4216 4217int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) 4218{ 4219 int err; 4220 u32 val; 4221 4222 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 4223 if (err) 4224 return err; 4225 4226 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4227 if (ena) { 4228 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4229 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 4230 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold); 4231 } 4232 4233 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 4234} 4235 4236/** 4237 * ice_ptp_init_phy_e82x - initialize PHY parameters 4238 * @ptp: pointer to the PTP HW struct 4239 */ 4240static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) 4241{ 4242 ptp->num_lports = 8; 4243 ptp->ports_per_phy = 8; 4244} 4245 4246/* E810 functions 4247 * 4248 * The following functions operate on the E810 series devices which use 4249 * a separate external PHY. 4250 */ 4251 4252/** 4253 * ice_read_phy_reg_e810 - Read register from external PHY on E810 4254 * @hw: pointer to the HW struct 4255 * @addr: the address to read from 4256 * @val: On return, the value read from the PHY 4257 * 4258 * Read a register from the external PHY on the E810 device. 4259 */ 4260static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 4261{ 4262 struct ice_sbq_msg_input msg = {0}; 4263 int err; 4264 4265 msg.msg_addr_low = lower_16_bits(addr); 4266 msg.msg_addr_high = upper_16_bits(addr); 4267 msg.opcode = ice_sbq_msg_rd; 4268 msg.dest_dev = ice_sbq_dev_phy_0; 4269 4270 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 4271 if (err) { 4272 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4273 err); 4274 return err; 4275 } 4276 4277 *val = msg.data; 4278 4279 return 0; 4280} 4281 4282/** 4283 * ice_write_phy_reg_e810 - Write register on external PHY on E810 4284 * @hw: pointer to the HW struct 4285 * @addr: the address to writem to 4286 * @val: the value to write to the PHY 4287 * 4288 * Write a value to a register of the external PHY on the E810 device. 4289 */ 4290static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 4291{ 4292 struct ice_sbq_msg_input msg = {0}; 4293 int err; 4294 4295 msg.msg_addr_low = lower_16_bits(addr); 4296 msg.msg_addr_high = upper_16_bits(addr); 4297 msg.opcode = ice_sbq_msg_wr; 4298 msg.dest_dev = ice_sbq_dev_phy_0; 4299 msg.data = val; 4300 4301 err = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD); 4302 if (err) { 4303 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4304 err); 4305 return err; 4306 } 4307 4308 return 0; 4309} 4310 4311/** 4312 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW 4313 * @hw: pointer to the HW struct 4314 * @idx: the timestamp index to read 4315 * @hi: 8 bit timestamp high value 4316 * @lo: 32 bit timestamp low value 4317 * 4318 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4319 * timestamp block of the external PHY on the E810 device using the low latency 4320 * timestamp read. 4321 */ 4322static int 4323ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 4324{ 4325 struct ice_e810_params *params = &hw->ptp.phy.e810; 4326 unsigned long flags; 4327 u32 val; 4328 int err; 4329 4330 spin_lock_irqsave(¶ms->atqbal_wq.lock, flags); 4331 4332 /* Wait for any pending in-progress low latency interrupt */ 4333 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4334 !(params->atqbal_flags & 4335 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4336 if (err) { 4337 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4338 return err; 4339 } 4340 4341 /* Write TS index to read to the PF register so the FW can read it */ 4342 val = FIELD_PREP(REG_LL_PROXY_H_TS_IDX, idx) | REG_LL_PROXY_H_EXEC; 4343 wr32(hw, REG_LL_PROXY_H, val); 4344 4345 /* Read the register repeatedly until the FW provides us the TS */ 4346 err = read_poll_timeout_atomic(rd32, val, 4347 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 10, 4348 REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4349 REG_LL_PROXY_H); 4350 if (err) { 4351 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); 4352 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4353 return err; 4354 } 4355 4356 /* High 8 bit value of the TS is on the bits 16:23 */ 4357 *hi = FIELD_GET(REG_LL_PROXY_H_TS_HIGH, val); 4358 4359 /* Read the low 32 bit value and set the TS valid bit */ 4360 *lo = rd32(hw, REG_LL_PROXY_L) | TS_VALID; 4361 4362 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4363 4364 return 0; 4365} 4366 4367/** 4368 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq 4369 * @hw: pointer to the HW struct 4370 * @lport: the lport to read from 4371 * @idx: the timestamp index to read 4372 * @hi: 8 bit timestamp high value 4373 * @lo: 32 bit timestamp low value 4374 * 4375 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4376 * timestamp block of the external PHY on the E810 device using sideband queue. 4377 */ 4378static int 4379ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, 4380 u32 *lo) 4381{ 4382 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4383 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4384 u32 lo_val, hi_val; 4385 int err; 4386 4387 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val); 4388 if (err) { 4389 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 4390 err); 4391 return err; 4392 } 4393 4394 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val); 4395 if (err) { 4396 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 4397 err); 4398 return err; 4399 } 4400 4401 *lo = lo_val; 4402 *hi = (u8)hi_val; 4403 4404 return 0; 4405} 4406 4407/** 4408 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 4409 * @hw: pointer to the HW struct 4410 * @lport: the lport to read from 4411 * @idx: the timestamp index to read 4412 * @tstamp: on return, the 40bit timestamp value 4413 * 4414 * Read a 40bit timestamp value out of the timestamp block of the external PHY 4415 * on the E810 device. 4416 */ 4417static int 4418ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 4419{ 4420 u32 lo = 0; 4421 u8 hi = 0; 4422 int err; 4423 4424 if (hw->dev_caps.ts_dev_info.ts_ll_read) 4425 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); 4426 else 4427 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); 4428 4429 if (err) 4430 return err; 4431 4432 /* For E810 devices, the timestamp is reported with the lower 32 bits 4433 * in the low register, and the upper 8 bits in the high register. 4434 */ 4435 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 4436 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 4437 4438 return 0; 4439} 4440 4441/** 4442 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 4443 * @hw: pointer to the HW struct 4444 * @lport: the lport to read from 4445 * @idx: the timestamp index to reset 4446 * 4447 * Read the timestamp and then forcibly overwrite its value to clear the valid 4448 * bit from the timestamp block of the external PHY on the E810 device. 4449 * 4450 * This function should only be called on an idx whose bit is set according to 4451 * ice_get_phy_tx_tstamp_ready(). 4452 */ 4453static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 4454{ 4455 u32 lo_addr, hi_addr; 4456 u64 unused_tstamp; 4457 int err; 4458 4459 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); 4460 if (err) { 4461 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", 4462 lport, idx, err); 4463 return err; 4464 } 4465 4466 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4467 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4468 4469 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 4470 if (err) { 4471 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", 4472 lport, idx, err); 4473 return err; 4474 } 4475 4476 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 4477 if (err) { 4478 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", 4479 lport, idx, err); 4480 return err; 4481 } 4482 4483 return 0; 4484} 4485 4486/** 4487 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 4488 * @hw: pointer to HW struct 4489 * 4490 * Perform E810-specific PTP hardware clock initialization steps. 4491 * 4492 * Return: 0 on success, other error codes when failed to initialize TimeSync 4493 */ 4494static int ice_ptp_init_phc_e810(struct ice_hw *hw) 4495{ 4496 u8 tmr_idx; 4497 int err; 4498 4499 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 4500 4501 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4502 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 4503 GLTSYN_ENA_TSYN_ENA_M); 4504 if (err) 4505 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 4506 err); 4507 4508 return err; 4509} 4510 4511/** 4512 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 4513 * @hw: Board private structure 4514 * @time: Time to initialize the PHY port clock to 4515 * 4516 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 4517 * initial clock time. The time will not actually be programmed until the 4518 * driver issues an ICE_PTP_INIT_TIME command. 4519 * 4520 * The time value is the upper 32 bits of the PHY timer, usually in units of 4521 * nominal nanoseconds. 4522 */ 4523static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 4524{ 4525 u8 tmr_idx; 4526 int err; 4527 4528 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4529 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 4530 if (err) { 4531 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 4532 err); 4533 return err; 4534 } 4535 4536 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 4537 if (err) { 4538 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 4539 err); 4540 return err; 4541 } 4542 4543 return 0; 4544} 4545 4546/** 4547 * ice_ptp_prep_phy_adj_ll_e810 - Prep PHY ports for a time adjustment 4548 * @hw: pointer to HW struct 4549 * @adj: adjustment value to program 4550 * 4551 * Use the low latency firmware interface to program PHY time adjustment to 4552 * all PHY ports. 4553 * 4554 * Return: 0 on success, -EBUSY on timeout 4555 */ 4556static int ice_ptp_prep_phy_adj_ll_e810(struct ice_hw *hw, s32 adj) 4557{ 4558 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4559 struct ice_e810_params *params = &hw->ptp.phy.e810; 4560 u32 val; 4561 int err; 4562 4563 spin_lock_irq(¶ms->atqbal_wq.lock); 4564 4565 /* Wait for any pending in-progress low latency interrupt */ 4566 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4567 !(params->atqbal_flags & 4568 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4569 if (err) { 4570 spin_unlock_irq(¶ms->atqbal_wq.lock); 4571 return err; 4572 } 4573 4574 wr32(hw, REG_LL_PROXY_L, adj); 4575 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_ADJ) | 4576 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 4577 wr32(hw, REG_LL_PROXY_H, val); 4578 4579 /* Read the register repeatedly until the FW indicates completion */ 4580 err = read_poll_timeout_atomic(rd32, val, 4581 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 4582 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4583 REG_LL_PROXY_H); 4584 if (err) { 4585 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n"); 4586 spin_unlock_irq(¶ms->atqbal_wq.lock); 4587 return err; 4588 } 4589 4590 spin_unlock_irq(¶ms->atqbal_wq.lock); 4591 4592 return 0; 4593} 4594 4595/** 4596 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 4597 * @hw: pointer to HW struct 4598 * @adj: adjustment value to program 4599 * 4600 * Prepare the PHY port for an atomic adjustment by programming the PHY 4601 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 4602 * is completed by issuing an ICE_PTP_ADJ_TIME sync command. 4603 * 4604 * The adjustment value only contains the portion used for the upper 32bits of 4605 * the PHY timer, usually in units of nominal nanoseconds. Negative 4606 * adjustments are supported using 2s complement arithmetic. 4607 */ 4608static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 4609{ 4610 u8 tmr_idx; 4611 int err; 4612 4613 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 4614 return ice_ptp_prep_phy_adj_ll_e810(hw, adj); 4615 4616 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4617 4618 /* Adjustments are represented as signed 2's complement values in 4619 * nanoseconds. Sub-nanosecond adjustment is not supported. 4620 */ 4621 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 4622 if (err) { 4623 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 4624 err); 4625 return err; 4626 } 4627 4628 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 4629 if (err) { 4630 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 4631 err); 4632 return err; 4633 } 4634 4635 return 0; 4636} 4637 4638/** 4639 * ice_ptp_prep_phy_incval_ll_e810 - Prep PHY ports increment value change 4640 * @hw: pointer to HW struct 4641 * @incval: The new 40bit increment value to prepare 4642 * 4643 * Use the low latency firmware interface to program PHY time increment value 4644 * for all PHY ports. 4645 * 4646 * Return: 0 on success, -EBUSY on timeout 4647 */ 4648static int ice_ptp_prep_phy_incval_ll_e810(struct ice_hw *hw, u64 incval) 4649{ 4650 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4651 struct ice_e810_params *params = &hw->ptp.phy.e810; 4652 u32 val; 4653 int err; 4654 4655 spin_lock_irq(¶ms->atqbal_wq.lock); 4656 4657 /* Wait for any pending in-progress low latency interrupt */ 4658 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4659 !(params->atqbal_flags & 4660 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4661 if (err) { 4662 spin_unlock_irq(¶ms->atqbal_wq.lock); 4663 return err; 4664 } 4665 4666 wr32(hw, REG_LL_PROXY_L, lower_32_bits(incval)); 4667 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_FREQ) | 4668 FIELD_PREP(REG_LL_PROXY_H_TS_HIGH, (u8)upper_32_bits(incval)) | 4669 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 4670 wr32(hw, REG_LL_PROXY_H, val); 4671 4672 /* Read the register repeatedly until the FW indicates completion */ 4673 err = read_poll_timeout_atomic(rd32, val, 4674 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 4675 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4676 REG_LL_PROXY_H); 4677 if (err) { 4678 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n"); 4679 spin_unlock_irq(¶ms->atqbal_wq.lock); 4680 return err; 4681 } 4682 4683 spin_unlock_irq(¶ms->atqbal_wq.lock); 4684 4685 return 0; 4686} 4687 4688/** 4689 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 4690 * @hw: pointer to HW struct 4691 * @incval: The new 40bit increment value to prepare 4692 * 4693 * Prepare the PHY port for a new increment value by programming the PHY 4694 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 4695 * completed by issuing an ICE_PTP_INIT_INCVAL command. 4696 */ 4697static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 4698{ 4699 u32 high, low; 4700 u8 tmr_idx; 4701 int err; 4702 4703 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 4704 return ice_ptp_prep_phy_incval_ll_e810(hw, incval); 4705 4706 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4707 low = lower_32_bits(incval); 4708 high = upper_32_bits(incval); 4709 4710 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 4711 if (err) { 4712 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 4713 err); 4714 return err; 4715 } 4716 4717 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 4718 if (err) { 4719 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 4720 err); 4721 return err; 4722 } 4723 4724 return 0; 4725} 4726 4727/** 4728 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 4729 * @hw: pointer to HW struct 4730 * @cmd: Command to be sent to the port 4731 * 4732 * Prepare the external PHYs connected to this device for a timer sync 4733 * command. 4734 */ 4735static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 4736{ 4737 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 4738 4739 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val); 4740} 4741 4742/** 4743 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register 4744 * @hw: pointer to the HW struct 4745 * @port: the PHY port to read 4746 * @tstamp_ready: contents of the Tx memory status register 4747 * 4748 * E810 devices do not use a Tx memory status register. Instead simply 4749 * indicate that all timestamps are currently ready. 4750 */ 4751static int 4752ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) 4753{ 4754 *tstamp_ready = 0xFFFFFFFFFFFFFFFF; 4755 return 0; 4756} 4757 4758/* E810 SMA functions 4759 * 4760 * The following functions operate specifically on E810 hardware and are used 4761 * to access the extended GPIOs available. 4762 */ 4763 4764/** 4765 * ice_read_sma_ctrl 4766 * @hw: pointer to the hw struct 4767 * @data: pointer to data to be read from the GPIO controller 4768 * 4769 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 4770 * PCA9575 expander, so only bits 3-7 in data are valid. 4771 */ 4772int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data) 4773{ 4774 int status; 4775 u16 handle; 4776 u8 i; 4777 4778 status = ice_get_pca9575_handle(hw, &handle); 4779 if (status) 4780 return status; 4781 4782 *data = 0; 4783 4784 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 4785 bool pin; 4786 4787 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 4788 &pin, NULL); 4789 if (status) 4790 break; 4791 *data |= (u8)(!pin) << i; 4792 } 4793 4794 return status; 4795} 4796 4797/** 4798 * ice_write_sma_ctrl 4799 * @hw: pointer to the hw struct 4800 * @data: data to be written to the GPIO controller 4801 * 4802 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 4803 * of the PCA9575 expander, so only bits 3-7 in data are valid. 4804 */ 4805int ice_write_sma_ctrl(struct ice_hw *hw, u8 data) 4806{ 4807 int status; 4808 u16 handle; 4809 u8 i; 4810 4811 status = ice_get_pca9575_handle(hw, &handle); 4812 if (status) 4813 return status; 4814 4815 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 4816 bool pin; 4817 4818 pin = !(data & (1 << i)); 4819 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 4820 pin, NULL); 4821 if (status) 4822 break; 4823 } 4824 4825 return status; 4826} 4827 4828/** 4829 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM 4830 * @hw: pointer to the HW struct 4831 * @entries: returns the SDP available connections section from NVM 4832 * @num_entries: returns the number of valid entries 4833 * 4834 * Return: 0 on success, negative error code if NVM read failed or section does 4835 * not exist or is corrupted 4836 */ 4837int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries) 4838{ 4839 __le16 data; 4840 u32 offset; 4841 int err; 4842 4843 err = ice_acquire_nvm(hw, ICE_RES_READ); 4844 if (err) 4845 goto exit; 4846 4847 /* Read the offset of SDP_AC */ 4848 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET; 4849 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 4850 NULL); 4851 if (err) 4852 goto exit; 4853 4854 /* Check if section exist */ 4855 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data)); 4856 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) { 4857 err = -EINVAL; 4858 goto exit; 4859 } 4860 4861 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) { 4862 offset &= ICE_AQC_NVM_SDP_AC_PTR_M; 4863 offset *= ICE_AQC_NVM_SECTOR_UNIT; 4864 } else { 4865 offset *= sizeof(data); 4866 } 4867 4868 /* Skip reading section length and read the number of valid entries */ 4869 offset += sizeof(data); 4870 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 4871 NULL); 4872 if (err) 4873 goto exit; 4874 *num_entries = le16_to_cpu(data); 4875 4876 /* Read SDP configuration section */ 4877 offset += sizeof(data); 4878 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data), 4879 entries, false, true, NULL); 4880 4881exit: 4882 if (err) 4883 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n"); 4884 ice_release_nvm(hw); 4885 return err; 4886} 4887 4888/** 4889 * ice_ptp_init_phy_e810 - initialize PHY parameters 4890 * @ptp: pointer to the PTP HW struct 4891 */ 4892static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) 4893{ 4894 ptp->num_lports = 8; 4895 ptp->ports_per_phy = 4; 4896 4897 init_waitqueue_head(&ptp->phy.e810.atqbal_wq); 4898} 4899 4900/* E830 functions 4901 * 4902 * The following functions operate on the E830 series devices. 4903 * 4904 */ 4905 4906/** 4907 * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization 4908 * @hw: pointer to HW struct 4909 * 4910 * Perform E830-specific PTP hardware clock initialization steps. 4911 */ 4912static void ice_ptp_init_phc_e830(const struct ice_hw *hw) 4913{ 4914 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 4915} 4916 4917/** 4918 * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change 4919 * @hw: pointer to HW struct 4920 * @incval: The new 40bit increment value to prepare 4921 * 4922 * Prepare the PHY port for a new increment value by programming the PHC 4923 * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is 4924 * completed by FW automatically. 4925 */ 4926static void ice_ptp_write_direct_incval_e830(const struct ice_hw *hw, 4927 u64 incval) 4928{ 4929 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4930 4931 wr32(hw, GLTSYN_INCVAL_L(tmr_idx), lower_32_bits(incval)); 4932 wr32(hw, GLTSYN_INCVAL_H(tmr_idx), upper_32_bits(incval)); 4933} 4934 4935/** 4936 * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time 4937 * @hw: Board private structure 4938 * @time: Time to initialize the PHY port clock to 4939 * 4940 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 4941 * initial clock time. The time will not actually be programmed until the 4942 * driver issues an ICE_PTP_INIT_TIME command. 4943 * 4944 * The time value is the upper 32 bits of the PHY timer, usually in units of 4945 * nominal nanoseconds. 4946 */ 4947static void ice_ptp_write_direct_phc_time_e830(const struct ice_hw *hw, 4948 u64 time) 4949{ 4950 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4951 4952 wr32(hw, GLTSYN_TIME_0(tmr_idx), 0); 4953 wr32(hw, GLTSYN_TIME_L(tmr_idx), lower_32_bits(time)); 4954 wr32(hw, GLTSYN_TIME_H(tmr_idx), upper_32_bits(time)); 4955} 4956 4957/** 4958 * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command 4959 * @hw: pointer to HW struct 4960 * @cmd: Command to be sent to the port 4961 * 4962 * Prepare the external PHYs connected to this device for a timer sync 4963 * command. 4964 * 4965 * Return: 0 on success, negative error code when PHY write failed 4966 */ 4967static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 4968{ 4969 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 4970 4971 return ice_write_phy_reg_e810(hw, E830_ETH_GLTSYN_CMD, val); 4972} 4973 4974/** 4975 * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY 4976 * @hw: pointer to the HW struct 4977 * @idx: the timestamp index to read 4978 * @tstamp: on return, the 40bit timestamp value 4979 * 4980 * Read a 40bit timestamp value out of the timestamp block of the external PHY 4981 * on the E830 device. 4982 */ 4983static void ice_read_phy_tstamp_e830(const struct ice_hw *hw, u8 idx, 4984 u64 *tstamp) 4985{ 4986 u32 hi, lo; 4987 4988 hi = rd32(hw, E830_PRTTSYN_TXTIME_H(idx)); 4989 lo = rd32(hw, E830_PRTTSYN_TXTIME_L(idx)); 4990 4991 /* For E830 devices, the timestamp is reported with the lower 32 bits 4992 * in the low register, and the upper 8 bits in the high register. 4993 */ 4994 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 4995 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 4996} 4997 4998/** 4999 * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register 5000 * @hw: pointer to the HW struct 5001 * @port: the PHY port to read 5002 * @tstamp_ready: contents of the Tx memory status register 5003 */ 5004static void ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw *hw, u8 port, 5005 u64 *tstamp_ready) 5006{ 5007 *tstamp_ready = rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_H); 5008 *tstamp_ready <<= 32; 5009 *tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L); 5010} 5011 5012/** 5013 * ice_ptp_init_phy_e830 - initialize PHY parameters 5014 * @ptp: pointer to the PTP HW struct 5015 */ 5016static void ice_ptp_init_phy_e830(struct ice_ptp_hw *ptp) 5017{ 5018 ptp->num_lports = 8; 5019 ptp->ports_per_phy = 4; 5020} 5021 5022/* Device agnostic functions 5023 * 5024 * The following functions implement shared behavior common to all devices, 5025 * possibly calling a device specific implementation where necessary. 5026 */ 5027 5028/** 5029 * ice_ptp_lock - Acquire PTP global semaphore register lock 5030 * @hw: pointer to the HW struct 5031 * 5032 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 5033 * was acquired, false otherwise. 5034 * 5035 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 5036 * value. If software sees the busy bit cleared, this means that this function 5037 * acquired the lock (and the busy bit is now set). If software sees the busy 5038 * bit set, it means that another function acquired the lock. 5039 * 5040 * Software must clear the busy bit with a write to release the lock for other 5041 * functions when done. 5042 */ 5043bool ice_ptp_lock(struct ice_hw *hw) 5044{ 5045 u32 hw_lock; 5046 int i; 5047 5048#define MAX_TRIES 15 5049 5050 for (i = 0; i < MAX_TRIES; i++) { 5051 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 5052 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 5053 if (hw_lock) { 5054 /* Somebody is holding the lock */ 5055 usleep_range(5000, 6000); 5056 continue; 5057 } 5058 5059 break; 5060 } 5061 5062 return !hw_lock; 5063} 5064 5065/** 5066 * ice_ptp_unlock - Release PTP global semaphore register lock 5067 * @hw: pointer to the HW struct 5068 * 5069 * Release the global PTP hardware semaphore lock. This is done by writing to 5070 * the PFTSYN_SEM register. 5071 */ 5072void ice_ptp_unlock(struct ice_hw *hw) 5073{ 5074 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 5075} 5076 5077/** 5078 * ice_ptp_init_hw - Initialize hw based on device type 5079 * @hw: pointer to the HW structure 5080 * 5081 * Determine the PHY model for the device, and initialize hw 5082 * for use by other functions. 5083 */ 5084void ice_ptp_init_hw(struct ice_hw *hw) 5085{ 5086 struct ice_ptp_hw *ptp = &hw->ptp; 5087 5088 switch (hw->mac_type) { 5089 case ICE_MAC_E810: 5090 ice_ptp_init_phy_e810(ptp); 5091 break; 5092 case ICE_MAC_E830: 5093 ice_ptp_init_phy_e830(ptp); 5094 break; 5095 case ICE_MAC_GENERIC: 5096 ice_ptp_init_phy_e82x(ptp); 5097 break; 5098 case ICE_MAC_GENERIC_3K_E825: 5099 ice_ptp_init_phy_e825(hw); 5100 break; 5101 default: 5102 return; 5103 } 5104} 5105 5106/** 5107 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command 5108 * @hw: pointer to HW struct 5109 * @port: Port to which cmd has to be sent 5110 * @cmd: Command to be sent to the port 5111 * 5112 * Prepare one port for the upcoming timer sync command. Do not use this for 5113 * programming only a single port, instead use ice_ptp_one_port_cmd() to 5114 * ensure non-modified ports get properly initialized to ICE_PTP_NOP. 5115 * 5116 * Return: 5117 * * %0 - success 5118 * %-EBUSY - PHY type not supported 5119 * * %other - failed to write port command 5120 */ 5121static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, 5122 enum ice_ptp_tmr_cmd cmd) 5123{ 5124 switch (hw->mac_type) { 5125 case ICE_MAC_GENERIC: 5126 return ice_ptp_write_port_cmd_e82x(hw, port, cmd); 5127 case ICE_MAC_GENERIC_3K_E825: 5128 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd); 5129 default: 5130 return -EOPNOTSUPP; 5131 } 5132} 5133 5134/** 5135 * ice_ptp_one_port_cmd - Program one PHY port for a timer command 5136 * @hw: pointer to HW struct 5137 * @configured_port: the port that should execute the command 5138 * @configured_cmd: the command to be executed on the configured port 5139 * 5140 * Prepare one port for executing a timer command, while preparing all other 5141 * ports to ICE_PTP_NOP. This allows executing a command on a single port 5142 * while ensuring all other ports do not execute stale commands. 5143 * 5144 * Return: 5145 * * %0 - success 5146 * * %other - failed to write port command 5147 */ 5148int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, 5149 enum ice_ptp_tmr_cmd configured_cmd) 5150{ 5151 u32 port; 5152 5153 for (port = 0; port < hw->ptp.num_lports; port++) { 5154 int err; 5155 5156 /* Program the configured port with the configured command, 5157 * program all other ports with ICE_PTP_NOP. 5158 */ 5159 if (port == configured_port) 5160 err = ice_ptp_write_port_cmd(hw, port, configured_cmd); 5161 else 5162 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP); 5163 5164 if (err) 5165 return err; 5166 } 5167 5168 return 0; 5169} 5170 5171/** 5172 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command 5173 * @hw: pointer to HW struct 5174 * @cmd: the timer command to setup 5175 * 5176 * Prepare all PHY ports on this device for the requested timer command. For 5177 * some families this can be done in one shot, but for other families each 5178 * port must be configured individually. 5179 * 5180 * Return: 5181 * * %0 - success 5182 * * %other - failed to write port command 5183 */ 5184static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5185{ 5186 u32 port; 5187 5188 /* PHY models which can program all ports simultaneously */ 5189 switch (hw->mac_type) { 5190 case ICE_MAC_E810: 5191 return ice_ptp_port_cmd_e810(hw, cmd); 5192 case ICE_MAC_E830: 5193 return ice_ptp_port_cmd_e830(hw, cmd); 5194 default: 5195 break; 5196 } 5197 5198 /* PHY models which require programming each port separately */ 5199 for (port = 0; port < hw->ptp.num_lports; port++) { 5200 int err; 5201 5202 err = ice_ptp_write_port_cmd(hw, port, cmd); 5203 if (err) 5204 return err; 5205 } 5206 5207 return 0; 5208} 5209 5210/** 5211 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 5212 * @hw: pointer to HW struct 5213 * @cmd: the command to issue 5214 * 5215 * Prepare the source timer and PHY timers and then trigger the requested 5216 * command. This causes the shadow registers previously written in preparation 5217 * for the command to be synchronously applied to both the source and PHY 5218 * timers. 5219 */ 5220static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5221{ 5222 int err; 5223 5224 /* First, prepare the source timer */ 5225 ice_ptp_src_cmd(hw, cmd); 5226 5227 /* Next, prepare the ports */ 5228 err = ice_ptp_port_cmd(hw, cmd); 5229 if (err) { 5230 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 5231 cmd, err); 5232 return err; 5233 } 5234 5235 /* Write the sync command register to drive both source and PHY timer 5236 * commands synchronously 5237 */ 5238 ice_ptp_exec_tmr_cmd(hw); 5239 5240 return 0; 5241} 5242 5243/** 5244 * ice_ptp_init_time - Initialize device time to provided value 5245 * @hw: pointer to HW struct 5246 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 5247 * 5248 * Initialize the device to the specified time provided. This requires a three 5249 * step process: 5250 * 5251 * 1) write the new init time to the source timer shadow registers 5252 * 2) write the new init time to the PHY timer shadow registers 5253 * 3) issue an init_time timer command to synchronously switch both the source 5254 * and port timers to the new init time value at the next clock cycle. 5255 */ 5256int ice_ptp_init_time(struct ice_hw *hw, u64 time) 5257{ 5258 u8 tmr_idx; 5259 int err; 5260 5261 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5262 5263 /* Source timers */ 5264 /* For E830 we don't need to use shadow registers, its automatic */ 5265 if (hw->mac_type == ICE_MAC_E830) { 5266 ice_ptp_write_direct_phc_time_e830(hw, time); 5267 return 0; 5268 } 5269 5270 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 5271 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 5272 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 5273 5274 /* PHY timers */ 5275 /* Fill Rx and Tx ports and send msg to PHY */ 5276 switch (hw->mac_type) { 5277 case ICE_MAC_E810: 5278 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 5279 break; 5280 case ICE_MAC_GENERIC: 5281 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF); 5282 break; 5283 case ICE_MAC_GENERIC_3K_E825: 5284 err = ice_ptp_prep_phy_time_eth56g(hw, 5285 (u32)(time & 0xFFFFFFFF)); 5286 break; 5287 default: 5288 err = -EOPNOTSUPP; 5289 } 5290 5291 if (err) 5292 return err; 5293 5294 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME); 5295} 5296 5297/** 5298 * ice_ptp_write_incval - Program PHC with new increment value 5299 * @hw: pointer to HW struct 5300 * @incval: Source timer increment value per clock cycle 5301 * 5302 * Program the PHC with a new increment value. This requires a three-step 5303 * process: 5304 * 5305 * 1) Write the increment value to the source timer shadow registers 5306 * 2) Write the increment value to the PHY timer shadow registers 5307 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both 5308 * the source and port timers to the new increment value at the next clock 5309 * cycle. 5310 */ 5311int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 5312{ 5313 u8 tmr_idx; 5314 int err; 5315 5316 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5317 5318 /* For E830 we don't need to use shadow registers, its automatic */ 5319 if (hw->mac_type == ICE_MAC_E830) { 5320 ice_ptp_write_direct_incval_e830(hw, incval); 5321 return 0; 5322 } 5323 5324 /* Shadow Adjust */ 5325 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 5326 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 5327 5328 switch (hw->mac_type) { 5329 case ICE_MAC_E810: 5330 err = ice_ptp_prep_phy_incval_e810(hw, incval); 5331 break; 5332 case ICE_MAC_GENERIC: 5333 err = ice_ptp_prep_phy_incval_e82x(hw, incval); 5334 break; 5335 case ICE_MAC_GENERIC_3K_E825: 5336 err = ice_ptp_prep_phy_incval_eth56g(hw, incval); 5337 break; 5338 default: 5339 err = -EOPNOTSUPP; 5340 } 5341 5342 if (err) 5343 return err; 5344 5345 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL); 5346} 5347 5348/** 5349 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 5350 * @hw: pointer to HW struct 5351 * @incval: Source timer increment value per clock cycle 5352 * 5353 * Program a new PHC incval while holding the PTP semaphore. 5354 */ 5355int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 5356{ 5357 int err; 5358 5359 if (!ice_ptp_lock(hw)) 5360 return -EBUSY; 5361 5362 err = ice_ptp_write_incval(hw, incval); 5363 5364 ice_ptp_unlock(hw); 5365 5366 return err; 5367} 5368 5369/** 5370 * ice_ptp_adj_clock - Adjust PHC clock time atomically 5371 * @hw: pointer to HW struct 5372 * @adj: Adjustment in nanoseconds 5373 * 5374 * Perform an atomic adjustment of the PHC time by the specified number of 5375 * nanoseconds. This requires a three-step process: 5376 * 5377 * 1) Write the adjustment to the source timer shadow registers 5378 * 2) Write the adjustment to the PHY timer shadow registers 5379 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the 5380 * adjustment to both the source and port timers at the next clock cycle. 5381 */ 5382int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 5383{ 5384 u8 tmr_idx; 5385 int err; 5386 5387 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5388 5389 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 5390 * For an ICE_PTP_ADJ_TIME command, this set of registers represents 5391 * the value to add to the clock time. It supports subtraction by 5392 * interpreting the value as a 2's complement integer. 5393 */ 5394 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 5395 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 5396 5397 switch (hw->mac_type) { 5398 case ICE_MAC_E810: 5399 err = ice_ptp_prep_phy_adj_e810(hw, adj); 5400 break; 5401 case ICE_MAC_E830: 5402 /* E830 sync PHYs automatically after setting GLTSYN_SHADJ */ 5403 return 0; 5404 case ICE_MAC_GENERIC: 5405 err = ice_ptp_prep_phy_adj_e82x(hw, adj); 5406 break; 5407 case ICE_MAC_GENERIC_3K_E825: 5408 err = ice_ptp_prep_phy_adj_eth56g(hw, adj); 5409 break; 5410 default: 5411 err = -EOPNOTSUPP; 5412 } 5413 5414 if (err) 5415 return err; 5416 5417 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME); 5418} 5419 5420/** 5421 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 5422 * @hw: pointer to the HW struct 5423 * @block: the block to read from 5424 * @idx: the timestamp index to read 5425 * @tstamp: on return, the 40bit timestamp value 5426 * 5427 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 5428 * the block is the quad to read from. For E810 devices, the block is the 5429 * logical port to read from. 5430 */ 5431int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 5432{ 5433 switch (hw->mac_type) { 5434 case ICE_MAC_E810: 5435 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 5436 case ICE_MAC_E830: 5437 ice_read_phy_tstamp_e830(hw, idx, tstamp); 5438 return 0; 5439 case ICE_MAC_GENERIC: 5440 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp); 5441 case ICE_MAC_GENERIC_3K_E825: 5442 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); 5443 default: 5444 return -EOPNOTSUPP; 5445 } 5446} 5447 5448/** 5449 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 5450 * @hw: pointer to the HW struct 5451 * @block: the block to read from 5452 * @idx: the timestamp index to reset 5453 * 5454 * Clear a timestamp from the timestamp block, discarding its value without 5455 * returning it. This resets the memory status bit for the timestamp index 5456 * allowing it to be reused for another timestamp in the future. 5457 * 5458 * For E822 devices, the block number is the PHY quad to clear from. For E810 5459 * devices, the block number is the logical port to clear from. 5460 * 5461 * This function must only be called on a timestamp index whose valid bit is 5462 * set according to ice_get_phy_tx_tstamp_ready(). 5463 */ 5464int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 5465{ 5466 switch (hw->mac_type) { 5467 case ICE_MAC_E810: 5468 return ice_clear_phy_tstamp_e810(hw, block, idx); 5469 case ICE_MAC_GENERIC: 5470 return ice_clear_phy_tstamp_e82x(hw, block, idx); 5471 case ICE_MAC_GENERIC_3K_E825: 5472 return ice_clear_ptp_tstamp_eth56g(hw, block, idx); 5473 default: 5474 return -EOPNOTSUPP; 5475 } 5476} 5477 5478/** 5479 * ice_get_pf_c827_idx - find and return the C827 index for the current pf 5480 * @hw: pointer to the hw struct 5481 * @idx: index of the found C827 PHY 5482 * Return: 5483 * * 0 - success 5484 * * negative - failure 5485 */ 5486static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) 5487{ 5488 struct ice_aqc_get_link_topo cmd; 5489 u8 node_part_number; 5490 u16 node_handle; 5491 int status; 5492 u8 ctx; 5493 5494 if (hw->mac_type != ICE_MAC_E810) 5495 return -ENODEV; 5496 5497 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { 5498 *idx = C827_0; 5499 return 0; 5500 } 5501 5502 memset(&cmd, 0, sizeof(cmd)); 5503 5504 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S; 5505 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S; 5506 cmd.addr.topo_params.node_type_ctx = ctx; 5507 5508 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 5509 &node_handle); 5510 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 5511 return -ENOENT; 5512 5513 if (node_handle == E810C_QSFP_C827_0_HANDLE) 5514 *idx = C827_0; 5515 else if (node_handle == E810C_QSFP_C827_1_HANDLE) 5516 *idx = C827_1; 5517 else 5518 return -EIO; 5519 5520 return 0; 5521} 5522 5523/** 5524 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks 5525 * @hw: pointer to the HW struct 5526 */ 5527void ice_ptp_reset_ts_memory(struct ice_hw *hw) 5528{ 5529 switch (hw->mac_type) { 5530 case ICE_MAC_GENERIC: 5531 ice_ptp_reset_ts_memory_e82x(hw); 5532 break; 5533 case ICE_MAC_GENERIC_3K_E825: 5534 ice_ptp_reset_ts_memory_eth56g(hw); 5535 break; 5536 case ICE_MAC_E810: 5537 default: 5538 return; 5539 } 5540} 5541 5542/** 5543 * ice_ptp_init_phc - Initialize PTP hardware clock 5544 * @hw: pointer to the HW struct 5545 * 5546 * Perform the steps required to initialize the PTP hardware clock. 5547 */ 5548int ice_ptp_init_phc(struct ice_hw *hw) 5549{ 5550 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5551 5552 /* Enable source clocks */ 5553 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 5554 5555 /* Clear event err indications for auxiliary pins */ 5556 (void)rd32(hw, GLTSYN_STAT(src_idx)); 5557 5558 switch (hw->mac_type) { 5559 case ICE_MAC_E810: 5560 return ice_ptp_init_phc_e810(hw); 5561 case ICE_MAC_E830: 5562 ice_ptp_init_phc_e830(hw); 5563 return 0; 5564 case ICE_MAC_GENERIC: 5565 return ice_ptp_init_phc_e82x(hw); 5566 case ICE_MAC_GENERIC_3K_E825: 5567 return 0; 5568 default: 5569 return -EOPNOTSUPP; 5570 } 5571} 5572 5573/** 5574 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication 5575 * @hw: pointer to the HW struct 5576 * @block: the timestamp block to check 5577 * @tstamp_ready: storage for the PHY Tx memory status information 5578 * 5579 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value 5580 * which indicates which timestamps in the block may be captured. A set bit 5581 * means the timestamp can be read. An unset bit means the timestamp is not 5582 * ready and software should avoid reading the register. 5583 */ 5584int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) 5585{ 5586 switch (hw->mac_type) { 5587 case ICE_MAC_E810: 5588 return ice_get_phy_tx_tstamp_ready_e810(hw, block, 5589 tstamp_ready); 5590 case ICE_MAC_E830: 5591 ice_get_phy_tx_tstamp_ready_e830(hw, block, tstamp_ready); 5592 return 0; 5593 case ICE_MAC_GENERIC: 5594 return ice_get_phy_tx_tstamp_ready_e82x(hw, block, 5595 tstamp_ready); 5596 case ICE_MAC_GENERIC_3K_E825: 5597 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, 5598 tstamp_ready); 5599 default: 5600 return -EOPNOTSUPP; 5601 } 5602} 5603 5604/** 5605 * ice_cgu_get_pin_desc_e823 - get pin description array 5606 * @hw: pointer to the hw struct 5607 * @input: if request is done against input or output pin 5608 * @size: number of inputs/outputs 5609 * 5610 * Return: pointer to pin description array associated to given hw. 5611 */ 5612static const struct ice_cgu_pin_desc * 5613ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size) 5614{ 5615 static const struct ice_cgu_pin_desc *t; 5616 5617 if (hw->cgu_part_number == 5618 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) { 5619 if (input) { 5620 t = ice_e823_zl_cgu_inputs; 5621 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs); 5622 } else { 5623 t = ice_e823_zl_cgu_outputs; 5624 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs); 5625 } 5626 } else if (hw->cgu_part_number == 5627 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) { 5628 if (input) { 5629 t = ice_e823_si_cgu_inputs; 5630 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs); 5631 } else { 5632 t = ice_e823_si_cgu_outputs; 5633 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs); 5634 } 5635 } else { 5636 t = NULL; 5637 *size = 0; 5638 } 5639 5640 return t; 5641} 5642 5643/** 5644 * ice_cgu_get_pin_desc - get pin description array 5645 * @hw: pointer to the hw struct 5646 * @input: if request is done against input or output pins 5647 * @size: size of array returned by function 5648 * 5649 * Return: pointer to pin description array associated to given hw. 5650 */ 5651static const struct ice_cgu_pin_desc * 5652ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size) 5653{ 5654 const struct ice_cgu_pin_desc *t = NULL; 5655 5656 switch (hw->device_id) { 5657 case ICE_DEV_ID_E810C_SFP: 5658 if (input) { 5659 t = ice_e810t_sfp_cgu_inputs; 5660 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs); 5661 } else { 5662 t = ice_e810t_sfp_cgu_outputs; 5663 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs); 5664 } 5665 break; 5666 case ICE_DEV_ID_E810C_QSFP: 5667 if (input) { 5668 t = ice_e810t_qsfp_cgu_inputs; 5669 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs); 5670 } else { 5671 t = ice_e810t_qsfp_cgu_outputs; 5672 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs); 5673 } 5674 break; 5675 case ICE_DEV_ID_E823L_10G_BASE_T: 5676 case ICE_DEV_ID_E823L_1GBE: 5677 case ICE_DEV_ID_E823L_BACKPLANE: 5678 case ICE_DEV_ID_E823L_QSFP: 5679 case ICE_DEV_ID_E823L_SFP: 5680 case ICE_DEV_ID_E823C_10G_BASE_T: 5681 case ICE_DEV_ID_E823C_BACKPLANE: 5682 case ICE_DEV_ID_E823C_QSFP: 5683 case ICE_DEV_ID_E823C_SFP: 5684 case ICE_DEV_ID_E823C_SGMII: 5685 t = ice_cgu_get_pin_desc_e823(hw, input, size); 5686 break; 5687 default: 5688 break; 5689 } 5690 5691 return t; 5692} 5693 5694/** 5695 * ice_cgu_get_num_pins - get pin description array size 5696 * @hw: pointer to the hw struct 5697 * @input: if request is done against input or output pins 5698 * 5699 * Return: size of pin description array for given hw. 5700 */ 5701int ice_cgu_get_num_pins(struct ice_hw *hw, bool input) 5702{ 5703 const struct ice_cgu_pin_desc *t; 5704 int size; 5705 5706 t = ice_cgu_get_pin_desc(hw, input, &size); 5707 if (t) 5708 return size; 5709 5710 return 0; 5711} 5712 5713/** 5714 * ice_cgu_get_pin_type - get pin's type 5715 * @hw: pointer to the hw struct 5716 * @pin: pin index 5717 * @input: if request is done against input or output pin 5718 * 5719 * Return: type of a pin. 5720 */ 5721enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input) 5722{ 5723 const struct ice_cgu_pin_desc *t; 5724 int t_size; 5725 5726 t = ice_cgu_get_pin_desc(hw, input, &t_size); 5727 5728 if (!t) 5729 return 0; 5730 5731 if (pin >= t_size) 5732 return 0; 5733 5734 return t[pin].type; 5735} 5736 5737/** 5738 * ice_cgu_get_pin_freq_supp - get pin's supported frequency 5739 * @hw: pointer to the hw struct 5740 * @pin: pin index 5741 * @input: if request is done against input or output pin 5742 * @num: output number of supported frequencies 5743 * 5744 * Get frequency supported number and array of supported frequencies. 5745 * 5746 * Return: array of supported frequencies for given pin. 5747 */ 5748struct dpll_pin_frequency * 5749ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num) 5750{ 5751 const struct ice_cgu_pin_desc *t; 5752 int t_size; 5753 5754 *num = 0; 5755 t = ice_cgu_get_pin_desc(hw, input, &t_size); 5756 if (!t) 5757 return NULL; 5758 if (pin >= t_size) 5759 return NULL; 5760 *num = t[pin].freq_supp_num; 5761 5762 return t[pin].freq_supp; 5763} 5764 5765/** 5766 * ice_cgu_get_pin_name - get pin's name 5767 * @hw: pointer to the hw struct 5768 * @pin: pin index 5769 * @input: if request is done against input or output pin 5770 * 5771 * Return: 5772 * * null terminated char array with name 5773 * * NULL in case of failure 5774 */ 5775const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input) 5776{ 5777 const struct ice_cgu_pin_desc *t; 5778 int t_size; 5779 5780 t = ice_cgu_get_pin_desc(hw, input, &t_size); 5781 5782 if (!t) 5783 return NULL; 5784 5785 if (pin >= t_size) 5786 return NULL; 5787 5788 return t[pin].name; 5789} 5790 5791/** 5792 * ice_get_cgu_state - get the state of the DPLL 5793 * @hw: pointer to the hw struct 5794 * @dpll_idx: Index of internal DPLL unit 5795 * @last_dpll_state: last known state of DPLL 5796 * @pin: pointer to a buffer for returning currently active pin 5797 * @ref_state: reference clock state 5798 * @eec_mode: eec mode of the DPLL 5799 * @phase_offset: pointer to a buffer for returning phase offset 5800 * @dpll_state: state of the DPLL (output) 5801 * 5802 * This function will read the state of the DPLL(dpll_idx). Non-null 5803 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to 5804 * retrieve currently active pin, state, mode and phase_offset respectively. 5805 * 5806 * Return: state of the DPLL 5807 */ 5808int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, 5809 enum dpll_lock_status last_dpll_state, u8 *pin, 5810 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, 5811 enum dpll_lock_status *dpll_state) 5812{ 5813 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config; 5814 s64 hw_phase_offset; 5815 int status; 5816 5817 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state, 5818 &hw_dpll_state, &hw_config, 5819 &hw_phase_offset, &hw_eec_mode); 5820 if (status) 5821 return status; 5822 5823 if (pin) 5824 /* current ref pin in dpll_state_refsel_status_X register */ 5825 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL; 5826 if (phase_offset) 5827 *phase_offset = hw_phase_offset; 5828 if (ref_state) 5829 *ref_state = hw_ref_state; 5830 if (eec_mode) 5831 *eec_mode = hw_eec_mode; 5832 if (!dpll_state) 5833 return 0; 5834 5835 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ 5836 * it would never return to FREERUN. This aligns to ITU-T G.781 5837 * Recommendation. We cannot report HOLDOVER as HO memory is cleared 5838 * while switching to another reference. 5839 * Only for situations where previous state was either: "LOCKED without 5840 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN. 5841 */ 5842 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) { 5843 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY) 5844 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 5845 else 5846 *dpll_state = DPLL_LOCK_STATUS_LOCKED; 5847 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ || 5848 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) { 5849 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER; 5850 } else { 5851 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED; 5852 } 5853 5854 return 0; 5855} 5856 5857/** 5858 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins 5859 * @hw: pointer to the hw struct 5860 * @base_idx: returns index of first recovered clock pin on device 5861 * @pin_num: returns number of recovered clock pins available on device 5862 * 5863 * Based on hw provide caller info about recovery clock pins available on the 5864 * board. 5865 * 5866 * Return: 5867 * * 0 - success, information is valid 5868 * * negative - failure, information is not valid 5869 */ 5870int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num) 5871{ 5872 u8 phy_idx; 5873 int ret; 5874 5875 switch (hw->device_id) { 5876 case ICE_DEV_ID_E810C_SFP: 5877 case ICE_DEV_ID_E810C_QSFP: 5878 5879 ret = ice_get_pf_c827_idx(hw, &phy_idx); 5880 if (ret) 5881 return ret; 5882 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN); 5883 *pin_num = ICE_E810_RCLK_PINS_NUM; 5884 ret = 0; 5885 break; 5886 case ICE_DEV_ID_E823L_10G_BASE_T: 5887 case ICE_DEV_ID_E823L_1GBE: 5888 case ICE_DEV_ID_E823L_BACKPLANE: 5889 case ICE_DEV_ID_E823L_QSFP: 5890 case ICE_DEV_ID_E823L_SFP: 5891 case ICE_DEV_ID_E823C_10G_BASE_T: 5892 case ICE_DEV_ID_E823C_BACKPLANE: 5893 case ICE_DEV_ID_E823C_QSFP: 5894 case ICE_DEV_ID_E823C_SFP: 5895 case ICE_DEV_ID_E823C_SGMII: 5896 *pin_num = ICE_E82X_RCLK_PINS_NUM; 5897 ret = 0; 5898 if (hw->cgu_part_number == 5899 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) 5900 *base_idx = ZL_REF1P; 5901 else if (hw->cgu_part_number == 5902 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) 5903 *base_idx = SI_REF1P; 5904 else 5905 ret = -ENODEV; 5906 5907 break; 5908 default: 5909 ret = -ENODEV; 5910 break; 5911 } 5912 5913 return ret; 5914} 5915 5916/** 5917 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities 5918 * @hw: pointer to the hw struct 5919 * @pin_id: id of a pin 5920 * @caps: capabilities to modify 5921 * 5922 * Return: 5923 * * 0 - success, state capabilities were modified 5924 * * negative - failure, capabilities were not modified 5925 */ 5926int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, 5927 unsigned long *caps) 5928{ 5929 bool can_change = true; 5930 5931 switch (hw->device_id) { 5932 case ICE_DEV_ID_E810C_SFP: 5933 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3) 5934 can_change = false; 5935 break; 5936 case ICE_DEV_ID_E810C_QSFP: 5937 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4) 5938 can_change = false; 5939 break; 5940 case ICE_DEV_ID_E823L_10G_BASE_T: 5941 case ICE_DEV_ID_E823L_1GBE: 5942 case ICE_DEV_ID_E823L_BACKPLANE: 5943 case ICE_DEV_ID_E823L_QSFP: 5944 case ICE_DEV_ID_E823L_SFP: 5945 case ICE_DEV_ID_E823C_10G_BASE_T: 5946 case ICE_DEV_ID_E823C_BACKPLANE: 5947 case ICE_DEV_ID_E823C_QSFP: 5948 case ICE_DEV_ID_E823C_SFP: 5949 case ICE_DEV_ID_E823C_SGMII: 5950 if (hw->cgu_part_number == 5951 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 && 5952 pin_id == ZL_OUT2) 5953 can_change = false; 5954 else if (hw->cgu_part_number == 5955 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 && 5956 pin_id == SI_OUT1) 5957 can_change = false; 5958 break; 5959 default: 5960 return -EINVAL; 5961 } 5962 if (can_change) 5963 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 5964 else 5965 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 5966 5967 return 0; 5968}
~/
Read-only file preview.