ice_lan_tx_rx.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2018, Intel Corporation. */
  3
  4#ifndef _ICE_LAN_TX_RX_H_
  5#define _ICE_LAN_TX_RX_H_
  6
  7union ice_32byte_rx_desc {
  8	struct {
  9		__le64 pkt_addr; /* Packet buffer address */
 10		__le64 hdr_addr; /* Header buffer address */
 11			/* bit 0 of hdr_addr is DD bit */
 12		__le64 rsvd1;
 13		__le64 rsvd2;
 14	} read;
 15	struct {
 16		struct {
 17			struct {
 18				__le16 mirroring_status;
 19				__le16 l2tag1;
 20			} lo_dword;
 21			union {
 22				__le32 rss; /* RSS Hash */
 23				__le32 fd_id; /* Flow Director filter ID */
 24			} hi_dword;
 25		} qword0;
 26		struct {
 27			/* status/error/PTYPE/length */
 28			__le64 status_error_len;
 29		} qword1;
 30		struct {
 31			__le16 ext_status; /* extended status */
 32			__le16 rsvd;
 33			__le16 l2tag2_1;
 34			__le16 l2tag2_2;
 35		} qword2;
 36		struct {
 37			__le32 reserved;
 38			__le32 fd_id;
 39		} qword3;
 40	} wb; /* writeback */
 41};
 42
 43struct ice_fltr_desc {
 44	__le64 qidx_compq_space_stat;
 45	__le64 dtype_cmd_vsi_fdid;
 46};
 47
 48#define ICE_FXD_FLTR_QW0_QINDEX_S	0
 49#define ICE_FXD_FLTR_QW0_QINDEX_M	(0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S)
 50#define ICE_FXD_FLTR_QW0_COMP_Q_S	11
 51#define ICE_FXD_FLTR_QW0_COMP_Q_M	BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S)
 52#define ICE_FXD_FLTR_QW0_COMP_Q_ZERO	0x0ULL
 53
 54#define ICE_FXD_FLTR_QW0_COMP_REPORT_S	12
 55#define ICE_FXD_FLTR_QW0_COMP_REPORT_M	\
 56				(0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S)
 57#define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL	0x1ULL
 58#define ICE_FXD_FLTR_QW0_COMP_REPORT_SW		0x2ULL
 59
 60#define ICE_FXD_FLTR_QW0_FD_SPACE_S	14
 61#define ICE_FXD_FLTR_QW0_FD_SPACE_M	(0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S)
 62#define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST		0x2ULL
 63
 64#define ICE_FXD_FLTR_QW0_STAT_CNT_S	16
 65#define ICE_FXD_FLTR_QW0_STAT_CNT_M	\
 66				(0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S)
 67#define ICE_FXD_FLTR_QW0_STAT_ENA_S	29
 68#define ICE_FXD_FLTR_QW0_STAT_ENA_M	(0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S)
 69#define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS		0x1ULL
 70
 71#define ICE_FXD_FLTR_QW0_EVICT_ENA_S	31
 72#define ICE_FXD_FLTR_QW0_EVICT_ENA_M	BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S)
 73#define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE	0x0ULL
 74#define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE		0x1ULL
 75
 76#define ICE_FXD_FLTR_QW0_TO_Q_S		32
 77#define ICE_FXD_FLTR_QW0_TO_Q_M		(0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S)
 78#define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX	0x0ULL
 79
 80#define ICE_FXD_FLTR_QW0_TO_Q_PRI_S	35
 81#define ICE_FXD_FLTR_QW0_TO_Q_PRI_M	(0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S)
 82#define ICE_FXD_FLTR_QW0_TO_Q_PRIO1	0x1ULL
 83
 84#define ICE_FXD_FLTR_QW0_DPU_RECIPE_S	38
 85#define ICE_FXD_FLTR_QW0_DPU_RECIPE_M	\
 86			(0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S)
 87#define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT	0x0ULL
 88
 89#define ICE_FXD_FLTR_QW0_DROP_S		40
 90#define ICE_FXD_FLTR_QW0_DROP_M		BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S)
 91#define ICE_FXD_FLTR_QW0_DROP_NO	0x0ULL
 92#define ICE_FXD_FLTR_QW0_DROP_YES	0x1ULL
 93
 94#define ICE_FXD_FLTR_QW0_FLEX_PRI_S	41
 95#define ICE_FXD_FLTR_QW0_FLEX_PRI_M	(0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S)
 96#define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE	0x0ULL
 97
 98#define ICE_FXD_FLTR_QW0_FLEX_MDID_S	44
 99#define ICE_FXD_FLTR_QW0_FLEX_MDID_M	(0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S)
100#define ICE_FXD_FLTR_QW0_FLEX_MDID0	0x0ULL
101
102#define ICE_FXD_FLTR_QW0_FLEX_VAL_S	48
103#define ICE_FXD_FLTR_QW0_FLEX_VAL_M	\
104				(0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S)
105#define ICE_FXD_FLTR_QW0_FLEX_VAL0	0x0ULL
106
107#define ICE_FXD_FLTR_QW1_DTYPE_S	0
108#define ICE_FXD_FLTR_QW1_DTYPE_M	(0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S)
109#define ICE_FXD_FLTR_QW1_PCMD_S		4
110#define ICE_FXD_FLTR_QW1_PCMD_M		BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S)
111#define ICE_FXD_FLTR_QW1_PCMD_ADD	0x0ULL
112#define ICE_FXD_FLTR_QW1_PCMD_REMOVE	0x1ULL
113
114#define ICE_FXD_FLTR_QW1_PROF_PRI_S	5
115#define ICE_FXD_FLTR_QW1_PROF_PRI_M	(0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S)
116#define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO	0x0ULL
117
118#define ICE_FXD_FLTR_QW1_PROF_S		8
119#define ICE_FXD_FLTR_QW1_PROF_M		(0x3FULL << ICE_FXD_FLTR_QW1_PROF_S)
120#define ICE_FXD_FLTR_QW1_PROF_ZERO	0x0ULL
121
122#define ICE_FXD_FLTR_QW1_FD_VSI_S	14
123#define ICE_FXD_FLTR_QW1_FD_VSI_M	(0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S)
124#define ICE_FXD_FLTR_QW1_SWAP_S		24
125#define ICE_FXD_FLTR_QW1_SWAP_M		BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S)
126#define ICE_FXD_FLTR_QW1_SWAP_NOT_SET	0x0ULL
127#define ICE_FXD_FLTR_QW1_SWAP_SET	0x1ULL
128
129#define ICE_FXD_FLTR_QW1_FDID_PRI_S	25
130#define ICE_FXD_FLTR_QW1_FDID_PRI_M	(0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
131#define ICE_FXD_FLTR_QW1_FDID_PRI_ONE	0x1ULL
132#define ICE_FXD_FLTR_QW1_FDID_PRI_THREE	0x3ULL
133
134#define ICE_FXD_FLTR_QW1_FDID_MDID_S	28
135#define ICE_FXD_FLTR_QW1_FDID_MDID_M	(0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)
136#define ICE_FXD_FLTR_QW1_FDID_MDID_FD	0x05ULL
137
138#define ICE_FXD_FLTR_QW1_FDID_S		32
139#define ICE_FXD_FLTR_QW1_FDID_M		\
140			(0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
141#define ICE_FXD_FLTR_QW1_FDID_ZERO	0x0ULL
142
143/* definition for FD filter programming status descriptor WB format */
144#define ICE_FXD_FLTR_WB_QW1_DD_S	0
145#define ICE_FXD_FLTR_WB_QW1_DD_M	(0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S)
146#define ICE_FXD_FLTR_WB_QW1_DD_YES	0x1ULL
147
148#define ICE_FXD_FLTR_WB_QW1_PROG_ID_S	1
149#define ICE_FXD_FLTR_WB_QW1_PROG_ID_M	\
150				(0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S)
151#define ICE_FXD_FLTR_WB_QW1_PROG_ADD	0x0ULL
152#define ICE_FXD_FLTR_WB_QW1_PROG_DEL	0x1ULL
153
154#define ICE_FXD_FLTR_WB_QW1_FAIL_S	4
155#define ICE_FXD_FLTR_WB_QW1_FAIL_M	(0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S)
156#define ICE_FXD_FLTR_WB_QW1_FAIL_YES	0x1ULL
157
158#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S	5
159#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M	\
160				(0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)
161#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES	0x1ULL
162
163/* Rx Flex Descriptor
164 * This descriptor is used instead of the legacy version descriptor when
165 * ice_rlan_ctx.adv_desc is set
166 */
167union ice_32b_rx_flex_desc {
168	struct {
169		__le64 pkt_addr; /* Packet buffer address */
170		__le64 hdr_addr; /* Header buffer address */
171				 /* bit 0 of hdr_addr is DD bit */
172		__le64 rsvd1;
173		__le64 rsvd2;
174	} read;
175	struct {
176		/* Qword 0 */
177		u8 rxdid; /* descriptor builder profile ID */
178		u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
179		__le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
180		__le16 pkt_len; /* [15:14] are reserved */
181		__le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
182						/* sph=[11:11] */
183						/* ff1/ext=[15:12] */
184
185		/* Qword 1 */
186		__le16 status_error0;
187		__le16 l2tag1;
188		__le16 flex_meta0;
189		__le16 flex_meta1;
190
191		/* Qword 2 */
192		__le16 status_error1;
193		u8 flex_flags2;
194		u8 time_stamp_low;
195		__le16 l2tag2_1st;
196		__le16 l2tag2_2nd;
197
198		/* Qword 3 */
199		__le16 flex_meta2;
200		__le16 flex_meta3;
201		union {
202			struct {
203				__le16 flex_meta4;
204				__le16 flex_meta5;
205			} flex;
206			__le32 ts_high;
207		} flex_ts;
208	} wb; /* writeback */
209};
210
211/* Rx Flex Descriptor NIC Profile
212 * This descriptor corresponds to RxDID 2 which contains
213 * metadata fields for RSS, flow ID and timestamp info
214 */
215struct ice_32b_rx_flex_desc_nic {
216	/* Qword 0 */
217	u8 rxdid;
218	u8 mir_id_umb_cast;
219	__le16 ptype_flexi_flags0;
220	__le16 pkt_len;
221	__le16 hdr_len_sph_flex_flags1;
222
223	/* Qword 1 */
224	__le16 status_error0;
225	__le16 l2tag1;
226	__le32 rss_hash;
227
228	/* Qword 2 */
229	__le16 status_error1;
230	u8 flexi_flags2;
231	u8 ts_low;
232	__le16 raw_csum;
233	__le16 l2tag2_2nd;
234
235	/* Qword 3 */
236	__le32 flow_id;
237	union {
238		struct {
239			__le16 vlan_id;
240			__le16 flow_id_ipv6;
241		} flex;
242		__le32 ts_high;
243	} flex_ts;
244};
245
246/* Rx Flex Descriptor NIC Profile
247 * RxDID Profile ID 6
248 * Flex-field 0: RSS hash lower 16-bits
249 * Flex-field 1: RSS hash upper 16-bits
250 * Flex-field 2: Flow ID lower 16-bits
251 * Flex-field 3: Source VSI
252 * Flex-field 4: reserved, VLAN ID taken from L2Tag
253 */
254struct ice_32b_rx_flex_desc_nic_2 {
255	/* Qword 0 */
256	u8 rxdid;
257	u8 mir_id_umb_cast;
258	__le16 ptype_flexi_flags0;
259	__le16 pkt_len;
260	__le16 hdr_len_sph_flex_flags1;
261
262	/* Qword 1 */
263	__le16 status_error0;
264	__le16 l2tag1;
265	__le32 rss_hash;
266
267	/* Qword 2 */
268	__le16 status_error1;
269	u8 flexi_flags2;
270	u8 ts_low;
271	__le16 l2tag2_1st;
272	__le16 l2tag2_2nd;
273
274	/* Qword 3 */
275	__le16 flow_id;
276	__le16 src_vsi;
277	union {
278		struct {
279			__le16 rsvd;
280			__le16 flow_id_ipv6;
281		} flex;
282		__le32 ts_high;
283	} flex_ts;
284};
285
286/* Receive Flex Descriptor profile IDs: There are a total
287 * of 64 profiles where profile IDs 0/1 are for legacy; and
288 * profiles 2-63 are flex profiles that can be programmed
289 * with a specific metadata (profile 7 reserved for HW)
290 */
291enum ice_rxdid {
292	ICE_RXDID_LEGACY_0		= 0,
293	ICE_RXDID_LEGACY_1		= 1,
294	ICE_RXDID_FLEX_NIC		= 2,
295	ICE_RXDID_FLEX_NIC_2		= 6,
296	ICE_RXDID_HW			= 7,
297	ICE_RXDID_LAST			= 63,
298};
299
300/* Receive Flex Descriptor Rx opcode values */
301#define ICE_RX_OPC_MDID		0x01
302
303/* Receive Descriptor MDID values that access packet flags */
304enum ice_flex_mdid_pkt_flags {
305	ICE_RX_MDID_PKT_FLAGS_15_0	= 20,
306	ICE_RX_MDID_PKT_FLAGS_31_16,
307	ICE_RX_MDID_PKT_FLAGS_47_32,
308	ICE_RX_MDID_PKT_FLAGS_63_48,
309};
310
311/* Receive Descriptor MDID values */
312enum ice_flex_rx_mdid {
313	ICE_RX_MDID_FLOW_ID_LOWER	= 5,
314	ICE_RX_MDID_FLOW_ID_HIGH,
315	ICE_RX_MDID_SRC_VSI		= 19,
316	ICE_RX_MDID_HASH_LOW		= 56,
317	ICE_RX_MDID_HASH_HIGH,
318};
319
320/* Rx/Tx Flag64 packet flag bits */
321enum ice_flg64_bits {
322	ICE_FLG_PKT_DSI		= 0,
323	ICE_FLG_EVLAN_x8100	= 14,
324	ICE_FLG_EVLAN_x9100,
325	ICE_FLG_VLAN_x8100,
326	ICE_FLG_TNL_MAC		= 22,
327	ICE_FLG_TNL_VLAN,
328	ICE_FLG_PKT_FRG,
329	ICE_FLG_FIN		= 32,
330	ICE_FLG_SYN,
331	ICE_FLG_RST,
332	ICE_FLG_TNL0		= 38,
333	ICE_FLG_TNL1,
334	ICE_FLG_TNL2,
335	ICE_FLG_UDP_GRE,
336	ICE_FLG_RSVD		= 63
337};
338
339/* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */
340#define ICE_RX_FLEX_DESC_PTYPE_M	(0x3FF) /* 10-bits */
341
342/* for ice_32byte_rx_flex_desc.pkt_length member */
343#define ICE_RX_FLX_DESC_PKT_LEN_M	(0x3FFF) /* 14-bits */
344
345/* ice_32byte_rx_flex_desc::hdr_len_sph_flex_flags1 */
346#define ICE_RX_FLEX_DESC_HDR_LEN_M	GENMASK(10, 0)
347
348enum ice_rx_flex_desc_status_error_0_bits {
349	/* Note: These are predefined bit offsets */
350	ICE_RX_FLEX_DESC_STATUS0_DD_S = 0,
351	ICE_RX_FLEX_DESC_STATUS0_EOF_S,
352	ICE_RX_FLEX_DESC_STATUS0_HBO_S,
353	ICE_RX_FLEX_DESC_STATUS0_L3L4P_S,
354	ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
355	ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
356	ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
357	ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
358	ICE_RX_FLEX_DESC_STATUS0_LPBK_S,
359	ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
360	ICE_RX_FLEX_DESC_STATUS0_RXE_S,
361	ICE_RX_FLEX_DESC_STATUS0_CRCP_S,
362	ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
363	ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
364	ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
365	ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
366	ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
367};
368
369enum ice_rx_flex_desc_status_error_1_bits {
370	/* Note: These are predefined bit offsets */
371	ICE_RX_FLEX_DESC_STATUS1_NAT_S = 4,
372	 /* [10:5] reserved */
373	ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
374	ICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
375};
376
377#define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS	22
378#define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS	5
379#define GLTCLAN_CQ_CNTX(i, CQ)		(GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))
380
381/* RLAN Rx queue context data */
382struct ice_rlan_ctx {
383	u16 head;
384	u8 cpuid;
385#define ICE_RLAN_BASE_S 7
386	u64 base;
387	u16 qlen;
388#define ICE_RLAN_CTX_DBUF_S 7
389	u8 dbuf;
390#define ICE_RLAN_CTX_HBUF_S 6
391	u8 hbuf;
392	u8 dtype;
393	u8 dsize;
394	u8 crcstrip;
395	u8 l2tsel;
396	u8 hsplit_0;
397	u8 hsplit_1;
398	u8 showiv;
399	u16 rxmax;
400	u8 tphrdesc_ena;
401	u8 tphwdesc_ena;
402	u8 tphdata_ena;
403	u8 tphhead_ena;
404	u8 lrxqthresh;
405	u8 prefena;	/* NOTE: normally must be set to 1 at init */
406};
407
408/* for hsplit_0 field of Rx RLAN context */
409enum ice_rlan_ctx_rx_hsplit_0 {
410	ICE_RLAN_RX_HSPLIT_0_NO_SPLIT		= 0,
411	ICE_RLAN_RX_HSPLIT_0_SPLIT_L2		= 1,
412	ICE_RLAN_RX_HSPLIT_0_SPLIT_IP		= 2,
413	ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP	= 4,
414	ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP		= 8,
415};
416
417/* for hsplit_1 field of Rx RLAN context */
418enum ice_rlan_ctx_rx_hsplit_1 {
419	ICE_RLAN_RX_HSPLIT_1_NO_SPLIT		= 0,
420	ICE_RLAN_RX_HSPLIT_1_SPLIT_L2		= 1,
421	ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS	= 2,
422};
423
424/* Tx Descriptor */
425struct ice_tx_desc {
426	__le64 buf_addr; /* Address of descriptor's data buf */
427	__le64 cmd_type_offset_bsz;
428};
429
430enum ice_tx_desc_dtype_value {
431	ICE_TX_DESC_DTYPE_DATA		= 0x0,
432	ICE_TX_DESC_DTYPE_CTX		= 0x1,
433	ICE_TX_DESC_DTYPE_FLTR_PROG	= 0x8,
434	/* DESC_DONE - HW has completed write-back of descriptor */
435	ICE_TX_DESC_DTYPE_DESC_DONE	= 0xF,
436};
437
438#define ICE_TXD_QW1_CMD_S	4
439#define ICE_TXD_QW1_CMD_M	(0xFFFUL << ICE_TXD_QW1_CMD_S)
440
441enum ice_tx_desc_cmd_bits {
442	ICE_TX_DESC_CMD_EOP			= 0x0001,
443	ICE_TX_DESC_CMD_RS			= 0x0002,
444	ICE_TX_DESC_CMD_IL2TAG1			= 0x0008,
445	ICE_TX_DESC_CMD_DUMMY			= 0x0010,
446	ICE_TX_DESC_CMD_IIPT_IPV6		= 0x0020,
447	ICE_TX_DESC_CMD_IIPT_IPV4		= 0x0040,
448	ICE_TX_DESC_CMD_IIPT_IPV4_CSUM		= 0x0060,
449	ICE_TX_DESC_CMD_L4T_EOFT_TCP		= 0x0100,
450	ICE_TX_DESC_CMD_L4T_EOFT_SCTP		= 0x0200,
451	ICE_TX_DESC_CMD_L4T_EOFT_UDP		= 0x0300,
452	ICE_TX_DESC_CMD_RE			= 0x0400,
453};
454
455#define ICE_TXD_QW1_OFFSET_S	16
456#define ICE_TXD_QW1_OFFSET_M	(0x3FFFFULL << ICE_TXD_QW1_OFFSET_S)
457
458enum ice_tx_desc_len_fields {
459	/* Note: These are predefined bit offsets */
460	ICE_TX_DESC_LEN_MACLEN_S	= 0, /* 7 BITS */
461	ICE_TX_DESC_LEN_IPLEN_S	= 7, /* 7 BITS */
462	ICE_TX_DESC_LEN_L4_LEN_S	= 14 /* 4 BITS */
463};
464
465#define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S)
466#define ICE_TXD_QW1_IPLEN_M  (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S)
467#define ICE_TXD_QW1_L4LEN_M  (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S)
468
469/* Tx descriptor field limits in bytes */
470#define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \
471			     ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD)
472#define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \
473			    ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD)
474#define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \
475			    ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD)
476
477#define ICE_TXD_QW1_TX_BUF_SZ_S	34
478#define ICE_TXD_QW1_L2TAG1_S	48
479
480/* Context descriptors */
481struct ice_tx_ctx_desc {
482	__le32 tunneling_params;
483	__le16 l2tag2;
484	__le16 gcs;
485	__le64 qw1;
486};
487
488#define ICE_TX_GCS_DESC_START_M		GENMASK(7, 0)
489#define ICE_TX_GCS_DESC_OFFSET_M	GENMASK(11, 8)
490#define ICE_TX_GCS_DESC_TYPE_M		GENMASK(14, 12)
491#define ICE_TX_GCS_DESC_CSUM_PSH	1
492
493#define ICE_TXD_CTX_QW1_CMD_S	4
494#define ICE_TXD_CTX_QW1_CMD_M	(0x7FUL << ICE_TXD_CTX_QW1_CMD_S)
495
496#define ICE_TXD_CTX_QW1_TSO_LEN_S	30
497#define ICE_TXD_CTX_QW1_TSO_LEN_M	\
498			(0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S)
499
500#define ICE_TXD_CTX_QW1_MSS_S	50
501#define ICE_TXD_CTX_MIN_MSS	64
502
503#define ICE_TXD_CTX_QW1_VSI_S	50
504#define ICE_TXD_CTX_QW1_VSI_M	(0x3FFULL << ICE_TXD_CTX_QW1_VSI_S)
505
506enum ice_tx_ctx_desc_cmd_bits {
507	ICE_TX_CTX_DESC_TSO		= 0x01,
508	ICE_TX_CTX_DESC_TSYN		= 0x02,
509	ICE_TX_CTX_DESC_IL2TAG2		= 0x04,
510	ICE_TX_CTX_DESC_IL2TAG2_IL2H	= 0x08,
511	ICE_TX_CTX_DESC_SWTCH_NOTAG	= 0x00,
512	ICE_TX_CTX_DESC_SWTCH_UPLINK	= 0x10,
513	ICE_TX_CTX_DESC_SWTCH_LOCAL	= 0x20,
514	ICE_TX_CTX_DESC_SWTCH_VSI	= 0x30,
515	ICE_TX_CTX_DESC_RESERVED	= 0x40
516};
517
518enum ice_tx_ctx_desc_eipt_offload {
519	ICE_TX_CTX_EIPT_NONE		= 0x0,
520	ICE_TX_CTX_EIPT_IPV6		= 0x1,
521	ICE_TX_CTX_EIPT_IPV4_NO_CSUM	= 0x2,
522	ICE_TX_CTX_EIPT_IPV4		= 0x3
523};
524
525#define ICE_TXD_CTX_QW0_EIPLEN_S	2
526
527#define ICE_TXD_CTX_QW0_L4TUNT_S	9
528
529#define ICE_TXD_CTX_UDP_TUNNELING	BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S)
530#define ICE_TXD_CTX_GRE_TUNNELING	(0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S)
531
532#define ICE_TXD_CTX_QW0_NATLEN_S	12
533
534#define ICE_TXD_CTX_QW0_L4T_CS_S	23
535#define ICE_TXD_CTX_QW0_L4T_CS_M	BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
536
537#define ICE_LAN_TXQ_MAX_QGRPS	127
538#define ICE_LAN_TXQ_MAX_QDIS	1023
539
540/* Tx queue context data */
541struct ice_tlan_ctx {
542#define ICE_TLAN_CTX_BASE_S	7
543	u64 base;		/* base is defined in 128-byte units */
544	u8 port_num;
545	u8 cgd_num;
546	u8 pf_num;
547	u16 vmvf_num;
548	u8 vmvf_type;
549#define ICE_TLAN_CTX_VMVF_TYPE_VF	0
550#define ICE_TLAN_CTX_VMVF_TYPE_VMQ	1
551#define ICE_TLAN_CTX_VMVF_TYPE_PF	2
552	u16 src_vsi;
553	u8 tsyn_ena;
554	u8 internal_usage_flag;
555	u8 alt_vlan;
556	u8 cpuid;
557	u8 wb_mode;
558	u8 tphrd_desc;
559	u8 tphrd;
560	u8 tphwr_desc;
561	u16 cmpq_id;
562	u16 qnum_in_func;
563	u8 itr_notification_mode;
564	u8 adjust_prof_id;
565	u16 qlen;
566	u8 quanta_prof_idx;
567	u8 tso_ena;
568	u16 tso_qnum;
569	u8 legacy_int;
570	u8 drop_ena;
571	u8 cache_prof_idx;
572	u8 pkt_shaper_prof_idx;
573};
574
575#define ICE_TXTIME_TX_DESC_IDX_M	GENMASK(12, 0)
576#define ICE_TXTIME_STAMP_M		GENMASK(31, 13)
577
578/* Tx time stamp descriptor */
579struct ice_ts_desc {
580	__le32 tx_desc_idx_tstamp;
581};
582
583#define ICE_TS_DESC(R, i) (&(((struct ice_ts_desc *)((R)->desc))[i]))
584
585#define ICE_TXTIME_MAX_QUEUE		2047
586#define ICE_SET_TXTIME_MAX_Q_AMOUNT	127
587#define ICE_TXTIME_FETCH_TS_DESC_DFLT	8
588#define ICE_TXTIME_FETCH_PROFILE_CNT	16
589
590/* Tx Time queue context data */
591struct ice_txtime_ctx {
592#define ICE_TXTIME_CTX_BASE_S		7
593	u64 base;			/* base is defined in 128-byte units */
594	u8 pf_num;
595	u16 vmvf_num;
596	u8 vmvf_type;
597	u16 src_vsi;
598	u8 cpuid;
599	u8 tphrd_desc;
600	u16 qlen;
601	u8 timer_num;
602	u8 txtime_ena_q;
603	u8 drbell_mode_32;
604#define ICE_TXTIME_CTX_DRBELL_MODE_32	1
605	u8 ts_res;
606#define ICE_TXTIME_CTX_RESOLUTION_128NS 7
607	u8 ts_round_type;
608	u8 ts_pacing_slot;
609#define ICE_TXTIME_CTX_FETCH_PROF_ID_0 0
610	u8 merging_ena;
611	u8 ts_fetch_prof_id;
612	u8 ts_fetch_cache_line_aln_thld;
613	u8 tx_pipe_delay_mode;
614};
615
616#endif /* _ICE_LAN_TX_RX_H_ */