ice_dpll.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (C) 2022, Intel Corporation. */
  3
  4#ifndef _ICE_DPLL_H_
  5#define _ICE_DPLL_H_
  6
  7#include "ice.h"
  8
  9#define ICE_DPLL_RCLK_NUM_MAX	4
 10
 11/**
 12 * enum ice_dpll_pin_sw - enumerate ice software pin indices:
 13 * @ICE_DPLL_PIN_SW_1_IDX: index of first SW pin
 14 * @ICE_DPLL_PIN_SW_2_IDX: index of second SW pin
 15 * @ICE_DPLL_PIN_SW_NUM: number of SW pins in pair
 16 */
 17enum ice_dpll_pin_sw {
 18	ICE_DPLL_PIN_SW_1_IDX,
 19	ICE_DPLL_PIN_SW_2_IDX,
 20	ICE_DPLL_PIN_SW_NUM
 21};
 22
 23/** ice_dpll_pin - store info about pins
 24 * @pin: dpll pin structure
 25 * @pf: pointer to pf, which has registered the dpll_pin
 26 * @idx: ice pin private idx
 27 * @num_parents: hols number of parent pins
 28 * @parent_idx: hold indexes of parent pins
 29 * @flags: pin flags returned from HW
 30 * @state: state of a pin
 31 * @prop: pin properties
 32 * @freq: current frequency of a pin
 33 * @phase_adjust: current phase adjust value
 34 * @phase_offset: monitored phase offset value
 35 * @ref_sync: store id of reference sync pin
 36 */
 37struct ice_dpll_pin {
 38	struct dpll_pin *pin;
 39	struct ice_pf *pf;
 40	u8 idx;
 41	u8 num_parents;
 42	u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX];
 43	u8 flags[ICE_DPLL_RCLK_NUM_MAX];
 44	u8 state[ICE_DPLL_RCLK_NUM_MAX];
 45	struct dpll_pin_properties prop;
 46	u32 freq;
 47	s32 phase_adjust;
 48	struct ice_dpll_pin *input;
 49	struct ice_dpll_pin *output;
 50	enum dpll_pin_direction direction;
 51	s64 phase_offset;
 52	u8 status;
 53	u8 ref_sync;
 54	bool active;
 55	bool hidden;
 56};
 57
 58/** ice_dpll - store info required for DPLL control
 59 * @dpll: pointer to dpll dev
 60 * @pf: pointer to pf, which has registered the dpll_device
 61 * @dpll_idx: index of dpll on the NIC
 62 * @input_idx: currently selected input index
 63 * @prev_input_idx: previously selected input index
 64 * @ref_state: state of dpll reference signals
 65 * @eec_mode: eec_mode dpll is configured for
 66 * @phase_offset: phase offset of active pin vs dpll signal
 67 * @prev_phase_offset: previous phase offset of active pin vs dpll signal
 68 * @input_prio: priorities of each input
 69 * @dpll_state: current dpll sync state
 70 * @prev_dpll_state: last dpll sync state
 71 * @phase_offset_monitor_period: period for phase offset monitor read frequency
 72 * @active_input: pointer to active input pin
 73 * @prev_input: pointer to previous active input pin
 74 * @ops: holds the registered ops
 75 */
 76struct ice_dpll {
 77	struct dpll_device *dpll;
 78	struct ice_pf *pf;
 79	u8 dpll_idx;
 80	u8 input_idx;
 81	u8 prev_input_idx;
 82	u8 ref_state;
 83	u8 eec_mode;
 84	s64 phase_offset;
 85	s64 prev_phase_offset;
 86	u8 *input_prio;
 87	enum dpll_lock_status dpll_state;
 88	enum dpll_lock_status prev_dpll_state;
 89	enum dpll_mode mode;
 90	u32 phase_offset_monitor_period;
 91	struct dpll_pin *active_input;
 92	struct dpll_pin *prev_input;
 93	const struct dpll_device_ops *ops;
 94};
 95
 96/** ice_dplls - store info required for CCU (clock controlling unit)
 97 * @kworker: periodic worker
 98 * @work: periodic work
 99 * @lock: locks access to configuration of a dpll
100 * @eec: pointer to EEC dpll dev
101 * @pps: pointer to PPS dpll dev
102 * @inputs: input pins pointer
103 * @outputs: output pins pointer
104 * @rclk: recovered pins pointer
105 * @num_inputs: number of input pins available on dpll
106 * @num_outputs: number of output pins available on dpll
107 * @cgu_state_acq_err_num: number of errors returned during periodic work
108 * @base_rclk_idx: idx of first pin used for clock revocery pins
109 * @clock_id: clock_id of dplls
110 * @input_phase_adj_max: max phase adjust value for an input pins
111 * @output_phase_adj_max: max phase adjust value for an output pins
112 * @periodic_counter: counter of periodic work executions
113 */
114struct ice_dplls {
115	struct kthread_worker *kworker;
116	struct kthread_delayed_work work;
117	struct mutex lock;
118	struct ice_dpll eec;
119	struct ice_dpll pps;
120	struct ice_dpll_pin *inputs;
121	struct ice_dpll_pin *outputs;
122	struct ice_dpll_pin sma[ICE_DPLL_PIN_SW_NUM];
123	struct ice_dpll_pin ufl[ICE_DPLL_PIN_SW_NUM];
124	struct ice_dpll_pin rclk;
125	u8 num_inputs;
126	u8 num_outputs;
127	u8 sma_data;
128	u8 base_rclk_idx;
129	int cgu_state_acq_err_num;
130	u64 clock_id;
131	s32 input_phase_adj_max;
132	s32 output_phase_adj_max;
133	u32 periodic_counter;
134	bool generic;
135};
136
137#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
138void ice_dpll_init(struct ice_pf *pf);
139void ice_dpll_deinit(struct ice_pf *pf);
140#else
141static inline void ice_dpll_init(struct ice_pf *pf) { }
142static inline void ice_dpll_deinit(struct ice_pf *pf) { }
143#endif
144
145#endif