ice_common.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2018, Intel Corporation. */
  3
  4#ifndef _ICE_COMMON_H_
  5#define _ICE_COMMON_H_
  6
  7#include <linux/bitfield.h>
  8
  9#include "ice.h"
 10#include "ice_type.h"
 11#include "ice_nvm.h"
 12#include "ice_flex_pipe.h"
 13#include "ice_parser.h"
 14#include <linux/avf/virtchnl.h>
 15#include "ice_switch.h"
 16#include "ice_fdir.h"
 17
 18#define ICE_SQ_SEND_DELAY_TIME_MS	10
 19#define ICE_SQ_SEND_MAX_EXECUTE		3
 20
 21#define FEC_REG_SHIFT 2
 22#define FEC_RECV_ID_SHIFT 4
 23#define FEC_CORR_LOW_REG_PORT0 (0x02 << FEC_REG_SHIFT)
 24#define FEC_CORR_HIGH_REG_PORT0 (0x03 << FEC_REG_SHIFT)
 25#define FEC_UNCORR_LOW_REG_PORT0 (0x04 << FEC_REG_SHIFT)
 26#define FEC_UNCORR_HIGH_REG_PORT0 (0x05 << FEC_REG_SHIFT)
 27#define FEC_CORR_LOW_REG_PORT1 (0x42 << FEC_REG_SHIFT)
 28#define FEC_CORR_HIGH_REG_PORT1 (0x43 << FEC_REG_SHIFT)
 29#define FEC_UNCORR_LOW_REG_PORT1 (0x44 << FEC_REG_SHIFT)
 30#define FEC_UNCORR_HIGH_REG_PORT1 (0x45 << FEC_REG_SHIFT)
 31#define FEC_CORR_LOW_REG_PORT2 (0x4A << FEC_REG_SHIFT)
 32#define FEC_CORR_HIGH_REG_PORT2 (0x4B << FEC_REG_SHIFT)
 33#define FEC_UNCORR_LOW_REG_PORT2 (0x4C << FEC_REG_SHIFT)
 34#define FEC_UNCORR_HIGH_REG_PORT2 (0x4D << FEC_REG_SHIFT)
 35#define FEC_CORR_LOW_REG_PORT3 (0x52 << FEC_REG_SHIFT)
 36#define FEC_CORR_HIGH_REG_PORT3 (0x53 << FEC_REG_SHIFT)
 37#define FEC_UNCORR_LOW_REG_PORT3 (0x54 << FEC_REG_SHIFT)
 38#define FEC_UNCORR_HIGH_REG_PORT3 (0x55 << FEC_REG_SHIFT)
 39#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)
 40#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)
 41
 42#define ICE_CGU_R9			0x24
 43#define ICE_CGU_R9_TIME_REF_FREQ_SEL	GENMASK(2, 0)
 44#define ICE_CGU_R9_CLK_EREF0_EN		BIT(4)
 45#define ICE_CGU_R9_TIME_REF_EN		BIT(5)
 46#define ICE_CGU_R9_TIME_SYNC_EN		BIT(6)
 47#define ICE_CGU_R9_ONE_PPS_OUT_EN	BIT(7)
 48#define ICE_CGU_R9_ONE_PPS_OUT_AMP	GENMASK(19, 18)
 49
 50#define ICE_CGU_R16			0x40
 51#define ICE_CGU_R16_TSPLL_CK_REFCLKFREQ	GENMASK(31, 24)
 52
 53#define ICE_CGU_R19			0x4C
 54#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X	GENMASK(7, 0)
 55#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825	GENMASK(9, 0)
 56#define ICE_CGU_R19_TSPLL_NDIVRATIO	GENMASK(19, 16)
 57
 58#define ICE_CGU_R22			0x58
 59#define ICE_CGU_R22_TIME1588CLK_DIV	GENMASK(23, 20)
 60#define ICE_CGU_R22_TIME1588CLK_DIV2	BIT(30)
 61
 62#define ICE_CGU_R23			0x5C
 63#define ICE_CGU_R24			0x60
 64#define ICE_CGU_R24_FBDIV_FRAC		GENMASK(21, 0)
 65#define ICE_CGU_R23_R24_TSPLL_ENABLE	BIT(24)
 66#define ICE_CGU_R23_R24_REF1588_CK_DIV	GENMASK(30, 27)
 67#define ICE_CGU_R23_R24_TIME_REF_SEL	BIT(31)
 68
 69#define ICE_CGU_BW_TDC			0x31C
 70#define ICE_CGU_BW_TDC_PLLLOCK_SEL	GENMASK(30, 29)
 71
 72#define ICE_CGU_RO_LOCK			0x3F0
 73#define ICE_CGU_RO_LOCK_TRUE_LOCK	BIT(12)
 74#define ICE_CGU_RO_LOCK_UNLOCK		BIT(13)
 75
 76#define ICE_CGU_CNTR_BIST		0x344
 77#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_0	BIT(15)
 78#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_1	BIT(16)
 79
 80#define ICE_CGU_RO_BWM_LF		0x370
 81#define ICE_CGU_RO_BWM_LF_TRUE_LOCK	BIT(12)
 82
 83int ice_init_hw(struct ice_hw *hw);
 84void ice_deinit_hw(struct ice_hw *hw);
 85int ice_check_reset(struct ice_hw *hw);
 86int ice_reset(struct ice_hw *hw, enum ice_reset_req req);
 87int ice_create_all_ctrlq(struct ice_hw *hw);
 88int ice_init_all_ctrlq(struct ice_hw *hw);
 89void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading);
 90void ice_destroy_all_ctrlq(struct ice_hw *hw);
 91int
 92ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 93		  struct ice_rq_event_info *e, u16 *pending);
 94int
 95ice_get_link_status(struct ice_port_info *pi, bool *link_up);
 96int ice_update_link_info(struct ice_port_info *pi);
 97int
 98ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
 99		enum ice_aq_res_access_type access, u32 timeout);
100void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
101int
102ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
103int
104ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
105int ice_aq_alloc_free_res(struct ice_hw *hw,
106			  struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
107			  enum ice_adminq_opc opc);
108bool ice_is_sbq_supported(struct ice_hw *hw);
109struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw);
110int
111ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
112		struct libie_aq_desc *desc, void *buf, u16 buf_size,
113		struct ice_sq_cd *cd);
114void ice_clear_pxe_mode(struct ice_hw *hw);
115int ice_get_caps(struct ice_hw *hw);
116
117void ice_set_safe_mode_caps(struct ice_hw *hw);
118
119int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
120		      u32 rxq_index);
121int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
122		     u32 rxq_index);
123int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx,
124		     u32 txq_index);
125int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx,
126		      u32 txq_index);
127
128int
129ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params);
130int
131ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params);
132int
133ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
134		   struct ice_aqc_get_set_rss_keys *keys);
135int
136ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
137		   struct ice_aqc_get_set_rss_keys *keys);
138
139bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
140int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
141void ice_fill_dflt_direct_cmd_desc(struct libie_aq_desc *desc, u16 opcode);
142
143void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf);
144
145extern struct mutex ice_global_cfg_lock_sw;
146
147int
148ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc,
149		void *buf, u16 buf_size, struct ice_sq_cd *cd);
150int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
151
152int
153ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
154		       struct ice_sq_cd *cd);
155int
156ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
157		       struct ice_sq_cd *cd);
158int
159ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
160		    struct ice_aqc_get_phy_caps_data *caps,
161		    struct ice_sq_cd *cd);
162bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw);
163bool ice_is_clock_mux_in_netlist(struct ice_hw *hw);
164bool ice_is_cgu_in_netlist(struct ice_hw *hw);
165bool ice_is_gps_in_netlist(struct ice_hw *hw);
166int
167ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
168			u8 *node_part_number, u16 *node_handle);
169int
170ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
171		 enum ice_adminq_opc opc, struct ice_sq_cd *cd);
172int
173ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps);
174void
175ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
176		    u16 link_speeds_bitmap);
177int
178ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
179			struct ice_sq_cd *cd);
180bool ice_is_generic_mac(struct ice_hw *hw);
181int ice_clear_pf_cfg(struct ice_hw *hw);
182int
183ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
184		   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
185bool ice_fw_supports_link_override(struct ice_hw *hw);
186int
187ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
188			      struct ice_port_info *pi);
189bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
190bool ice_is_fw_health_report_supported(struct ice_hw *hw);
191int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source);
192int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
193				u8 serdes_num, int *output);
194int
195ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port,
196		     enum ice_fec_stats_types fec_type, u32 *output);
197
198enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
199enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
200int
201ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
202	   bool ena_auto_link_update);
203int
204ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
205	       enum ice_fc_mode req_mode);
206bool
207ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
208			struct ice_aqc_set_phy_cfg_data *cfg);
209void
210ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
211			 struct ice_aqc_get_phy_caps_data *caps,
212			 struct ice_aqc_set_phy_cfg_data *cfg);
213int
214ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
215		enum ice_fec_mode fec);
216int
217ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
218			   struct ice_sq_cd *cd);
219int
220ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
221int
222ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
223		     struct ice_link_status *link, struct ice_sq_cd *cd);
224int
225ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
226		      struct ice_sq_cd *cd);
227int
228ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
229
230int
231ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
232		       struct ice_sq_cd *cd);
233int
234ice_aq_get_port_options(struct ice_hw *hw,
235			struct ice_aqc_get_port_options_elem *options,
236			u8 *option_count, u8 lport, bool lport_valid,
237			u8 *active_option_idx, bool *active_option_valid,
238			u8 *pending_option_idx, bool *pending_option_valid);
239int
240ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
241		       u8 new_option);
242int ice_get_phy_lane_number(struct ice_hw *hw);
243int
244ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
245		  u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
246		  bool write, struct ice_sq_cd *cd);
247u32 ice_get_link_speed(u16 index);
248
249int
250ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
251		 u16 *max_rdmaqs);
252int
253ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
254		      u16 *rdma_qset, u16 num_qsets, u32 *qset_teid);
255int
256ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
257		      u16 *q_id);
258int
259ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
260		u16 *q_handle, u16 *q_ids, u32 *q_teids,
261		enum ice_disq_rst_src rst_src, u16 vmvf_num,
262		struct ice_sq_cd *cd);
263int
264ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
265		u16 *max_lanqs);
266int
267ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
268		u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
269		struct ice_sq_cd *cd);
270int
271ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
272		   u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
273		   u8 mode, struct ice_sq_cd *cd);
274int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
275void ice_replay_post(struct ice_hw *hw);
276struct ice_q_ctx *
277ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
278int
279ice_aq_set_txtimeq(struct ice_hw *hw, u16 txtimeq, u8 q_count,
280		   struct ice_aqc_set_txtime_qgrp *txtime_qg,
281		   u16 buf_size, struct ice_sq_cd *cd);
282void ice_pack_txtime_ctx(const struct ice_txtime_ctx *ctx,
283			 ice_txtime_ctx_buf_t *buf);
284int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag);
285int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx,
286				     struct ice_cgu_input_measure *meas,
287				     u16 meas_num);
288int
289ice_aq_get_cgu_abilities(struct ice_hw *hw,
290			 struct ice_aqc_get_cgu_abilities *abilities);
291int
292ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,
293			 u32 freq, s32 phase_delay);
294int
295ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type,
296			 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay);
297int
298ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,
299			  u8 src_sel, u32 freq, s32 phase_delay);
300int
301ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags,
302			  u8 *src_sel, u32 *freq, u32 *src_freq);
303int
304ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
305			   u8 *dpll_state, u8 *config, s64 *phase_offset,
306			   u8 *eec_mode);
307int
308ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
309			   u8 config, u8 eec_mode);
310int
311ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
312			u8 ref_priority);
313int
314ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
315			u8 *ref_prio);
316int
317ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,
318		    u32 *cgu_fw_ver);
319
320int
321ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
322			   u32 *freq);
323int
324ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,
325			   u8 *flags, u16 *node_handle);
326int ice_aq_get_sensor_reading(struct ice_hw *hw,
327			      struct ice_aqc_get_sensor_reading_resp *data);
328void
329ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
330		  u64 *prev_stat, u64 *cur_stat);
331void
332ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
333		  u64 *prev_stat, u64 *cur_stat);
334int
335ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
336		     struct ice_aqc_txsched_elem_data *buf);
337int
338ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
339		struct ice_sq_cd *cd);
340int
341ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
342		bool *value, struct ice_sq_cd *cd);
343bool ice_is_100m_speed_supported(struct ice_hw *hw);
344u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high);
345int
346ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
347		    struct ice_sq_cd *cd);
348bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
349int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add);
350int ice_lldp_execute_pending_mib(struct ice_hw *hw);
351int
352ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
353		u16 bus_addr, __le16 addr, u8 params, u8 *data,
354		struct ice_sq_cd *cd);
355int
356ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
357		 u16 bus_addr, __le16 addr, u8 params, const u8 *data,
358		 struct ice_sq_cd *cd);
359int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle);
360int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
361bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
362int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val);
363int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val);
364#endif /* _ICE_COMMON_H_ */