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ice_common.c
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linux-6.19.14/drivers/net/ethernet/intel/ice/ice_common.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2018-2023, Intel Corporation. */ 3 4#include "ice_common.h" 5#include "ice_sched.h" 6#include "ice_adminq_cmd.h" 7#include "ice_flow.h" 8#include "ice_ptp_hw.h" 9#include <linux/packing.h> 10 11#define ICE_PF_RESET_WAIT_COUNT 300 12#define ICE_MAX_NETLIST_SIZE 10 13 14static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79}; 80 81static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87}; 88 89/** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96static void 97ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98{ 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114} 115 116/** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123static int ice_set_mac_type(struct ice_hw *hw) 124{ 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192} 193 194/** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200bool ice_is_generic_mac(struct ice_hw *hw) 201{ 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204} 205 206/** 207 * ice_is_pf_c827 - check if pf contains c827 phy 208 * @hw: pointer to the hw struct 209 * 210 * Return: true if the device has c827 phy. 211 */ 212static bool ice_is_pf_c827(struct ice_hw *hw) 213{ 214 struct ice_aqc_get_link_topo cmd = {}; 215 u8 node_part_number; 216 u16 node_handle; 217 int status; 218 219 if (hw->mac_type != ICE_MAC_E810) 220 return false; 221 222 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) 223 return true; 224 225 cmd.addr.topo_params.node_type_ctx = 226 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) | 227 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT); 228 cmd.addr.topo_params.index = 0; 229 230 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 231 &node_handle); 232 233 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 234 return false; 235 236 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE) 237 return true; 238 239 return false; 240} 241 242/** 243 * ice_clear_pf_cfg - Clear PF configuration 244 * @hw: pointer to the hardware structure 245 * 246 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 247 * configuration, flow director filters, etc.). 248 */ 249int ice_clear_pf_cfg(struct ice_hw *hw) 250{ 251 struct libie_aq_desc desc; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 254 255 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 256} 257 258/** 259 * ice_aq_manage_mac_read - manage MAC address read command 260 * @hw: pointer to the HW struct 261 * @buf: a virtual buffer to hold the manage MAC read response 262 * @buf_size: Size of the virtual buffer 263 * @cd: pointer to command details structure or NULL 264 * 265 * This function is used to return per PF station MAC address (0x0107). 266 * NOTE: Upon successful completion of this command, MAC address information 267 * is returned in user specified buffer. Please interpret user specified 268 * buffer as "manage_mac_read" response. 269 * Response such as various MAC addresses are stored in HW struct (port.mac) 270 * ice_discover_dev_caps is expected to be called before this function is 271 * called. 272 */ 273static int 274ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 275 struct ice_sq_cd *cd) 276{ 277 struct ice_aqc_manage_mac_read_resp *resp; 278 struct ice_aqc_manage_mac_read *cmd; 279 struct libie_aq_desc desc; 280 int status; 281 u16 flags; 282 u8 i; 283 284 cmd = libie_aq_raw(&desc); 285 286 if (buf_size < sizeof(*resp)) 287 return -EINVAL; 288 289 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 290 291 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 292 if (status) 293 return status; 294 295 resp = buf; 296 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 297 298 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 299 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 300 return -EIO; 301 } 302 303 /* A single port can report up to two (LAN and WoL) addresses */ 304 for (i = 0; i < cmd->num_addr; i++) 305 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 306 ether_addr_copy(hw->port_info->mac.lan_addr, 307 resp[i].mac_addr); 308 ether_addr_copy(hw->port_info->mac.perm_addr, 309 resp[i].mac_addr); 310 break; 311 } 312 313 return 0; 314} 315 316/** 317 * ice_aq_get_phy_caps - returns PHY capabilities 318 * @pi: port information structure 319 * @qual_mods: report qualified modules 320 * @report_mode: report mode capabilities 321 * @pcaps: structure for PHY capabilities to be filled 322 * @cd: pointer to command details structure or NULL 323 * 324 * Returns the various PHY capabilities supported on the Port (0x0600) 325 */ 326int 327ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 328 struct ice_aqc_get_phy_caps_data *pcaps, 329 struct ice_sq_cd *cd) 330{ 331 struct ice_aqc_get_phy_caps *cmd; 332 u16 pcaps_size = sizeof(*pcaps); 333 struct libie_aq_desc desc; 334 const char *prefix; 335 struct ice_hw *hw; 336 int status; 337 338 cmd = libie_aq_raw(&desc); 339 340 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 341 return -EINVAL; 342 hw = pi->hw; 343 344 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 345 !ice_fw_supports_report_dflt_cfg(hw)) 346 return -EINVAL; 347 348 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 349 350 if (qual_mods) 351 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 352 353 cmd->param0 |= cpu_to_le16(report_mode); 354 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 355 356 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 357 358 switch (report_mode) { 359 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 360 prefix = "phy_caps_media"; 361 break; 362 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 363 prefix = "phy_caps_no_media"; 364 break; 365 case ICE_AQC_REPORT_ACTIVE_CFG: 366 prefix = "phy_caps_active"; 367 break; 368 case ICE_AQC_REPORT_DFLT_CFG: 369 prefix = "phy_caps_default"; 370 break; 371 default: 372 prefix = "phy_caps_invalid"; 373 } 374 375 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 376 le64_to_cpu(pcaps->phy_type_high), prefix); 377 378 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 379 prefix, report_mode); 380 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 381 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 382 pcaps->low_power_ctrl_an); 383 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 384 pcaps->eee_cap); 385 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 386 pcaps->eeer_value); 387 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 388 pcaps->link_fec_options); 389 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 390 prefix, pcaps->module_compliance_enforcement); 391 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 392 prefix, pcaps->extended_compliance_code); 393 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 394 pcaps->module_type[0]); 395 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 396 pcaps->module_type[1]); 397 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 398 pcaps->module_type[2]); 399 400 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 401 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 402 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 403 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 404 sizeof(pi->phy.link_info.module_type)); 405 } 406 407 return status; 408} 409 410/** 411 * ice_aq_get_link_topo_handle - get link topology node return status 412 * @pi: port information structure 413 * @node_type: requested node type 414 * @cd: pointer to command details structure or NULL 415 * 416 * Get link topology node return status for specified node type (0x06E0) 417 * 418 * Node type cage can be used to determine if cage is present. If AQC 419 * returns error (ENOENT), then no cage present. If no cage present, then 420 * connection type is backplane or BASE-T. 421 */ 422static int 423ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 424 struct ice_sq_cd *cd) 425{ 426 struct ice_aqc_get_link_topo *cmd; 427 struct libie_aq_desc desc; 428 429 cmd = libie_aq_raw(&desc); 430 431 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 432 433 cmd->addr.topo_params.node_type_ctx = 434 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 435 ICE_AQC_LINK_TOPO_NODE_CTX_S); 436 437 /* set node type */ 438 cmd->addr.topo_params.node_type_ctx |= 439 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 440 441 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 442} 443 444/** 445 * ice_aq_get_netlist_node 446 * @hw: pointer to the hw struct 447 * @cmd: get_link_topo AQ structure 448 * @node_part_number: output node part number if node found 449 * @node_handle: output node handle parameter if node found 450 * 451 * Get netlist node handle. 452 */ 453int 454ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 455 u8 *node_part_number, u16 *node_handle) 456{ 457 struct ice_aqc_get_link_topo *resp; 458 struct libie_aq_desc desc; 459 460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 461 resp = libie_aq_raw(&desc); 462 *resp = *cmd; 463 464 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 465 return -EINTR; 466 467 if (node_handle) 468 *node_handle = le16_to_cpu(resp->addr.handle); 469 if (node_part_number) 470 *node_part_number = resp->node_part_num; 471 472 return 0; 473} 474 475/** 476 * ice_find_netlist_node 477 * @hw: pointer to the hw struct 478 * @node_type: type of netlist node to look for 479 * @ctx: context of the search 480 * @node_part_number: node part number to look for 481 * @node_handle: output parameter if node found - optional 482 * 483 * Scan the netlist for a node handle of the given node type and part number. 484 * 485 * If node_handle is non-NULL it will be modified on function exit. It is only 486 * valid if the function returns zero, and should be ignored on any non-zero 487 * return value. 488 * 489 * Return: 490 * * 0 if the node is found, 491 * * -ENOENT if no handle was found, 492 * * negative error code on failure to access the AQ. 493 */ 494static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 495 u8 node_part_number, u16 *node_handle) 496{ 497 u8 idx; 498 499 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 500 struct ice_aqc_get_link_topo cmd = {}; 501 u8 rec_node_part_number; 502 int status; 503 504 cmd.addr.topo_params.node_type_ctx = 505 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 506 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 507 cmd.addr.topo_params.index = idx; 508 509 status = ice_aq_get_netlist_node(hw, &cmd, 510 &rec_node_part_number, 511 node_handle); 512 if (status) 513 return status; 514 515 if (rec_node_part_number == node_part_number) 516 return 0; 517 } 518 519 return -ENOENT; 520} 521 522/** 523 * ice_is_media_cage_present 524 * @pi: port information structure 525 * 526 * Returns true if media cage is present, else false. If no cage, then 527 * media type is backplane or BASE-T. 528 */ 529static bool ice_is_media_cage_present(struct ice_port_info *pi) 530{ 531 /* Node type cage can be used to determine if cage is present. If AQC 532 * returns error (ENOENT), then no cage present. If no cage present then 533 * connection type is backplane or BASE-T. 534 */ 535 return !ice_aq_get_link_topo_handle(pi, 536 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 537 NULL); 538} 539 540/** 541 * ice_get_media_type - Gets media type 542 * @pi: port information structure 543 */ 544static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 545{ 546 struct ice_link_status *hw_link_info; 547 548 if (!pi) 549 return ICE_MEDIA_UNKNOWN; 550 551 hw_link_info = &pi->phy.link_info; 552 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 553 /* If more than one media type is selected, report unknown */ 554 return ICE_MEDIA_UNKNOWN; 555 556 if (hw_link_info->phy_type_low) { 557 /* 1G SGMII is a special case where some DA cable PHYs 558 * may show this as an option when it really shouldn't 559 * be since SGMII is meant to be between a MAC and a PHY 560 * in a backplane. Try to detect this case and handle it 561 */ 562 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 563 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 564 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 565 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 566 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 567 return ICE_MEDIA_DA; 568 569 switch (hw_link_info->phy_type_low) { 570 case ICE_PHY_TYPE_LOW_1000BASE_SX: 571 case ICE_PHY_TYPE_LOW_1000BASE_LX: 572 case ICE_PHY_TYPE_LOW_10GBASE_SR: 573 case ICE_PHY_TYPE_LOW_10GBASE_LR: 574 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 575 case ICE_PHY_TYPE_LOW_25GBASE_SR: 576 case ICE_PHY_TYPE_LOW_25GBASE_LR: 577 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 578 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 579 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 580 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 581 case ICE_PHY_TYPE_LOW_50GBASE_SR: 582 case ICE_PHY_TYPE_LOW_50GBASE_FR: 583 case ICE_PHY_TYPE_LOW_50GBASE_LR: 584 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 585 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 586 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 587 case ICE_PHY_TYPE_LOW_100GBASE_DR: 588 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 589 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 590 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 591 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 592 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 593 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 594 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 595 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 596 return ICE_MEDIA_FIBER; 597 case ICE_PHY_TYPE_LOW_100BASE_TX: 598 case ICE_PHY_TYPE_LOW_1000BASE_T: 599 case ICE_PHY_TYPE_LOW_2500BASE_T: 600 case ICE_PHY_TYPE_LOW_5GBASE_T: 601 case ICE_PHY_TYPE_LOW_10GBASE_T: 602 case ICE_PHY_TYPE_LOW_25GBASE_T: 603 return ICE_MEDIA_BASET; 604 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 605 case ICE_PHY_TYPE_LOW_25GBASE_CR: 606 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 607 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 608 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 609 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 610 case ICE_PHY_TYPE_LOW_50GBASE_CP: 611 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 612 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 613 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 614 return ICE_MEDIA_DA; 615 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 616 case ICE_PHY_TYPE_LOW_40G_XLAUI: 617 case ICE_PHY_TYPE_LOW_50G_LAUI2: 618 case ICE_PHY_TYPE_LOW_50G_AUI2: 619 case ICE_PHY_TYPE_LOW_50G_AUI1: 620 case ICE_PHY_TYPE_LOW_100G_AUI4: 621 case ICE_PHY_TYPE_LOW_100G_CAUI4: 622 if (ice_is_media_cage_present(pi)) 623 return ICE_MEDIA_DA; 624 fallthrough; 625 case ICE_PHY_TYPE_LOW_1000BASE_KX: 626 case ICE_PHY_TYPE_LOW_2500BASE_KX: 627 case ICE_PHY_TYPE_LOW_2500BASE_X: 628 case ICE_PHY_TYPE_LOW_5GBASE_KR: 629 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 630 case ICE_PHY_TYPE_LOW_25GBASE_KR: 631 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 632 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 633 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 634 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 635 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 636 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 637 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 638 return ICE_MEDIA_BACKPLANE; 639 } 640 } else { 641 switch (hw_link_info->phy_type_high) { 642 case ICE_PHY_TYPE_HIGH_100G_AUI2: 643 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 644 if (ice_is_media_cage_present(pi)) 645 return ICE_MEDIA_DA; 646 fallthrough; 647 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 648 return ICE_MEDIA_BACKPLANE; 649 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 650 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 651 return ICE_MEDIA_FIBER; 652 } 653 } 654 return ICE_MEDIA_UNKNOWN; 655} 656 657/** 658 * ice_get_link_status_datalen 659 * @hw: pointer to the HW struct 660 * 661 * Returns datalength for the Get Link Status AQ command, which is bigger for 662 * newer adapter families handled by ice driver. 663 */ 664static u16 ice_get_link_status_datalen(struct ice_hw *hw) 665{ 666 switch (hw->mac_type) { 667 case ICE_MAC_E830: 668 return ICE_AQC_LS_DATA_SIZE_V2; 669 case ICE_MAC_E810: 670 default: 671 return ICE_AQC_LS_DATA_SIZE_V1; 672 } 673} 674 675/** 676 * ice_aq_get_link_info 677 * @pi: port information structure 678 * @ena_lse: enable/disable LinkStatusEvent reporting 679 * @link: pointer to link status structure - optional 680 * @cd: pointer to command details structure or NULL 681 * 682 * Get Link Status (0x607). Returns the link status of the adapter. 683 */ 684int 685ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 686 struct ice_link_status *link, struct ice_sq_cd *cd) 687{ 688 struct ice_aqc_get_link_status_data link_data = { 0 }; 689 struct ice_aqc_get_link_status *resp; 690 struct ice_link_status *li_old, *li; 691 enum ice_media_type *hw_media_type; 692 struct ice_fc_info *hw_fc_info; 693 struct libie_aq_desc desc; 694 bool tx_pause, rx_pause; 695 struct ice_hw *hw; 696 u16 cmd_flags; 697 int status; 698 699 if (!pi) 700 return -EINVAL; 701 hw = pi->hw; 702 li_old = &pi->phy.link_info_old; 703 hw_media_type = &pi->phy.media_type; 704 li = &pi->phy.link_info; 705 hw_fc_info = &pi->fc; 706 707 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 708 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 709 resp = libie_aq_raw(&desc); 710 resp->cmd_flags = cpu_to_le16(cmd_flags); 711 resp->lport_num = pi->lport; 712 713 status = ice_aq_send_cmd(hw, &desc, &link_data, 714 ice_get_link_status_datalen(hw), cd); 715 if (status) 716 return status; 717 718 /* save off old link status information */ 719 *li_old = *li; 720 721 /* update current link status information */ 722 li->link_speed = le16_to_cpu(link_data.link_speed); 723 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 724 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 725 *hw_media_type = ice_get_media_type(pi); 726 li->link_info = link_data.link_info; 727 li->link_cfg_err = link_data.link_cfg_err; 728 li->an_info = link_data.an_info; 729 li->ext_info = link_data.ext_info; 730 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 731 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 732 li->topo_media_conflict = link_data.topo_media_conflict; 733 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 734 ICE_AQ_CFG_PACING_TYPE_M); 735 736 /* update fc info */ 737 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 738 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 739 if (tx_pause && rx_pause) 740 hw_fc_info->current_mode = ICE_FC_FULL; 741 else if (tx_pause) 742 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 743 else if (rx_pause) 744 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 745 else 746 hw_fc_info->current_mode = ICE_FC_NONE; 747 748 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 749 750 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 751 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 752 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 753 (unsigned long long)li->phy_type_low); 754 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 755 (unsigned long long)li->phy_type_high); 756 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 757 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 758 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 759 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 760 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 761 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 762 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 763 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 764 li->max_frame_size); 765 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 766 767 /* save link status information */ 768 if (link) 769 *link = *li; 770 771 /* flag cleared so calling functions don't call AQ again */ 772 pi->phy.get_link_info = false; 773 774 return 0; 775} 776 777/** 778 * ice_fill_tx_timer_and_fc_thresh 779 * @hw: pointer to the HW struct 780 * @cmd: pointer to MAC cfg structure 781 * 782 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 783 * descriptor 784 */ 785static void 786ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 787 struct ice_aqc_set_mac_cfg *cmd) 788{ 789 u32 val, fc_thres_m; 790 791 /* We read back the transmit timer and FC threshold value of 792 * LFC. Thus, we will use index = 793 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 794 * 795 * Also, because we are operating on transmit timer and FC 796 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 797 */ 798#define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 799#define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 800 801 if (hw->mac_type == ICE_MAC_E830) { 802 /* Retrieve the transmit timer */ 803 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 804 cmd->tx_tmr_value = 805 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 806 807 /* Retrieve the fc threshold */ 808 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 809 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 810 } else { 811 /* Retrieve the transmit timer */ 812 val = rd32(hw, 813 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 814 cmd->tx_tmr_value = 815 le16_encode_bits(val, 816 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 817 818 /* Retrieve the fc threshold */ 819 val = rd32(hw, 820 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 821 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 822 } 823 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 824} 825 826/** 827 * ice_aq_set_mac_cfg 828 * @hw: pointer to the HW struct 829 * @max_frame_size: Maximum Frame Size to be supported 830 * @cd: pointer to command details structure or NULL 831 * 832 * Set MAC configuration (0x0603) 833 */ 834int 835ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 836{ 837 struct ice_aqc_set_mac_cfg *cmd; 838 struct libie_aq_desc desc; 839 840 cmd = libie_aq_raw(&desc); 841 842 if (max_frame_size == 0) 843 return -EINVAL; 844 845 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 846 847 cmd->max_frame_size = cpu_to_le16(max_frame_size); 848 849 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 850 851 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 852} 853 854/** 855 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 856 * @hw: pointer to the HW struct 857 */ 858static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 859{ 860 struct ice_switch_info *sw; 861 int status; 862 863 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 864 sizeof(*hw->switch_info), GFP_KERNEL); 865 sw = hw->switch_info; 866 867 if (!sw) 868 return -ENOMEM; 869 870 INIT_LIST_HEAD(&sw->vsi_list_map_head); 871 sw->prof_res_bm_init = 0; 872 873 /* Initialize recipe count with default recipes read from NVM */ 874 sw->recp_cnt = ICE_SW_LKUP_LAST; 875 876 status = ice_init_def_sw_recp(hw); 877 if (status) { 878 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 879 return status; 880 } 881 return 0; 882} 883 884/** 885 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 886 * @hw: pointer to the HW struct 887 */ 888static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 889{ 890 struct ice_switch_info *sw = hw->switch_info; 891 struct ice_vsi_list_map_info *v_pos_map; 892 struct ice_vsi_list_map_info *v_tmp_map; 893 struct ice_sw_recipe *recps; 894 u8 i; 895 896 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 897 list_entry) { 898 list_del(&v_pos_map->list_entry); 899 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 900 } 901 recps = sw->recp_list; 902 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 903 recps[i].root_rid = i; 904 905 if (recps[i].adv_rule) { 906 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 907 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 908 909 mutex_destroy(&recps[i].filt_rule_lock); 910 list_for_each_entry_safe(lst_itr, tmp_entry, 911 &recps[i].filt_rules, 912 list_entry) { 913 list_del(&lst_itr->list_entry); 914 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 915 devm_kfree(ice_hw_to_dev(hw), lst_itr); 916 } 917 } else { 918 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 919 920 mutex_destroy(&recps[i].filt_rule_lock); 921 list_for_each_entry_safe(lst_itr, tmp_entry, 922 &recps[i].filt_rules, 923 list_entry) { 924 list_del(&lst_itr->list_entry); 925 devm_kfree(ice_hw_to_dev(hw), lst_itr); 926 } 927 } 928 } 929 ice_rm_all_sw_replay_rule_info(hw); 930 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 931 devm_kfree(ice_hw_to_dev(hw), sw); 932} 933 934/** 935 * ice_get_itr_intrl_gran 936 * @hw: pointer to the HW struct 937 * 938 * Determines the ITR/INTRL granularities based on the maximum aggregate 939 * bandwidth according to the device's configuration during power-on. 940 */ 941static void ice_get_itr_intrl_gran(struct ice_hw *hw) 942{ 943 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 944 rd32(hw, GL_PWR_MODE_CTL)); 945 946 switch (max_agg_bw) { 947 case ICE_MAX_AGG_BW_200G: 948 case ICE_MAX_AGG_BW_100G: 949 case ICE_MAX_AGG_BW_50G: 950 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 951 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 952 break; 953 case ICE_MAX_AGG_BW_25G: 954 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 955 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 956 break; 957 } 958} 959 960/** 961 * ice_wait_for_fw - wait for full FW readiness 962 * @hw: pointer to the hardware structure 963 * @timeout: milliseconds that can elapse before timing out 964 * 965 * Return: 0 on success, -ETIMEDOUT on timeout. 966 */ 967static int ice_wait_for_fw(struct ice_hw *hw, u32 timeout) 968{ 969 int fw_loading; 970 u32 elapsed = 0; 971 972 while (elapsed <= timeout) { 973 fw_loading = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 974 975 /* firmware was not yet loaded, we have to wait more */ 976 if (fw_loading) { 977 elapsed += 100; 978 msleep(100); 979 continue; 980 } 981 return 0; 982 } 983 984 return -ETIMEDOUT; 985} 986 987static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 988 u16 size) 989{ 990 struct ice_hw *hw = priv; 991 992 return ice_aq_send_cmd(hw, desc, buf, size, NULL); 993} 994 995static int __fwlog_init(struct ice_hw *hw) 996{ 997 struct ice_pf *pf = hw->back; 998 struct libie_fwlog_api api = { 999 .pdev = pf->pdev, 1000 .send_cmd = __fwlog_send_cmd, 1001 .priv = hw, 1002 }; 1003 int err; 1004 1005 /* only support fw log commands on PF 0 */ 1006 if (hw->bus.func) 1007 return -EINVAL; 1008 1009 err = ice_debugfs_pf_init(pf); 1010 if (err) 1011 return err; 1012 1013 api.debugfs_root = pf->ice_debugfs_pf; 1014 1015 return libie_fwlog_init(&hw->fwlog, &api); 1016} 1017 1018/** 1019 * ice_init_hw - main hardware initialization routine 1020 * @hw: pointer to the hardware structure 1021 */ 1022int ice_init_hw(struct ice_hw *hw) 1023{ 1024 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 1025 void *mac_buf __free(kfree) = NULL; 1026 u16 mac_buf_len; 1027 int status; 1028 1029 /* Set MAC type based on DeviceID */ 1030 status = ice_set_mac_type(hw); 1031 if (status) 1032 return status; 1033 1034 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1035 1036 status = ice_reset(hw, ICE_RESET_PFR); 1037 if (status) 1038 return status; 1039 1040 ice_get_itr_intrl_gran(hw); 1041 1042 status = ice_create_all_ctrlq(hw); 1043 if (status) 1044 goto err_unroll_cqinit; 1045 1046 status = __fwlog_init(hw); 1047 if (status) 1048 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1049 status); 1050 1051 status = ice_clear_pf_cfg(hw); 1052 if (status) 1053 goto err_unroll_cqinit; 1054 1055 /* Set bit to enable Flow Director filters */ 1056 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1057 INIT_LIST_HEAD(&hw->fdir_list_head); 1058 1059 ice_clear_pxe_mode(hw); 1060 1061 status = ice_init_nvm(hw); 1062 if (status) 1063 goto err_unroll_cqinit; 1064 1065 status = ice_get_caps(hw); 1066 if (status) 1067 goto err_unroll_cqinit; 1068 1069 if (!hw->port_info) 1070 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1071 sizeof(*hw->port_info), 1072 GFP_KERNEL); 1073 if (!hw->port_info) { 1074 status = -ENOMEM; 1075 goto err_unroll_cqinit; 1076 } 1077 1078 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1079 /* set the back pointer to HW */ 1080 hw->port_info->hw = hw; 1081 1082 /* Initialize port_info struct with switch configuration data */ 1083 status = ice_get_initial_sw_cfg(hw); 1084 if (status) 1085 goto err_unroll_alloc; 1086 1087 hw->evb_veb = true; 1088 1089 /* init xarray for identifying scheduling nodes uniquely */ 1090 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1091 1092 /* Query the allocated resources for Tx scheduler */ 1093 status = ice_sched_query_res_alloc(hw); 1094 if (status) { 1095 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1096 goto err_unroll_alloc; 1097 } 1098 ice_sched_get_psm_clk_freq(hw); 1099 1100 /* Initialize port_info struct with scheduler data */ 1101 status = ice_sched_init_port(hw->port_info); 1102 if (status) 1103 goto err_unroll_sched; 1104 1105 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 1106 if (!pcaps) { 1107 status = -ENOMEM; 1108 goto err_unroll_sched; 1109 } 1110 1111 /* Initialize port_info struct with PHY capabilities */ 1112 status = ice_aq_get_phy_caps(hw->port_info, false, 1113 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1114 NULL); 1115 if (status) 1116 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1117 status); 1118 1119 /* Initialize port_info struct with link information */ 1120 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1121 if (status) 1122 goto err_unroll_sched; 1123 1124 /* need a valid SW entry point to build a Tx tree */ 1125 if (!hw->sw_entry_point_layer) { 1126 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1127 status = -EIO; 1128 goto err_unroll_sched; 1129 } 1130 INIT_LIST_HEAD(&hw->agg_list); 1131 /* Initialize max burst size */ 1132 if (!hw->max_burst_size) 1133 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1134 1135 status = ice_init_fltr_mgmt_struct(hw); 1136 if (status) 1137 goto err_unroll_sched; 1138 1139 /* Get MAC information */ 1140 /* A single port can report up to two (LAN and WoL) addresses */ 1141 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp), 1142 GFP_KERNEL); 1143 if (!mac_buf) { 1144 status = -ENOMEM; 1145 goto err_unroll_fltr_mgmt_struct; 1146 } 1147 1148 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1149 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1150 1151 if (status) 1152 goto err_unroll_fltr_mgmt_struct; 1153 /* enable jumbo frame support at MAC level */ 1154 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1155 if (status) 1156 goto err_unroll_fltr_mgmt_struct; 1157 /* Obtain counter base index which would be used by flow director */ 1158 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1159 if (status) 1160 goto err_unroll_fltr_mgmt_struct; 1161 status = ice_init_hw_tbls(hw); 1162 if (status) 1163 goto err_unroll_fltr_mgmt_struct; 1164 1165 ice_init_dev_hw(hw->back); 1166 1167 mutex_init(&hw->tnl_lock); 1168 ice_init_chk_recipe_reuse_support(hw); 1169 1170 /* Some cards require longer initialization times 1171 * due to necessity of loading FW from an external source. 1172 * This can take even half a minute. 1173 */ 1174 if (ice_is_pf_c827(hw)) { 1175 status = ice_wait_for_fw(hw, 30000); 1176 if (status) { 1177 dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); 1178 goto err_unroll_fltr_mgmt_struct; 1179 } 1180 } 1181 1182 hw->lane_num = ice_get_phy_lane_number(hw); 1183 1184 return 0; 1185err_unroll_fltr_mgmt_struct: 1186 ice_cleanup_fltr_mgmt_struct(hw); 1187err_unroll_sched: 1188 ice_sched_cleanup_all(hw); 1189err_unroll_alloc: 1190 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1191err_unroll_cqinit: 1192 ice_destroy_all_ctrlq(hw); 1193 return status; 1194} 1195 1196static void __fwlog_deinit(struct ice_hw *hw) 1197{ 1198 /* only support fw log commands on PF 0 */ 1199 if (hw->bus.func) 1200 return; 1201 1202 ice_debugfs_pf_deinit(hw->back); 1203 libie_fwlog_deinit(&hw->fwlog); 1204} 1205 1206/** 1207 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1208 * @hw: pointer to the hardware structure 1209 * 1210 * This should be called only during nominal operation, not as a result of 1211 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1212 * applicable initializations if it fails for any reason. 1213 */ 1214void ice_deinit_hw(struct ice_hw *hw) 1215{ 1216 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1217 ice_cleanup_fltr_mgmt_struct(hw); 1218 1219 ice_sched_cleanup_all(hw); 1220 ice_sched_clear_agg(hw); 1221 ice_free_seg(hw); 1222 ice_free_hw_tbls(hw); 1223 mutex_destroy(&hw->tnl_lock); 1224 __fwlog_deinit(hw); 1225 ice_destroy_all_ctrlq(hw); 1226 1227 /* Clear VSI contexts if not already cleared */ 1228 ice_clear_all_vsi_ctx(hw); 1229} 1230 1231/** 1232 * ice_check_reset - Check to see if a global reset is complete 1233 * @hw: pointer to the hardware structure 1234 */ 1235int ice_check_reset(struct ice_hw *hw) 1236{ 1237 u32 cnt, reg = 0, grst_timeout, uld_mask; 1238 1239 /* Poll for Device Active state in case a recent CORER, GLOBR, 1240 * or EMPR has occurred. The grst delay value is in 100ms units. 1241 * Add 1sec for outstanding AQ commands that can take a long time. 1242 */ 1243 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1244 rd32(hw, GLGEN_RSTCTL)) + 10; 1245 1246 for (cnt = 0; cnt < grst_timeout; cnt++) { 1247 mdelay(100); 1248 reg = rd32(hw, GLGEN_RSTAT); 1249 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1250 break; 1251 } 1252 1253 if (cnt == grst_timeout) { 1254 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1255 return -EIO; 1256 } 1257 1258#define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1259 GLNVM_ULD_PCIER_DONE_1_M |\ 1260 GLNVM_ULD_CORER_DONE_M |\ 1261 GLNVM_ULD_GLOBR_DONE_M |\ 1262 GLNVM_ULD_POR_DONE_M |\ 1263 GLNVM_ULD_POR_DONE_1_M |\ 1264 GLNVM_ULD_PCIER_DONE_2_M) 1265 1266 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1267 GLNVM_ULD_PE_DONE_M : 0); 1268 1269 /* Device is Active; check Global Reset processes are done */ 1270 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1271 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1272 if (reg == uld_mask) { 1273 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1274 break; 1275 } 1276 mdelay(10); 1277 } 1278 1279 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1280 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1281 reg); 1282 return -EIO; 1283 } 1284 1285 return 0; 1286} 1287 1288/** 1289 * ice_pf_reset - Reset the PF 1290 * @hw: pointer to the hardware structure 1291 * 1292 * If a global reset has been triggered, this function checks 1293 * for its completion and then issues the PF reset 1294 */ 1295static int ice_pf_reset(struct ice_hw *hw) 1296{ 1297 u32 cnt, reg; 1298 1299 /* If at function entry a global reset was already in progress, i.e. 1300 * state is not 'device active' or any of the reset done bits are not 1301 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1302 * global reset is done. 1303 */ 1304 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1305 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1306 /* poll on global reset currently in progress until done */ 1307 if (ice_check_reset(hw)) 1308 return -EIO; 1309 1310 return 0; 1311 } 1312 1313 /* Reset the PF */ 1314 reg = rd32(hw, PFGEN_CTRL); 1315 1316 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1317 1318 /* Wait for the PFR to complete. The wait time is the global config lock 1319 * timeout plus the PFR timeout which will account for a possible reset 1320 * that is occurring during a download package operation. 1321 */ 1322 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1323 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1324 reg = rd32(hw, PFGEN_CTRL); 1325 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1326 break; 1327 1328 mdelay(1); 1329 } 1330 1331 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1332 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1333 return -EIO; 1334 } 1335 1336 return 0; 1337} 1338 1339/** 1340 * ice_reset - Perform different types of reset 1341 * @hw: pointer to the hardware structure 1342 * @req: reset request 1343 * 1344 * This function triggers a reset as specified by the req parameter. 1345 * 1346 * Note: 1347 * If anything other than a PF reset is triggered, PXE mode is restored. 1348 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1349 * interface has been restored in the rebuild flow. 1350 */ 1351int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1352{ 1353 u32 val = 0; 1354 1355 switch (req) { 1356 case ICE_RESET_PFR: 1357 return ice_pf_reset(hw); 1358 case ICE_RESET_CORER: 1359 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1360 val = GLGEN_RTRIG_CORER_M; 1361 break; 1362 case ICE_RESET_GLOBR: 1363 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1364 val = GLGEN_RTRIG_GLOBR_M; 1365 break; 1366 default: 1367 return -EINVAL; 1368 } 1369 1370 val |= rd32(hw, GLGEN_RTRIG); 1371 wr32(hw, GLGEN_RTRIG, val); 1372 ice_flush(hw); 1373 1374 /* wait for the FW to be ready */ 1375 return ice_check_reset(hw); 1376} 1377 1378/** 1379 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1380 * @hw: pointer to the hardware structure 1381 * @rxq_ctx: pointer to the packed Rx queue context 1382 * @rxq_index: the index of the Rx queue 1383 */ 1384static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1385 const ice_rxq_ctx_buf_t *rxq_ctx, 1386 u32 rxq_index) 1387{ 1388 /* Copy each dword separately to HW */ 1389 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1390 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1391 1392 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1393 1394 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1395 } 1396} 1397 1398/** 1399 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1400 * @hw: pointer to the hardware structure 1401 * @rxq_ctx: pointer to the packed Rx queue context 1402 * @rxq_index: the index of the Rx queue 1403 */ 1404static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1405 ice_rxq_ctx_buf_t *rxq_ctx, 1406 u32 rxq_index) 1407{ 1408 u32 *ctx = (u32 *)rxq_ctx; 1409 1410 /* Copy each dword separately from HW */ 1411 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1412 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1413 1414 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1415 } 1416} 1417 1418#define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1419 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1420 1421/* LAN Rx Queue Context */ 1422static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1423 /* Field Width LSB */ 1424 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1425 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1426 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1427 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1428 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1429 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1430 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1431 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1432 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1433 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1434 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1435 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1436 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1437 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1438 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1439 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1440 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1441 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1442 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1443 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1444}; 1445 1446/** 1447 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1448 * @ctx: the Rx queue context to pack 1449 * @buf: the HW buffer to pack into 1450 * 1451 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1452 * bit-packed HW layout. 1453 */ 1454static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1455 ice_rxq_ctx_buf_t *buf) 1456{ 1457 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1458 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1459} 1460 1461/** 1462 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1463 * @buf: the HW buffer to unpack from 1464 * @ctx: the Rx queue context to unpack 1465 * 1466 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1467 * structure. 1468 */ 1469static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1470 struct ice_rlan_ctx *ctx) 1471{ 1472 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1473 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1474} 1475 1476/** 1477 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1478 * @hw: pointer to the hardware structure 1479 * @rlan_ctx: pointer to the unpacked Rx queue context 1480 * @rxq_index: the index of the Rx queue 1481 * 1482 * Pack the sparse Rx Queue context into dense hardware format and write it 1483 * into the HW register space. 1484 * 1485 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1486 */ 1487int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1488 u32 rxq_index) 1489{ 1490 ice_rxq_ctx_buf_t buf = {}; 1491 1492 if (rxq_index > QRX_CTRL_MAX_INDEX) 1493 return -EINVAL; 1494 1495 ice_pack_rxq_ctx(rlan_ctx, &buf); 1496 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1497 1498 return 0; 1499} 1500 1501/** 1502 * ice_read_rxq_ctx - Read Rx queue context from HW 1503 * @hw: pointer to the hardware structure 1504 * @rlan_ctx: pointer to the Rx queue context 1505 * @rxq_index: the index of the Rx queue 1506 * 1507 * Read the Rx queue context from the hardware registers, and unpack it into 1508 * the sparse Rx queue context structure. 1509 * 1510 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1511 */ 1512int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1513 u32 rxq_index) 1514{ 1515 ice_rxq_ctx_buf_t buf = {}; 1516 1517 if (rxq_index > QRX_CTRL_MAX_INDEX) 1518 return -EINVAL; 1519 1520 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1521 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1522 1523 return 0; 1524} 1525 1526/* LAN Tx Queue Context */ 1527static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1528 /* Field Width LSB */ 1529 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1530 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1531 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1532 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1533 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1534 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1535 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1536 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1537 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1538 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1539 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1540 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1541 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1542 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1543 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1544 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1545 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1546 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1547 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1548 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1549 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1550 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1551 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1552 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1553 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1554 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1555 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1556}; 1557 1558/** 1559 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1560 * @ctx: the Tx queue context to pack 1561 * @buf: the Admin Queue HW buffer to pack into 1562 * 1563 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1564 * bit-packed Admin Queue layout. 1565 */ 1566void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1567{ 1568 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1569 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1570} 1571 1572/** 1573 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1574 * @ctx: the Tx queue context to pack 1575 * @buf: the HW buffer to pack into 1576 * 1577 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1578 * bit-packed HW layout, including the internal data portion. 1579 */ 1580static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1581 ice_txq_ctx_buf_full_t *buf) 1582{ 1583 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1584 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1585} 1586 1587/** 1588 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1589 * @buf: the HW buffer to unpack from 1590 * @ctx: the Tx queue context to unpack 1591 * 1592 * Unpack the Tx queue context from the HW buffer (including the full internal 1593 * state) into the CPU-friendly structure. 1594 */ 1595static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1596 struct ice_tlan_ctx *ctx) 1597{ 1598 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1599 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1600} 1601 1602/** 1603 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1604 * @hw: pointer to the hardware structure 1605 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1606 * @txq_index: the index of the Tx queue 1607 * 1608 * Copy Tx Queue context from HW register space to dense structure 1609 */ 1610static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1611 ice_txq_ctx_buf_full_t *txq_ctx, 1612 u32 txq_index) 1613{ 1614 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1615 u32 *ctx = (u32 *)txq_ctx; 1616 u32 txq_base, reg; 1617 1618 /* Get Tx queue base within card space */ 1619 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1620 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1621 1622 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1623 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1624 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1625 txq_base + txq_index) | 1626 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1627 1628 /* Prevent other PFs on the same adapter from accessing the Tx queue 1629 * context interface concurrently. 1630 */ 1631 spin_lock(&pf->adapter->txq_ctx_lock); 1632 1633 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1634 ice_flush(hw); 1635 1636 /* Copy each dword separately from HW */ 1637 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1638 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1639 1640 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1641 } 1642 1643 spin_unlock(&pf->adapter->txq_ctx_lock); 1644} 1645 1646/** 1647 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1648 * @hw: pointer to the hardware structure 1649 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1650 * @txq_index: the index of the Tx queue 1651 */ 1652static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1653 const ice_txq_ctx_buf_full_t *txq_ctx, 1654 u32 txq_index) 1655{ 1656 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1657 u32 txq_base, reg; 1658 1659 /* Get Tx queue base within card space */ 1660 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1661 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1662 1663 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1664 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1665 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1666 txq_base + txq_index) | 1667 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1668 1669 /* Prevent other PFs on the same adapter from accessing the Tx queue 1670 * context interface concurrently. 1671 */ 1672 spin_lock(&pf->adapter->txq_ctx_lock); 1673 1674 /* Copy each dword separately to HW */ 1675 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1676 u32 ctx = ((const u32 *)txq_ctx)[i]; 1677 1678 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1679 1680 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1681 } 1682 1683 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1684 ice_flush(hw); 1685 1686 spin_unlock(&pf->adapter->txq_ctx_lock); 1687} 1688 1689/** 1690 * ice_read_txq_ctx - Read Tx queue context from HW 1691 * @hw: pointer to the hardware structure 1692 * @tlan_ctx: pointer to the Tx queue context 1693 * @txq_index: the index of the Tx queue 1694 * 1695 * Read the Tx queue context from the HW registers, then unpack it into the 1696 * ice_tlan_ctx structure for use. 1697 * 1698 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1699 */ 1700int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1701 u32 txq_index) 1702{ 1703 ice_txq_ctx_buf_full_t buf = {}; 1704 1705 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1706 return -EINVAL; 1707 1708 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1709 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1710 1711 return 0; 1712} 1713 1714/** 1715 * ice_write_txq_ctx - Write Tx queue context to HW 1716 * @hw: pointer to the hardware structure 1717 * @tlan_ctx: pointer to the Tx queue context 1718 * @txq_index: the index of the Tx queue 1719 * 1720 * Pack the Tx queue context into the dense HW layout, then write it into the 1721 * HW registers. 1722 * 1723 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1724 */ 1725int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1726 u32 txq_index) 1727{ 1728 ice_txq_ctx_buf_full_t buf = {}; 1729 1730 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1731 return -EINVAL; 1732 1733 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1734 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1735 1736 return 0; 1737} 1738 1739/* Tx time Queue Context */ 1740static const struct packed_field_u8 ice_txtime_ctx_fields[] = { 1741 /* Field Width LSB */ 1742 ICE_CTX_STORE(ice_txtime_ctx, base, 57, 0), 1743 ICE_CTX_STORE(ice_txtime_ctx, pf_num, 3, 57), 1744 ICE_CTX_STORE(ice_txtime_ctx, vmvf_num, 10, 60), 1745 ICE_CTX_STORE(ice_txtime_ctx, vmvf_type, 2, 70), 1746 ICE_CTX_STORE(ice_txtime_ctx, src_vsi, 10, 72), 1747 ICE_CTX_STORE(ice_txtime_ctx, cpuid, 8, 82), 1748 ICE_CTX_STORE(ice_txtime_ctx, tphrd_desc, 1, 90), 1749 ICE_CTX_STORE(ice_txtime_ctx, qlen, 13, 91), 1750 ICE_CTX_STORE(ice_txtime_ctx, timer_num, 1, 104), 1751 ICE_CTX_STORE(ice_txtime_ctx, txtime_ena_q, 1, 105), 1752 ICE_CTX_STORE(ice_txtime_ctx, drbell_mode_32, 1, 106), 1753 ICE_CTX_STORE(ice_txtime_ctx, ts_res, 4, 107), 1754 ICE_CTX_STORE(ice_txtime_ctx, ts_round_type, 2, 111), 1755 ICE_CTX_STORE(ice_txtime_ctx, ts_pacing_slot, 3, 113), 1756 ICE_CTX_STORE(ice_txtime_ctx, merging_ena, 1, 116), 1757 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_prof_id, 4, 117), 1758 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_cache_line_aln_thld, 4, 121), 1759 ICE_CTX_STORE(ice_txtime_ctx, tx_pipe_delay_mode, 1, 125), 1760}; 1761 1762/** 1763 * ice_pack_txtime_ctx - pack Tx time queue context into a HW buffer 1764 * @ctx: the Tx time queue context to pack 1765 * @buf: the HW buffer to pack into 1766 * 1767 * Pack the Tx time queue context from the CPU-friendly unpacked buffer into 1768 * its bit-packed HW layout. 1769 */ 1770void ice_pack_txtime_ctx(const struct ice_txtime_ctx *ctx, 1771 ice_txtime_ctx_buf_t *buf) 1772{ 1773 pack_fields(buf, sizeof(*buf), ctx, ice_txtime_ctx_fields, 1774 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1775} 1776 1777/* Sideband Queue command wrappers */ 1778 1779/** 1780 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1781 * @hw: pointer to the HW struct 1782 * @desc: descriptor describing the command 1783 * @buf: buffer to use for indirect commands (NULL for direct commands) 1784 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1785 * @cd: pointer to command details structure 1786 */ 1787static int 1788ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1789 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1790{ 1791 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1792 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1793} 1794 1795/** 1796 * ice_sbq_rw_reg - Fill Sideband Queue command 1797 * @hw: pointer to the HW struct 1798 * @in: message info to be filled in descriptor 1799 * @flags: control queue descriptor flags 1800 */ 1801int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1802{ 1803 struct ice_sbq_cmd_desc desc = {0}; 1804 struct ice_sbq_msg_req msg = {0}; 1805 u16 msg_len; 1806 int status; 1807 1808 msg_len = sizeof(msg); 1809 1810 msg.dest_dev = in->dest_dev; 1811 msg.opcode = in->opcode; 1812 msg.flags = ICE_SBQ_MSG_FLAGS; 1813 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1814 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1815 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1816 1817 if (in->opcode) 1818 msg.data = cpu_to_le32(in->data); 1819 else 1820 /* data read comes back in completion, so shorten the struct by 1821 * sizeof(msg.data) 1822 */ 1823 msg_len -= sizeof(msg.data); 1824 1825 desc.flags = cpu_to_le16(flags); 1826 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1827 desc.param0.cmd_len = cpu_to_le16(msg_len); 1828 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1829 if (!status && !in->opcode) 1830 in->data = le32_to_cpu 1831 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1832 return status; 1833} 1834 1835/* FW Admin Queue command wrappers */ 1836 1837/* Software lock/mutex that is meant to be held while the Global Config Lock 1838 * in firmware is acquired by the software to prevent most (but not all) types 1839 * of AQ commands from being sent to FW 1840 */ 1841DEFINE_MUTEX(ice_global_cfg_lock_sw); 1842 1843/** 1844 * ice_should_retry_sq_send_cmd 1845 * @opcode: AQ opcode 1846 * 1847 * Decide if we should retry the send command routine for the ATQ, depending 1848 * on the opcode. 1849 */ 1850static bool ice_should_retry_sq_send_cmd(u16 opcode) 1851{ 1852 switch (opcode) { 1853 case ice_aqc_opc_get_link_topo: 1854 case ice_aqc_opc_lldp_stop: 1855 case ice_aqc_opc_lldp_start: 1856 case ice_aqc_opc_lldp_filter_ctrl: 1857 case ice_aqc_opc_sff_eeprom: 1858 return true; 1859 } 1860 1861 return false; 1862} 1863 1864/** 1865 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1866 * @hw: pointer to the HW struct 1867 * @cq: pointer to the specific Control queue 1868 * @desc: prefilled descriptor describing the command 1869 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1870 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1871 * @cd: pointer to command details structure 1872 * 1873 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1874 * Queue if the EBUSY AQ error is returned. 1875 */ 1876static int 1877ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1878 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1879 struct ice_sq_cd *cd) 1880{ 1881 struct libie_aq_desc desc_cpy; 1882 bool is_cmd_for_retry; 1883 u8 *buf_cpy = NULL; 1884 u8 idx = 0; 1885 u16 opcode; 1886 int status; 1887 1888 opcode = le16_to_cpu(desc->opcode); 1889 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1890 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1891 1892 if (is_cmd_for_retry) { 1893 if (buf) { 1894 buf_cpy = kmemdup(buf, buf_size, GFP_KERNEL); 1895 if (!buf_cpy) 1896 return -ENOMEM; 1897 } 1898 1899 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1900 } 1901 1902 do { 1903 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1904 1905 if (!is_cmd_for_retry || !status || 1906 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1907 break; 1908 1909 if (buf_cpy) 1910 memcpy(buf, buf_cpy, buf_size); 1911 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1912 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1913 1914 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1915 1916 kfree(buf_cpy); 1917 return status; 1918} 1919 1920/** 1921 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1922 * @hw: pointer to the HW struct 1923 * @desc: descriptor describing the command 1924 * @buf: buffer to use for indirect commands (NULL for direct commands) 1925 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1926 * @cd: pointer to command details structure 1927 * 1928 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1929 */ 1930int 1931ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1932 u16 buf_size, struct ice_sq_cd *cd) 1933{ 1934 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1935 bool lock_acquired = false; 1936 int status; 1937 1938 /* When a package download is in process (i.e. when the firmware's 1939 * Global Configuration Lock resource is held), only the Download 1940 * Package, Get Version, Get Package Info List, Upload Section, 1941 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1942 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1943 * Recipes to Profile Association, and Release Resource (with resource 1944 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1945 * must block until the package download completes and the Global Config 1946 * Lock is released. See also ice_acquire_global_cfg_lock(). 1947 */ 1948 switch (le16_to_cpu(desc->opcode)) { 1949 case ice_aqc_opc_download_pkg: 1950 case ice_aqc_opc_get_pkg_info_list: 1951 case ice_aqc_opc_get_ver: 1952 case ice_aqc_opc_upload_section: 1953 case ice_aqc_opc_update_pkg: 1954 case ice_aqc_opc_set_port_params: 1955 case ice_aqc_opc_get_vlan_mode_parameters: 1956 case ice_aqc_opc_set_vlan_mode_parameters: 1957 case ice_aqc_opc_set_tx_topo: 1958 case ice_aqc_opc_get_tx_topo: 1959 case ice_aqc_opc_add_recipe: 1960 case ice_aqc_opc_recipe_to_profile: 1961 case ice_aqc_opc_get_recipe: 1962 case ice_aqc_opc_get_recipe_to_profile: 1963 break; 1964 case ice_aqc_opc_release_res: 1965 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1966 break; 1967 fallthrough; 1968 default: 1969 mutex_lock(&ice_global_cfg_lock_sw); 1970 lock_acquired = true; 1971 break; 1972 } 1973 1974 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1975 if (lock_acquired) 1976 mutex_unlock(&ice_global_cfg_lock_sw); 1977 1978 return status; 1979} 1980 1981/** 1982 * ice_aq_get_fw_ver 1983 * @hw: pointer to the HW struct 1984 * @cd: pointer to command details structure or NULL 1985 * 1986 * Get the firmware version (0x0001) from the admin queue commands 1987 */ 1988int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1989{ 1990 struct libie_aqc_get_ver *resp; 1991 struct libie_aq_desc desc; 1992 int status; 1993 1994 resp = &desc.params.get_ver; 1995 1996 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1997 1998 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1999 2000 if (!status) { 2001 hw->fw_branch = resp->fw_branch; 2002 hw->fw_maj_ver = resp->fw_major; 2003 hw->fw_min_ver = resp->fw_minor; 2004 hw->fw_patch = resp->fw_patch; 2005 hw->fw_build = le32_to_cpu(resp->fw_build); 2006 hw->api_branch = resp->api_branch; 2007 hw->api_maj_ver = resp->api_major; 2008 hw->api_min_ver = resp->api_minor; 2009 hw->api_patch = resp->api_patch; 2010 } 2011 2012 return status; 2013} 2014 2015/** 2016 * ice_aq_send_driver_ver 2017 * @hw: pointer to the HW struct 2018 * @dv: driver's major, minor version 2019 * @cd: pointer to command details structure or NULL 2020 * 2021 * Send the driver version (0x0002) to the firmware 2022 */ 2023int 2024ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 2025 struct ice_sq_cd *cd) 2026{ 2027 struct libie_aqc_driver_ver *cmd; 2028 struct libie_aq_desc desc; 2029 u16 len; 2030 2031 cmd = &desc.params.driver_ver; 2032 2033 if (!dv) 2034 return -EINVAL; 2035 2036 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 2037 2038 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2039 cmd->major_ver = dv->major_ver; 2040 cmd->minor_ver = dv->minor_ver; 2041 cmd->build_ver = dv->build_ver; 2042 cmd->subbuild_ver = dv->subbuild_ver; 2043 2044 len = 0; 2045 while (len < sizeof(dv->driver_string) && 2046 isascii(dv->driver_string[len]) && dv->driver_string[len]) 2047 len++; 2048 2049 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 2050} 2051 2052/** 2053 * ice_aq_q_shutdown 2054 * @hw: pointer to the HW struct 2055 * @unloading: is the driver unloading itself 2056 * 2057 * Tell the Firmware that we're shutting down the AdminQ and whether 2058 * or not the driver is unloading as well (0x0003). 2059 */ 2060int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 2061{ 2062 struct ice_aqc_q_shutdown *cmd; 2063 struct libie_aq_desc desc; 2064 2065 cmd = libie_aq_raw(&desc); 2066 2067 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 2068 2069 if (unloading) 2070 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 2071 2072 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2073} 2074 2075/** 2076 * ice_aq_req_res 2077 * @hw: pointer to the HW struct 2078 * @res: resource ID 2079 * @access: access type 2080 * @sdp_number: resource number 2081 * @timeout: the maximum time in ms that the driver may hold the resource 2082 * @cd: pointer to command details structure or NULL 2083 * 2084 * Requests common resource using the admin queue commands (0x0008). 2085 * When attempting to acquire the Global Config Lock, the driver can 2086 * learn of three states: 2087 * 1) 0 - acquired lock, and can perform download package 2088 * 2) -EIO - did not get lock, driver should fail to load 2089 * 3) -EALREADY - did not get lock, but another driver has 2090 * successfully downloaded the package; the driver does 2091 * not have to download the package and can continue 2092 * loading 2093 * 2094 * Note that if the caller is in an acquire lock, perform action, release lock 2095 * phase of operation, it is possible that the FW may detect a timeout and issue 2096 * a CORER. In this case, the driver will receive a CORER interrupt and will 2097 * have to determine its cause. The calling thread that is handling this flow 2098 * will likely get an error propagated back to it indicating the Download 2099 * Package, Update Package or the Release Resource AQ commands timed out. 2100 */ 2101static int 2102ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2103 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2104 struct ice_sq_cd *cd) 2105{ 2106 struct libie_aqc_req_res *cmd_resp; 2107 struct libie_aq_desc desc; 2108 int status; 2109 2110 cmd_resp = &desc.params.res_owner; 2111 2112 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2113 2114 cmd_resp->res_id = cpu_to_le16(res); 2115 cmd_resp->access_type = cpu_to_le16(access); 2116 cmd_resp->res_number = cpu_to_le32(sdp_number); 2117 cmd_resp->timeout = cpu_to_le32(*timeout); 2118 *timeout = 0; 2119 2120 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2121 2122 /* The completion specifies the maximum time in ms that the driver 2123 * may hold the resource in the Timeout field. 2124 */ 2125 2126 /* Global config lock response utilizes an additional status field. 2127 * 2128 * If the Global config lock resource is held by some other driver, the 2129 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2130 * and the timeout field indicates the maximum time the current owner 2131 * of the resource has to free it. 2132 */ 2133 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2134 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2135 *timeout = le32_to_cpu(cmd_resp->timeout); 2136 return 0; 2137 } else if (le16_to_cpu(cmd_resp->status) == 2138 LIBIE_AQ_RES_GLBL_IN_PROG) { 2139 *timeout = le32_to_cpu(cmd_resp->timeout); 2140 return -EIO; 2141 } else if (le16_to_cpu(cmd_resp->status) == 2142 LIBIE_AQ_RES_GLBL_DONE) { 2143 return -EALREADY; 2144 } 2145 2146 /* invalid FW response, force a timeout immediately */ 2147 *timeout = 0; 2148 return -EIO; 2149 } 2150 2151 /* If the resource is held by some other driver, the command completes 2152 * with a busy return value and the timeout field indicates the maximum 2153 * time the current owner of the resource has to free it. 2154 */ 2155 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2156 *timeout = le32_to_cpu(cmd_resp->timeout); 2157 2158 return status; 2159} 2160 2161/** 2162 * ice_aq_release_res 2163 * @hw: pointer to the HW struct 2164 * @res: resource ID 2165 * @sdp_number: resource number 2166 * @cd: pointer to command details structure or NULL 2167 * 2168 * release common resource using the admin queue commands (0x0009) 2169 */ 2170static int 2171ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2172 struct ice_sq_cd *cd) 2173{ 2174 struct libie_aqc_req_res *cmd; 2175 struct libie_aq_desc desc; 2176 2177 cmd = &desc.params.res_owner; 2178 2179 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2180 2181 cmd->res_id = cpu_to_le16(res); 2182 cmd->res_number = cpu_to_le32(sdp_number); 2183 2184 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2185} 2186 2187/** 2188 * ice_acquire_res 2189 * @hw: pointer to the HW structure 2190 * @res: resource ID 2191 * @access: access type (read or write) 2192 * @timeout: timeout in milliseconds 2193 * 2194 * This function will attempt to acquire the ownership of a resource. 2195 */ 2196int 2197ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2198 enum ice_aq_res_access_type access, u32 timeout) 2199{ 2200#define ICE_RES_POLLING_DELAY_MS 10 2201 u32 delay = ICE_RES_POLLING_DELAY_MS; 2202 u32 time_left = timeout; 2203 int status; 2204 2205 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2206 2207 /* A return code of -EALREADY means that another driver has 2208 * previously acquired the resource and performed any necessary updates; 2209 * in this case the caller does not obtain the resource and has no 2210 * further work to do. 2211 */ 2212 if (status == -EALREADY) 2213 goto ice_acquire_res_exit; 2214 2215 if (status) 2216 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2217 2218 /* If necessary, poll until the current lock owner timeouts */ 2219 timeout = time_left; 2220 while (status && timeout && time_left) { 2221 mdelay(delay); 2222 timeout = (timeout > delay) ? timeout - delay : 0; 2223 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2224 2225 if (status == -EALREADY) 2226 /* lock free, but no work to do */ 2227 break; 2228 2229 if (!status) 2230 /* lock acquired */ 2231 break; 2232 } 2233 if (status && status != -EALREADY) 2234 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2235 2236ice_acquire_res_exit: 2237 if (status == -EALREADY) { 2238 if (access == ICE_RES_WRITE) 2239 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2240 else 2241 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2242 } 2243 return status; 2244} 2245 2246/** 2247 * ice_release_res 2248 * @hw: pointer to the HW structure 2249 * @res: resource ID 2250 * 2251 * This function will release a resource using the proper Admin Command. 2252 */ 2253void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2254{ 2255 unsigned long timeout; 2256 int status; 2257 2258 /* there are some rare cases when trying to release the resource 2259 * results in an admin queue timeout, so handle them correctly 2260 */ 2261 timeout = jiffies + 10 * usecs_to_jiffies(ICE_CTL_Q_SQ_CMD_TIMEOUT); 2262 do { 2263 status = ice_aq_release_res(hw, res, 0, NULL); 2264 if (status != -EIO) 2265 break; 2266 usleep_range(1000, 2000); 2267 } while (time_before(jiffies, timeout)); 2268} 2269 2270/** 2271 * ice_aq_alloc_free_res - command to allocate/free resources 2272 * @hw: pointer to the HW struct 2273 * @buf: Indirect buffer to hold data parameters and response 2274 * @buf_size: size of buffer for indirect commands 2275 * @opc: pass in the command opcode 2276 * 2277 * Helper function to allocate/free resources using the admin queue commands 2278 */ 2279int ice_aq_alloc_free_res(struct ice_hw *hw, 2280 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2281 enum ice_adminq_opc opc) 2282{ 2283 struct ice_aqc_alloc_free_res_cmd *cmd; 2284 struct libie_aq_desc desc; 2285 2286 cmd = libie_aq_raw(&desc); 2287 2288 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2289 return -EINVAL; 2290 2291 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2292 2293 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2294 2295 cmd->num_entries = cpu_to_le16(1); 2296 2297 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2298} 2299 2300/** 2301 * ice_alloc_hw_res - allocate resource 2302 * @hw: pointer to the HW struct 2303 * @type: type of resource 2304 * @num: number of resources to allocate 2305 * @btm: allocate from bottom 2306 * @res: pointer to array that will receive the resources 2307 */ 2308int 2309ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2310{ 2311 struct ice_aqc_alloc_free_res_elem *buf; 2312 u16 buf_len; 2313 int status; 2314 2315 buf_len = struct_size(buf, elem, num); 2316 buf = kzalloc(buf_len, GFP_KERNEL); 2317 if (!buf) 2318 return -ENOMEM; 2319 2320 /* Prepare buffer to allocate resource. */ 2321 buf->num_elems = cpu_to_le16(num); 2322 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2323 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2324 if (btm) 2325 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2326 2327 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2328 if (status) 2329 goto ice_alloc_res_exit; 2330 2331 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2332 2333ice_alloc_res_exit: 2334 kfree(buf); 2335 return status; 2336} 2337 2338/** 2339 * ice_free_hw_res - free allocated HW resource 2340 * @hw: pointer to the HW struct 2341 * @type: type of resource to free 2342 * @num: number of resources 2343 * @res: pointer to array that contains the resources to free 2344 */ 2345int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2346{ 2347 struct ice_aqc_alloc_free_res_elem *buf; 2348 u16 buf_len; 2349 int status; 2350 2351 buf_len = struct_size(buf, elem, num); 2352 buf = kzalloc(buf_len, GFP_KERNEL); 2353 if (!buf) 2354 return -ENOMEM; 2355 2356 /* Prepare buffer to free resource. */ 2357 buf->num_elems = cpu_to_le16(num); 2358 buf->res_type = cpu_to_le16(type); 2359 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2360 2361 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2362 if (status) 2363 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2364 2365 kfree(buf); 2366 return status; 2367} 2368 2369/** 2370 * ice_get_num_per_func - determine number of resources per PF 2371 * @hw: pointer to the HW structure 2372 * @max: value to be evenly split between each PF 2373 * 2374 * Determine the number of valid functions by going through the bitmap returned 2375 * from parsing capabilities and use this to calculate the number of resources 2376 * per PF based on the max value passed in. 2377 */ 2378static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2379{ 2380 u8 funcs; 2381 2382#define ICE_CAPS_VALID_FUNCS_M 0xFF 2383 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2384 ICE_CAPS_VALID_FUNCS_M); 2385 2386 if (!funcs) 2387 return 0; 2388 2389 return max / funcs; 2390} 2391 2392/** 2393 * ice_parse_common_caps - parse common device/function capabilities 2394 * @hw: pointer to the HW struct 2395 * @caps: pointer to common capabilities structure 2396 * @elem: the capability element to parse 2397 * @prefix: message prefix for tracing capabilities 2398 * 2399 * Given a capability element, extract relevant details into the common 2400 * capability structure. 2401 * 2402 * Returns: true if the capability matches one of the common capability ids, 2403 * false otherwise. 2404 */ 2405static bool 2406ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2407 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2408{ 2409 u32 logical_id = le32_to_cpu(elem->logical_id); 2410 u32 phys_id = le32_to_cpu(elem->phys_id); 2411 u32 number = le32_to_cpu(elem->number); 2412 u16 cap = le16_to_cpu(elem->cap); 2413 bool found = true; 2414 2415 switch (cap) { 2416 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2417 caps->valid_functions = number; 2418 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2419 caps->valid_functions); 2420 break; 2421 case LIBIE_AQC_CAPS_SRIOV: 2422 caps->sr_iov_1_1 = (number == 1); 2423 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2424 caps->sr_iov_1_1); 2425 break; 2426 case LIBIE_AQC_CAPS_DCB: 2427 caps->dcb = (number == 1); 2428 caps->active_tc_bitmap = logical_id; 2429 caps->maxtc = phys_id; 2430 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2431 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2432 caps->active_tc_bitmap); 2433 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2434 break; 2435 case LIBIE_AQC_CAPS_RSS: 2436 caps->rss_table_size = number; 2437 caps->rss_table_entry_width = logical_id; 2438 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2439 caps->rss_table_size); 2440 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2441 caps->rss_table_entry_width); 2442 break; 2443 case LIBIE_AQC_CAPS_RXQS: 2444 caps->num_rxq = number; 2445 caps->rxq_first_id = phys_id; 2446 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2447 caps->num_rxq); 2448 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2449 caps->rxq_first_id); 2450 break; 2451 case LIBIE_AQC_CAPS_TXQS: 2452 caps->num_txq = number; 2453 caps->txq_first_id = phys_id; 2454 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2455 caps->num_txq); 2456 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2457 caps->txq_first_id); 2458 break; 2459 case LIBIE_AQC_CAPS_MSIX: 2460 caps->num_msix_vectors = number; 2461 caps->msix_vector_first_id = phys_id; 2462 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2463 caps->num_msix_vectors); 2464 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2465 caps->msix_vector_first_id); 2466 break; 2467 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2468 caps->nvm_update_pending_nvm = true; 2469 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2470 break; 2471 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2472 caps->nvm_update_pending_orom = true; 2473 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2474 break; 2475 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2476 caps->nvm_update_pending_netlist = true; 2477 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2478 break; 2479 case LIBIE_AQC_CAPS_NVM_MGMT: 2480 caps->nvm_unified_update = 2481 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2482 true : false; 2483 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2484 caps->nvm_unified_update); 2485 break; 2486 case LIBIE_AQC_CAPS_RDMA: 2487 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2488 caps->rdma = (number == 1); 2489 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2490 break; 2491 case LIBIE_AQC_CAPS_MAX_MTU: 2492 caps->max_mtu = number; 2493 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2494 prefix, caps->max_mtu); 2495 break; 2496 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2497 caps->pcie_reset_avoidance = (number > 0); 2498 ice_debug(hw, ICE_DBG_INIT, 2499 "%s: pcie_reset_avoidance = %d\n", prefix, 2500 caps->pcie_reset_avoidance); 2501 break; 2502 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2503 caps->reset_restrict_support = (number == 1); 2504 ice_debug(hw, ICE_DBG_INIT, 2505 "%s: reset_restrict_support = %d\n", prefix, 2506 caps->reset_restrict_support); 2507 break; 2508 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2509 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2510 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2511 prefix, caps->roce_lag); 2512 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2513 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2514 prefix, caps->sriov_lag); 2515 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2516 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2517 prefix, caps->sriov_aa_lag); 2518 break; 2519 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2520 caps->tx_sched_topo_comp_mode_en = (number == 1); 2521 break; 2522 default: 2523 /* Not one of the recognized common capabilities */ 2524 found = false; 2525 } 2526 2527 return found; 2528} 2529 2530/** 2531 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2532 * @hw: pointer to the HW structure 2533 * @caps: pointer to capabilities structure to fix 2534 * 2535 * Re-calculate the capabilities that are dependent on the number of physical 2536 * ports; i.e. some features are not supported or function differently on 2537 * devices with more than 4 ports. 2538 */ 2539static void 2540ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2541{ 2542 /* This assumes device capabilities are always scanned before function 2543 * capabilities during the initialization flow. 2544 */ 2545 if (hw->dev_caps.num_funcs > 4) { 2546 /* Max 4 TCs per port */ 2547 caps->maxtc = 4; 2548 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2549 caps->maxtc); 2550 if (caps->rdma) { 2551 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2552 caps->rdma = 0; 2553 } 2554 2555 /* print message only when processing device capabilities 2556 * during initialization. 2557 */ 2558 if (caps == &hw->dev_caps.common_cap) 2559 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2560 } 2561} 2562 2563/** 2564 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2565 * @hw: pointer to the HW struct 2566 * @func_p: pointer to function capabilities structure 2567 * @cap: pointer to the capability element to parse 2568 * 2569 * Extract function capabilities for ICE_AQC_CAPS_VF. 2570 */ 2571static void 2572ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2573 struct libie_aqc_list_caps_elem *cap) 2574{ 2575 u32 logical_id = le32_to_cpu(cap->logical_id); 2576 u32 number = le32_to_cpu(cap->number); 2577 2578 func_p->num_allocd_vfs = number; 2579 func_p->vf_base_id = logical_id; 2580 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2581 func_p->num_allocd_vfs); 2582 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2583 func_p->vf_base_id); 2584} 2585 2586/** 2587 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2588 * @hw: pointer to the HW struct 2589 * @func_p: pointer to function capabilities structure 2590 * @cap: pointer to the capability element to parse 2591 * 2592 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2593 */ 2594static void 2595ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2596 struct libie_aqc_list_caps_elem *cap) 2597{ 2598 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2599 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2600 le32_to_cpu(cap->number)); 2601 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2602 func_p->guar_num_vsi); 2603} 2604 2605/** 2606 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2607 * @hw: pointer to the HW struct 2608 * @func_p: pointer to function capabilities structure 2609 * @cap: pointer to the capability element to parse 2610 * 2611 * Extract function capabilities for ICE_AQC_CAPS_1588. 2612 */ 2613static void 2614ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2615 struct libie_aqc_list_caps_elem *cap) 2616{ 2617 struct ice_ts_func_info *info = &func_p->ts_func_info; 2618 u32 number = le32_to_cpu(cap->number); 2619 2620 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2621 func_p->common_cap.ieee_1588 = info->ena; 2622 2623 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2624 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2625 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2626 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2627 2628 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2629 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2630 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2631 } else { 2632 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2633 info->clk_src = ICE_CLK_SRC_TIME_REF; 2634 } 2635 2636 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2637 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2638 } else { 2639 /* Unknown clock frequency, so assume a (probably incorrect) 2640 * default to avoid out-of-bounds look ups of frequency 2641 * related information. 2642 */ 2643 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2644 info->clk_freq); 2645 info->time_ref = ICE_TSPLL_FREQ_25_000; 2646 } 2647 2648 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2649 func_p->common_cap.ieee_1588); 2650 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2651 info->src_tmr_owned); 2652 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2653 info->tmr_ena); 2654 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2655 info->tmr_index_owned); 2656 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2657 info->tmr_index_assoc); 2658 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2659 info->clk_freq); 2660 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2661 info->clk_src); 2662} 2663 2664/** 2665 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2666 * @hw: pointer to the HW struct 2667 * @func_p: pointer to function capabilities structure 2668 * 2669 * Extract function capabilities for ICE_AQC_CAPS_FD. 2670 */ 2671static void 2672ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2673{ 2674 u32 reg_val, gsize, bsize; 2675 2676 reg_val = rd32(hw, GLQF_FD_SIZE); 2677 switch (hw->mac_type) { 2678 case ICE_MAC_E830: 2679 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2680 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2681 break; 2682 case ICE_MAC_E810: 2683 default: 2684 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2685 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2686 } 2687 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2688 func_p->fd_fltr_best_effort = bsize; 2689 2690 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2691 func_p->fd_fltr_guar); 2692 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2693 func_p->fd_fltr_best_effort); 2694} 2695 2696/** 2697 * ice_parse_func_caps - Parse function capabilities 2698 * @hw: pointer to the HW struct 2699 * @func_p: pointer to function capabilities structure 2700 * @buf: buffer containing the function capability records 2701 * @cap_count: the number of capabilities 2702 * 2703 * Helper function to parse function (0x000A) capabilities list. For 2704 * capabilities shared between device and function, this relies on 2705 * ice_parse_common_caps. 2706 * 2707 * Loop through the list of provided capabilities and extract the relevant 2708 * data into the function capabilities structured. 2709 */ 2710static void 2711ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2712 void *buf, u32 cap_count) 2713{ 2714 struct libie_aqc_list_caps_elem *cap_resp; 2715 u32 i; 2716 2717 cap_resp = buf; 2718 2719 memset(func_p, 0, sizeof(*func_p)); 2720 2721 for (i = 0; i < cap_count; i++) { 2722 u16 cap = le16_to_cpu(cap_resp[i].cap); 2723 bool found; 2724 2725 found = ice_parse_common_caps(hw, &func_p->common_cap, 2726 &cap_resp[i], "func caps"); 2727 2728 switch (cap) { 2729 case LIBIE_AQC_CAPS_VF: 2730 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2731 break; 2732 case LIBIE_AQC_CAPS_VSI: 2733 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2734 break; 2735 case LIBIE_AQC_CAPS_1588: 2736 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2737 break; 2738 case LIBIE_AQC_CAPS_FD: 2739 ice_parse_fdir_func_caps(hw, func_p); 2740 break; 2741 default: 2742 /* Don't list common capabilities as unknown */ 2743 if (!found) 2744 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2745 i, cap); 2746 break; 2747 } 2748 } 2749 2750 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2751} 2752 2753/** 2754 * ice_func_id_to_logical_id - map from function id to logical pf id 2755 * @active_function_bitmap: active function bitmap 2756 * @pf_id: function number of device 2757 * 2758 * Return: logical PF ID. 2759 */ 2760static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2761{ 2762 u8 logical_id = 0; 2763 u8 i; 2764 2765 for (i = 0; i < pf_id; i++) 2766 if (active_function_bitmap & BIT(i)) 2767 logical_id++; 2768 2769 return logical_id; 2770} 2771 2772/** 2773 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2774 * @hw: pointer to the HW struct 2775 * @dev_p: pointer to device capabilities structure 2776 * @cap: capability element to parse 2777 * 2778 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2779 */ 2780static void 2781ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2782 struct libie_aqc_list_caps_elem *cap) 2783{ 2784 u32 number = le32_to_cpu(cap->number); 2785 2786 dev_p->num_funcs = hweight32(number); 2787 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2788 dev_p->num_funcs); 2789 2790 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2791} 2792 2793/** 2794 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2795 * @hw: pointer to the HW struct 2796 * @dev_p: pointer to device capabilities structure 2797 * @cap: capability element to parse 2798 * 2799 * Parse ICE_AQC_CAPS_VF for device capabilities. 2800 */ 2801static void 2802ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2803 struct libie_aqc_list_caps_elem *cap) 2804{ 2805 u32 number = le32_to_cpu(cap->number); 2806 2807 dev_p->num_vfs_exposed = number; 2808 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2809 dev_p->num_vfs_exposed); 2810} 2811 2812/** 2813 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2814 * @hw: pointer to the HW struct 2815 * @dev_p: pointer to device capabilities structure 2816 * @cap: capability element to parse 2817 * 2818 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2819 */ 2820static void 2821ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2822 struct libie_aqc_list_caps_elem *cap) 2823{ 2824 u32 number = le32_to_cpu(cap->number); 2825 2826 dev_p->num_vsi_allocd_to_host = number; 2827 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2828 dev_p->num_vsi_allocd_to_host); 2829} 2830 2831/** 2832 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2833 * @hw: pointer to the HW struct 2834 * @dev_p: pointer to device capabilities structure 2835 * @cap: capability element to parse 2836 * 2837 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2838 */ 2839static void 2840ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2841 struct libie_aqc_list_caps_elem *cap) 2842{ 2843 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2844 u32 logical_id = le32_to_cpu(cap->logical_id); 2845 u32 phys_id = le32_to_cpu(cap->phys_id); 2846 u32 number = le32_to_cpu(cap->number); 2847 2848 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2849 dev_p->common_cap.ieee_1588 = info->ena; 2850 2851 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2852 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2853 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2854 2855 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2856 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2857 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2858 2859 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2860 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2861 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2862 2863 info->ena_ports = logical_id; 2864 info->tmr_own_map = phys_id; 2865 2866 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2867 dev_p->common_cap.ieee_1588); 2868 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2869 info->tmr0_owner); 2870 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2871 info->tmr0_owned); 2872 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2873 info->tmr0_ena); 2874 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2875 info->tmr1_owner); 2876 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2877 info->tmr1_owned); 2878 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2879 info->tmr1_ena); 2880 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2881 info->ts_ll_read); 2882 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2883 info->ts_ll_int_read); 2884 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2885 info->ll_phy_tmr_update); 2886 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2887 info->ena_ports); 2888 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2889 info->tmr_own_map); 2890} 2891 2892/** 2893 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2894 * @hw: pointer to the HW struct 2895 * @dev_p: pointer to device capabilities structure 2896 * @cap: capability element to parse 2897 * 2898 * Parse ICE_AQC_CAPS_FD for device capabilities. 2899 */ 2900static void 2901ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2902 struct libie_aqc_list_caps_elem *cap) 2903{ 2904 u32 number = le32_to_cpu(cap->number); 2905 2906 dev_p->num_flow_director_fltr = number; 2907 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2908 dev_p->num_flow_director_fltr); 2909} 2910 2911/** 2912 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2913 * @hw: pointer to the HW struct 2914 * @dev_p: pointer to device capabilities structure 2915 * @cap: capability element to parse 2916 * 2917 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2918 * enabled sensors. 2919 */ 2920static void 2921ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2922 struct libie_aqc_list_caps_elem *cap) 2923{ 2924 dev_p->supported_sensors = le32_to_cpu(cap->number); 2925 2926 ice_debug(hw, ICE_DBG_INIT, 2927 "dev caps: supported sensors (bitmap) = 0x%x\n", 2928 dev_p->supported_sensors); 2929} 2930 2931/** 2932 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2933 * @hw: pointer to the HW struct 2934 * @dev_p: pointer to device capabilities structure 2935 * @cap: capability element to parse 2936 * 2937 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2938 */ 2939static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2940 struct ice_hw_dev_caps *dev_p, 2941 struct libie_aqc_list_caps_elem *cap) 2942{ 2943 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2944 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2945 2946 dev_info(ice_hw_to_dev(hw), 2947 "PF is configured in %s mode with IP instance ID %d\n", 2948 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2949 "primary" : "secondary", dev_p->nac_topo.id); 2950 2951 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2952 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2953 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2954 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2955 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2956 dev_p->nac_topo.id); 2957} 2958 2959/** 2960 * ice_parse_dev_caps - Parse device capabilities 2961 * @hw: pointer to the HW struct 2962 * @dev_p: pointer to device capabilities structure 2963 * @buf: buffer containing the device capability records 2964 * @cap_count: the number of capabilities 2965 * 2966 * Helper device to parse device (0x000B) capabilities list. For 2967 * capabilities shared between device and function, this relies on 2968 * ice_parse_common_caps. 2969 * 2970 * Loop through the list of provided capabilities and extract the relevant 2971 * data into the device capabilities structured. 2972 */ 2973static void 2974ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2975 void *buf, u32 cap_count) 2976{ 2977 struct libie_aqc_list_caps_elem *cap_resp; 2978 u32 i; 2979 2980 cap_resp = buf; 2981 2982 memset(dev_p, 0, sizeof(*dev_p)); 2983 2984 for (i = 0; i < cap_count; i++) { 2985 u16 cap = le16_to_cpu(cap_resp[i].cap); 2986 bool found; 2987 2988 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2989 &cap_resp[i], "dev caps"); 2990 2991 switch (cap) { 2992 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2993 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2994 break; 2995 case LIBIE_AQC_CAPS_VF: 2996 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2997 break; 2998 case LIBIE_AQC_CAPS_VSI: 2999 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 3000 break; 3001 case LIBIE_AQC_CAPS_1588: 3002 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 3003 break; 3004 case LIBIE_AQC_CAPS_FD: 3005 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 3006 break; 3007 case LIBIE_AQC_CAPS_SENSOR_READING: 3008 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 3009 break; 3010 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 3011 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 3012 break; 3013 default: 3014 /* Don't list common capabilities as unknown */ 3015 if (!found) 3016 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 3017 i, cap); 3018 break; 3019 } 3020 } 3021 3022 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 3023} 3024 3025/** 3026 * ice_is_phy_rclk_in_netlist 3027 * @hw: pointer to the hw struct 3028 * 3029 * Check if the PHY Recovered Clock device is present in the netlist 3030 */ 3031bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 3032{ 3033 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 3034 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 3035 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 3036 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 3037 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 3038 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 3039 return false; 3040 3041 return true; 3042} 3043 3044/** 3045 * ice_is_clock_mux_in_netlist 3046 * @hw: pointer to the hw struct 3047 * 3048 * Check if the Clock Multiplexer device is present in the netlist 3049 */ 3050bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 3051{ 3052 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 3053 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3054 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 3055 NULL)) 3056 return false; 3057 3058 return true; 3059} 3060 3061/** 3062 * ice_is_cgu_in_netlist - check for CGU presence 3063 * @hw: pointer to the hw struct 3064 * 3065 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 3066 * Save the CGU part number in the hw structure for later use. 3067 * Return: 3068 * * true - cgu is present 3069 * * false - cgu is not present 3070 */ 3071bool ice_is_cgu_in_netlist(struct ice_hw *hw) 3072{ 3073 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3074 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3075 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 3076 NULL)) { 3077 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 3078 return true; 3079 } else if (!ice_find_netlist_node(hw, 3080 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3081 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3082 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 3083 NULL)) { 3084 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 3085 return true; 3086 } 3087 3088 return false; 3089} 3090 3091/** 3092 * ice_is_gps_in_netlist 3093 * @hw: pointer to the hw struct 3094 * 3095 * Check if the GPS generic device is present in the netlist 3096 */ 3097bool ice_is_gps_in_netlist(struct ice_hw *hw) 3098{ 3099 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3100 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3101 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3102 return false; 3103 3104 return true; 3105} 3106 3107/** 3108 * ice_aq_list_caps - query function/device capabilities 3109 * @hw: pointer to the HW struct 3110 * @buf: a buffer to hold the capabilities 3111 * @buf_size: size of the buffer 3112 * @cap_count: if not NULL, set to the number of capabilities reported 3113 * @opc: capabilities type to discover, device or function 3114 * @cd: pointer to command details structure or NULL 3115 * 3116 * Get the function (0x000A) or device (0x000B) capabilities description from 3117 * firmware and store it in the buffer. 3118 * 3119 * If the cap_count pointer is not NULL, then it is set to the number of 3120 * capabilities firmware will report. Note that if the buffer size is too 3121 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3122 * cap_count will still be updated in this case. It is recommended that the 3123 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3124 * firmware could return) to avoid this. 3125 */ 3126int 3127ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3128 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3129{ 3130 struct libie_aqc_list_caps *cmd; 3131 struct libie_aq_desc desc; 3132 int status; 3133 3134 cmd = &desc.params.get_cap; 3135 3136 if (opc != ice_aqc_opc_list_func_caps && 3137 opc != ice_aqc_opc_list_dev_caps) 3138 return -EINVAL; 3139 3140 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3141 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3142 3143 if (cap_count) 3144 *cap_count = le32_to_cpu(cmd->count); 3145 3146 return status; 3147} 3148 3149/** 3150 * ice_discover_dev_caps - Read and extract device capabilities 3151 * @hw: pointer to the hardware structure 3152 * @dev_caps: pointer to device capabilities structure 3153 * 3154 * Read the device capabilities and extract them into the dev_caps structure 3155 * for later use. 3156 */ 3157int 3158ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3159{ 3160 u32 cap_count = 0; 3161 void *cbuf; 3162 int status; 3163 3164 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3165 if (!cbuf) 3166 return -ENOMEM; 3167 3168 /* Although the driver doesn't know the number of capabilities the 3169 * device will return, we can simply send a 4KB buffer, the maximum 3170 * possible size that firmware can return. 3171 */ 3172 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3173 3174 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3175 ice_aqc_opc_list_dev_caps, NULL); 3176 if (!status) 3177 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3178 kfree(cbuf); 3179 3180 return status; 3181} 3182 3183/** 3184 * ice_discover_func_caps - Read and extract function capabilities 3185 * @hw: pointer to the hardware structure 3186 * @func_caps: pointer to function capabilities structure 3187 * 3188 * Read the function capabilities and extract them into the func_caps structure 3189 * for later use. 3190 */ 3191static int 3192ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3193{ 3194 u32 cap_count = 0; 3195 void *cbuf; 3196 int status; 3197 3198 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3199 if (!cbuf) 3200 return -ENOMEM; 3201 3202 /* Although the driver doesn't know the number of capabilities the 3203 * device will return, we can simply send a 4KB buffer, the maximum 3204 * possible size that firmware can return. 3205 */ 3206 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3207 3208 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3209 ice_aqc_opc_list_func_caps, NULL); 3210 if (!status) 3211 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3212 kfree(cbuf); 3213 3214 return status; 3215} 3216 3217/** 3218 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3219 * @hw: pointer to the hardware structure 3220 */ 3221void ice_set_safe_mode_caps(struct ice_hw *hw) 3222{ 3223 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3224 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3225 struct ice_hw_common_caps cached_caps; 3226 u32 num_funcs; 3227 3228 /* cache some func_caps values that should be restored after memset */ 3229 cached_caps = func_caps->common_cap; 3230 3231 /* unset func capabilities */ 3232 memset(func_caps, 0, sizeof(*func_caps)); 3233 3234#define ICE_RESTORE_FUNC_CAP(name) \ 3235 func_caps->common_cap.name = cached_caps.name 3236 3237 /* restore cached values */ 3238 ICE_RESTORE_FUNC_CAP(valid_functions); 3239 ICE_RESTORE_FUNC_CAP(txq_first_id); 3240 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3241 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3242 ICE_RESTORE_FUNC_CAP(max_mtu); 3243 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3244 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3245 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3246 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3247 3248 /* one Tx and one Rx queue in safe mode */ 3249 func_caps->common_cap.num_rxq = 1; 3250 func_caps->common_cap.num_txq = 1; 3251 3252 /* two MSIX vectors, one for traffic and one for misc causes */ 3253 func_caps->common_cap.num_msix_vectors = 2; 3254 func_caps->guar_num_vsi = 1; 3255 3256 /* cache some dev_caps values that should be restored after memset */ 3257 cached_caps = dev_caps->common_cap; 3258 num_funcs = dev_caps->num_funcs; 3259 3260 /* unset dev capabilities */ 3261 memset(dev_caps, 0, sizeof(*dev_caps)); 3262 3263#define ICE_RESTORE_DEV_CAP(name) \ 3264 dev_caps->common_cap.name = cached_caps.name 3265 3266 /* restore cached values */ 3267 ICE_RESTORE_DEV_CAP(valid_functions); 3268 ICE_RESTORE_DEV_CAP(txq_first_id); 3269 ICE_RESTORE_DEV_CAP(rxq_first_id); 3270 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3271 ICE_RESTORE_DEV_CAP(max_mtu); 3272 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3273 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3274 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3275 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3276 dev_caps->num_funcs = num_funcs; 3277 3278 /* one Tx and one Rx queue per function in safe mode */ 3279 dev_caps->common_cap.num_rxq = num_funcs; 3280 dev_caps->common_cap.num_txq = num_funcs; 3281 3282 /* two MSIX vectors per function */ 3283 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3284} 3285 3286/** 3287 * ice_get_caps - get info about the HW 3288 * @hw: pointer to the hardware structure 3289 */ 3290int ice_get_caps(struct ice_hw *hw) 3291{ 3292 int status; 3293 3294 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3295 if (status) 3296 return status; 3297 3298 return ice_discover_func_caps(hw, &hw->func_caps); 3299} 3300 3301/** 3302 * ice_aq_manage_mac_write - manage MAC address write command 3303 * @hw: pointer to the HW struct 3304 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3305 * @flags: flags to control write behavior 3306 * @cd: pointer to command details structure or NULL 3307 * 3308 * This function is used to write MAC address to the NVM (0x0108). 3309 */ 3310int 3311ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3312 struct ice_sq_cd *cd) 3313{ 3314 struct ice_aqc_manage_mac_write *cmd; 3315 struct libie_aq_desc desc; 3316 3317 cmd = libie_aq_raw(&desc); 3318 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3319 3320 cmd->flags = flags; 3321 ether_addr_copy(cmd->mac_addr, mac_addr); 3322 3323 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3324} 3325 3326/** 3327 * ice_aq_clear_pxe_mode 3328 * @hw: pointer to the HW struct 3329 * 3330 * Tell the firmware that the driver is taking over from PXE (0x0110). 3331 */ 3332static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3333{ 3334 struct ice_aqc_clear_pxe *cmd; 3335 struct libie_aq_desc desc; 3336 3337 cmd = libie_aq_raw(&desc); 3338 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3339 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3340 3341 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3342} 3343 3344/** 3345 * ice_clear_pxe_mode - clear pxe operations mode 3346 * @hw: pointer to the HW struct 3347 * 3348 * Make sure all PXE mode settings are cleared, including things 3349 * like descriptor fetch/write-back mode. 3350 */ 3351void ice_clear_pxe_mode(struct ice_hw *hw) 3352{ 3353 if (ice_check_sq_alive(hw, &hw->adminq)) 3354 ice_aq_clear_pxe_mode(hw); 3355} 3356 3357/** 3358 * ice_aq_set_port_params - set physical port parameters. 3359 * @pi: pointer to the port info struct 3360 * @double_vlan: if set double VLAN is enabled 3361 * @cd: pointer to command details structure or NULL 3362 * 3363 * Set Physical port parameters (0x0203) 3364 */ 3365int 3366ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3367 struct ice_sq_cd *cd) 3368 3369{ 3370 struct ice_aqc_set_port_params *cmd; 3371 struct ice_hw *hw = pi->hw; 3372 struct libie_aq_desc desc; 3373 u16 cmd_flags = 0; 3374 3375 cmd = libie_aq_raw(&desc); 3376 3377 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3378 if (double_vlan) 3379 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3380 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3381 3382 cmd->local_fwd_mode = pi->local_fwd_mode | 3383 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3384 3385 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3386} 3387 3388/** 3389 * ice_is_100m_speed_supported 3390 * @hw: pointer to the HW struct 3391 * 3392 * returns true if 100M speeds are supported by the device, 3393 * false otherwise. 3394 */ 3395bool ice_is_100m_speed_supported(struct ice_hw *hw) 3396{ 3397 switch (hw->device_id) { 3398 case ICE_DEV_ID_E822C_SGMII: 3399 case ICE_DEV_ID_E822L_SGMII: 3400 case ICE_DEV_ID_E823L_1GBE: 3401 case ICE_DEV_ID_E823C_SGMII: 3402 case ICE_DEV_ID_E825C_SGMII: 3403 return true; 3404 default: 3405 return false; 3406 } 3407} 3408 3409/** 3410 * ice_get_link_speed_based_on_phy_type - returns link speed 3411 * @phy_type_low: lower part of phy_type 3412 * @phy_type_high: higher part of phy_type 3413 * 3414 * This helper function will convert an entry in PHY type structure 3415 * [phy_type_low, phy_type_high] to its corresponding link speed. 3416 * Note: In the structure of [phy_type_low, phy_type_high], there should 3417 * be one bit set, as this function will convert one PHY type to its 3418 * speed. 3419 * 3420 * Return: 3421 * * PHY speed for recognized PHY type 3422 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3423 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3424 */ 3425u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3426{ 3427 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3428 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3429 3430 switch (phy_type_low) { 3431 case ICE_PHY_TYPE_LOW_100BASE_TX: 3432 case ICE_PHY_TYPE_LOW_100M_SGMII: 3433 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3434 break; 3435 case ICE_PHY_TYPE_LOW_1000BASE_T: 3436 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3437 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3438 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3439 case ICE_PHY_TYPE_LOW_1G_SGMII: 3440 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3441 break; 3442 case ICE_PHY_TYPE_LOW_2500BASE_T: 3443 case ICE_PHY_TYPE_LOW_2500BASE_X: 3444 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3445 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3446 break; 3447 case ICE_PHY_TYPE_LOW_5GBASE_T: 3448 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3449 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3450 break; 3451 case ICE_PHY_TYPE_LOW_10GBASE_T: 3452 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3453 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3454 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3455 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3456 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3457 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3458 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3459 break; 3460 case ICE_PHY_TYPE_LOW_25GBASE_T: 3461 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3462 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3463 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3464 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3465 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3466 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3467 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3468 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3469 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3470 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3471 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3472 break; 3473 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3474 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3475 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3476 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3477 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3478 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3479 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3480 break; 3481 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3482 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3483 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3484 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3485 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3486 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3487 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3488 case ICE_PHY_TYPE_LOW_50G_AUI2: 3489 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3490 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3491 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3492 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3493 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3494 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3495 case ICE_PHY_TYPE_LOW_50G_AUI1: 3496 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3497 break; 3498 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3499 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3500 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3501 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3502 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3503 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3504 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3505 case ICE_PHY_TYPE_LOW_100G_AUI4: 3506 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3507 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3508 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3509 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3510 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3511 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3512 break; 3513 default: 3514 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3515 break; 3516 } 3517 3518 switch (phy_type_high) { 3519 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3520 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3521 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3522 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3523 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3524 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3525 break; 3526 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3527 case ICE_PHY_TYPE_HIGH_200G_SR4: 3528 case ICE_PHY_TYPE_HIGH_200G_FR4: 3529 case ICE_PHY_TYPE_HIGH_200G_LR4: 3530 case ICE_PHY_TYPE_HIGH_200G_DR4: 3531 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3532 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3533 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3534 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3535 break; 3536 default: 3537 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3538 break; 3539 } 3540 3541 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3542 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3543 return ICE_AQ_LINK_SPEED_UNKNOWN; 3544 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3545 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3546 return ICE_AQ_LINK_SPEED_UNKNOWN; 3547 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3548 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3549 return speed_phy_type_low; 3550 else 3551 return speed_phy_type_high; 3552} 3553 3554/** 3555 * ice_update_phy_type 3556 * @phy_type_low: pointer to the lower part of phy_type 3557 * @phy_type_high: pointer to the higher part of phy_type 3558 * @link_speeds_bitmap: targeted link speeds bitmap 3559 * 3560 * Note: For the link_speeds_bitmap structure, you can check it at 3561 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3562 * link_speeds_bitmap include multiple speeds. 3563 * 3564 * Each entry in this [phy_type_low, phy_type_high] structure will 3565 * present a certain link speed. This helper function will turn on bits 3566 * in [phy_type_low, phy_type_high] structure based on the value of 3567 * link_speeds_bitmap input parameter. 3568 */ 3569void 3570ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3571 u16 link_speeds_bitmap) 3572{ 3573 u64 pt_high; 3574 u64 pt_low; 3575 int index; 3576 u16 speed; 3577 3578 /* We first check with low part of phy_type */ 3579 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3580 pt_low = BIT_ULL(index); 3581 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3582 3583 if (link_speeds_bitmap & speed) 3584 *phy_type_low |= BIT_ULL(index); 3585 } 3586 3587 /* We then check with high part of phy_type */ 3588 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3589 pt_high = BIT_ULL(index); 3590 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3591 3592 if (link_speeds_bitmap & speed) 3593 *phy_type_high |= BIT_ULL(index); 3594 } 3595} 3596 3597/** 3598 * ice_aq_set_phy_cfg 3599 * @hw: pointer to the HW struct 3600 * @pi: port info structure of the interested logical port 3601 * @cfg: structure with PHY configuration data to be set 3602 * @cd: pointer to command details structure or NULL 3603 * 3604 * Set the various PHY configuration parameters supported on the Port. 3605 * One or more of the Set PHY config parameters may be ignored in an MFP 3606 * mode as the PF may not have the privilege to set some of the PHY Config 3607 * parameters. This status will be indicated by the command response (0x0601). 3608 */ 3609int 3610ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3611 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3612{ 3613 struct ice_aqc_set_phy_cfg *cmd; 3614 struct libie_aq_desc desc; 3615 int status; 3616 3617 if (!cfg) 3618 return -EINVAL; 3619 3620 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3621 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3622 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3623 cfg->caps); 3624 3625 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3626 } 3627 3628 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3629 cmd = libie_aq_raw(&desc); 3630 cmd->lport_num = pi->lport; 3631 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3632 3633 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3634 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3635 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3636 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3637 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3638 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3639 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3640 cfg->low_power_ctrl_an); 3641 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3642 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3643 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3644 cfg->link_fec_opt); 3645 3646 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3647 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3648 status = 0; 3649 3650 if (!status) 3651 pi->phy.curr_user_phy_cfg = *cfg; 3652 3653 return status; 3654} 3655 3656/** 3657 * ice_update_link_info - update status of the HW network link 3658 * @pi: port info structure of the interested logical port 3659 */ 3660int ice_update_link_info(struct ice_port_info *pi) 3661{ 3662 struct ice_link_status *li; 3663 int status; 3664 3665 if (!pi) 3666 return -EINVAL; 3667 3668 li = &pi->phy.link_info; 3669 3670 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3671 if (status) 3672 return status; 3673 3674 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3675 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3676 3677 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3678 if (!pcaps) 3679 return -ENOMEM; 3680 3681 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3682 pcaps, NULL); 3683 } 3684 3685 return status; 3686} 3687 3688/** 3689 * ice_aq_get_phy_equalization - function to read serdes equaliser 3690 * value from firmware using admin queue command. 3691 * @hw: pointer to the HW struct 3692 * @data_in: represents the serdes equalization parameter requested 3693 * @op_code: represents the serdes number and flag to represent tx or rx 3694 * @serdes_num: represents the serdes number 3695 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3696 * 3697 * Return: non-zero status on error and 0 on success. 3698 */ 3699int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3700 u8 serdes_num, int *output) 3701{ 3702 struct ice_aqc_dnl_call_command *cmd; 3703 struct ice_aqc_dnl_call buf = {}; 3704 struct libie_aq_desc desc; 3705 int err; 3706 3707 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3708 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3709 cpu_to_le16(op_code | (serdes_num & 0xF)); 3710 cmd = libie_aq_raw(&desc); 3711 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3712 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3713 LIBIE_AQ_FLAG_RD | 3714 LIBIE_AQ_FLAG_SI); 3715 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3716 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3717 3718 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3719 NULL); 3720 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3721 3722 return err; 3723} 3724 3725#define FEC_REG_PORT(port) { \ 3726 FEC_CORR_LOW_REG_PORT##port, \ 3727 FEC_CORR_HIGH_REG_PORT##port, \ 3728 FEC_UNCORR_LOW_REG_PORT##port, \ 3729 FEC_UNCORR_HIGH_REG_PORT##port, \ 3730} 3731 3732static const u32 fec_reg[][ICE_FEC_MAX] = { 3733 FEC_REG_PORT(0), 3734 FEC_REG_PORT(1), 3735 FEC_REG_PORT(2), 3736 FEC_REG_PORT(3) 3737}; 3738 3739/** 3740 * ice_aq_get_fec_stats - reads fec stats from phy 3741 * @hw: pointer to the HW struct 3742 * @pcs_quad: represents pcsquad of user input serdes 3743 * @pcs_port: represents the pcs port number part of above pcs quad 3744 * @fec_type: represents FEC stats type 3745 * @output: pointer to the caller-supplied buffer to return requested fec stats 3746 * 3747 * Return: non-zero status on error and 0 on success. 3748 */ 3749int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3750 enum ice_fec_stats_types fec_type, u32 *output) 3751{ 3752 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3753 struct ice_sbq_msg_input msg = {}; 3754 u32 receiver_id, reg_offset; 3755 int err; 3756 3757 if (pcs_port > 3) 3758 return -EINVAL; 3759 3760 reg_offset = fec_reg[pcs_port][fec_type]; 3761 3762 if (pcs_quad == 0) 3763 receiver_id = FEC_RECEIVER_ID_PCS0; 3764 else if (pcs_quad == 1) 3765 receiver_id = FEC_RECEIVER_ID_PCS1; 3766 else 3767 return -EINVAL; 3768 3769 msg.msg_addr_low = lower_16_bits(reg_offset); 3770 msg.msg_addr_high = receiver_id; 3771 msg.opcode = ice_sbq_msg_rd; 3772 msg.dest_dev = ice_sbq_dev_phy_0; 3773 3774 err = ice_sbq_rw_reg(hw, &msg, flag); 3775 if (err) 3776 return err; 3777 3778 *output = msg.data; 3779 return 0; 3780} 3781 3782/** 3783 * ice_cache_phy_user_req 3784 * @pi: port information structure 3785 * @cache_data: PHY logging data 3786 * @cache_mode: PHY logging mode 3787 * 3788 * Log the user request on (FC, FEC, SPEED) for later use. 3789 */ 3790static void 3791ice_cache_phy_user_req(struct ice_port_info *pi, 3792 struct ice_phy_cache_mode_data cache_data, 3793 enum ice_phy_cache_mode cache_mode) 3794{ 3795 if (!pi) 3796 return; 3797 3798 switch (cache_mode) { 3799 case ICE_FC_MODE: 3800 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3801 break; 3802 case ICE_SPEED_MODE: 3803 pi->phy.curr_user_speed_req = 3804 cache_data.data.curr_user_speed_req; 3805 break; 3806 case ICE_FEC_MODE: 3807 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3808 break; 3809 default: 3810 break; 3811 } 3812} 3813 3814/** 3815 * ice_caps_to_fc_mode 3816 * @caps: PHY capabilities 3817 * 3818 * Convert PHY FC capabilities to ice FC mode 3819 */ 3820enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3821{ 3822 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3823 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3824 return ICE_FC_FULL; 3825 3826 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3827 return ICE_FC_TX_PAUSE; 3828 3829 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3830 return ICE_FC_RX_PAUSE; 3831 3832 return ICE_FC_NONE; 3833} 3834 3835/** 3836 * ice_caps_to_fec_mode 3837 * @caps: PHY capabilities 3838 * @fec_options: Link FEC options 3839 * 3840 * Convert PHY FEC capabilities to ice FEC mode 3841 */ 3842enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3843{ 3844 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3845 return ICE_FEC_AUTO; 3846 3847 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3848 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3849 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3850 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3851 return ICE_FEC_BASER; 3852 3853 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3854 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3855 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3856 return ICE_FEC_RS; 3857 3858 return ICE_FEC_NONE; 3859} 3860 3861/** 3862 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3863 * @pi: port information structure 3864 * @cfg: PHY configuration data to set FC mode 3865 * @req_mode: FC mode to configure 3866 */ 3867int 3868ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3869 enum ice_fc_mode req_mode) 3870{ 3871 struct ice_phy_cache_mode_data cache_data; 3872 u8 pause_mask = 0x0; 3873 3874 if (!pi || !cfg) 3875 return -EINVAL; 3876 3877 switch (req_mode) { 3878 case ICE_FC_FULL: 3879 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3880 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3881 break; 3882 case ICE_FC_RX_PAUSE: 3883 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3884 break; 3885 case ICE_FC_TX_PAUSE: 3886 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3887 break; 3888 default: 3889 break; 3890 } 3891 3892 /* clear the old pause settings */ 3893 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3894 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3895 3896 /* set the new capabilities */ 3897 cfg->caps |= pause_mask; 3898 3899 /* Cache user FC request */ 3900 cache_data.data.curr_user_fc_req = req_mode; 3901 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3902 3903 return 0; 3904} 3905 3906/** 3907 * ice_set_fc 3908 * @pi: port information structure 3909 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3910 * @ena_auto_link_update: enable automatic link update 3911 * 3912 * Set the requested flow control mode. 3913 */ 3914int 3915ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3916{ 3917 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3918 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3919 struct ice_hw *hw; 3920 int status; 3921 3922 if (!pi || !aq_failures) 3923 return -EINVAL; 3924 3925 *aq_failures = 0; 3926 hw = pi->hw; 3927 3928 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3929 if (!pcaps) 3930 return -ENOMEM; 3931 3932 /* Get the current PHY config */ 3933 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3934 pcaps, NULL); 3935 if (status) { 3936 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3937 goto out; 3938 } 3939 3940 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3941 3942 /* Configure the set PHY data */ 3943 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3944 if (status) 3945 goto out; 3946 3947 /* If the capabilities have changed, then set the new config */ 3948 if (cfg.caps != pcaps->caps) { 3949 int retry_count, retry_max = 10; 3950 3951 /* Auto restart link so settings take effect */ 3952 if (ena_auto_link_update) 3953 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3954 3955 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3956 if (status) { 3957 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3958 goto out; 3959 } 3960 3961 /* Update the link info 3962 * It sometimes takes a really long time for link to 3963 * come back from the atomic reset. Thus, we wait a 3964 * little bit. 3965 */ 3966 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3967 status = ice_update_link_info(pi); 3968 3969 if (!status) 3970 break; 3971 3972 mdelay(100); 3973 } 3974 3975 if (status) 3976 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3977 } 3978 3979out: 3980 return status; 3981} 3982 3983/** 3984 * ice_phy_caps_equals_cfg 3985 * @phy_caps: PHY capabilities 3986 * @phy_cfg: PHY configuration 3987 * 3988 * Helper function to determine if PHY capabilities matches PHY 3989 * configuration 3990 */ 3991bool 3992ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3993 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3994{ 3995 u8 caps_mask, cfg_mask; 3996 3997 if (!phy_caps || !phy_cfg) 3998 return false; 3999 4000 /* These bits are not common between capabilities and configuration. 4001 * Do not use them to determine equality. 4002 */ 4003 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 4004 ICE_AQC_GET_PHY_EN_MOD_QUAL); 4005 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 4006 4007 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 4008 phy_caps->phy_type_high != phy_cfg->phy_type_high || 4009 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 4010 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 4011 phy_caps->eee_cap != phy_cfg->eee_cap || 4012 phy_caps->eeer_value != phy_cfg->eeer_value || 4013 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 4014 return false; 4015 4016 return true; 4017} 4018 4019/** 4020 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 4021 * @pi: port information structure 4022 * @caps: PHY ability structure to copy date from 4023 * @cfg: PHY configuration structure to copy data to 4024 * 4025 * Helper function to copy AQC PHY get ability data to PHY set configuration 4026 * data structure 4027 */ 4028void 4029ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 4030 struct ice_aqc_get_phy_caps_data *caps, 4031 struct ice_aqc_set_phy_cfg_data *cfg) 4032{ 4033 if (!pi || !caps || !cfg) 4034 return; 4035 4036 memset(cfg, 0, sizeof(*cfg)); 4037 cfg->phy_type_low = caps->phy_type_low; 4038 cfg->phy_type_high = caps->phy_type_high; 4039 cfg->caps = caps->caps; 4040 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 4041 cfg->eee_cap = caps->eee_cap; 4042 cfg->eeer_value = caps->eeer_value; 4043 cfg->link_fec_opt = caps->link_fec_options; 4044 cfg->module_compliance_enforcement = 4045 caps->module_compliance_enforcement; 4046} 4047 4048/** 4049 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 4050 * @pi: port information structure 4051 * @cfg: PHY configuration data to set FEC mode 4052 * @fec: FEC mode to configure 4053 */ 4054int 4055ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 4056 enum ice_fec_mode fec) 4057{ 4058 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 4059 struct ice_hw *hw; 4060 int status; 4061 4062 if (!pi || !cfg) 4063 return -EINVAL; 4064 4065 hw = pi->hw; 4066 4067 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 4068 if (!pcaps) 4069 return -ENOMEM; 4070 4071 status = ice_aq_get_phy_caps(pi, false, 4072 (ice_fw_supports_report_dflt_cfg(hw) ? 4073 ICE_AQC_REPORT_DFLT_CFG : 4074 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 4075 if (status) 4076 goto out; 4077 4078 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 4079 cfg->link_fec_opt = pcaps->link_fec_options; 4080 4081 switch (fec) { 4082 case ICE_FEC_BASER: 4083 /* Clear RS bits, and AND BASE-R ability 4084 * bits and OR request bits. 4085 */ 4086 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 4087 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 4088 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4089 ICE_AQC_PHY_FEC_25G_KR_REQ; 4090 break; 4091 case ICE_FEC_RS: 4092 /* Clear BASE-R bits, and AND RS ability 4093 * bits and OR request bits. 4094 */ 4095 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4096 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4097 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4098 break; 4099 case ICE_FEC_NONE: 4100 /* Clear all FEC option bits. */ 4101 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4102 break; 4103 case ICE_FEC_AUTO: 4104 /* AND auto FEC bit, and all caps bits. */ 4105 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4106 cfg->link_fec_opt |= pcaps->link_fec_options; 4107 break; 4108 default: 4109 status = -EINVAL; 4110 break; 4111 } 4112 4113 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4114 !ice_fw_supports_report_dflt_cfg(hw)) { 4115 struct ice_link_default_override_tlv tlv = { 0 }; 4116 4117 status = ice_get_link_default_override(&tlv, pi); 4118 if (status) 4119 goto out; 4120 4121 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4122 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4123 cfg->link_fec_opt = tlv.fec_options; 4124 } 4125 4126out: 4127 return status; 4128} 4129 4130/** 4131 * ice_get_link_status - get status of the HW network link 4132 * @pi: port information structure 4133 * @link_up: pointer to bool (true/false = linkup/linkdown) 4134 * 4135 * Variable link_up is true if link is up, false if link is down. 4136 * The variable link_up is invalid if status is non zero. As a 4137 * result of this call, link status reporting becomes enabled 4138 */ 4139int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4140{ 4141 struct ice_phy_info *phy_info; 4142 int status = 0; 4143 4144 if (!pi || !link_up) 4145 return -EINVAL; 4146 4147 phy_info = &pi->phy; 4148 4149 if (phy_info->get_link_info) { 4150 status = ice_update_link_info(pi); 4151 4152 if (status) 4153 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4154 status); 4155 } 4156 4157 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4158 4159 return status; 4160} 4161 4162/** 4163 * ice_aq_set_link_restart_an 4164 * @pi: pointer to the port information structure 4165 * @ena_link: if true: enable link, if false: disable link 4166 * @cd: pointer to command details structure or NULL 4167 * 4168 * Sets up the link and restarts the Auto-Negotiation over the link. 4169 */ 4170int 4171ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4172 struct ice_sq_cd *cd) 4173{ 4174 struct ice_aqc_restart_an *cmd; 4175 struct libie_aq_desc desc; 4176 4177 cmd = libie_aq_raw(&desc); 4178 4179 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4180 4181 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4182 cmd->lport_num = pi->lport; 4183 if (ena_link) 4184 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4185 else 4186 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4187 4188 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4189} 4190 4191/** 4192 * ice_aq_set_event_mask 4193 * @hw: pointer to the HW struct 4194 * @port_num: port number of the physical function 4195 * @mask: event mask to be set 4196 * @cd: pointer to command details structure or NULL 4197 * 4198 * Set event mask (0x0613) 4199 */ 4200int 4201ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4202 struct ice_sq_cd *cd) 4203{ 4204 struct ice_aqc_set_event_mask *cmd; 4205 struct libie_aq_desc desc; 4206 4207 cmd = libie_aq_raw(&desc); 4208 4209 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4210 4211 cmd->lport_num = port_num; 4212 4213 cmd->event_mask = cpu_to_le16(mask); 4214 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4215} 4216 4217/** 4218 * ice_aq_set_mac_loopback 4219 * @hw: pointer to the HW struct 4220 * @ena_lpbk: Enable or Disable loopback 4221 * @cd: pointer to command details structure or NULL 4222 * 4223 * Enable/disable loopback on a given port 4224 */ 4225int 4226ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4227{ 4228 struct ice_aqc_set_mac_lb *cmd; 4229 struct libie_aq_desc desc; 4230 4231 cmd = libie_aq_raw(&desc); 4232 4233 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4234 if (ena_lpbk) 4235 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4236 4237 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4238} 4239 4240/** 4241 * ice_aq_set_port_id_led 4242 * @pi: pointer to the port information 4243 * @is_orig_mode: is this LED set to original mode (by the net-list) 4244 * @cd: pointer to command details structure or NULL 4245 * 4246 * Set LED value for the given port (0x06e9) 4247 */ 4248int 4249ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4250 struct ice_sq_cd *cd) 4251{ 4252 struct ice_aqc_set_port_id_led *cmd; 4253 struct ice_hw *hw = pi->hw; 4254 struct libie_aq_desc desc; 4255 4256 cmd = libie_aq_raw(&desc); 4257 4258 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4259 4260 if (is_orig_mode) 4261 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4262 else 4263 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4264 4265 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4266} 4267 4268/** 4269 * ice_aq_get_port_options 4270 * @hw: pointer to the HW struct 4271 * @options: buffer for the resultant port options 4272 * @option_count: input - size of the buffer in port options structures, 4273 * output - number of returned port options 4274 * @lport: logical port to call the command with (optional) 4275 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4276 * when PF owns more than 1 port it must be true 4277 * @active_option_idx: index of active port option in returned buffer 4278 * @active_option_valid: active option in returned buffer is valid 4279 * @pending_option_idx: index of pending port option in returned buffer 4280 * @pending_option_valid: pending option in returned buffer is valid 4281 * 4282 * Calls Get Port Options AQC (0x06ea) and verifies result. 4283 */ 4284int 4285ice_aq_get_port_options(struct ice_hw *hw, 4286 struct ice_aqc_get_port_options_elem *options, 4287 u8 *option_count, u8 lport, bool lport_valid, 4288 u8 *active_option_idx, bool *active_option_valid, 4289 u8 *pending_option_idx, bool *pending_option_valid) 4290{ 4291 struct ice_aqc_get_port_options *cmd; 4292 struct libie_aq_desc desc; 4293 int status; 4294 u8 i; 4295 4296 /* options buffer shall be able to hold max returned options */ 4297 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4298 return -EINVAL; 4299 4300 cmd = libie_aq_raw(&desc); 4301 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4302 4303 if (lport_valid) 4304 cmd->lport_num = lport; 4305 cmd->lport_num_valid = lport_valid; 4306 4307 status = ice_aq_send_cmd(hw, &desc, options, 4308 *option_count * sizeof(*options), NULL); 4309 if (status) 4310 return status; 4311 4312 /* verify direct FW response & set output parameters */ 4313 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4314 cmd->port_options_count); 4315 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4316 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4317 cmd->port_options); 4318 if (*active_option_valid) { 4319 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4320 cmd->port_options); 4321 if (*active_option_idx > (*option_count - 1)) 4322 return -EIO; 4323 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4324 *active_option_idx); 4325 } 4326 4327 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4328 cmd->pending_port_option_status); 4329 if (*pending_option_valid) { 4330 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4331 cmd->pending_port_option_status); 4332 if (*pending_option_idx > (*option_count - 1)) 4333 return -EIO; 4334 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4335 *pending_option_idx); 4336 } 4337 4338 /* mask output options fields */ 4339 for (i = 0; i < *option_count; i++) { 4340 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4341 options[i].pmd); 4342 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4343 options[i].max_lane_speed); 4344 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4345 options[i].pmd, options[i].max_lane_speed); 4346 } 4347 4348 return 0; 4349} 4350 4351/** 4352 * ice_aq_set_port_option 4353 * @hw: pointer to the HW struct 4354 * @lport: logical port to call the command with 4355 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4356 * when PF owns more than 1 port it must be true 4357 * @new_option: new port option to be written 4358 * 4359 * Calls Set Port Options AQC (0x06eb). 4360 */ 4361int 4362ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4363 u8 new_option) 4364{ 4365 struct ice_aqc_set_port_option *cmd; 4366 struct libie_aq_desc desc; 4367 4368 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4369 return -EINVAL; 4370 4371 cmd = libie_aq_raw(&desc); 4372 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4373 4374 if (lport_valid) 4375 cmd->lport_num = lport; 4376 4377 cmd->lport_num_valid = lport_valid; 4378 cmd->selected_port_option = new_option; 4379 4380 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4381} 4382 4383/** 4384 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4385 * @hw: pointer to the hw struct 4386 * 4387 * Return: PHY lane number on success, negative error code otherwise. 4388 */ 4389int ice_get_phy_lane_number(struct ice_hw *hw) 4390{ 4391 struct ice_aqc_get_port_options_elem *options; 4392 unsigned int lport = 0; 4393 unsigned int lane; 4394 int err; 4395 4396 /* E82X does not have sequential IDs, lane number is PF ID. 4397 * For E825 device, the exception is the variant with external 4398 * PHY (0x579F), in which there is also 1:1 pf_id -> lane_number 4399 * mapping. 4400 */ 4401 if (hw->mac_type == ICE_MAC_GENERIC || 4402 hw->device_id == ICE_DEV_ID_E825C_SGMII) 4403 return hw->pf_id; 4404 4405 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); 4406 if (!options) 4407 return -ENOMEM; 4408 4409 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4410 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4411 u8 speed, active_idx, pending_idx; 4412 bool active_valid, pending_valid; 4413 4414 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4415 true, &active_idx, &active_valid, 4416 &pending_idx, &pending_valid); 4417 if (err) 4418 goto err; 4419 4420 if (!active_valid) 4421 continue; 4422 4423 speed = options[active_idx].max_lane_speed; 4424 /* If we don't get speed for this lane, it's unoccupied */ 4425 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4426 continue; 4427 4428 if (hw->pf_id == lport) { 4429 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4430 ice_is_dual(hw) && !ice_is_primary(hw)) 4431 lane += ICE_PORTS_PER_QUAD; 4432 kfree(options); 4433 return lane; 4434 } 4435 lport++; 4436 } 4437 4438 /* PHY lane not found */ 4439 err = -ENXIO; 4440err: 4441 kfree(options); 4442 return err; 4443} 4444 4445/** 4446 * ice_aq_sff_eeprom 4447 * @hw: pointer to the HW struct 4448 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4449 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4450 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4451 * @page: QSFP page 4452 * @set_page: set or ignore the page 4453 * @data: pointer to data buffer to be read/written to the I2C device. 4454 * @length: 1-16 for read, 1 for write. 4455 * @write: 0 read, 1 for write. 4456 * @cd: pointer to command details structure or NULL 4457 * 4458 * Read/Write SFF EEPROM (0x06EE) 4459 */ 4460int 4461ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4462 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4463 bool write, struct ice_sq_cd *cd) 4464{ 4465 struct ice_aqc_sff_eeprom *cmd; 4466 struct libie_aq_desc desc; 4467 u16 i2c_bus_addr; 4468 int status; 4469 4470 if (!data || (mem_addr & 0xff00)) 4471 return -EINVAL; 4472 4473 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4474 cmd = libie_aq_raw(&desc); 4475 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4476 cmd->lport_num = (u8)(lport & 0xff); 4477 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4478 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4479 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4480 if (write) 4481 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4482 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4483 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4484 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4485 4486 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4487 return status; 4488} 4489 4490static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4491{ 4492 switch (type) { 4493 case ICE_LUT_VSI: 4494 return ICE_LUT_VSI_SIZE; 4495 case ICE_LUT_GLOBAL: 4496 return ICE_LUT_GLOBAL_SIZE; 4497 case ICE_LUT_PF: 4498 return ICE_LUT_PF_SIZE; 4499 } 4500 WARN_ONCE(1, "incorrect type passed"); 4501 return ICE_LUT_VSI_SIZE; 4502} 4503 4504static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4505{ 4506 switch (size) { 4507 case ICE_LUT_VSI_SIZE: 4508 return ICE_AQC_LUT_SIZE_SMALL; 4509 case ICE_LUT_GLOBAL_SIZE: 4510 return ICE_AQC_LUT_SIZE_512; 4511 case ICE_LUT_PF_SIZE: 4512 return ICE_AQC_LUT_SIZE_2K; 4513 } 4514 WARN_ONCE(1, "incorrect size passed"); 4515 return 0; 4516} 4517 4518/** 4519 * __ice_aq_get_set_rss_lut 4520 * @hw: pointer to the hardware structure 4521 * @params: RSS LUT parameters 4522 * @set: set true to set the table, false to get the table 4523 * 4524 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4525 */ 4526static int 4527__ice_aq_get_set_rss_lut(struct ice_hw *hw, 4528 struct ice_aq_get_set_rss_lut_params *params, bool set) 4529{ 4530 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4531 enum ice_lut_type lut_type = params->lut_type; 4532 struct ice_aqc_get_set_rss_lut *desc_params; 4533 enum ice_aqc_lut_flags flags; 4534 enum ice_lut_size lut_size; 4535 struct libie_aq_desc desc; 4536 u8 *lut = params->lut; 4537 4538 4539 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4540 return -EINVAL; 4541 4542 lut_size = ice_lut_type_to_size(lut_type); 4543 if (lut_size > params->lut_size) 4544 return -EINVAL; 4545 else if (set && lut_size != params->lut_size) 4546 return -EINVAL; 4547 4548 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4549 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4550 if (set) 4551 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4552 4553 desc_params = libie_aq_raw(&desc); 4554 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4555 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4556 4557 if (lut_type == ICE_LUT_GLOBAL) 4558 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4559 params->global_lut_id); 4560 4561 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4562 desc_params->flags = cpu_to_le16(flags); 4563 4564 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4565} 4566 4567/** 4568 * ice_aq_get_rss_lut 4569 * @hw: pointer to the hardware structure 4570 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4571 * 4572 * get the RSS lookup table, PF or VSI type 4573 */ 4574int 4575ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4576{ 4577 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4578} 4579 4580/** 4581 * ice_aq_set_rss_lut 4582 * @hw: pointer to the hardware structure 4583 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4584 * 4585 * set the RSS lookup table, PF or VSI type 4586 */ 4587int 4588ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4589{ 4590 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4591} 4592 4593/** 4594 * __ice_aq_get_set_rss_key 4595 * @hw: pointer to the HW struct 4596 * @vsi_id: VSI FW index 4597 * @key: pointer to key info struct 4598 * @set: set true to set the key, false to get the key 4599 * 4600 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4601 */ 4602static int 4603__ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4604 struct ice_aqc_get_set_rss_keys *key, bool set) 4605{ 4606 struct ice_aqc_get_set_rss_key *desc_params; 4607 u16 key_size = sizeof(*key); 4608 struct libie_aq_desc desc; 4609 4610 if (set) { 4611 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4612 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4613 } else { 4614 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4615 } 4616 4617 desc_params = libie_aq_raw(&desc); 4618 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4619 4620 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4621} 4622 4623/** 4624 * ice_aq_get_rss_key 4625 * @hw: pointer to the HW struct 4626 * @vsi_handle: software VSI handle 4627 * @key: pointer to key info struct 4628 * 4629 * get the RSS key per VSI 4630 */ 4631int 4632ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4633 struct ice_aqc_get_set_rss_keys *key) 4634{ 4635 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4636 return -EINVAL; 4637 4638 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4639 key, false); 4640} 4641 4642/** 4643 * ice_aq_set_rss_key 4644 * @hw: pointer to the HW struct 4645 * @vsi_handle: software VSI handle 4646 * @keys: pointer to key info struct 4647 * 4648 * set the RSS key per VSI 4649 */ 4650int 4651ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4652 struct ice_aqc_get_set_rss_keys *keys) 4653{ 4654 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4655 return -EINVAL; 4656 4657 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4658 keys, true); 4659} 4660 4661/** 4662 * ice_aq_add_lan_txq 4663 * @hw: pointer to the hardware structure 4664 * @num_qgrps: Number of added queue groups 4665 * @qg_list: list of queue groups to be added 4666 * @buf_size: size of buffer for indirect command 4667 * @cd: pointer to command details structure or NULL 4668 * 4669 * Add Tx LAN queue (0x0C30) 4670 * 4671 * NOTE: 4672 * Prior to calling add Tx LAN queue: 4673 * Initialize the following as part of the Tx queue context: 4674 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4675 * Cache profile and Packet shaper profile. 4676 * 4677 * After add Tx LAN queue AQ command is completed: 4678 * Interrupts should be associated with specific queues, 4679 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4680 * flow. 4681 */ 4682static int 4683ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4684 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4685 struct ice_sq_cd *cd) 4686{ 4687 struct ice_aqc_add_tx_qgrp *list; 4688 struct ice_aqc_add_txqs *cmd; 4689 struct libie_aq_desc desc; 4690 u16 i, sum_size = 0; 4691 4692 cmd = libie_aq_raw(&desc); 4693 4694 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4695 4696 if (!qg_list) 4697 return -EINVAL; 4698 4699 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4700 return -EINVAL; 4701 4702 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4703 sum_size += struct_size(list, txqs, list->num_txqs); 4704 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4705 list->num_txqs); 4706 } 4707 4708 if (buf_size != sum_size) 4709 return -EINVAL; 4710 4711 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4712 4713 cmd->num_qgrps = num_qgrps; 4714 4715 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4716} 4717 4718/** 4719 * ice_aq_dis_lan_txq 4720 * @hw: pointer to the hardware structure 4721 * @num_qgrps: number of groups in the list 4722 * @qg_list: the list of groups to disable 4723 * @buf_size: the total size of the qg_list buffer in bytes 4724 * @rst_src: if called due to reset, specifies the reset source 4725 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4726 * @cd: pointer to command details structure or NULL 4727 * 4728 * Disable LAN Tx queue (0x0C31) 4729 */ 4730static int 4731ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4732 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4733 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4734 struct ice_sq_cd *cd) 4735{ 4736 struct ice_aqc_dis_txq_item *item; 4737 struct ice_aqc_dis_txqs *cmd; 4738 struct libie_aq_desc desc; 4739 u16 vmvf_and_timeout; 4740 u16 i, sz = 0; 4741 int status; 4742 4743 cmd = libie_aq_raw(&desc); 4744 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4745 4746 /* qg_list can be NULL only in VM/VF reset flow */ 4747 if (!qg_list && !rst_src) 4748 return -EINVAL; 4749 4750 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4751 return -EINVAL; 4752 4753 cmd->num_entries = num_qgrps; 4754 4755 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4756 4757 switch (rst_src) { 4758 case ICE_VM_RESET: 4759 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4760 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4761 break; 4762 case ICE_VF_RESET: 4763 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4764 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4765 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4766 ICE_AQC_Q_DIS_VMVF_NUM_M; 4767 break; 4768 case ICE_NO_RESET: 4769 default: 4770 break; 4771 } 4772 4773 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4774 4775 /* flush pipe on time out */ 4776 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4777 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4778 if (!qg_list) 4779 goto do_aq; 4780 4781 /* set RD bit to indicate that command buffer is provided by the driver 4782 * and it needs to be read by the firmware 4783 */ 4784 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4785 4786 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4787 u16 item_size = struct_size(item, q_id, item->num_qs); 4788 4789 /* If the num of queues is even, add 2 bytes of padding */ 4790 if ((item->num_qs % 2) == 0) 4791 item_size += 2; 4792 4793 sz += item_size; 4794 4795 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4796 } 4797 4798 if (buf_size != sz) 4799 return -EINVAL; 4800 4801do_aq: 4802 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4803 if (status) { 4804 if (!qg_list) 4805 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4806 vmvf_num, hw->adminq.sq_last_status); 4807 else 4808 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4809 le16_to_cpu(qg_list[0].q_id[0]), 4810 hw->adminq.sq_last_status); 4811 } 4812 return status; 4813} 4814 4815/** 4816 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4817 * @hw: pointer to the hardware structure 4818 * @buf: buffer for command 4819 * @buf_size: size of buffer in bytes 4820 * @num_qs: number of queues being configured 4821 * @oldport: origination lport 4822 * @newport: destination lport 4823 * @mode: cmd_type for move to use 4824 * @cd: pointer to command details structure or NULL 4825 * 4826 * Move/Configure LAN Tx queue (0x0C32) 4827 * 4828 * Return: Zero on success, associated error code on failure. 4829 */ 4830int 4831ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4832 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4833 u8 mode, struct ice_sq_cd *cd) 4834{ 4835 struct ice_aqc_cfg_txqs *cmd; 4836 struct libie_aq_desc desc; 4837 int status; 4838 4839 cmd = libie_aq_raw(&desc); 4840 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4841 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4842 4843 if (!buf) 4844 return -EINVAL; 4845 4846 cmd->cmd_type = mode; 4847 cmd->num_qs = num_qs; 4848 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4849 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4850 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4851 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4852 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4853 cmd->blocked_cgds = 0; 4854 4855 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4856 if (status) 4857 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4858 hw->adminq.sq_last_status); 4859 return status; 4860} 4861 4862/** 4863 * ice_aq_add_rdma_qsets 4864 * @hw: pointer to the hardware structure 4865 * @num_qset_grps: Number of RDMA Qset groups 4866 * @qset_list: list of Qset groups to be added 4867 * @buf_size: size of buffer for indirect command 4868 * @cd: pointer to command details structure or NULL 4869 * 4870 * Add Tx RDMA Qsets (0x0C33) 4871 */ 4872static int 4873ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4874 struct ice_aqc_add_rdma_qset_data *qset_list, 4875 u16 buf_size, struct ice_sq_cd *cd) 4876{ 4877 struct ice_aqc_add_rdma_qset_data *list; 4878 struct ice_aqc_add_rdma_qset *cmd; 4879 struct libie_aq_desc desc; 4880 u16 i, sum_size = 0; 4881 4882 cmd = libie_aq_raw(&desc); 4883 4884 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4885 4886 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4887 return -EINVAL; 4888 4889 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4890 u16 num_qsets = le16_to_cpu(list->num_qsets); 4891 4892 sum_size += struct_size(list, rdma_qsets, num_qsets); 4893 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4894 num_qsets); 4895 } 4896 4897 if (buf_size != sum_size) 4898 return -EINVAL; 4899 4900 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4901 4902 cmd->num_qset_grps = num_qset_grps; 4903 4904 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4905} 4906 4907/** 4908 * ice_aq_set_txtimeq - set Tx time queues 4909 * @hw: pointer to the hardware structure 4910 * @txtimeq: first Tx time queue id to configure 4911 * @q_count: number of queues to configure 4912 * @txtime_qg: queue group to be set 4913 * @buf_size: size of buffer for indirect command 4914 * @cd: pointer to command details structure or NULL 4915 * 4916 * Set Tx Time queue (0x0C35) 4917 * Return: 0 on success or negative value on failure. 4918 */ 4919int 4920ice_aq_set_txtimeq(struct ice_hw *hw, u16 txtimeq, u8 q_count, 4921 struct ice_aqc_set_txtime_qgrp *txtime_qg, u16 buf_size, 4922 struct ice_sq_cd *cd) 4923{ 4924 struct ice_aqc_set_txtimeqs *cmd; 4925 struct libie_aq_desc desc; 4926 u16 size; 4927 4928 if (!txtime_qg || txtimeq > ICE_TXTIME_MAX_QUEUE || 4929 q_count < 1 || q_count > ICE_SET_TXTIME_MAX_Q_AMOUNT) 4930 return -EINVAL; 4931 4932 size = struct_size(txtime_qg, txtimeqs, q_count); 4933 if (buf_size != size) 4934 return -EINVAL; 4935 4936 cmd = libie_aq_raw(&desc); 4937 4938 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_txtimeqs); 4939 4940 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4941 4942 cmd->q_id = cpu_to_le16(txtimeq); 4943 cmd->q_amount = cpu_to_le16(q_count); 4944 return ice_aq_send_cmd(hw, &desc, txtime_qg, buf_size, cd); 4945} 4946 4947/* End of FW Admin Queue command wrappers */ 4948 4949/** 4950 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4951 * @hw: pointer to the HW struct 4952 * @vsi_handle: software VSI handle 4953 * @tc: TC number 4954 * @q_handle: software queue handle 4955 */ 4956struct ice_q_ctx * 4957ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4958{ 4959 struct ice_vsi_ctx *vsi; 4960 struct ice_q_ctx *q_ctx; 4961 4962 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4963 if (!vsi) 4964 return NULL; 4965 if (q_handle >= vsi->num_lan_q_entries[tc]) 4966 return NULL; 4967 if (!vsi->lan_q_ctx[tc]) 4968 return NULL; 4969 q_ctx = vsi->lan_q_ctx[tc]; 4970 return &q_ctx[q_handle]; 4971} 4972 4973/** 4974 * ice_ena_vsi_txq 4975 * @pi: port information structure 4976 * @vsi_handle: software VSI handle 4977 * @tc: TC number 4978 * @q_handle: software queue handle 4979 * @num_qgrps: Number of added queue groups 4980 * @buf: list of queue groups to be added 4981 * @buf_size: size of buffer for indirect command 4982 * @cd: pointer to command details structure or NULL 4983 * 4984 * This function adds one LAN queue 4985 */ 4986int 4987ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4988 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4989 struct ice_sq_cd *cd) 4990{ 4991 struct ice_aqc_txsched_elem_data node = { 0 }; 4992 struct ice_sched_node *parent; 4993 struct ice_q_ctx *q_ctx; 4994 struct ice_hw *hw; 4995 int status; 4996 4997 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4998 return -EIO; 4999 5000 if (num_qgrps > 1 || buf->num_txqs > 1) 5001 return -ENOSPC; 5002 5003 hw = pi->hw; 5004 5005 if (!ice_is_vsi_valid(hw, vsi_handle)) 5006 return -EINVAL; 5007 5008 mutex_lock(&pi->sched_lock); 5009 5010 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 5011 if (!q_ctx) { 5012 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 5013 q_handle); 5014 status = -EINVAL; 5015 goto ena_txq_exit; 5016 } 5017 5018 /* find a parent node */ 5019 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5020 ICE_SCHED_NODE_OWNER_LAN); 5021 if (!parent) { 5022 status = -EINVAL; 5023 goto ena_txq_exit; 5024 } 5025 5026 buf->parent_teid = parent->info.node_teid; 5027 node.parent_teid = parent->info.node_teid; 5028 /* Mark that the values in the "generic" section as valid. The default 5029 * value in the "generic" section is zero. This means that : 5030 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 5031 * - 0 priority among siblings, indicated by Bit 1-3. 5032 * - WFQ, indicated by Bit 4. 5033 * - 0 Adjustment value is used in PSM credit update flow, indicated by 5034 * Bit 5-6. 5035 * - Bit 7 is reserved. 5036 * Without setting the generic section as valid in valid_sections, the 5037 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 5038 */ 5039 buf->txqs[0].info.valid_sections = 5040 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5041 ICE_AQC_ELEM_VALID_EIR; 5042 buf->txqs[0].info.generic = 0; 5043 buf->txqs[0].info.cir_bw.bw_profile_idx = 5044 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5045 buf->txqs[0].info.cir_bw.bw_alloc = 5046 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5047 buf->txqs[0].info.eir_bw.bw_profile_idx = 5048 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5049 buf->txqs[0].info.eir_bw.bw_alloc = 5050 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5051 5052 /* add the LAN queue */ 5053 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 5054 if (status) { 5055 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 5056 le16_to_cpu(buf->txqs[0].txq_id), 5057 hw->adminq.sq_last_status); 5058 goto ena_txq_exit; 5059 } 5060 5061 node.node_teid = buf->txqs[0].q_teid; 5062 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5063 q_ctx->q_handle = q_handle; 5064 q_ctx->q_teid = le32_to_cpu(node.node_teid); 5065 5066 /* add a leaf node into scheduler tree queue layer */ 5067 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 5068 if (!status) 5069 status = ice_sched_replay_q_bw(pi, q_ctx); 5070 5071ena_txq_exit: 5072 mutex_unlock(&pi->sched_lock); 5073 return status; 5074} 5075 5076/** 5077 * ice_dis_vsi_txq 5078 * @pi: port information structure 5079 * @vsi_handle: software VSI handle 5080 * @tc: TC number 5081 * @num_queues: number of queues 5082 * @q_handles: pointer to software queue handle array 5083 * @q_ids: pointer to the q_id array 5084 * @q_teids: pointer to queue node teids 5085 * @rst_src: if called due to reset, specifies the reset source 5086 * @vmvf_num: the relative VM or VF number that is undergoing the reset 5087 * @cd: pointer to command details structure or NULL 5088 * 5089 * This function removes queues and their corresponding nodes in SW DB 5090 */ 5091int 5092ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 5093 u16 *q_handles, u16 *q_ids, u32 *q_teids, 5094 enum ice_disq_rst_src rst_src, u16 vmvf_num, 5095 struct ice_sq_cd *cd) 5096{ 5097 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5098 u16 i, buf_size = __struct_size(qg_list); 5099 struct ice_q_ctx *q_ctx; 5100 int status = -ENOENT; 5101 struct ice_hw *hw; 5102 5103 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5104 return -EIO; 5105 5106 hw = pi->hw; 5107 5108 if (!num_queues) { 5109 /* if queue is disabled already yet the disable queue command 5110 * has to be sent to complete the VF reset, then call 5111 * ice_aq_dis_lan_txq without any queue information 5112 */ 5113 if (rst_src) 5114 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5115 vmvf_num, NULL); 5116 return -EIO; 5117 } 5118 5119 mutex_lock(&pi->sched_lock); 5120 5121 for (i = 0; i < num_queues; i++) { 5122 struct ice_sched_node *node; 5123 5124 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5125 if (!node) 5126 continue; 5127 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5128 if (!q_ctx) { 5129 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5130 q_handles[i]); 5131 continue; 5132 } 5133 if (q_ctx->q_handle != q_handles[i]) { 5134 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5135 q_ctx->q_handle, q_handles[i]); 5136 continue; 5137 } 5138 qg_list->parent_teid = node->info.parent_teid; 5139 qg_list->num_qs = 1; 5140 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5141 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5142 vmvf_num, cd); 5143 5144 if (status) 5145 break; 5146 ice_free_sched_node(pi, node); 5147 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5148 q_ctx->q_teid = ICE_INVAL_TEID; 5149 } 5150 mutex_unlock(&pi->sched_lock); 5151 return status; 5152} 5153 5154/** 5155 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5156 * @pi: port information structure 5157 * @vsi_handle: software VSI handle 5158 * @tc_bitmap: TC bitmap 5159 * @maxqs: max queues array per TC 5160 * @owner: LAN or RDMA 5161 * 5162 * This function adds/updates the VSI queues per TC. 5163 */ 5164static int 5165ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5166 u16 *maxqs, u8 owner) 5167{ 5168 int status = 0; 5169 u8 i; 5170 5171 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5172 return -EIO; 5173 5174 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5175 return -EINVAL; 5176 5177 mutex_lock(&pi->sched_lock); 5178 5179 ice_for_each_traffic_class(i) { 5180 /* configuration is possible only if TC node is present */ 5181 if (!ice_sched_get_tc_node(pi, i)) 5182 continue; 5183 5184 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5185 ice_is_tc_ena(tc_bitmap, i)); 5186 if (status) 5187 break; 5188 } 5189 5190 mutex_unlock(&pi->sched_lock); 5191 return status; 5192} 5193 5194/** 5195 * ice_cfg_vsi_lan - configure VSI LAN queues 5196 * @pi: port information structure 5197 * @vsi_handle: software VSI handle 5198 * @tc_bitmap: TC bitmap 5199 * @max_lanqs: max LAN queues array per TC 5200 * 5201 * This function adds/updates the VSI LAN queues per TC. 5202 */ 5203int 5204ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5205 u16 *max_lanqs) 5206{ 5207 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5208 ICE_SCHED_NODE_OWNER_LAN); 5209} 5210 5211/** 5212 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5213 * @pi: port information structure 5214 * @vsi_handle: software VSI handle 5215 * @tc_bitmap: TC bitmap 5216 * @max_rdmaqs: max RDMA queues array per TC 5217 * 5218 * This function adds/updates the VSI RDMA queues per TC. 5219 */ 5220int 5221ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5222 u16 *max_rdmaqs) 5223{ 5224 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5225 ICE_SCHED_NODE_OWNER_RDMA); 5226} 5227 5228/** 5229 * ice_ena_vsi_rdma_qset 5230 * @pi: port information structure 5231 * @vsi_handle: software VSI handle 5232 * @tc: TC number 5233 * @rdma_qset: pointer to RDMA Qset 5234 * @num_qsets: number of RDMA Qsets 5235 * @qset_teid: pointer to Qset node TEIDs 5236 * 5237 * This function adds RDMA Qset 5238 */ 5239int 5240ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5241 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5242{ 5243 struct ice_aqc_txsched_elem_data node = { 0 }; 5244 struct ice_aqc_add_rdma_qset_data *buf; 5245 struct ice_sched_node *parent; 5246 struct ice_hw *hw; 5247 u16 i, buf_size; 5248 int ret; 5249 5250 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5251 return -EIO; 5252 hw = pi->hw; 5253 5254 if (!ice_is_vsi_valid(hw, vsi_handle)) 5255 return -EINVAL; 5256 5257 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5258 buf = kzalloc(buf_size, GFP_KERNEL); 5259 if (!buf) 5260 return -ENOMEM; 5261 mutex_lock(&pi->sched_lock); 5262 5263 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5264 ICE_SCHED_NODE_OWNER_RDMA); 5265 if (!parent) { 5266 ret = -EINVAL; 5267 goto rdma_error_exit; 5268 } 5269 buf->parent_teid = parent->info.node_teid; 5270 node.parent_teid = parent->info.node_teid; 5271 5272 buf->num_qsets = cpu_to_le16(num_qsets); 5273 for (i = 0; i < num_qsets; i++) { 5274 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5275 buf->rdma_qsets[i].info.valid_sections = 5276 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5277 ICE_AQC_ELEM_VALID_EIR; 5278 buf->rdma_qsets[i].info.generic = 0; 5279 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5280 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5281 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5282 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5283 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5284 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5285 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5286 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5287 } 5288 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5289 if (ret) { 5290 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5291 goto rdma_error_exit; 5292 } 5293 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5294 for (i = 0; i < num_qsets; i++) { 5295 node.node_teid = buf->rdma_qsets[i].qset_teid; 5296 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5297 &node, NULL); 5298 if (ret) 5299 break; 5300 qset_teid[i] = le32_to_cpu(node.node_teid); 5301 } 5302rdma_error_exit: 5303 mutex_unlock(&pi->sched_lock); 5304 kfree(buf); 5305 return ret; 5306} 5307 5308/** 5309 * ice_dis_vsi_rdma_qset - free RDMA resources 5310 * @pi: port_info struct 5311 * @count: number of RDMA Qsets to free 5312 * @qset_teid: TEID of Qset node 5313 * @q_id: list of queue IDs being disabled 5314 */ 5315int 5316ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5317 u16 *q_id) 5318{ 5319 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5320 u16 qg_size = __struct_size(qg_list); 5321 struct ice_hw *hw; 5322 int status = 0; 5323 int i; 5324 5325 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5326 return -EIO; 5327 5328 hw = pi->hw; 5329 5330 mutex_lock(&pi->sched_lock); 5331 5332 for (i = 0; i < count; i++) { 5333 struct ice_sched_node *node; 5334 5335 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5336 if (!node) 5337 continue; 5338 5339 qg_list->parent_teid = node->info.parent_teid; 5340 qg_list->num_qs = 1; 5341 qg_list->q_id[0] = 5342 cpu_to_le16(q_id[i] | 5343 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5344 5345 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5346 ICE_NO_RESET, 0, NULL); 5347 if (status) 5348 break; 5349 5350 ice_free_sched_node(pi, node); 5351 } 5352 5353 mutex_unlock(&pi->sched_lock); 5354 return status; 5355} 5356 5357/** 5358 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5359 * @hw: pointer to the HW struct 5360 * @dpll_idx: index of dpll to be measured 5361 * @meas: array to be filled with results 5362 * @meas_num: max number of results array can hold 5363 * 5364 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5365 * pins on given dpll. 5366 * 5367 * Return: 0 on success or negative value on failure. 5368 */ 5369int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5370 struct ice_cgu_input_measure *meas, 5371 u16 meas_num) 5372{ 5373 struct ice_aqc_get_cgu_input_measure *cmd; 5374 struct libie_aq_desc desc; 5375 5376 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5377 cmd = libie_aq_raw(&desc); 5378 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5379 5380 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5381} 5382 5383/** 5384 * ice_aq_get_cgu_abilities - get cgu abilities 5385 * @hw: pointer to the HW struct 5386 * @abilities: CGU abilities 5387 * 5388 * Get CGU abilities (0x0C61) 5389 * Return: 0 on success or negative value on failure. 5390 */ 5391int 5392ice_aq_get_cgu_abilities(struct ice_hw *hw, 5393 struct ice_aqc_get_cgu_abilities *abilities) 5394{ 5395 struct libie_aq_desc desc; 5396 5397 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5398 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5399} 5400 5401/** 5402 * ice_aq_set_input_pin_cfg - set input pin config 5403 * @hw: pointer to the HW struct 5404 * @input_idx: Input index 5405 * @flags1: Input flags 5406 * @flags2: Input flags 5407 * @freq: Frequency in Hz 5408 * @phase_delay: Delay in ps 5409 * 5410 * Set CGU input config (0x0C62) 5411 * Return: 0 on success or negative value on failure. 5412 */ 5413int 5414ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5415 u32 freq, s32 phase_delay) 5416{ 5417 struct ice_aqc_set_cgu_input_config *cmd; 5418 struct libie_aq_desc desc; 5419 5420 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5421 cmd = libie_aq_raw(&desc); 5422 cmd->input_idx = input_idx; 5423 cmd->flags1 = flags1; 5424 cmd->flags2 = flags2; 5425 cmd->freq = cpu_to_le32(freq); 5426 cmd->phase_delay = cpu_to_le32(phase_delay); 5427 5428 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5429} 5430 5431/** 5432 * ice_aq_get_input_pin_cfg - get input pin config 5433 * @hw: pointer to the HW struct 5434 * @input_idx: Input index 5435 * @status: Pin status 5436 * @type: Pin type 5437 * @flags1: Input flags 5438 * @flags2: Input flags 5439 * @freq: Frequency in Hz 5440 * @phase_delay: Delay in ps 5441 * 5442 * Get CGU input config (0x0C63) 5443 * Return: 0 on success or negative value on failure. 5444 */ 5445int 5446ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5447 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5448{ 5449 struct ice_aqc_get_cgu_input_config *cmd; 5450 struct libie_aq_desc desc; 5451 int ret; 5452 5453 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5454 cmd = libie_aq_raw(&desc); 5455 cmd->input_idx = input_idx; 5456 5457 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5458 if (!ret) { 5459 if (status) 5460 *status = cmd->status; 5461 if (type) 5462 *type = cmd->type; 5463 if (flags1) 5464 *flags1 = cmd->flags1; 5465 if (flags2) 5466 *flags2 = cmd->flags2; 5467 if (freq) 5468 *freq = le32_to_cpu(cmd->freq); 5469 if (phase_delay) 5470 *phase_delay = le32_to_cpu(cmd->phase_delay); 5471 } 5472 5473 return ret; 5474} 5475 5476/** 5477 * ice_aq_set_output_pin_cfg - set output pin config 5478 * @hw: pointer to the HW struct 5479 * @output_idx: Output index 5480 * @flags: Output flags 5481 * @src_sel: Index of DPLL block 5482 * @freq: Output frequency 5483 * @phase_delay: Output phase compensation 5484 * 5485 * Set CGU output config (0x0C64) 5486 * Return: 0 on success or negative value on failure. 5487 */ 5488int 5489ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5490 u8 src_sel, u32 freq, s32 phase_delay) 5491{ 5492 struct ice_aqc_set_cgu_output_config *cmd; 5493 struct libie_aq_desc desc; 5494 5495 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5496 cmd = libie_aq_raw(&desc); 5497 cmd->output_idx = output_idx; 5498 cmd->flags = flags; 5499 cmd->src_sel = src_sel; 5500 cmd->freq = cpu_to_le32(freq); 5501 cmd->phase_delay = cpu_to_le32(phase_delay); 5502 5503 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5504} 5505 5506/** 5507 * ice_aq_get_output_pin_cfg - get output pin config 5508 * @hw: pointer to the HW struct 5509 * @output_idx: Output index 5510 * @flags: Output flags 5511 * @src_sel: Internal DPLL source 5512 * @freq: Output frequency 5513 * @src_freq: Source frequency 5514 * 5515 * Get CGU output config (0x0C65) 5516 * Return: 0 on success or negative value on failure. 5517 */ 5518int 5519ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5520 u8 *src_sel, u32 *freq, u32 *src_freq) 5521{ 5522 struct ice_aqc_get_cgu_output_config *cmd; 5523 struct libie_aq_desc desc; 5524 int ret; 5525 5526 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5527 cmd = libie_aq_raw(&desc); 5528 cmd->output_idx = output_idx; 5529 5530 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5531 if (!ret) { 5532 if (flags) 5533 *flags = cmd->flags; 5534 if (src_sel) 5535 *src_sel = cmd->src_sel; 5536 if (freq) 5537 *freq = le32_to_cpu(cmd->freq); 5538 if (src_freq) 5539 *src_freq = le32_to_cpu(cmd->src_freq); 5540 } 5541 5542 return ret; 5543} 5544 5545/** 5546 * ice_aq_get_cgu_dpll_status - get dpll status 5547 * @hw: pointer to the HW struct 5548 * @dpll_num: DPLL index 5549 * @ref_state: Reference clock state 5550 * @config: current DPLL config 5551 * @dpll_state: current DPLL state 5552 * @phase_offset: Phase offset in ns 5553 * @eec_mode: EEC_mode 5554 * 5555 * Get CGU DPLL status (0x0C66) 5556 * Return: 0 on success or negative value on failure. 5557 */ 5558int 5559ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5560 u8 *dpll_state, u8 *config, s64 *phase_offset, 5561 u8 *eec_mode) 5562{ 5563 struct ice_aqc_get_cgu_dpll_status *cmd; 5564 struct libie_aq_desc desc; 5565 int status; 5566 5567 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5568 cmd = libie_aq_raw(&desc); 5569 cmd->dpll_num = dpll_num; 5570 5571 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5572 if (!status) { 5573 *ref_state = cmd->ref_state; 5574 *dpll_state = cmd->dpll_state; 5575 *config = cmd->config; 5576 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5577 *phase_offset <<= 32; 5578 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5579 *phase_offset = sign_extend64(*phase_offset, 47); 5580 *eec_mode = cmd->eec_mode; 5581 } 5582 5583 return status; 5584} 5585 5586/** 5587 * ice_aq_set_cgu_dpll_config - set dpll config 5588 * @hw: pointer to the HW struct 5589 * @dpll_num: DPLL index 5590 * @ref_state: Reference clock state 5591 * @config: DPLL config 5592 * @eec_mode: EEC mode 5593 * 5594 * Set CGU DPLL config (0x0C67) 5595 * Return: 0 on success or negative value on failure. 5596 */ 5597int 5598ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5599 u8 config, u8 eec_mode) 5600{ 5601 struct ice_aqc_set_cgu_dpll_config *cmd; 5602 struct libie_aq_desc desc; 5603 5604 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5605 cmd = libie_aq_raw(&desc); 5606 cmd->dpll_num = dpll_num; 5607 cmd->ref_state = ref_state; 5608 cmd->config = config; 5609 cmd->eec_mode = eec_mode; 5610 5611 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5612} 5613 5614/** 5615 * ice_aq_set_cgu_ref_prio - set input reference priority 5616 * @hw: pointer to the HW struct 5617 * @dpll_num: DPLL index 5618 * @ref_idx: Reference pin index 5619 * @ref_priority: Reference input priority 5620 * 5621 * Set CGU reference priority (0x0C68) 5622 * Return: 0 on success or negative value on failure. 5623 */ 5624int 5625ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5626 u8 ref_priority) 5627{ 5628 struct ice_aqc_set_cgu_ref_prio *cmd; 5629 struct libie_aq_desc desc; 5630 5631 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5632 cmd = libie_aq_raw(&desc); 5633 cmd->dpll_num = dpll_num; 5634 cmd->ref_idx = ref_idx; 5635 cmd->ref_priority = ref_priority; 5636 5637 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5638} 5639 5640/** 5641 * ice_aq_get_cgu_ref_prio - get input reference priority 5642 * @hw: pointer to the HW struct 5643 * @dpll_num: DPLL index 5644 * @ref_idx: Reference pin index 5645 * @ref_prio: Reference input priority 5646 * 5647 * Get CGU reference priority (0x0C69) 5648 * Return: 0 on success or negative value on failure. 5649 */ 5650int 5651ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5652 u8 *ref_prio) 5653{ 5654 struct ice_aqc_get_cgu_ref_prio *cmd; 5655 struct libie_aq_desc desc; 5656 int status; 5657 5658 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5659 cmd = libie_aq_raw(&desc); 5660 cmd->dpll_num = dpll_num; 5661 cmd->ref_idx = ref_idx; 5662 5663 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5664 if (!status) 5665 *ref_prio = cmd->ref_priority; 5666 5667 return status; 5668} 5669 5670/** 5671 * ice_aq_get_cgu_info - get cgu info 5672 * @hw: pointer to the HW struct 5673 * @cgu_id: CGU ID 5674 * @cgu_cfg_ver: CGU config version 5675 * @cgu_fw_ver: CGU firmware version 5676 * 5677 * Get CGU info (0x0C6A) 5678 * Return: 0 on success or negative value on failure. 5679 */ 5680int 5681ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5682 u32 *cgu_fw_ver) 5683{ 5684 struct ice_aqc_get_cgu_info *cmd; 5685 struct libie_aq_desc desc; 5686 int status; 5687 5688 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5689 cmd = libie_aq_raw(&desc); 5690 5691 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5692 if (!status) { 5693 *cgu_id = le32_to_cpu(cmd->cgu_id); 5694 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5695 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5696 } 5697 5698 return status; 5699} 5700 5701/** 5702 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5703 * @hw: pointer to the HW struct 5704 * @phy_output: PHY reference clock output pin 5705 * @enable: GPIO state to be applied 5706 * @freq: PHY output frequency 5707 * 5708 * Set phy recovered clock as reference (0x0630) 5709 * Return: 0 on success or negative value on failure. 5710 */ 5711int 5712ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5713 u32 *freq) 5714{ 5715 struct ice_aqc_set_phy_rec_clk_out *cmd; 5716 struct libie_aq_desc desc; 5717 int status; 5718 5719 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5720 cmd = libie_aq_raw(&desc); 5721 cmd->phy_output = phy_output; 5722 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5723 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5724 cmd->freq = cpu_to_le32(*freq); 5725 5726 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5727 if (!status) 5728 *freq = le32_to_cpu(cmd->freq); 5729 5730 return status; 5731} 5732 5733/** 5734 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5735 * @hw: pointer to the HW struct 5736 * @phy_output: PHY reference clock output pin 5737 * @port_num: Port number 5738 * @flags: PHY flags 5739 * @node_handle: PHY output frequency 5740 * 5741 * Get PHY recovered clock output info (0x0631) 5742 * Return: 0 on success or negative value on failure. 5743 */ 5744int 5745ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5746 u8 *flags, u16 *node_handle) 5747{ 5748 struct ice_aqc_get_phy_rec_clk_out *cmd; 5749 struct libie_aq_desc desc; 5750 int status; 5751 5752 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5753 cmd = libie_aq_raw(&desc); 5754 cmd->phy_output = *phy_output; 5755 5756 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5757 if (!status) { 5758 *phy_output = cmd->phy_output; 5759 if (port_num) 5760 *port_num = cmd->port_num; 5761 if (flags) 5762 *flags = cmd->flags; 5763 if (node_handle) 5764 *node_handle = le16_to_cpu(cmd->node_handle); 5765 } 5766 5767 return status; 5768} 5769 5770/** 5771 * ice_aq_get_sensor_reading 5772 * @hw: pointer to the HW struct 5773 * @data: pointer to data to be read from the sensor 5774 * 5775 * Get sensor reading (0x0632) 5776 */ 5777int ice_aq_get_sensor_reading(struct ice_hw *hw, 5778 struct ice_aqc_get_sensor_reading_resp *data) 5779{ 5780 struct ice_aqc_get_sensor_reading *cmd; 5781 struct libie_aq_desc desc; 5782 int status; 5783 5784 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5785 cmd = libie_aq_raw(&desc); 5786#define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5787#define ICE_INTERNAL_TEMP_SENSOR 0 5788 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5789 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5790 5791 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5792 if (!status) 5793 memcpy(data, &desc.params.raw, 5794 sizeof(*data)); 5795 5796 return status; 5797} 5798 5799/** 5800 * ice_replay_pre_init - replay pre initialization 5801 * @hw: pointer to the HW struct 5802 * 5803 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5804 */ 5805static int ice_replay_pre_init(struct ice_hw *hw) 5806{ 5807 struct ice_switch_info *sw = hw->switch_info; 5808 u8 i; 5809 5810 /* Delete old entries from replay filter list head if there is any */ 5811 ice_rm_all_sw_replay_rule_info(hw); 5812 /* In start of replay, move entries into replay_rules list, it 5813 * will allow adding rules entries back to filt_rules list, 5814 * which is operational list. 5815 */ 5816 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5817 list_replace_init(&sw->recp_list[i].filt_rules, 5818 &sw->recp_list[i].filt_replay_rules); 5819 ice_sched_replay_agg_vsi_preinit(hw); 5820 5821 return 0; 5822} 5823 5824/** 5825 * ice_replay_vsi - replay VSI configuration 5826 * @hw: pointer to the HW struct 5827 * @vsi_handle: driver VSI handle 5828 * 5829 * Restore all VSI configuration after reset. It is required to call this 5830 * function with main VSI first. 5831 */ 5832int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5833{ 5834 int status; 5835 5836 if (!ice_is_vsi_valid(hw, vsi_handle)) 5837 return -EINVAL; 5838 5839 /* Replay pre-initialization if there is any */ 5840 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5841 status = ice_replay_pre_init(hw); 5842 if (status) 5843 return status; 5844 } 5845 /* Replay per VSI all RSS configurations */ 5846 status = ice_replay_rss_cfg(hw, vsi_handle); 5847 if (status) 5848 return status; 5849 /* Replay per VSI all filters */ 5850 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5851 if (!status) 5852 status = ice_replay_vsi_agg(hw, vsi_handle); 5853 return status; 5854} 5855 5856/** 5857 * ice_replay_post - post replay configuration cleanup 5858 * @hw: pointer to the HW struct 5859 * 5860 * Post replay cleanup. 5861 */ 5862void ice_replay_post(struct ice_hw *hw) 5863{ 5864 /* Delete old entries from replay filter list head */ 5865 ice_rm_all_sw_replay_rule_info(hw); 5866 ice_sched_replay_agg(hw); 5867} 5868 5869/** 5870 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5871 * @hw: ptr to the hardware info 5872 * @reg: offset of 64 bit HW register to read from 5873 * @prev_stat_loaded: bool to specify if previous stats are loaded 5874 * @prev_stat: ptr to previous loaded stat value 5875 * @cur_stat: ptr to current stat value 5876 */ 5877void 5878ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5879 u64 *prev_stat, u64 *cur_stat) 5880{ 5881 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5882 5883 /* device stats are not reset at PFR, they likely will not be zeroed 5884 * when the driver starts. Thus, save the value from the first read 5885 * without adding to the statistic value so that we report stats which 5886 * count up from zero. 5887 */ 5888 if (!prev_stat_loaded) { 5889 *prev_stat = new_data; 5890 return; 5891 } 5892 5893 /* Calculate the difference between the new and old values, and then 5894 * add it to the software stat value. 5895 */ 5896 if (new_data >= *prev_stat) 5897 *cur_stat += new_data - *prev_stat; 5898 else 5899 /* to manage the potential roll-over */ 5900 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5901 5902 /* Update the previously stored value to prepare for next read */ 5903 *prev_stat = new_data; 5904} 5905 5906/** 5907 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5908 * @hw: ptr to the hardware info 5909 * @reg: offset of HW register to read from 5910 * @prev_stat_loaded: bool to specify if previous stats are loaded 5911 * @prev_stat: ptr to previous loaded stat value 5912 * @cur_stat: ptr to current stat value 5913 */ 5914void 5915ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5916 u64 *prev_stat, u64 *cur_stat) 5917{ 5918 u32 new_data; 5919 5920 new_data = rd32(hw, reg); 5921 5922 /* device stats are not reset at PFR, they likely will not be zeroed 5923 * when the driver starts. Thus, save the value from the first read 5924 * without adding to the statistic value so that we report stats which 5925 * count up from zero. 5926 */ 5927 if (!prev_stat_loaded) { 5928 *prev_stat = new_data; 5929 return; 5930 } 5931 5932 /* Calculate the difference between the new and old values, and then 5933 * add it to the software stat value. 5934 */ 5935 if (new_data >= *prev_stat) 5936 *cur_stat += new_data - *prev_stat; 5937 else 5938 /* to manage the potential roll-over */ 5939 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5940 5941 /* Update the previously stored value to prepare for next read */ 5942 *prev_stat = new_data; 5943} 5944 5945/** 5946 * ice_sched_query_elem - query element information from HW 5947 * @hw: pointer to the HW struct 5948 * @node_teid: node TEID to be queried 5949 * @buf: buffer to element information 5950 * 5951 * This function queries HW element information 5952 */ 5953int 5954ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5955 struct ice_aqc_txsched_elem_data *buf) 5956{ 5957 u16 buf_size, num_elem_ret = 0; 5958 int status; 5959 5960 buf_size = sizeof(*buf); 5961 memset(buf, 0, buf_size); 5962 buf->node_teid = cpu_to_le32(node_teid); 5963 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5964 NULL); 5965 if (status || num_elem_ret != 1) 5966 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5967 return status; 5968} 5969 5970/** 5971 * ice_aq_read_i2c 5972 * @hw: pointer to the hw struct 5973 * @topo_addr: topology address for a device to communicate with 5974 * @bus_addr: 7-bit I2C bus address 5975 * @addr: I2C memory address (I2C offset) with up to 16 bits 5976 * @params: I2C parameters: bit [7] - Repeated start, 5977 * bits [6:5] data offset size, 5978 * bit [4] - I2C address type, 5979 * bits [3:0] - data size to read (0-16 bytes) 5980 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5981 * @cd: pointer to command details structure or NULL 5982 * 5983 * Read I2C (0x06E2) 5984 */ 5985int 5986ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5987 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5988 struct ice_sq_cd *cd) 5989{ 5990 struct libie_aq_desc desc = { 0 }; 5991 struct ice_aqc_i2c *cmd; 5992 u8 data_size; 5993 int status; 5994 5995 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5996 cmd = libie_aq_raw(&desc); 5997 5998 if (!data) 5999 return -EINVAL; 6000 6001 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 6002 6003 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 6004 cmd->topo_addr = topo_addr; 6005 cmd->i2c_params = params; 6006 cmd->i2c_addr = addr; 6007 6008 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6009 if (!status) { 6010 struct ice_aqc_read_i2c_resp *resp; 6011 u8 i; 6012 6013 resp = libie_aq_raw(&desc); 6014 for (i = 0; i < data_size; i++) { 6015 *data = resp->i2c_data[i]; 6016 data++; 6017 } 6018 } 6019 6020 return status; 6021} 6022 6023/** 6024 * ice_aq_write_i2c 6025 * @hw: pointer to the hw struct 6026 * @topo_addr: topology address for a device to communicate with 6027 * @bus_addr: 7-bit I2C bus address 6028 * @addr: I2C memory address (I2C offset) with up to 16 bits 6029 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 6030 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 6031 * @cd: pointer to command details structure or NULL 6032 * 6033 * Write I2C (0x06E3) 6034 * 6035 * * Return: 6036 * * 0 - Successful write to the i2c device 6037 * * -EINVAL - Data size greater than 4 bytes 6038 * * -EIO - FW error 6039 */ 6040int 6041ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 6042 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 6043 struct ice_sq_cd *cd) 6044{ 6045 struct libie_aq_desc desc = { 0 }; 6046 struct ice_aqc_i2c *cmd; 6047 u8 data_size; 6048 6049 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 6050 cmd = libie_aq_raw(&desc); 6051 6052 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 6053 6054 /* data_size limited to 4 */ 6055 if (data_size > 4) 6056 return -EINVAL; 6057 6058 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 6059 cmd->topo_addr = topo_addr; 6060 cmd->i2c_params = params; 6061 cmd->i2c_addr = addr; 6062 6063 memcpy(cmd->i2c_data, data, data_size); 6064 6065 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6066} 6067 6068/** 6069 * ice_get_pca9575_handle - find and return the PCA9575 controller 6070 * @hw: pointer to the hw struct 6071 * @pca9575_handle: GPIO controller's handle 6072 * 6073 * Find and return the GPIO controller's handle in the netlist. 6074 * When found - the value will be cached in the hw structure and following calls 6075 * will return cached value. 6076 * 6077 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 6078 */ 6079int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 6080{ 6081 struct ice_aqc_get_link_topo *cmd; 6082 struct libie_aq_desc desc; 6083 int err; 6084 u8 idx; 6085 6086 /* If handle was read previously return cached value */ 6087 if (hw->io_expander_handle) { 6088 *pca9575_handle = hw->io_expander_handle; 6089 return 0; 6090 } 6091 6092#define SW_PCA9575_SFP_TOPO_IDX 2 6093#define SW_PCA9575_QSFP_TOPO_IDX 1 6094 6095 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 6096 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 6097 idx = SW_PCA9575_SFP_TOPO_IDX; 6098 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 6099 idx = SW_PCA9575_QSFP_TOPO_IDX; 6100 else 6101 return -ENXIO; 6102 6103 /* If handle was not detected read it from the netlist */ 6104 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 6105 cmd = libie_aq_raw(&desc); 6106 cmd->addr.topo_params.node_type_ctx = 6107 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 6108 cmd->addr.topo_params.index = idx; 6109 6110 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6111 if (err) 6112 return -ENXIO; 6113 6114 /* Verify if we found the right IO expander type */ 6115 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 6116 return -ENXIO; 6117 6118 /* If present save the handle and return it */ 6119 hw->io_expander_handle = 6120 le16_to_cpu(cmd->addr.handle); 6121 *pca9575_handle = hw->io_expander_handle; 6122 6123 return 0; 6124} 6125 6126/** 6127 * ice_read_pca9575_reg - read the register from the PCA9575 controller 6128 * @hw: pointer to the hw struct 6129 * @offset: GPIO controller register offset 6130 * @data: pointer to data to be read from the GPIO controller 6131 * 6132 * Return: 0 on success, negative error code otherwise. 6133 */ 6134int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 6135{ 6136 struct ice_aqc_link_topo_addr link_topo; 6137 __le16 addr; 6138 u16 handle; 6139 int err; 6140 6141 memset(&link_topo, 0, sizeof(link_topo)); 6142 6143 err = ice_get_pca9575_handle(hw, &handle); 6144 if (err) 6145 return err; 6146 6147 link_topo.handle = cpu_to_le16(handle); 6148 link_topo.topo_params.node_type_ctx = 6149 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6150 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6151 6152 addr = cpu_to_le16((u16)offset); 6153 6154 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6155} 6156 6157/** 6158 * ice_aq_set_gpio 6159 * @hw: pointer to the hw struct 6160 * @gpio_ctrl_handle: GPIO controller node handle 6161 * @pin_idx: IO Number of the GPIO that needs to be set 6162 * @value: SW provide IO value to set in the LSB 6163 * @cd: pointer to command details structure or NULL 6164 * 6165 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6166 */ 6167int 6168ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6169 struct ice_sq_cd *cd) 6170{ 6171 struct libie_aq_desc desc; 6172 struct ice_aqc_gpio *cmd; 6173 6174 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6175 cmd = libie_aq_raw(&desc); 6176 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6177 cmd->gpio_num = pin_idx; 6178 cmd->gpio_val = value ? 1 : 0; 6179 6180 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6181} 6182 6183/** 6184 * ice_aq_get_gpio 6185 * @hw: pointer to the hw struct 6186 * @gpio_ctrl_handle: GPIO controller node handle 6187 * @pin_idx: IO Number of the GPIO that needs to be set 6188 * @value: IO value read 6189 * @cd: pointer to command details structure or NULL 6190 * 6191 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6192 * the topology 6193 */ 6194int 6195ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6196 bool *value, struct ice_sq_cd *cd) 6197{ 6198 struct libie_aq_desc desc; 6199 struct ice_aqc_gpio *cmd; 6200 int status; 6201 6202 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6203 cmd = libie_aq_raw(&desc); 6204 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6205 cmd->gpio_num = pin_idx; 6206 6207 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6208 if (status) 6209 return status; 6210 6211 *value = !!cmd->gpio_val; 6212 return 0; 6213} 6214 6215/** 6216 * ice_is_fw_api_min_ver 6217 * @hw: pointer to the hardware structure 6218 * @maj: major version 6219 * @min: minor version 6220 * @patch: patch version 6221 * 6222 * Checks if the firmware API is minimum version 6223 */ 6224static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6225{ 6226 if (hw->api_maj_ver == maj) { 6227 if (hw->api_min_ver > min) 6228 return true; 6229 if (hw->api_min_ver == min && hw->api_patch >= patch) 6230 return true; 6231 } else if (hw->api_maj_ver > maj) { 6232 return true; 6233 } 6234 6235 return false; 6236} 6237 6238/** 6239 * ice_fw_supports_link_override 6240 * @hw: pointer to the hardware structure 6241 * 6242 * Checks if the firmware supports link override 6243 */ 6244bool ice_fw_supports_link_override(struct ice_hw *hw) 6245{ 6246 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6247 ICE_FW_API_LINK_OVERRIDE_MIN, 6248 ICE_FW_API_LINK_OVERRIDE_PATCH); 6249} 6250 6251/** 6252 * ice_get_link_default_override 6253 * @ldo: pointer to the link default override struct 6254 * @pi: pointer to the port info struct 6255 * 6256 * Gets the link default override for a port 6257 */ 6258int 6259ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6260 struct ice_port_info *pi) 6261{ 6262 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6263 struct ice_hw *hw = pi->hw; 6264 int status; 6265 6266 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6267 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6268 if (status) { 6269 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6270 return status; 6271 } 6272 6273 /* Each port has its own config; calculate for our port */ 6274 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6275 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6276 6277 /* link options first */ 6278 status = ice_read_sr_word(hw, tlv_start, &buf); 6279 if (status) { 6280 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6281 return status; 6282 } 6283 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6284 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6285 ICE_LINK_OVERRIDE_PHY_CFG_S; 6286 6287 /* link PHY config */ 6288 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6289 status = ice_read_sr_word(hw, offset, &buf); 6290 if (status) { 6291 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6292 return status; 6293 } 6294 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6295 6296 /* PHY types low */ 6297 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6298 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6299 status = ice_read_sr_word(hw, (offset + i), &buf); 6300 if (status) { 6301 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6302 return status; 6303 } 6304 /* shift 16 bits at a time to fill 64 bits */ 6305 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6306 } 6307 6308 /* PHY types high */ 6309 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6310 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6311 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6312 status = ice_read_sr_word(hw, (offset + i), &buf); 6313 if (status) { 6314 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6315 return status; 6316 } 6317 /* shift 16 bits at a time to fill 64 bits */ 6318 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6319 } 6320 6321 return status; 6322} 6323 6324/** 6325 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6326 * @caps: get PHY capability data 6327 */ 6328bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6329{ 6330 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6331 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6332 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6333 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6334 return true; 6335 6336 return false; 6337} 6338 6339/** 6340 * ice_is_fw_health_report_supported - checks if firmware supports health events 6341 * @hw: pointer to the hardware structure 6342 * 6343 * Return: true if firmware supports health status reports, 6344 * false otherwise 6345 */ 6346bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6347{ 6348 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6349 ICE_FW_API_HEALTH_REPORT_MIN, 6350 ICE_FW_API_HEALTH_REPORT_PATCH); 6351} 6352 6353/** 6354 * ice_aq_set_health_status_cfg - Configure FW health events 6355 * @hw: pointer to the HW struct 6356 * @event_source: type of diagnostic events to enable 6357 * 6358 * Configure the health status event types that the firmware will send to this 6359 * PF. The supported event types are: PF-specific, all PFs, and global. 6360 * 6361 * Return: 0 on success, negative error code otherwise. 6362 */ 6363int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6364{ 6365 struct ice_aqc_set_health_status_cfg *cmd; 6366 struct libie_aq_desc desc; 6367 6368 cmd = libie_aq_raw(&desc); 6369 6370 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6371 6372 cmd->event_source = event_source; 6373 6374 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6375} 6376 6377/** 6378 * ice_aq_set_lldp_mib - Set the LLDP MIB 6379 * @hw: pointer to the HW struct 6380 * @mib_type: Local, Remote or both Local and Remote MIBs 6381 * @buf: pointer to the caller-supplied buffer to store the MIB block 6382 * @buf_size: size of the buffer (in bytes) 6383 * @cd: pointer to command details structure or NULL 6384 * 6385 * Set the LLDP MIB. (0x0A08) 6386 */ 6387int 6388ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6389 struct ice_sq_cd *cd) 6390{ 6391 struct ice_aqc_lldp_set_local_mib *cmd; 6392 struct libie_aq_desc desc; 6393 6394 cmd = libie_aq_raw(&desc); 6395 6396 if (buf_size == 0 || !buf) 6397 return -EINVAL; 6398 6399 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6400 6401 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6402 desc.datalen = cpu_to_le16(buf_size); 6403 6404 cmd->type = mib_type; 6405 cmd->length = cpu_to_le16(buf_size); 6406 6407 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6408} 6409 6410/** 6411 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6412 * @hw: pointer to HW struct 6413 */ 6414bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6415{ 6416 if (hw->mac_type != ICE_MAC_E810) 6417 return false; 6418 6419 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6420 ICE_FW_API_LLDP_FLTR_MIN, 6421 ICE_FW_API_LLDP_FLTR_PATCH); 6422} 6423 6424/** 6425 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6426 * @hw: pointer to HW struct 6427 * @vsi: VSI to add the filter to 6428 * @add: boolean for if adding or removing a filter 6429 * 6430 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6431 * with this HW or VSI, otherwise an error corresponding to 6432 * the AQ transaction result. 6433 */ 6434int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6435{ 6436 struct ice_aqc_lldp_filter_ctrl *cmd; 6437 struct libie_aq_desc desc; 6438 6439 if (!ice_fw_supports_lldp_fltr_ctrl(hw)) 6440 return -EOPNOTSUPP; 6441 6442 cmd = libie_aq_raw(&desc); 6443 6444 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6445 6446 if (add) 6447 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6448 else 6449 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6450 6451 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6452 6453 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6454} 6455 6456/** 6457 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6458 * @hw: pointer to HW struct 6459 */ 6460int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6461{ 6462 struct libie_aq_desc desc; 6463 6464 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6465 6466 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6467} 6468 6469/** 6470 * ice_fw_supports_report_dflt_cfg 6471 * @hw: pointer to the hardware structure 6472 * 6473 * Checks if the firmware supports report default configuration 6474 */ 6475bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6476{ 6477 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6478 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6479 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6480} 6481 6482/* each of the indexes into the following array match the speed of a return 6483 * value from the list of AQ returned speeds like the range: 6484 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6485 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6486 * array. The array is defined as 15 elements long because the link_speed 6487 * returned by the firmware is a 16 bit * value, but is indexed 6488 * by [fls(speed) - 1] 6489 */ 6490static const u32 ice_aq_to_link_speed[] = { 6491 SPEED_10, /* BIT(0) */ 6492 SPEED_100, 6493 SPEED_1000, 6494 SPEED_2500, 6495 SPEED_5000, 6496 SPEED_10000, 6497 SPEED_20000, 6498 SPEED_25000, 6499 SPEED_40000, 6500 SPEED_50000, 6501 SPEED_100000, /* BIT(10) */ 6502 SPEED_200000, 6503}; 6504 6505/** 6506 * ice_get_link_speed - get integer speed from table 6507 * @index: array index from fls(aq speed) - 1 6508 * 6509 * Returns: u32 value containing integer speed 6510 */ 6511u32 ice_get_link_speed(u16 index) 6512{ 6513 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6514 return 0; 6515 6516 return ice_aq_to_link_speed[index]; 6517} 6518 6519/** 6520 * ice_get_dest_cgu - get destination CGU dev for given HW 6521 * @hw: pointer to the HW struct 6522 * 6523 * Get CGU client id for CGU register read/write operations. 6524 * 6525 * Return: CGU device id to use in SBQ transactions. 6526 */ 6527static enum ice_sbq_dev_id ice_get_dest_cgu(struct ice_hw *hw) 6528{ 6529 /* On dual complex E825 only complex 0 has functional CGU powering all 6530 * the PHYs. 6531 * SBQ destination device cgu points to CGU on a current complex and to 6532 * access primary CGU from the secondary complex, the driver should use 6533 * cgu_peer as a destination device. 6534 */ 6535 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && ice_is_dual(hw) && 6536 !ice_is_primary(hw)) 6537 return ice_sbq_dev_cgu_peer; 6538 return ice_sbq_dev_cgu; 6539} 6540 6541/** 6542 * ice_read_cgu_reg - Read a CGU register 6543 * @hw: Pointer to the HW struct 6544 * @addr: Register address to read 6545 * @val: Storage for register value read 6546 * 6547 * Read the contents of a register of the Clock Generation Unit. Only 6548 * applicable to E82X devices. 6549 * 6550 * Return: 0 on success, other error codes when failed to read from CGU. 6551 */ 6552int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6553{ 6554 struct ice_sbq_msg_input cgu_msg = { 6555 .dest_dev = ice_get_dest_cgu(hw), 6556 .opcode = ice_sbq_msg_rd, 6557 .msg_addr_low = addr 6558 }; 6559 int err; 6560 6561 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6562 if (err) { 6563 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6564 addr, err); 6565 return err; 6566 } 6567 6568 *val = cgu_msg.data; 6569 6570 return 0; 6571} 6572 6573/** 6574 * ice_write_cgu_reg - Write a CGU register 6575 * @hw: Pointer to the HW struct 6576 * @addr: Register address to write 6577 * @val: Value to write into the register 6578 * 6579 * Write the specified value to a register of the Clock Generation Unit. Only 6580 * applicable to E82X devices. 6581 * 6582 * Return: 0 on success, other error codes when failed to write to CGU. 6583 */ 6584int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6585{ 6586 struct ice_sbq_msg_input cgu_msg = { 6587 .dest_dev = ice_get_dest_cgu(hw), 6588 .opcode = ice_sbq_msg_wr, 6589 .msg_addr_low = addr, 6590 .data = val 6591 }; 6592 int err; 6593 6594 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6595 if (err) 6596 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6597 addr, err); 6598 6599 return err; 6600}
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