ice_base.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright (c) 2019, Intel Corporation. */
   3
   4#include <net/xdp_sock_drv.h>
   5#include <linux/net/intel/libie/rx.h>
   6#include "ice_base.h"
   7#include "ice_lib.h"
   8#include "ice_dcb_lib.h"
   9#include "ice_sriov.h"
  10
  11/**
  12 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI
  13 * @qs_cfg: gathered variables needed for PF->VSI queues assignment
  14 *
  15 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
  16 */
  17static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg)
  18{
  19	unsigned int offset, i;
  20
  21	mutex_lock(qs_cfg->qs_mutex);
  22	offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size,
  23					    0, qs_cfg->q_count, 0);
  24	if (offset >= qs_cfg->pf_map_size) {
  25		mutex_unlock(qs_cfg->qs_mutex);
  26		return -ENOMEM;
  27	}
  28
  29	bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count);
  30	for (i = 0; i < qs_cfg->q_count; i++)
  31		qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)(i + offset);
  32	mutex_unlock(qs_cfg->qs_mutex);
  33
  34	return 0;
  35}
  36
  37/**
  38 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI
  39 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
  40 *
  41 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
  42 */
  43static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg)
  44{
  45	unsigned int i, index = 0;
  46
  47	mutex_lock(qs_cfg->qs_mutex);
  48	for (i = 0; i < qs_cfg->q_count; i++) {
  49		index = find_next_zero_bit(qs_cfg->pf_map,
  50					   qs_cfg->pf_map_size, index);
  51		if (index >= qs_cfg->pf_map_size)
  52			goto err_scatter;
  53		set_bit(index, qs_cfg->pf_map);
  54		qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)index;
  55	}
  56	mutex_unlock(qs_cfg->qs_mutex);
  57
  58	return 0;
  59err_scatter:
  60	for (index = 0; index < i; index++) {
  61		clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map);
  62		qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0;
  63	}
  64	mutex_unlock(qs_cfg->qs_mutex);
  65
  66	return -ENOMEM;
  67}
  68
  69/**
  70 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
  71 * @pf: the PF being configured
  72 * @pf_q: the PF queue
  73 * @ena: enable or disable state of the queue
  74 *
  75 * This routine will wait for the given Rx queue of the PF to reach the
  76 * enabled or disabled state.
  77 * Returns -ETIMEDOUT in case of failing to reach the requested state after
  78 * multiple retries; else will return 0 in case of success.
  79 */
  80static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena)
  81{
  82	int i;
  83
  84	for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) {
  85		if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) &
  86			      QRX_CTRL_QENA_STAT_M))
  87			return 0;
  88
  89		usleep_range(20, 40);
  90	}
  91
  92	return -ETIMEDOUT;
  93}
  94
  95/**
  96 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
  97 * @vsi: the VSI being configured
  98 * @v_idx: index of the vector in the VSI struct
  99 *
 100 * We allocate one q_vector and set default value for ITR setting associated
 101 * with this q_vector. If allocation fails we return -ENOMEM.
 102 */
 103static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, u16 v_idx)
 104{
 105	struct ice_pf *pf = vsi->back;
 106	struct ice_q_vector *q_vector;
 107	int err;
 108
 109	/* allocate q_vector */
 110	q_vector = kzalloc(sizeof(*q_vector), GFP_KERNEL);
 111	if (!q_vector)
 112		return -ENOMEM;
 113
 114	q_vector->vsi = vsi;
 115	q_vector->v_idx = v_idx;
 116	q_vector->tx.itr_setting = ICE_DFLT_TX_ITR;
 117	q_vector->rx.itr_setting = ICE_DFLT_RX_ITR;
 118	q_vector->tx.itr_mode = ITR_DYNAMIC;
 119	q_vector->rx.itr_mode = ITR_DYNAMIC;
 120	q_vector->tx.type = ICE_TX_CONTAINER;
 121	q_vector->rx.type = ICE_RX_CONTAINER;
 122	q_vector->irq.index = -ENOENT;
 123
 124	if (vsi->type == ICE_VSI_VF) {
 125		ice_calc_vf_reg_idx(vsi->vf, q_vector);
 126		goto out;
 127	} else if (vsi->type == ICE_VSI_LB) {
 128		goto skip_alloc;
 129	} else if (vsi->type == ICE_VSI_CTRL && vsi->vf) {
 130		struct ice_vsi *ctrl_vsi = ice_get_vf_ctrl_vsi(pf, vsi);
 131
 132		if (ctrl_vsi) {
 133			if (unlikely(!ctrl_vsi->q_vectors)) {
 134				err = -ENOENT;
 135				goto err_free_q_vector;
 136			}
 137
 138			q_vector->irq = ctrl_vsi->q_vectors[0]->irq;
 139			goto skip_alloc;
 140		}
 141	}
 142
 143	q_vector->irq = ice_alloc_irq(pf, vsi->irq_dyn_alloc);
 144	if (q_vector->irq.index < 0) {
 145		err = -ENOMEM;
 146		goto err_free_q_vector;
 147	}
 148
 149skip_alloc:
 150	q_vector->reg_idx = q_vector->irq.index;
 151	q_vector->vf_reg_idx = q_vector->irq.index;
 152
 153	/* This will not be called in the driver load path because the netdev
 154	 * will not be created yet. All other cases with register the NAPI
 155	 * handler here (i.e. resume, reset/rebuild, etc.)
 156	 */
 157	if (vsi->netdev)
 158		netif_napi_add_config(vsi->netdev, &q_vector->napi,
 159				      ice_napi_poll, v_idx);
 160
 161out:
 162	/* tie q_vector and VSI together */
 163	vsi->q_vectors[v_idx] = q_vector;
 164
 165	return 0;
 166
 167err_free_q_vector:
 168	kfree(q_vector);
 169
 170	return err;
 171}
 172
 173/**
 174 * ice_free_q_vector - Free memory allocated for a specific interrupt vector
 175 * @vsi: VSI having the memory freed
 176 * @v_idx: index of the vector to be freed
 177 */
 178static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx)
 179{
 180	struct ice_q_vector *q_vector;
 181	struct ice_pf *pf = vsi->back;
 182	struct ice_tx_ring *tx_ring;
 183	struct ice_rx_ring *rx_ring;
 184	struct device *dev;
 185
 186	dev = ice_pf_to_dev(pf);
 187	if (!vsi->q_vectors[v_idx]) {
 188		dev_dbg(dev, "Queue vector at index %d not found\n", v_idx);
 189		return;
 190	}
 191	q_vector = vsi->q_vectors[v_idx];
 192
 193	ice_for_each_tx_ring(tx_ring, vsi->q_vectors[v_idx]->tx)
 194		tx_ring->q_vector = NULL;
 195
 196	ice_for_each_rx_ring(rx_ring, vsi->q_vectors[v_idx]->rx)
 197		rx_ring->q_vector = NULL;
 198
 199	/* only VSI with an associated netdev is set up with NAPI */
 200	if (vsi->netdev)
 201		netif_napi_del(&q_vector->napi);
 202
 203	/* release MSIX interrupt if q_vector had interrupt allocated */
 204	if (q_vector->irq.index < 0)
 205		goto free_q_vector;
 206
 207	/* only free last VF ctrl vsi interrupt */
 208	if (vsi->type == ICE_VSI_CTRL && vsi->vf &&
 209	    ice_get_vf_ctrl_vsi(pf, vsi))
 210		goto free_q_vector;
 211
 212	ice_free_irq(pf, q_vector->irq);
 213
 214free_q_vector:
 215	kfree(q_vector);
 216	vsi->q_vectors[v_idx] = NULL;
 217}
 218
 219/**
 220 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set
 221 * @hw: board specific structure
 222 */
 223static void ice_cfg_itr_gran(struct ice_hw *hw)
 224{
 225	u32 regval = rd32(hw, GLINT_CTL);
 226
 227	/* no need to update global register if ITR gran is already set */
 228	if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&
 229	    (FIELD_GET(GLINT_CTL_ITR_GRAN_200_M, regval) == ICE_ITR_GRAN_US) &&
 230	    (FIELD_GET(GLINT_CTL_ITR_GRAN_100_M, regval) == ICE_ITR_GRAN_US) &&
 231	    (FIELD_GET(GLINT_CTL_ITR_GRAN_50_M, regval) == ICE_ITR_GRAN_US) &&
 232	    (FIELD_GET(GLINT_CTL_ITR_GRAN_25_M, regval) == ICE_ITR_GRAN_US))
 233		return;
 234
 235	regval = FIELD_PREP(GLINT_CTL_ITR_GRAN_200_M, ICE_ITR_GRAN_US) |
 236		 FIELD_PREP(GLINT_CTL_ITR_GRAN_100_M, ICE_ITR_GRAN_US) |
 237		 FIELD_PREP(GLINT_CTL_ITR_GRAN_50_M, ICE_ITR_GRAN_US) |
 238		 FIELD_PREP(GLINT_CTL_ITR_GRAN_25_M, ICE_ITR_GRAN_US);
 239	wr32(hw, GLINT_CTL, regval);
 240}
 241
 242/**
 243 * ice_calc_txq_handle - calculate the queue handle
 244 * @vsi: VSI that ring belongs to
 245 * @ring: ring to get the absolute queue index
 246 * @tc: traffic class number
 247 */
 248static u16
 249ice_calc_txq_handle(const struct ice_vsi *vsi, struct ice_tx_ring *ring, u8 tc)
 250{
 251	WARN_ONCE(ice_ring_is_xdp(ring) && tc, "XDP ring can't belong to TC other than 0\n");
 252
 253	if (ring->ch)
 254		return ring->q_index - ring->ch->base_q;
 255
 256	/* Idea here for calculation is that we subtract the number of queue
 257	 * count from TC that ring belongs to from its absolute queue index
 258	 * and as a result we get the queue's index within TC.
 259	 */
 260	return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset;
 261}
 262
 263/**
 264 * ice_cfg_xps_tx_ring - Configure XPS for a Tx ring
 265 * @ring: The Tx ring to configure
 266 *
 267 * This enables/disables XPS for a given Tx descriptor ring
 268 * based on the TCs enabled for the VSI that ring belongs to.
 269 */
 270static void ice_cfg_xps_tx_ring(struct ice_tx_ring *ring)
 271{
 272	if (!ring->q_vector || !ring->netdev)
 273		return;
 274
 275	/* We only initialize XPS once, so as not to overwrite user settings */
 276	if (test_and_set_bit(ICE_TX_XPS_INIT_DONE, ring->xps_state))
 277		return;
 278
 279	netif_set_xps_queue(ring->netdev,
 280			    &ring->q_vector->napi.config->affinity_mask,
 281			    ring->q_index);
 282}
 283
 284/**
 285 * ice_set_txq_ctx_vmvf - set queue context VM/VF type and number by VSI type
 286 * @ring: the Tx ring to configure
 287 * @vmvf_type: VM/VF type
 288 * @vmvf_num: VM/VF number
 289 *
 290 * Return: 0 on success and a negative value on error.
 291 */
 292static int
 293ice_set_txq_ctx_vmvf(struct ice_tx_ring *ring, u8 *vmvf_type, u16 *vmvf_num)
 294{
 295	struct ice_vsi *vsi = ring->vsi;
 296	struct ice_hw *hw;
 297
 298	hw = &vsi->back->hw;
 299
 300	/* queue belongs to a specific VSI type
 301	 * VF / VM index should be programmed per vmvf_type setting:
 302	 * for vmvf_type = VF, it is VF number between 0-256
 303	 * for vmvf_type = VM, it is VM number between 0-767
 304	 * for PF or EMP this field should be set to zero
 305	 */
 306	switch (vsi->type) {
 307	case ICE_VSI_LB:
 308	case ICE_VSI_CTRL:
 309	case ICE_VSI_PF:
 310		if (ring->ch)
 311			*vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ;
 312		else
 313			*vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 314		break;
 315	case ICE_VSI_VF:
 316		/* Firmware expects vmvf_num to be absolute VF ID */
 317		*vmvf_num = hw->func_caps.vf_base_id + vsi->vf->vf_id;
 318		*vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF;
 319		break;
 320	case ICE_VSI_SF:
 321		*vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ;
 322		break;
 323	default:
 324		dev_info(ice_pf_to_dev(vsi->back),
 325			 "Unable to set VMVF type for VSI type %d\n",
 326			 vsi->type);
 327		return -EINVAL;
 328	}
 329	return 0;
 330}
 331
 332/**
 333 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance
 334 * @ring: the Tx ring to configure
 335 * @tlan_ctx: pointer to the Tx LAN queue context structure to be initialized
 336 * @pf_q: queue index in the PF space
 337 *
 338 * Configure the Tx descriptor ring in TLAN context.
 339 *
 340 * Return: 0 on success and a negative value on error.
 341 */
 342static int
 343ice_setup_tx_ctx(struct ice_tx_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)
 344{
 345	struct ice_vsi *vsi = ring->vsi;
 346	struct ice_hw *hw;
 347	int err;
 348
 349	hw = &vsi->back->hw;
 350	tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S;
 351	tlan_ctx->port_num = vsi->port_info->lport;
 352
 353	/* Transmit Queue Length */
 354	tlan_ctx->qlen = ring->count;
 355
 356	ice_set_cgd_num(tlan_ctx, ring->dcb_tc);
 357
 358	/* PF number */
 359	tlan_ctx->pf_num = hw->pf_id;
 360
 361	err = ice_set_txq_ctx_vmvf(ring, &tlan_ctx->vmvf_type,
 362				   &tlan_ctx->vmvf_num);
 363	if (err)
 364		return err;
 365
 366	/* make sure the context is associated with the right VSI */
 367	if (ring->ch)
 368		tlan_ctx->src_vsi = ring->ch->vsi_num;
 369	else
 370		tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx);
 371
 372	/* Restrict Tx timestamps to the PF VSI */
 373	switch (vsi->type) {
 374	case ICE_VSI_PF:
 375		tlan_ctx->tsyn_ena = 1;
 376		break;
 377	default:
 378		break;
 379	}
 380
 381	tlan_ctx->quanta_prof_idx = ring->quanta_prof_id;
 382
 383	tlan_ctx->tso_ena = ICE_TX_LEGACY;
 384	tlan_ctx->tso_qnum = pf_q;
 385
 386	/* Legacy or Advanced Host Interface:
 387	 * 0: Advanced Host Interface
 388	 * 1: Legacy Host Interface
 389	 */
 390	tlan_ctx->legacy_int = ICE_TX_LEGACY;
 391
 392	return 0;
 393}
 394
 395/**
 396 * ice_setup_txtime_ctx - setup a struct ice_txtime_ctx instance
 397 * @ring: the tstamp ring to configure
 398 * @txtime_ctx: pointer to the Tx time queue context structure to be initialized
 399 *
 400 * Return: 0 on success and a negative value on error.
 401 */
 402static int
 403ice_setup_txtime_ctx(const struct ice_tstamp_ring *ring,
 404		     struct ice_txtime_ctx *txtime_ctx)
 405{
 406	struct ice_tx_ring *tx_ring = ring->tx_ring;
 407	struct ice_vsi *vsi = tx_ring->vsi;
 408	struct ice_hw *hw = &vsi->back->hw;
 409	int err;
 410
 411	txtime_ctx->base = ring->dma >> ICE_TXTIME_CTX_BASE_S;
 412
 413	/* Tx time Queue Length */
 414	txtime_ctx->qlen = ring->count;
 415	txtime_ctx->txtime_ena_q = 1;
 416
 417	/* PF number */
 418	txtime_ctx->pf_num = hw->pf_id;
 419
 420	err = ice_set_txq_ctx_vmvf(tx_ring, &txtime_ctx->vmvf_type,
 421				   &txtime_ctx->vmvf_num);
 422	if (err)
 423		return err;
 424
 425	/* make sure the context is associated with the right VSI */
 426	if (tx_ring->ch)
 427		txtime_ctx->src_vsi = tx_ring->ch->vsi_num;
 428	else
 429		txtime_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx);
 430
 431	txtime_ctx->ts_res = ICE_TXTIME_CTX_RESOLUTION_128NS;
 432	txtime_ctx->drbell_mode_32 = ICE_TXTIME_CTX_DRBELL_MODE_32;
 433	txtime_ctx->ts_fetch_prof_id = ICE_TXTIME_CTX_FETCH_PROF_ID_0;
 434
 435	return 0;
 436}
 437
 438/**
 439 * ice_calc_ts_ring_count - calculate the number of Tx time stamp descriptors
 440 * @tx_ring: Tx ring to calculate the count for
 441 *
 442 * Return: the number of Tx time stamp descriptors.
 443 */
 444u16 ice_calc_ts_ring_count(struct ice_tx_ring *tx_ring)
 445{
 446	u16 prof = ICE_TXTIME_CTX_FETCH_PROF_ID_0;
 447	struct ice_vsi *vsi = tx_ring->vsi;
 448	struct ice_hw *hw = &vsi->back->hw;
 449	u16 max_fetch_desc = 0, fetch, i;
 450	u32 reg;
 451
 452	for (i = 0; i < ICE_TXTIME_FETCH_PROFILE_CNT; i++) {
 453		reg = rd32(hw, E830_GLTXTIME_FETCH_PROFILE(prof, 0));
 454		fetch = FIELD_GET(E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_M,
 455				  reg);
 456		max_fetch_desc = max(fetch, max_fetch_desc);
 457	}
 458
 459	if (!max_fetch_desc)
 460		max_fetch_desc = ICE_TXTIME_FETCH_TS_DESC_DFLT;
 461
 462	max_fetch_desc = ALIGN(max_fetch_desc, ICE_REQ_DESC_MULTIPLE);
 463
 464	return tx_ring->count + max_fetch_desc;
 465}
 466
 467/**
 468 * ice_setup_rx_ctx - Configure a receive ring context
 469 * @ring: The Rx ring to configure
 470 *
 471 * Configure the Rx descriptor ring in RLAN context.
 472 */
 473static int ice_setup_rx_ctx(struct ice_rx_ring *ring)
 474{
 475	struct ice_vsi *vsi = ring->vsi;
 476	u32 rxdid = ICE_RXDID_FLEX_NIC;
 477	struct ice_rlan_ctx rlan_ctx;
 478	struct ice_hw *hw;
 479	u16 pf_q;
 480	int err;
 481
 482	hw = &vsi->back->hw;
 483
 484	/* what is Rx queue number in global space of 2K Rx queues */
 485	pf_q = vsi->rxq_map[ring->q_index];
 486
 487	/* clear the context structure first */
 488	memset(&rlan_ctx, 0, sizeof(rlan_ctx));
 489
 490	/* Receive Queue Base Address.
 491	 * Indicates the starting address of the descriptor queue defined in
 492	 * 128 Byte units.
 493	 */
 494	rlan_ctx.base = ring->dma >> ICE_RLAN_BASE_S;
 495
 496	rlan_ctx.qlen = ring->count;
 497
 498	/* Receive Packet Data Buffer Size.
 499	 * The Packet Data Buffer Size is defined in 128 byte units.
 500	 */
 501	rlan_ctx.dbuf = DIV_ROUND_UP(ring->rx_buf_len,
 502				     BIT_ULL(ICE_RLAN_CTX_DBUF_S));
 503
 504	/* use 32 byte descriptors */
 505	rlan_ctx.dsize = 1;
 506
 507	/* Strip the Ethernet CRC bytes before the packet is posted to host
 508	 * memory.
 509	 */
 510	rlan_ctx.crcstrip = !(ring->flags & ICE_RX_FLAGS_CRC_STRIP_DIS);
 511
 512	/* L2TSEL flag defines the reported L2 Tags in the receive descriptor
 513	 * and it needs to remain 1 for non-DVM capable configurations to not
 514	 * break backward compatibility for VF drivers. Setting this field to 0
 515	 * will cause the single/outer VLAN tag to be stripped to the L2TAG2_2ND
 516	 * field in the Rx descriptor. Setting it to 1 allows the VLAN tag to
 517	 * be stripped in L2TAG1 of the Rx descriptor, which is where VFs will
 518	 * check for the tag
 519	 */
 520	if (ice_is_dvm_ena(hw))
 521		if (vsi->type == ICE_VSI_VF &&
 522		    ice_vf_is_port_vlan_ena(vsi->vf))
 523			rlan_ctx.l2tsel = 1;
 524		else
 525			rlan_ctx.l2tsel = 0;
 526	else
 527		rlan_ctx.l2tsel = 1;
 528
 529	if (ring->hdr_pp) {
 530		rlan_ctx.hbuf = ring->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 531		rlan_ctx.dtype = ICE_RX_DTYPE_HEADER_SPLIT;
 532
 533		/*
 534		 * If the frame is TCP/UDP/SCTP, it will be split by the
 535		 * payload.
 536		 * If not, but it's an IPv4/IPv6 frame, it will be split by
 537		 * the IP header.
 538		 * If not IP, it will be split by the Ethernet header.
 539		 *
 540		 * In any case, the header buffer will never be left empty.
 541		 */
 542		rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 |
 543				    ICE_RLAN_RX_HSPLIT_0_SPLIT_IP |
 544				    ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP |
 545				    ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP;
 546	} else {
 547		rlan_ctx.hbuf = 0;
 548		rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT;
 549		rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT;
 550	}
 551
 552	rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT;
 553
 554	/* This controls whether VLAN is stripped from inner headers
 555	 * The VLAN in the inner L2 header is stripped to the receive
 556	 * descriptor if enabled by this flag.
 557	 */
 558	rlan_ctx.showiv = 0;
 559
 560	/* Max packet size for this queue - must not be set to a larger value
 561	 * than 5 x DBUF
 562	 */
 563	rlan_ctx.rxmax = min_t(u32, vsi->max_frame,
 564			       ICE_MAX_CHAINED_RX_BUFS * ring->rx_buf_len);
 565
 566	/* Rx queue threshold in units of 64 */
 567	rlan_ctx.lrxqthresh = 1;
 568
 569	/* Enable descriptor prefetch */
 570	rlan_ctx.prefena = 1;
 571
 572	/* PF acts as uplink for switchdev; set flex descriptor with src_vsi
 573	 * metadata and flags to allow redirecting to PR netdev
 574	 */
 575	if (ice_is_eswitch_mode_switchdev(vsi->back)) {
 576		ring->flags |= ICE_RX_FLAGS_MULTIDEV;
 577		rxdid = ICE_RXDID_FLEX_NIC_2;
 578	}
 579
 580	/* Enable Flexible Descriptors in the queue context which
 581	 * allows this driver to select a specific receive descriptor format
 582	 * increasing context priority to pick up profile ID; default is 0x01;
 583	 * setting to 0x03 to ensure profile is programming if prev context is
 584	 * of same priority
 585	 */
 586	if (vsi->type != ICE_VSI_VF)
 587		ice_write_qrxflxp_cntxt(hw, pf_q, rxdid, 0x3, true);
 588
 589	/* Absolute queue number out of 2K needs to be passed */
 590	err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);
 591	if (err) {
 592		dev_err(ice_pf_to_dev(vsi->back), "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n",
 593			pf_q, err);
 594		return -EIO;
 595	}
 596
 597	if (vsi->type == ICE_VSI_VF)
 598		return 0;
 599
 600	/* init queue specific tail register */
 601	ring->tail = hw->hw_addr + QRX_TAIL(pf_q);
 602	writel(0, ring->tail);
 603
 604	return 0;
 605}
 606
 607static int ice_rxq_pp_create(struct ice_rx_ring *rq)
 608{
 609	struct libeth_fq fq = {
 610		.count		= rq->count,
 611		.nid		= NUMA_NO_NODE,
 612		.hsplit		= rq->vsi->hsplit,
 613		.xdp		= ice_is_xdp_ena_vsi(rq->vsi),
 614		.buf_len	= LIBIE_MAX_RX_BUF_LEN,
 615	};
 616	int err;
 617
 618	err = libeth_rx_fq_create(&fq, &rq->q_vector->napi);
 619	if (err)
 620		return err;
 621
 622	rq->pp = fq.pp;
 623	rq->rx_fqes = fq.fqes;
 624	rq->truesize = fq.truesize;
 625	rq->rx_buf_len = fq.buf_len;
 626
 627	if (!fq.hsplit)
 628		return 0;
 629
 630	fq = (struct libeth_fq){
 631		.count		= rq->count,
 632		.type		= LIBETH_FQE_HDR,
 633		.nid		= NUMA_NO_NODE,
 634		.xdp		= ice_is_xdp_ena_vsi(rq->vsi),
 635	};
 636
 637	err = libeth_rx_fq_create(&fq, &rq->q_vector->napi);
 638	if (err)
 639		goto destroy;
 640
 641	rq->hdr_pp = fq.pp;
 642	rq->hdr_fqes = fq.fqes;
 643	rq->hdr_truesize = fq.truesize;
 644	rq->rx_hdr_len = fq.buf_len;
 645
 646	return 0;
 647
 648destroy:
 649	ice_rxq_pp_destroy(rq);
 650
 651	return err;
 652}
 653
 654/**
 655 * ice_vsi_cfg_rxq - Configure an Rx queue
 656 * @ring: the ring being configured
 657 *
 658 * Return 0 on success and a negative value on error.
 659 */
 660static int ice_vsi_cfg_rxq(struct ice_rx_ring *ring)
 661{
 662	struct device *dev = ice_pf_to_dev(ring->vsi->back);
 663	u32 num_bufs = ICE_DESC_UNUSED(ring);
 664	int err;
 665
 666	if (ring->vsi->type == ICE_VSI_PF || ring->vsi->type == ICE_VSI_SF ||
 667	    ring->vsi->type == ICE_VSI_LB) {
 668		ice_rx_xsk_pool(ring);
 669		err = ice_realloc_rx_xdp_bufs(ring, ring->xsk_pool);
 670		if (err)
 671			return err;
 672
 673		if (ring->xsk_pool) {
 674			u32 frag_size =
 675				xsk_pool_get_rx_frag_step(ring->xsk_pool);
 676			err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
 677						 ring->q_index,
 678						 ring->q_vector->napi.napi_id,
 679						 frag_size);
 680			if (err)
 681				return err;
 682			err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
 683							 MEM_TYPE_XSK_BUFF_POOL,
 684							 NULL);
 685			if (err)
 686				return err;
 687			xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
 688
 689			dev_info(dev, "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n",
 690				 ring->q_index);
 691		} else {
 692			err = ice_rxq_pp_create(ring);
 693			if (err)
 694				return err;
 695
 696			err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
 697						 ring->q_index,
 698						 ring->q_vector->napi.napi_id,
 699						 ring->truesize);
 700			if (err)
 701				goto err_destroy_fq;
 702
 703			xdp_rxq_info_attach_page_pool(&ring->xdp_rxq,
 704						      ring->pp);
 705		}
 706	}
 707
 708	ring->xdp.data = NULL;
 709	err = ice_setup_rx_ctx(ring);
 710	if (err) {
 711		dev_err(dev, "ice_setup_rx_ctx failed for RxQ %d, err %d\n",
 712			ring->q_index, err);
 713		goto err_destroy_fq;
 714	}
 715
 716	if (ring->xsk_pool) {
 717		bool ok;
 718
 719		if (!xsk_buff_can_alloc(ring->xsk_pool, num_bufs)) {
 720			dev_warn(dev, "XSK buffer pool does not provide enough addresses to fill %d buffers on Rx ring %d\n",
 721				 num_bufs, ring->q_index);
 722			dev_warn(dev, "Change Rx ring/fill queue size to avoid performance issues\n");
 723
 724			return 0;
 725		}
 726
 727		ok = ice_alloc_rx_bufs_zc(ring, ring->xsk_pool, num_bufs);
 728		if (!ok) {
 729			u16 pf_q = ring->vsi->rxq_map[ring->q_index];
 730
 731			dev_info(dev, "Failed to allocate some buffers on XSK buffer pool enabled Rx ring %d (pf_q %d)\n",
 732				 ring->q_index, pf_q);
 733		}
 734
 735		return 0;
 736	}
 737
 738	if (ring->vsi->type == ICE_VSI_CTRL)
 739		ice_init_ctrl_rx_descs(ring, num_bufs);
 740	else
 741		err = ice_alloc_rx_bufs(ring, num_bufs);
 742
 743	if (err)
 744		goto err_destroy_fq;
 745
 746	return 0;
 747
 748err_destroy_fq:
 749	ice_rxq_pp_destroy(ring);
 750
 751	return err;
 752}
 753
 754int ice_vsi_cfg_single_rxq(struct ice_vsi *vsi, u16 q_idx)
 755{
 756	if (q_idx >= vsi->num_rxq)
 757		return -EINVAL;
 758
 759	return ice_vsi_cfg_rxq(vsi->rx_rings[q_idx]);
 760}
 761
 762/**
 763 * ice_vsi_cfg_frame_size - setup max frame size and Rx buffer length
 764 * @vsi: VSI
 765 * @ring: Rx ring to configure
 766 *
 767 * Determine the maximum frame size and Rx buffer length to use for a PF VSI.
 768 * Set these in the associated Rx ring structure.
 769 */
 770static void ice_vsi_cfg_frame_size(struct ice_vsi *vsi, struct ice_rx_ring *ring)
 771{
 772	if (!vsi->netdev) {
 773		vsi->max_frame = ICE_MAX_FRAME_LEGACY_RX;
 774	} else {
 775		vsi->max_frame = ICE_AQ_SET_MAC_FRAME_SIZE_MAX;
 776	}
 777}
 778
 779/**
 780 * ice_vsi_cfg_rxqs - Configure the VSI for Rx
 781 * @vsi: the VSI being configured
 782 *
 783 * Return 0 on success and a negative value on error
 784 * Configure the Rx VSI for operation.
 785 */
 786int ice_vsi_cfg_rxqs(struct ice_vsi *vsi)
 787{
 788	u16 i;
 789
 790	/* set up individual rings */
 791	ice_for_each_rxq(vsi, i) {
 792		struct ice_rx_ring *ring = vsi->rx_rings[i];
 793		int err;
 794
 795		if (vsi->type != ICE_VSI_VF)
 796			ice_vsi_cfg_frame_size(vsi, ring);
 797
 798		err = ice_vsi_cfg_rxq(ring);
 799		if (err)
 800			return err;
 801	}
 802
 803	return 0;
 804}
 805
 806/**
 807 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI
 808 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
 809 *
 810 * This function first tries to find contiguous space. If it is not successful,
 811 * it tries with the scatter approach.
 812 *
 813 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
 814 */
 815int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg)
 816{
 817	int ret = 0;
 818
 819	ret = __ice_vsi_get_qs_contig(qs_cfg);
 820	if (ret) {
 821		/* contig failed, so try with scatter approach */
 822		qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER;
 823		qs_cfg->q_count = min_t(unsigned int, qs_cfg->q_count,
 824					qs_cfg->scatter_count);
 825		ret = __ice_vsi_get_qs_sc(qs_cfg);
 826	}
 827	return ret;
 828}
 829
 830/**
 831 * ice_vsi_ctrl_one_rx_ring - start/stop VSI's Rx ring with no busy wait
 832 * @vsi: the VSI being configured
 833 * @ena: start or stop the Rx ring
 834 * @rxq_idx: 0-based Rx queue index for the VSI passed in
 835 * @wait: wait or don't wait for configuration to finish in hardware
 836 *
 837 * Return 0 on success and negative on error.
 838 */
 839int
 840ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait)
 841{
 842	int pf_q = vsi->rxq_map[rxq_idx];
 843	struct ice_pf *pf = vsi->back;
 844	struct ice_hw *hw = &pf->hw;
 845	u32 rx_reg;
 846
 847	rx_reg = rd32(hw, QRX_CTRL(pf_q));
 848
 849	/* Skip if the queue is already in the requested state */
 850	if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M))
 851		return 0;
 852
 853	/* turn on/off the queue */
 854	if (ena)
 855		rx_reg |= QRX_CTRL_QENA_REQ_M;
 856	else
 857		rx_reg &= ~QRX_CTRL_QENA_REQ_M;
 858	wr32(hw, QRX_CTRL(pf_q), rx_reg);
 859
 860	if (!wait)
 861		return 0;
 862
 863	ice_flush(hw);
 864	return ice_pf_rxq_wait(pf, pf_q, ena);
 865}
 866
 867/**
 868 * ice_vsi_wait_one_rx_ring - wait for a VSI's Rx ring to be stopped/started
 869 * @vsi: the VSI being configured
 870 * @ena: true/false to verify Rx ring has been enabled/disabled respectively
 871 * @rxq_idx: 0-based Rx queue index for the VSI passed in
 872 *
 873 * This routine will wait for the given Rx queue of the VSI to reach the
 874 * enabled or disabled state. Returns -ETIMEDOUT in case of failing to reach
 875 * the requested state after multiple retries; else will return 0 in case of
 876 * success.
 877 */
 878int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx)
 879{
 880	int pf_q = vsi->rxq_map[rxq_idx];
 881	struct ice_pf *pf = vsi->back;
 882
 883	return ice_pf_rxq_wait(pf, pf_q, ena);
 884}
 885
 886/**
 887 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
 888 * @vsi: the VSI being configured
 889 *
 890 * We allocate one q_vector per queue interrupt. If allocation fails we
 891 * return -ENOMEM.
 892 */
 893int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi)
 894{
 895	struct device *dev = ice_pf_to_dev(vsi->back);
 896	u16 v_idx;
 897	int err;
 898
 899	if (vsi->q_vectors[0]) {
 900		dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num);
 901		return -EEXIST;
 902	}
 903
 904	for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) {
 905		err = ice_vsi_alloc_q_vector(vsi, v_idx);
 906		if (err)
 907			goto err_out;
 908	}
 909
 910	return 0;
 911
 912err_out:
 913
 914	dev_info(dev, "Failed to allocate %d q_vectors for VSI %d, new value %d",
 915		 vsi->num_q_vectors, vsi->vsi_num, v_idx);
 916	vsi->num_q_vectors = v_idx;
 917	return v_idx ? 0 : err;
 918}
 919
 920/**
 921 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors
 922 * @vsi: the VSI being configured
 923 *
 924 * This function maps descriptor rings to the queue-specific vectors allotted
 925 * through the MSI-X enabling code. On a constrained vector budget, we map Tx
 926 * and Rx rings to the vector as "efficiently" as possible.
 927 */
 928void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)
 929{
 930	int q_vectors = vsi->num_q_vectors;
 931	u16 tx_rings_rem, rx_rings_rem;
 932	int v_id;
 933
 934	/* initially assigning remaining rings count to VSIs num queue value */
 935	tx_rings_rem = vsi->num_txq;
 936	rx_rings_rem = vsi->num_rxq;
 937
 938	for (v_id = 0; v_id < q_vectors; v_id++) {
 939		struct ice_q_vector *q_vector = vsi->q_vectors[v_id];
 940		u8 tx_rings_per_v, rx_rings_per_v;
 941		u16 q_id, q_base;
 942
 943		/* Tx rings mapping to vector */
 944		tx_rings_per_v = (u8)DIV_ROUND_UP(tx_rings_rem,
 945						  q_vectors - v_id);
 946		q_vector->num_ring_tx = tx_rings_per_v;
 947		q_vector->tx.tx_ring = NULL;
 948		q_vector->tx.itr_idx = ICE_TX_ITR;
 949		q_base = vsi->num_txq - tx_rings_rem;
 950
 951		for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) {
 952			struct ice_tx_ring *tx_ring = vsi->tx_rings[q_id];
 953
 954			tx_ring->q_vector = q_vector;
 955			tx_ring->next = q_vector->tx.tx_ring;
 956			q_vector->tx.tx_ring = tx_ring;
 957		}
 958		tx_rings_rem -= tx_rings_per_v;
 959
 960		/* Rx rings mapping to vector */
 961		rx_rings_per_v = (u8)DIV_ROUND_UP(rx_rings_rem,
 962						  q_vectors - v_id);
 963		q_vector->num_ring_rx = rx_rings_per_v;
 964		q_vector->rx.rx_ring = NULL;
 965		q_vector->rx.itr_idx = ICE_RX_ITR;
 966		q_base = vsi->num_rxq - rx_rings_rem;
 967
 968		for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) {
 969			struct ice_rx_ring *rx_ring = vsi->rx_rings[q_id];
 970
 971			rx_ring->q_vector = q_vector;
 972			rx_ring->next = q_vector->rx.rx_ring;
 973			q_vector->rx.rx_ring = rx_ring;
 974		}
 975		rx_rings_rem -= rx_rings_per_v;
 976	}
 977
 978	if (ice_is_xdp_ena_vsi(vsi))
 979		ice_map_xdp_rings(vsi);
 980}
 981
 982/**
 983 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors
 984 * @vsi: the VSI having memory freed
 985 */
 986void ice_vsi_free_q_vectors(struct ice_vsi *vsi)
 987{
 988	int v_idx;
 989
 990	ice_for_each_q_vector(vsi, v_idx)
 991		ice_free_q_vector(vsi, v_idx);
 992
 993	vsi->num_q_vectors = 0;
 994}
 995
 996/**
 997 * ice_cfg_tstamp - Configure Tx time stamp queue
 998 * @tx_ring: Tx ring to be configured with timestamping
 999 *
1000 * Return: 0 on success and a negative value on error.
1001 */
1002static int
1003ice_cfg_tstamp(struct ice_tx_ring *tx_ring)
1004{
1005	DEFINE_RAW_FLEX(struct ice_aqc_set_txtime_qgrp, txtime_qg_buf,
1006			txtimeqs, 1);
1007	u8 txtime_buf_len = struct_size(txtime_qg_buf, txtimeqs, 1);
1008	struct ice_tstamp_ring *tstamp_ring = tx_ring->tstamp_ring;
1009	struct ice_txtime_ctx txtime_ctx = {};
1010	struct ice_vsi *vsi = tx_ring->vsi;
1011	struct ice_pf *pf = vsi->back;
1012	struct ice_hw *hw = &pf->hw;
1013	u16 pf_q = tx_ring->reg_idx;
1014	int err;
1015
1016	err = ice_setup_txtime_ctx(tstamp_ring, &txtime_ctx);
1017	if (err) {
1018		dev_err(ice_pf_to_dev(pf), "Failed to setup Tx time queue context for queue %d, error: %d\n",
1019			pf_q, err);
1020		return err;
1021	}
1022	ice_pack_txtime_ctx(&txtime_ctx,
1023			    &txtime_qg_buf->txtimeqs[0].txtime_ctx);
1024
1025	tstamp_ring->tail = hw->hw_addr + E830_GLQTX_TXTIME_DBELL_LSB(pf_q);
1026	return ice_aq_set_txtimeq(hw, pf_q, 1, txtime_qg_buf,
1027				  txtime_buf_len, NULL);
1028}
1029
1030/**
1031 * ice_vsi_cfg_txq - Configure single Tx queue
1032 * @vsi: the VSI that queue belongs to
1033 * @ring: Tx ring to be configured
1034 * @qg_buf: queue group buffer
1035 *
1036 * Return: 0 on success and a negative value on error.
1037 */
1038static int
1039ice_vsi_cfg_txq(const struct ice_vsi *vsi, struct ice_tx_ring *ring,
1040		struct ice_aqc_add_tx_qgrp *qg_buf)
1041{
1042	u8 buf_len = struct_size(qg_buf, txqs, 1);
1043	struct ice_tlan_ctx tlan_ctx = { 0 };
1044	struct ice_aqc_add_txqs_perq *txq;
1045	struct ice_channel *ch = ring->ch;
1046	struct ice_pf *pf = vsi->back;
1047	struct ice_hw *hw = &pf->hw;
1048	u32 pf_q, vsi_idx;
1049	int status;
1050	u8 tc;
1051
1052	/* Configure XPS */
1053	ice_cfg_xps_tx_ring(ring);
1054
1055	pf_q = ring->reg_idx;
1056	status = ice_setup_tx_ctx(ring, &tlan_ctx, pf_q);
1057	if (status) {
1058		dev_err(ice_pf_to_dev(pf), "Failed to setup Tx context for queue %d, error: %d\n",
1059			pf_q, status);
1060		return status;
1061	}
1062	/* copy context contents into the qg_buf */
1063	qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);
1064	ice_pack_txq_ctx(&tlan_ctx, &qg_buf->txqs[0].txq_ctx);
1065
1066	/* init queue specific tail reg. It is referred as
1067	 * transmit comm scheduler queue doorbell.
1068	 */
1069	ring->tail = hw->hw_addr + QTX_COMM_DBELL(pf_q);
1070
1071	if (IS_ENABLED(CONFIG_DCB))
1072		tc = ring->dcb_tc;
1073	else
1074		tc = 0;
1075
1076	/* Add unique software queue handle of the Tx queue per
1077	 * TC into the VSI Tx ring
1078	 */
1079	ring->q_handle = ice_calc_txq_handle(vsi, ring, tc);
1080
1081	if (ch) {
1082		tc = 0;
1083		vsi_idx = ch->ch_vsi->idx;
1084	} else {
1085		vsi_idx = vsi->idx;
1086	}
1087
1088	status = ice_ena_vsi_txq(vsi->port_info, vsi_idx, tc, ring->q_handle,
1089				 1, qg_buf, buf_len, NULL);
1090	if (status) {
1091		dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %d\n",
1092			status);
1093		return status;
1094	}
1095
1096	/* Add Tx Queue TEID into the VSI Tx ring from the
1097	 * response. This will complete configuring and
1098	 * enabling the queue.
1099	 */
1100	txq = &qg_buf->txqs[0];
1101	if (pf_q == le16_to_cpu(txq->txq_id))
1102		ring->txq_teid = le32_to_cpu(txq->q_teid);
1103
1104	if (ice_is_txtime_ena(ring)) {
1105		status = ice_alloc_setup_tstamp_ring(ring);
1106		if (status) {
1107			dev_err(ice_pf_to_dev(pf),
1108				"Failed to allocate Tx timestamp ring, error: %d\n",
1109				status);
1110			goto err_setup_tstamp;
1111		}
1112
1113		status = ice_cfg_tstamp(ring);
1114		if (status) {
1115			dev_err(ice_pf_to_dev(pf), "Failed to set Tx Time queue context, error: %d\n",
1116				status);
1117			goto err_cfg_tstamp;
1118		}
1119	}
1120	return 0;
1121
1122err_cfg_tstamp:
1123	ice_free_tx_tstamp_ring(ring);
1124err_setup_tstamp:
1125	ice_dis_vsi_txq(vsi->port_info, vsi_idx, tc, 1, &ring->q_handle,
1126			&ring->reg_idx, &ring->txq_teid, ICE_NO_RESET,
1127			tlan_ctx.vmvf_num, NULL);
1128
1129	return status;
1130}
1131
1132int ice_vsi_cfg_single_txq(struct ice_vsi *vsi, struct ice_tx_ring **tx_rings,
1133			   u16 q_idx)
1134{
1135	DEFINE_RAW_FLEX(struct ice_aqc_add_tx_qgrp, qg_buf, txqs, 1);
1136
1137	if (q_idx >= vsi->alloc_txq || !tx_rings || !tx_rings[q_idx])
1138		return -EINVAL;
1139
1140	qg_buf->num_txqs = 1;
1141
1142	return ice_vsi_cfg_txq(vsi, tx_rings[q_idx], qg_buf);
1143}
1144
1145/**
1146 * ice_vsi_cfg_txqs - Configure the VSI for Tx
1147 * @vsi: the VSI being configured
1148 * @rings: Tx ring array to be configured
1149 * @count: number of Tx ring array elements
1150 *
1151 * Return 0 on success and a negative value on error
1152 * Configure the Tx VSI for operation.
1153 */
1154static int
1155ice_vsi_cfg_txqs(struct ice_vsi *vsi, struct ice_tx_ring **rings, u16 count)
1156{
1157	DEFINE_RAW_FLEX(struct ice_aqc_add_tx_qgrp, qg_buf, txqs, 1);
1158	int err = 0;
1159	u16 q_idx;
1160
1161	qg_buf->num_txqs = 1;
1162
1163	for (q_idx = 0; q_idx < count; q_idx++) {
1164		err = ice_vsi_cfg_txq(vsi, rings[q_idx], qg_buf);
1165		if (err)
1166			break;
1167	}
1168
1169	return err;
1170}
1171
1172/**
1173 * ice_vsi_cfg_lan_txqs - Configure the VSI for Tx
1174 * @vsi: the VSI being configured
1175 *
1176 * Return 0 on success and a negative value on error
1177 * Configure the Tx VSI for operation.
1178 */
1179int ice_vsi_cfg_lan_txqs(struct ice_vsi *vsi)
1180{
1181	return ice_vsi_cfg_txqs(vsi, vsi->tx_rings, vsi->num_txq);
1182}
1183
1184/**
1185 * ice_vsi_cfg_xdp_txqs - Configure Tx queues dedicated for XDP in given VSI
1186 * @vsi: the VSI being configured
1187 *
1188 * Return 0 on success and a negative value on error
1189 * Configure the Tx queues dedicated for XDP in given VSI for operation.
1190 */
1191int ice_vsi_cfg_xdp_txqs(struct ice_vsi *vsi)
1192{
1193	int ret;
1194	int i;
1195
1196	ret = ice_vsi_cfg_txqs(vsi, vsi->xdp_rings, vsi->num_xdp_txq);
1197	if (ret)
1198		return ret;
1199
1200	ice_for_each_rxq(vsi, i)
1201		ice_tx_xsk_pool(vsi, i);
1202
1203	return 0;
1204}
1205
1206/**
1207 * ice_cfg_itr - configure the initial interrupt throttle values
1208 * @hw: pointer to the HW structure
1209 * @q_vector: interrupt vector that's being configured
1210 *
1211 * Configure interrupt throttling values for the ring containers that are
1212 * associated with the interrupt vector passed in.
1213 */
1214void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector)
1215{
1216	ice_cfg_itr_gran(hw);
1217
1218	if (q_vector->num_ring_rx)
1219		ice_write_itr(&q_vector->rx, q_vector->rx.itr_setting);
1220
1221	if (q_vector->num_ring_tx)
1222		ice_write_itr(&q_vector->tx, q_vector->tx.itr_setting);
1223
1224	ice_write_intrl(q_vector, q_vector->intrl);
1225}
1226
1227/**
1228 * ice_cfg_txq_interrupt - configure interrupt on Tx queue
1229 * @vsi: the VSI being configured
1230 * @txq: Tx queue being mapped to MSI-X vector
1231 * @msix_idx: MSI-X vector index within the function
1232 * @itr_idx: ITR index of the interrupt cause
1233 *
1234 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector
1235 * within the function space.
1236 */
1237void
1238ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)
1239{
1240	struct ice_pf *pf = vsi->back;
1241	struct ice_hw *hw = &pf->hw;
1242	u32 val;
1243
1244	itr_idx = FIELD_PREP(QINT_TQCTL_ITR_INDX_M, itr_idx);
1245
1246	val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |
1247	      FIELD_PREP(QINT_TQCTL_MSIX_INDX_M, msix_idx);
1248
1249	wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);
1250	if (ice_is_xdp_ena_vsi(vsi)) {
1251		u32 xdp_txq = txq + vsi->num_xdp_txq;
1252
1253		wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]),
1254		     val);
1255	}
1256	ice_flush(hw);
1257}
1258
1259/**
1260 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue
1261 * @vsi: the VSI being configured
1262 * @rxq: Rx queue being mapped to MSI-X vector
1263 * @msix_idx: MSI-X vector index within the function
1264 * @itr_idx: ITR index of the interrupt cause
1265 *
1266 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector
1267 * within the function space.
1268 */
1269void
1270ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)
1271{
1272	struct ice_pf *pf = vsi->back;
1273	struct ice_hw *hw = &pf->hw;
1274	u32 val;
1275
1276	itr_idx = FIELD_PREP(QINT_RQCTL_ITR_INDX_M, itr_idx);
1277
1278	val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |
1279	      FIELD_PREP(QINT_RQCTL_MSIX_INDX_M, msix_idx);
1280
1281	wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);
1282
1283	ice_flush(hw);
1284}
1285
1286/**
1287 * ice_trigger_sw_intr - trigger a software interrupt
1288 * @hw: pointer to the HW structure
1289 * @q_vector: interrupt vector to trigger the software interrupt for
1290 */
1291void ice_trigger_sw_intr(struct ice_hw *hw, const struct ice_q_vector *q_vector)
1292{
1293	wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx),
1294	     (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) |
1295	     GLINT_DYN_CTL_SWINT_TRIG_M |
1296	     GLINT_DYN_CTL_INTENA_M);
1297}
1298
1299/**
1300 * ice_vsi_stop_tx_ring - Disable single Tx ring
1301 * @vsi: the VSI being configured
1302 * @rst_src: reset source
1303 * @rel_vmvf_num: Relative ID of VF/VM
1304 * @ring: Tx ring to be stopped
1305 * @txq_meta: Meta data of Tx ring to be stopped
1306 */
1307int
1308ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
1309		     u16 rel_vmvf_num, struct ice_tx_ring *ring,
1310		     struct ice_txq_meta *txq_meta)
1311{
1312	struct ice_pf *pf = vsi->back;
1313	struct ice_q_vector *q_vector;
1314	struct ice_hw *hw = &pf->hw;
1315	int status;
1316	u32 val;
1317
1318	/* clear cause_ena bit for disabled queues */
1319	val = rd32(hw, QINT_TQCTL(ring->reg_idx));
1320	val &= ~QINT_TQCTL_CAUSE_ENA_M;
1321	wr32(hw, QINT_TQCTL(ring->reg_idx), val);
1322
1323	/* software is expected to wait for 100 ns */
1324	ndelay(100);
1325
1326	/* trigger a software interrupt for the vector
1327	 * associated to the queue to schedule NAPI handler
1328	 */
1329	q_vector = ring->q_vector;
1330	if (q_vector && !(vsi->vf && ice_is_vf_disabled(vsi->vf)))
1331		ice_trigger_sw_intr(hw, q_vector);
1332
1333	status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,
1334				 txq_meta->tc, 1, &txq_meta->q_handle,
1335				 &txq_meta->q_id, &txq_meta->q_teid, rst_src,
1336				 rel_vmvf_num, NULL);
1337
1338	/* if the disable queue command was exercised during an
1339	 * active reset flow, -EBUSY is returned.
1340	 * This is not an error as the reset operation disables
1341	 * queues at the hardware level anyway.
1342	 */
1343	if (status == -EBUSY) {
1344		dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n");
1345	} else if (status == -ENOENT) {
1346		dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n");
1347	} else if (status) {
1348		dev_dbg(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %d\n",
1349			status);
1350		return status;
1351	}
1352
1353	return 0;
1354}
1355
1356/**
1357 * ice_fill_txq_meta - Prepare the Tx queue's meta data
1358 * @vsi: VSI that ring belongs to
1359 * @ring: ring that txq_meta will be based on
1360 * @txq_meta: a helper struct that wraps Tx queue's information
1361 *
1362 * Set up a helper struct that will contain all the necessary fields that
1363 * are needed for stopping Tx queue
1364 */
1365void
1366ice_fill_txq_meta(const struct ice_vsi *vsi, struct ice_tx_ring *ring,
1367		  struct ice_txq_meta *txq_meta)
1368{
1369	struct ice_channel *ch = ring->ch;
1370	u8 tc;
1371
1372	if (IS_ENABLED(CONFIG_DCB))
1373		tc = ring->dcb_tc;
1374	else
1375		tc = 0;
1376
1377	txq_meta->q_id = ring->reg_idx;
1378	txq_meta->q_teid = ring->txq_teid;
1379	txq_meta->q_handle = ring->q_handle;
1380	if (ch) {
1381		txq_meta->vsi_idx = ch->ch_vsi->idx;
1382		txq_meta->tc = 0;
1383	} else {
1384		txq_meta->vsi_idx = vsi->idx;
1385		txq_meta->tc = tc;
1386	}
1387}
1388
1389/**
1390 * ice_qp_reset_stats - Resets all stats for rings of given index
1391 * @vsi: VSI that contains rings of interest
1392 * @q_idx: ring index in array
1393 */
1394static void ice_qp_reset_stats(struct ice_vsi *vsi, u16 q_idx)
1395{
1396	struct ice_vsi_stats *vsi_stat;
1397	struct ice_pf *pf;
1398
1399	pf = vsi->back;
1400	if (!pf->vsi_stats)
1401		return;
1402
1403	vsi_stat = pf->vsi_stats[vsi->idx];
1404	if (!vsi_stat)
1405		return;
1406
1407	memset(&vsi_stat->rx_ring_stats[q_idx]->rx_stats, 0,
1408	       sizeof(vsi_stat->rx_ring_stats[q_idx]->rx_stats));
1409	memset(&vsi_stat->tx_ring_stats[q_idx]->stats, 0,
1410	       sizeof(vsi_stat->tx_ring_stats[q_idx]->stats));
1411	if (vsi->xdp_rings)
1412		memset(&vsi->xdp_rings[q_idx]->ring_stats->stats, 0,
1413		       sizeof(vsi->xdp_rings[q_idx]->ring_stats->stats));
1414}
1415
1416/**
1417 * ice_qp_clean_rings - Cleans all the rings of a given index
1418 * @vsi: VSI that contains rings of interest
1419 * @q_idx: ring index in array
1420 */
1421static void ice_qp_clean_rings(struct ice_vsi *vsi, u16 q_idx)
1422{
1423	ice_clean_tx_ring(vsi->tx_rings[q_idx]);
1424	if (vsi->xdp_rings)
1425		ice_clean_tx_ring(vsi->xdp_rings[q_idx]);
1426	ice_clean_rx_ring(vsi->rx_rings[q_idx]);
1427}
1428
1429/**
1430 * ice_qp_dis - Disables a queue pair
1431 * @vsi: VSI of interest
1432 * @q_idx: ring index in array
1433 *
1434 * Returns 0 on success, negative on failure.
1435 */
1436int ice_qp_dis(struct ice_vsi *vsi, u16 q_idx)
1437{
1438	struct ice_txq_meta txq_meta = { };
1439	struct ice_q_vector *q_vector;
1440	struct ice_tx_ring *tx_ring;
1441	struct ice_rx_ring *rx_ring;
1442	int fail = 0;
1443	int err;
1444
1445	if (q_idx >= vsi->num_rxq || q_idx >= vsi->num_txq)
1446		return -EINVAL;
1447
1448	tx_ring = vsi->tx_rings[q_idx];
1449	rx_ring = vsi->rx_rings[q_idx];
1450	q_vector = rx_ring->q_vector;
1451
1452	synchronize_net();
1453	netif_carrier_off(vsi->netdev);
1454	netif_tx_stop_queue(netdev_get_tx_queue(vsi->netdev, q_idx));
1455
1456	ice_qvec_dis_irq(vsi, rx_ring, q_vector);
1457	ice_qvec_toggle_napi(vsi, q_vector, false);
1458
1459	ice_fill_txq_meta(vsi, tx_ring, &txq_meta);
1460	err = ice_vsi_stop_tx_ring(vsi, ICE_NO_RESET, 0, tx_ring, &txq_meta);
1461	if (!fail)
1462		fail = err;
1463	if (vsi->xdp_rings) {
1464		struct ice_tx_ring *xdp_ring = vsi->xdp_rings[q_idx];
1465
1466		memset(&txq_meta, 0, sizeof(txq_meta));
1467		ice_fill_txq_meta(vsi, xdp_ring, &txq_meta);
1468		err = ice_vsi_stop_tx_ring(vsi, ICE_NO_RESET, 0, xdp_ring,
1469					   &txq_meta);
1470		if (!fail)
1471			fail = err;
1472	}
1473
1474	ice_vsi_ctrl_one_rx_ring(vsi, false, q_idx, false);
1475	ice_qp_clean_rings(vsi, q_idx);
1476	ice_qp_reset_stats(vsi, q_idx);
1477
1478	return fail;
1479}
1480
1481/**
1482 * ice_qp_ena - Enables a queue pair
1483 * @vsi: VSI of interest
1484 * @q_idx: ring index in array
1485 *
1486 * Returns 0 on success, negative on failure.
1487 */
1488int ice_qp_ena(struct ice_vsi *vsi, u16 q_idx)
1489{
1490	struct ice_q_vector *q_vector;
1491	int fail = 0;
1492	bool link_up;
1493	int err;
1494
1495	err = ice_vsi_cfg_single_txq(vsi, vsi->tx_rings, q_idx);
1496	if (!fail)
1497		fail = err;
1498
1499	if (ice_is_xdp_ena_vsi(vsi)) {
1500		struct ice_tx_ring *xdp_ring = vsi->xdp_rings[q_idx];
1501
1502		err = ice_vsi_cfg_single_txq(vsi, vsi->xdp_rings, q_idx);
1503		if (!fail)
1504			fail = err;
1505		ice_set_ring_xdp(xdp_ring);
1506		ice_tx_xsk_pool(vsi, q_idx);
1507	}
1508
1509	err = ice_vsi_cfg_single_rxq(vsi, q_idx);
1510	if (!fail)
1511		fail = err;
1512
1513	q_vector = vsi->rx_rings[q_idx]->q_vector;
1514	ice_qvec_cfg_msix(vsi, q_vector, q_idx);
1515
1516	err = ice_vsi_ctrl_one_rx_ring(vsi, true, q_idx, true);
1517	if (!fail)
1518		fail = err;
1519
1520	ice_qvec_toggle_napi(vsi, q_vector, true);
1521	ice_qvec_ena_irq(vsi, q_vector);
1522
1523	/* make sure NAPI sees updated ice_{t,x}_ring::xsk_pool */
1524	synchronize_net();
1525	ice_get_link_status(vsi->port_info, &link_up);
1526	if (link_up) {
1527		netif_tx_start_queue(netdev_get_tx_queue(vsi->netdev, q_idx));
1528		netif_carrier_on(vsi->netdev);
1529	}
1530
1531	return fail;
1532}