FILE
ice_adminq_cmd.h
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linux-6.19.14/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (c) 2018, Intel Corporation. */ 3 4#ifndef _ICE_ADMINQ_CMD_H_ 5#define _ICE_ADMINQ_CMD_H_ 6 7#include <linux/net/intel/libie/adminq.h> 8 9/* This header file defines the Admin Queue commands, error codes and 10 * descriptor format. It is shared between Firmware and Software. 11 */ 12 13#define ICE_MAX_VSI 768 14#define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 15#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 16 17#define ICE_RXQ_CTX_SIZE_DWORDS 8 18#define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) 19 20typedef struct __packed { u8 buf[ICE_RXQ_CTX_SZ]; } ice_rxq_ctx_buf_t; 21 22/* The Tx queue context is 40 bytes, and includes some internal state. The 23 * Admin Queue buffers don't include the internal state, so only include the 24 * first 22 bytes of the context. 25 */ 26#define ICE_TXQ_CTX_SZ 22 27 28typedef struct __packed { u8 buf[ICE_TXQ_CTX_SZ]; } ice_txq_ctx_buf_t; 29 30#define ICE_TXQ_CTX_FULL_SIZE_DWORDS 10 31#define ICE_TXQ_CTX_FULL_SZ \ 32 (ICE_TXQ_CTX_FULL_SIZE_DWORDS * sizeof(u32)) 33 34typedef struct __packed { u8 buf[ICE_TXQ_CTX_FULL_SZ]; } ice_txq_ctx_buf_full_t; 35 36#define ICE_TXTIME_CTX_SZ 25 37 38typedef struct __packed { u8 buf[ICE_TXTIME_CTX_SZ]; } ice_txtime_ctx_buf_t; 39 40/* Queue Shutdown (direct 0x0003) */ 41struct ice_aqc_q_shutdown { 42 u8 driver_unloading; 43#define ICE_AQC_DRIVER_UNLOADING BIT(0) 44 u8 reserved[15]; 45}; 46 47/* Manage MAC address, read command - indirect (0x0107) 48 * This struct is also used for the response 49 */ 50struct ice_aqc_manage_mac_read { 51 __le16 flags; /* Zeroed by device driver */ 52#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 53#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 54#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 55#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 56#define ICE_AQC_MAN_MAC_READ_S 4 57#define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 58 u8 rsvd[2]; 59 u8 num_addr; /* Used in response */ 60 u8 rsvd1[3]; 61 __le32 addr_high; 62 __le32 addr_low; 63}; 64 65/* Response buffer format for manage MAC read command */ 66struct ice_aqc_manage_mac_read_resp { 67 u8 lport_num; 68 u8 addr_type; 69#define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 70#define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 71 u8 mac_addr[ETH_ALEN]; 72}; 73 74/* Manage MAC address, write command - direct (0x0108) */ 75struct ice_aqc_manage_mac_write { 76 u8 rsvd; 77 u8 flags; 78#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 79#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 80#define ICE_AQC_MAN_MAC_WR_S 6 81#define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 82#define ICE_AQC_MAN_MAC_UPDATE_LAA 0 83#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 84 /* byte stream in network order */ 85 u8 mac_addr[ETH_ALEN]; 86 __le32 addr_high; 87 __le32 addr_low; 88}; 89 90/* Clear PXE Command and response (direct 0x0110) */ 91struct ice_aqc_clear_pxe { 92 u8 rx_cnt; 93#define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 94 u8 reserved[15]; 95}; 96 97/* Get switch configuration (0x0200) */ 98struct ice_aqc_get_sw_cfg { 99 /* Reserved for command and copy of request flags for response */ 100 __le16 flags; 101 /* First desc in case of command and next_elem in case of response 102 * In case of response, if it is not zero, means all the configuration 103 * was not returned and new command shall be sent with this value in 104 * the 'first desc' field 105 */ 106 __le16 element; 107 /* Reserved for command, only used for response */ 108 __le16 num_elems; 109 __le16 rsvd; 110 __le32 addr_high; 111 __le32 addr_low; 112}; 113 114/* Each entry in the response buffer is of the following type: */ 115struct ice_aqc_get_sw_cfg_resp_elem { 116 /* VSI/Port Number */ 117 __le16 vsi_port_num; 118#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 119#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 120 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 121#define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 122#define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 123#define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 124#define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 125#define ICE_AQC_GET_SW_CONF_RESP_VSI 2 126 127 /* SWID VSI/Port belongs to */ 128 __le16 swid; 129 130 /* Bit 14..0 : PF/VF number VSI belongs to 131 * Bit 15 : VF indication bit 132 */ 133 __le16 pf_vf_num; 134#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 135#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 136 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 137#define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 138}; 139 140/* Loopback port parameter mode values. */ 141enum ice_local_fwd_mode { 142 ICE_LOCAL_FWD_MODE_ENABLED = 0, 143 ICE_LOCAL_FWD_MODE_DISABLED = 1, 144 ICE_LOCAL_FWD_MODE_PRIORITIZED = 2, 145}; 146 147/* Set Port parameters, (direct, 0x0203) */ 148struct ice_aqc_set_port_params { 149 __le16 cmd_flags; 150#define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 151 __le16 bad_frame_vsi; 152 __le16 swid; 153#define ICE_AQC_PORT_SWID_VALID BIT(15) 154#define ICE_AQC_PORT_SWID_M 0xFF 155 u8 local_fwd_mode; 156#define ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID BIT(2) 157 u8 reserved[9]; 158}; 159 160/* These resource type defines are used for all switch resource 161 * commands where a resource type is required, such as: 162 * Get Resource Allocation command (indirect 0x0204) 163 * Allocate Resources command (indirect 0x0208) 164 * Free Resources command (indirect 0x0209) 165 * Get Allocated Resource Descriptors Command (indirect 0x020A) 166 * Share Resource command (indirect 0x020B) 167 */ 168#define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 169#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 170#define ICE_AQC_RES_TYPE_RECIPE 0x05 171#define ICE_AQC_RES_TYPE_SWID 0x07 172#define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 173#define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 174#define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 175#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 176#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 177#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 178#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 179 180#define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 181#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 182#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 183#define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14) 184#define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15) 185 186#define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 187 188#define ICE_AQC_RES_TYPE_S 0 189#define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 190 191/* Allocate Resources command (indirect 0x0208) 192 * Free Resources command (indirect 0x0209) 193 * Share Resource command (indirect 0x020B) 194 */ 195struct ice_aqc_alloc_free_res_cmd { 196 __le16 num_entries; /* Number of Resource entries */ 197 u8 reserved[6]; 198 __le32 addr_high; 199 __le32 addr_low; 200}; 201 202/* Resource descriptor */ 203struct ice_aqc_res_elem { 204 union { 205 __le16 sw_resp; 206 __le16 flu_resp; 207 } e; 208}; 209 210/* Buffer for Allocate/Free Resources commands */ 211struct ice_aqc_alloc_free_res_elem { 212 __le16 res_type; /* Types defined above cmd 0x0204 */ 213#define ICE_AQC_RES_TYPE_SHARED_S 7 214#define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 215#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 216#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 217 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 218 __le16 num_elems; 219 struct ice_aqc_res_elem elem[]; 220}; 221 222/* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 223struct ice_aqc_set_vlan_mode { 224 u8 reserved; 225 u8 l2tag_prio_tagging; 226#define ICE_AQ_VLAN_PRIO_TAG_S 0 227#define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 228#define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 229#define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 230#define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 231#define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 232#define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 233#define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 234#define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 235 u8 l2tag_reserved[64]; 236 u8 rdma_packet; 237#define ICE_AQ_VLAN_RDMA_TAG_S 0 238#define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 239#define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 240#define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 241 u8 rdma_reserved[2]; 242 u8 mng_vlan_prot_id; 243#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 244#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 245 u8 prot_id_reserved[30]; 246}; 247 248/* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 249struct ice_aqc_get_vlan_mode { 250 u8 vlan_mode; 251#define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 252 u8 l2tag_prio_tagging; 253 u8 reserved[98]; 254}; 255 256/* Add VSI (indirect 0x0210) 257 * Update VSI (indirect 0x0211) 258 * Get VSI (indirect 0x0212) 259 * Free VSI (indirect 0x0213) 260 */ 261struct ice_aqc_add_get_update_free_vsi { 262 __le16 vsi_num; 263#define ICE_AQ_VSI_NUM_S 0 264#define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 265#define ICE_AQ_VSI_IS_VALID BIT(15) 266 __le16 cmd_flags; 267#define ICE_AQ_VSI_KEEP_ALLOC 0x1 268 u8 vf_id; 269 u8 reserved; 270 __le16 vsi_flags; 271#define ICE_AQ_VSI_TYPE_S 0 272#define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 273#define ICE_AQ_VSI_TYPE_VF 0x0 274#define ICE_AQ_VSI_TYPE_VMDQ2 0x1 275#define ICE_AQ_VSI_TYPE_PF 0x2 276#define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 277 __le32 addr_high; 278 __le32 addr_low; 279}; 280 281/* Response descriptor for: 282 * Add VSI (indirect 0x0210) 283 * Update VSI (indirect 0x0211) 284 * Free VSI (indirect 0x0213) 285 */ 286struct ice_aqc_add_update_free_vsi_resp { 287 __le16 vsi_num; 288 __le16 ext_status; 289 __le16 vsi_used; 290 __le16 vsi_free; 291 __le32 addr_high; 292 __le32 addr_low; 293}; 294 295struct ice_aqc_vsi_props { 296 __le16 valid_sections; 297#define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 298#define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 299#define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 300#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 301#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 302#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 303#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 304#define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 305#define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 306#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 307#define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 308 /* switch section */ 309 u8 sw_id; 310 u8 sw_flags; 311#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 312#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 313#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 314 u8 sw_flags2; 315#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 316#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 317#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 318#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 319 u8 veb_stat_id; 320#define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 321#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 322#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 323 /* security section */ 324 u8 sec_flags; 325#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 326#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 327#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 328#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 329#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 330 u8 sec_reserved; 331 /* VLAN section */ 332 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 333 u8 inner_vlan_reserved[2]; 334 u8 inner_vlan_flags; 335#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 336#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 337#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 338#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 339#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 340#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 341#define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 342#define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 343#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U 344#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U 345#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U 346#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U 347 u8 inner_vlan_reserved2[3]; 348 /* ingress egress up sections */ 349 __le32 ingress_table; /* bitmap, 3 bits per up */ 350#define ICE_AQ_VSI_UP_TABLE_UP0_S 0 351#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 352#define ICE_AQ_VSI_UP_TABLE_UP1_S 3 353#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 354#define ICE_AQ_VSI_UP_TABLE_UP2_S 6 355#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 356#define ICE_AQ_VSI_UP_TABLE_UP3_S 9 357#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 358#define ICE_AQ_VSI_UP_TABLE_UP4_S 12 359#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 360#define ICE_AQ_VSI_UP_TABLE_UP5_S 15 361#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 362#define ICE_AQ_VSI_UP_TABLE_UP6_S 18 363#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 364#define ICE_AQ_VSI_UP_TABLE_UP7_S 21 365#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 366 __le32 egress_table; /* same defines as for ingress table */ 367 /* outer tags section */ 368 __le16 port_based_outer_vlan; 369 u8 outer_vlan_flags; 370#define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 371#define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 372#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 373#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 374#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 375#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 376#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 377#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 378#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 379#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 380#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 381#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 382#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 383#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 384#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 385#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 386#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 387#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 388#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 389 u8 outer_vlan_reserved; 390 /* queue mapping section */ 391 __le16 mapping_flags; 392#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 393#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 394 __le16 q_mapping[16]; 395#define ICE_AQ_VSI_Q_S 0 396#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 397 __le16 tc_mapping[8]; 398#define ICE_AQ_VSI_TC_Q_OFFSET_S 0 399#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 400#define ICE_AQ_VSI_TC_Q_NUM_S 11 401#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 402 /* queueing option section */ 403 u8 q_opt_rss; 404#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 405#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 406#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 407#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 408#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 409#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 410#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 411#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 412#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6) 413#define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U 414#define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U 415#define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U 416#define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH 0x3U 417 u8 q_opt_tc; 418#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 419#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 420#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 421 u8 q_opt_flags; 422#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 423 u8 q_opt_reserved[3]; 424 /* outer up section */ 425 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 426 /* section 10 */ 427 __le16 sect_10_reserved; 428 /* flow director section */ 429 __le16 fd_options; 430#define ICE_AQ_VSI_FD_ENABLE BIT(0) 431#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 432#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 433 __le16 max_fd_fltr_dedicated; 434 __le16 max_fd_fltr_shared; 435 __le16 fd_def_q; 436#define ICE_AQ_VSI_FD_DEF_Q_S 0 437#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 438#define ICE_AQ_VSI_FD_DEF_GRP_S 12 439#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 440 __le16 fd_report_opt; 441#define ICE_AQ_VSI_FD_REPORT_Q_S 0 442#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 443#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 444#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 445#define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 446 /* PASID section */ 447 __le32 pasid_id; 448#define ICE_AQ_VSI_PASID_ID_S 0 449#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 450#define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 451 u8 reserved[24]; 452}; 453 454#define ICE_MAX_NUM_RECIPES 64 455 456/* Add/Get Recipe (indirect 0x0290/0x0292) */ 457struct ice_aqc_add_get_recipe { 458 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 459 __le16 return_index; /* Input, used for Get cmd only */ 460 u8 reserved[4]; 461 __le32 addr_high; 462 __le32 addr_low; 463}; 464 465struct ice_aqc_recipe_content { 466 u8 rid; 467#define ICE_AQ_RECIPE_ID_S 0 468#define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 469#define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 470#define ICE_AQ_SW_ID_LKUP_IDX 0 471 u8 lkup_indx[5]; 472#define ICE_AQ_RECIPE_LKUP_DATA_S 0 473#define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 474#define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 475#define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 476 __le16 mask[5]; 477 u8 result_indx; 478#define ICE_AQ_RECIPE_RESULT_DATA_S 0 479#define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 480#define ICE_AQ_RECIPE_RESULT_EN BIT(7) 481 u8 rsvd0[3]; 482 u8 act_ctrl_join_priority; 483 u8 act_ctrl_fwd_priority; 484#define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 485#define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 486 u8 act_ctrl; 487#define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 488#define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 489#define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 490#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 491#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 492 u8 rsvd1; 493 __le32 dflt_act; 494#define ICE_AQ_RECIPE_DFLT_ACT_S 0 495#define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 496#define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 497}; 498 499struct ice_aqc_recipe_data_elem { 500 u8 recipe_indx; 501 u8 resp_bits; 502#define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 503 u8 rsvd0[2]; 504 u8 recipe_bitmap[8]; 505 u8 rsvd1[4]; 506 struct ice_aqc_recipe_content content; 507 u8 rsvd2[20]; 508}; 509 510/* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 511struct ice_aqc_recipe_to_profile { 512 __le16 profile_id; 513 u8 rsvd[6]; 514 __le64 recipe_assoc; 515}; 516static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16); 517 518/* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 519 */ 520struct ice_aqc_sw_rules { 521 /* ops: add switch rules, referring the number of rules. 522 * ops: update switch rules, referring the number of filters 523 * ops: remove switch rules, referring the entry index. 524 * ops: get switch rules, referring to the number of filters. 525 */ 526 __le16 num_rules_fltr_entry_index; 527 u8 reserved[6]; 528 __le32 addr_high; 529 __le32 addr_low; 530}; 531 532/* Add switch rule response: 533 * Content of return buffer is same as the input buffer. The status field and 534 * LUT index are updated as part of the response 535 */ 536struct ice_aqc_sw_rules_elem_hdr { 537 __le16 type; /* Switch rule type, one of T_... */ 538#define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 539#define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 540#define ICE_AQC_SW_RULES_T_LG_ACT 0x2 541#define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 542#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 543#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 544#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 545 __le16 status; 546} __packed __aligned(sizeof(__le16)); 547 548/* Add/Update/Get/Remove lookup Rx/Tx command/response entry 549 * This structures describes the lookup rules and associated actions. "index" 550 * is returned as part of a response to a successful Add command, and can be 551 * used to identify the rule for Update/Get/Remove commands. 552 */ 553struct ice_sw_rule_lkup_rx_tx { 554 struct ice_aqc_sw_rules_elem_hdr hdr; 555 556 __le16 recipe_id; 557#define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 558 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 559 __le16 src; 560 __le32 act; 561 562 /* Bit 0:1 - Action type */ 563#define ICE_SINGLE_ACT_TYPE_S 0x00 564#define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 565 566 /* Bit 2 - Loop back enable 567 * Bit 3 - LAN enable 568 */ 569#define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 570#define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 571 572 /* Action type = 0 - Forward to VSI or VSI list */ 573#define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 574 575#define ICE_SINGLE_ACT_VSI_ID_S 4 576#define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 577#define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 578#define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 579 /* This bit needs to be set if action is forward to VSI list */ 580#define ICE_SINGLE_ACT_VSI_LIST BIT(14) 581#define ICE_SINGLE_ACT_VALID_BIT BIT(17) 582#define ICE_SINGLE_ACT_DROP BIT(18) 583 584 /* Action type = 1 - Forward to Queue of Queue group */ 585#define ICE_SINGLE_ACT_TO_Q 0x1 586#define ICE_SINGLE_ACT_Q_INDEX_S 4 587#define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 588#define ICE_SINGLE_ACT_Q_REGION_S 15 589#define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 590#define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 591 592 /* Action type = 2 - Prune */ 593#define ICE_SINGLE_ACT_PRUNE 0x2 594#define ICE_SINGLE_ACT_EGRESS BIT(15) 595#define ICE_SINGLE_ACT_INGRESS BIT(16) 596#define ICE_SINGLE_ACT_PRUNET BIT(17) 597 /* Bit 18 should be set to 0 for this action */ 598 599 /* Action type = 2 - Pointer */ 600#define ICE_SINGLE_ACT_PTR 0x2 601#define ICE_SINGLE_ACT_PTR_VAL_S 4 602#define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 603 /* Bit 18 should be set to 1 */ 604#define ICE_SINGLE_ACT_PTR_BIT BIT(18) 605 606 /* Action type = 3 - Other actions. Last two bits 607 * are other action identifier 608 */ 609#define ICE_SINGLE_ACT_OTHER_ACTS 0x3 610#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 611#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 612 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 613 614 /* Bit 17:18 - Defines other actions */ 615 /* Other action = 0 - Mirror VSI */ 616#define ICE_SINGLE_OTHER_ACT_MIRROR 0 617#define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 618#define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 619 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 620 621 /* Other action = 3 - Set Stat count */ 622#define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 623#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 624#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 625 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 626 627 __le16 index; /* The index of the rule in the lookup table */ 628 /* Length and values of the header to be matched per recipe or 629 * lookup-type 630 */ 631 __le16 hdr_len; 632 u8 hdr_data[]; 633} __packed __aligned(sizeof(__le16)); 634 635/* Add/Update/Remove large action command/response entry 636 * "index" is returned as part of a response to a successful Add command, and 637 * can be used to identify the action for Update/Get/Remove commands. 638 */ 639struct ice_sw_rule_lg_act { 640 struct ice_aqc_sw_rules_elem_hdr hdr; 641 642 __le16 index; /* Index in large action table */ 643 __le16 size; 644 /* Max number of large actions */ 645#define ICE_MAX_LG_ACT 4 646 /* Bit 0:1 - Action type */ 647#define ICE_LG_ACT_TYPE_S 0 648#define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 649 650 /* Action type = 0 - Forward to VSI or VSI list */ 651#define ICE_LG_ACT_VSI_FORWARDING 0 652#define ICE_LG_ACT_VSI_ID_S 3 653#define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 654#define ICE_LG_ACT_VSI_LIST_ID_S 3 655#define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 656 /* This bit needs to be set if action is forward to VSI list */ 657#define ICE_LG_ACT_VSI_LIST BIT(13) 658 659#define ICE_LG_ACT_VALID_BIT BIT(16) 660 661 /* Action type = 1 - Forward to Queue of Queue group */ 662#define ICE_LG_ACT_TO_Q 0x1 663#define ICE_LG_ACT_Q_INDEX_S 3 664#define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 665#define ICE_LG_ACT_Q_REGION_S 14 666#define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 667#define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 668 669 /* Action type = 2 - Prune */ 670#define ICE_LG_ACT_PRUNE 0x2 671#define ICE_LG_ACT_EGRESS BIT(14) 672#define ICE_LG_ACT_INGRESS BIT(15) 673#define ICE_LG_ACT_PRUNET BIT(16) 674 675 /* Action type = 3 - Mirror VSI */ 676#define ICE_LG_OTHER_ACT_MIRROR 0x3 677#define ICE_LG_ACT_MIRROR_VSI_ID_S 3 678#define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 679 680 /* Action type = 5 - Generic Value */ 681#define ICE_LG_ACT_GENERIC 0x5 682#define ICE_LG_ACT_GENERIC_VALUE_S 3 683#define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 684#define ICE_LG_ACT_GENERIC_OFFSET_S 19 685#define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 686#define ICE_LG_ACT_GENERIC_PRIORITY_S 22 687#define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 688#define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 689 690 /* Action = 7 - Set Stat count */ 691#define ICE_LG_ACT_STAT_COUNT 0x7 692#define ICE_LG_ACT_STAT_COUNT_S 3 693#define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 694 __le32 act[]; /* array of size for actions */ 695} __packed __aligned(sizeof(__le16)); 696 697/* Add/Update/Remove VSI list command/response entry 698 * "index" is returned as part of a response to a successful Add command, and 699 * can be used to identify the VSI list for Update/Get/Remove commands. 700 */ 701struct ice_sw_rule_vsi_list { 702 struct ice_aqc_sw_rules_elem_hdr hdr; 703 704 __le16 index; /* Index of VSI/Prune list */ 705 __le16 number_vsi; 706 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 707} __packed __aligned(sizeof(__le16)); 708 709/* Query PFC Mode (direct 0x0302) 710 * Set PFC Mode (direct 0x0303) 711 */ 712struct ice_aqc_set_query_pfc_mode { 713 u8 pfc_mode; 714/* For Query Command response, reserved in all other cases */ 715#define ICE_AQC_PFC_VLAN_BASED_PFC 1 716#define ICE_AQC_PFC_DSCP_BASED_PFC 2 717 u8 rsvd[15]; 718}; 719/* Get Default Topology (indirect 0x0400) */ 720struct ice_aqc_get_topo { 721 u8 port_num; 722 u8 num_branches; 723 __le16 reserved1; 724 __le32 reserved2; 725 __le32 addr_high; 726 __le32 addr_low; 727}; 728 729/* Get/Set Tx Topology (indirect 0x0418/0x0417) */ 730struct ice_aqc_get_set_tx_topo { 731 u8 set_flags; 732#define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0) 733#define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1) 734#define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4) 735#define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5) 736 737 u8 get_flags; 738#define ICE_AQC_TX_TOPO_GET_RAM 2 739 740 __le16 reserved1; 741 __le32 reserved2; 742 __le32 addr_high; 743 __le32 addr_low; 744}; 745 746/* Update TSE (indirect 0x0403) 747 * Get TSE (indirect 0x0404) 748 * Add TSE (indirect 0x0401) 749 * Delete TSE (indirect 0x040F) 750 * Move TSE (indirect 0x0408) 751 * Suspend Nodes (indirect 0x0409) 752 * Resume Nodes (indirect 0x040A) 753 */ 754struct ice_aqc_sched_elem_cmd { 755 __le16 num_elem_req; /* Used by commands */ 756 __le16 num_elem_resp; /* Used by responses */ 757 __le32 reserved; 758 __le32 addr_high; 759 __le32 addr_low; 760}; 761 762struct ice_aqc_txsched_move_grp_info_hdr { 763 __le32 src_parent_teid; 764 __le32 dest_parent_teid; 765 __le16 num_elems; 766 u8 mode; 767#define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0 768#define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1 769#define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2 770 u8 reserved; 771}; 772 773struct ice_aqc_move_elem { 774 struct ice_aqc_txsched_move_grp_info_hdr hdr; 775 __le32 teid[]; 776}; 777 778struct ice_aqc_elem_info_bw { 779 __le16 bw_profile_idx; 780 __le16 bw_alloc; 781}; 782 783struct ice_aqc_txsched_elem { 784 u8 elem_type; /* Special field, reserved for some aq calls */ 785#define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 786#define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 787#define ICE_AQC_ELEM_TYPE_TC 0x2 788#define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 789#define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 790#define ICE_AQC_ELEM_TYPE_LEAF 0x5 791#define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 792 u8 valid_sections; 793#define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 794#define ICE_AQC_ELEM_VALID_CIR BIT(1) 795#define ICE_AQC_ELEM_VALID_EIR BIT(2) 796#define ICE_AQC_ELEM_VALID_SHARED BIT(3) 797 u8 generic; 798#define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 799#define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 800#define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1) 801#define ICE_AQC_ELEM_GENERIC_SP_S 0x4 802#define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4) 803#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 804#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 805 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 806 u8 flags; /* Special field, reserved for some aq calls */ 807#define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 808 struct ice_aqc_elem_info_bw cir_bw; 809 struct ice_aqc_elem_info_bw eir_bw; 810 __le16 srl_id; 811 __le16 reserved2; 812}; 813 814struct ice_aqc_txsched_elem_data { 815 __le32 parent_teid; 816 __le32 node_teid; 817 struct ice_aqc_txsched_elem data; 818}; 819 820struct ice_aqc_txsched_topo_grp_info_hdr { 821 __le32 parent_teid; 822 __le16 num_elems; 823 __le16 reserved2; 824}; 825 826struct ice_aqc_add_elem { 827 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 828 struct ice_aqc_txsched_elem_data generic[]; 829}; 830 831struct ice_aqc_get_topo_elem { 832 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 833 struct ice_aqc_txsched_elem_data 834 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 835}; 836 837struct ice_aqc_delete_elem { 838 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 839 __le32 teid[]; 840}; 841 842/* Query Port ETS (indirect 0x040E) 843 * 844 * This indirect command is used to query port TC node configuration. 845 */ 846struct ice_aqc_query_port_ets { 847 __le32 port_teid; 848 __le32 reserved; 849 __le32 addr_high; 850 __le32 addr_low; 851}; 852 853struct ice_aqc_port_ets_elem { 854 u8 tc_valid_bits; 855 u8 reserved[3]; 856 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 857 __le32 up2tc; 858 u8 tc_bw_share[8]; 859 __le32 port_eir_prof_id; 860 __le32 port_cir_prof_id; 861 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 862 __le32 tc_node_prio; 863#define ICE_TC_NODE_PRIO_S 0x4 864 u8 reserved1[4]; 865 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 866}; 867 868/* Rate limiting profile for 869 * Add RL profile (indirect 0x0410) 870 * Query RL profile (indirect 0x0411) 871 * Remove RL profile (indirect 0x0415) 872 * These indirect commands acts on single or multiple 873 * RL profiles with specified data. 874 */ 875struct ice_aqc_rl_profile { 876 __le16 num_profiles; 877 __le16 num_processed; /* Only for response. Reserved in Command. */ 878 u8 reserved[4]; 879 __le32 addr_high; 880 __le32 addr_low; 881}; 882 883struct ice_aqc_rl_profile_elem { 884 u8 level; 885 u8 flags; 886#define ICE_AQC_RL_PROFILE_TYPE_S 0x0 887#define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 888#define ICE_AQC_RL_PROFILE_TYPE_CIR 0 889#define ICE_AQC_RL_PROFILE_TYPE_EIR 1 890#define ICE_AQC_RL_PROFILE_TYPE_SRL 2 891/* The following flag is used for Query RL Profile Data */ 892#define ICE_AQC_RL_PROFILE_INVAL_S 0x7 893#define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 894 895 __le16 profile_id; 896 __le16 max_burst_size; 897 __le16 rl_multiply; 898 __le16 wake_up_calc; 899 __le16 rl_encode; 900}; 901 902/* Query Scheduler Resource Allocation (indirect 0x0412) 903 * This indirect command retrieves the scheduler resources allocated by 904 * EMP Firmware to the given PF. 905 */ 906struct ice_aqc_query_txsched_res { 907 u8 reserved[8]; 908 __le32 addr_high; 909 __le32 addr_low; 910}; 911 912struct ice_aqc_generic_sched_props { 913 __le16 phys_levels; 914 __le16 logical_levels; 915 u8 flattening_bitmap; 916 u8 max_device_cgds; 917 u8 max_pf_cgds; 918 u8 rsvd0; 919 __le16 rdma_qsets; 920 u8 rsvd1[22]; 921}; 922 923struct ice_aqc_layer_props { 924 u8 logical_layer; 925 u8 chunk_size; 926 __le16 max_device_nodes; 927 __le16 max_pf_nodes; 928 u8 rsvd0[4]; 929 __le16 max_sibl_grp_sz; 930 __le16 max_cir_rl_profiles; 931 __le16 max_eir_rl_profiles; 932 __le16 max_srl_profiles; 933 u8 rsvd1[14]; 934}; 935 936struct ice_aqc_query_txsched_res_resp { 937 struct ice_aqc_generic_sched_props sched_props; 938 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 939}; 940 941/* Get PHY capabilities (indirect 0x0600) */ 942struct ice_aqc_get_phy_caps { 943 u8 lport_num; 944 u8 reserved; 945 __le16 param0; 946 /* 18.0 - Report qualified modules */ 947#define ICE_AQC_GET_PHY_RQM BIT(0) 948 /* 18.1 - 18.3 : Report mode 949 * 000b - Report NVM capabilities 950 * 001b - Report topology capabilities 951 * 010b - Report SW configured 952 * 100b - Report default capabilities 953 */ 954#define ICE_AQC_REPORT_MODE_S 1 955#define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 956#define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 957#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 958#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 959#define ICE_AQC_REPORT_DFLT_CFG BIT(3) 960 __le32 reserved1; 961 __le32 addr_high; 962 __le32 addr_low; 963}; 964 965/* This is #define of PHY type (Extended): 966 * The first set of defines is for phy_type_low. 967 */ 968#define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 969#define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 970#define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 971#define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 972#define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 973#define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 974#define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 975#define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 976#define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 977#define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 978#define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 979#define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 980#define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 981#define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 982#define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 983#define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 984#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 985#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 986#define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 987#define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 988#define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 989#define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 990#define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 991#define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 992#define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 993#define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 994#define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 995#define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 996#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 997#define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 998#define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 999#define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1000#define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1001#define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1002#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1003#define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1004#define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1005#define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1006#define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1007#define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1008#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1009#define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1010#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1011#define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1012#define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1013#define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1014#define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1015#define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1016#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1017#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1018#define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1019#define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1020#define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1021#define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1022#define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1023#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1024#define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1025#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1026#define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1027#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1028#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1029#define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1030#define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1031#define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1032#define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1033/* The second set of defines is for phy_type_high. */ 1034#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1035#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1036#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1037#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1038#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1039#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) 1040#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) 1041#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) 1042#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) 1043#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) 1044#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) 1045#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) 1046#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) 1047#define ICE_PHY_TYPE_HIGH_MAX_INDEX 12 1048 1049struct ice_aqc_get_phy_caps_data { 1050 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1051 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1052 u8 caps; 1053#define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1054#define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1055#define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1056#define ICE_AQC_PHY_EN_LINK BIT(3) 1057#define ICE_AQC_PHY_AN_MODE BIT(4) 1058#define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 1059#define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1060#define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 1061 u8 low_power_ctrl_an; 1062#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1063#define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1064#define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1065#define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1066 __le16 eee_cap; 1067#define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1068#define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1069#define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1070#define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1071#define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1072#define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1073#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1074 __le16 eeer_value; 1075 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1076 u8 phy_fw_ver[8]; 1077 u8 link_fec_options; 1078#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1079#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1080#define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1081#define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1082#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1083#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1084#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1085#define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1086 u8 module_compliance_enforcement; 1087#define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1088 u8 extended_compliance_code; 1089#define ICE_MODULE_TYPE_TOTAL_BYTE 3 1090 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1091#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1092#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1093#define ICE_AQC_MOD_TYPE_IDENT 1 1094#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1095#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1096#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1097#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1098#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1099#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1100#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1101#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1102 u8 qualified_module_count; 1103 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1104#define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1105 struct { 1106 u8 v_oui[3]; 1107 u8 rsvd3; 1108 u8 v_part[16]; 1109 __le32 v_rev; 1110 __le64 rsvd4; 1111 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1112}; 1113 1114/* Set PHY capabilities (direct 0x0601) 1115 * NOTE: This command must be followed by setup link and restart auto-neg 1116 */ 1117struct ice_aqc_set_phy_cfg { 1118 u8 lport_num; 1119 u8 reserved[7]; 1120 __le32 addr_high; 1121 __le32 addr_low; 1122}; 1123 1124/* Set PHY config command data structure */ 1125struct ice_aqc_set_phy_cfg_data { 1126 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1127 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1128 u8 caps; 1129#define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1130#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1131#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1132#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1133#define ICE_AQ_PHY_ENA_LINK BIT(3) 1134#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1135#define ICE_AQ_PHY_ENA_LESM BIT(6) 1136#define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1137 u8 low_power_ctrl_an; 1138 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1139 __le16 eeer_value; 1140 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1141 u8 module_compliance_enforcement; 1142}; 1143 1144/* Set MAC Config command data structure (direct 0x0603) */ 1145struct ice_aqc_set_mac_cfg { 1146 __le16 max_frame_size; 1147 u8 params; 1148#define ICE_AQ_SET_MAC_PACE_S 3 1149#define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1150#define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1151#define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1152#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1153 u8 tx_tmr_priority; 1154 __le16 tx_tmr_value; 1155 __le16 fc_refresh_threshold; 1156 u8 drop_opts; 1157#define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1158#define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1159#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1160 u8 reserved[7]; 1161}; 1162 1163/* Restart AN command data structure (direct 0x0605) 1164 * Also used for response, with only the lport_num field present. 1165 */ 1166struct ice_aqc_restart_an { 1167 u8 lport_num; 1168 u8 reserved; 1169 u8 cmd_flags; 1170#define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1171#define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1172 u8 reserved2[13]; 1173}; 1174 1175/* Get link status (indirect 0x0607), also used for Link Status Event */ 1176struct ice_aqc_get_link_status { 1177 u8 lport_num; 1178 u8 reserved; 1179 __le16 cmd_flags; 1180#define ICE_AQ_LSE_M 0x3 1181#define ICE_AQ_LSE_NOP 0x0 1182#define ICE_AQ_LSE_DIS 0x2 1183#define ICE_AQ_LSE_ENA 0x3 1184 /* only response uses this flag */ 1185#define ICE_AQ_LSE_IS_ENABLED 0x1 1186 __le32 reserved2; 1187 __le32 addr_high; 1188 __le32 addr_low; 1189}; 1190 1191/* Get link status response data structure, also used for Link Status Event */ 1192struct ice_aqc_get_link_status_data { 1193 u8 topo_media_conflict; 1194#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1195#define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1196#define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1197#define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1198#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1199#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1200#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1201 u8 link_cfg_err; 1202#define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1203#define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1204#define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1205 u8 link_info; 1206#define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1207#define ICE_AQ_LINK_FAULT BIT(1) 1208#define ICE_AQ_LINK_FAULT_TX BIT(2) 1209#define ICE_AQ_LINK_FAULT_RX BIT(3) 1210#define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1211#define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1212#define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1213#define ICE_AQ_SIGNAL_DETECT BIT(7) 1214 u8 an_info; 1215#define ICE_AQ_AN_COMPLETED BIT(0) 1216#define ICE_AQ_LP_AN_ABILITY BIT(1) 1217#define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1218#define ICE_AQ_FEC_EN BIT(3) 1219#define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1220#define ICE_AQ_LINK_PAUSE_TX BIT(5) 1221#define ICE_AQ_LINK_PAUSE_RX BIT(6) 1222#define ICE_AQ_QUALIFIED_MODULE BIT(7) 1223 u8 ext_info; 1224#define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1225#define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1226 /* Port Tx Suspended */ 1227#define ICE_AQ_LINK_TX_S 2 1228#define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1229#define ICE_AQ_LINK_TX_ACTIVE 0 1230#define ICE_AQ_LINK_TX_DRAINED 1 1231#define ICE_AQ_LINK_TX_FLUSHED 3 1232 u8 reserved2; 1233 __le16 max_frame_size; 1234 u8 cfg; 1235#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1236#define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1237#define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1238#define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1239 /* Pacing Config */ 1240#define ICE_AQ_CFG_PACING_S 3 1241#define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1242#define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1243#define ICE_AQ_CFG_PACING_TYPE_AVG 0 1244#define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1245 /* External Device Power Ability */ 1246 u8 power_desc; 1247#define ICE_AQ_PWR_CLASS_M 0x3F 1248#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1249#define ICE_AQ_LINK_PWR_BASET_HIGH 1 1250#define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1251#define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1252#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1253#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1254 __le16 link_speed; 1255#define ICE_AQ_LINK_SPEED_M 0x7FF 1256#define ICE_AQ_LINK_SPEED_10MB BIT(0) 1257#define ICE_AQ_LINK_SPEED_100MB BIT(1) 1258#define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1259#define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1260#define ICE_AQ_LINK_SPEED_5GB BIT(4) 1261#define ICE_AQ_LINK_SPEED_10GB BIT(5) 1262#define ICE_AQ_LINK_SPEED_20GB BIT(6) 1263#define ICE_AQ_LINK_SPEED_25GB BIT(7) 1264#define ICE_AQ_LINK_SPEED_40GB BIT(8) 1265#define ICE_AQ_LINK_SPEED_50GB BIT(9) 1266#define ICE_AQ_LINK_SPEED_100GB BIT(10) 1267#define ICE_AQ_LINK_SPEED_200GB BIT(11) 1268#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1269 /* Aligns next field to 8-byte boundary */ 1270 __le16 reserved3; 1271 u8 ext_fec_status; 1272 /* RS 272 FEC enabled */ 1273#define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) 1274 u8 reserved4; 1275 /* Use values from ICE_PHY_TYPE_LOW_* */ 1276 __le64 phy_type_low; 1277 /* Use values from ICE_PHY_TYPE_HIGH_* */ 1278 __le64 phy_type_high; 1279#define ICE_AQC_LS_DATA_SIZE_V1 \ 1280 offsetofend(struct ice_aqc_get_link_status_data, phy_type_high) 1281 /* Get link status v2 link partner data */ 1282 __le64 lp_phy_type_low; 1283 __le64 lp_phy_type_high; 1284 u8 lp_fec_adv; 1285#define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0) 1286#define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1) 1287#define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2) 1288#define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 1289#define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 1290#define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 1291 u8 lp_fec_req; 1292#define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0) 1293#define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1) 1294#define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2) 1295#define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3) 1296 u8 lp_flowcontrol; 1297#define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0) 1298#define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1) 1299 u8 reserved5[5]; 1300#define ICE_AQC_LS_DATA_SIZE_V2 \ 1301 offsetofend(struct ice_aqc_get_link_status_data, reserved5) 1302} __packed; 1303 1304/* Set event mask command (direct 0x0613) */ 1305struct ice_aqc_set_event_mask { 1306 u8 lport_num; 1307 u8 reserved[7]; 1308 __le16 event_mask; 1309#define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1310#define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1311#define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1312#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1313#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1314#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1315#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1316#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1317#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1318#define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1319 u8 reserved1[6]; 1320}; 1321 1322/* Set MAC Loopback command (direct 0x0620) */ 1323struct ice_aqc_set_mac_lb { 1324 u8 lb_mode; 1325#define ICE_AQ_MAC_LB_EN BIT(0) 1326#define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1327 u8 reserved[15]; 1328}; 1329 1330/* Set PHY recovered clock output (direct 0x0630) */ 1331struct ice_aqc_set_phy_rec_clk_out { 1332 u8 phy_output; 1333 u8 port_num; 1334#define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1335 u8 flags; 1336#define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1337 u8 rsvd; 1338 __le32 freq; 1339 u8 rsvd2[6]; 1340 __le16 node_handle; 1341}; 1342 1343/* Get PHY recovered clock output (direct 0x0631) */ 1344struct ice_aqc_get_phy_rec_clk_out { 1345 u8 phy_output; 1346 u8 port_num; 1347#define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF 1348 u8 flags; 1349#define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0) 1350 u8 rsvd[11]; 1351 __le16 node_handle; 1352}; 1353 1354/* Get sensor reading (direct 0x0632) */ 1355struct ice_aqc_get_sensor_reading { 1356 u8 sensor; 1357 u8 format; 1358 u8 reserved[6]; 1359 __le32 addr_high; 1360 __le32 addr_low; 1361}; 1362 1363/* Get sensor reading response (direct 0x0632) */ 1364struct ice_aqc_get_sensor_reading_resp { 1365 union { 1366 u8 raw[8]; 1367 /* Output data for sensor 0x00, format 0x00 */ 1368 struct _packed { 1369 s8 temp; 1370 u8 temp_warning_threshold; 1371 u8 temp_critical_threshold; 1372 u8 temp_fatal_threshold; 1373 u8 reserved[4]; 1374 } s0f0; 1375 } data; 1376}; 1377 1378/* DNL call command (indirect 0x0682) 1379 * Struct is used for both command and response 1380 */ 1381struct ice_aqc_dnl_call_command { 1382 u8 ctx; /* Used in command, reserved in response */ 1383 u8 reserved; 1384 __le16 activity_id; 1385#define ICE_AQC_ACT_ID_DNL 0x1129 1386 __le32 reserved1; 1387 __le32 addr_high; 1388 __le32 addr_low; 1389}; 1390 1391struct ice_aqc_dnl_equa_param { 1392 __le16 data_in; 1393#define ICE_AQC_RX_EQU_SHIFT 8 1394#define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT) 1395#define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT) 1396#define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT) 1397#define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT) 1398#define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT) 1399#define ICE_AQC_RX_EQU_CTLE_GAINHF (0x20 << ICE_AQC_RX_EQU_SHIFT) 1400#define ICE_AQC_RX_EQU_CTLE_GAINLF (0x21 << ICE_AQC_RX_EQU_SHIFT) 1401#define ICE_AQC_RX_EQU_CTLE_GAINDC (0x22 << ICE_AQC_RX_EQU_SHIFT) 1402#define ICE_AQC_RX_EQU_CTLE_BW (0x23 << ICE_AQC_RX_EQU_SHIFT) 1403#define ICE_AQC_RX_EQU_DFE_GAIN (0x30 << ICE_AQC_RX_EQU_SHIFT) 1404#define ICE_AQC_RX_EQU_DFE_GAIN2 (0x31 << ICE_AQC_RX_EQU_SHIFT) 1405#define ICE_AQC_RX_EQU_DFE_2 (0x32 << ICE_AQC_RX_EQU_SHIFT) 1406#define ICE_AQC_RX_EQU_DFE_3 (0x33 << ICE_AQC_RX_EQU_SHIFT) 1407#define ICE_AQC_RX_EQU_DFE_4 (0x34 << ICE_AQC_RX_EQU_SHIFT) 1408#define ICE_AQC_RX_EQU_DFE_5 (0x35 << ICE_AQC_RX_EQU_SHIFT) 1409#define ICE_AQC_RX_EQU_DFE_6 (0x36 << ICE_AQC_RX_EQU_SHIFT) 1410#define ICE_AQC_RX_EQU_DFE_7 (0x37 << ICE_AQC_RX_EQU_SHIFT) 1411#define ICE_AQC_RX_EQU_DFE_8 (0x38 << ICE_AQC_RX_EQU_SHIFT) 1412#define ICE_AQC_RX_EQU_DFE_9 (0x39 << ICE_AQC_RX_EQU_SHIFT) 1413#define ICE_AQC_RX_EQU_DFE_10 (0x3A << ICE_AQC_RX_EQU_SHIFT) 1414#define ICE_AQC_RX_EQU_DFE_11 (0x3B << ICE_AQC_RX_EQU_SHIFT) 1415#define ICE_AQC_RX_EQU_DFE_12 (0x3C << ICE_AQC_RX_EQU_SHIFT) 1416#define ICE_AQC_TX_EQU_PRE1 0x0 1417#define ICE_AQC_TX_EQU_PRE3 0x3 1418#define ICE_AQC_TX_EQU_ATTEN 0x4 1419#define ICE_AQC_TX_EQU_POST1 0x8 1420#define ICE_AQC_TX_EQU_PRE2 0xC 1421 __le16 op_code_serdes_sel; 1422#define ICE_AQC_OP_CODE_SHIFT 4 1423#define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT) 1424#define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT) 1425 __le32 reserved[3]; 1426}; 1427 1428struct ice_aqc_dnl_equa_respon { 1429 /* Equalization value can be negative */ 1430 int val; 1431 __le32 reserved[3]; 1432}; 1433 1434/* DNL call command/response buffer (indirect 0x0682) */ 1435struct ice_aqc_dnl_call { 1436 union { 1437 struct ice_aqc_dnl_equa_param txrx_equa_reqs; 1438 __le32 stores[4]; 1439 struct ice_aqc_dnl_equa_respon txrx_equa_resp; 1440 } sto; 1441}; 1442 1443struct ice_aqc_link_topo_params { 1444 u8 lport_num; 1445 u8 lport_num_valid; 1446#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1447 u8 node_type_ctx; 1448#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1449#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1450#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1451#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1452#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1453#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1454#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1455#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1456#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1457#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1458#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1459#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 1460#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10 1461#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 11 1462#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1463#define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1464 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1465#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1466#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1467#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1468#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1469#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1470#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1471 u8 index; 1472}; 1473 1474struct ice_aqc_link_topo_addr { 1475 struct ice_aqc_link_topo_params topo_params; 1476 __le16 handle; 1477#define ICE_AQC_LINK_TOPO_HANDLE_S 0 1478#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1479/* Used to decode the handle field */ 1480#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1481#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1482#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1483#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1484/* In case of a Mezzanine type */ 1485#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1486 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1487#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1488#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1489/* In case of a LOM type */ 1490#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1491 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1492}; 1493 1494/* Get Link Topology Handle (direct, 0x06E0) */ 1495struct ice_aqc_get_link_topo { 1496 struct ice_aqc_link_topo_addr addr; 1497 u8 node_part_num; 1498#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1499#define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 1500#define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25 1501#define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30 1502#define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31 1503#define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 1504#define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 1505 u8 rsvd[9]; 1506}; 1507 1508/* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1509struct ice_aqc_i2c { 1510 struct ice_aqc_link_topo_addr topo_addr; 1511 __le16 i2c_addr; 1512 u8 i2c_params; 1513#define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0) 1514#define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1515 1516 u8 rsvd; 1517 __le16 i2c_bus_addr; 1518 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1519}; 1520 1521/* Read I2C Response (direct, 0x06E2) */ 1522struct ice_aqc_read_i2c_resp { 1523 u8 i2c_data[16]; 1524}; 1525 1526/* Set Port Identification LED (direct, 0x06E9) */ 1527struct ice_aqc_set_port_id_led { 1528 u8 lport_num; 1529 u8 lport_num_valid; 1530 u8 ident_mode; 1531#define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1532#define ICE_AQC_PORT_IDENT_LED_ORIG 0 1533 u8 rsvd[13]; 1534}; 1535 1536/* Get Port Options (indirect, 0x06EA) */ 1537struct ice_aqc_get_port_options { 1538 u8 lport_num; 1539 u8 lport_num_valid; 1540 u8 port_options_count; 1541#define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0) 1542#define ICE_AQC_PORT_OPT_MAX 16 1543 1544 u8 innermost_phy_index; 1545 u8 port_options; 1546#define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0) 1547#define ICE_AQC_PORT_OPT_VALID BIT(7) 1548 1549 u8 pending_port_option_status; 1550#define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0) 1551#define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1552 1553 u8 rsvd[2]; 1554 __le32 addr_high; 1555 __le32 addr_low; 1556}; 1557 1558struct ice_aqc_get_port_options_elem { 1559 u8 pmd; 1560#define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0) 1561 1562 u8 max_lane_speed; 1563#define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0) 1564#define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1565#define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1566#define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1567#define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1568#define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1569#define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1570#define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1571#define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1572#define ICE_AQC_PORT_OPT_MAX_LANE_200G 8 1573#define ICE_AQC_PORT_OPT_MAX_LANE_40G 9 1574 1575 u8 global_scid[2]; 1576 u8 phy_scid[2]; 1577 u8 pf2port_cid[2]; 1578}; 1579 1580/* Set Port Option (direct, 0x06EB) */ 1581struct ice_aqc_set_port_option { 1582 u8 lport_num; 1583 u8 lport_num_valid; 1584 u8 selected_port_option; 1585 u8 rsvd[13]; 1586}; 1587 1588/* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1589struct ice_aqc_gpio { 1590 __le16 gpio_ctrl_handle; 1591#define ICE_AQC_GPIO_HANDLE_S 0 1592#define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1593 u8 gpio_num; 1594 u8 gpio_val; 1595 u8 rsvd[12]; 1596}; 1597 1598/* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1599struct ice_aqc_sff_eeprom { 1600 u8 lport_num; 1601 u8 lport_num_valid; 1602#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1603 __le16 i2c_bus_addr; 1604#define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1605#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1606#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1607#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1608#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1609#define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1610#define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1611#define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1612#define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1613#define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1614#define ICE_AQC_SFF_IS_WRITE BIT(15) 1615 __le16 i2c_mem_addr; 1616 __le16 eeprom_page; 1617#define ICE_AQC_SFF_EEPROM_BANK_S 0 1618#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1619#define ICE_AQC_SFF_EEPROM_PAGE_S 8 1620#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1621 __le32 addr_high; 1622 __le32 addr_low; 1623}; 1624 1625/* NVM Read command (indirect 0x0701) 1626 * NVM Erase commands (direct 0x0702) 1627 * NVM Update commands (indirect 0x0703) 1628 */ 1629struct ice_aqc_nvm { 1630#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1631 __le16 offset_low; 1632 u8 offset_high; 1633 u8 cmd_flags; 1634#define ICE_AQC_NVM_LAST_CMD BIT(0) 1635#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1636#define ICE_AQC_NVM_PRESERVATION_S 1 1637#define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1638#define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1639#define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1640#define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1641#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1642#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1643#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1644#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1645#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1646#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1647#define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1648#define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1649#define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */ 1650#define ICE_AQC_NVM_POR_FLAG 0 1651#define ICE_AQC_NVM_PERST_FLAG 1 1652#define ICE_AQC_NVM_EMPR_FLAG 2 1653#define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1654 /* For Write Activate, several flags are sent as part of a separate 1655 * flags2 field using a separate byte. For simplicity of the software 1656 * interface, we pass the flags as a 16 bit value so these flags are 1657 * all offset by 8 bits 1658 */ 1659#define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 1660 __le16 module_typeid; 1661 __le16 length; 1662#define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1663 __le32 addr_high; 1664 __le32 addr_low; 1665}; 1666 1667#define ICE_AQC_NVM_START_POINT 0 1668#define ICE_AQC_NVM_SECTOR_UNIT 4096 1669#define ICE_AQC_NVM_SDP_AC_PTR_OFFSET 0xD8 1670#define ICE_AQC_NVM_SDP_AC_PTR_M GENMASK(14, 0) 1671#define ICE_AQC_NVM_SDP_AC_PTR_INVAL 0x7FFF 1672#define ICE_AQC_NVM_SDP_AC_PTR_TYPE_M BIT(15) 1673#define ICE_AQC_NVM_SDP_AC_SDP_NUM_M GENMASK(2, 0) 1674#define ICE_AQC_NVM_SDP_AC_DIR_M BIT(3) 1675#define ICE_AQC_NVM_SDP_AC_PIN_M GENMASK(15, 6) 1676#define ICE_AQC_NVM_SDP_AC_MAX_SIZE 7 1677 1678#define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B 1679 1680struct ice_aqc_nvm_tx_topo_user_sel { 1681 __le16 length; 1682 u8 data; 1683#define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4) 1684 u8 reserved; 1685}; 1686 1687/* NVM Checksum Command (direct, 0x0706) */ 1688struct ice_aqc_nvm_checksum { 1689 u8 flags; 1690#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1691#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1692 u8 rsvd; 1693 __le16 checksum; /* Used only by response */ 1694#define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1695 u8 rsvd2[12]; 1696}; 1697 1698/* Used for NVM Set Package Data command - 0x070A */ 1699struct ice_aqc_nvm_pkg_data { 1700 u8 reserved[3]; 1701 u8 cmd_flags; 1702#define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1703#define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1704 1705 u32 reserved1; 1706 __le32 addr_high; 1707 __le32 addr_low; 1708}; 1709 1710/* Used for Pass Component Table command - 0x070B */ 1711struct ice_aqc_nvm_pass_comp_tbl { 1712 u8 component_response; /* Response only */ 1713#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1714#define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1715#define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1716#define ICE_AQ_NVM_PASS_COMP_PARTIAL_CHECK 0x3 1717 u8 component_response_code; /* Response only */ 1718#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1719#define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1720#define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1721#define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1722#define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1723#define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1724#define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1725#define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1726#define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1727#define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1728#define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1729 u8 reserved; 1730 u8 transfer_flag; 1731#define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1732#define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1733#define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1734#define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1735 __le32 reserved1; 1736 __le32 addr_high; 1737 __le32 addr_low; 1738}; 1739 1740struct ice_aqc_nvm_comp_tbl { 1741 __le16 comp_class; 1742#define NVM_COMP_CLASS_ALL_FW 0x000A 1743 1744 __le16 comp_id; 1745#define NVM_COMP_ID_OROM 0x5 1746#define NVM_COMP_ID_NVM 0x6 1747#define NVM_COMP_ID_NETLIST 0x8 1748 1749 u8 comp_class_idx; 1750#define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1751 1752 __le32 comp_cmp_stamp; 1753 u8 cvs_type; 1754#define NVM_CVS_TYPE_ASCII 0x1 1755 1756 u8 cvs_len; 1757 u8 cvs[]; /* Component Version String */ 1758} __packed; 1759 1760/* Send to PF command (indirect 0x0801) ID is only used by PF 1761 * 1762 * Send to VF command (indirect 0x0802) ID is only used by PF 1763 * 1764 */ 1765struct ice_aqc_pf_vf_msg { 1766 __le32 id; 1767 u32 reserved; 1768 __le32 addr_high; 1769 __le32 addr_low; 1770}; 1771 1772/* Get LLDP MIB (indirect 0x0A00) 1773 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1774 * as the format is the same. 1775 */ 1776struct ice_aqc_lldp_get_mib { 1777 u8 type; 1778#define ICE_AQ_LLDP_MIB_TYPE_S 0 1779#define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1780#define ICE_AQ_LLDP_MIB_LOCAL 0 1781#define ICE_AQ_LLDP_MIB_REMOTE 1 1782#define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1783#define ICE_AQ_LLDP_BRID_TYPE_S 2 1784#define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1785#define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1786#define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1787/* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1788#define ICE_AQ_LLDP_TX_S 0x4 1789#define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1790#define ICE_AQ_LLDP_TX_ACTIVE 0 1791#define ICE_AQ_LLDP_TX_SUSPENDED 1 1792#define ICE_AQ_LLDP_TX_FLUSHED 3 1793/* DCBX mode */ 1794#define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6) 1795#define ICE_AQ_LLDP_DCBX_NA 0 1796#define ICE_AQ_LLDP_DCBX_CEE 1 1797#define ICE_AQ_LLDP_DCBX_IEEE 2 1798 1799 u8 state; 1800#define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0) 1801#define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 1802#define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 1803 1804/* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1805 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1806 * Get LLDP MIB (0x0A00) response only. 1807 */ 1808 __le16 local_len; 1809 __le16 remote_len; 1810 u8 reserved[2]; 1811 __le32 addr_high; 1812 __le32 addr_low; 1813}; 1814 1815/* Configure LLDP MIB Change Event (direct 0x0A01) */ 1816/* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1817struct ice_aqc_lldp_set_mib_change { 1818 u8 command; 1819#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1820#define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1821#define ICE_AQ_LLDP_MIB_PENDING_M BIT(1) 1822#define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 1823#define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 1824 u8 reserved[15]; 1825}; 1826 1827/* Stop LLDP (direct 0x0A05) */ 1828struct ice_aqc_lldp_stop { 1829 u8 command; 1830#define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1831#define ICE_AQ_LLDP_AGENT_STOP 0x0 1832#define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1833#define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1834 u8 reserved[15]; 1835}; 1836 1837/* Start LLDP (direct 0x0A06) */ 1838struct ice_aqc_lldp_start { 1839 u8 command; 1840#define ICE_AQ_LLDP_AGENT_START BIT(0) 1841#define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1842 u8 reserved[15]; 1843}; 1844 1845/* Get CEE DCBX Oper Config (0x0A07) 1846 * The command uses the generic descriptor struct and 1847 * returns the struct below as an indirect response. 1848 */ 1849struct ice_aqc_get_cee_dcb_cfg_resp { 1850 u8 oper_num_tc; 1851 u8 oper_prio_tc[4]; 1852 u8 oper_tc_bw[8]; 1853 u8 oper_pfc_en; 1854 __le16 oper_app_prio; 1855#define ICE_AQC_CEE_APP_FCOE_S 0 1856#define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1857#define ICE_AQC_CEE_APP_ISCSI_S 3 1858#define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1859#define ICE_AQC_CEE_APP_FIP_S 8 1860#define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1861 __le32 tlv_status; 1862#define ICE_AQC_CEE_PG_STATUS_S 0 1863#define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1864#define ICE_AQC_CEE_PFC_STATUS_S 3 1865#define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1866#define ICE_AQC_CEE_FCOE_STATUS_S 8 1867#define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1868#define ICE_AQC_CEE_ISCSI_STATUS_S 11 1869#define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1870#define ICE_AQC_CEE_FIP_STATUS_S 16 1871#define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1872 u8 reserved[12]; 1873}; 1874 1875/* Set Local LLDP MIB (indirect 0x0A08) 1876 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1877 */ 1878struct ice_aqc_lldp_set_local_mib { 1879 u8 type; 1880#define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1881#define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1882#define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1883#define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1884#define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1885 u8 reserved0; 1886 __le16 length; 1887 u8 reserved1[4]; 1888 __le32 addr_high; 1889 __le32 addr_low; 1890}; 1891 1892/* Stop/Start LLDP Agent (direct 0x0A09) 1893 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1894 * The same structure is used for the response, with the command field 1895 * being used as the status field. 1896 */ 1897struct ice_aqc_lldp_stop_start_specific_agent { 1898 u8 command; 1899#define ICE_AQC_START_STOP_AGENT_M BIT(0) 1900#define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1901#define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1902 u8 reserved[15]; 1903}; 1904 1905/* LLDP Filter Control (direct 0x0A0A) */ 1906struct ice_aqc_lldp_filter_ctrl { 1907 u8 cmd_flags; 1908#define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1909#define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1910 u8 reserved1; 1911 __le16 vsi_num; 1912 u8 reserved2[12]; 1913}; 1914 1915#define ICE_AQC_RSS_VSI_VALID BIT(15) 1916 1917/* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1918struct ice_aqc_get_set_rss_key { 1919 __le16 vsi_id; 1920 u8 reserved[6]; 1921 __le32 addr_high; 1922 __le32 addr_low; 1923}; 1924 1925#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1926#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1927#define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1928 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1929 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1930 1931struct ice_aqc_get_set_rss_keys { 1932 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1933 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1934}; 1935 1936enum ice_lut_type { 1937 ICE_LUT_VSI = 0, 1938 ICE_LUT_PF = 1, 1939 ICE_LUT_GLOBAL = 2, 1940}; 1941 1942enum ice_lut_size { 1943 ICE_LUT_VSI_SIZE = 64, 1944 ICE_LUT_GLOBAL_SIZE = 512, 1945 ICE_LUT_PF_SIZE = 2048, 1946}; 1947 1948/* enum ice_aqc_lut_flags combines constants used to fill 1949 * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID, 1950 * LUT size and LUT type, last of which does not need neither shift nor mask. 1951 */ 1952enum ice_aqc_lut_flags { 1953 ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */ 1954 ICE_AQC_LUT_SIZE_512 = BIT(2), 1955 ICE_AQC_LUT_SIZE_2K = BIT(3), 1956 1957 ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4), 1958}; 1959 1960/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1961struct ice_aqc_get_set_rss_lut { 1962 __le16 vsi_id; 1963 __le16 flags; 1964 __le32 reserved; 1965 __le32 addr_high; 1966 __le32 addr_low; 1967}; 1968 1969/* Sideband Control Interface Commands */ 1970/* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 1971struct ice_aqc_neigh_dev_req { 1972 __le16 sb_data_len; 1973 u8 reserved[6]; 1974 __le32 addr_high; 1975 __le32 addr_low; 1976}; 1977 1978/* Add Tx LAN Queues (indirect 0x0C30) */ 1979struct ice_aqc_add_txqs { 1980 u8 num_qgrps; 1981 u8 reserved[3]; 1982 __le32 reserved1; 1983 __le32 addr_high; 1984 __le32 addr_low; 1985}; 1986 1987/* This is the descriptor of each queue entry for the Add Tx LAN Queues 1988 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1989 */ 1990struct ice_aqc_add_txqs_perq { 1991 __le16 txq_id; 1992 u8 rsvd[2]; 1993 __le32 q_teid; 1994 ice_txq_ctx_buf_t txq_ctx; 1995 u8 rsvd2[2]; 1996 struct ice_aqc_txsched_elem info; 1997} __packed; 1998 1999/* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2000 * is an array of the following structs. Please note that the length of 2001 * each struct ice_aqc_add_tx_qgrp is variable due 2002 * to the variable number of queues in each group! 2003 */ 2004struct ice_aqc_add_tx_qgrp { 2005 __le32 parent_teid; 2006 u8 num_txqs; 2007 u8 rsvd[3]; 2008 struct ice_aqc_add_txqs_perq txqs[]; 2009}; 2010 2011/* Disable Tx LAN Queues (indirect 0x0C31) */ 2012struct ice_aqc_dis_txqs { 2013 u8 cmd_type; 2014#define ICE_AQC_Q_DIS_CMD_S 0 2015#define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2016#define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2017#define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2018#define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2019#define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2020#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2021#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2022 u8 num_entries; 2023 __le16 vmvf_and_timeout; 2024#define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2025#define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2026#define ICE_AQC_Q_DIS_TIMEOUT_S 10 2027#define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2028 __le32 blocked_cgds; 2029 __le32 addr_high; 2030 __le32 addr_low; 2031}; 2032 2033/* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2034 * contains the following structures, arrayed one after the 2035 * other. 2036 * Note: Since the q_id is 16 bits wide, if the 2037 * number of queues is even, then 2 bytes of alignment MUST be 2038 * added before the start of the next group, to allow correct 2039 * alignment of the parent_teid field. 2040 */ 2041struct ice_aqc_dis_txq_item { 2042 __le32 parent_teid; 2043 u8 num_qs; 2044 u8 rsvd; 2045 /* The length of the q_id array varies according to num_qs */ 2046#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2047#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2048 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2049#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2050 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2051 __le16 q_id[]; 2052} __packed; 2053 2054/* Move/Reconfigure Tx queue (indirect 0x0C32) */ 2055struct ice_aqc_cfg_txqs { 2056 u8 cmd_type; 2057#define ICE_AQC_Q_CFG_MOVE_NODE 0x1 2058#define ICE_AQC_Q_CFG_TC_CHNG 0x2 2059#define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x3 2060#define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2) 2061#define ICE_AQC_Q_CFG_FLUSH BIT(3) 2062 u8 num_qs; 2063 u8 port_num_chng; 2064#define ICE_AQC_Q_CFG_SRC_PRT_M 0x7 2065#define ICE_AQC_Q_CFG_DST_PRT_S 3 2066#define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S) 2067#define ICE_AQC_Q_CFG_MODE_M GENMASK(7, 6) 2068#define ICE_AQC_Q_CFG_MODE_SAME_PF 0x0 2069#define ICE_AQC_Q_CFG_MODE_GIVE_OWN 0x1 2070#define ICE_AQC_Q_CFG_MODE_KEEP_OWN 0x2 2071 u8 time_out; 2072#define ICE_AQC_Q_CFG_TIMEOUT_S 2 2073#define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S) 2074 __le32 blocked_cgds; 2075 __le32 addr_high; 2076 __le32 addr_low; 2077}; 2078 2079/* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2080struct ice_aqc_cfg_txq_perq { 2081 __le16 q_handle; 2082 u8 tc; 2083 u8 rsvd; 2084 __le32 q_teid; 2085}; 2086 2087/* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 2088struct ice_aqc_cfg_txqs_buf { 2089 __le32 src_parent_teid; 2090 __le32 dst_parent_teid; 2091 struct ice_aqc_cfg_txq_perq queue_info[]; 2092}; 2093 2094/* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2095struct ice_aqc_add_rdma_qset { 2096 u8 num_qset_grps; 2097 u8 reserved[7]; 2098 __le32 addr_high; 2099 __le32 addr_low; 2100}; 2101 2102/* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 2103 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2104 */ 2105struct ice_aqc_add_tx_rdma_qset_entry { 2106 __le16 tx_qset_id; 2107 u8 rsvd[2]; 2108 __le32 qset_teid; 2109 struct ice_aqc_txsched_elem info; 2110}; 2111 2112/* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2113 * is an array of the following structs. Please note that the length of 2114 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2115 * number of queues in each group! 2116 */ 2117struct ice_aqc_add_rdma_qset_data { 2118 __le32 parent_teid; 2119 __le16 num_qsets; 2120 u8 rsvd[2]; 2121 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 2122}; 2123 2124/* Set Tx Time LAN Queue (indirect 0x0C35) */ 2125struct ice_aqc_set_txtimeqs { 2126 __le16 q_id; 2127 __le16 q_amount; 2128 u8 reserved[4]; 2129 __le32 addr_high; 2130 __le32 addr_low; 2131}; 2132 2133/* This is the descriptor of each queue entry for the Set Tx Time Queue 2134 * command (0x0C35). Only used within struct ice_aqc_set_txtime_qgrp. 2135 */ 2136struct ice_aqc_set_txtimeqs_perq { 2137 u8 reserved[4]; 2138 ice_txtime_ctx_buf_t txtime_ctx; 2139 u8 reserved1[3]; 2140}; 2141 2142/* The format of the command buffer for Set Tx Time Queue (0x0C35) 2143 * is an array of the following structs. Please note that the length of 2144 * each struct ice_aqc_set_txtime_qgrp is variable due to the variable 2145 * number of queues in each group! 2146 */ 2147struct ice_aqc_set_txtime_qgrp { 2148 u8 reserved[8]; 2149 struct ice_aqc_set_txtimeqs_perq txtimeqs[]; 2150}; 2151 2152/* Download Package (indirect 0x0C40) */ 2153/* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2154struct ice_aqc_download_pkg { 2155 u8 flags; 2156#define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2157 u8 reserved[3]; 2158 __le32 reserved1; 2159 __le32 addr_high; 2160 __le32 addr_low; 2161}; 2162 2163struct ice_aqc_download_pkg_resp { 2164 __le32 error_offset; 2165 __le32 error_info; 2166 __le32 addr_high; 2167 __le32 addr_low; 2168}; 2169 2170/* Get Package Info List (indirect 0x0C43) */ 2171struct ice_aqc_get_pkg_info_list { 2172 __le32 reserved1; 2173 __le32 reserved2; 2174 __le32 addr_high; 2175 __le32 addr_low; 2176}; 2177 2178/* Version format for packages */ 2179struct ice_pkg_ver { 2180 u8 major; 2181 u8 minor; 2182 u8 update; 2183 u8 draft; 2184}; 2185 2186#define ICE_PKG_NAME_SIZE 32 2187#define ICE_SEG_ID_SIZE 28 2188#define ICE_SEG_NAME_SIZE 28 2189 2190struct ice_aqc_get_pkg_info { 2191 struct ice_pkg_ver ver; 2192 char name[ICE_SEG_NAME_SIZE]; 2193 __le32 track_id; 2194 u8 is_in_nvm; 2195 u8 is_active; 2196 u8 is_active_at_boot; 2197 u8 is_modified; 2198}; 2199 2200/* Get Package Info List response buffer format (0x0C43) */ 2201struct ice_aqc_get_pkg_info_resp { 2202 __le32 count; 2203 struct ice_aqc_get_pkg_info pkg_info[]; 2204}; 2205 2206#define ICE_CGU_INPUT_PHASE_OFFSET_BYTES 6 2207 2208struct ice_cgu_input_measure { 2209 u8 phase_offset[ICE_CGU_INPUT_PHASE_OFFSET_BYTES]; 2210 __le32 freq; 2211} __packed __aligned(sizeof(__le16)); 2212 2213#define ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M ICE_M(0xf, 0) 2214 2215/* Get CGU input measure command response data structure (indirect 0x0C59) */ 2216struct ice_aqc_get_cgu_input_measure { 2217 u8 dpll_idx_opt; 2218 u8 length; 2219 u8 rsvd[6]; 2220}; 2221 2222#define ICE_AQC_GET_CGU_MAX_PHASE_ADJ GENMASK(30, 0) 2223 2224/* Get CGU abilities command response data structure (indirect 0x0C61) */ 2225struct ice_aqc_get_cgu_abilities { 2226 u8 num_inputs; 2227 u8 num_outputs; 2228 u8 pps_dpll_idx; 2229 u8 eec_dpll_idx; 2230 __le32 max_in_freq; 2231 __le32 max_in_phase_adj; 2232 __le32 max_out_freq; 2233 __le32 max_out_phase_adj; 2234 u8 cgu_part_num; 2235 u8 rsvd[3]; 2236}; 2237 2238#define ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN BIT(7) 2239 2240/* Set CGU input config (direct 0x0C62) */ 2241struct ice_aqc_set_cgu_input_config { 2242 u8 input_idx; 2243 u8 flags1; 2244#define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6) 2245#define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7) 2246 u8 flags2; 2247#define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2248#define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2249 u8 rsvd; 2250 __le32 freq; 2251 __le32 phase_delay; 2252 u8 rsvd2[2]; 2253 __le16 node_handle; 2254}; 2255 2256/* Get CGU input config response descriptor structure (direct 0x0C63) */ 2257struct ice_aqc_get_cgu_input_config { 2258 u8 input_idx; 2259 u8 status; 2260#define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0) 2261#define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1) 2262#define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2) 2263#define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3) 2264#define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4) 2265#define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6) 2266#define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7) 2267 u8 type; 2268#define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0) 2269#define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4) 2270#define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5) 2271#define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6) 2272 u8 flags1; 2273#define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0) 2274#define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2) 2275#define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3) 2276#define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7) 2277 __le32 freq; 2278 __le32 phase_delay; 2279 u8 flags2; 2280#define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) 2281#define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) 2282 u8 rsvd[1]; 2283 __le16 node_handle; 2284}; 2285 2286/* Set CGU output config (direct 0x0C64) */ 2287struct ice_aqc_set_cgu_output_config { 2288 u8 output_idx; 2289 u8 flags; 2290#define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0) 2291#define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2292#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2) 2293#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3) 2294#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4) 2295 u8 src_sel; 2296#define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0) 2297 u8 rsvd; 2298 __le32 freq; 2299 __le32 phase_delay; 2300 u8 rsvd2[2]; 2301 __le16 node_handle; 2302}; 2303 2304/* Get CGU output config (direct 0x0C65) */ 2305struct ice_aqc_get_cgu_output_config { 2306 u8 output_idx; 2307 u8 flags; 2308#define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0) 2309#define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1) 2310#define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2) 2311 u8 src_sel; 2312#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0 2313#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \ 2314 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT) 2315#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5 2316#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \ 2317 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT) 2318 u8 rsvd; 2319 __le32 freq; 2320 __le32 src_freq; 2321 u8 rsvd2[2]; 2322 __le16 node_handle; 2323}; 2324 2325/* Get CGU DPLL status (direct 0x0C66) */ 2326struct ice_aqc_get_cgu_dpll_status { 2327 u8 dpll_num; 2328 u8 ref_state; 2329#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0) 2330#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1) 2331#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2) 2332#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3) 2333#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4) 2334#define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5) 2335#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6) 2336 u8 dpll_state; 2337#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0) 2338#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1) 2339#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2) 2340#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5) 2341#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7) 2342 u8 config; 2343#define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2344#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2345#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \ 2346 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2347#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2348#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2349 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT) 2350 __le32 phase_offset_h; 2351 __le32 phase_offset_l; 2352 u8 eec_mode; 2353#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA 2354#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB 2355#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF 2356 u8 rsvd[1]; 2357 __le16 node_handle; 2358}; 2359 2360/* Set CGU DPLL config (direct 0x0C67) */ 2361struct ice_aqc_set_cgu_dpll_config { 2362 u8 dpll_num; 2363 u8 ref_state; 2364#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0) 2365#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1) 2366#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2) 2367#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3) 2368#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4) 2369#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5) 2370#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6) 2371 u8 rsvd; 2372 u8 config; 2373#define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0) 2374#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 5 2375#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \ 2376 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2377#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 0 2378#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \ 2379 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT) 2380 u8 rsvd2[8]; 2381 u8 eec_mode; 2382 u8 rsvd3[1]; 2383 __le16 node_handle; 2384}; 2385 2386/* Set CGU reference priority (direct 0x0C68) */ 2387struct ice_aqc_set_cgu_ref_prio { 2388 u8 dpll_num; 2389 u8 ref_idx; 2390 u8 ref_priority; 2391 u8 rsvd[11]; 2392 __le16 node_handle; 2393}; 2394 2395/* Get CGU reference priority (direct 0x0C69) */ 2396struct ice_aqc_get_cgu_ref_prio { 2397 u8 dpll_num; 2398 u8 ref_idx; 2399 u8 ref_priority; /* Valid only in response */ 2400 u8 rsvd[13]; 2401}; 2402 2403/* Get CGU info (direct 0x0C6A) */ 2404struct ice_aqc_get_cgu_info { 2405 __le32 cgu_id; 2406 __le32 cgu_cfg_ver; 2407 __le32 cgu_fw_ver; 2408 u8 node_part_num; 2409 u8 dev_rev; 2410 __le16 node_handle; 2411}; 2412 2413/* Driver Shared Parameters (direct, 0x0C90) */ 2414struct ice_aqc_driver_shared_params { 2415 u8 set_or_get_op; 2416#define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2417#define ICE_AQC_DRIVER_PARAM_SET 0 2418#define ICE_AQC_DRIVER_PARAM_GET 1 2419 u8 param_indx; 2420#define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2421 u8 rsvd[2]; 2422 __le32 param_val; 2423 __le32 addr_high; 2424 __le32 addr_low; 2425}; 2426 2427/* Lan Queue Overflow Event (direct, 0x1001) */ 2428struct ice_aqc_event_lan_overflow { 2429 __le32 prtdcb_ruptq; 2430 __le32 qtx_ctl; 2431 u8 reserved[8]; 2432}; 2433 2434enum ice_aqc_health_status_mask { 2435 ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK = BIT(0), 2436 ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK = BIT(1), 2437 ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK = BIT(2), 2438}; 2439 2440/* Set Health Status (direct 0xFF20) */ 2441struct ice_aqc_set_health_status_cfg { 2442 u8 event_source; 2443 u8 reserved[15]; 2444}; 2445 2446enum ice_aqc_health_status { 2447 ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT = 0x101, 2448 ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE = 0x102, 2449 ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL = 0x103, 2450 ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM = 0x104, 2451 ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT = 0x105, 2452 ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT = 0x106, 2453 ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED = 0x107, 2454 ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT = 0x108, 2455 ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE = 0x109, 2456 ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG = 0x10B, 2457 ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS = 0x10C, 2458 ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE = 0x10D, 2459 ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED = 0x10F, 2460 ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT = 0x110, 2461 ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED = 0x111, 2462 ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO = 0x112, 2463 ICE_AQC_HEALTH_STATUS_ERR_NETLIST = 0x113, 2464 ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT = 0x114, 2465 ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS = 0x115, 2466 ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME = 0x116, 2467 ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT = 0x117, 2468 ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG = 0x120, 2469 ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD = 0x121, 2470 ICE_AQC_HEALTH_STATUS_INFO_RECOVERY = 0x500, 2471 ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS = 0x501, 2472 ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH = 0x502, 2473 ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH = 0x503, 2474 ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH = 0x504, 2475 ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT = 0x505, 2476 ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT = 0x506, 2477 ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION = 0x507, 2478 ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION = 0x508, 2479 ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB = 0x509, 2480 ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT = 0x50A, 2481 ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET = 0x50B, 2482 ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL = 0x50C, 2483 ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL = 0x50D, 2484 ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP = 0x1000, 2485 ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL = 0x1001, 2486 ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ = 0x1002, 2487}; 2488 2489/* Get Health Status (indirect 0xFF22) */ 2490struct ice_aqc_get_health_status { 2491 __le16 health_status_count; 2492 u8 reserved[6]; 2493 __le32 addr_high; 2494 __le32 addr_low; 2495}; 2496 2497enum ice_aqc_health_status_scope { 2498 ICE_AQC_HEALTH_STATUS_PF = 0x1, 2499 ICE_AQC_HEALTH_STATUS_PORT = 0x2, 2500 ICE_AQC_HEALTH_STATUS_GLOBAL = 0x3, 2501}; 2502 2503#define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA 0xDEADBEEF 2504 2505/* Get Health Status event buffer entry (0xFF22), 2506 * repeated per reported health status. 2507 */ 2508struct ice_aqc_health_status_elem { 2509 __le16 health_status_code; 2510 __le16 event_source; 2511 __le32 internal_data1; 2512 __le32 internal_data2; 2513}; 2514 2515/* Admin Queue command opcodes */ 2516enum ice_adminq_opc { 2517 /* AQ commands */ 2518 ice_aqc_opc_get_ver = 0x0001, 2519 ice_aqc_opc_driver_ver = 0x0002, 2520 ice_aqc_opc_q_shutdown = 0x0003, 2521 2522 /* resource ownership */ 2523 ice_aqc_opc_req_res = 0x0008, 2524 ice_aqc_opc_release_res = 0x0009, 2525 2526 /* device/function capabilities */ 2527 ice_aqc_opc_list_func_caps = 0x000A, 2528 ice_aqc_opc_list_dev_caps = 0x000B, 2529 2530 /* manage MAC address */ 2531 ice_aqc_opc_manage_mac_read = 0x0107, 2532 ice_aqc_opc_manage_mac_write = 0x0108, 2533 2534 /* PXE */ 2535 ice_aqc_opc_clear_pxe_mode = 0x0110, 2536 2537 /* internal switch commands */ 2538 ice_aqc_opc_get_sw_cfg = 0x0200, 2539 ice_aqc_opc_set_port_params = 0x0203, 2540 2541 /* Alloc/Free/Get Resources */ 2542 ice_aqc_opc_alloc_res = 0x0208, 2543 ice_aqc_opc_free_res = 0x0209, 2544 ice_aqc_opc_share_res = 0x020B, 2545 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 2546 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 2547 2548 /* VSI commands */ 2549 ice_aqc_opc_add_vsi = 0x0210, 2550 ice_aqc_opc_update_vsi = 0x0211, 2551 ice_aqc_opc_free_vsi = 0x0213, 2552 2553 /* recipe commands */ 2554 ice_aqc_opc_add_recipe = 0x0290, 2555 ice_aqc_opc_recipe_to_profile = 0x0291, 2556 ice_aqc_opc_get_recipe = 0x0292, 2557 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2558 2559 /* switch rules population commands */ 2560 ice_aqc_opc_add_sw_rules = 0x02A0, 2561 ice_aqc_opc_update_sw_rules = 0x02A1, 2562 ice_aqc_opc_remove_sw_rules = 0x02A2, 2563 2564 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2565 2566 /* DCB commands */ 2567 ice_aqc_opc_query_pfc_mode = 0x0302, 2568 ice_aqc_opc_set_pfc_mode = 0x0303, 2569 2570 /* transmit scheduler commands */ 2571 ice_aqc_opc_get_dflt_topo = 0x0400, 2572 ice_aqc_opc_add_sched_elems = 0x0401, 2573 ice_aqc_opc_cfg_sched_elems = 0x0403, 2574 ice_aqc_opc_get_sched_elems = 0x0404, 2575 ice_aqc_opc_move_sched_elems = 0x0408, 2576 ice_aqc_opc_suspend_sched_elems = 0x0409, 2577 ice_aqc_opc_resume_sched_elems = 0x040A, 2578 ice_aqc_opc_query_port_ets = 0x040E, 2579 ice_aqc_opc_delete_sched_elems = 0x040F, 2580 ice_aqc_opc_add_rl_profiles = 0x0410, 2581 ice_aqc_opc_query_sched_res = 0x0412, 2582 ice_aqc_opc_remove_rl_profiles = 0x0415, 2583 2584 /* tx topology commands */ 2585 ice_aqc_opc_set_tx_topo = 0x0417, 2586 ice_aqc_opc_get_tx_topo = 0x0418, 2587 2588 /* PHY commands */ 2589 ice_aqc_opc_get_phy_caps = 0x0600, 2590 ice_aqc_opc_set_phy_cfg = 0x0601, 2591 ice_aqc_opc_set_mac_cfg = 0x0603, 2592 ice_aqc_opc_restart_an = 0x0605, 2593 ice_aqc_opc_get_link_status = 0x0607, 2594 ice_aqc_opc_set_event_mask = 0x0613, 2595 ice_aqc_opc_set_mac_lb = 0x0620, 2596 ice_aqc_opc_set_phy_rec_clk_out = 0x0630, 2597 ice_aqc_opc_get_phy_rec_clk_out = 0x0631, 2598 ice_aqc_opc_get_sensor_reading = 0x0632, 2599 ice_aqc_opc_dnl_call = 0x0682, 2600 ice_aqc_opc_get_link_topo = 0x06E0, 2601 ice_aqc_opc_read_i2c = 0x06E2, 2602 ice_aqc_opc_write_i2c = 0x06E3, 2603 ice_aqc_opc_set_port_id_led = 0x06E9, 2604 ice_aqc_opc_get_port_options = 0x06EA, 2605 ice_aqc_opc_set_port_option = 0x06EB, 2606 ice_aqc_opc_set_gpio = 0x06EC, 2607 ice_aqc_opc_get_gpio = 0x06ED, 2608 ice_aqc_opc_sff_eeprom = 0x06EE, 2609 2610 /* NVM commands */ 2611 ice_aqc_opc_nvm_read = 0x0701, 2612 ice_aqc_opc_nvm_erase = 0x0702, 2613 ice_aqc_opc_nvm_write = 0x0703, 2614 ice_aqc_opc_nvm_checksum = 0x0706, 2615 ice_aqc_opc_nvm_write_activate = 0x0707, 2616 ice_aqc_opc_nvm_update_empr = 0x0709, 2617 ice_aqc_opc_nvm_pkg_data = 0x070A, 2618 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2619 2620 /* PF/VF mailbox commands */ 2621 ice_mbx_opc_send_msg_to_pf = 0x0801, 2622 ice_mbx_opc_send_msg_to_vf = 0x0802, 2623 /* LLDP commands */ 2624 ice_aqc_opc_lldp_get_mib = 0x0A00, 2625 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2626 ice_aqc_opc_lldp_stop = 0x0A05, 2627 ice_aqc_opc_lldp_start = 0x0A06, 2628 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2629 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2630 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2631 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2632 ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B, 2633 2634 /* RSS commands */ 2635 ice_aqc_opc_set_rss_key = 0x0B02, 2636 ice_aqc_opc_set_rss_lut = 0x0B03, 2637 ice_aqc_opc_get_rss_key = 0x0B04, 2638 ice_aqc_opc_get_rss_lut = 0x0B05, 2639 2640 /* Sideband Control Interface commands */ 2641 ice_aqc_opc_neighbour_device_request = 0x0C00, 2642 2643 /* Tx queue handling commands/events */ 2644 ice_aqc_opc_add_txqs = 0x0C30, 2645 ice_aqc_opc_dis_txqs = 0x0C31, 2646 ice_aqc_opc_cfg_txqs = 0x0C32, 2647 ice_aqc_opc_add_rdma_qset = 0x0C33, 2648 2649 /* Tx Time queue commands */ 2650 ice_aqc_opc_set_txtimeqs = 0x0C35, 2651 2652 /* package commands */ 2653 ice_aqc_opc_download_pkg = 0x0C40, 2654 ice_aqc_opc_upload_section = 0x0C41, 2655 ice_aqc_opc_update_pkg = 0x0C42, 2656 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2657 2658 /* 1588/SyncE commands/events */ 2659 ice_aqc_opc_get_cgu_input_measure = 0x0C59, 2660 ice_aqc_opc_get_cgu_abilities = 0x0C61, 2661 ice_aqc_opc_set_cgu_input_config = 0x0C62, 2662 ice_aqc_opc_get_cgu_input_config = 0x0C63, 2663 ice_aqc_opc_set_cgu_output_config = 0x0C64, 2664 ice_aqc_opc_get_cgu_output_config = 0x0C65, 2665 ice_aqc_opc_get_cgu_dpll_status = 0x0C66, 2666 ice_aqc_opc_set_cgu_dpll_config = 0x0C67, 2667 ice_aqc_opc_set_cgu_ref_prio = 0x0C68, 2668 ice_aqc_opc_get_cgu_ref_prio = 0x0C69, 2669 ice_aqc_opc_get_cgu_info = 0x0C6A, 2670 2671 ice_aqc_opc_driver_shared_params = 0x0C90, 2672 2673 /* Standalone Commands/Events */ 2674 ice_aqc_opc_event_lan_overflow = 0x1001, 2675 2676 /* System Diagnostic commands */ 2677 ice_aqc_opc_set_health_status_cfg = 0xFF20, 2678 ice_aqc_opc_get_health_status = 0xFF22, 2679 2680 /* FW Logging Commands */ 2681 ice_aqc_opc_fw_logs_config = 0xFF30, 2682 ice_aqc_opc_fw_logs_register = 0xFF31, 2683 ice_aqc_opc_fw_logs_query = 0xFF32, 2684 ice_aqc_opc_fw_logs_event = 0xFF33, 2685}; 2686 2687#endif /* _ICE_ADMINQ_CMD_H_ */
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