iavf_type.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright(c) 2013 - 2018 Intel Corporation. */
  3
  4#ifndef _IAVF_TYPE_H_
  5#define _IAVF_TYPE_H_
  6
  7#include "iavf_status.h"
  8#include "iavf_osdep.h"
  9#include "iavf_register.h"
 10#include "iavf_adminq.h"
 11#include "iavf_devids.h"
 12
 13/* IAVF_MASK is a macro used on 32 bit registers */
 14#define IAVF_MASK(mask, shift) ((u32)(mask) << (shift))
 15
 16#define IAVF_MAX_VSI_QP			16
 17#define IAVF_MAX_VF_VSI			3
 18#define IAVF_MAX_CHAINED_RX_BUFFERS	5
 19
 20/* forward declaration */
 21struct iavf_hw;
 22typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct libie_aq_desc *);
 23
 24/* Data type manipulation macros. */
 25
 26#define IAVF_DESC_UNUSED(R)	\
 27	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 28	(R)->next_to_clean - (R)->next_to_use - 1)
 29
 30/* bitfields for Tx queue mapping in QTX_CTL */
 31#define IAVF_QTX_CTL_VF_QUEUE	0x0
 32#define IAVF_QTX_CTL_VM_QUEUE	0x1
 33#define IAVF_QTX_CTL_PF_QUEUE	0x2
 34
 35/* debug masks - set these bits in hw->debug_mask to control output */
 36enum iavf_debug_mask {
 37	IAVF_DEBUG_INIT			= 0x00000001,
 38	IAVF_DEBUG_RELEASE		= 0x00000002,
 39
 40	IAVF_DEBUG_LINK			= 0x00000010,
 41	IAVF_DEBUG_PHY			= 0x00000020,
 42	IAVF_DEBUG_HMC			= 0x00000040,
 43	IAVF_DEBUG_NVM			= 0x00000080,
 44	IAVF_DEBUG_LAN			= 0x00000100,
 45	IAVF_DEBUG_FLOW			= 0x00000200,
 46	IAVF_DEBUG_DCB			= 0x00000400,
 47	IAVF_DEBUG_DIAG			= 0x00000800,
 48	IAVF_DEBUG_FD			= 0x00001000,
 49	IAVF_DEBUG_PACKAGE		= 0x00002000,
 50
 51	IAVF_DEBUG_AQ_MESSAGE		= 0x01000000,
 52	IAVF_DEBUG_AQ_DESCRIPTOR	= 0x02000000,
 53	IAVF_DEBUG_AQ_DESC_BUFFER	= 0x04000000,
 54	IAVF_DEBUG_AQ_COMMAND		= 0x06000000,
 55	IAVF_DEBUG_AQ			= 0x0F000000,
 56
 57	IAVF_DEBUG_USER			= 0xF0000000,
 58
 59	IAVF_DEBUG_ALL			= 0xFFFFFFFF
 60};
 61
 62/* These are structs for managing the hardware information and the operations.
 63 * The structures of function pointers are filled out at init time when we
 64 * know for sure exactly which hardware we're working with.  This gives us the
 65 * flexibility of using the same main driver code but adapting to slightly
 66 * different hardware needs as new parts are developed.  For this architecture,
 67 * the Firmware and AdminQ are intended to insulate the driver from most of the
 68 * future changes, but these structures will also do part of the job.
 69 */
 70enum iavf_vsi_type {
 71	IAVF_VSI_MAIN	= 0,
 72	IAVF_VSI_VMDQ1	= 1,
 73	IAVF_VSI_VMDQ2	= 2,
 74	IAVF_VSI_CTRL	= 3,
 75	IAVF_VSI_FCOE	= 4,
 76	IAVF_VSI_MIRROR	= 5,
 77	IAVF_VSI_SRIOV	= 6,
 78	IAVF_VSI_FDIR	= 7,
 79	IAVF_VSI_TYPE_UNKNOWN
 80};
 81
 82enum iavf_queue_type {
 83	IAVF_QUEUE_TYPE_RX = 0,
 84	IAVF_QUEUE_TYPE_TX,
 85	IAVF_QUEUE_TYPE_PE_CEQ,
 86	IAVF_QUEUE_TYPE_UNKNOWN
 87};
 88
 89#define IAVF_HW_CAP_MAX_GPIO		30
 90/* Capabilities of a PF or a VF or the whole device */
 91struct iavf_hw_capabilities {
 92	bool dcb;
 93	bool fcoe;
 94	u32 num_vsis;
 95	u32 num_rx_qp;
 96	u32 num_tx_qp;
 97	u32 base_queue;
 98	u32 num_msix_vectors_vf;
 99};
100
101struct iavf_mac_info {
102	u8 addr[ETH_ALEN];
103	u8 perm_addr[ETH_ALEN];
104};
105
106/* PCI bus types */
107enum iavf_bus_type {
108	iavf_bus_type_unknown = 0,
109	iavf_bus_type_pci,
110	iavf_bus_type_pcix,
111	iavf_bus_type_pci_express,
112	iavf_bus_type_reserved
113};
114
115/* PCI bus speeds */
116enum iavf_bus_speed {
117	iavf_bus_speed_unknown	= 0,
118	iavf_bus_speed_33	= 33,
119	iavf_bus_speed_66	= 66,
120	iavf_bus_speed_100	= 100,
121	iavf_bus_speed_120	= 120,
122	iavf_bus_speed_133	= 133,
123	iavf_bus_speed_2500	= 2500,
124	iavf_bus_speed_5000	= 5000,
125	iavf_bus_speed_8000	= 8000,
126	iavf_bus_speed_reserved
127};
128
129/* PCI bus widths */
130enum iavf_bus_width {
131	iavf_bus_width_unknown	= 0,
132	iavf_bus_width_pcie_x1	= 1,
133	iavf_bus_width_pcie_x2	= 2,
134	iavf_bus_width_pcie_x4	= 4,
135	iavf_bus_width_pcie_x8	= 8,
136	iavf_bus_width_32	= 32,
137	iavf_bus_width_64	= 64,
138	iavf_bus_width_reserved
139};
140
141/* Bus parameters */
142struct iavf_bus_info {
143	enum iavf_bus_speed speed;
144	enum iavf_bus_width width;
145	enum iavf_bus_type type;
146
147	u16 func;
148	u16 device;
149	u16 lan_id;
150	u16 bus_id;
151};
152
153#define IAVF_MAX_USER_PRIORITY		8
154/* Port hardware description */
155struct iavf_hw {
156	u8 __iomem *hw_addr;
157	void *back;
158
159	/* subsystem structs */
160	struct iavf_mac_info mac;
161	struct iavf_bus_info bus;
162
163	/* pci info */
164	u16 device_id;
165	u16 vendor_id;
166	u16 subsystem_device_id;
167	u16 subsystem_vendor_id;
168	u8 revision_id;
169
170	/* capabilities for entire device and PCI func */
171	struct iavf_hw_capabilities dev_caps;
172
173	/* Admin Queue info */
174	struct iavf_adminq_info aq;
175
176	/* debug mask */
177	u32 debug_mask;
178	char err_str[16];
179};
180
181/**
182 * struct iavf_rx_desc - Receive descriptor (both legacy and flexible)
183 * @qw0: quad word 0 fields:
184 *	 Legacy: Descriptor Type; Mirror ID; L2TAG1P (S-TAG); Filter Status
185 *	 Flex: Descriptor Type; Mirror ID; UMBCAST; Packet Type; Flexible Flags
186 *	       Section 0; Packet Length; Header Length; Split Header Flag;
187 *	       Flexible Flags section 1 / Extended Status
188 * @qw1: quad word 1 fields:
189 *	 Legacy: Status Field; Error Field; Packet Type; Packet Length (packet,
190 *		 header, Split Header Flag)
191 *	 Flex: Status / Error 0 Field; L2TAG1P (S-TAG); Flexible Metadata
192 *	       Container #0; Flexible Metadata Container #1
193 * @qw2: quad word 2 fields:
194 *	 Legacy: Extended Status; 1st L2TAG2P (C-TAG); 2nd L2TAG2P (C-TAG)
195 *	 Flex: Status / Error 1 Field; Flexible Flags section 2; Timestamp Low;
196 *	       1st L2TAG2 (C-TAG); 2nd L2TAG2 (C-TAG)
197 * @qw3: quad word 3 fields:
198 *	 Legacy: FD Filter ID / Flexible Bytes
199 *	 Flex: Flexible Metadata Container #2; Flexible Metadata Container #3;
200 *	       Flexible Metadata Container #4 / Timestamp High 0; Flexible
201 *	       Metadata Container #5 / Timestamp High 1;
202 */
203struct iavf_rx_desc {
204	aligned_le64 qw0;
205/* The hash signature (RSS) */
206#define IAVF_RXD_LEGACY_RSS_M			GENMASK_ULL(63, 32)
207/* Stripped C-TAG VLAN from the receive packet */
208#define IAVF_RXD_LEGACY_L2TAG1_M		GENMASK_ULL(33, 16)
209/* Packet type */
210#define IAVF_RXD_FLEX_PTYPE_M			GENMASK_ULL(25, 16)
211/* Packet length */
212#define IAVF_RXD_FLEX_PKT_LEN_M			GENMASK_ULL(45, 32)
213
214	aligned_le64 qw1;
215/* Descriptor done indication flag. */
216#define IAVF_RXD_LEGACY_DD_M			BIT(0)
217/* End of packet. Set to 1 if this descriptor is the last one of the packet */
218#define IAVF_RXD_LEGACY_EOP_M			BIT(1)
219/* L2 TAG 1 presence indication */
220#define IAVF_RXD_LEGACY_L2TAG1P_M		BIT(2)
221/* Detectable L3 and L4 integrity check is processed by the HW */
222#define IAVF_RXD_LEGACY_L3L4P_M			BIT(3)
223/* Set when an IPv6 packet contains a Destination Options Header or a Routing
224 * Header.
225 */
226#define IAVF_RXD_LEGACY_IPV6EXADD_M		BIT(15)
227/* Receive MAC Errors: CRC; Alignment; Oversize; Undersizes; Length error */
228#define IAVF_RXD_LEGACY_RXE_M			BIT(19)
229/* Checksum reports:
230 * - IPE: IP checksum error
231 * - L4E: L4 integrity error
232 * - EIPE: External IP header (tunneled packets)
233 */
234#define IAVF_RXD_LEGACY_IPE_M			BIT(22)
235#define IAVF_RXD_LEGACY_L4E_M			BIT(23)
236#define IAVF_RXD_LEGACY_EIPE_M			BIT(24)
237/* Set for packets that skip checksum calculation in pre-parser */
238#define IAVF_RXD_LEGACY_PPRS_M			BIT(26)
239/* Indicates the content in the Filter Status field */
240#define IAVF_RXD_LEGACY_FLTSTAT_M		GENMASK_ULL(13, 12)
241/* Packet type */
242#define IAVF_RXD_LEGACY_PTYPE_M			GENMASK_ULL(37, 30)
243/* Packet length */
244#define IAVF_RXD_LEGACY_LENGTH_M		GENMASK_ULL(51, 38)
245/* Descriptor done indication flag */
246#define IAVF_RXD_FLEX_DD_M			BIT(0)
247/* End of packet. Set to 1 if this descriptor is the last one of the packet */
248#define IAVF_RXD_FLEX_EOP_M			BIT(1)
249/* Detectable L3 and L4 integrity check is processed by the HW */
250#define IAVF_RXD_FLEX_L3L4P_M			BIT(3)
251/* Checksum reports:
252 * - IPE: IP checksum error
253 * - L4E: L4 integrity error
254 * - EIPE: External IP header (tunneled packets)
255 * - EUDPE: External UDP checksum error (tunneled packets)
256 */
257#define IAVF_RXD_FLEX_XSUM_IPE_M		BIT(4)
258#define IAVF_RXD_FLEX_XSUM_L4E_M		BIT(5)
259#define IAVF_RXD_FLEX_XSUM_EIPE_M		BIT(6)
260#define IAVF_RXD_FLEX_XSUM_EUDPE_M		BIT(7)
261/* Set when an IPv6 packet contains a Destination Options Header or a Routing
262 * Header.
263 */
264#define IAVF_RXD_FLEX_IPV6EXADD_M		BIT(9)
265/* Receive MAC Errors: CRC; Alignment; Oversize; Undersizes; Length error */
266#define IAVF_RXD_FLEX_RXE_M			BIT(10)
267/* Indicates that the RSS/HASH result is valid */
268#define IAVF_RXD_FLEX_RSS_VALID_M		BIT(12)
269/* L2 TAG 1 presence indication */
270#define IAVF_RXD_FLEX_L2TAG1P_M			BIT(13)
271/* Stripped L2 Tag from the receive packet */
272#define IAVF_RXD_FLEX_L2TAG1_M			GENMASK_ULL(31, 16)
273/* The hash signature (RSS) */
274#define IAVF_RXD_FLEX_RSS_HASH_M		GENMASK_ULL(63, 32)
275
276	aligned_le64 qw2;
277/* L2 Tag 2 Presence */
278#define IAVF_RXD_LEGACY_L2TAG2P_M		BIT(0)
279/* Stripped S-TAG VLAN from the receive packet */
280#define IAVF_RXD_LEGACY_L2TAG2_M		GENMASK_ULL(63, 32)
281/* Stripped S-TAG VLAN from the receive packet */
282#define IAVF_RXD_FLEX_L2TAG2_2_M		GENMASK_ULL(63, 48)
283/* The packet is a UDP tunneled packet */
284#define IAVF_RXD_FLEX_NAT_M			BIT(4)
285/* L2 Tag 2 Presence */
286#define IAVF_RXD_FLEX_L2TAG2P_M			BIT(11)
287	aligned_le64 qw3;
288#define IAVF_RXD_FLEX_QW3_TSTAMP_HIGH_M		GENMASK_ULL(63, 32)
289} __aligned(4 * sizeof(__le64));
290static_assert(sizeof(struct iavf_rx_desc) == 32);
291
292#define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
293#define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK  (0x3UL << \
294					    IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
295
296#define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
297#define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK \
298				    BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
299
300enum iavf_rx_desc_fltstat_values {
301	IAVF_RX_DESC_FLTSTAT_NO_DATA	= 0,
302	IAVF_RX_DESC_FLTSTAT_RSV_FD_ID	= 1, /* 16byte desc? FD_ID : RSV */
303	IAVF_RX_DESC_FLTSTAT_RSV	= 2,
304	IAVF_RX_DESC_FLTSTAT_RSS_HASH	= 3,
305};
306
307enum iavf_rx_desc_error_l3l4e_fcoe_masks {
308	IAVF_RX_DESC_ERROR_L3L4E_NONE		= 0,
309	IAVF_RX_DESC_ERROR_L3L4E_PROT		= 1,
310	IAVF_RX_DESC_ERROR_L3L4E_FC		= 2,
311	IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR	= 3,
312	IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN	= 4
313};
314
315#define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT	52
316#define IAVF_RXD_QW1_LENGTH_HBUF_MASK	(0x7FFULL << \
317					 IAVF_RXD_QW1_LENGTH_HBUF_SHIFT)
318
319#define IAVF_RXD_QW1_LENGTH_SPH_SHIFT	63
320#define IAVF_RXD_QW1_LENGTH_SPH_MASK	BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
321
322enum iavf_rx_desc_ext_status_bits {
323	/* Note: These are predefined bit offsets */
324	IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT	= 0,
325	IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT	= 1,
326	IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT	= 2, /* 2 BITS */
327	IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT	= 4, /* 2 BITS */
328	IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT	= 9,
329	IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT	= 10,
330	IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT	= 11,
331};
332
333#define IAVF_RX_DESC_EXT_STATUS_L2TAG2P_M	BIT(IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)
334
335enum iavf_rx_desc_pe_status_bits {
336	/* Note: These are predefined bit offsets */
337	IAVF_RX_DESC_PE_STATUS_QPID_SHIFT	= 0, /* 18 BITS */
338	IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT	= 0, /* 16 BITS */
339	IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT	= 16, /* 8 BITS */
340	IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT	= 24,
341	IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT	= 25,
342	IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT	= 26,
343	IAVF_RX_DESC_PE_STATUS_URG_SHIFT	= 27,
344	IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT	= 28,
345	IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT	= 29
346};
347
348#define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT		38
349#define IAVF_RX_PROG_STATUS_DESC_LENGTH			0x2000000
350
351#define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT	2
352#define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK	(0x7UL << \
353				IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
354
355#define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT	19
356#define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK		(0x3FUL << \
357				IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
358
359enum iavf_rx_prog_status_desc_status_bits {
360	/* Note: These are predefined bit offsets */
361	IAVF_RX_PROG_STATUS_DESC_DD_SHIFT	= 0,
362	IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT	= 2 /* 3 BITS */
363};
364
365enum iavf_rx_prog_status_desc_prog_id_masks {
366	IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS	= 1,
367	IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS	= 2,
368	IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS	= 4,
369};
370
371enum iavf_rx_prog_status_desc_error_bits {
372	/* Note: These are predefined bit offsets */
373	IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT	= 0,
374	IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT	= 1,
375	IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT	= 2,
376	IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT	= 3
377};
378
379/* TX Descriptor */
380struct iavf_tx_desc {
381	__le64 buffer_addr; /* Address of descriptor's data buf */
382	__le64 cmd_type_offset_bsz;
383};
384
385#define IAVF_TXD_QW1_DTYPE_SHIFT	0
386#define IAVF_TXD_QW1_DTYPE_MASK		(0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
387
388enum iavf_tx_desc_dtype_value {
389	IAVF_TX_DESC_DTYPE_DATA		= 0x0,
390	IAVF_TX_DESC_DTYPE_NOP		= 0x1, /* same as Context desc */
391	IAVF_TX_DESC_DTYPE_CONTEXT	= 0x1,
392	IAVF_TX_DESC_DTYPE_FCOE_CTX	= 0x2,
393	IAVF_TX_DESC_DTYPE_FILTER_PROG	= 0x8,
394	IAVF_TX_DESC_DTYPE_DDP_CTX	= 0x9,
395	IAVF_TX_DESC_DTYPE_FLEX_DATA	= 0xB,
396	IAVF_TX_DESC_DTYPE_FLEX_CTX_1	= 0xC,
397	IAVF_TX_DESC_DTYPE_FLEX_CTX_2	= 0xD,
398	IAVF_TX_DESC_DTYPE_DESC_DONE	= 0xF
399};
400
401#define IAVF_TXD_QW1_CMD_SHIFT	4
402#define IAVF_TXD_QW1_CMD_MASK	(0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT)
403
404enum iavf_tx_desc_cmd_bits {
405	IAVF_TX_DESC_CMD_EOP			= 0x0001,
406	IAVF_TX_DESC_CMD_RS			= 0x0002,
407	IAVF_TX_DESC_CMD_ICRC			= 0x0004,
408	IAVF_TX_DESC_CMD_IL2TAG1		= 0x0008,
409	IAVF_TX_DESC_CMD_DUMMY			= 0x0010,
410	IAVF_TX_DESC_CMD_IIPT_NONIP		= 0x0000, /* 2 BITS */
411	IAVF_TX_DESC_CMD_IIPT_IPV6		= 0x0020, /* 2 BITS */
412	IAVF_TX_DESC_CMD_IIPT_IPV4		= 0x0040, /* 2 BITS */
413	IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM		= 0x0060, /* 2 BITS */
414	IAVF_TX_DESC_CMD_FCOET			= 0x0080,
415	IAVF_TX_DESC_CMD_L4T_EOFT_UNK		= 0x0000, /* 2 BITS */
416	IAVF_TX_DESC_CMD_L4T_EOFT_TCP		= 0x0100, /* 2 BITS */
417	IAVF_TX_DESC_CMD_L4T_EOFT_SCTP		= 0x0200, /* 2 BITS */
418	IAVF_TX_DESC_CMD_L4T_EOFT_UDP		= 0x0300, /* 2 BITS */
419	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N		= 0x0000, /* 2 BITS */
420	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T		= 0x0100, /* 2 BITS */
421	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI	= 0x0200, /* 2 BITS */
422	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A		= 0x0300, /* 2 BITS */
423};
424
425#define IAVF_TXD_QW1_OFFSET_SHIFT	16
426#define IAVF_TXD_QW1_OFFSET_MASK	(0x3FFFFULL << \
427					 IAVF_TXD_QW1_OFFSET_SHIFT)
428
429enum iavf_tx_desc_length_fields {
430	/* Note: These are predefined bit offsets */
431	IAVF_TX_DESC_LENGTH_MACLEN_SHIFT	= 0, /* 7 BITS */
432	IAVF_TX_DESC_LENGTH_IPLEN_SHIFT		= 7, /* 7 BITS */
433	IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT	= 14 /* 4 BITS */
434};
435
436#define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT	34
437#define IAVF_TXD_QW1_TX_BUF_SZ_MASK	(0x3FFFULL << \
438					 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)
439
440#define IAVF_TXD_QW1_L2TAG1_SHIFT	48
441#define IAVF_TXD_QW1_L2TAG1_MASK	(0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT)
442
443/* Context descriptors */
444struct iavf_tx_context_desc {
445	__le32 tunneling_params;
446	__le16 l2tag2;
447	__le16 rsvd;
448	__le64 type_cmd_tso_mss;
449};
450
451#define IAVF_TXD_CTX_QW1_CMD_SHIFT	4
452#define IAVF_TXD_CTX_QW1_CMD_MASK	(0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT)
453
454enum iavf_tx_ctx_desc_cmd_bits {
455	IAVF_TX_CTX_DESC_TSO		= 0x01,
456	IAVF_TX_CTX_DESC_TSYN		= 0x02,
457	IAVF_TX_CTX_DESC_IL2TAG2	= 0x04,
458	IAVF_TX_CTX_DESC_IL2TAG2_IL2H	= 0x08,
459	IAVF_TX_CTX_DESC_SWTCH_NOTAG	= 0x00,
460	IAVF_TX_CTX_DESC_SWTCH_UPLINK	= 0x10,
461	IAVF_TX_CTX_DESC_SWTCH_LOCAL	= 0x20,
462	IAVF_TX_CTX_DESC_SWTCH_VSI	= 0x30,
463	IAVF_TX_CTX_DESC_SWPE		= 0x40
464};
465
466#define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT	30
467#define IAVF_TXD_CTX_QW1_TSO_LEN_MASK	(0x3FFFFULL << \
468					 IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
469
470#define IAVF_TXD_CTX_QW1_MSS_SHIFT	50
471#define IAVF_TXD_CTX_QW1_MSS_MASK	(0x3FFFULL << \
472					 IAVF_TXD_CTX_QW1_MSS_SHIFT)
473
474#define IAVF_TXD_CTX_QW1_VSI_SHIFT	50
475#define IAVF_TXD_CTX_QW1_VSI_MASK	(0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
476
477#define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT	0
478#define IAVF_TXD_CTX_QW0_EXT_IP_MASK	(0x3ULL << \
479					 IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
480
481enum iavf_tx_ctx_desc_eipt_offload {
482	IAVF_TX_CTX_EXT_IP_NONE		= 0x0,
483	IAVF_TX_CTX_EXT_IP_IPV6		= 0x1,
484	IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM	= 0x2,
485	IAVF_TX_CTX_EXT_IP_IPV4		= 0x3
486};
487
488#define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT	2
489#define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK	(0x3FULL << \
490					 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
491
492#define IAVF_TXD_CTX_QW0_NATT_SHIFT	9
493#define IAVF_TXD_CTX_QW0_NATT_MASK	(0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
494
495#define IAVF_TXD_CTX_UDP_TUNNELING	BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
496#define IAVF_TXD_CTX_GRE_TUNNELING	(0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
497
498#define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT	11
499#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \
500				       BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
501
502#define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST	IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
503
504#define IAVF_TXD_CTX_QW0_NATLEN_SHIFT	12
505#define IAVF_TXD_CTX_QW0_NATLEN_MASK	(0X7FULL << \
506					 IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
507
508#define IAVF_TXD_CTX_QW0_DECTTL_SHIFT	19
509#define IAVF_TXD_CTX_QW0_DECTTL_MASK	(0xFULL << \
510					 IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
511
512#define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT	23
513#define IAVF_TXD_CTX_QW0_L4T_CS_MASK	BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
514
515/* Statistics collected by each port, VSI, VEB, and S-channel */
516struct iavf_eth_stats {
517	u64 rx_bytes;			/* gorc */
518	u64 rx_unicast;			/* uprc */
519	u64 rx_multicast;		/* mprc */
520	u64 rx_broadcast;		/* bprc */
521	u64 rx_discards;		/* rdpc */
522	u64 rx_unknown_protocol;	/* rupp */
523	u64 tx_bytes;			/* gotc */
524	u64 tx_unicast;			/* uptc */
525	u64 tx_multicast;		/* mptc */
526	u64 tx_broadcast;		/* bptc */
527	u64 tx_discards;		/* tdpc */
528	u64 tx_errors;			/* tepc */
529};
530#endif /* _IAVF_TYPE_H_ */