iavf_txrx.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4#include <linux/bitfield.h>
   5#include <linux/net/intel/libie/rx.h>
   6#include <linux/prefetch.h>
   7
   8#include "iavf.h"
   9#include "iavf_trace.h"
  10#include "iavf_prototype.h"
  11#include "iavf_ptp.h"
  12
  13/**
  14 * iavf_is_descriptor_done - tests DD bit in Rx descriptor
  15 * @qw1: quad word 1 from descriptor to get Descriptor Done field from
  16 * @flex: is the descriptor flex or legacy
  17 *
  18 * This function tests the descriptor done bit in specified descriptor. Because
  19 * there are two types of descriptors (legacy and flex) the parameter rx_ring
  20 * is used to distinguish.
  21 *
  22 * Return: true or false based on the state of DD bit in Rx descriptor.
  23 */
  24static bool iavf_is_descriptor_done(u64 qw1, bool flex)
  25{
  26	if (flex)
  27		return FIELD_GET(IAVF_RXD_FLEX_DD_M, qw1);
  28	else
  29		return FIELD_GET(IAVF_RXD_LEGACY_DD_M, qw1);
  30}
  31
  32static __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  33			 u32 td_tag)
  34{
  35	return cpu_to_le64(IAVF_TX_DESC_DTYPE_DATA |
  36			   ((u64)td_cmd  << IAVF_TXD_QW1_CMD_SHIFT) |
  37			   ((u64)td_offset << IAVF_TXD_QW1_OFFSET_SHIFT) |
  38			   ((u64)size  << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
  39			   ((u64)td_tag  << IAVF_TXD_QW1_L2TAG1_SHIFT));
  40}
  41
  42#define IAVF_TXD_CMD (IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_RS)
  43
  44/**
  45 * iavf_unmap_and_free_tx_resource - Release a Tx buffer
  46 * @ring:      the ring that owns the buffer
  47 * @tx_buffer: the buffer to free
  48 **/
  49static void iavf_unmap_and_free_tx_resource(struct iavf_ring *ring,
  50					    struct iavf_tx_buffer *tx_buffer)
  51{
  52	if (tx_buffer->skb) {
  53		if (tx_buffer->tx_flags & IAVF_TX_FLAGS_FD_SB)
  54			kfree(tx_buffer->raw_buf);
  55		else
  56			dev_kfree_skb_any(tx_buffer->skb);
  57		if (dma_unmap_len(tx_buffer, len))
  58			dma_unmap_single(ring->dev,
  59					 dma_unmap_addr(tx_buffer, dma),
  60					 dma_unmap_len(tx_buffer, len),
  61					 DMA_TO_DEVICE);
  62	} else if (dma_unmap_len(tx_buffer, len)) {
  63		dma_unmap_page(ring->dev,
  64			       dma_unmap_addr(tx_buffer, dma),
  65			       dma_unmap_len(tx_buffer, len),
  66			       DMA_TO_DEVICE);
  67	}
  68
  69	tx_buffer->next_to_watch = NULL;
  70	tx_buffer->skb = NULL;
  71	dma_unmap_len_set(tx_buffer, len, 0);
  72	/* tx_buffer must be completely set up in the transmit path */
  73}
  74
  75/**
  76 * iavf_clean_tx_ring - Free any empty Tx buffers
  77 * @tx_ring: ring to be cleaned
  78 **/
  79static void iavf_clean_tx_ring(struct iavf_ring *tx_ring)
  80{
  81	unsigned long bi_size;
  82	u16 i;
  83
  84	/* ring already cleared, nothing to do */
  85	if (!tx_ring->tx_bi)
  86		return;
  87
  88	/* Free all the Tx ring sk_buffs */
  89	for (i = 0; i < tx_ring->count; i++)
  90		iavf_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  91
  92	bi_size = sizeof(struct iavf_tx_buffer) * tx_ring->count;
  93	memset(tx_ring->tx_bi, 0, bi_size);
  94
  95	/* Zero out the descriptor ring */
  96	memset(tx_ring->desc, 0, tx_ring->size);
  97
  98	tx_ring->next_to_use = 0;
  99	tx_ring->next_to_clean = 0;
 100
 101	if (!tx_ring->netdev)
 102		return;
 103
 104	/* cleanup Tx queue statistics */
 105	netdev_tx_reset_queue(txring_txq(tx_ring));
 106}
 107
 108/**
 109 * iavf_free_tx_resources - Free Tx resources per queue
 110 * @tx_ring: Tx descriptor ring for a specific queue
 111 *
 112 * Free all transmit software resources
 113 **/
 114void iavf_free_tx_resources(struct iavf_ring *tx_ring)
 115{
 116	iavf_clean_tx_ring(tx_ring);
 117	kfree(tx_ring->tx_bi);
 118	tx_ring->tx_bi = NULL;
 119
 120	if (tx_ring->desc) {
 121		dma_free_coherent(tx_ring->dev, tx_ring->size,
 122				  tx_ring->desc, tx_ring->dma);
 123		tx_ring->desc = NULL;
 124	}
 125}
 126
 127/**
 128 * iavf_get_tx_pending - how many Tx descriptors not processed
 129 * @ring: the ring of descriptors
 130 * @in_sw: is tx_pending being checked in SW or HW
 131 *
 132 * Since there is no access to the ring head register
 133 * in XL710, we need to use our local copies
 134 **/
 135static u32 iavf_get_tx_pending(struct iavf_ring *ring, bool in_sw)
 136{
 137	u32 head, tail;
 138
 139	/* underlying hardware might not allow access and/or always return
 140	 * 0 for the head/tail registers so just use the cached values
 141	 */
 142	head = ring->next_to_clean;
 143	tail = ring->next_to_use;
 144
 145	if (head != tail)
 146		return (head < tail) ?
 147			tail - head : (tail + ring->count - head);
 148
 149	return 0;
 150}
 151
 152/**
 153 * iavf_force_wb - Issue SW Interrupt so HW does a wb
 154 * @vsi: the VSI we care about
 155 * @q_vector: the vector on which to force writeback
 156 **/
 157static void iavf_force_wb(struct iavf_vsi *vsi, struct iavf_q_vector *q_vector)
 158{
 159	u32 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
 160		  IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 161		  IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 162		  IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
 163		  /* allow 00 to be written to the index */;
 164
 165	wr32(&vsi->back->hw,
 166	     IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx),
 167	     val);
 168}
 169
 170/**
 171 * iavf_detect_recover_hung - Function to detect and recover hung_queues
 172 * @vsi:  pointer to vsi struct with tx queues
 173 *
 174 * VSI has netdev and netdev has TX queues. This function is to check each of
 175 * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
 176 **/
 177void iavf_detect_recover_hung(struct iavf_vsi *vsi)
 178{
 179	struct iavf_ring *tx_ring = NULL;
 180	struct net_device *netdev;
 181	unsigned int i;
 182	int packets;
 183
 184	if (!vsi)
 185		return;
 186
 187	if (test_bit(__IAVF_VSI_DOWN, vsi->state))
 188		return;
 189
 190	netdev = vsi->netdev;
 191	if (!netdev)
 192		return;
 193
 194	if (!netif_carrier_ok(netdev))
 195		return;
 196
 197	for (i = 0; i < vsi->back->num_active_queues; i++) {
 198		tx_ring = &vsi->back->tx_rings[i];
 199		if (tx_ring && tx_ring->desc) {
 200			/* If packet counter has not changed the queue is
 201			 * likely stalled, so force an interrupt for this
 202			 * queue.
 203			 *
 204			 * prev_pkt_ctr would be negative if there was no
 205			 * pending work.
 206			 */
 207			packets = tx_ring->stats.packets & INT_MAX;
 208			if (tx_ring->prev_pkt_ctr == packets) {
 209				iavf_force_wb(vsi, tx_ring->q_vector);
 210				continue;
 211			}
 212
 213			/* Memory barrier between read of packet count and call
 214			 * to iavf_get_tx_pending()
 215			 */
 216			smp_rmb();
 217			tx_ring->prev_pkt_ctr =
 218			  iavf_get_tx_pending(tx_ring, true) ? packets : -1;
 219		}
 220	}
 221}
 222
 223#define WB_STRIDE 4
 224
 225/**
 226 * iavf_clean_tx_irq - Reclaim resources after transmit completes
 227 * @vsi: the VSI we care about
 228 * @tx_ring: Tx ring to clean
 229 * @napi_budget: Used to determine if we are in netpoll
 230 *
 231 * Returns true if there's any budget left (e.g. the clean is finished)
 232 **/
 233static bool iavf_clean_tx_irq(struct iavf_vsi *vsi,
 234			      struct iavf_ring *tx_ring, int napi_budget)
 235{
 236	int i = tx_ring->next_to_clean;
 237	struct iavf_tx_buffer *tx_buf;
 238	struct iavf_tx_desc *tx_desc;
 239	unsigned int total_bytes = 0, total_packets = 0;
 240	unsigned int budget = IAVF_DEFAULT_IRQ_WORK;
 241
 242	tx_buf = &tx_ring->tx_bi[i];
 243	tx_desc = IAVF_TX_DESC(tx_ring, i);
 244	i -= tx_ring->count;
 245
 246	do {
 247		struct iavf_tx_desc *eop_desc = tx_buf->next_to_watch;
 248
 249		/* if next_to_watch is not set then there is no work pending */
 250		if (!eop_desc)
 251			break;
 252
 253		/* prevent any other reads prior to eop_desc */
 254		smp_rmb();
 255
 256		iavf_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
 257		/* if the descriptor isn't done, no work yet to do */
 258		if (!(eop_desc->cmd_type_offset_bsz &
 259		      cpu_to_le64(IAVF_TX_DESC_DTYPE_DESC_DONE)))
 260			break;
 261
 262		/* clear next_to_watch to prevent false hangs */
 263		tx_buf->next_to_watch = NULL;
 264
 265		/* update the statistics for this packet */
 266		total_bytes += tx_buf->bytecount;
 267		total_packets += tx_buf->gso_segs;
 268
 269		/* free the skb */
 270		napi_consume_skb(tx_buf->skb, napi_budget);
 271
 272		/* unmap skb header data */
 273		dma_unmap_single(tx_ring->dev,
 274				 dma_unmap_addr(tx_buf, dma),
 275				 dma_unmap_len(tx_buf, len),
 276				 DMA_TO_DEVICE);
 277
 278		/* clear tx_buffer data */
 279		tx_buf->skb = NULL;
 280		dma_unmap_len_set(tx_buf, len, 0);
 281
 282		/* unmap remaining buffers */
 283		while (tx_desc != eop_desc) {
 284			iavf_trace(clean_tx_irq_unmap,
 285				   tx_ring, tx_desc, tx_buf);
 286
 287			tx_buf++;
 288			tx_desc++;
 289			i++;
 290			if (unlikely(!i)) {
 291				i -= tx_ring->count;
 292				tx_buf = tx_ring->tx_bi;
 293				tx_desc = IAVF_TX_DESC(tx_ring, 0);
 294			}
 295
 296			/* unmap any remaining paged data */
 297			if (dma_unmap_len(tx_buf, len)) {
 298				dma_unmap_page(tx_ring->dev,
 299					       dma_unmap_addr(tx_buf, dma),
 300					       dma_unmap_len(tx_buf, len),
 301					       DMA_TO_DEVICE);
 302				dma_unmap_len_set(tx_buf, len, 0);
 303			}
 304		}
 305
 306		/* move us one more past the eop_desc for start of next pkt */
 307		tx_buf++;
 308		tx_desc++;
 309		i++;
 310		if (unlikely(!i)) {
 311			i -= tx_ring->count;
 312			tx_buf = tx_ring->tx_bi;
 313			tx_desc = IAVF_TX_DESC(tx_ring, 0);
 314		}
 315
 316		prefetch(tx_desc);
 317
 318		/* update budget accounting */
 319		budget--;
 320	} while (likely(budget));
 321
 322	i += tx_ring->count;
 323	tx_ring->next_to_clean = i;
 324	u64_stats_update_begin(&tx_ring->syncp);
 325	tx_ring->stats.bytes += total_bytes;
 326	tx_ring->stats.packets += total_packets;
 327	u64_stats_update_end(&tx_ring->syncp);
 328	tx_ring->q_vector->tx.total_bytes += total_bytes;
 329	tx_ring->q_vector->tx.total_packets += total_packets;
 330
 331	if (tx_ring->flags & IAVF_TXR_FLAGS_WB_ON_ITR) {
 332		/* check to see if there are < 4 descriptors
 333		 * waiting to be written back, then kick the hardware to force
 334		 * them to be written back in case we stay in NAPI.
 335		 * In this mode on X722 we do not enable Interrupt.
 336		 */
 337		unsigned int j = iavf_get_tx_pending(tx_ring, false);
 338
 339		if (budget &&
 340		    ((j / WB_STRIDE) == 0) && (j > 0) &&
 341		    !test_bit(__IAVF_VSI_DOWN, vsi->state) &&
 342		    (IAVF_DESC_UNUSED(tx_ring) != tx_ring->count))
 343			tx_ring->flags |= IAVF_TXR_FLAGS_ARM_WB;
 344	}
 345
 346	/* notify netdev of completed buffers */
 347	netdev_tx_completed_queue(txring_txq(tx_ring),
 348				  total_packets, total_bytes);
 349
 350#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
 351	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 352		     (IAVF_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 353		/* Make sure that anybody stopping the queue after this
 354		 * sees the new next_to_clean.
 355		 */
 356		smp_mb();
 357		if (__netif_subqueue_stopped(tx_ring->netdev,
 358					     tx_ring->queue_index) &&
 359		   !test_bit(__IAVF_VSI_DOWN, vsi->state)) {
 360			netif_wake_subqueue(tx_ring->netdev,
 361					    tx_ring->queue_index);
 362			++tx_ring->tx_stats.restart_queue;
 363		}
 364	}
 365
 366	return !!budget;
 367}
 368
 369/**
 370 * iavf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
 371 * @vsi: the VSI we care about
 372 * @q_vector: the vector on which to enable writeback
 373 *
 374 **/
 375static void iavf_enable_wb_on_itr(struct iavf_vsi *vsi,
 376				  struct iavf_q_vector *q_vector)
 377{
 378	u16 flags = q_vector->tx.ring[0].flags;
 379	u32 val;
 380
 381	if (!(flags & IAVF_TXR_FLAGS_WB_ON_ITR))
 382		return;
 383
 384	if (q_vector->arm_wb_state)
 385		return;
 386
 387	val = IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
 388	      IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
 389
 390	wr32(&vsi->back->hw,
 391	     IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx), val);
 392	q_vector->arm_wb_state = true;
 393}
 394
 395static bool iavf_container_is_rx(struct iavf_q_vector *q_vector,
 396				 struct iavf_ring_container *rc)
 397{
 398	return &q_vector->rx == rc;
 399}
 400
 401#define IAVF_AIM_MULTIPLIER_100G	2560
 402#define IAVF_AIM_MULTIPLIER_50G		1280
 403#define IAVF_AIM_MULTIPLIER_40G		1024
 404#define IAVF_AIM_MULTIPLIER_20G		512
 405#define IAVF_AIM_MULTIPLIER_10G		256
 406#define IAVF_AIM_MULTIPLIER_1G		32
 407
 408static unsigned int iavf_mbps_itr_multiplier(u32 speed_mbps)
 409{
 410	switch (speed_mbps) {
 411	case SPEED_100000:
 412		return IAVF_AIM_MULTIPLIER_100G;
 413	case SPEED_50000:
 414		return IAVF_AIM_MULTIPLIER_50G;
 415	case SPEED_40000:
 416		return IAVF_AIM_MULTIPLIER_40G;
 417	case SPEED_25000:
 418	case SPEED_20000:
 419		return IAVF_AIM_MULTIPLIER_20G;
 420	case SPEED_10000:
 421	default:
 422		return IAVF_AIM_MULTIPLIER_10G;
 423	case SPEED_1000:
 424	case SPEED_100:
 425		return IAVF_AIM_MULTIPLIER_1G;
 426	}
 427}
 428
 429static unsigned int
 430iavf_virtchnl_itr_multiplier(enum virtchnl_link_speed speed_virtchnl)
 431{
 432	switch (speed_virtchnl) {
 433	case VIRTCHNL_LINK_SPEED_40GB:
 434		return IAVF_AIM_MULTIPLIER_40G;
 435	case VIRTCHNL_LINK_SPEED_25GB:
 436	case VIRTCHNL_LINK_SPEED_20GB:
 437		return IAVF_AIM_MULTIPLIER_20G;
 438	case VIRTCHNL_LINK_SPEED_10GB:
 439	default:
 440		return IAVF_AIM_MULTIPLIER_10G;
 441	case VIRTCHNL_LINK_SPEED_1GB:
 442	case VIRTCHNL_LINK_SPEED_100MB:
 443		return IAVF_AIM_MULTIPLIER_1G;
 444	}
 445}
 446
 447static unsigned int iavf_itr_divisor(struct iavf_adapter *adapter)
 448{
 449	if (ADV_LINK_SUPPORT(adapter))
 450		return IAVF_ITR_ADAPTIVE_MIN_INC *
 451			iavf_mbps_itr_multiplier(adapter->link_speed_mbps);
 452	else
 453		return IAVF_ITR_ADAPTIVE_MIN_INC *
 454			iavf_virtchnl_itr_multiplier(adapter->link_speed);
 455}
 456
 457/**
 458 * iavf_update_itr - update the dynamic ITR value based on statistics
 459 * @q_vector: structure containing interrupt and ring information
 460 * @rc: structure containing ring performance data
 461 *
 462 * Stores a new ITR value based on packets and byte
 463 * counts during the last interrupt.  The advantage of per interrupt
 464 * computation is faster updates and more accurate ITR for the current
 465 * traffic pattern.  Constants in this function were computed
 466 * based on theoretical maximum wire speed and thresholds were set based
 467 * on testing data as well as attempting to minimize response time
 468 * while increasing bulk throughput.
 469 **/
 470static void iavf_update_itr(struct iavf_q_vector *q_vector,
 471			    struct iavf_ring_container *rc)
 472{
 473	unsigned int avg_wire_size, packets, bytes, itr;
 474	unsigned long next_update = jiffies;
 475
 476	/* If we don't have any rings just leave ourselves set for maximum
 477	 * possible latency so we take ourselves out of the equation.
 478	 */
 479	if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
 480		return;
 481
 482	/* For Rx we want to push the delay up and default to low latency.
 483	 * for Tx we want to pull the delay down and default to high latency.
 484	 */
 485	itr = iavf_container_is_rx(q_vector, rc) ?
 486	      IAVF_ITR_ADAPTIVE_MIN_USECS | IAVF_ITR_ADAPTIVE_LATENCY :
 487	      IAVF_ITR_ADAPTIVE_MAX_USECS | IAVF_ITR_ADAPTIVE_LATENCY;
 488
 489	/* If we didn't update within up to 1 - 2 jiffies we can assume
 490	 * that either packets are coming in so slow there hasn't been
 491	 * any work, or that there is so much work that NAPI is dealing
 492	 * with interrupt moderation and we don't need to do anything.
 493	 */
 494	if (time_after(next_update, rc->next_update))
 495		goto clear_counts;
 496
 497	/* If itr_countdown is set it means we programmed an ITR within
 498	 * the last 4 interrupt cycles. This has a side effect of us
 499	 * potentially firing an early interrupt. In order to work around
 500	 * this we need to throw out any data received for a few
 501	 * interrupts following the update.
 502	 */
 503	if (q_vector->itr_countdown) {
 504		itr = rc->target_itr;
 505		goto clear_counts;
 506	}
 507
 508	packets = rc->total_packets;
 509	bytes = rc->total_bytes;
 510
 511	if (iavf_container_is_rx(q_vector, rc)) {
 512		/* If Rx there are 1 to 4 packets and bytes are less than
 513		 * 9000 assume insufficient data to use bulk rate limiting
 514		 * approach unless Tx is already in bulk rate limiting. We
 515		 * are likely latency driven.
 516		 */
 517		if (packets && packets < 4 && bytes < 9000 &&
 518		    (q_vector->tx.target_itr & IAVF_ITR_ADAPTIVE_LATENCY)) {
 519			itr = IAVF_ITR_ADAPTIVE_LATENCY;
 520			goto adjust_by_size;
 521		}
 522	} else if (packets < 4) {
 523		/* If we have Tx and Rx ITR maxed and Tx ITR is running in
 524		 * bulk mode and we are receiving 4 or fewer packets just
 525		 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
 526		 * that the Rx can relax.
 527		 */
 528		if (rc->target_itr == IAVF_ITR_ADAPTIVE_MAX_USECS &&
 529		    (q_vector->rx.target_itr & IAVF_ITR_MASK) ==
 530		     IAVF_ITR_ADAPTIVE_MAX_USECS)
 531			goto clear_counts;
 532	} else if (packets > 32) {
 533		/* If we have processed over 32 packets in a single interrupt
 534		 * for Tx assume we need to switch over to "bulk" mode.
 535		 */
 536		rc->target_itr &= ~IAVF_ITR_ADAPTIVE_LATENCY;
 537	}
 538
 539	/* We have no packets to actually measure against. This means
 540	 * either one of the other queues on this vector is active or
 541	 * we are a Tx queue doing TSO with too high of an interrupt rate.
 542	 *
 543	 * Between 4 and 56 we can assume that our current interrupt delay
 544	 * is only slightly too low. As such we should increase it by a small
 545	 * fixed amount.
 546	 */
 547	if (packets < 56) {
 548		itr = rc->target_itr + IAVF_ITR_ADAPTIVE_MIN_INC;
 549		if ((itr & IAVF_ITR_MASK) > IAVF_ITR_ADAPTIVE_MAX_USECS) {
 550			itr &= IAVF_ITR_ADAPTIVE_LATENCY;
 551			itr += IAVF_ITR_ADAPTIVE_MAX_USECS;
 552		}
 553		goto clear_counts;
 554	}
 555
 556	if (packets <= 256) {
 557		itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
 558		itr &= IAVF_ITR_MASK;
 559
 560		/* Between 56 and 112 is our "goldilocks" zone where we are
 561		 * working out "just right". Just report that our current
 562		 * ITR is good for us.
 563		 */
 564		if (packets <= 112)
 565			goto clear_counts;
 566
 567		/* If packet count is 128 or greater we are likely looking
 568		 * at a slight overrun of the delay we want. Try halving
 569		 * our delay to see if that will cut the number of packets
 570		 * in half per interrupt.
 571		 */
 572		itr /= 2;
 573		itr &= IAVF_ITR_MASK;
 574		if (itr < IAVF_ITR_ADAPTIVE_MIN_USECS)
 575			itr = IAVF_ITR_ADAPTIVE_MIN_USECS;
 576
 577		goto clear_counts;
 578	}
 579
 580	/* The paths below assume we are dealing with a bulk ITR since
 581	 * number of packets is greater than 256. We are just going to have
 582	 * to compute a value and try to bring the count under control,
 583	 * though for smaller packet sizes there isn't much we can do as
 584	 * NAPI polling will likely be kicking in sooner rather than later.
 585	 */
 586	itr = IAVF_ITR_ADAPTIVE_BULK;
 587
 588adjust_by_size:
 589	/* If packet counts are 256 or greater we can assume we have a gross
 590	 * overestimation of what the rate should be. Instead of trying to fine
 591	 * tune it just use the formula below to try and dial in an exact value
 592	 * give the current packet size of the frame.
 593	 */
 594	avg_wire_size = bytes / packets;
 595
 596	/* The following is a crude approximation of:
 597	 *  wmem_default / (size + overhead) = desired_pkts_per_int
 598	 *  rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
 599	 *  (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
 600	 *
 601	 * Assuming wmem_default is 212992 and overhead is 640 bytes per
 602	 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
 603	 * formula down to
 604	 *
 605	 *  (170 * (size + 24)) / (size + 640) = ITR
 606	 *
 607	 * We first do some math on the packet size and then finally bitshift
 608	 * by 8 after rounding up. We also have to account for PCIe link speed
 609	 * difference as ITR scales based on this.
 610	 */
 611	if (avg_wire_size <= 60) {
 612		/* Start at 250k ints/sec */
 613		avg_wire_size = 4096;
 614	} else if (avg_wire_size <= 380) {
 615		/* 250K ints/sec to 60K ints/sec */
 616		avg_wire_size *= 40;
 617		avg_wire_size += 1696;
 618	} else if (avg_wire_size <= 1084) {
 619		/* 60K ints/sec to 36K ints/sec */
 620		avg_wire_size *= 15;
 621		avg_wire_size += 11452;
 622	} else if (avg_wire_size <= 1980) {
 623		/* 36K ints/sec to 30K ints/sec */
 624		avg_wire_size *= 5;
 625		avg_wire_size += 22420;
 626	} else {
 627		/* plateau at a limit of 30K ints/sec */
 628		avg_wire_size = 32256;
 629	}
 630
 631	/* If we are in low latency mode halve our delay which doubles the
 632	 * rate to somewhere between 100K to 16K ints/sec
 633	 */
 634	if (itr & IAVF_ITR_ADAPTIVE_LATENCY)
 635		avg_wire_size /= 2;
 636
 637	/* Resultant value is 256 times larger than it needs to be. This
 638	 * gives us room to adjust the value as needed to either increase
 639	 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
 640	 *
 641	 * Use addition as we have already recorded the new latency flag
 642	 * for the ITR value.
 643	 */
 644	itr += DIV_ROUND_UP(avg_wire_size,
 645			    iavf_itr_divisor(q_vector->adapter)) *
 646		IAVF_ITR_ADAPTIVE_MIN_INC;
 647
 648	if ((itr & IAVF_ITR_MASK) > IAVF_ITR_ADAPTIVE_MAX_USECS) {
 649		itr &= IAVF_ITR_ADAPTIVE_LATENCY;
 650		itr += IAVF_ITR_ADAPTIVE_MAX_USECS;
 651	}
 652
 653clear_counts:
 654	/* write back value */
 655	rc->target_itr = itr;
 656
 657	/* next update should occur within next jiffy */
 658	rc->next_update = next_update + 1;
 659
 660	rc->total_bytes = 0;
 661	rc->total_packets = 0;
 662}
 663
 664/**
 665 * iavf_setup_tx_descriptors - Allocate the Tx descriptors
 666 * @tx_ring: the tx ring to set up
 667 *
 668 * Return 0 on success, negative on error
 669 **/
 670int iavf_setup_tx_descriptors(struct iavf_ring *tx_ring)
 671{
 672	struct device *dev = tx_ring->dev;
 673	int bi_size;
 674
 675	if (!dev)
 676		return -ENOMEM;
 677
 678	/* warn if we are about to overwrite the pointer */
 679	WARN_ON(tx_ring->tx_bi);
 680	bi_size = sizeof(struct iavf_tx_buffer) * tx_ring->count;
 681	tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 682	if (!tx_ring->tx_bi)
 683		goto err;
 684
 685	/* round up to nearest 4K */
 686	tx_ring->size = tx_ring->count * sizeof(struct iavf_tx_desc);
 687	tx_ring->size = ALIGN(tx_ring->size, 4096);
 688	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 689					   &tx_ring->dma, GFP_KERNEL);
 690	if (!tx_ring->desc) {
 691		dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 692			 tx_ring->size);
 693		goto err;
 694	}
 695
 696	tx_ring->next_to_use = 0;
 697	tx_ring->next_to_clean = 0;
 698	tx_ring->prev_pkt_ctr = -1;
 699	return 0;
 700
 701err:
 702	kfree(tx_ring->tx_bi);
 703	tx_ring->tx_bi = NULL;
 704	return -ENOMEM;
 705}
 706
 707/**
 708 * iavf_clean_rx_ring - Free Rx buffers
 709 * @rx_ring: ring to be cleaned
 710 **/
 711static void iavf_clean_rx_ring(struct iavf_ring *rx_ring)
 712{
 713	/* ring already cleared, nothing to do */
 714	if (!rx_ring->rx_fqes)
 715		return;
 716
 717	if (rx_ring->skb) {
 718		dev_kfree_skb(rx_ring->skb);
 719		rx_ring->skb = NULL;
 720	}
 721
 722	/* Free all the Rx ring buffers */
 723	for (u32 i = rx_ring->next_to_clean; i != rx_ring->next_to_use; ) {
 724		const struct libeth_fqe *rx_fqes = &rx_ring->rx_fqes[i];
 725
 726		libeth_rx_recycle_slow(rx_fqes->netmem);
 727
 728		if (unlikely(++i == rx_ring->count))
 729			i = 0;
 730	}
 731
 732	rx_ring->next_to_clean = 0;
 733	rx_ring->next_to_use = 0;
 734}
 735
 736/**
 737 * iavf_free_rx_resources - Free Rx resources
 738 * @rx_ring: ring to clean the resources from
 739 *
 740 * Free all receive software resources
 741 **/
 742void iavf_free_rx_resources(struct iavf_ring *rx_ring)
 743{
 744	struct libeth_fq fq = {
 745		.fqes	= rx_ring->rx_fqes,
 746		.pp	= rx_ring->pp,
 747	};
 748
 749	iavf_clean_rx_ring(rx_ring);
 750
 751	if (rx_ring->desc) {
 752		dma_free_coherent(rx_ring->pp->p.dev, rx_ring->size,
 753				  rx_ring->desc, rx_ring->dma);
 754		rx_ring->desc = NULL;
 755	}
 756
 757	libeth_rx_fq_destroy(&fq);
 758	rx_ring->rx_fqes = NULL;
 759	rx_ring->pp = NULL;
 760}
 761
 762/**
 763 * iavf_setup_rx_descriptors - Allocate Rx descriptors
 764 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 765 *
 766 * Returns 0 on success, negative on failure
 767 **/
 768int iavf_setup_rx_descriptors(struct iavf_ring *rx_ring)
 769{
 770	struct libeth_fq fq = {
 771		.count		= rx_ring->count,
 772		.buf_len	= LIBIE_MAX_RX_BUF_LEN,
 773		.nid		= NUMA_NO_NODE,
 774	};
 775	int ret;
 776
 777	ret = libeth_rx_fq_create(&fq, &rx_ring->q_vector->napi);
 778	if (ret)
 779		return ret;
 780
 781	rx_ring->pp = fq.pp;
 782	rx_ring->rx_fqes = fq.fqes;
 783	rx_ring->truesize = fq.truesize;
 784	rx_ring->rx_buf_len = fq.buf_len;
 785
 786	u64_stats_init(&rx_ring->syncp);
 787
 788	/* Round up to nearest 4K */
 789	rx_ring->size = rx_ring->count * sizeof(struct iavf_rx_desc);
 790	rx_ring->size = ALIGN(rx_ring->size, 4096);
 791	rx_ring->desc = dma_alloc_coherent(fq.pp->p.dev, rx_ring->size,
 792					   &rx_ring->dma, GFP_KERNEL);
 793
 794	if (!rx_ring->desc) {
 795		dev_info(fq.pp->p.dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 796			 rx_ring->size);
 797		goto err;
 798	}
 799
 800	rx_ring->next_to_clean = 0;
 801	rx_ring->next_to_use = 0;
 802
 803	return 0;
 804
 805err:
 806	libeth_rx_fq_destroy(&fq);
 807	rx_ring->rx_fqes = NULL;
 808	rx_ring->pp = NULL;
 809
 810	return -ENOMEM;
 811}
 812
 813/**
 814 * iavf_release_rx_desc - Store the new tail and head values
 815 * @rx_ring: ring to bump
 816 * @val: new head index
 817 **/
 818static void iavf_release_rx_desc(struct iavf_ring *rx_ring, u32 val)
 819{
 820	rx_ring->next_to_use = val;
 821
 822	/* Force memory writes to complete before letting h/w
 823	 * know there are new descriptors to fetch.  (Only
 824	 * applicable for weak-ordered memory model archs,
 825	 * such as IA-64).
 826	 */
 827	wmb();
 828	writel(val, rx_ring->tail);
 829}
 830
 831/**
 832 * iavf_receive_skb - Send a completed packet up the stack
 833 * @rx_ring:  rx ring in play
 834 * @skb: packet to send up
 835 * @vlan_tag: vlan tag for packet
 836 **/
 837static void iavf_receive_skb(struct iavf_ring *rx_ring,
 838			     struct sk_buff *skb, u16 vlan_tag)
 839{
 840	struct iavf_q_vector *q_vector = rx_ring->q_vector;
 841
 842	if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
 843	    (vlan_tag & VLAN_VID_MASK))
 844		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 845	else if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_STAG_RX) &&
 846		 vlan_tag & VLAN_VID_MASK)
 847		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan_tag);
 848
 849	napi_gro_receive(&q_vector->napi, skb);
 850}
 851
 852/**
 853 * iavf_alloc_rx_buffers - Replace used receive buffers
 854 * @rx_ring: ring to place buffers on
 855 * @cleaned_count: number of buffers to replace
 856 *
 857 * Returns false if all allocations were successful, true if any fail
 858 **/
 859bool iavf_alloc_rx_buffers(struct iavf_ring *rx_ring, u16 cleaned_count)
 860{
 861	const struct libeth_fq_fp fq = {
 862		.pp		= rx_ring->pp,
 863		.fqes		= rx_ring->rx_fqes,
 864		.truesize	= rx_ring->truesize,
 865		.count		= rx_ring->count,
 866	};
 867	u16 ntu = rx_ring->next_to_use;
 868	struct iavf_rx_desc *rx_desc;
 869
 870	/* do nothing if no valid netdev defined */
 871	if (!rx_ring->netdev || !cleaned_count)
 872		return false;
 873
 874	rx_desc = IAVF_RX_DESC(rx_ring, ntu);
 875
 876	do {
 877		dma_addr_t addr;
 878
 879		addr = libeth_rx_alloc(&fq, ntu);
 880		if (addr == DMA_MAPPING_ERROR)
 881			goto no_buffers;
 882
 883		/* Refresh the desc even if buffer_addrs didn't change
 884		 * because each write-back erases this info.
 885		 */
 886		rx_desc->qw0 = cpu_to_le64(addr);
 887
 888		rx_desc++;
 889		ntu++;
 890		if (unlikely(ntu == rx_ring->count)) {
 891			rx_desc = IAVF_RX_DESC(rx_ring, 0);
 892			ntu = 0;
 893		}
 894
 895		/* clear the status bits for the next_to_use descriptor */
 896		rx_desc->qw1 = 0;
 897
 898		cleaned_count--;
 899	} while (cleaned_count);
 900
 901	if (rx_ring->next_to_use != ntu)
 902		iavf_release_rx_desc(rx_ring, ntu);
 903
 904	return false;
 905
 906no_buffers:
 907	if (rx_ring->next_to_use != ntu)
 908		iavf_release_rx_desc(rx_ring, ntu);
 909
 910	rx_ring->rx_stats.alloc_page_failed++;
 911
 912	/* make sure to come back via polling to try again after
 913	 * allocation failure
 914	 */
 915	return true;
 916}
 917
 918/**
 919 * iavf_rx_csum - Indicate in skb if hw indicated a good checksum
 920 * @vsi: the VSI we care about
 921 * @skb: skb currently being received and modified
 922 * @decoded_pt: decoded ptype information
 923 * @csum_bits: decoded Rx descriptor information
 924 **/
 925static void iavf_rx_csum(const struct iavf_vsi *vsi, struct sk_buff *skb,
 926			 struct libeth_rx_pt decoded_pt,
 927			 struct libeth_rx_csum csum_bits)
 928{
 929	bool ipv4, ipv6;
 930
 931	skb->ip_summed = CHECKSUM_NONE;
 932
 933	/* did the hardware decode the packet and checksum? */
 934	if (unlikely(!csum_bits.l3l4p))
 935		return;
 936
 937	ipv4 = libeth_rx_pt_get_ip_ver(decoded_pt) == LIBETH_RX_PT_OUTER_IPV4;
 938	ipv6 = libeth_rx_pt_get_ip_ver(decoded_pt) == LIBETH_RX_PT_OUTER_IPV6;
 939
 940	if (unlikely(ipv4 && (csum_bits.ipe || csum_bits.eipe)))
 941		goto checksum_fail;
 942
 943	/* likely incorrect csum if alternate IP extension headers found */
 944	if (unlikely(ipv6 && csum_bits.ipv6exadd))
 945		return;
 946
 947	/* there was some L4 error, count error and punt packet to the stack */
 948	if (unlikely(csum_bits.l4e))
 949		goto checksum_fail;
 950
 951	/* handle packets that were not able to be checksummed due
 952	 * to arrival speed, in this case the stack can compute
 953	 * the csum.
 954	 */
 955	if (unlikely(csum_bits.pprs))
 956		return;
 957
 958	skb->ip_summed = CHECKSUM_UNNECESSARY;
 959	return;
 960
 961checksum_fail:
 962	vsi->back->hw_csum_rx_error++;
 963}
 964
 965/**
 966 * iavf_legacy_rx_csum - Indicate in skb if hw indicated a good checksum
 967 * @vsi: the VSI we care about
 968 * @qw1: quad word 1
 969 * @decoded_pt: decoded packet type
 970 *
 971 * This function only operates on the VIRTCHNL_RXDID_1_32B_BASE legacy 32byte
 972 * descriptor writeback format.
 973 *
 974 * Return: decoded checksum bits.
 975 **/
 976static struct libeth_rx_csum
 977iavf_legacy_rx_csum(const struct iavf_vsi *vsi, u64 qw1,
 978		    const struct libeth_rx_pt decoded_pt)
 979{
 980	struct libeth_rx_csum csum_bits = {};
 981
 982	if (!libeth_rx_pt_has_checksum(vsi->netdev, decoded_pt))
 983		return csum_bits;
 984
 985	csum_bits.ipe = FIELD_GET(IAVF_RXD_LEGACY_IPE_M, qw1);
 986	csum_bits.eipe = FIELD_GET(IAVF_RXD_LEGACY_EIPE_M, qw1);
 987	csum_bits.l4e = FIELD_GET(IAVF_RXD_LEGACY_L4E_M, qw1);
 988	csum_bits.pprs = FIELD_GET(IAVF_RXD_LEGACY_PPRS_M, qw1);
 989	csum_bits.l3l4p = FIELD_GET(IAVF_RXD_LEGACY_L3L4P_M, qw1);
 990	csum_bits.ipv6exadd = FIELD_GET(IAVF_RXD_LEGACY_IPV6EXADD_M, qw1);
 991
 992	return csum_bits;
 993}
 994
 995/**
 996 * iavf_flex_rx_csum - Indicate in skb if hw indicated a good checksum
 997 * @vsi: the VSI we care about
 998 * @qw1: quad word 1
 999 * @decoded_pt: decoded packet type
1000 *
1001 * This function only operates on the VIRTCHNL_RXDID_2_FLEX_SQ_NIC flexible
1002 * descriptor writeback format.
1003 *
1004 * Return: decoded checksum bits.
1005 **/
1006static struct libeth_rx_csum
1007iavf_flex_rx_csum(const struct iavf_vsi *vsi, u64 qw1,
1008		  const struct libeth_rx_pt decoded_pt)
1009{
1010	struct libeth_rx_csum csum_bits = {};
1011
1012	if (!libeth_rx_pt_has_checksum(vsi->netdev, decoded_pt))
1013		return csum_bits;
1014
1015	csum_bits.ipe = FIELD_GET(IAVF_RXD_FLEX_XSUM_IPE_M, qw1);
1016	csum_bits.eipe = FIELD_GET(IAVF_RXD_FLEX_XSUM_EIPE_M, qw1);
1017	csum_bits.l4e = FIELD_GET(IAVF_RXD_FLEX_XSUM_L4E_M, qw1);
1018	csum_bits.eudpe = FIELD_GET(IAVF_RXD_FLEX_XSUM_EUDPE_M, qw1);
1019	csum_bits.l3l4p = FIELD_GET(IAVF_RXD_FLEX_L3L4P_M, qw1);
1020	csum_bits.ipv6exadd = FIELD_GET(IAVF_RXD_FLEX_IPV6EXADD_M, qw1);
1021	csum_bits.nat = FIELD_GET(IAVF_RXD_FLEX_NAT_M, qw1);
1022
1023	return csum_bits;
1024}
1025
1026/**
1027 * iavf_legacy_rx_hash - set the hash value in the skb
1028 * @ring: descriptor ring
1029 * @qw0: quad word 0
1030 * @qw1: quad word 1
1031 * @skb: skb currently being received and modified
1032 * @decoded_pt: decoded packet type
1033 *
1034 * This function only operates on the VIRTCHNL_RXDID_1_32B_BASE legacy 32byte
1035 * descriptor writeback format.
1036 **/
1037static void iavf_legacy_rx_hash(const struct iavf_ring *ring, __le64 qw0,
1038				__le64 qw1, struct sk_buff *skb,
1039				const struct libeth_rx_pt decoded_pt)
1040{
1041	const __le64 rss_mask = cpu_to_le64(IAVF_RXD_LEGACY_FLTSTAT_M);
1042	u32 hash;
1043
1044	if (!libeth_rx_pt_has_hash(ring->netdev, decoded_pt))
1045		return;
1046
1047	if ((qw1 & rss_mask) == rss_mask) {
1048		hash = le64_get_bits(qw0, IAVF_RXD_LEGACY_RSS_M);
1049		libeth_rx_pt_set_hash(skb, hash, decoded_pt);
1050	}
1051}
1052
1053/**
1054 * iavf_flex_rx_hash - set the hash value in the skb
1055 * @ring: descriptor ring
1056 * @qw1: quad word 1
1057 * @skb: skb currently being received and modified
1058 * @decoded_pt: decoded packet type
1059 *
1060 * This function only operates on the VIRTCHNL_RXDID_2_FLEX_SQ_NIC flexible
1061 * descriptor writeback format.
1062 **/
1063static void iavf_flex_rx_hash(const struct iavf_ring *ring, __le64 qw1,
1064			      struct sk_buff *skb,
1065			      const struct libeth_rx_pt decoded_pt)
1066{
1067	bool rss_valid;
1068	u32 hash;
1069
1070	if (!libeth_rx_pt_has_hash(ring->netdev, decoded_pt))
1071		return;
1072
1073	rss_valid = le64_get_bits(qw1, IAVF_RXD_FLEX_RSS_VALID_M);
1074	if (rss_valid) {
1075		hash = le64_get_bits(qw1, IAVF_RXD_FLEX_RSS_HASH_M);
1076		libeth_rx_pt_set_hash(skb, hash, decoded_pt);
1077	}
1078}
1079
1080/**
1081 * iavf_flex_rx_tstamp - Capture Rx timestamp from the descriptor
1082 * @rx_ring: descriptor ring
1083 * @qw2: quad word 2 of descriptor
1084 * @qw3: quad word 3 of descriptor
1085 * @skb: skb currently being received
1086 *
1087 * Read the Rx timestamp value from the descriptor and pass it to the stack.
1088 *
1089 * This function only operates on the VIRTCHNL_RXDID_2_FLEX_SQ_NIC flexible
1090 * descriptor writeback format.
1091 */
1092static void iavf_flex_rx_tstamp(const struct iavf_ring *rx_ring, __le64 qw2,
1093				__le64 qw3, struct sk_buff *skb)
1094{
1095	u32 tstamp;
1096	u64 ns;
1097
1098	/* Skip processing if timestamps aren't enabled */
1099	if (!(rx_ring->flags & IAVF_TXRX_FLAGS_HW_TSTAMP))
1100		return;
1101
1102	/* Check if this Rx descriptor has a valid timestamp */
1103	if (!le64_get_bits(qw2, IAVF_PTP_40B_TSTAMP_VALID))
1104		return;
1105
1106	/* the ts_low field only contains the valid bit and sub-nanosecond
1107	 * precision, so we don't need to extract it.
1108	 */
1109	tstamp = le64_get_bits(qw3, IAVF_RXD_FLEX_QW3_TSTAMP_HIGH_M);
1110
1111	ns = iavf_ptp_extend_32b_timestamp(rx_ring->ptp->cached_phc_time,
1112					   tstamp);
1113
1114	*skb_hwtstamps(skb) = (struct skb_shared_hwtstamps) {
1115		.hwtstamp = ns_to_ktime(ns),
1116	};
1117}
1118
1119/**
1120 * iavf_process_skb_fields - Populate skb header fields from Rx descriptor
1121 * @rx_ring: rx descriptor ring packet is being transacted on
1122 * @rx_desc: pointer to the EOP Rx descriptor
1123 * @skb: pointer to current skb being populated
1124 * @ptype: the packet type decoded by hardware
1125 * @flex: is the descriptor flex or legacy
1126 *
1127 * This function checks the ring, descriptor, and packet information in
1128 * order to populate the hash, checksum, VLAN, protocol, and
1129 * other fields within the skb.
1130 **/
1131static void iavf_process_skb_fields(const struct iavf_ring *rx_ring,
1132				    const struct iavf_rx_desc *rx_desc,
1133				    struct sk_buff *skb, u32 ptype,
1134				    bool flex)
1135{
1136	struct libeth_rx_csum csum_bits;
1137	struct libeth_rx_pt decoded_pt;
1138	__le64 qw0 = rx_desc->qw0;
1139	__le64 qw1 = rx_desc->qw1;
1140	__le64 qw2 = rx_desc->qw2;
1141	__le64 qw3 = rx_desc->qw3;
1142
1143	decoded_pt = libie_rx_pt_parse(ptype);
1144
1145	if (flex) {
1146		iavf_flex_rx_hash(rx_ring, qw1, skb, decoded_pt);
1147		iavf_flex_rx_tstamp(rx_ring, qw2, qw3, skb);
1148		csum_bits = iavf_flex_rx_csum(rx_ring->vsi, le64_to_cpu(qw1),
1149					      decoded_pt);
1150	} else {
1151		iavf_legacy_rx_hash(rx_ring, qw0, qw1, skb, decoded_pt);
1152		csum_bits = iavf_legacy_rx_csum(rx_ring->vsi, le64_to_cpu(qw1),
1153						decoded_pt);
1154	}
1155	iavf_rx_csum(rx_ring->vsi, skb, decoded_pt, csum_bits);
1156
1157	skb_record_rx_queue(skb, rx_ring->queue_index);
1158
1159	/* modifies the skb - consumes the enet header */
1160	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1161}
1162
1163/**
1164 * iavf_cleanup_headers - Correct empty headers
1165 * @rx_ring: rx descriptor ring packet is being transacted on
1166 * @skb: pointer to current skb being fixed
1167 *
1168 * Also address the case where we are pulling data in on pages only
1169 * and as such no data is present in the skb header.
1170 *
1171 * In addition if skb is not at least 60 bytes we need to pad it so that
1172 * it is large enough to qualify as a valid Ethernet frame.
1173 *
1174 * Returns true if an error was encountered and skb was freed.
1175 **/
1176static bool iavf_cleanup_headers(struct iavf_ring *rx_ring, struct sk_buff *skb)
1177{
1178	/* if eth_skb_pad returns an error the skb was freed */
1179	if (eth_skb_pad(skb))
1180		return true;
1181
1182	return false;
1183}
1184
1185/**
1186 * iavf_add_rx_frag - Add contents of Rx buffer to sk_buff
1187 * @skb: sk_buff to place the data into
1188 * @rx_buffer: buffer containing page to add
1189 * @size: packet length from rx_desc
1190 *
1191 * This function will add the data contained in rx_buffer->page to the skb.
1192 * It will just attach the page as a frag to the skb.
1193 *
1194 * The function will then update the page offset.
1195 **/
1196static void iavf_add_rx_frag(struct sk_buff *skb,
1197			     const struct libeth_fqe *rx_buffer,
1198			     unsigned int size)
1199{
1200	u32 hr = netmem_get_pp(rx_buffer->netmem)->p.offset;
1201
1202	skb_add_rx_frag_netmem(skb, skb_shinfo(skb)->nr_frags,
1203			       rx_buffer->netmem, rx_buffer->offset + hr,
1204			       size, rx_buffer->truesize);
1205}
1206
1207/**
1208 * iavf_build_skb - Build skb around an existing buffer
1209 * @rx_buffer: Rx buffer to pull data from
1210 * @size: size of buffer to add to skb
1211 *
1212 * This function builds an skb around an existing Rx buffer, taking care
1213 * to set up the skb correctly and avoid any memcpy overhead.
1214 */
1215static struct sk_buff *iavf_build_skb(const struct libeth_fqe *rx_buffer,
1216				      unsigned int size)
1217{
1218	struct page *buf_page = __netmem_to_page(rx_buffer->netmem);
1219	u32 hr = pp_page_to_nmdesc(buf_page)->pp->p.offset;
1220	struct sk_buff *skb;
1221	void *va;
1222
1223	/* prefetch first cache line of first page */
1224	va = page_address(buf_page) + rx_buffer->offset;
1225	net_prefetch(va + hr);
1226
1227	/* build an skb around the page buffer */
1228	skb = napi_build_skb(va, rx_buffer->truesize);
1229	if (unlikely(!skb))
1230		return NULL;
1231
1232	skb_mark_for_recycle(skb);
1233
1234	/* update pointers within the skb to store the data */
1235	skb_reserve(skb, hr);
1236	__skb_put(skb, size);
1237
1238	return skb;
1239}
1240
1241/**
1242 * iavf_is_non_eop - process handling of non-EOP buffers
1243 * @rx_ring: Rx ring being processed
1244 * @fields: Rx descriptor extracted fields
1245 *
1246 * This function updates next to clean.  If the buffer is an EOP buffer
1247 * this function exits returning false, otherwise it will place the
1248 * sk_buff in the next buffer to be chained and return true indicating
1249 * that this is in fact a non-EOP buffer.
1250 **/
1251static bool iavf_is_non_eop(struct iavf_ring *rx_ring,
1252			    struct libeth_rqe_info fields)
1253{
1254	u32 ntc = rx_ring->next_to_clean + 1;
1255
1256	/* fetch, update, and store next to clean */
1257	ntc = (ntc < rx_ring->count) ? ntc : 0;
1258	rx_ring->next_to_clean = ntc;
1259
1260	prefetch(IAVF_RX_DESC(rx_ring, ntc));
1261
1262	/* if we are the last buffer then there is nothing else to do */
1263	if (likely(fields.eop))
1264		return false;
1265
1266	rx_ring->rx_stats.non_eop_descs++;
1267
1268	return true;
1269}
1270
1271/**
1272 * iavf_extract_legacy_rx_fields - Extract fields from the Rx descriptor
1273 * @rx_ring: rx descriptor ring
1274 * @rx_desc: the descriptor to process
1275 *
1276 * Decode the Rx descriptor and extract relevant information including the
1277 * size, VLAN tag, Rx packet type, end of packet field and RXE field value.
1278 *
1279 * This function only operates on the VIRTCHNL_RXDID_1_32B_BASE legacy 32byte
1280 * descriptor writeback format.
1281 *
1282 * Return: fields extracted from the Rx descriptor.
1283 */
1284static struct libeth_rqe_info
1285iavf_extract_legacy_rx_fields(const struct iavf_ring *rx_ring,
1286			      const struct iavf_rx_desc *rx_desc)
1287{
1288	u64 qw0 = le64_to_cpu(rx_desc->qw0);
1289	u64 qw1 = le64_to_cpu(rx_desc->qw1);
1290	u64 qw2 = le64_to_cpu(rx_desc->qw2);
1291	struct libeth_rqe_info fields;
1292	bool l2tag1p, l2tag2p;
1293
1294	fields.eop = FIELD_GET(IAVF_RXD_LEGACY_EOP_M, qw1);
1295	fields.len = FIELD_GET(IAVF_RXD_LEGACY_LENGTH_M, qw1);
1296
1297	if (!fields.eop)
1298		return fields;
1299
1300	fields.rxe = FIELD_GET(IAVF_RXD_LEGACY_RXE_M, qw1);
1301	fields.ptype = FIELD_GET(IAVF_RXD_LEGACY_PTYPE_M, qw1);
1302	fields.vlan = 0;
1303
1304	if (rx_ring->flags & IAVF_TXRX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
1305		l2tag1p = FIELD_GET(IAVF_RXD_LEGACY_L2TAG1P_M, qw1);
1306		if (l2tag1p)
1307			fields.vlan = FIELD_GET(IAVF_RXD_LEGACY_L2TAG1_M, qw0);
1308	} else if (rx_ring->flags & IAVF_RXR_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1309		l2tag2p = FIELD_GET(IAVF_RXD_LEGACY_L2TAG2P_M, qw2);
1310		if (l2tag2p)
1311			fields.vlan = FIELD_GET(IAVF_RXD_LEGACY_L2TAG2_M, qw2);
1312	}
1313
1314	return fields;
1315}
1316
1317/**
1318 * iavf_extract_flex_rx_fields - Extract fields from the Rx descriptor
1319 * @rx_ring: rx descriptor ring
1320 * @rx_desc: the descriptor to process
1321 *
1322 * Decode the Rx descriptor and extract relevant information including the
1323 * size, VLAN tag, Rx packet type, end of packet field and RXE field value.
1324 *
1325 * This function only operates on the VIRTCHNL_RXDID_2_FLEX_SQ_NIC flexible
1326 * descriptor writeback format.
1327 *
1328 * Return: fields extracted from the Rx descriptor.
1329 */
1330static struct libeth_rqe_info
1331iavf_extract_flex_rx_fields(const struct iavf_ring *rx_ring,
1332			    const struct iavf_rx_desc *rx_desc)
1333{
1334	struct libeth_rqe_info fields = {};
1335	u64 qw0 = le64_to_cpu(rx_desc->qw0);
1336	u64 qw1 = le64_to_cpu(rx_desc->qw1);
1337	u64 qw2 = le64_to_cpu(rx_desc->qw2);
1338	bool l2tag1p, l2tag2p;
1339
1340	fields.eop = FIELD_GET(IAVF_RXD_FLEX_EOP_M, qw1);
1341	fields.len = FIELD_GET(IAVF_RXD_FLEX_PKT_LEN_M, qw0);
1342
1343	if (!fields.eop)
1344		return fields;
1345
1346	fields.rxe = FIELD_GET(IAVF_RXD_FLEX_RXE_M, qw1);
1347	fields.ptype = FIELD_GET(IAVF_RXD_FLEX_PTYPE_M, qw0);
1348	fields.vlan = 0;
1349
1350	if (rx_ring->flags & IAVF_TXRX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
1351		l2tag1p = FIELD_GET(IAVF_RXD_FLEX_L2TAG1P_M, qw1);
1352		if (l2tag1p)
1353			fields.vlan = FIELD_GET(IAVF_RXD_FLEX_L2TAG1_M, qw1);
1354	} else if (rx_ring->flags & IAVF_RXR_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1355		l2tag2p = FIELD_GET(IAVF_RXD_FLEX_L2TAG2P_M, qw2);
1356		if (l2tag2p)
1357			fields.vlan = FIELD_GET(IAVF_RXD_FLEX_L2TAG2_2_M, qw2);
1358	}
1359
1360	return fields;
1361}
1362
1363static struct libeth_rqe_info
1364iavf_extract_rx_fields(const struct iavf_ring *rx_ring,
1365		       const struct iavf_rx_desc *rx_desc,
1366		       bool flex)
1367{
1368	if (flex)
1369		return iavf_extract_flex_rx_fields(rx_ring, rx_desc);
1370	else
1371		return iavf_extract_legacy_rx_fields(rx_ring, rx_desc);
1372}
1373
1374/**
1375 * iavf_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1376 * @rx_ring: rx descriptor ring to transact packets on
1377 * @budget: Total limit on number of packets to process
1378 *
1379 * This function provides a "bounce buffer" approach to Rx interrupt
1380 * processing.  The advantage to this is that on systems that have
1381 * expensive overhead for IOMMU access this provides a means of avoiding
1382 * it by maintaining the mapping of the page to the system.
1383 *
1384 * Returns amount of work completed
1385 **/
1386static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget)
1387{
1388	bool flex = rx_ring->rxdid == VIRTCHNL_RXDID_2_FLEX_SQ_NIC;
1389	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1390	struct sk_buff *skb = rx_ring->skb;
1391	u16 cleaned_count = IAVF_DESC_UNUSED(rx_ring);
1392	bool failure = false;
1393
1394	while (likely(total_rx_packets < (unsigned int)budget)) {
1395		struct libeth_rqe_info fields;
1396		struct libeth_fqe *rx_buffer;
1397		struct iavf_rx_desc *rx_desc;
1398		u64 qw1;
1399
1400		/* return some buffers to hardware, one at a time is too slow */
1401		if (cleaned_count >= IAVF_RX_BUFFER_WRITE) {
1402			failure = failure ||
1403				  iavf_alloc_rx_buffers(rx_ring, cleaned_count);
1404			cleaned_count = 0;
1405		}
1406
1407		rx_desc = IAVF_RX_DESC(rx_ring, rx_ring->next_to_clean);
1408
1409		/* This memory barrier is needed to keep us from reading
1410		 * any other fields out of the rx_desc until we have
1411		 * verified the descriptor has been written back.
1412		 */
1413		dma_rmb();
1414
1415		qw1 = le64_to_cpu(rx_desc->qw1);
1416		/* If DD field (descriptor done) is unset then other fields are
1417		 * not valid
1418		 */
1419		if (!iavf_is_descriptor_done(qw1, flex))
1420			break;
1421
1422		fields = iavf_extract_rx_fields(rx_ring, rx_desc, flex);
1423
1424		iavf_trace(clean_rx_irq, rx_ring, rx_desc, skb);
1425
1426		rx_buffer = &rx_ring->rx_fqes[rx_ring->next_to_clean];
1427		if (!libeth_rx_sync_for_cpu(rx_buffer, fields.len))
1428			goto skip_data;
1429
1430		/* retrieve a buffer from the ring */
1431		if (skb)
1432			iavf_add_rx_frag(skb, rx_buffer, fields.len);
1433		else
1434			skb = iavf_build_skb(rx_buffer, fields.len);
1435
1436		/* exit if we failed to retrieve a buffer */
1437		if (!skb) {
1438			rx_ring->rx_stats.alloc_buff_failed++;
1439			break;
1440		}
1441
1442skip_data:
1443		cleaned_count++;
1444
1445		if (iavf_is_non_eop(rx_ring, fields) || unlikely(!skb))
1446			continue;
1447
1448		/* RXE field in descriptor is an indication of the MAC errors
1449		 * (like CRC, alignment, oversize etc). If it is set then iavf
1450		 * should finish.
1451		 */
1452		if (unlikely(fields.rxe)) {
1453			dev_kfree_skb_any(skb);
1454			skb = NULL;
1455			continue;
1456		}
1457
1458		if (iavf_cleanup_headers(rx_ring, skb)) {
1459			skb = NULL;
1460			continue;
1461		}
1462
1463		/* probably a little skewed due to removing CRC */
1464		total_rx_bytes += skb->len;
1465
1466		/* populate checksum, VLAN, and protocol */
1467		iavf_process_skb_fields(rx_ring, rx_desc, skb, fields.ptype, flex);
1468
1469		iavf_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
1470		iavf_receive_skb(rx_ring, skb, fields.vlan);
1471		skb = NULL;
1472
1473		/* update budget accounting */
1474		total_rx_packets++;
1475	}
1476
1477	rx_ring->skb = skb;
1478
1479	u64_stats_update_begin(&rx_ring->syncp);
1480	rx_ring->stats.packets += total_rx_packets;
1481	rx_ring->stats.bytes += total_rx_bytes;
1482	u64_stats_update_end(&rx_ring->syncp);
1483	rx_ring->q_vector->rx.total_packets += total_rx_packets;
1484	rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1485
1486	/* guarantee a trip back through this routine if there was a failure */
1487	return failure ? budget : (int)total_rx_packets;
1488}
1489
1490static inline u32 iavf_buildreg_itr(const int type, u16 itr)
1491{
1492	u32 val;
1493
1494	/* We don't bother with setting the CLEARPBA bit as the data sheet
1495	 * points out doing so is "meaningless since it was already
1496	 * auto-cleared". The auto-clearing happens when the interrupt is
1497	 * asserted.
1498	 *
1499	 * Hardware errata 28 for also indicates that writing to a
1500	 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
1501	 * an event in the PBA anyway so we need to rely on the automask
1502	 * to hold pending events for us until the interrupt is re-enabled
1503	 *
1504	 * The itr value is reported in microseconds, and the register
1505	 * value is recorded in 2 microsecond units. For this reason we
1506	 * only need to shift by the interval shift - 1 instead of the
1507	 * full value.
1508	 */
1509	itr &= IAVF_ITR_MASK;
1510
1511	val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
1512	      (type << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1513	      (itr << (IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT - 1));
1514
1515	return val;
1516}
1517
1518/* a small macro to shorten up some long lines */
1519#define INTREG IAVF_VFINT_DYN_CTLN1
1520
1521/* The act of updating the ITR will cause it to immediately trigger. In order
1522 * to prevent this from throwing off adaptive update statistics we defer the
1523 * update so that it can only happen so often. So after either Tx or Rx are
1524 * updated we make the adaptive scheme wait until either the ITR completely
1525 * expires via the next_update expiration or we have been through at least
1526 * 3 interrupts.
1527 */
1528#define ITR_COUNTDOWN_START 3
1529
1530/**
1531 * iavf_update_enable_itr - Update itr and re-enable MSIX interrupt
1532 * @vsi: the VSI we care about
1533 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1534 *
1535 **/
1536static void iavf_update_enable_itr(struct iavf_vsi *vsi,
1537				   struct iavf_q_vector *q_vector)
1538{
1539	struct iavf_hw *hw = &vsi->back->hw;
1540	u32 intval;
1541
1542	/* These will do nothing if dynamic updates are not enabled */
1543	iavf_update_itr(q_vector, &q_vector->tx);
1544	iavf_update_itr(q_vector, &q_vector->rx);
1545
1546	/* This block of logic allows us to get away with only updating
1547	 * one ITR value with each interrupt. The idea is to perform a
1548	 * pseudo-lazy update with the following criteria.
1549	 *
1550	 * 1. Rx is given higher priority than Tx if both are in same state
1551	 * 2. If we must reduce an ITR that is given highest priority.
1552	 * 3. We then give priority to increasing ITR based on amount.
1553	 */
1554	if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
1555		/* Rx ITR needs to be reduced, this is highest priority */
1556		intval = iavf_buildreg_itr(IAVF_RX_ITR,
1557					   q_vector->rx.target_itr);
1558		q_vector->rx.current_itr = q_vector->rx.target_itr;
1559		q_vector->itr_countdown = ITR_COUNTDOWN_START;
1560	} else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
1561		   ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
1562		    (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
1563		/* Tx ITR needs to be reduced, this is second priority
1564		 * Tx ITR needs to be increased more than Rx, fourth priority
1565		 */
1566		intval = iavf_buildreg_itr(IAVF_TX_ITR,
1567					   q_vector->tx.target_itr);
1568		q_vector->tx.current_itr = q_vector->tx.target_itr;
1569		q_vector->itr_countdown = ITR_COUNTDOWN_START;
1570	} else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
1571		/* Rx ITR needs to be increased, third priority */
1572		intval = iavf_buildreg_itr(IAVF_RX_ITR,
1573					   q_vector->rx.target_itr);
1574		q_vector->rx.current_itr = q_vector->rx.target_itr;
1575		q_vector->itr_countdown = ITR_COUNTDOWN_START;
1576	} else {
1577		/* No ITR update, lowest priority */
1578		intval = iavf_buildreg_itr(IAVF_ITR_NONE, 0);
1579		if (q_vector->itr_countdown)
1580			q_vector->itr_countdown--;
1581	}
1582
1583	if (!test_bit(__IAVF_VSI_DOWN, vsi->state))
1584		wr32(hw, INTREG(q_vector->reg_idx), intval);
1585}
1586
1587/**
1588 * iavf_napi_poll - NAPI polling Rx/Tx cleanup routine
1589 * @napi: napi struct with our devices info in it
1590 * @budget: amount of work driver is allowed to do this pass, in packets
1591 *
1592 * This function will clean all queues associated with a q_vector.
1593 *
1594 * Returns the amount of work done
1595 **/
1596int iavf_napi_poll(struct napi_struct *napi, int budget)
1597{
1598	struct iavf_q_vector *q_vector =
1599			       container_of(napi, struct iavf_q_vector, napi);
1600	struct iavf_vsi *vsi = q_vector->vsi;
1601	struct iavf_ring *ring;
1602	bool clean_complete = true;
1603	bool arm_wb = false;
1604	int budget_per_ring;
1605	int work_done = 0;
1606
1607	if (test_bit(__IAVF_VSI_DOWN, vsi->state)) {
1608		napi_complete(napi);
1609		return 0;
1610	}
1611
1612	/* Since the actual Tx work is minimal, we can give the Tx a larger
1613	 * budget and be more aggressive about cleaning up the Tx descriptors.
1614	 */
1615	iavf_for_each_ring(ring, q_vector->tx) {
1616		if (!iavf_clean_tx_irq(vsi, ring, budget)) {
1617			clean_complete = false;
1618			continue;
1619		}
1620		arm_wb |= !!(ring->flags & IAVF_TXR_FLAGS_ARM_WB);
1621		ring->flags &= ~IAVF_TXR_FLAGS_ARM_WB;
1622	}
1623
1624	/* Handle case where we are called by netpoll with a budget of 0 */
1625	if (budget <= 0)
1626		goto tx_only;
1627
1628	/* We attempt to distribute budget to each Rx queue fairly, but don't
1629	 * allow the budget to go below 1 because that would exit polling early.
1630	 */
1631	budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1632
1633	iavf_for_each_ring(ring, q_vector->rx) {
1634		int cleaned = iavf_clean_rx_irq(ring, budget_per_ring);
1635
1636		work_done += cleaned;
1637		/* if we clean as many as budgeted, we must not be done */
1638		if (cleaned >= budget_per_ring)
1639			clean_complete = false;
1640	}
1641
1642	/* If work not completed, return budget and polling will return */
1643	if (!clean_complete) {
1644		int cpu_id = smp_processor_id();
1645
1646		/* It is possible that the interrupt affinity has changed but,
1647		 * if the cpu is pegged at 100%, polling will never exit while
1648		 * traffic continues and the interrupt will be stuck on this
1649		 * cpu.  We check to make sure affinity is correct before we
1650		 * continue to poll, otherwise we must stop polling so the
1651		 * interrupt can move to the correct cpu.
1652		 */
1653		if (!cpumask_test_cpu(cpu_id,
1654				      &q_vector->napi.config->affinity_mask)) {
1655			/* Tell napi that we are done polling */
1656			napi_complete_done(napi, work_done);
1657
1658			/* Force an interrupt */
1659			iavf_force_wb(vsi, q_vector);
1660
1661			/* Return budget-1 so that polling stops */
1662			return budget - 1;
1663		}
1664tx_only:
1665		if (arm_wb) {
1666			q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1667			iavf_enable_wb_on_itr(vsi, q_vector);
1668		}
1669		return budget;
1670	}
1671
1672	if (vsi->back->flags & IAVF_TXR_FLAGS_WB_ON_ITR)
1673		q_vector->arm_wb_state = false;
1674
1675	/* Exit the polling mode, but don't re-enable interrupts if stack might
1676	 * poll us due to busy-polling
1677	 */
1678	if (likely(napi_complete_done(napi, work_done)))
1679		iavf_update_enable_itr(vsi, q_vector);
1680
1681	return min_t(int, work_done, budget - 1);
1682}
1683
1684/**
1685 * iavf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1686 * @skb:     send buffer
1687 * @tx_ring: ring to send buffer on
1688 * @flags:   the tx flags to be set
1689 *
1690 * Checks the skb and set up correspondingly several generic transmit flags
1691 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1692 *
1693 * Returns error code indicate the frame should be dropped upon error and the
1694 * otherwise  returns 0 to indicate the flags has been set properly.
1695 **/
1696static void iavf_tx_prepare_vlan_flags(struct sk_buff *skb,
1697				       struct iavf_ring *tx_ring, u32 *flags)
1698{
1699	u32  tx_flags = 0;
1700
1701
1702	/* stack will only request hardware VLAN insertion offload for protocols
1703	 * that the driver supports and has enabled
1704	 */
1705	if (!skb_vlan_tag_present(skb))
1706		return;
1707
1708	tx_flags |= skb_vlan_tag_get(skb) << IAVF_TX_FLAGS_VLAN_SHIFT;
1709	if (tx_ring->flags & IAVF_TXR_FLAGS_VLAN_TAG_LOC_L2TAG2) {
1710		tx_flags |= IAVF_TX_FLAGS_HW_OUTER_SINGLE_VLAN;
1711	} else if (tx_ring->flags & IAVF_TXRX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
1712		tx_flags |= IAVF_TX_FLAGS_HW_VLAN;
1713	} else {
1714		dev_dbg(tx_ring->dev, "Unsupported Tx VLAN tag location requested\n");
1715		return;
1716	}
1717
1718	*flags = tx_flags;
1719}
1720
1721/**
1722 * iavf_tso - set up the tso context descriptor
1723 * @first:    pointer to first Tx buffer for xmit
1724 * @hdr_len:  ptr to the size of the packet header
1725 * @cd_type_cmd_tso_mss: Quad Word 1
1726 *
1727 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1728 **/
1729static int iavf_tso(struct iavf_tx_buffer *first, u8 *hdr_len,
1730		    u64 *cd_type_cmd_tso_mss)
1731{
1732	struct sk_buff *skb = first->skb;
1733	u64 cd_cmd, cd_tso_len, cd_mss;
1734	union {
1735		struct iphdr *v4;
1736		struct ipv6hdr *v6;
1737		unsigned char *hdr;
1738	} ip;
1739	union {
1740		struct tcphdr *tcp;
1741		struct udphdr *udp;
1742		unsigned char *hdr;
1743	} l4;
1744	u32 paylen, l4_offset;
1745	u16 gso_segs, gso_size;
1746	int err;
1747
1748	if (skb->ip_summed != CHECKSUM_PARTIAL)
1749		return 0;
1750
1751	if (!skb_is_gso(skb))
1752		return 0;
1753
1754	err = skb_cow_head(skb, 0);
1755	if (err < 0)
1756		return err;
1757
1758	ip.hdr = skb_network_header(skb);
1759	l4.hdr = skb_transport_header(skb);
1760
1761	/* initialize outer IP header fields */
1762	if (ip.v4->version == 4) {
1763		ip.v4->tot_len = 0;
1764		ip.v4->check = 0;
1765	} else {
1766		ip.v6->payload_len = 0;
1767	}
1768
1769	if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1770					 SKB_GSO_GRE_CSUM |
1771					 SKB_GSO_IPXIP4 |
1772					 SKB_GSO_IPXIP6 |
1773					 SKB_GSO_UDP_TUNNEL |
1774					 SKB_GSO_UDP_TUNNEL_CSUM)) {
1775		if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1776		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
1777			l4.udp->len = 0;
1778
1779			/* determine offset of outer transport header */
1780			l4_offset = l4.hdr - skb->data;
1781
1782			/* remove payload length from outer checksum */
1783			paylen = skb->len - l4_offset;
1784			csum_replace_by_diff(&l4.udp->check,
1785					     (__force __wsum)htonl(paylen));
1786		}
1787
1788		/* reset pointers to inner headers */
1789		ip.hdr = skb_inner_network_header(skb);
1790		l4.hdr = skb_inner_transport_header(skb);
1791
1792		/* initialize inner IP header fields */
1793		if (ip.v4->version == 4) {
1794			ip.v4->tot_len = 0;
1795			ip.v4->check = 0;
1796		} else {
1797			ip.v6->payload_len = 0;
1798		}
1799	}
1800
1801	/* determine offset of inner transport header */
1802	l4_offset = l4.hdr - skb->data;
1803	/* remove payload length from inner checksum */
1804	paylen = skb->len - l4_offset;
1805
1806	if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1807		csum_replace_by_diff(&l4.udp->check,
1808				     (__force __wsum)htonl(paylen));
1809		/* compute length of UDP segmentation header */
1810		*hdr_len = (u8)sizeof(l4.udp) + l4_offset;
1811	} else {
1812		csum_replace_by_diff(&l4.tcp->check,
1813				     (__force __wsum)htonl(paylen));
1814		/* compute length of TCP segmentation header */
1815		*hdr_len = (u8)((l4.tcp->doff * 4) + l4_offset);
1816	}
1817
1818	/* pull values out of skb_shinfo */
1819	gso_size = skb_shinfo(skb)->gso_size;
1820	gso_segs = skb_shinfo(skb)->gso_segs;
1821
1822	/* update GSO size and bytecount with header size */
1823	first->gso_segs = gso_segs;
1824	first->bytecount += (first->gso_segs - 1) * *hdr_len;
1825
1826	/* find the field values */
1827	cd_cmd = IAVF_TX_CTX_DESC_TSO;
1828	cd_tso_len = skb->len - *hdr_len;
1829	cd_mss = gso_size;
1830	*cd_type_cmd_tso_mss |= (cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
1831				(cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1832				(cd_mss << IAVF_TXD_CTX_QW1_MSS_SHIFT);
1833	return 1;
1834}
1835
1836/**
1837 * iavf_tx_enable_csum - Enable Tx checksum offloads
1838 * @skb: send buffer
1839 * @tx_flags: pointer to Tx flags currently set
1840 * @td_cmd: Tx descriptor command bits to set
1841 * @td_offset: Tx descriptor header offsets to set
1842 * @tx_ring: Tx descriptor ring
1843 * @cd_tunneling: ptr to context desc bits
1844 **/
1845static int iavf_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1846			       u32 *td_cmd, u32 *td_offset,
1847			       struct iavf_ring *tx_ring,
1848			       u32 *cd_tunneling)
1849{
1850	union {
1851		struct iphdr *v4;
1852		struct ipv6hdr *v6;
1853		unsigned char *hdr;
1854	} ip;
1855	union {
1856		struct tcphdr *tcp;
1857		struct udphdr *udp;
1858		unsigned char *hdr;
1859	} l4;
1860	unsigned char *exthdr;
1861	u32 offset, cmd = 0;
1862	__be16 frag_off;
1863	u8 l4_proto = 0;
1864
1865	if (skb->ip_summed != CHECKSUM_PARTIAL)
1866		return 0;
1867
1868	ip.hdr = skb_network_header(skb);
1869	l4.hdr = skb_transport_header(skb);
1870
1871	/* compute outer L2 header size */
1872	offset = ((ip.hdr - skb->data) / 2) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1873
1874	if (skb->encapsulation) {
1875		u32 tunnel = 0;
1876		/* define outer network header type */
1877		if (*tx_flags & IAVF_TX_FLAGS_IPV4) {
1878			tunnel |= (*tx_flags & IAVF_TX_FLAGS_TSO) ?
1879				  IAVF_TX_CTX_EXT_IP_IPV4 :
1880				  IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1881
1882			l4_proto = ip.v4->protocol;
1883		} else if (*tx_flags & IAVF_TX_FLAGS_IPV6) {
1884			tunnel |= IAVF_TX_CTX_EXT_IP_IPV6;
1885
1886			exthdr = ip.hdr + sizeof(*ip.v6);
1887			l4_proto = ip.v6->nexthdr;
1888			if (l4.hdr != exthdr)
1889				ipv6_skip_exthdr(skb, exthdr - skb->data,
1890						 &l4_proto, &frag_off);
1891		}
1892
1893		/* define outer transport */
1894		switch (l4_proto) {
1895		case IPPROTO_UDP:
1896			tunnel |= IAVF_TXD_CTX_UDP_TUNNELING;
1897			*tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL;
1898			break;
1899		case IPPROTO_GRE:
1900			tunnel |= IAVF_TXD_CTX_GRE_TUNNELING;
1901			*tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL;
1902			break;
1903		case IPPROTO_IPIP:
1904		case IPPROTO_IPV6:
1905			*tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL;
1906			l4.hdr = skb_inner_network_header(skb);
1907			break;
1908		default:
1909			if (*tx_flags & IAVF_TX_FLAGS_TSO)
1910				return -1;
1911
1912			skb_checksum_help(skb);
1913			return 0;
1914		}
1915
1916		/* compute outer L3 header size */
1917		tunnel |= ((l4.hdr - ip.hdr) / 4) <<
1918			  IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
1919
1920		/* switch IP header pointer from outer to inner header */
1921		ip.hdr = skb_inner_network_header(skb);
1922
1923		/* compute tunnel header size */
1924		tunnel |= ((ip.hdr - l4.hdr) / 2) <<
1925			  IAVF_TXD_CTX_QW0_NATLEN_SHIFT;
1926
1927		/* indicate if we need to offload outer UDP header */
1928		if ((*tx_flags & IAVF_TX_FLAGS_TSO) &&
1929		    !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1930		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
1931			tunnel |= IAVF_TXD_CTX_QW0_L4T_CS_MASK;
1932
1933		/* record tunnel offload values */
1934		*cd_tunneling |= tunnel;
1935
1936		/* switch L4 header pointer from outer to inner */
1937		l4.hdr = skb_inner_transport_header(skb);
1938		l4_proto = 0;
1939
1940		/* reset type as we transition from outer to inner headers */
1941		*tx_flags &= ~(IAVF_TX_FLAGS_IPV4 | IAVF_TX_FLAGS_IPV6);
1942		if (ip.v4->version == 4)
1943			*tx_flags |= IAVF_TX_FLAGS_IPV4;
1944		if (ip.v6->version == 6)
1945			*tx_flags |= IAVF_TX_FLAGS_IPV6;
1946	}
1947
1948	/* Enable IP checksum offloads */
1949	if (*tx_flags & IAVF_TX_FLAGS_IPV4) {
1950		l4_proto = ip.v4->protocol;
1951		/* the stack computes the IP header already, the only time we
1952		 * need the hardware to recompute it is in the case of TSO.
1953		 */
1954		cmd |= (*tx_flags & IAVF_TX_FLAGS_TSO) ?
1955		       IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM :
1956		       IAVF_TX_DESC_CMD_IIPT_IPV4;
1957	} else if (*tx_flags & IAVF_TX_FLAGS_IPV6) {
1958		cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
1959
1960		exthdr = ip.hdr + sizeof(*ip.v6);
1961		l4_proto = ip.v6->nexthdr;
1962		if (l4.hdr != exthdr)
1963			ipv6_skip_exthdr(skb, exthdr - skb->data,
1964					 &l4_proto, &frag_off);
1965	}
1966
1967	/* compute inner L3 header size */
1968	offset |= ((l4.hdr - ip.hdr) / 4) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1969
1970	/* Enable L4 checksum offloads */
1971	switch (l4_proto) {
1972	case IPPROTO_TCP:
1973		/* enable checksum offloads */
1974		cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1975		offset |= l4.tcp->doff << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1976		break;
1977	case IPPROTO_SCTP:
1978		/* enable SCTP checksum offload */
1979		cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1980		offset |= (sizeof(struct sctphdr) >> 2) <<
1981			  IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1982		break;
1983	case IPPROTO_UDP:
1984		/* enable UDP checksum offload */
1985		cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
1986		offset |= (sizeof(struct udphdr) >> 2) <<
1987			  IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1988		break;
1989	default:
1990		if (*tx_flags & IAVF_TX_FLAGS_TSO)
1991			return -1;
1992		skb_checksum_help(skb);
1993		return 0;
1994	}
1995
1996	*td_cmd |= cmd;
1997	*td_offset |= offset;
1998
1999	return 1;
2000}
2001
2002/**
2003 * iavf_create_tx_ctx - Build the Tx context descriptor
2004 * @tx_ring:  ring to create the descriptor on
2005 * @cd_type_cmd_tso_mss: Quad Word 1
2006 * @cd_tunneling: Quad Word 0 - bits 0-31
2007 * @cd_l2tag2: Quad Word 0 - bits 32-63
2008 **/
2009static void iavf_create_tx_ctx(struct iavf_ring *tx_ring,
2010			       const u64 cd_type_cmd_tso_mss,
2011			       const u32 cd_tunneling, const u32 cd_l2tag2)
2012{
2013	struct iavf_tx_context_desc *context_desc;
2014	int i = tx_ring->next_to_use;
2015
2016	if ((cd_type_cmd_tso_mss == IAVF_TX_DESC_DTYPE_CONTEXT) &&
2017	    !cd_tunneling && !cd_l2tag2)
2018		return;
2019
2020	/* grab the next descriptor */
2021	context_desc = IAVF_TX_CTXTDESC(tx_ring, i);
2022
2023	i++;
2024	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2025
2026	/* cpu_to_le32 and assign to struct fields */
2027	context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2028	context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
2029	context_desc->rsvd = cpu_to_le16(0);
2030	context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2031}
2032
2033/**
2034 * __iavf_chk_linearize - Check if there are more than 8 buffers per packet
2035 * @skb:      send buffer
2036 *
2037 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
2038 * and so we need to figure out the cases where we need to linearize the skb.
2039 *
2040 * For TSO we need to count the TSO header and segment payload separately.
2041 * As such we need to check cases where we have 7 fragments or more as we
2042 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
2043 * the segment payload in the first descriptor, and another 7 for the
2044 * fragments.
2045 **/
2046bool __iavf_chk_linearize(struct sk_buff *skb)
2047{
2048	const skb_frag_t *frag, *stale;
2049	int nr_frags, sum;
2050
2051	/* no need to check if number of frags is less than 7 */
2052	nr_frags = skb_shinfo(skb)->nr_frags;
2053	if (nr_frags < (IAVF_MAX_BUFFER_TXD - 1))
2054		return false;
2055
2056	/* We need to walk through the list and validate that each group
2057	 * of 6 fragments totals at least gso_size.
2058	 */
2059	nr_frags -= IAVF_MAX_BUFFER_TXD - 2;
2060	frag = &skb_shinfo(skb)->frags[0];
2061
2062	/* Initialize size to the negative value of gso_size minus 1.  We
2063	 * use this as the worst case scenerio in which the frag ahead
2064	 * of us only provides one byte which is why we are limited to 6
2065	 * descriptors for a single transmit as the header and previous
2066	 * fragment are already consuming 2 descriptors.
2067	 */
2068	sum = 1 - skb_shinfo(skb)->gso_size;
2069
2070	/* Add size of frags 0 through 4 to create our initial sum */
2071	sum += skb_frag_size(frag++);
2072	sum += skb_frag_size(frag++);
2073	sum += skb_frag_size(frag++);
2074	sum += skb_frag_size(frag++);
2075	sum += skb_frag_size(frag++);
2076
2077	/* Walk through fragments adding latest fragment, testing it, and
2078	 * then removing stale fragments from the sum.
2079	 */
2080	for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
2081		int stale_size = skb_frag_size(stale);
2082
2083		sum += skb_frag_size(frag++);
2084
2085		/* The stale fragment may present us with a smaller
2086		 * descriptor than the actual fragment size. To account
2087		 * for that we need to remove all the data on the front and
2088		 * figure out what the remainder would be in the last
2089		 * descriptor associated with the fragment.
2090		 */
2091		if (stale_size > IAVF_MAX_DATA_PER_TXD) {
2092			int align_pad = -(skb_frag_off(stale)) &
2093					(IAVF_MAX_READ_REQ_SIZE - 1);
2094
2095			sum -= align_pad;
2096			stale_size -= align_pad;
2097
2098			do {
2099				sum -= IAVF_MAX_DATA_PER_TXD_ALIGNED;
2100				stale_size -= IAVF_MAX_DATA_PER_TXD_ALIGNED;
2101			} while (stale_size > IAVF_MAX_DATA_PER_TXD);
2102		}
2103
2104		/* if sum is negative we failed to make sufficient progress */
2105		if (sum < 0)
2106			return true;
2107
2108		if (!nr_frags--)
2109			break;
2110
2111		sum -= stale_size;
2112	}
2113
2114	return false;
2115}
2116
2117/**
2118 * __iavf_maybe_stop_tx - 2nd level check for tx stop conditions
2119 * @tx_ring: the ring to be checked
2120 * @size:    the size buffer we want to assure is available
2121 *
2122 * Returns -EBUSY if a stop is needed, else 0
2123 **/
2124int __iavf_maybe_stop_tx(struct iavf_ring *tx_ring, int size)
2125{
2126	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2127	/* Memory barrier before checking head and tail */
2128	smp_mb();
2129
2130	/* Check again in a case another CPU has just made room available. */
2131	if (likely(IAVF_DESC_UNUSED(tx_ring) < size))
2132		return -EBUSY;
2133
2134	/* A reprieve! - use start_queue because it doesn't call schedule */
2135	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2136	++tx_ring->tx_stats.restart_queue;
2137	return 0;
2138}
2139
2140/**
2141 * iavf_tx_map - Build the Tx descriptor
2142 * @tx_ring:  ring to send buffer on
2143 * @skb:      send buffer
2144 * @first:    first buffer info buffer to use
2145 * @tx_flags: collected send information
2146 * @hdr_len:  size of the packet header
2147 * @td_cmd:   the command field in the descriptor
2148 * @td_offset: offset for checksum or crc
2149 **/
2150static void iavf_tx_map(struct iavf_ring *tx_ring, struct sk_buff *skb,
2151			struct iavf_tx_buffer *first, u32 tx_flags,
2152			const u8 hdr_len, u32 td_cmd, u32 td_offset)
2153{
2154	unsigned int data_len = skb->data_len;
2155	unsigned int size = skb_headlen(skb);
2156	skb_frag_t *frag;
2157	struct iavf_tx_buffer *tx_bi;
2158	struct iavf_tx_desc *tx_desc;
2159	u16 i = tx_ring->next_to_use;
2160	u32 td_tag = 0;
2161	dma_addr_t dma;
2162
2163	if (tx_flags & IAVF_TX_FLAGS_HW_VLAN) {
2164		td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2165		td_tag = FIELD_GET(IAVF_TX_FLAGS_VLAN_MASK, tx_flags);
2166	}
2167
2168	first->tx_flags = tx_flags;
2169
2170	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2171
2172	tx_desc = IAVF_TX_DESC(tx_ring, i);
2173	tx_bi = first;
2174
2175	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2176		unsigned int max_data = IAVF_MAX_DATA_PER_TXD_ALIGNED;
2177
2178		if (dma_mapping_error(tx_ring->dev, dma))
2179			goto dma_error;
2180
2181		/* record length, and DMA address */
2182		dma_unmap_len_set(tx_bi, len, size);
2183		dma_unmap_addr_set(tx_bi, dma, dma);
2184
2185		/* align size to end of page */
2186		max_data += -dma & (IAVF_MAX_READ_REQ_SIZE - 1);
2187		tx_desc->buffer_addr = cpu_to_le64(dma);
2188
2189		while (unlikely(size > IAVF_MAX_DATA_PER_TXD)) {
2190			tx_desc->cmd_type_offset_bsz =
2191				build_ctob(td_cmd, td_offset,
2192					   max_data, td_tag);
2193
2194			tx_desc++;
2195			i++;
2196
2197			if (i == tx_ring->count) {
2198				tx_desc = IAVF_TX_DESC(tx_ring, 0);
2199				i = 0;
2200			}
2201
2202			dma += max_data;
2203			size -= max_data;
2204
2205			max_data = IAVF_MAX_DATA_PER_TXD_ALIGNED;
2206			tx_desc->buffer_addr = cpu_to_le64(dma);
2207		}
2208
2209		if (likely(!data_len))
2210			break;
2211
2212		tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2213							  size, td_tag);
2214
2215		tx_desc++;
2216		i++;
2217
2218		if (i == tx_ring->count) {
2219			tx_desc = IAVF_TX_DESC(tx_ring, 0);
2220			i = 0;
2221		}
2222
2223		size = skb_frag_size(frag);
2224		data_len -= size;
2225
2226		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2227				       DMA_TO_DEVICE);
2228
2229		tx_bi = &tx_ring->tx_bi[i];
2230	}
2231
2232	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
2233
2234	i++;
2235	if (i == tx_ring->count)
2236		i = 0;
2237
2238	tx_ring->next_to_use = i;
2239
2240	iavf_maybe_stop_tx(tx_ring, DESC_NEEDED);
2241
2242	/* write last descriptor with RS and EOP bits */
2243	td_cmd |= IAVF_TXD_CMD;
2244	tx_desc->cmd_type_offset_bsz =
2245			build_ctob(td_cmd, td_offset, size, td_tag);
2246
2247	skb_tx_timestamp(skb);
2248
2249	/* Force memory writes to complete before letting h/w know there
2250	 * are new descriptors to fetch.
2251	 *
2252	 * We also use this memory barrier to make certain all of the
2253	 * status bits have been updated before next_to_watch is written.
2254	 */
2255	wmb();
2256
2257	/* set next_to_watch value indicating a packet is present */
2258	first->next_to_watch = tx_desc;
2259
2260	/* notify HW of packet */
2261	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
2262		writel(i, tx_ring->tail);
2263	}
2264
2265	return;
2266
2267dma_error:
2268	dev_info(tx_ring->dev, "TX DMA map failed\n");
2269
2270	/* clear dma mappings for failed tx_bi map */
2271	for (;;) {
2272		tx_bi = &tx_ring->tx_bi[i];
2273		iavf_unmap_and_free_tx_resource(tx_ring, tx_bi);
2274		if (tx_bi == first)
2275			break;
2276		if (i == 0)
2277			i = tx_ring->count;
2278		i--;
2279	}
2280
2281	tx_ring->next_to_use = i;
2282}
2283
2284/**
2285 * iavf_xmit_frame_ring - Sends buffer on Tx ring
2286 * @skb:     send buffer
2287 * @tx_ring: ring to send buffer on
2288 *
2289 * Returns NETDEV_TX_OK if sent, else an error code
2290 **/
2291static netdev_tx_t iavf_xmit_frame_ring(struct sk_buff *skb,
2292					struct iavf_ring *tx_ring)
2293{
2294	u64 cd_type_cmd_tso_mss = IAVF_TX_DESC_DTYPE_CONTEXT;
2295	u32 cd_tunneling = 0, cd_l2tag2 = 0;
2296	struct iavf_tx_buffer *first;
2297	u32 td_offset = 0;
2298	u32 tx_flags = 0;
2299	__be16 protocol;
2300	u32 td_cmd = 0;
2301	u8 hdr_len = 0;
2302	int tso, count;
2303
2304	/* prefetch the data, we'll need it later */
2305	prefetch(skb->data);
2306
2307	iavf_trace(xmit_frame_ring, skb, tx_ring);
2308
2309	count = iavf_xmit_descriptor_count(skb);
2310	if (iavf_chk_linearize(skb, count)) {
2311		if (__skb_linearize(skb)) {
2312			dev_kfree_skb_any(skb);
2313			return NETDEV_TX_OK;
2314		}
2315		count = iavf_txd_use_count(skb->len);
2316		tx_ring->tx_stats.tx_linearize++;
2317	}
2318
2319	/* need: 1 descriptor per page * PAGE_SIZE/IAVF_MAX_DATA_PER_TXD,
2320	 *       + 1 desc for skb_head_len/IAVF_MAX_DATA_PER_TXD,
2321	 *       + 4 desc gap to avoid the cache line where head is,
2322	 *       + 1 desc for context descriptor,
2323	 * otherwise try next time
2324	 */
2325	if (iavf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2326		tx_ring->tx_stats.tx_busy++;
2327		return NETDEV_TX_BUSY;
2328	}
2329
2330	/* record the location of the first descriptor for this packet */
2331	first = &tx_ring->tx_bi[tx_ring->next_to_use];
2332	first->skb = skb;
2333	first->bytecount = skb->len;
2334	first->gso_segs = 1;
2335
2336	/* prepare the xmit flags */
2337	iavf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags);
2338	if (tx_flags & IAVF_TX_FLAGS_HW_OUTER_SINGLE_VLAN) {
2339		cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2 <<
2340			IAVF_TXD_CTX_QW1_CMD_SHIFT;
2341		cd_l2tag2 = FIELD_GET(IAVF_TX_FLAGS_VLAN_MASK, tx_flags);
2342	}
2343
2344	/* obtain protocol of skb */
2345	protocol = vlan_get_protocol(skb);
2346
2347	/* setup IPv4/IPv6 offloads */
2348	if (protocol == htons(ETH_P_IP))
2349		tx_flags |= IAVF_TX_FLAGS_IPV4;
2350	else if (protocol == htons(ETH_P_IPV6))
2351		tx_flags |= IAVF_TX_FLAGS_IPV6;
2352
2353	tso = iavf_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
2354
2355	if (tso < 0)
2356		goto out_drop;
2357	else if (tso)
2358		tx_flags |= IAVF_TX_FLAGS_TSO;
2359
2360	/* Always offload the checksum, since it's in the data descriptor */
2361	tso = iavf_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2362				  tx_ring, &cd_tunneling);
2363	if (tso < 0)
2364		goto out_drop;
2365
2366	/* always enable CRC insertion offload */
2367	td_cmd |= IAVF_TX_DESC_CMD_ICRC;
2368
2369	iavf_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2370			   cd_tunneling, cd_l2tag2);
2371
2372	iavf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2373		    td_cmd, td_offset);
2374
2375	return NETDEV_TX_OK;
2376
2377out_drop:
2378	iavf_trace(xmit_frame_ring_drop, first->skb, tx_ring);
2379	dev_kfree_skb_any(first->skb);
2380	first->skb = NULL;
2381	return NETDEV_TX_OK;
2382}
2383
2384/**
2385 * iavf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2386 * @skb:    send buffer
2387 * @netdev: network interface device structure
2388 *
2389 * Returns NETDEV_TX_OK if sent, else an error code
2390 **/
2391netdev_tx_t iavf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2392{
2393	struct iavf_adapter *adapter = netdev_priv(netdev);
2394	struct iavf_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2395
2396	/* hardware can't handle really short frames, hardware padding works
2397	 * beyond this point
2398	 */
2399	if (unlikely(skb->len < IAVF_MIN_TX_LEN)) {
2400		if (skb_pad(skb, IAVF_MIN_TX_LEN - skb->len))
2401			return NETDEV_TX_OK;
2402		skb->len = IAVF_MIN_TX_LEN;
2403		skb_set_tail_pointer(skb, IAVF_MIN_TX_LEN);
2404	}
2405
2406	return iavf_xmit_frame_ring(skb, tx_ring);
2407}