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i40e_common.c
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linux-6.19.14/drivers/net/ethernet/intel/i40e/i40e_common.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4#include <linux/avf/virtchnl.h> 5#include <linux/bitfield.h> 6#include <linux/delay.h> 7#include <linux/etherdevice.h> 8#include <linux/pci.h> 9#include "i40e_adminq_cmd.h" 10#include "i40e_devids.h" 11#include "i40e_prototype.h" 12#include "i40e_register.h" 13 14/** 15 * i40e_set_mac_type - Sets MAC type 16 * @hw: pointer to the HW structure 17 * 18 * This function sets the mac type of the adapter based on the 19 * vendor ID and device ID stored in the hw structure. 20 **/ 21int i40e_set_mac_type(struct i40e_hw *hw) 22{ 23 int status = 0; 24 25 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 26 switch (hw->device_id) { 27 case I40E_DEV_ID_SFP_XL710: 28 case I40E_DEV_ID_QEMU: 29 case I40E_DEV_ID_KX_B: 30 case I40E_DEV_ID_KX_C: 31 case I40E_DEV_ID_QSFP_A: 32 case I40E_DEV_ID_QSFP_B: 33 case I40E_DEV_ID_QSFP_C: 34 case I40E_DEV_ID_1G_BASE_T_BC: 35 case I40E_DEV_ID_5G_BASE_T_BC: 36 case I40E_DEV_ID_10G_BASE_T: 37 case I40E_DEV_ID_10G_BASE_T4: 38 case I40E_DEV_ID_10G_BASE_T_BC: 39 case I40E_DEV_ID_10G_B: 40 case I40E_DEV_ID_10G_SFP: 41 case I40E_DEV_ID_20G_KR2: 42 case I40E_DEV_ID_20G_KR2_A: 43 case I40E_DEV_ID_25G_B: 44 case I40E_DEV_ID_25G_SFP28: 45 case I40E_DEV_ID_X710_N3000: 46 case I40E_DEV_ID_XXV710_N3000: 47 hw->mac.type = I40E_MAC_XL710; 48 break; 49 case I40E_DEV_ID_KX_X722: 50 case I40E_DEV_ID_QSFP_X722: 51 case I40E_DEV_ID_SFP_X722: 52 case I40E_DEV_ID_1G_BASE_T_X722: 53 case I40E_DEV_ID_10G_BASE_T_X722: 54 case I40E_DEV_ID_SFP_I_X722: 55 case I40E_DEV_ID_SFP_X722_A: 56 hw->mac.type = I40E_MAC_X722; 57 break; 58 default: 59 hw->mac.type = I40E_MAC_GENERIC; 60 break; 61 } 62 } else { 63 status = -ENODEV; 64 } 65 66 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 67 hw->mac.type, status); 68 return status; 69} 70 71/** 72 * i40e_debug_aq 73 * @hw: debug mask related to admin queue 74 * @mask: debug mask 75 * @desc: pointer to admin queue descriptor 76 * @buffer: pointer to command buffer 77 * @buf_len: max length of buffer 78 * 79 * Dumps debug log about adminq command with descriptor contents. 80 **/ 81void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 82 void *buffer, u16 buf_len) 83{ 84 struct libie_aq_desc *aq_desc = (struct libie_aq_desc *)desc; 85 u32 effective_mask = hw->debug_mask & mask; 86 char prefix[27]; 87 u16 len; 88 u8 *buf = (u8 *)buffer; 89 90 if (!effective_mask || !desc) 91 return; 92 93 len = le16_to_cpu(aq_desc->datalen); 94 95 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 96 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 97 le16_to_cpu(aq_desc->opcode), 98 le16_to_cpu(aq_desc->flags), 99 le16_to_cpu(aq_desc->datalen), 100 le16_to_cpu(aq_desc->retval)); 101 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 102 "\tcookie (h,l) 0x%08X 0x%08X\n", 103 le32_to_cpu(aq_desc->cookie_high), 104 le32_to_cpu(aq_desc->cookie_low)); 105 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 106 "\tparam (0,1) 0x%08X 0x%08X\n", 107 le32_to_cpu(aq_desc->params.generic.param0), 108 le32_to_cpu(aq_desc->params.generic.param1)); 109 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 110 "\taddr (h,l) 0x%08X 0x%08X\n", 111 le32_to_cpu(aq_desc->params.generic.addr_high), 112 le32_to_cpu(aq_desc->params.generic.addr_low)); 113 114 if (buffer && buf_len != 0 && len != 0 && 115 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 116 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 117 if (buf_len < len) 118 len = buf_len; 119 120 snprintf(prefix, sizeof(prefix), 121 "i40e %02x:%02x.%x: \t0x", 122 hw->bus.bus_id, 123 hw->bus.device, 124 hw->bus.func); 125 126 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 127 16, 1, buf, len, false); 128 } 129} 130 131/** 132 * i40e_check_asq_alive 133 * @hw: pointer to the hw struct 134 * 135 * Returns true if Queue is enabled else false. 136 **/ 137bool i40e_check_asq_alive(struct i40e_hw *hw) 138{ 139 /* Check if the queue is initialized */ 140 if (!hw->aq.asq.count) 141 return false; 142 143 return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK); 144} 145 146/** 147 * i40e_aq_queue_shutdown 148 * @hw: pointer to the hw struct 149 * @unloading: is the driver unloading itself 150 * 151 * Tell the Firmware that we're shutting down the AdminQ and whether 152 * or not the driver is unloading as well. 153 **/ 154int i40e_aq_queue_shutdown(struct i40e_hw *hw, 155 bool unloading) 156{ 157 struct i40e_aqc_queue_shutdown *cmd; 158 struct libie_aq_desc desc; 159 int status; 160 161 i40e_fill_default_direct_cmd_desc(&desc, 162 i40e_aqc_opc_queue_shutdown); 163 164 cmd = libie_aq_raw(&desc); 165 if (unloading) 166 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 167 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 168 169 return status; 170} 171 172/** 173 * i40e_aq_get_set_rss_lut 174 * @hw: pointer to the hardware structure 175 * @vsi_id: vsi fw index 176 * @pf_lut: for PF table set true, for VSI table set false 177 * @lut: pointer to the lut buffer provided by the caller 178 * @lut_size: size of the lut buffer 179 * @set: set true to set the table, false to get the table 180 * 181 * Internal function to get or set RSS look up table 182 **/ 183static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 184 u16 vsi_id, bool pf_lut, 185 u8 *lut, u16 lut_size, 186 bool set) 187{ 188 struct i40e_aqc_get_set_rss_lut *cmd_resp; 189 struct libie_aq_desc desc; 190 int status; 191 u16 flags; 192 193 if (set) 194 i40e_fill_default_direct_cmd_desc(&desc, 195 i40e_aqc_opc_set_rss_lut); 196 else 197 i40e_fill_default_direct_cmd_desc(&desc, 198 i40e_aqc_opc_get_rss_lut); 199 200 cmd_resp = libie_aq_raw(&desc); 201 /* Indirect command */ 202 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 203 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 204 205 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) | 206 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1); 207 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 208 209 if (pf_lut) 210 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 211 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF); 212 else 213 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 214 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI); 215 216 cmd_resp->flags = cpu_to_le16(flags); 217 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 218 219 return status; 220} 221 222/** 223 * i40e_aq_get_rss_lut 224 * @hw: pointer to the hardware structure 225 * @vsi_id: vsi fw index 226 * @pf_lut: for PF table set true, for VSI table set false 227 * @lut: pointer to the lut buffer provided by the caller 228 * @lut_size: size of the lut buffer 229 * 230 * get the RSS lookup table, PF or VSI type 231 **/ 232int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 233 bool pf_lut, u8 *lut, u16 lut_size) 234{ 235 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 236 false); 237} 238 239/** 240 * i40e_aq_set_rss_lut 241 * @hw: pointer to the hardware structure 242 * @vsi_id: vsi fw index 243 * @pf_lut: for PF table set true, for VSI table set false 244 * @lut: pointer to the lut buffer provided by the caller 245 * @lut_size: size of the lut buffer 246 * 247 * set the RSS lookup table, PF or VSI type 248 **/ 249int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 250 bool pf_lut, u8 *lut, u16 lut_size) 251{ 252 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 253} 254 255/** 256 * i40e_aq_get_set_rss_key 257 * @hw: pointer to the hw struct 258 * @vsi_id: vsi fw index 259 * @key: pointer to key info struct 260 * @set: set true to set the key, false to get the key 261 * 262 * get the RSS key per VSI 263 **/ 264static int i40e_aq_get_set_rss_key(struct i40e_hw *hw, 265 u16 vsi_id, 266 struct i40e_aqc_get_set_rss_key_data *key, 267 bool set) 268{ 269 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 270 struct i40e_aqc_get_set_rss_key *cmd_resp; 271 struct libie_aq_desc desc; 272 int status; 273 274 if (set) 275 i40e_fill_default_direct_cmd_desc(&desc, 276 i40e_aqc_opc_set_rss_key); 277 else 278 i40e_fill_default_direct_cmd_desc(&desc, 279 i40e_aqc_opc_get_rss_key); 280 281 cmd_resp = libie_aq_raw(&desc); 282 /* Indirect command */ 283 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 284 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 285 286 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) | 287 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1); 288 cmd_resp->vsi_id = cpu_to_le16(vsi_id); 289 290 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 291 292 return status; 293} 294 295/** 296 * i40e_aq_get_rss_key 297 * @hw: pointer to the hw struct 298 * @vsi_id: vsi fw index 299 * @key: pointer to key info struct 300 * 301 **/ 302int i40e_aq_get_rss_key(struct i40e_hw *hw, 303 u16 vsi_id, 304 struct i40e_aqc_get_set_rss_key_data *key) 305{ 306 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 307} 308 309/** 310 * i40e_aq_set_rss_key 311 * @hw: pointer to the hw struct 312 * @vsi_id: vsi fw index 313 * @key: pointer to key info struct 314 * 315 * set the RSS key per VSI 316 **/ 317int i40e_aq_set_rss_key(struct i40e_hw *hw, 318 u16 vsi_id, 319 struct i40e_aqc_get_set_rss_key_data *key) 320{ 321 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 322} 323 324/** 325 * i40e_init_shared_code - Initialize the shared code 326 * @hw: pointer to hardware structure 327 * 328 * This assigns the MAC type and PHY code and inits the NVM. 329 * Does not touch the hardware. This function must be called prior to any 330 * other function in the shared code. The i40e_hw structure should be 331 * memset to 0 prior to calling this function. The following fields in 332 * hw structure should be filled in prior to calling this function: 333 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 334 * subsystem_vendor_id, and revision_id 335 **/ 336int i40e_init_shared_code(struct i40e_hw *hw) 337{ 338 u32 port, ari, func_rid; 339 int status = 0; 340 341 i40e_set_mac_type(hw); 342 343 switch (hw->mac.type) { 344 case I40E_MAC_XL710: 345 case I40E_MAC_X722: 346 break; 347 default: 348 return -ENODEV; 349 } 350 351 hw->phy.get_link_info = true; 352 353 /* Determine port number and PF number*/ 354 port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK, 355 rd32(hw, I40E_PFGEN_PORTNUM)); 356 hw->port = (u8)port; 357 ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK, 358 rd32(hw, I40E_GLPCI_CAPSUP)); 359 func_rid = rd32(hw, I40E_PF_FUNC_RID); 360 if (ari) 361 hw->pf_id = (u8)(func_rid & 0xff); 362 else 363 hw->pf_id = (u8)(func_rid & 0x7); 364 365 status = i40e_init_nvm(hw); 366 return status; 367} 368 369/** 370 * i40e_aq_mac_address_read - Retrieve the MAC addresses 371 * @hw: pointer to the hw struct 372 * @flags: a return indicator of what addresses were added to the addr store 373 * @addrs: the requestor's mac addr store 374 * @cmd_details: pointer to command details structure or NULL 375 **/ 376static int 377i40e_aq_mac_address_read(struct i40e_hw *hw, 378 u16 *flags, 379 struct i40e_aqc_mac_address_read_data *addrs, 380 struct i40e_asq_cmd_details *cmd_details) 381{ 382 struct i40e_aqc_mac_address_read *cmd_data; 383 struct libie_aq_desc desc; 384 int status; 385 386 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 387 cmd_data = libie_aq_raw(&desc); 388 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF); 389 390 status = i40e_asq_send_command(hw, &desc, addrs, 391 sizeof(*addrs), cmd_details); 392 *flags = le16_to_cpu(cmd_data->command_flags); 393 394 return status; 395} 396 397/** 398 * i40e_aq_mac_address_write - Change the MAC addresses 399 * @hw: pointer to the hw struct 400 * @flags: indicates which MAC to be written 401 * @mac_addr: address to write 402 * @cmd_details: pointer to command details structure or NULL 403 **/ 404int i40e_aq_mac_address_write(struct i40e_hw *hw, 405 u16 flags, u8 *mac_addr, 406 struct i40e_asq_cmd_details *cmd_details) 407{ 408 struct i40e_aqc_mac_address_write *cmd_data; 409 struct libie_aq_desc desc; 410 int status; 411 412 i40e_fill_default_direct_cmd_desc(&desc, 413 i40e_aqc_opc_mac_address_write); 414 cmd_data = libie_aq_raw(&desc); 415 cmd_data->command_flags = cpu_to_le16(flags); 416 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 417 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 418 ((u32)mac_addr[3] << 16) | 419 ((u32)mac_addr[4] << 8) | 420 mac_addr[5]); 421 422 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 423 424 return status; 425} 426 427/** 428 * i40e_get_mac_addr - get MAC address 429 * @hw: pointer to the HW structure 430 * @mac_addr: pointer to MAC address 431 * 432 * Reads the adapter's MAC address from register 433 **/ 434int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 435{ 436 struct i40e_aqc_mac_address_read_data addrs; 437 u16 flags = 0; 438 int status; 439 440 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 441 442 if (flags & I40E_AQC_LAN_ADDR_VALID) 443 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 444 445 return status; 446} 447 448/** 449 * i40e_get_port_mac_addr - get Port MAC address 450 * @hw: pointer to the HW structure 451 * @mac_addr: pointer to Port MAC address 452 * 453 * Reads the adapter's Port MAC address 454 **/ 455int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 456{ 457 struct i40e_aqc_mac_address_read_data addrs; 458 u16 flags = 0; 459 int status; 460 461 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 462 if (status) 463 return status; 464 465 if (flags & I40E_AQC_PORT_ADDR_VALID) 466 ether_addr_copy(mac_addr, addrs.port_mac); 467 else 468 status = -EINVAL; 469 470 return status; 471} 472 473/** 474 * i40e_pre_tx_queue_cfg - pre tx queue configure 475 * @hw: pointer to the HW structure 476 * @queue: target PF queue index 477 * @enable: state change request 478 * 479 * Handles hw requirement to indicate intention to enable 480 * or disable target queue. 481 **/ 482void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 483{ 484 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 485 u32 reg_block = 0; 486 u32 reg_val; 487 488 if (abs_queue_idx >= 128) { 489 reg_block = abs_queue_idx / 128; 490 abs_queue_idx %= 128; 491 } 492 493 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 494 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 495 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 496 497 if (enable) 498 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 499 else 500 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 501 502 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 503} 504 505/** 506 * i40e_get_pba_string - Reads part number string from EEPROM 507 * @hw: pointer to hardware structure 508 * 509 * Reads the part number string from the EEPROM and stores it 510 * into newly allocated buffer and saves resulting pointer 511 * to i40e_hw->pba_id field. 512 **/ 513void i40e_get_pba_string(struct i40e_hw *hw) 514{ 515#define I40E_NVM_PBA_FLAGS_BLK_PRESENT 0xFAFA 516 u16 pba_word = 0; 517 u16 pba_size = 0; 518 u16 pba_ptr = 0; 519 int status; 520 char *ptr; 521 u16 i; 522 523 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 524 if (status) { 525 hw_dbg(hw, "Failed to read PBA flags.\n"); 526 return; 527 } 528 if (pba_word != I40E_NVM_PBA_FLAGS_BLK_PRESENT) { 529 hw_dbg(hw, "PBA block is not present.\n"); 530 return; 531 } 532 533 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 534 if (status) { 535 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 536 return; 537 } 538 539 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 540 if (status) { 541 hw_dbg(hw, "Failed to read PBA Block size.\n"); 542 return; 543 } 544 545 /* Subtract one to get PBA word count (PBA Size word is included in 546 * total size) and advance pointer to first PBA word. 547 */ 548 pba_size--; 549 pba_ptr++; 550 if (!pba_size) { 551 hw_dbg(hw, "PBA ID is empty.\n"); 552 return; 553 } 554 555 ptr = devm_kzalloc(i40e_hw_to_dev(hw), pba_size * 2 + 1, GFP_KERNEL); 556 if (!ptr) 557 return; 558 hw->pba_id = ptr; 559 560 for (i = 0; i < pba_size; i++) { 561 status = i40e_read_nvm_word(hw, pba_ptr + i, &pba_word); 562 if (status) { 563 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 564 devm_kfree(i40e_hw_to_dev(hw), hw->pba_id); 565 hw->pba_id = NULL; 566 return; 567 } 568 569 *ptr++ = (pba_word >> 8) & 0xFF; 570 *ptr++ = pba_word & 0xFF; 571 } 572} 573 574/** 575 * i40e_get_media_type - Gets media type 576 * @hw: pointer to the hardware structure 577 **/ 578static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 579{ 580 enum i40e_media_type media; 581 582 switch (hw->phy.link_info.phy_type) { 583 case I40E_PHY_TYPE_10GBASE_SR: 584 case I40E_PHY_TYPE_10GBASE_LR: 585 case I40E_PHY_TYPE_1000BASE_SX: 586 case I40E_PHY_TYPE_1000BASE_LX: 587 case I40E_PHY_TYPE_40GBASE_SR4: 588 case I40E_PHY_TYPE_40GBASE_LR4: 589 case I40E_PHY_TYPE_25GBASE_LR: 590 case I40E_PHY_TYPE_25GBASE_SR: 591 media = I40E_MEDIA_TYPE_FIBER; 592 break; 593 case I40E_PHY_TYPE_100BASE_TX: 594 case I40E_PHY_TYPE_1000BASE_T: 595 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS: 596 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS: 597 case I40E_PHY_TYPE_10GBASE_T: 598 media = I40E_MEDIA_TYPE_BASET; 599 break; 600 case I40E_PHY_TYPE_10GBASE_CR1_CU: 601 case I40E_PHY_TYPE_40GBASE_CR4_CU: 602 case I40E_PHY_TYPE_10GBASE_CR1: 603 case I40E_PHY_TYPE_40GBASE_CR4: 604 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 605 case I40E_PHY_TYPE_40GBASE_AOC: 606 case I40E_PHY_TYPE_10GBASE_AOC: 607 case I40E_PHY_TYPE_25GBASE_CR: 608 case I40E_PHY_TYPE_25GBASE_AOC: 609 case I40E_PHY_TYPE_25GBASE_ACC: 610 media = I40E_MEDIA_TYPE_DA; 611 break; 612 case I40E_PHY_TYPE_1000BASE_KX: 613 case I40E_PHY_TYPE_10GBASE_KX4: 614 case I40E_PHY_TYPE_10GBASE_KR: 615 case I40E_PHY_TYPE_40GBASE_KR4: 616 case I40E_PHY_TYPE_20GBASE_KR2: 617 case I40E_PHY_TYPE_25GBASE_KR: 618 media = I40E_MEDIA_TYPE_BACKPLANE; 619 break; 620 case I40E_PHY_TYPE_SGMII: 621 case I40E_PHY_TYPE_XAUI: 622 case I40E_PHY_TYPE_XFI: 623 case I40E_PHY_TYPE_XLAUI: 624 case I40E_PHY_TYPE_XLPPI: 625 default: 626 media = I40E_MEDIA_TYPE_UNKNOWN; 627 break; 628 } 629 630 return media; 631} 632 633/** 634 * i40e_poll_globr - Poll for Global Reset completion 635 * @hw: pointer to the hardware structure 636 * @retry_limit: how many times to retry before failure 637 **/ 638static int i40e_poll_globr(struct i40e_hw *hw, 639 u32 retry_limit) 640{ 641 u32 cnt, reg = 0; 642 643 for (cnt = 0; cnt < retry_limit; cnt++) { 644 reg = rd32(hw, I40E_GLGEN_RSTAT); 645 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 646 return 0; 647 msleep(100); 648 } 649 650 hw_dbg(hw, "Global reset failed.\n"); 651 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); 652 653 return -EIO; 654} 655 656#define I40E_PF_RESET_WAIT_COUNT_A0 200 657#define I40E_PF_RESET_WAIT_COUNT 200 658/** 659 * i40e_pf_reset - Reset the PF 660 * @hw: pointer to the hardware structure 661 * 662 * Assuming someone else has triggered a global reset, 663 * assure the global reset is complete and then reset the PF 664 **/ 665int i40e_pf_reset(struct i40e_hw *hw) 666{ 667 u32 cnt = 0; 668 u32 cnt1 = 0; 669 u32 reg = 0; 670 u32 grst_del; 671 672 /* Poll for Global Reset steady state in case of recent GRST. 673 * The grst delay value is in 100ms units, and we'll wait a 674 * couple counts longer to be sure we don't just miss the end. 675 */ 676 grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK, 677 rd32(hw, I40E_GLGEN_RSTCTL)); 678 679 /* It can take upto 15 secs for GRST steady state. 680 * Bump it to 16 secs max to be safe. 681 */ 682 grst_del = grst_del * 20; 683 684 for (cnt = 0; cnt < grst_del; cnt++) { 685 reg = rd32(hw, I40E_GLGEN_RSTAT); 686 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 687 break; 688 msleep(100); 689 } 690 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 691 hw_dbg(hw, "Global reset polling failed to complete.\n"); 692 return -EIO; 693 } 694 695 /* Now Wait for the FW to be ready */ 696 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 697 reg = rd32(hw, I40E_GLNVM_ULD); 698 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 699 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 700 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 701 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 702 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 703 break; 704 } 705 usleep_range(10000, 20000); 706 } 707 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 708 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 709 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 710 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 711 return -EIO; 712 } 713 714 /* If there was a Global Reset in progress when we got here, 715 * we don't need to do the PF Reset 716 */ 717 if (!cnt) { 718 u32 reg2 = 0; 719 if (hw->revision_id == 0) 720 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 721 else 722 cnt = I40E_PF_RESET_WAIT_COUNT; 723 reg = rd32(hw, I40E_PFGEN_CTRL); 724 wr32(hw, I40E_PFGEN_CTRL, 725 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 726 for (; cnt; cnt--) { 727 reg = rd32(hw, I40E_PFGEN_CTRL); 728 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 729 break; 730 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 731 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 732 break; 733 usleep_range(1000, 2000); 734 } 735 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 736 if (i40e_poll_globr(hw, grst_del)) 737 return -EIO; 738 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 739 hw_dbg(hw, "PF reset polling failed to complete.\n"); 740 return -EIO; 741 } 742 } 743 744 i40e_clear_pxe_mode(hw); 745 746 return 0; 747} 748 749/** 750 * i40e_clear_hw - clear out any left over hw state 751 * @hw: pointer to the hw struct 752 * 753 * Clear queues and interrupts, typically called at init time, 754 * but after the capabilities have been found so we know how many 755 * queues and msix vectors have been allocated. 756 **/ 757void i40e_clear_hw(struct i40e_hw *hw) 758{ 759 u32 num_queues, base_queue; 760 s32 num_pf_int; 761 s32 num_vf_int; 762 u32 num_vfs; 763 s32 i; 764 u32 j; 765 u32 val; 766 u32 eol = 0x7ff; 767 768 /* get number of interrupts, queues, and VFs */ 769 val = rd32(hw, I40E_GLPCI_CNF2); 770 num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val); 771 num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val); 772 773 val = rd32(hw, I40E_PFLAN_QALLOC); 774 base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val); 775 j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val); 776 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue) 777 num_queues = (j - base_queue) + 1; 778 else 779 num_queues = 0; 780 781 val = rd32(hw, I40E_PF_VT_PFALLOC); 782 i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val); 783 j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val); 784 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i) 785 num_vfs = (j - i) + 1; 786 else 787 num_vfs = 0; 788 789 /* stop all the interrupts */ 790 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 791 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 792 for (i = 0; i < num_pf_int - 2; i++) 793 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 794 795 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 796 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 797 wr32(hw, I40E_PFINT_LNKLST0, val); 798 for (i = 0; i < num_pf_int - 2; i++) 799 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 800 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 801 for (i = 0; i < num_vfs; i++) 802 wr32(hw, I40E_VPINT_LNKLST0(i), val); 803 for (i = 0; i < num_vf_int - 2; i++) 804 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 805 806 /* warn the HW of the coming Tx disables */ 807 for (i = 0; i < num_queues; i++) { 808 u32 abs_queue_idx = base_queue + i; 809 u32 reg_block = 0; 810 811 if (abs_queue_idx >= 128) { 812 reg_block = abs_queue_idx / 128; 813 abs_queue_idx %= 128; 814 } 815 816 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 817 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 818 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 819 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 820 821 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 822 } 823 udelay(400); 824 825 /* stop all the queues */ 826 for (i = 0; i < num_queues; i++) { 827 wr32(hw, I40E_QINT_TQCTL(i), 0); 828 wr32(hw, I40E_QTX_ENA(i), 0); 829 wr32(hw, I40E_QINT_RQCTL(i), 0); 830 wr32(hw, I40E_QRX_ENA(i), 0); 831 } 832 833 /* short wait for all queue disables to settle */ 834 udelay(50); 835} 836 837/** 838 * i40e_clear_pxe_mode - clear pxe operations mode 839 * @hw: pointer to the hw struct 840 * 841 * Make sure all PXE mode settings are cleared, including things 842 * like descriptor fetch/write-back mode. 843 **/ 844void i40e_clear_pxe_mode(struct i40e_hw *hw) 845{ 846 u32 reg; 847 848 if (i40e_check_asq_alive(hw)) 849 i40e_aq_clear_pxe_mode(hw, NULL); 850 851 /* Clear single descriptor fetch/write-back mode */ 852 reg = rd32(hw, I40E_GLLAN_RCTL_0); 853 854 if (hw->revision_id == 0) { 855 /* As a work around clear PXE_MODE instead of setting it */ 856 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 857 } else { 858 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 859 } 860} 861 862/** 863 * i40e_led_is_mine - helper to find matching led 864 * @hw: pointer to the hw struct 865 * @idx: index into GPIO registers 866 * 867 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 868 */ 869static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 870{ 871 u32 gpio_val = 0; 872 u32 port; 873 874 if (!I40E_IS_X710TL_DEVICE(hw->device_id) && 875 !hw->func_caps.led[idx]) 876 return 0; 877 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 878 port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val); 879 880 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 881 * if it is not our port then ignore 882 */ 883 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 884 (port != hw->port)) 885 return 0; 886 887 return gpio_val; 888} 889 890#define I40E_FW_LED BIT(4) 891#define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 892 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 893 894#define I40E_LED0 22 895 896#define I40E_PIN_FUNC_SDP 0x0 897#define I40E_PIN_FUNC_LED 0x1 898 899/** 900 * i40e_led_get - return current on/off mode 901 * @hw: pointer to the hw struct 902 * 903 * The value returned is the 'mode' field as defined in the 904 * GPIO register definitions: 0x0 = off, 0xf = on, and other 905 * values are variations of possible behaviors relating to 906 * blink, link, and wire. 907 **/ 908u32 i40e_led_get(struct i40e_hw *hw) 909{ 910 u32 mode = 0; 911 int i; 912 913 /* as per the documentation GPIO 22-29 are the LED 914 * GPIO pins named LED0..LED7 915 */ 916 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 917 u32 gpio_val = i40e_led_is_mine(hw, i); 918 919 if (!gpio_val) 920 continue; 921 922 mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val); 923 break; 924 } 925 926 return mode; 927} 928 929/** 930 * i40e_led_set - set new on/off mode 931 * @hw: pointer to the hw struct 932 * @mode: 0=off, 0xf=on (else see manual for mode details) 933 * @blink: true if the LED should blink when on, false if steady 934 * 935 * if this function is used to turn on the blink it should 936 * be used to disable the blink when restoring the original state. 937 **/ 938void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 939{ 940 int i; 941 942 if (mode & ~I40E_LED_MODE_VALID) { 943 hw_dbg(hw, "invalid mode passed in %X\n", mode); 944 return; 945 } 946 947 /* as per the documentation GPIO 22-29 are the LED 948 * GPIO pins named LED0..LED7 949 */ 950 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 951 u32 gpio_val = i40e_led_is_mine(hw, i); 952 953 if (!gpio_val) 954 continue; 955 956 if (I40E_IS_X710TL_DEVICE(hw->device_id)) { 957 u32 pin_func = 0; 958 959 if (mode & I40E_FW_LED) 960 pin_func = I40E_PIN_FUNC_SDP; 961 else 962 pin_func = I40E_PIN_FUNC_LED; 963 964 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 965 gpio_val |= 966 FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK, 967 pin_func); 968 } 969 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 970 /* this & is a bit of paranoia, but serves as a range check */ 971 gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, 972 mode); 973 974 if (blink) 975 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 976 else 977 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 978 979 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 980 break; 981 } 982} 983 984/* Admin command wrappers */ 985 986/** 987 * i40e_aq_get_phy_capabilities 988 * @hw: pointer to the hw struct 989 * @abilities: structure for PHY capabilities to be filled 990 * @qualified_modules: report Qualified Modules 991 * @report_init: report init capabilities (active are default) 992 * @cmd_details: pointer to command details structure or NULL 993 * 994 * Returns the various PHY abilities supported on the Port. 995 **/ 996int 997i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 998 bool qualified_modules, bool report_init, 999 struct i40e_aq_get_phy_abilities_resp *abilities, 1000 struct i40e_asq_cmd_details *cmd_details) 1001{ 1002 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1003 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1004 struct libie_aq_desc desc; 1005 int status; 1006 1007 if (!abilities) 1008 return -EINVAL; 1009 1010 do { 1011 i40e_fill_default_direct_cmd_desc(&desc, 1012 i40e_aqc_opc_get_phy_abilities); 1013 1014 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1015 if (abilities_size > I40E_AQ_LARGE_BUF) 1016 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 1017 1018 if (qualified_modules) 1019 desc.params.generic.param0 |= 1020 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1021 1022 if (report_init) 1023 desc.params.generic.param0 |= 1024 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1025 1026 status = i40e_asq_send_command(hw, &desc, abilities, 1027 abilities_size, cmd_details); 1028 1029 switch (hw->aq.asq_last_status) { 1030 case LIBIE_AQ_RC_EIO: 1031 status = -EIO; 1032 break; 1033 case LIBIE_AQ_RC_EAGAIN: 1034 usleep_range(1000, 2000); 1035 total_delay++; 1036 status = -EIO; 1037 break; 1038 /* also covers LIBIE_AQ_RC_OK */ 1039 default: 1040 break; 1041 } 1042 1043 } while ((hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN) && 1044 (total_delay < max_delay)); 1045 1046 if (status) 1047 return status; 1048 1049 if (report_init) { 1050 if (hw->mac.type == I40E_MAC_XL710 && 1051 i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR, 1052 I40E_MINOR_VER_GET_LINK_INFO_XL710)) { 1053 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1054 } else { 1055 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1056 hw->phy.phy_types |= 1057 ((u64)abilities->phy_type_ext << 32); 1058 } 1059 } 1060 1061 return status; 1062} 1063 1064/** 1065 * i40e_aq_set_phy_config 1066 * @hw: pointer to the hw struct 1067 * @config: structure with PHY configuration to be set 1068 * @cmd_details: pointer to command details structure or NULL 1069 * 1070 * Set the various PHY configuration parameters 1071 * supported on the Port.One or more of the Set PHY config parameters may be 1072 * ignored in an MFP mode as the PF may not have the privilege to set some 1073 * of the PHY Config parameters. This status will be indicated by the 1074 * command response. 1075 **/ 1076int i40e_aq_set_phy_config(struct i40e_hw *hw, 1077 struct i40e_aq_set_phy_config *config, 1078 struct i40e_asq_cmd_details *cmd_details) 1079{ 1080 struct i40e_aq_set_phy_config *cmd; 1081 struct libie_aq_desc desc; 1082 int status; 1083 1084 if (!config) 1085 return -EINVAL; 1086 1087 i40e_fill_default_direct_cmd_desc(&desc, 1088 i40e_aqc_opc_set_phy_config); 1089 1090 cmd = libie_aq_raw(&desc); 1091 *cmd = *config; 1092 1093 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1094 1095 return status; 1096} 1097 1098static noinline_for_stack int 1099i40e_set_fc_status(struct i40e_hw *hw, 1100 struct i40e_aq_get_phy_abilities_resp *abilities, 1101 bool atomic_restart) 1102{ 1103 struct i40e_aq_set_phy_config config; 1104 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1105 u8 pause_mask = 0x0; 1106 1107 switch (fc_mode) { 1108 case I40E_FC_FULL: 1109 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1110 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1111 break; 1112 case I40E_FC_RX_PAUSE: 1113 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1114 break; 1115 case I40E_FC_TX_PAUSE: 1116 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1117 break; 1118 default: 1119 break; 1120 } 1121 1122 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1123 /* clear the old pause settings */ 1124 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1125 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1126 /* set the new abilities */ 1127 config.abilities |= pause_mask; 1128 /* If the abilities have changed, then set the new config */ 1129 if (config.abilities == abilities->abilities) 1130 return 0; 1131 1132 /* Auto restart link so settings take effect */ 1133 if (atomic_restart) 1134 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1135 /* Copy over all the old settings */ 1136 config.phy_type = abilities->phy_type; 1137 config.phy_type_ext = abilities->phy_type_ext; 1138 config.link_speed = abilities->link_speed; 1139 config.eee_capability = abilities->eee_capability; 1140 config.eeer = abilities->eeer_val; 1141 config.low_power_ctrl = abilities->d3_lpan; 1142 config.fec_config = abilities->fec_cfg_curr_mod_ext_info & 1143 I40E_AQ_PHY_FEC_CONFIG_MASK; 1144 1145 return i40e_aq_set_phy_config(hw, &config, NULL); 1146} 1147 1148/** 1149 * i40e_set_fc 1150 * @hw: pointer to the hw struct 1151 * @aq_failures: buffer to return AdminQ failure information 1152 * @atomic_restart: whether to enable atomic link restart 1153 * 1154 * Set the requested flow control mode using set_phy_config. 1155 **/ 1156int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1157 bool atomic_restart) 1158{ 1159 struct i40e_aq_get_phy_abilities_resp abilities; 1160 int status; 1161 1162 *aq_failures = 0x0; 1163 1164 /* Get the current phy config */ 1165 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1166 NULL); 1167 if (status) { 1168 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1169 return status; 1170 } 1171 1172 status = i40e_set_fc_status(hw, &abilities, atomic_restart); 1173 if (status) 1174 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1175 1176 /* Update the link info */ 1177 status = i40e_update_link_info(hw); 1178 if (status) { 1179 /* Wait a little bit (on 40G cards it sometimes takes a really 1180 * long time for link to come back from the atomic reset) 1181 * and try once more 1182 */ 1183 msleep(1000); 1184 status = i40e_update_link_info(hw); 1185 } 1186 if (status) 1187 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1188 1189 return status; 1190} 1191 1192/** 1193 * i40e_aq_set_mac_config - Configure MAC settings 1194 * @hw: pointer to the hw struct 1195 * @max_frame_size: Maximum Frame Size to be supported by the port 1196 * @cmd_details: pointer to command details structure or NULL 1197 * 1198 * Set MAC configuration (0x0603). Note that max_frame_size must be greater 1199 * than zero. 1200 * 1201 * Return: 0 on success, or a negative error code on failure. 1202 */ 1203int i40e_aq_set_mac_config(struct i40e_hw *hw, u16 max_frame_size, 1204 struct i40e_asq_cmd_details *cmd_details) 1205{ 1206 struct i40e_aq_set_mac_config *cmd; 1207 struct libie_aq_desc desc; 1208 1209 cmd = libie_aq_raw(&desc); 1210 1211 if (max_frame_size == 0) 1212 return -EINVAL; 1213 1214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_mac_config); 1215 1216 cmd->max_frame_size = cpu_to_le16(max_frame_size); 1217 cmd->params = I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1218 1219#define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF 1220 cmd->fc_refresh_threshold = 1221 cpu_to_le16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD); 1222 1223 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1224} 1225 1226/** 1227 * i40e_aq_clear_pxe_mode 1228 * @hw: pointer to the hw struct 1229 * @cmd_details: pointer to command details structure or NULL 1230 * 1231 * Tell the firmware that the driver is taking over from PXE 1232 **/ 1233int i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1234 struct i40e_asq_cmd_details *cmd_details) 1235{ 1236 struct i40e_aqc_clear_pxe *cmd; 1237 struct libie_aq_desc desc; 1238 int status; 1239 1240 i40e_fill_default_direct_cmd_desc(&desc, 1241 i40e_aqc_opc_clear_pxe_mode); 1242 1243 cmd = libie_aq_raw(&desc); 1244 cmd->rx_cnt = 0x2; 1245 1246 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1247 1248 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1249 1250 return status; 1251} 1252 1253/** 1254 * i40e_aq_set_link_restart_an 1255 * @hw: pointer to the hw struct 1256 * @enable_link: if true: enable link, if false: disable link 1257 * @cmd_details: pointer to command details structure or NULL 1258 * 1259 * Sets up the link and restarts the Auto-Negotiation over the link. 1260 **/ 1261int i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1262 bool enable_link, 1263 struct i40e_asq_cmd_details *cmd_details) 1264{ 1265 struct i40e_aqc_set_link_restart_an *cmd; 1266 struct libie_aq_desc desc; 1267 int status; 1268 1269 i40e_fill_default_direct_cmd_desc(&desc, 1270 i40e_aqc_opc_set_link_restart_an); 1271 1272 cmd = libie_aq_raw(&desc); 1273 cmd->command = I40E_AQ_PHY_RESTART_AN; 1274 if (enable_link) 1275 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1276 else 1277 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1278 1279 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1280 1281 return status; 1282} 1283 1284/** 1285 * i40e_aq_get_link_info 1286 * @hw: pointer to the hw struct 1287 * @enable_lse: enable/disable LinkStatusEvent reporting 1288 * @link: pointer to link status structure - optional 1289 * @cmd_details: pointer to command details structure or NULL 1290 * 1291 * Returns the link status of the adapter. 1292 **/ 1293int i40e_aq_get_link_info(struct i40e_hw *hw, 1294 bool enable_lse, struct i40e_link_status *link, 1295 struct i40e_asq_cmd_details *cmd_details) 1296{ 1297 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1298 struct i40e_aqc_get_link_status *resp; 1299 struct libie_aq_desc desc; 1300 bool tx_pause, rx_pause; 1301 u16 command_flags; 1302 int status; 1303 1304 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1305 1306 resp = libie_aq_raw(&desc); 1307 if (enable_lse) 1308 command_flags = I40E_AQ_LSE_ENABLE; 1309 else 1310 command_flags = I40E_AQ_LSE_DISABLE; 1311 resp->command_flags = cpu_to_le16(command_flags); 1312 1313 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1314 1315 if (status) 1316 goto aq_get_link_info_exit; 1317 1318 /* save off old link status information */ 1319 hw->phy.link_info_old = *hw_link_info; 1320 1321 /* update link status */ 1322 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1323 hw->phy.media_type = i40e_get_media_type(hw); 1324 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1325 hw_link_info->link_info = resp->link_info; 1326 hw_link_info->an_info = resp->an_info; 1327 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1328 I40E_AQ_CONFIG_FEC_RS_ENA); 1329 hw_link_info->ext_info = resp->ext_info; 1330 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1331 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1332 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1333 1334 /* update fc info */ 1335 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1336 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1337 if (tx_pause & rx_pause) 1338 hw->fc.current_mode = I40E_FC_FULL; 1339 else if (tx_pause) 1340 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1341 else if (rx_pause) 1342 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1343 else 1344 hw->fc.current_mode = I40E_FC_NONE; 1345 1346 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1347 hw_link_info->crc_enable = true; 1348 else 1349 hw_link_info->crc_enable = false; 1350 1351 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1352 hw_link_info->lse_enable = true; 1353 else 1354 hw_link_info->lse_enable = false; 1355 1356 if (hw->mac.type == I40E_MAC_XL710 && i40e_is_fw_ver_lt(hw, 4, 40) && 1357 hw_link_info->phy_type == 0xE) 1358 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1359 1360 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps) && 1361 hw->mac.type != I40E_MAC_X722) { 1362 __le32 tmp; 1363 1364 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1365 hw->phy.phy_types = le32_to_cpu(tmp); 1366 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1367 } 1368 1369 /* save link status information */ 1370 if (link) 1371 *link = *hw_link_info; 1372 1373 /* flag cleared so helper functions don't call AQ again */ 1374 hw->phy.get_link_info = false; 1375 1376aq_get_link_info_exit: 1377 return status; 1378} 1379 1380/** 1381 * i40e_aq_set_phy_int_mask 1382 * @hw: pointer to the hw struct 1383 * @mask: interrupt mask to be set 1384 * @cmd_details: pointer to command details structure or NULL 1385 * 1386 * Set link interrupt mask. 1387 **/ 1388int i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1389 u16 mask, 1390 struct i40e_asq_cmd_details *cmd_details) 1391{ 1392 struct i40e_aqc_set_phy_int_mask *cmd; 1393 struct libie_aq_desc desc; 1394 int status; 1395 1396 i40e_fill_default_direct_cmd_desc(&desc, 1397 i40e_aqc_opc_set_phy_int_mask); 1398 1399 cmd = libie_aq_raw(&desc); 1400 cmd->event_mask = cpu_to_le16(mask); 1401 1402 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1403 1404 return status; 1405} 1406 1407/** 1408 * i40e_aq_set_mac_loopback 1409 * @hw: pointer to the HW struct 1410 * @ena_lpbk: Enable or Disable loopback 1411 * @cmd_details: pointer to command details structure or NULL 1412 * 1413 * Enable/disable loopback on a given port 1414 */ 1415int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk, 1416 struct i40e_asq_cmd_details *cmd_details) 1417{ 1418 struct i40e_aqc_set_lb_mode *cmd; 1419 struct libie_aq_desc desc; 1420 1421 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes); 1422 cmd = libie_aq_raw(&desc); 1423 if (ena_lpbk) { 1424 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER) 1425 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY); 1426 else 1427 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL); 1428 } 1429 1430 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1431} 1432 1433/** 1434 * i40e_aq_set_phy_debug 1435 * @hw: pointer to the hw struct 1436 * @cmd_flags: debug command flags 1437 * @cmd_details: pointer to command details structure or NULL 1438 * 1439 * Reset the external PHY. 1440 **/ 1441int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1442 struct i40e_asq_cmd_details *cmd_details) 1443{ 1444 struct i40e_aqc_set_phy_debug *cmd; 1445 struct libie_aq_desc desc; 1446 int status; 1447 1448 i40e_fill_default_direct_cmd_desc(&desc, 1449 i40e_aqc_opc_set_phy_debug); 1450 1451 cmd = libie_aq_raw(&desc); 1452 cmd->command_flags = cmd_flags; 1453 1454 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1455 1456 return status; 1457} 1458 1459/** 1460 * i40e_aq_add_vsi 1461 * @hw: pointer to the hw struct 1462 * @vsi_ctx: pointer to a vsi context struct 1463 * @cmd_details: pointer to command details structure or NULL 1464 * 1465 * Add a VSI context to the hardware. 1466**/ 1467int i40e_aq_add_vsi(struct i40e_hw *hw, 1468 struct i40e_vsi_context *vsi_ctx, 1469 struct i40e_asq_cmd_details *cmd_details) 1470{ 1471 struct i40e_aqc_add_get_update_vsi_completion *resp; 1472 struct i40e_aqc_add_get_update_vsi *cmd; 1473 struct libie_aq_desc desc; 1474 int status; 1475 1476 i40e_fill_default_direct_cmd_desc(&desc, 1477 i40e_aqc_opc_add_vsi); 1478 1479 resp = libie_aq_raw(&desc); 1480 cmd = libie_aq_raw(&desc); 1481 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1482 cmd->connection_type = vsi_ctx->connection_type; 1483 cmd->vf_id = vsi_ctx->vf_num; 1484 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1485 1486 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 1487 1488 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1489 sizeof(vsi_ctx->info), 1490 cmd_details, true); 1491 1492 if (status) 1493 goto aq_add_vsi_exit; 1494 1495 vsi_ctx->seid = le16_to_cpu(resp->seid); 1496 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1497 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1498 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1499 1500aq_add_vsi_exit: 1501 return status; 1502} 1503 1504/** 1505 * i40e_aq_set_default_vsi 1506 * @hw: pointer to the hw struct 1507 * @seid: vsi number 1508 * @cmd_details: pointer to command details structure or NULL 1509 **/ 1510int i40e_aq_set_default_vsi(struct i40e_hw *hw, 1511 u16 seid, 1512 struct i40e_asq_cmd_details *cmd_details) 1513{ 1514 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1515 struct libie_aq_desc desc; 1516 int status; 1517 1518 i40e_fill_default_direct_cmd_desc(&desc, 1519 i40e_aqc_opc_set_vsi_promiscuous_modes); 1520 1521 cmd = libie_aq_raw(&desc); 1522 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1523 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1524 cmd->seid = cpu_to_le16(seid); 1525 1526 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1527 1528 return status; 1529} 1530 1531/** 1532 * i40e_aq_clear_default_vsi 1533 * @hw: pointer to the hw struct 1534 * @seid: vsi number 1535 * @cmd_details: pointer to command details structure or NULL 1536 **/ 1537int i40e_aq_clear_default_vsi(struct i40e_hw *hw, 1538 u16 seid, 1539 struct i40e_asq_cmd_details *cmd_details) 1540{ 1541 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1542 struct libie_aq_desc desc; 1543 int status; 1544 1545 i40e_fill_default_direct_cmd_desc(&desc, 1546 i40e_aqc_opc_set_vsi_promiscuous_modes); 1547 1548 cmd = libie_aq_raw(&desc); 1549 cmd->promiscuous_flags = cpu_to_le16(0); 1550 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1551 cmd->seid = cpu_to_le16(seid); 1552 1553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1554 1555 return status; 1556} 1557 1558/** 1559 * i40e_aq_set_vsi_unicast_promiscuous 1560 * @hw: pointer to the hw struct 1561 * @seid: vsi number 1562 * @set: set unicast promiscuous enable/disable 1563 * @cmd_details: pointer to command details structure or NULL 1564 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 1565 **/ 1566int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1567 u16 seid, bool set, 1568 struct i40e_asq_cmd_details *cmd_details, 1569 bool rx_only_promisc) 1570{ 1571 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1572 struct libie_aq_desc desc; 1573 u16 flags = 0; 1574 int status; 1575 1576 i40e_fill_default_direct_cmd_desc(&desc, 1577 i40e_aqc_opc_set_vsi_promiscuous_modes); 1578 1579 cmd = libie_aq_raw(&desc); 1580 if (set) { 1581 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1582 if (rx_only_promisc && i40e_is_aq_api_ver_ge(hw, 1, 5)) 1583 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1584 } 1585 1586 cmd->promiscuous_flags = cpu_to_le16(flags); 1587 1588 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1589 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1590 cmd->valid_flags |= 1591 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1592 1593 cmd->seid = cpu_to_le16(seid); 1594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1595 1596 return status; 1597} 1598 1599/** 1600 * i40e_aq_set_vsi_multicast_promiscuous 1601 * @hw: pointer to the hw struct 1602 * @seid: vsi number 1603 * @set: set multicast promiscuous enable/disable 1604 * @cmd_details: pointer to command details structure or NULL 1605 **/ 1606int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1607 u16 seid, bool set, 1608 struct i40e_asq_cmd_details *cmd_details) 1609{ 1610 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1611 struct libie_aq_desc desc; 1612 u16 flags = 0; 1613 int status; 1614 1615 i40e_fill_default_direct_cmd_desc(&desc, 1616 i40e_aqc_opc_set_vsi_promiscuous_modes); 1617 1618 cmd = libie_aq_raw(&desc); 1619 if (set) 1620 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1621 1622 cmd->promiscuous_flags = cpu_to_le16(flags); 1623 1624 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1625 1626 cmd->seid = cpu_to_le16(seid); 1627 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1628 1629 return status; 1630} 1631 1632/** 1633 * i40e_aq_set_vsi_mc_promisc_on_vlan 1634 * @hw: pointer to the hw struct 1635 * @seid: vsi number 1636 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1637 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 1638 * @cmd_details: pointer to command details structure or NULL 1639 **/ 1640int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 1641 u16 seid, bool enable, 1642 u16 vid, 1643 struct i40e_asq_cmd_details *cmd_details) 1644{ 1645 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1646 struct libie_aq_desc desc; 1647 u16 flags = 0; 1648 int status; 1649 1650 i40e_fill_default_direct_cmd_desc(&desc, 1651 i40e_aqc_opc_set_vsi_promiscuous_modes); 1652 1653 cmd = libie_aq_raw(&desc); 1654 if (enable) 1655 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1656 1657 cmd->promiscuous_flags = cpu_to_le16(flags); 1658 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1659 cmd->seid = cpu_to_le16(seid); 1660 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1661 1662 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1663 cmd_details, true); 1664 1665 return status; 1666} 1667 1668/** 1669 * i40e_aq_set_vsi_uc_promisc_on_vlan 1670 * @hw: pointer to the hw struct 1671 * @seid: vsi number 1672 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 1673 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 1674 * @cmd_details: pointer to command details structure or NULL 1675 **/ 1676int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 1677 u16 seid, bool enable, 1678 u16 vid, 1679 struct i40e_asq_cmd_details *cmd_details) 1680{ 1681 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1682 struct libie_aq_desc desc; 1683 u16 flags = 0; 1684 int status; 1685 1686 i40e_fill_default_direct_cmd_desc(&desc, 1687 i40e_aqc_opc_set_vsi_promiscuous_modes); 1688 1689 cmd = libie_aq_raw(&desc); 1690 if (enable) { 1691 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1692 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1693 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1694 } 1695 1696 cmd->promiscuous_flags = cpu_to_le16(flags); 1697 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1698 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) 1699 cmd->valid_flags |= 1700 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 1701 cmd->seid = cpu_to_le16(seid); 1702 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1703 1704 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 1705 cmd_details, true); 1706 1707 return status; 1708} 1709 1710/** 1711 * i40e_aq_set_vsi_bc_promisc_on_vlan 1712 * @hw: pointer to the hw struct 1713 * @seid: vsi number 1714 * @enable: set broadcast promiscuous enable/disable for a given VLAN 1715 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 1716 * @cmd_details: pointer to command details structure or NULL 1717 **/ 1718int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 1719 u16 seid, bool enable, u16 vid, 1720 struct i40e_asq_cmd_details *cmd_details) 1721{ 1722 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1723 struct libie_aq_desc desc; 1724 u16 flags = 0; 1725 int status; 1726 1727 i40e_fill_default_direct_cmd_desc(&desc, 1728 i40e_aqc_opc_set_vsi_promiscuous_modes); 1729 1730 if (enable) 1731 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 1732 1733 cmd = libie_aq_raw(&desc); 1734 cmd->promiscuous_flags = cpu_to_le16(flags); 1735 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1736 cmd->seid = cpu_to_le16(seid); 1737 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 1738 1739 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1740 1741 return status; 1742} 1743 1744/** 1745 * i40e_aq_set_vsi_broadcast 1746 * @hw: pointer to the hw struct 1747 * @seid: vsi number 1748 * @set_filter: true to set filter, false to clear filter 1749 * @cmd_details: pointer to command details structure or NULL 1750 * 1751 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1752 **/ 1753int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1754 u16 seid, bool set_filter, 1755 struct i40e_asq_cmd_details *cmd_details) 1756{ 1757 struct i40e_aqc_set_vsi_promiscuous_modes *cmd; 1758 struct libie_aq_desc desc; 1759 int status; 1760 1761 i40e_fill_default_direct_cmd_desc(&desc, 1762 i40e_aqc_opc_set_vsi_promiscuous_modes); 1763 1764 cmd = libie_aq_raw(&desc); 1765 if (set_filter) 1766 cmd->promiscuous_flags 1767 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1768 else 1769 cmd->promiscuous_flags 1770 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1771 1772 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1773 cmd->seid = cpu_to_le16(seid); 1774 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1775 1776 return status; 1777} 1778 1779/** 1780 * i40e_aq_get_vsi_params - get VSI configuration info 1781 * @hw: pointer to the hw struct 1782 * @vsi_ctx: pointer to a vsi context struct 1783 * @cmd_details: pointer to command details structure or NULL 1784 **/ 1785int i40e_aq_get_vsi_params(struct i40e_hw *hw, 1786 struct i40e_vsi_context *vsi_ctx, 1787 struct i40e_asq_cmd_details *cmd_details) 1788{ 1789 struct i40e_aqc_add_get_update_vsi_completion *resp; 1790 struct i40e_aqc_add_get_update_vsi *cmd; 1791 struct libie_aq_desc desc; 1792 int status; 1793 1794 i40e_fill_default_direct_cmd_desc(&desc, 1795 i40e_aqc_opc_get_vsi_parameters); 1796 1797 resp = libie_aq_raw(&desc); 1798 cmd = libie_aq_raw(&desc); 1799 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1800 1801 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1802 1803 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1804 sizeof(vsi_ctx->info), NULL); 1805 1806 if (status) 1807 goto aq_get_vsi_params_exit; 1808 1809 vsi_ctx->seid = le16_to_cpu(resp->seid); 1810 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1811 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1812 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1813 1814aq_get_vsi_params_exit: 1815 return status; 1816} 1817 1818/** 1819 * i40e_aq_update_vsi_params 1820 * @hw: pointer to the hw struct 1821 * @vsi_ctx: pointer to a vsi context struct 1822 * @cmd_details: pointer to command details structure or NULL 1823 * 1824 * Update a VSI context. 1825 **/ 1826int i40e_aq_update_vsi_params(struct i40e_hw *hw, 1827 struct i40e_vsi_context *vsi_ctx, 1828 struct i40e_asq_cmd_details *cmd_details) 1829{ 1830 struct i40e_aqc_add_get_update_vsi_completion *resp; 1831 struct i40e_aqc_add_get_update_vsi *cmd; 1832 struct libie_aq_desc desc; 1833 int status; 1834 1835 i40e_fill_default_direct_cmd_desc(&desc, 1836 i40e_aqc_opc_update_vsi_parameters); 1837 resp = libie_aq_raw(&desc); 1838 cmd = libie_aq_raw(&desc); 1839 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1840 1841 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 1842 1843 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info, 1844 sizeof(vsi_ctx->info), 1845 cmd_details, true); 1846 1847 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1848 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1849 1850 return status; 1851} 1852 1853/** 1854 * i40e_aq_get_switch_config 1855 * @hw: pointer to the hardware structure 1856 * @buf: pointer to the result buffer 1857 * @buf_size: length of input buffer 1858 * @start_seid: seid to start for the report, 0 == beginning 1859 * @cmd_details: pointer to command details structure or NULL 1860 * 1861 * Fill the buf with switch configuration returned from AdminQ command 1862 **/ 1863int i40e_aq_get_switch_config(struct i40e_hw *hw, 1864 struct i40e_aqc_get_switch_config_resp *buf, 1865 u16 buf_size, u16 *start_seid, 1866 struct i40e_asq_cmd_details *cmd_details) 1867{ 1868 struct i40e_aqc_switch_seid *scfg; 1869 struct libie_aq_desc desc; 1870 int status; 1871 1872 i40e_fill_default_direct_cmd_desc(&desc, 1873 i40e_aqc_opc_get_switch_config); 1874 scfg = libie_aq_raw(&desc); 1875 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 1876 if (buf_size > I40E_AQ_LARGE_BUF) 1877 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 1878 scfg->seid = cpu_to_le16(*start_seid); 1879 1880 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1881 *start_seid = le16_to_cpu(scfg->seid); 1882 1883 return status; 1884} 1885 1886/** 1887 * i40e_aq_set_switch_config 1888 * @hw: pointer to the hardware structure 1889 * @flags: bit flag values to set 1890 * @mode: cloud filter mode 1891 * @valid_flags: which bit flags to set 1892 * @mode: cloud filter mode 1893 * @cmd_details: pointer to command details structure or NULL 1894 * 1895 * Set switch configuration bits 1896 **/ 1897int i40e_aq_set_switch_config(struct i40e_hw *hw, 1898 u16 flags, 1899 u16 valid_flags, u8 mode, 1900 struct i40e_asq_cmd_details *cmd_details) 1901{ 1902 struct i40e_aqc_set_switch_config *scfg; 1903 struct libie_aq_desc desc; 1904 int status; 1905 1906 i40e_fill_default_direct_cmd_desc(&desc, 1907 i40e_aqc_opc_set_switch_config); 1908 scfg = libie_aq_raw(&desc); 1909 scfg->flags = cpu_to_le16(flags); 1910 scfg->valid_flags = cpu_to_le16(valid_flags); 1911 scfg->mode = mode; 1912 if (test_bit(I40E_HW_CAP_802_1AD, hw->caps)) { 1913 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 1914 scfg->first_tag = cpu_to_le16(hw->first_tag); 1915 scfg->second_tag = cpu_to_le16(hw->second_tag); 1916 } 1917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1918 1919 return status; 1920} 1921 1922/** 1923 * i40e_aq_get_firmware_version 1924 * @hw: pointer to the hw struct 1925 * @fw_major_version: firmware major version 1926 * @fw_minor_version: firmware minor version 1927 * @fw_build: firmware build number 1928 * @api_major_version: major queue version 1929 * @api_minor_version: minor queue version 1930 * @cmd_details: pointer to command details structure or NULL 1931 * 1932 * Get the firmware version from the admin queue commands 1933 **/ 1934int i40e_aq_get_firmware_version(struct i40e_hw *hw, 1935 u16 *fw_major_version, u16 *fw_minor_version, 1936 u32 *fw_build, 1937 u16 *api_major_version, u16 *api_minor_version, 1938 struct i40e_asq_cmd_details *cmd_details) 1939{ 1940 struct i40e_aqc_get_version *resp; 1941 struct libie_aq_desc desc; 1942 int status; 1943 1944 resp = libie_aq_raw(&desc); 1945 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1946 1947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1948 1949 if (!status) { 1950 if (fw_major_version) 1951 *fw_major_version = le16_to_cpu(resp->fw_major); 1952 if (fw_minor_version) 1953 *fw_minor_version = le16_to_cpu(resp->fw_minor); 1954 if (fw_build) 1955 *fw_build = le32_to_cpu(resp->fw_build); 1956 if (api_major_version) 1957 *api_major_version = le16_to_cpu(resp->api_major); 1958 if (api_minor_version) 1959 *api_minor_version = le16_to_cpu(resp->api_minor); 1960 } 1961 1962 return status; 1963} 1964 1965/** 1966 * i40e_aq_send_driver_version 1967 * @hw: pointer to the hw struct 1968 * @dv: driver's major, minor version 1969 * @cmd_details: pointer to command details structure or NULL 1970 * 1971 * Send the driver version to the firmware 1972 **/ 1973int i40e_aq_send_driver_version(struct i40e_hw *hw, 1974 struct i40e_driver_version *dv, 1975 struct i40e_asq_cmd_details *cmd_details) 1976{ 1977 struct libie_aqc_driver_ver *cmd; 1978 struct libie_aq_desc desc; 1979 int status; 1980 u16 len; 1981 1982 if (dv == NULL) 1983 return -EINVAL; 1984 1985 cmd = libie_aq_raw(&desc); 1986 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 1987 1988 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD); 1989 cmd->major_ver = dv->major_version; 1990 cmd->minor_ver = dv->minor_version; 1991 cmd->build_ver = dv->build_version; 1992 cmd->subbuild_ver = dv->subbuild_version; 1993 1994 len = 0; 1995 while (len < sizeof(dv->driver_string) && 1996 (dv->driver_string[len] < 0x80) && 1997 dv->driver_string[len]) 1998 len++; 1999 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2000 len, cmd_details); 2001 2002 return status; 2003} 2004 2005/** 2006 * i40e_get_link_status - get status of the HW network link 2007 * @hw: pointer to the hw struct 2008 * @link_up: pointer to bool (true/false = linkup/linkdown) 2009 * 2010 * Variable link_up true if link is up, false if link is down. 2011 * The variable link_up is invalid if returned value of status != 0 2012 * 2013 * Side effect: LinkStatusEvent reporting becomes enabled 2014 **/ 2015int i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2016{ 2017 int status = 0; 2018 2019 if (hw->phy.get_link_info) { 2020 status = i40e_update_link_info(hw); 2021 2022 if (status) 2023 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2024 status); 2025 } 2026 2027 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2028 2029 return status; 2030} 2031 2032/** 2033 * i40e_update_link_info - update status of the HW network link 2034 * @hw: pointer to the hw struct 2035 **/ 2036noinline_for_stack int i40e_update_link_info(struct i40e_hw *hw) 2037{ 2038 struct i40e_aq_get_phy_abilities_resp abilities; 2039 int status = 0; 2040 2041 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2042 if (status) 2043 return status; 2044 2045 /* extra checking needed to ensure link info to user is timely */ 2046 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2047 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2048 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2049 status = i40e_aq_get_phy_capabilities(hw, false, false, 2050 &abilities, NULL); 2051 if (status) 2052 return status; 2053 2054 if (abilities.fec_cfg_curr_mod_ext_info & 2055 I40E_AQ_ENABLE_FEC_AUTO) 2056 hw->phy.link_info.req_fec_info = 2057 (I40E_AQ_REQUEST_FEC_KR | 2058 I40E_AQ_REQUEST_FEC_RS); 2059 else 2060 hw->phy.link_info.req_fec_info = 2061 abilities.fec_cfg_curr_mod_ext_info & 2062 (I40E_AQ_REQUEST_FEC_KR | 2063 I40E_AQ_REQUEST_FEC_RS); 2064 2065 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2066 sizeof(hw->phy.link_info.module_type)); 2067 } 2068 2069 return status; 2070} 2071 2072/** 2073 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2074 * @hw: pointer to the hw struct 2075 * @uplink_seid: the MAC or other gizmo SEID 2076 * @downlink_seid: the VSI SEID 2077 * @enabled_tc: bitmap of TCs to be enabled 2078 * @default_port: true for default port VSI, false for control port 2079 * @veb_seid: pointer to where to put the resulting VEB SEID 2080 * @enable_stats: true to turn on VEB stats 2081 * @cmd_details: pointer to command details structure or NULL 2082 * 2083 * This asks the FW to add a VEB between the uplink and downlink 2084 * elements. If the uplink SEID is 0, this will be a floating VEB. 2085 **/ 2086int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2087 u16 downlink_seid, u8 enabled_tc, 2088 bool default_port, u16 *veb_seid, 2089 bool enable_stats, 2090 struct i40e_asq_cmd_details *cmd_details) 2091{ 2092 struct i40e_aqc_add_veb_completion *resp; 2093 struct i40e_aqc_add_veb *cmd; 2094 struct libie_aq_desc desc; 2095 u16 veb_flags = 0; 2096 int status; 2097 2098 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2099 if (!!uplink_seid != !!downlink_seid) 2100 return -EINVAL; 2101 2102 resp = libie_aq_raw(&desc); 2103 cmd = libie_aq_raw(&desc); 2104 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2105 2106 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2107 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2108 cmd->enable_tcs = enabled_tc; 2109 if (!uplink_seid) 2110 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2111 if (default_port) 2112 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2113 else 2114 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2115 2116 /* reverse logic here: set the bitflag to disable the stats */ 2117 if (!enable_stats) 2118 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2119 2120 cmd->veb_flags = cpu_to_le16(veb_flags); 2121 2122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2123 2124 if (!status && veb_seid) 2125 *veb_seid = le16_to_cpu(resp->veb_seid); 2126 2127 return status; 2128} 2129 2130/** 2131 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2132 * @hw: pointer to the hw struct 2133 * @veb_seid: the SEID of the VEB to query 2134 * @switch_id: the uplink switch id 2135 * @floating: set to true if the VEB is floating 2136 * @statistic_index: index of the stats counter block for this VEB 2137 * @vebs_used: number of VEB's used by function 2138 * @vebs_free: total VEB's not reserved by any function 2139 * @cmd_details: pointer to command details structure or NULL 2140 * 2141 * This retrieves the parameters for a particular VEB, specified by 2142 * uplink_seid, and returns them to the caller. 2143 **/ 2144int i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2145 u16 veb_seid, u16 *switch_id, 2146 bool *floating, u16 *statistic_index, 2147 u16 *vebs_used, u16 *vebs_free, 2148 struct i40e_asq_cmd_details *cmd_details) 2149{ 2150 struct i40e_aqc_get_veb_parameters_completion *cmd_resp; 2151 struct libie_aq_desc desc; 2152 int status; 2153 2154 if (veb_seid == 0) 2155 return -EINVAL; 2156 2157 cmd_resp = libie_aq_raw(&desc); 2158 i40e_fill_default_direct_cmd_desc(&desc, 2159 i40e_aqc_opc_get_veb_parameters); 2160 cmd_resp->seid = cpu_to_le16(veb_seid); 2161 2162 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2163 if (status) 2164 goto get_veb_exit; 2165 2166 if (switch_id) 2167 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2168 if (statistic_index) 2169 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2170 if (vebs_used) 2171 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2172 if (vebs_free) 2173 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2174 if (floating) { 2175 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2176 2177 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2178 *floating = true; 2179 else 2180 *floating = false; 2181 } 2182 2183get_veb_exit: 2184 return status; 2185} 2186 2187/** 2188 * i40e_prepare_add_macvlan 2189 * @mv_list: list of macvlans to be added 2190 * @desc: pointer to AQ descriptor structure 2191 * @count: length of the list 2192 * @seid: VSI for the mac address 2193 * 2194 * Internal helper function that prepares the add macvlan request 2195 * and returns the buffer size. 2196 **/ 2197static u16 2198i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list, 2199 struct libie_aq_desc *desc, u16 count, u16 seid) 2200{ 2201 struct i40e_aqc_macvlan *cmd = libie_aq_raw(desc); 2202 u16 buf_size; 2203 int i; 2204 2205 buf_size = count * sizeof(*mv_list); 2206 2207 /* prep the rest of the request */ 2208 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan); 2209 cmd->num_addresses = cpu_to_le16(count); 2210 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2211 cmd->seid[1] = 0; 2212 cmd->seid[2] = 0; 2213 2214 for (i = 0; i < count; i++) 2215 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2216 mv_list[i].flags |= 2217 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2218 2219 desc->flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2220 if (buf_size > I40E_AQ_LARGE_BUF) 2221 desc->flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2222 2223 return buf_size; 2224} 2225 2226/** 2227 * i40e_aq_add_macvlan 2228 * @hw: pointer to the hw struct 2229 * @seid: VSI for the mac address 2230 * @mv_list: list of macvlans to be added 2231 * @count: length of the list 2232 * @cmd_details: pointer to command details structure or NULL 2233 * 2234 * Add MAC/VLAN addresses to the HW filtering 2235 **/ 2236int 2237i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2238 struct i40e_aqc_add_macvlan_element_data *mv_list, 2239 u16 count, struct i40e_asq_cmd_details *cmd_details) 2240{ 2241 struct libie_aq_desc desc; 2242 u16 buf_size; 2243 2244 if (count == 0 || !mv_list || !hw) 2245 return -EINVAL; 2246 2247 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2248 2249 return i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2250 cmd_details, true); 2251} 2252 2253/** 2254 * i40e_aq_add_macvlan_v2 2255 * @hw: pointer to the hw struct 2256 * @seid: VSI for the mac address 2257 * @mv_list: list of macvlans to be added 2258 * @count: length of the list 2259 * @cmd_details: pointer to command details structure or NULL 2260 * @aq_status: pointer to Admin Queue status return value 2261 * 2262 * Add MAC/VLAN addresses to the HW filtering. 2263 * The _v2 version returns the last Admin Queue status in aq_status 2264 * to avoid race conditions in access to hw->aq.asq_last_status. 2265 * It also calls _v2 versions of asq_send_command functions to 2266 * get the aq_status on the stack. 2267 **/ 2268int 2269i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid, 2270 struct i40e_aqc_add_macvlan_element_data *mv_list, 2271 u16 count, struct i40e_asq_cmd_details *cmd_details, 2272 enum libie_aq_err *aq_status) 2273{ 2274 struct libie_aq_desc desc; 2275 u16 buf_size; 2276 2277 if (count == 0 || !mv_list || !hw) 2278 return -EINVAL; 2279 2280 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid); 2281 2282 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2283 cmd_details, true, aq_status); 2284} 2285 2286/** 2287 * i40e_aq_remove_macvlan 2288 * @hw: pointer to the hw struct 2289 * @seid: VSI for the mac address 2290 * @mv_list: list of macvlans to be removed 2291 * @count: length of the list 2292 * @cmd_details: pointer to command details structure or NULL 2293 * 2294 * Remove MAC/VLAN addresses from the HW filtering 2295 **/ 2296int 2297i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2298 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2299 u16 count, struct i40e_asq_cmd_details *cmd_details) 2300{ 2301 struct i40e_aqc_macvlan *cmd; 2302 struct libie_aq_desc desc; 2303 u16 buf_size; 2304 int status; 2305 2306 if (count == 0 || !mv_list || !hw) 2307 return -EINVAL; 2308 2309 buf_size = count * sizeof(*mv_list); 2310 2311 /* prep the rest of the request */ 2312 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2313 cmd = libie_aq_raw(&desc); 2314 cmd->num_addresses = cpu_to_le16(count); 2315 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2316 cmd->seid[1] = 0; 2317 cmd->seid[2] = 0; 2318 2319 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2320 if (buf_size > I40E_AQ_LARGE_BUF) 2321 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2322 2323 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size, 2324 cmd_details, true); 2325 2326 return status; 2327} 2328 2329/** 2330 * i40e_aq_remove_macvlan_v2 2331 * @hw: pointer to the hw struct 2332 * @seid: VSI for the mac address 2333 * @mv_list: list of macvlans to be removed 2334 * @count: length of the list 2335 * @cmd_details: pointer to command details structure or NULL 2336 * @aq_status: pointer to Admin Queue status return value 2337 * 2338 * Remove MAC/VLAN addresses from the HW filtering. 2339 * The _v2 version returns the last Admin Queue status in aq_status 2340 * to avoid race conditions in access to hw->aq.asq_last_status. 2341 * It also calls _v2 versions of asq_send_command functions to 2342 * get the aq_status on the stack. 2343 **/ 2344int 2345i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid, 2346 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2347 u16 count, struct i40e_asq_cmd_details *cmd_details, 2348 enum libie_aq_err *aq_status) 2349{ 2350 struct i40e_aqc_macvlan *cmd; 2351 struct libie_aq_desc desc; 2352 u16 buf_size; 2353 2354 if (count == 0 || !mv_list || !hw) 2355 return -EINVAL; 2356 2357 buf_size = count * sizeof(*mv_list); 2358 2359 /* prep the rest of the request */ 2360 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2361 cmd = libie_aq_raw(&desc); 2362 cmd->num_addresses = cpu_to_le16(count); 2363 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2364 cmd->seid[1] = 0; 2365 cmd->seid[2] = 0; 2366 2367 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2368 if (buf_size > I40E_AQ_LARGE_BUF) 2369 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2370 2371 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size, 2372 cmd_details, true, aq_status); 2373} 2374 2375/** 2376 * i40e_aq_send_msg_to_vf 2377 * @hw: pointer to the hardware structure 2378 * @vfid: VF id to send msg 2379 * @v_opcode: opcodes for VF-PF communication 2380 * @v_retval: return error code 2381 * @msg: pointer to the msg buffer 2382 * @msglen: msg length 2383 * @cmd_details: pointer to command details 2384 * 2385 * send msg to vf 2386 **/ 2387int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2388 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2389 struct i40e_asq_cmd_details *cmd_details) 2390{ 2391 struct i40e_aqc_pf_vf_message *cmd; 2392 struct libie_aq_desc desc; 2393 int status; 2394 2395 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2396 cmd = libie_aq_raw(&desc); 2397 cmd->id = cpu_to_le32(vfid); 2398 desc.cookie_high = cpu_to_le32(v_opcode); 2399 desc.cookie_low = cpu_to_le32(v_retval); 2400 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_SI); 2401 if (msglen) { 2402 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | 2403 LIBIE_AQ_FLAG_RD)); 2404 if (msglen > I40E_AQ_LARGE_BUF) 2405 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2406 desc.datalen = cpu_to_le16(msglen); 2407 } 2408 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2409 2410 return status; 2411} 2412 2413/** 2414 * i40e_aq_debug_read_register 2415 * @hw: pointer to the hw struct 2416 * @reg_addr: register address 2417 * @reg_val: register value 2418 * @cmd_details: pointer to command details structure or NULL 2419 * 2420 * Read the register using the admin queue commands 2421 **/ 2422int i40e_aq_debug_read_register(struct i40e_hw *hw, 2423 u32 reg_addr, u64 *reg_val, 2424 struct i40e_asq_cmd_details *cmd_details) 2425{ 2426 struct i40e_aqc_debug_reg_read_write *cmd_resp; 2427 struct libie_aq_desc desc; 2428 int status; 2429 2430 if (reg_val == NULL) 2431 return -EINVAL; 2432 2433 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2434 2435 cmd_resp = libie_aq_raw(&desc); 2436 cmd_resp->address = cpu_to_le32(reg_addr); 2437 2438 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2439 2440 if (!status) { 2441 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2442 (u64)le32_to_cpu(cmd_resp->value_low); 2443 } 2444 2445 return status; 2446} 2447 2448/** 2449 * i40e_aq_debug_write_register 2450 * @hw: pointer to the hw struct 2451 * @reg_addr: register address 2452 * @reg_val: register value 2453 * @cmd_details: pointer to command details structure or NULL 2454 * 2455 * Write to a register using the admin queue commands 2456 **/ 2457int i40e_aq_debug_write_register(struct i40e_hw *hw, 2458 u32 reg_addr, u64 reg_val, 2459 struct i40e_asq_cmd_details *cmd_details) 2460{ 2461 struct i40e_aqc_debug_reg_read_write *cmd; 2462 struct libie_aq_desc desc; 2463 int status; 2464 2465 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2466 2467 cmd = libie_aq_raw(&desc); 2468 cmd->address = cpu_to_le32(reg_addr); 2469 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2470 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2471 2472 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2473 2474 return status; 2475} 2476 2477/** 2478 * i40e_aq_request_resource 2479 * @hw: pointer to the hw struct 2480 * @resource: resource id 2481 * @access: access type 2482 * @sdp_number: resource number 2483 * @timeout: the maximum time in ms that the driver may hold the resource 2484 * @cmd_details: pointer to command details structure or NULL 2485 * 2486 * requests common resource using the admin queue commands 2487 **/ 2488int i40e_aq_request_resource(struct i40e_hw *hw, 2489 enum i40e_aq_resources_ids resource, 2490 enum i40e_aq_resource_access_type access, 2491 u8 sdp_number, u64 *timeout, 2492 struct i40e_asq_cmd_details *cmd_details) 2493{ 2494 struct libie_aqc_req_res *cmd_resp; 2495 struct libie_aq_desc desc; 2496 int status; 2497 2498 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2499 2500 cmd_resp = libie_aq_raw(&desc); 2501 cmd_resp->res_id = cpu_to_le16(resource); 2502 cmd_resp->access_type = cpu_to_le16(access); 2503 cmd_resp->res_number = cpu_to_le32(sdp_number); 2504 2505 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2506 /* The completion specifies the maximum time in ms that the driver 2507 * may hold the resource in the Timeout field. 2508 * If the resource is held by someone else, the command completes with 2509 * busy return value and the timeout field indicates the maximum time 2510 * the current owner of the resource has to free it. 2511 */ 2512 if (!status || hw->aq.asq_last_status == LIBIE_AQ_RC_EBUSY) 2513 *timeout = le32_to_cpu(cmd_resp->timeout); 2514 2515 return status; 2516} 2517 2518/** 2519 * i40e_aq_release_resource 2520 * @hw: pointer to the hw struct 2521 * @resource: resource id 2522 * @sdp_number: resource number 2523 * @cmd_details: pointer to command details structure or NULL 2524 * 2525 * release common resource using the admin queue commands 2526 **/ 2527int i40e_aq_release_resource(struct i40e_hw *hw, 2528 enum i40e_aq_resources_ids resource, 2529 u8 sdp_number, 2530 struct i40e_asq_cmd_details *cmd_details) 2531{ 2532 struct libie_aqc_req_res *cmd; 2533 struct libie_aq_desc desc; 2534 int status; 2535 2536 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2537 2538 cmd = libie_aq_raw(&desc); 2539 cmd->res_id = cpu_to_le16(resource); 2540 cmd->res_number = cpu_to_le32(sdp_number); 2541 2542 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2543 2544 return status; 2545} 2546 2547/** 2548 * i40e_aq_read_nvm 2549 * @hw: pointer to the hw struct 2550 * @module_pointer: module pointer location in words from the NVM beginning 2551 * @offset: byte offset from the module beginning 2552 * @length: length of the section to be read (in bytes from the offset) 2553 * @data: command buffer (size [bytes] = length) 2554 * @last_command: tells if this is the last command in a series 2555 * @cmd_details: pointer to command details structure or NULL 2556 * 2557 * Read the NVM using the admin queue commands 2558 **/ 2559int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2560 u32 offset, u16 length, void *data, 2561 bool last_command, 2562 struct i40e_asq_cmd_details *cmd_details) 2563{ 2564 struct i40e_aqc_nvm_update *cmd; 2565 struct libie_aq_desc desc; 2566 int status; 2567 2568 /* In offset the highest byte must be zeroed. */ 2569 if (offset & 0xFF000000) { 2570 status = -EINVAL; 2571 goto i40e_aq_read_nvm_exit; 2572 } 2573 2574 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2575 2576 cmd = libie_aq_raw(&desc); 2577 /* If this is the last command in a series, set the proper flag. */ 2578 if (last_command) 2579 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2580 cmd->module_pointer = module_pointer; 2581 cmd->offset = cpu_to_le32(offset); 2582 cmd->length = cpu_to_le16(length); 2583 2584 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2585 if (length > I40E_AQ_LARGE_BUF) 2586 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2587 2588 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2589 2590i40e_aq_read_nvm_exit: 2591 return status; 2592} 2593 2594/** 2595 * i40e_aq_erase_nvm 2596 * @hw: pointer to the hw struct 2597 * @module_pointer: module pointer location in words from the NVM beginning 2598 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2599 * @length: length of the section to be erased (expressed in 4 KB) 2600 * @last_command: tells if this is the last command in a series 2601 * @cmd_details: pointer to command details structure or NULL 2602 * 2603 * Erase the NVM sector using the admin queue commands 2604 **/ 2605int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2606 u32 offset, u16 length, bool last_command, 2607 struct i40e_asq_cmd_details *cmd_details) 2608{ 2609 struct i40e_aqc_nvm_update *cmd; 2610 struct libie_aq_desc desc; 2611 int status; 2612 2613 /* In offset the highest byte must be zeroed. */ 2614 if (offset & 0xFF000000) { 2615 status = -EINVAL; 2616 goto i40e_aq_erase_nvm_exit; 2617 } 2618 2619 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2620 2621 cmd = libie_aq_raw(&desc); 2622 /* If this is the last command in a series, set the proper flag. */ 2623 if (last_command) 2624 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2625 cmd->module_pointer = module_pointer; 2626 cmd->offset = cpu_to_le32(offset); 2627 cmd->length = cpu_to_le16(length); 2628 2629 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2630 2631i40e_aq_erase_nvm_exit: 2632 return status; 2633} 2634 2635/** 2636 * i40e_parse_discover_capabilities 2637 * @hw: pointer to the hw struct 2638 * @buff: pointer to a buffer containing device/function capability records 2639 * @cap_count: number of capability records in the list 2640 * @list_type_opc: type of capabilities list to parse 2641 * 2642 * Parse the device/function capabilities list. 2643 **/ 2644static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2645 u32 cap_count, 2646 enum i40e_admin_queue_opc list_type_opc) 2647{ 2648 struct libie_aqc_list_caps_elem *cap; 2649 u32 valid_functions, num_functions; 2650 u32 number, logical_id, phys_id; 2651 struct i40e_hw_capabilities *p; 2652 u16 id, ocp_cfg_word0; 2653 u8 major_rev; 2654 int status; 2655 u32 i = 0; 2656 2657 cap = (struct libie_aqc_list_caps_elem *)buff; 2658 2659 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2660 p = &hw->dev_caps; 2661 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2662 p = &hw->func_caps; 2663 else 2664 return; 2665 2666 for (i = 0; i < cap_count; i++, cap++) { 2667 id = le16_to_cpu(cap->cap); 2668 number = le32_to_cpu(cap->number); 2669 logical_id = le32_to_cpu(cap->logical_id); 2670 phys_id = le32_to_cpu(cap->phys_id); 2671 major_rev = cap->major_ver; 2672 2673 switch (id) { 2674 case LIBIE_AQC_CAPS_SWITCH_MODE: 2675 p->switch_mode = number; 2676 break; 2677 case LIBIE_AQC_CAPS_MNG_MODE: 2678 p->management_mode = number; 2679 if (major_rev > 1) { 2680 p->mng_protocols_over_mctp = logical_id; 2681 i40e_debug(hw, I40E_DEBUG_INIT, 2682 "HW Capability: Protocols over MCTP = %d\n", 2683 p->mng_protocols_over_mctp); 2684 } else { 2685 p->mng_protocols_over_mctp = 0; 2686 } 2687 break; 2688 case LIBIE_AQC_CAPS_NPAR_ACTIVE: 2689 p->npar_enable = number; 2690 break; 2691 case LIBIE_AQC_CAPS_OS2BMC_CAP: 2692 p->os2bmc = number; 2693 break; 2694 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2695 p->valid_functions = number; 2696 break; 2697 case LIBIE_AQC_CAPS_SRIOV: 2698 if (number == 1) 2699 p->sr_iov_1_1 = true; 2700 break; 2701 case LIBIE_AQC_CAPS_VF: 2702 p->num_vfs = number; 2703 p->vf_base_id = logical_id; 2704 break; 2705 case LIBIE_AQC_CAPS_VMDQ: 2706 if (number == 1) 2707 p->vmdq = true; 2708 break; 2709 case LIBIE_AQC_CAPS_8021QBG: 2710 if (number == 1) 2711 p->evb_802_1_qbg = true; 2712 break; 2713 case LIBIE_AQC_CAPS_8021QBR: 2714 if (number == 1) 2715 p->evb_802_1_qbh = true; 2716 break; 2717 case LIBIE_AQC_CAPS_VSI: 2718 p->num_vsis = number; 2719 break; 2720 case LIBIE_AQC_CAPS_DCB: 2721 if (number == 1) { 2722 p->dcb = true; 2723 p->enabled_tcmap = logical_id; 2724 p->maxtc = phys_id; 2725 } 2726 break; 2727 case LIBIE_AQC_CAPS_FCOE: 2728 if (number == 1) 2729 p->fcoe = true; 2730 break; 2731 case LIBIE_AQC_CAPS_ISCSI: 2732 if (number == 1) 2733 p->iscsi = true; 2734 break; 2735 case LIBIE_AQC_CAPS_RSS: 2736 p->rss = true; 2737 p->rss_table_size = number; 2738 p->rss_table_entry_width = logical_id; 2739 break; 2740 case LIBIE_AQC_CAPS_RXQS: 2741 p->num_rx_qp = number; 2742 p->base_queue = phys_id; 2743 break; 2744 case LIBIE_AQC_CAPS_TXQS: 2745 p->num_tx_qp = number; 2746 p->base_queue = phys_id; 2747 break; 2748 case LIBIE_AQC_CAPS_MSIX: 2749 p->num_msix_vectors = number; 2750 i40e_debug(hw, I40E_DEBUG_INIT, 2751 "HW Capability: MSIX vector count = %d\n", 2752 p->num_msix_vectors); 2753 break; 2754 case LIBIE_AQC_CAPS_VF_MSIX: 2755 p->num_msix_vectors_vf = number; 2756 break; 2757 case LIBIE_AQC_CAPS_FLEX10: 2758 if (major_rev == 1) { 2759 if (number == 1) { 2760 p->flex10_enable = true; 2761 p->flex10_capable = true; 2762 } 2763 } else { 2764 /* Capability revision >= 2 */ 2765 if (number & 1) 2766 p->flex10_enable = true; 2767 if (number & 2) 2768 p->flex10_capable = true; 2769 } 2770 p->flex10_mode = logical_id; 2771 p->flex10_status = phys_id; 2772 break; 2773 case LIBIE_AQC_CAPS_CEM: 2774 if (number == 1) 2775 p->mgmt_cem = true; 2776 break; 2777 case LIBIE_AQC_CAPS_RDMA: 2778 if (number == 1) 2779 p->iwarp = true; 2780 break; 2781 case LIBIE_AQC_CAPS_LED: 2782 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2783 p->led[phys_id] = true; 2784 break; 2785 case LIBIE_AQC_CAPS_SDP: 2786 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2787 p->sdp[phys_id] = true; 2788 break; 2789 case LIBIE_AQC_CAPS_MDIO: 2790 if (number == 1) { 2791 p->mdio_port_num = phys_id; 2792 p->mdio_port_mode = logical_id; 2793 } 2794 break; 2795 case LIBIE_AQC_CAPS_1588: 2796 if (number == 1) 2797 p->ieee_1588 = true; 2798 break; 2799 case LIBIE_AQC_CAPS_FD: 2800 p->fd = true; 2801 p->fd_filters_guaranteed = number; 2802 p->fd_filters_best_effort = logical_id; 2803 break; 2804 case LIBIE_AQC_CAPS_WSR_PROT: 2805 p->wr_csr_prot = (u64)number; 2806 p->wr_csr_prot |= (u64)logical_id << 32; 2807 break; 2808 case LIBIE_AQC_CAPS_NVM_MGMT: 2809 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 2810 p->sec_rev_disabled = true; 2811 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 2812 p->update_disabled = true; 2813 break; 2814 default: 2815 break; 2816 } 2817 } 2818 2819 if (p->fcoe) 2820 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 2821 2822 /* Software override ensuring FCoE is disabled if npar or mfp 2823 * mode because it is not supported in these modes. 2824 */ 2825 if (p->npar_enable || p->flex10_enable) 2826 p->fcoe = false; 2827 2828 /* count the enabled ports (aka the "not disabled" ports) */ 2829 hw->num_ports = 0; 2830 for (i = 0; i < 4; i++) { 2831 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 2832 u64 port_cfg = 0; 2833 2834 /* use AQ read to get the physical register offset instead 2835 * of the port relative offset 2836 */ 2837 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 2838 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 2839 hw->num_ports++; 2840 } 2841 2842 /* OCP cards case: if a mezz is removed the Ethernet port is at 2843 * disabled state in PRTGEN_CNF register. Additional NVM read is 2844 * needed in order to check if we are dealing with OCP card. 2845 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 2846 * physical ports results in wrong partition id calculation and thus 2847 * not supporting WoL. 2848 */ 2849 if (hw->mac.type == I40E_MAC_X722) { 2850 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) { 2851 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 2852 2 * I40E_SR_OCP_CFG_WORD0, 2853 sizeof(ocp_cfg_word0), 2854 &ocp_cfg_word0, true, NULL); 2855 if (!status && 2856 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 2857 hw->num_ports = 4; 2858 i40e_release_nvm(hw); 2859 } 2860 } 2861 2862 valid_functions = p->valid_functions; 2863 num_functions = 0; 2864 while (valid_functions) { 2865 if (valid_functions & 1) 2866 num_functions++; 2867 valid_functions >>= 1; 2868 } 2869 2870 /* partition id is 1-based, and functions are evenly spread 2871 * across the ports as partitions 2872 */ 2873 if (hw->num_ports != 0) { 2874 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 2875 hw->num_partitions = num_functions / hw->num_ports; 2876 } 2877 2878 /* additional HW specific goodies that might 2879 * someday be HW version specific 2880 */ 2881 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2882} 2883 2884/** 2885 * i40e_aq_discover_capabilities 2886 * @hw: pointer to the hw struct 2887 * @buff: a virtual buffer to hold the capabilities 2888 * @buff_size: Size of the virtual buffer 2889 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2890 * @list_type_opc: capabilities type to discover - pass in the command opcode 2891 * @cmd_details: pointer to command details structure or NULL 2892 * 2893 * Get the device capabilities descriptions from the firmware 2894 **/ 2895int i40e_aq_discover_capabilities(struct i40e_hw *hw, 2896 void *buff, u16 buff_size, u16 *data_size, 2897 enum i40e_admin_queue_opc list_type_opc, 2898 struct i40e_asq_cmd_details *cmd_details) 2899{ 2900 struct libie_aqc_list_caps *cmd; 2901 struct libie_aq_desc desc; 2902 int status = 0; 2903 2904 cmd = libie_aq_raw(&desc); 2905 2906 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2907 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 2908 status = -EINVAL; 2909 goto exit; 2910 } 2911 2912 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2913 2914 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 2915 if (buff_size > I40E_AQ_LARGE_BUF) 2916 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2917 2918 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2919 *data_size = le16_to_cpu(desc.datalen); 2920 2921 if (status) 2922 goto exit; 2923 2924 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 2925 list_type_opc); 2926 2927exit: 2928 return status; 2929} 2930 2931/** 2932 * i40e_aq_update_nvm 2933 * @hw: pointer to the hw struct 2934 * @module_pointer: module pointer location in words from the NVM beginning 2935 * @offset: byte offset from the module beginning 2936 * @length: length of the section to be written (in bytes from the offset) 2937 * @data: command buffer (size [bytes] = length) 2938 * @last_command: tells if this is the last command in a series 2939 * @preservation_flags: Preservation mode flags 2940 * @cmd_details: pointer to command details structure or NULL 2941 * 2942 * Update the NVM using the admin queue commands 2943 **/ 2944int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 2945 u32 offset, u16 length, void *data, 2946 bool last_command, u8 preservation_flags, 2947 struct i40e_asq_cmd_details *cmd_details) 2948{ 2949 struct i40e_aqc_nvm_update *cmd; 2950 struct libie_aq_desc desc; 2951 int status; 2952 2953 /* In offset the highest byte must be zeroed. */ 2954 if (offset & 0xFF000000) { 2955 status = -EINVAL; 2956 goto i40e_aq_update_nvm_exit; 2957 } 2958 2959 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2960 2961 cmd = libie_aq_raw(&desc); 2962 /* If this is the last command in a series, set the proper flag. */ 2963 if (last_command) 2964 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2965 if (hw->mac.type == I40E_MAC_X722) { 2966 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 2967 cmd->command_flags |= 2968 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 2969 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 2970 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 2971 cmd->command_flags |= 2972 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 2973 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 2974 } 2975 cmd->module_pointer = module_pointer; 2976 cmd->offset = cpu_to_le32(offset); 2977 cmd->length = cpu_to_le16(length); 2978 2979 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 2980 if (length > I40E_AQ_LARGE_BUF) 2981 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 2982 2983 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2984 2985i40e_aq_update_nvm_exit: 2986 return status; 2987} 2988 2989/** 2990 * i40e_aq_get_lldp_mib 2991 * @hw: pointer to the hw struct 2992 * @bridge_type: type of bridge requested 2993 * @mib_type: Local, Remote or both Local and Remote MIBs 2994 * @buff: pointer to a user supplied buffer to store the MIB block 2995 * @buff_size: size of the buffer (in bytes) 2996 * @local_len : length of the returned Local LLDP MIB 2997 * @remote_len: length of the returned Remote LLDP MIB 2998 * @cmd_details: pointer to command details structure or NULL 2999 * 3000 * Requests the complete LLDP MIB (entire packet). 3001 **/ 3002int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3003 u8 mib_type, void *buff, u16 buff_size, 3004 u16 *local_len, u16 *remote_len, 3005 struct i40e_asq_cmd_details *cmd_details) 3006{ 3007 struct i40e_aqc_lldp_get_mib *resp; 3008 struct i40e_aqc_lldp_get_mib *cmd; 3009 struct libie_aq_desc desc; 3010 int status; 3011 3012 if (buff_size == 0 || !buff) 3013 return -EINVAL; 3014 3015 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3016 /* Indirect Command */ 3017 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3018 3019 resp = libie_aq_raw(&desc); 3020 cmd = libie_aq_raw(&desc); 3021 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3022 cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type); 3023 3024 desc.datalen = cpu_to_le16(buff_size); 3025 3026 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3027 if (buff_size > I40E_AQ_LARGE_BUF) 3028 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3029 3030 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3031 if (!status) { 3032 if (local_len != NULL) 3033 *local_len = le16_to_cpu(resp->local_len); 3034 if (remote_len != NULL) 3035 *remote_len = le16_to_cpu(resp->remote_len); 3036 } 3037 3038 return status; 3039} 3040 3041/** 3042 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3043 * @hw: pointer to the hw struct 3044 * @mib_type: Local, Remote or both Local and Remote MIBs 3045 * @buff: pointer to a user supplied buffer to store the MIB block 3046 * @buff_size: size of the buffer (in bytes) 3047 * @cmd_details: pointer to command details structure or NULL 3048 * 3049 * Set the LLDP MIB. 3050 **/ 3051int 3052i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3053 u8 mib_type, void *buff, u16 buff_size, 3054 struct i40e_asq_cmd_details *cmd_details) 3055{ 3056 struct i40e_aqc_lldp_set_local_mib *cmd; 3057 struct libie_aq_desc desc; 3058 int status; 3059 3060 cmd = libie_aq_raw(&desc); 3061 if (buff_size == 0 || !buff) 3062 return -EINVAL; 3063 3064 i40e_fill_default_direct_cmd_desc(&desc, 3065 i40e_aqc_opc_lldp_set_local_mib); 3066 /* Indirect Command */ 3067 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 3068 if (buff_size > I40E_AQ_LARGE_BUF) 3069 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3070 desc.datalen = cpu_to_le16(buff_size); 3071 3072 cmd->type = mib_type; 3073 cmd->length = cpu_to_le16(buff_size); 3074 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff)); 3075 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff)); 3076 3077 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3078 return status; 3079} 3080 3081/** 3082 * i40e_aq_cfg_lldp_mib_change_event 3083 * @hw: pointer to the hw struct 3084 * @enable_update: Enable or Disable event posting 3085 * @cmd_details: pointer to command details structure or NULL 3086 * 3087 * Enable or Disable posting of an event on ARQ when LLDP MIB 3088 * associated with the interface changes 3089 **/ 3090int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3091 bool enable_update, 3092 struct i40e_asq_cmd_details *cmd_details) 3093{ 3094 struct i40e_aqc_lldp_update_mib *cmd; 3095 struct libie_aq_desc desc; 3096 int status; 3097 3098 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3099 3100 cmd = libie_aq_raw(&desc); 3101 if (!enable_update) 3102 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3103 3104 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3105 3106 return status; 3107} 3108 3109/** 3110 * i40e_aq_stop_lldp 3111 * @hw: pointer to the hw struct 3112 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3113 * @persist: True if stop of LLDP should be persistent across power cycles 3114 * @cmd_details: pointer to command details structure or NULL 3115 * 3116 * Stop or Shutdown the embedded LLDP Agent 3117 **/ 3118int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3119 bool persist, 3120 struct i40e_asq_cmd_details *cmd_details) 3121{ 3122 struct i40e_aqc_lldp_stop *cmd; 3123 struct libie_aq_desc desc; 3124 int status; 3125 3126 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3127 3128 cmd = libie_aq_raw(&desc); 3129 if (shutdown_agent) 3130 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3131 3132 if (persist) { 3133 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3134 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 3135 else 3136 i40e_debug(hw, I40E_DEBUG_ALL, 3137 "Persistent Stop LLDP not supported by current FW version.\n"); 3138 } 3139 3140 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3141 3142 return status; 3143} 3144 3145/** 3146 * i40e_aq_start_lldp 3147 * @hw: pointer to the hw struct 3148 * @persist: True if start of LLDP should be persistent across power cycles 3149 * @cmd_details: pointer to command details structure or NULL 3150 * 3151 * Start the embedded LLDP Agent on all ports. 3152 **/ 3153int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist, 3154 struct i40e_asq_cmd_details *cmd_details) 3155{ 3156 struct i40e_aqc_lldp_start *cmd; 3157 struct libie_aq_desc desc; 3158 int status; 3159 3160 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3161 3162 cmd = libie_aq_raw(&desc); 3163 cmd->command = I40E_AQ_LLDP_AGENT_START; 3164 3165 if (persist) { 3166 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) 3167 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 3168 else 3169 i40e_debug(hw, I40E_DEBUG_ALL, 3170 "Persistent Start LLDP not supported by current FW version.\n"); 3171 } 3172 3173 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3174 3175 return status; 3176} 3177 3178/** 3179 * i40e_aq_set_dcb_parameters 3180 * @hw: pointer to the hw struct 3181 * @cmd_details: pointer to command details structure or NULL 3182 * @dcb_enable: True if DCB configuration needs to be applied 3183 * 3184 **/ 3185int 3186i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3187 struct i40e_asq_cmd_details *cmd_details) 3188{ 3189 struct i40e_aqc_set_dcb_parameters *cmd; 3190 struct libie_aq_desc desc; 3191 int status; 3192 3193 if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps)) 3194 return -ENODEV; 3195 3196 i40e_fill_default_direct_cmd_desc(&desc, 3197 i40e_aqc_opc_set_dcb_parameters); 3198 3199 cmd = libie_aq_raw(&desc); 3200 if (dcb_enable) { 3201 cmd->valid_flags = I40E_DCB_VALID; 3202 cmd->command = I40E_AQ_DCB_SET_AGENT; 3203 } 3204 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3205 3206 return status; 3207} 3208 3209/** 3210 * i40e_aq_get_cee_dcb_config 3211 * @hw: pointer to the hw struct 3212 * @buff: response buffer that stores CEE operational configuration 3213 * @buff_size: size of the buffer passed 3214 * @cmd_details: pointer to command details structure or NULL 3215 * 3216 * Get CEE DCBX mode operational configuration from firmware 3217 **/ 3218int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3219 void *buff, u16 buff_size, 3220 struct i40e_asq_cmd_details *cmd_details) 3221{ 3222 struct libie_aq_desc desc; 3223 int status; 3224 3225 if (buff_size == 0 || !buff) 3226 return -EINVAL; 3227 3228 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3229 3230 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3231 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3232 cmd_details); 3233 3234 return status; 3235} 3236 3237/** 3238 * i40e_aq_add_udp_tunnel 3239 * @hw: pointer to the hw struct 3240 * @udp_port: the UDP port to add in Host byte order 3241 * @protocol_index: protocol index type 3242 * @filter_index: pointer to filter index 3243 * @cmd_details: pointer to command details structure or NULL 3244 * 3245 * Note: Firmware expects the udp_port value to be in Little Endian format, 3246 * and this function will call cpu_to_le16 to convert from Host byte order to 3247 * Little Endian order. 3248 **/ 3249int i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3250 u16 udp_port, u8 protocol_index, 3251 u8 *filter_index, 3252 struct i40e_asq_cmd_details *cmd_details) 3253{ 3254 struct i40e_aqc_del_udp_tunnel_completion *resp; 3255 struct i40e_aqc_add_udp_tunnel *cmd; 3256 struct libie_aq_desc desc; 3257 int status; 3258 3259 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3260 3261 resp = libie_aq_raw(&desc); 3262 cmd = libie_aq_raw(&desc); 3263 cmd->udp_port = cpu_to_le16(udp_port); 3264 cmd->protocol_type = protocol_index; 3265 3266 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3267 3268 if (!status && filter_index) 3269 *filter_index = resp->index; 3270 3271 return status; 3272} 3273 3274/** 3275 * i40e_aq_del_udp_tunnel 3276 * @hw: pointer to the hw struct 3277 * @index: filter index 3278 * @cmd_details: pointer to command details structure or NULL 3279 **/ 3280int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3281 struct i40e_asq_cmd_details *cmd_details) 3282{ 3283 struct i40e_aqc_remove_udp_tunnel *cmd; 3284 struct libie_aq_desc desc; 3285 int status; 3286 3287 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3288 3289 cmd = libie_aq_raw(&desc); 3290 cmd->index = index; 3291 3292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3293 3294 return status; 3295} 3296 3297/** 3298 * i40e_aq_delete_element - Delete switch element 3299 * @hw: pointer to the hw struct 3300 * @seid: the SEID to delete from the switch 3301 * @cmd_details: pointer to command details structure or NULL 3302 * 3303 * This deletes a switch element from the switch. 3304 **/ 3305int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3306 struct i40e_asq_cmd_details *cmd_details) 3307{ 3308 struct i40e_aqc_switch_seid *cmd; 3309 struct libie_aq_desc desc; 3310 int status; 3311 3312 if (seid == 0) 3313 return -EINVAL; 3314 3315 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3316 3317 cmd = libie_aq_raw(&desc); 3318 cmd->seid = cpu_to_le16(seid); 3319 3320 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 3321 cmd_details, true); 3322 3323 return status; 3324} 3325 3326/** 3327 * i40e_aq_dcb_updated - DCB Updated Command 3328 * @hw: pointer to the hw struct 3329 * @cmd_details: pointer to command details structure or NULL 3330 * 3331 * EMP will return when the shared RPB settings have been 3332 * recomputed and modified. The retval field in the descriptor 3333 * will be set to 0 when RPB is modified. 3334 **/ 3335int i40e_aq_dcb_updated(struct i40e_hw *hw, 3336 struct i40e_asq_cmd_details *cmd_details) 3337{ 3338 struct libie_aq_desc desc; 3339 int status; 3340 3341 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3342 3343 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3344 3345 return status; 3346} 3347 3348/** 3349 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3350 * @hw: pointer to the hw struct 3351 * @seid: seid for the physical port/switching component/vsi 3352 * @buff: Indirect buffer to hold data parameters and response 3353 * @buff_size: Indirect buffer size 3354 * @opcode: Tx scheduler AQ command opcode 3355 * @cmd_details: pointer to command details structure or NULL 3356 * 3357 * Generic command handler for Tx scheduler AQ commands 3358 **/ 3359static int i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3360 void *buff, u16 buff_size, 3361 enum i40e_admin_queue_opc opcode, 3362 struct i40e_asq_cmd_details *cmd_details) 3363{ 3364 struct i40e_aqc_tx_sched_ind *cmd; 3365 struct libie_aq_desc desc; 3366 int status; 3367 bool cmd_param_flag = false; 3368 3369 switch (opcode) { 3370 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3371 case i40e_aqc_opc_configure_vsi_tc_bw: 3372 case i40e_aqc_opc_enable_switching_comp_ets: 3373 case i40e_aqc_opc_modify_switching_comp_ets: 3374 case i40e_aqc_opc_disable_switching_comp_ets: 3375 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3376 case i40e_aqc_opc_configure_switching_comp_bw_config: 3377 cmd_param_flag = true; 3378 break; 3379 case i40e_aqc_opc_query_vsi_bw_config: 3380 case i40e_aqc_opc_query_vsi_ets_sla_config: 3381 case i40e_aqc_opc_query_switching_comp_ets_config: 3382 case i40e_aqc_opc_query_port_ets_config: 3383 case i40e_aqc_opc_query_switching_comp_bw_config: 3384 cmd_param_flag = false; 3385 break; 3386 default: 3387 return -EINVAL; 3388 } 3389 3390 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3391 3392 cmd = libie_aq_raw(&desc); 3393 /* Indirect command */ 3394 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3395 if (cmd_param_flag) 3396 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 3397 if (buff_size > I40E_AQ_LARGE_BUF) 3398 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3399 3400 desc.datalen = cpu_to_le16(buff_size); 3401 3402 cmd->vsi_seid = cpu_to_le16(seid); 3403 3404 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3405 3406 return status; 3407} 3408 3409/** 3410 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3411 * @hw: pointer to the hw struct 3412 * @seid: VSI seid 3413 * @credit: BW limit credits (0 = disabled) 3414 * @max_credit: Max BW limit credits 3415 * @cmd_details: pointer to command details structure or NULL 3416 **/ 3417int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3418 u16 seid, u16 credit, u8 max_credit, 3419 struct i40e_asq_cmd_details *cmd_details) 3420{ 3421 struct i40e_aqc_configure_vsi_bw_limit *cmd; 3422 struct libie_aq_desc desc; 3423 int status; 3424 3425 i40e_fill_default_direct_cmd_desc(&desc, 3426 i40e_aqc_opc_configure_vsi_bw_limit); 3427 3428 cmd = libie_aq_raw(&desc); 3429 cmd->vsi_seid = cpu_to_le16(seid); 3430 cmd->credit = cpu_to_le16(credit); 3431 cmd->max_credit = max_credit; 3432 3433 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3434 3435 return status; 3436} 3437 3438/** 3439 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3440 * @hw: pointer to the hw struct 3441 * @seid: VSI seid 3442 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3443 * @cmd_details: pointer to command details structure or NULL 3444 **/ 3445int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3446 u16 seid, 3447 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3448 struct i40e_asq_cmd_details *cmd_details) 3449{ 3450 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3451 i40e_aqc_opc_configure_vsi_tc_bw, 3452 cmd_details); 3453} 3454 3455/** 3456 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3457 * @hw: pointer to the hw struct 3458 * @seid: seid of the switching component connected to Physical Port 3459 * @ets_data: Buffer holding ETS parameters 3460 * @opcode: Tx scheduler AQ command opcode 3461 * @cmd_details: pointer to command details structure or NULL 3462 **/ 3463int 3464i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3465 u16 seid, 3466 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3467 enum i40e_admin_queue_opc opcode, 3468 struct i40e_asq_cmd_details *cmd_details) 3469{ 3470 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3471 sizeof(*ets_data), opcode, cmd_details); 3472} 3473 3474/** 3475 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3476 * @hw: pointer to the hw struct 3477 * @seid: seid of the switching component 3478 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3479 * @cmd_details: pointer to command details structure or NULL 3480 **/ 3481int 3482i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3483 u16 seid, 3484 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3485 struct i40e_asq_cmd_details *cmd_details) 3486{ 3487 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3488 i40e_aqc_opc_configure_switching_comp_bw_config, 3489 cmd_details); 3490} 3491 3492/** 3493 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3494 * @hw: pointer to the hw struct 3495 * @seid: seid of the VSI 3496 * @bw_data: Buffer to hold VSI BW configuration 3497 * @cmd_details: pointer to command details structure or NULL 3498 **/ 3499int 3500i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3501 u16 seid, 3502 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3503 struct i40e_asq_cmd_details *cmd_details) 3504{ 3505 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3506 i40e_aqc_opc_query_vsi_bw_config, 3507 cmd_details); 3508} 3509 3510/** 3511 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3512 * @hw: pointer to the hw struct 3513 * @seid: seid of the VSI 3514 * @bw_data: Buffer to hold VSI BW configuration per TC 3515 * @cmd_details: pointer to command details structure or NULL 3516 **/ 3517int 3518i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3519 u16 seid, 3520 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3521 struct i40e_asq_cmd_details *cmd_details) 3522{ 3523 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3524 i40e_aqc_opc_query_vsi_ets_sla_config, 3525 cmd_details); 3526} 3527 3528/** 3529 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3530 * @hw: pointer to the hw struct 3531 * @seid: seid of the switching component 3532 * @bw_data: Buffer to hold switching component's per TC BW config 3533 * @cmd_details: pointer to command details structure or NULL 3534 **/ 3535int 3536i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3537 u16 seid, 3538 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3539 struct i40e_asq_cmd_details *cmd_details) 3540{ 3541 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3542 i40e_aqc_opc_query_switching_comp_ets_config, 3543 cmd_details); 3544} 3545 3546/** 3547 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3548 * @hw: pointer to the hw struct 3549 * @seid: seid of the VSI or switching component connected to Physical Port 3550 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3551 * @cmd_details: pointer to command details structure or NULL 3552 **/ 3553int 3554i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3555 u16 seid, 3556 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3557 struct i40e_asq_cmd_details *cmd_details) 3558{ 3559 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3560 i40e_aqc_opc_query_port_ets_config, 3561 cmd_details); 3562} 3563 3564/** 3565 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3566 * @hw: pointer to the hw struct 3567 * @seid: seid of the switching component 3568 * @bw_data: Buffer to hold switching component's BW configuration 3569 * @cmd_details: pointer to command details structure or NULL 3570 **/ 3571int 3572i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3573 u16 seid, 3574 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3575 struct i40e_asq_cmd_details *cmd_details) 3576{ 3577 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3578 i40e_aqc_opc_query_switching_comp_bw_config, 3579 cmd_details); 3580} 3581 3582/** 3583 * i40e_validate_filter_settings 3584 * @hw: pointer to the hardware structure 3585 * @settings: Filter control settings 3586 * 3587 * Check and validate the filter control settings passed. 3588 * The function checks for the valid filter/context sizes being 3589 * passed for FCoE and PE. 3590 * 3591 * Returns 0 if the values passed are valid and within 3592 * range else returns an error. 3593 **/ 3594static int 3595i40e_validate_filter_settings(struct i40e_hw *hw, 3596 struct i40e_filter_control_settings *settings) 3597{ 3598 u32 fcoe_cntx_size, fcoe_filt_size; 3599 u32 fcoe_fmax; 3600 u32 val; 3601 3602 /* Validate FCoE settings passed */ 3603 switch (settings->fcoe_filt_num) { 3604 case I40E_HASH_FILTER_SIZE_1K: 3605 case I40E_HASH_FILTER_SIZE_2K: 3606 case I40E_HASH_FILTER_SIZE_4K: 3607 case I40E_HASH_FILTER_SIZE_8K: 3608 case I40E_HASH_FILTER_SIZE_16K: 3609 case I40E_HASH_FILTER_SIZE_32K: 3610 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3611 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3612 break; 3613 default: 3614 return -EINVAL; 3615 } 3616 3617 switch (settings->fcoe_cntx_num) { 3618 case I40E_DMA_CNTX_SIZE_512: 3619 case I40E_DMA_CNTX_SIZE_1K: 3620 case I40E_DMA_CNTX_SIZE_2K: 3621 case I40E_DMA_CNTX_SIZE_4K: 3622 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3623 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3624 break; 3625 default: 3626 return -EINVAL; 3627 } 3628 3629 /* Validate PE settings passed */ 3630 switch (settings->pe_filt_num) { 3631 case I40E_HASH_FILTER_SIZE_1K: 3632 case I40E_HASH_FILTER_SIZE_2K: 3633 case I40E_HASH_FILTER_SIZE_4K: 3634 case I40E_HASH_FILTER_SIZE_8K: 3635 case I40E_HASH_FILTER_SIZE_16K: 3636 case I40E_HASH_FILTER_SIZE_32K: 3637 case I40E_HASH_FILTER_SIZE_64K: 3638 case I40E_HASH_FILTER_SIZE_128K: 3639 case I40E_HASH_FILTER_SIZE_256K: 3640 case I40E_HASH_FILTER_SIZE_512K: 3641 case I40E_HASH_FILTER_SIZE_1M: 3642 break; 3643 default: 3644 return -EINVAL; 3645 } 3646 3647 switch (settings->pe_cntx_num) { 3648 case I40E_DMA_CNTX_SIZE_512: 3649 case I40E_DMA_CNTX_SIZE_1K: 3650 case I40E_DMA_CNTX_SIZE_2K: 3651 case I40E_DMA_CNTX_SIZE_4K: 3652 case I40E_DMA_CNTX_SIZE_8K: 3653 case I40E_DMA_CNTX_SIZE_16K: 3654 case I40E_DMA_CNTX_SIZE_32K: 3655 case I40E_DMA_CNTX_SIZE_64K: 3656 case I40E_DMA_CNTX_SIZE_128K: 3657 case I40E_DMA_CNTX_SIZE_256K: 3658 break; 3659 default: 3660 return -EINVAL; 3661 } 3662 3663 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3664 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3665 fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val); 3666 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3667 return -EINVAL; 3668 3669 return 0; 3670} 3671 3672/** 3673 * i40e_set_filter_control 3674 * @hw: pointer to the hardware structure 3675 * @settings: Filter control settings 3676 * 3677 * Set the Queue Filters for PE/FCoE and enable filters required 3678 * for a single PF. It is expected that these settings are programmed 3679 * at the driver initialization time. 3680 **/ 3681int i40e_set_filter_control(struct i40e_hw *hw, 3682 struct i40e_filter_control_settings *settings) 3683{ 3684 u32 hash_lut_size = 0; 3685 int ret = 0; 3686 u32 val; 3687 3688 if (!settings) 3689 return -EINVAL; 3690 3691 /* Validate the input settings */ 3692 ret = i40e_validate_filter_settings(hw, settings); 3693 if (ret) 3694 return ret; 3695 3696 /* Read the PF Queue Filter control register */ 3697 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 3698 3699 /* Program required PE hash buckets for the PF */ 3700 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3701 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings->pe_filt_num); 3702 /* Program required PE contexts for the PF */ 3703 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3704 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings->pe_cntx_num); 3705 3706 /* Program required FCoE hash buckets for the PF */ 3707 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3708 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK, 3709 settings->fcoe_filt_num); 3710 /* Program required FCoE DDP contexts for the PF */ 3711 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3712 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK, 3713 settings->fcoe_cntx_num); 3714 3715 /* Program Hash LUT size for the PF */ 3716 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3717 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3718 hash_lut_size = 1; 3719 val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size); 3720 3721 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3722 if (settings->enable_fdir) 3723 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3724 if (settings->enable_ethtype) 3725 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3726 if (settings->enable_macvlan) 3727 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3728 3729 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 3730 3731 return 0; 3732} 3733 3734/** 3735 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 3736 * @hw: pointer to the hw struct 3737 * @mac_addr: MAC address to use in the filter 3738 * @ethtype: Ethertype to use in the filter 3739 * @flags: Flags that needs to be applied to the filter 3740 * @vsi_seid: seid of the control VSI 3741 * @queue: VSI queue number to send the packet to 3742 * @is_add: Add control packet filter if True else remove 3743 * @stats: Structure to hold information on control filter counts 3744 * @cmd_details: pointer to command details structure or NULL 3745 * 3746 * This command will Add or Remove control packet filter for a control VSI. 3747 * In return it will update the total number of perfect filter count in 3748 * the stats member. 3749 **/ 3750int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 3751 u8 *mac_addr, u16 ethtype, u16 flags, 3752 u16 vsi_seid, u16 queue, bool is_add, 3753 struct i40e_control_filter_stats *stats, 3754 struct i40e_asq_cmd_details *cmd_details) 3755{ 3756 struct i40e_aqc_add_remove_control_packet_filter_completion *resp; 3757 struct i40e_aqc_add_remove_control_packet_filter *cmd; 3758 struct libie_aq_desc desc; 3759 int status; 3760 3761 if (vsi_seid == 0) 3762 return -EINVAL; 3763 3764 resp = libie_aq_raw(&desc); 3765 cmd = libie_aq_raw(&desc); 3766 if (is_add) { 3767 i40e_fill_default_direct_cmd_desc(&desc, 3768 i40e_aqc_opc_add_control_packet_filter); 3769 cmd->queue = cpu_to_le16(queue); 3770 } else { 3771 i40e_fill_default_direct_cmd_desc(&desc, 3772 i40e_aqc_opc_remove_control_packet_filter); 3773 } 3774 3775 if (mac_addr) 3776 ether_addr_copy(cmd->mac, mac_addr); 3777 3778 cmd->etype = cpu_to_le16(ethtype); 3779 cmd->flags = cpu_to_le16(flags); 3780 cmd->seid = cpu_to_le16(vsi_seid); 3781 3782 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3783 3784 if (!status && stats) { 3785 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 3786 stats->etype_used = le16_to_cpu(resp->etype_used); 3787 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 3788 stats->etype_free = le16_to_cpu(resp->etype_free); 3789 } 3790 3791 return status; 3792} 3793 3794/** 3795 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 3796 * @hw: pointer to the hw struct 3797 * @seid: VSI seid to add ethertype filter from 3798 **/ 3799void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 3800 u16 seid) 3801{ 3802#define I40E_FLOW_CONTROL_ETHTYPE 0x8808 3803 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 3804 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 3805 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 3806 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 3807 int status; 3808 3809 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 3810 seid, 0, true, NULL, 3811 NULL); 3812 if (status) 3813 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 3814} 3815 3816/** 3817 * i40e_aq_alternate_read 3818 * @hw: pointer to the hardware structure 3819 * @reg_addr0: address of first dword to be read 3820 * @reg_val0: pointer for data read from 'reg_addr0' 3821 * @reg_addr1: address of second dword to be read 3822 * @reg_val1: pointer for data read from 'reg_addr1' 3823 * 3824 * Read one or two dwords from alternate structure. Fields are indicated 3825 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 3826 * is not passed then only register at 'reg_addr0' is read. 3827 * 3828 **/ 3829static int i40e_aq_alternate_read(struct i40e_hw *hw, 3830 u32 reg_addr0, u32 *reg_val0, 3831 u32 reg_addr1, u32 *reg_val1) 3832{ 3833 struct i40e_aqc_alternate_write *cmd_resp; 3834 struct libie_aq_desc desc; 3835 int status; 3836 3837 if (!reg_val0) 3838 return -EINVAL; 3839 3840 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 3841 cmd_resp = libie_aq_raw(&desc); 3842 cmd_resp->address0 = cpu_to_le32(reg_addr0); 3843 cmd_resp->address1 = cpu_to_le32(reg_addr1); 3844 3845 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3846 3847 if (!status) { 3848 *reg_val0 = le32_to_cpu(cmd_resp->data0); 3849 3850 if (reg_val1) 3851 *reg_val1 = le32_to_cpu(cmd_resp->data1); 3852 } 3853 3854 return status; 3855} 3856 3857/** 3858 * i40e_aq_suspend_port_tx 3859 * @hw: pointer to the hardware structure 3860 * @seid: port seid 3861 * @cmd_details: pointer to command details structure or NULL 3862 * 3863 * Suspend port's Tx traffic 3864 **/ 3865int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, 3866 struct i40e_asq_cmd_details *cmd_details) 3867{ 3868 struct i40e_aqc_tx_sched_ind *cmd; 3869 struct libie_aq_desc desc; 3870 int status; 3871 3872 cmd = libie_aq_raw(&desc); 3873 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); 3874 cmd->vsi_seid = cpu_to_le16(seid); 3875 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3876 3877 return status; 3878} 3879 3880/** 3881 * i40e_aq_resume_port_tx 3882 * @hw: pointer to the hardware structure 3883 * @cmd_details: pointer to command details structure or NULL 3884 * 3885 * Resume port's Tx traffic 3886 **/ 3887int i40e_aq_resume_port_tx(struct i40e_hw *hw, 3888 struct i40e_asq_cmd_details *cmd_details) 3889{ 3890 struct libie_aq_desc desc; 3891 int status; 3892 3893 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 3894 3895 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3896 3897 return status; 3898} 3899 3900/** 3901 * i40e_set_pci_config_data - store PCI bus info 3902 * @hw: pointer to hardware structure 3903 * @link_status: the link status word from PCI config space 3904 * 3905 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 3906 **/ 3907void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 3908{ 3909 hw->bus.type = i40e_bus_type_pci_express; 3910 3911 switch (link_status & PCI_EXP_LNKSTA_NLW) { 3912 case PCI_EXP_LNKSTA_NLW_X1: 3913 hw->bus.width = i40e_bus_width_pcie_x1; 3914 break; 3915 case PCI_EXP_LNKSTA_NLW_X2: 3916 hw->bus.width = i40e_bus_width_pcie_x2; 3917 break; 3918 case PCI_EXP_LNKSTA_NLW_X4: 3919 hw->bus.width = i40e_bus_width_pcie_x4; 3920 break; 3921 case PCI_EXP_LNKSTA_NLW_X8: 3922 hw->bus.width = i40e_bus_width_pcie_x8; 3923 break; 3924 default: 3925 hw->bus.width = i40e_bus_width_unknown; 3926 break; 3927 } 3928 3929 switch (link_status & PCI_EXP_LNKSTA_CLS) { 3930 case PCI_EXP_LNKSTA_CLS_2_5GB: 3931 hw->bus.speed = i40e_bus_speed_2500; 3932 break; 3933 case PCI_EXP_LNKSTA_CLS_5_0GB: 3934 hw->bus.speed = i40e_bus_speed_5000; 3935 break; 3936 case PCI_EXP_LNKSTA_CLS_8_0GB: 3937 hw->bus.speed = i40e_bus_speed_8000; 3938 break; 3939 default: 3940 hw->bus.speed = i40e_bus_speed_unknown; 3941 break; 3942 } 3943} 3944 3945/** 3946 * i40e_aq_debug_dump 3947 * @hw: pointer to the hardware structure 3948 * @cluster_id: specific cluster to dump 3949 * @table_id: table id within cluster 3950 * @start_index: index of line in the block to read 3951 * @buff_size: dump buffer size 3952 * @buff: dump buffer 3953 * @ret_buff_size: actual buffer size returned 3954 * @ret_next_table: next block to read 3955 * @ret_next_index: next index to read 3956 * @cmd_details: pointer to command details structure or NULL 3957 * 3958 * Dump internal FW/HW data for debug purposes. 3959 * 3960 **/ 3961int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 3962 u8 table_id, u32 start_index, u16 buff_size, 3963 void *buff, u16 *ret_buff_size, 3964 u8 *ret_next_table, u32 *ret_next_index, 3965 struct i40e_asq_cmd_details *cmd_details) 3966{ 3967 struct i40e_aqc_debug_dump_internals *resp; 3968 struct i40e_aqc_debug_dump_internals *cmd; 3969 struct libie_aq_desc desc; 3970 int status; 3971 3972 if (buff_size == 0 || !buff) 3973 return -EINVAL; 3974 3975 i40e_fill_default_direct_cmd_desc(&desc, 3976 i40e_aqc_opc_debug_dump_internals); 3977 resp = libie_aq_raw(&desc); 3978 cmd = libie_aq_raw(&desc); 3979 /* Indirect Command */ 3980 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 3981 if (buff_size > I40E_AQ_LARGE_BUF) 3982 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 3983 3984 cmd->cluster_id = cluster_id; 3985 cmd->table_id = table_id; 3986 cmd->idx = cpu_to_le32(start_index); 3987 3988 desc.datalen = cpu_to_le16(buff_size); 3989 3990 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3991 if (!status) { 3992 if (ret_buff_size) 3993 *ret_buff_size = le16_to_cpu(desc.datalen); 3994 if (ret_next_table) 3995 *ret_next_table = resp->table_id; 3996 if (ret_next_index) 3997 *ret_next_index = le32_to_cpu(resp->idx); 3998 } 3999 4000 return status; 4001} 4002 4003/** 4004 * i40e_read_bw_from_alt_ram 4005 * @hw: pointer to the hardware structure 4006 * @max_bw: pointer for max_bw read 4007 * @min_bw: pointer for min_bw read 4008 * @min_valid: pointer for bool that is true if min_bw is a valid value 4009 * @max_valid: pointer for bool that is true if max_bw is a valid value 4010 * 4011 * Read bw from the alternate ram for the given pf 4012 **/ 4013int i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4014 u32 *max_bw, u32 *min_bw, 4015 bool *min_valid, bool *max_valid) 4016{ 4017 u32 max_bw_addr, min_bw_addr; 4018 int status; 4019 4020 /* Calculate the address of the min/max bw registers */ 4021 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4022 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4023 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4024 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4025 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4026 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4027 4028 /* Read the bandwidths from alt ram */ 4029 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4030 min_bw_addr, min_bw); 4031 4032 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4033 *min_valid = true; 4034 else 4035 *min_valid = false; 4036 4037 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4038 *max_valid = true; 4039 else 4040 *max_valid = false; 4041 4042 return status; 4043} 4044 4045/** 4046 * i40e_aq_configure_partition_bw 4047 * @hw: pointer to the hardware structure 4048 * @bw_data: Buffer holding valid pfs and bw limits 4049 * @cmd_details: pointer to command details 4050 * 4051 * Configure partitions guaranteed/max bw 4052 **/ 4053int 4054i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4055 struct i40e_aqc_configure_partition_bw_data *bw_data, 4056 struct i40e_asq_cmd_details *cmd_details) 4057{ 4058 u16 bwd_size = sizeof(*bw_data); 4059 struct libie_aq_desc desc; 4060 int status; 4061 4062 i40e_fill_default_direct_cmd_desc(&desc, 4063 i40e_aqc_opc_configure_partition_bw); 4064 4065 /* Indirect command */ 4066 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 4067 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 4068 4069 if (bwd_size > I40E_AQ_LARGE_BUF) 4070 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4071 4072 desc.datalen = cpu_to_le16(bwd_size); 4073 4074 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4075 cmd_details); 4076 4077 return status; 4078} 4079 4080/** 4081 * i40e_read_phy_register_clause22 4082 * @hw: pointer to the HW structure 4083 * @reg: register address in the page 4084 * @phy_addr: PHY address on MDIO interface 4085 * @value: PHY register value 4086 * 4087 * Reads specified PHY register value 4088 **/ 4089int i40e_read_phy_register_clause22(struct i40e_hw *hw, 4090 u16 reg, u8 phy_addr, u16 *value) 4091{ 4092 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4093 int status = -EIO; 4094 u32 command = 0; 4095 u16 retry = 1000; 4096 4097 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4098 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4099 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4100 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4101 (I40E_GLGEN_MSCA_MDICMD_MASK); 4102 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4103 do { 4104 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4105 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4106 status = 0; 4107 break; 4108 } 4109 udelay(10); 4110 retry--; 4111 } while (retry); 4112 4113 if (status) { 4114 i40e_debug(hw, I40E_DEBUG_PHY, 4115 "PHY: Can't write command to external PHY.\n"); 4116 } else { 4117 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4118 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4119 } 4120 4121 return status; 4122} 4123 4124/** 4125 * i40e_write_phy_register_clause22 4126 * @hw: pointer to the HW structure 4127 * @reg: register address in the page 4128 * @phy_addr: PHY address on MDIO interface 4129 * @value: PHY register value 4130 * 4131 * Writes specified PHY register value 4132 **/ 4133int i40e_write_phy_register_clause22(struct i40e_hw *hw, 4134 u16 reg, u8 phy_addr, u16 value) 4135{ 4136 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4137 int status = -EIO; 4138 u32 command = 0; 4139 u16 retry = 1000; 4140 4141 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4142 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4143 4144 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4145 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4146 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4147 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4148 (I40E_GLGEN_MSCA_MDICMD_MASK); 4149 4150 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4151 do { 4152 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4153 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4154 status = 0; 4155 break; 4156 } 4157 udelay(10); 4158 retry--; 4159 } while (retry); 4160 4161 return status; 4162} 4163 4164/** 4165 * i40e_read_phy_register_clause45 4166 * @hw: pointer to the HW structure 4167 * @page: registers page number 4168 * @reg: register address in the page 4169 * @phy_addr: PHY address on MDIO interface 4170 * @value: PHY register value 4171 * 4172 * Reads specified PHY register value 4173 **/ 4174int i40e_read_phy_register_clause45(struct i40e_hw *hw, 4175 u8 page, u16 reg, u8 phy_addr, u16 *value) 4176{ 4177 u8 port_num = hw->func_caps.mdio_port_num; 4178 int status = -EIO; 4179 u32 command = 0; 4180 u16 retry = 1000; 4181 4182 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4183 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4184 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4185 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4186 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4187 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4188 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4189 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4190 do { 4191 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4192 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4193 status = 0; 4194 break; 4195 } 4196 usleep_range(10, 20); 4197 retry--; 4198 } while (retry); 4199 4200 if (status) { 4201 i40e_debug(hw, I40E_DEBUG_PHY, 4202 "PHY: Can't write command to external PHY.\n"); 4203 goto phy_read_end; 4204 } 4205 4206 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4207 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4208 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4209 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4210 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4211 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4212 status = -EIO; 4213 retry = 1000; 4214 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4215 do { 4216 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4217 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4218 status = 0; 4219 break; 4220 } 4221 usleep_range(10, 20); 4222 retry--; 4223 } while (retry); 4224 4225 if (!status) { 4226 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4227 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4228 } else { 4229 i40e_debug(hw, I40E_DEBUG_PHY, 4230 "PHY: Can't read register value from external PHY.\n"); 4231 } 4232 4233phy_read_end: 4234 return status; 4235} 4236 4237/** 4238 * i40e_write_phy_register_clause45 4239 * @hw: pointer to the HW structure 4240 * @page: registers page number 4241 * @reg: register address in the page 4242 * @phy_addr: PHY address on MDIO interface 4243 * @value: PHY register value 4244 * 4245 * Writes value to specified PHY register 4246 **/ 4247int i40e_write_phy_register_clause45(struct i40e_hw *hw, 4248 u8 page, u16 reg, u8 phy_addr, u16 value) 4249{ 4250 u8 port_num = hw->func_caps.mdio_port_num; 4251 int status = -EIO; 4252 u16 retry = 1000; 4253 u32 command = 0; 4254 4255 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4256 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4257 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4258 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4259 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4260 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4261 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4262 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4263 do { 4264 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4265 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4266 status = 0; 4267 break; 4268 } 4269 usleep_range(10, 20); 4270 retry--; 4271 } while (retry); 4272 if (status) { 4273 i40e_debug(hw, I40E_DEBUG_PHY, 4274 "PHY: Can't write command to external PHY.\n"); 4275 goto phy_write_end; 4276 } 4277 4278 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4279 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4280 4281 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4282 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4283 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4284 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4285 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4286 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4287 status = -EIO; 4288 retry = 1000; 4289 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4290 do { 4291 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4292 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4293 status = 0; 4294 break; 4295 } 4296 usleep_range(10, 20); 4297 retry--; 4298 } while (retry); 4299 4300phy_write_end: 4301 return status; 4302} 4303 4304/** 4305 * i40e_get_phy_address 4306 * @hw: pointer to the HW structure 4307 * @dev_num: PHY port num that address we want 4308 * 4309 * Gets PHY address for current port 4310 **/ 4311u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4312{ 4313 u8 port_num = hw->func_caps.mdio_port_num; 4314 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4315 4316 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4317} 4318 4319/** 4320 * i40e_led_get_reg - read LED register 4321 * @hw: pointer to the HW structure 4322 * @led_addr: LED register address 4323 * @reg_val: read register value 4324 **/ 4325static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4326 u32 *reg_val) 4327{ 4328 u8 phy_addr = 0; 4329 u8 port_num; 4330 int status; 4331 u32 i; 4332 4333 *reg_val = 0; 4334 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4335 status = 4336 i40e_aq_get_phy_register(hw, 4337 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4338 I40E_PHY_COM_REG_PAGE, true, 4339 I40E_PHY_LED_PROV_REG_1, 4340 reg_val, NULL); 4341 } else { 4342 i = rd32(hw, I40E_PFGEN_PORTNUM); 4343 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4344 phy_addr = i40e_get_phy_address(hw, port_num); 4345 status = i40e_read_phy_register_clause45(hw, 4346 I40E_PHY_COM_REG_PAGE, 4347 led_addr, phy_addr, 4348 (u16 *)reg_val); 4349 } 4350 return status; 4351} 4352 4353/** 4354 * i40e_led_set_reg - write LED register 4355 * @hw: pointer to the HW structure 4356 * @led_addr: LED register address 4357 * @reg_val: register value to write 4358 **/ 4359static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 4360 u32 reg_val) 4361{ 4362 u8 phy_addr = 0; 4363 u8 port_num; 4364 int status; 4365 u32 i; 4366 4367 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4368 status = 4369 i40e_aq_set_phy_register(hw, 4370 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4371 I40E_PHY_COM_REG_PAGE, true, 4372 I40E_PHY_LED_PROV_REG_1, 4373 reg_val, NULL); 4374 } else { 4375 i = rd32(hw, I40E_PFGEN_PORTNUM); 4376 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4377 phy_addr = i40e_get_phy_address(hw, port_num); 4378 status = i40e_write_phy_register_clause45(hw, 4379 I40E_PHY_COM_REG_PAGE, 4380 led_addr, phy_addr, 4381 (u16)reg_val); 4382 } 4383 4384 return status; 4385} 4386 4387/** 4388 * i40e_led_get_phy - return current on/off mode 4389 * @hw: pointer to the hw struct 4390 * @led_addr: address of led register to use 4391 * @val: original value of register to use 4392 * 4393 **/ 4394int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4395 u16 *val) 4396{ 4397 u16 gpio_led_port; 4398 u8 phy_addr = 0; 4399 u32 reg_val_aq; 4400 int status = 0; 4401 u16 temp_addr; 4402 u16 reg_val; 4403 u8 port_num; 4404 u32 i; 4405 4406 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) { 4407 status = 4408 i40e_aq_get_phy_register(hw, 4409 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4410 I40E_PHY_COM_REG_PAGE, true, 4411 I40E_PHY_LED_PROV_REG_1, 4412 ®_val_aq, NULL); 4413 if (status == 0) 4414 *val = (u16)reg_val_aq; 4415 return status; 4416 } 4417 temp_addr = I40E_PHY_LED_PROV_REG_1; 4418 i = rd32(hw, I40E_PFGEN_PORTNUM); 4419 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4420 phy_addr = i40e_get_phy_address(hw, port_num); 4421 4422 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4423 temp_addr++) { 4424 status = i40e_read_phy_register_clause45(hw, 4425 I40E_PHY_COM_REG_PAGE, 4426 temp_addr, phy_addr, 4427 ®_val); 4428 if (status) 4429 return status; 4430 *val = reg_val; 4431 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4432 *led_addr = temp_addr; 4433 break; 4434 } 4435 } 4436 return status; 4437} 4438 4439/** 4440 * i40e_led_set_phy 4441 * @hw: pointer to the HW structure 4442 * @on: true or false 4443 * @led_addr: address of led register to use 4444 * @mode: original val plus bit for set or ignore 4445 * 4446 * Set led's on or off when controlled by the PHY 4447 * 4448 **/ 4449int i40e_led_set_phy(struct i40e_hw *hw, bool on, 4450 u16 led_addr, u32 mode) 4451{ 4452 u32 led_ctl = 0; 4453 u32 led_reg = 0; 4454 int status = 0; 4455 4456 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4457 if (status) 4458 return status; 4459 led_ctl = led_reg; 4460 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4461 led_reg = 0; 4462 status = i40e_led_set_reg(hw, led_addr, led_reg); 4463 if (status) 4464 return status; 4465 } 4466 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4467 if (status) 4468 goto restore_config; 4469 if (on) 4470 led_reg = I40E_PHY_LED_MANUAL_ON; 4471 else 4472 led_reg = 0; 4473 4474 status = i40e_led_set_reg(hw, led_addr, led_reg); 4475 if (status) 4476 goto restore_config; 4477 if (mode & I40E_PHY_LED_MODE_ORIG) { 4478 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 4479 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4480 } 4481 return status; 4482 4483restore_config: 4484 status = i40e_led_set_reg(hw, led_addr, led_ctl); 4485 return status; 4486} 4487 4488/** 4489 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 4490 * @hw: pointer to the hw struct 4491 * @reg_addr: register address 4492 * @reg_val: ptr to register value 4493 * @cmd_details: pointer to command details structure or NULL 4494 * 4495 * Use the firmware to read the Rx control register, 4496 * especially useful if the Rx unit is under heavy pressure 4497 **/ 4498int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 4499 u32 reg_addr, u32 *reg_val, 4500 struct i40e_asq_cmd_details *cmd_details) 4501{ 4502 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp; 4503 struct libie_aq_desc desc; 4504 int status; 4505 4506 if (!reg_val) 4507 return -EINVAL; 4508 4509 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 4510 4511 cmd_resp = libie_aq_raw(&desc); 4512 cmd_resp->address = cpu_to_le32(reg_addr); 4513 4514 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4515 4516 if (status == 0) 4517 *reg_val = le32_to_cpu(cmd_resp->value); 4518 4519 return status; 4520} 4521 4522/** 4523 * i40e_read_rx_ctl - read from an Rx control register 4524 * @hw: pointer to the hw struct 4525 * @reg_addr: register address 4526 **/ 4527u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 4528{ 4529 bool use_register = false; 4530 int status = 0; 4531 int retry = 5; 4532 u32 val = 0; 4533 4534 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 4535 use_register = true; 4536 4537 if (!use_register) { 4538do_retry: 4539 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 4540 if (hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN && retry) { 4541 usleep_range(1000, 2000); 4542 retry--; 4543 goto do_retry; 4544 } 4545 } 4546 4547 /* if the AQ access failed, try the old-fashioned way */ 4548 if (status || use_register) 4549 val = rd32(hw, reg_addr); 4550 4551 return val; 4552} 4553 4554/** 4555 * i40e_aq_rx_ctl_write_register 4556 * @hw: pointer to the hw struct 4557 * @reg_addr: register address 4558 * @reg_val: register value 4559 * @cmd_details: pointer to command details structure or NULL 4560 * 4561 * Use the firmware to write to an Rx control register, 4562 * especially useful if the Rx unit is under heavy pressure 4563 **/ 4564int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 4565 u32 reg_addr, u32 reg_val, 4566 struct i40e_asq_cmd_details *cmd_details) 4567{ 4568 struct i40e_aqc_rx_ctl_reg_read_write *cmd; 4569 struct libie_aq_desc desc; 4570 int status; 4571 4572 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 4573 4574 cmd = libie_aq_raw(&desc); 4575 cmd->address = cpu_to_le32(reg_addr); 4576 cmd->value = cpu_to_le32(reg_val); 4577 4578 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4579 4580 return status; 4581} 4582 4583/** 4584 * i40e_write_rx_ctl - write to an Rx control register 4585 * @hw: pointer to the hw struct 4586 * @reg_addr: register address 4587 * @reg_val: register value 4588 **/ 4589void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 4590{ 4591 bool use_register = false; 4592 int status = 0; 4593 int retry = 5; 4594 4595 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722) 4596 use_register = true; 4597 4598 if (!use_register) { 4599do_retry: 4600 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 4601 reg_val, NULL); 4602 if (hw->aq.asq_last_status == LIBIE_AQ_RC_EAGAIN && retry) { 4603 usleep_range(1000, 2000); 4604 retry--; 4605 goto do_retry; 4606 } 4607 } 4608 4609 /* if the AQ access failed, try the old-fashioned way */ 4610 if (status || use_register) 4611 wr32(hw, reg_addr, reg_val); 4612} 4613 4614/** 4615 * i40e_mdio_if_number_selection - MDIO I/F number selection 4616 * @hw: pointer to the hw struct 4617 * @set_mdio: use MDIO I/F number specified by mdio_num 4618 * @mdio_num: MDIO I/F number 4619 * @cmd: pointer to PHY Register command structure 4620 **/ 4621static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, 4622 u8 mdio_num, 4623 struct i40e_aqc_phy_register_access *cmd) 4624{ 4625 if (!set_mdio || 4626 cmd->phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL) 4627 return; 4628 4629 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) { 4630 cmd->cmd_flags |= 4631 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 4632 FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK, 4633 mdio_num); 4634 } else { 4635 i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n"); 4636 } 4637} 4638 4639/** 4640 * i40e_aq_set_phy_register_ext 4641 * @hw: pointer to the hw struct 4642 * @phy_select: select which phy should be accessed 4643 * @dev_addr: PHY device address 4644 * @page_change: flag to indicate if phy page should be updated 4645 * @set_mdio: use MDIO I/F number specified by mdio_num 4646 * @mdio_num: MDIO I/F number 4647 * @reg_addr: PHY register address 4648 * @reg_val: new register value 4649 * @cmd_details: pointer to command details structure or NULL 4650 * 4651 * Write the external PHY register. 4652 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 4653 * may use simple wrapper i40e_aq_set_phy_register. 4654 **/ 4655int i40e_aq_set_phy_register_ext(struct i40e_hw *hw, 4656 u8 phy_select, u8 dev_addr, bool page_change, 4657 bool set_mdio, u8 mdio_num, 4658 u32 reg_addr, u32 reg_val, 4659 struct i40e_asq_cmd_details *cmd_details) 4660{ 4661 struct i40e_aqc_phy_register_access *cmd; 4662 struct libie_aq_desc desc; 4663 int status; 4664 4665 i40e_fill_default_direct_cmd_desc(&desc, 4666 i40e_aqc_opc_set_phy_register); 4667 4668 cmd = libie_aq_raw(&desc); 4669 cmd->phy_interface = phy_select; 4670 cmd->dev_address = dev_addr; 4671 cmd->reg_address = cpu_to_le32(reg_addr); 4672 cmd->reg_value = cpu_to_le32(reg_val); 4673 4674 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 4675 4676 if (!page_change) 4677 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 4678 4679 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4680 4681 return status; 4682} 4683 4684/** 4685 * i40e_aq_get_phy_register_ext 4686 * @hw: pointer to the hw struct 4687 * @phy_select: select which phy should be accessed 4688 * @dev_addr: PHY device address 4689 * @page_change: flag to indicate if phy page should be updated 4690 * @set_mdio: use MDIO I/F number specified by mdio_num 4691 * @mdio_num: MDIO I/F number 4692 * @reg_addr: PHY register address 4693 * @reg_val: read register value 4694 * @cmd_details: pointer to command details structure or NULL 4695 * 4696 * Read the external PHY register. 4697 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 4698 * may use simple wrapper i40e_aq_get_phy_register. 4699 **/ 4700int i40e_aq_get_phy_register_ext(struct i40e_hw *hw, 4701 u8 phy_select, u8 dev_addr, bool page_change, 4702 bool set_mdio, u8 mdio_num, 4703 u32 reg_addr, u32 *reg_val, 4704 struct i40e_asq_cmd_details *cmd_details) 4705{ 4706 struct i40e_aqc_phy_register_access *cmd; 4707 struct libie_aq_desc desc; 4708 int status; 4709 4710 i40e_fill_default_direct_cmd_desc(&desc, 4711 i40e_aqc_opc_get_phy_register); 4712 4713 cmd = libie_aq_raw(&desc); 4714 cmd->phy_interface = phy_select; 4715 cmd->dev_address = dev_addr; 4716 cmd->reg_address = cpu_to_le32(reg_addr); 4717 4718 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 4719 4720 if (!page_change) 4721 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 4722 4723 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4724 if (!status) 4725 *reg_val = le32_to_cpu(cmd->reg_value); 4726 4727 return status; 4728} 4729 4730/** 4731 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 4732 * @hw: pointer to the hw struct 4733 * @buff: command buffer (size in bytes = buff_size) 4734 * @buff_size: buffer size in bytes 4735 * @track_id: package tracking id 4736 * @error_offset: returns error offset 4737 * @error_info: returns error information 4738 * @cmd_details: pointer to command details structure or NULL 4739 **/ 4740int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 4741 u16 buff_size, u32 track_id, 4742 u32 *error_offset, u32 *error_info, 4743 struct i40e_asq_cmd_details *cmd_details) 4744{ 4745 struct i40e_aqc_write_personalization_profile *cmd; 4746 struct i40e_aqc_write_ddp_resp *resp; 4747 struct libie_aq_desc desc; 4748 int status; 4749 4750 i40e_fill_default_direct_cmd_desc(&desc, 4751 i40e_aqc_opc_write_personalization_profile); 4752 4753 cmd = libie_aq_raw(&desc); 4754 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD); 4755 if (buff_size > I40E_AQ_LARGE_BUF) 4756 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4757 4758 desc.datalen = cpu_to_le16(buff_size); 4759 4760 cmd->profile_track_id = cpu_to_le32(track_id); 4761 4762 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4763 if (!status) { 4764 resp = libie_aq_raw(&desc); 4765 if (error_offset) 4766 *error_offset = le32_to_cpu(resp->error_offset); 4767 if (error_info) 4768 *error_info = le32_to_cpu(resp->error_info); 4769 } 4770 4771 return status; 4772} 4773 4774/** 4775 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 4776 * @hw: pointer to the hw struct 4777 * @buff: command buffer (size in bytes = buff_size) 4778 * @buff_size: buffer size in bytes 4779 * @flags: AdminQ command flags 4780 * @cmd_details: pointer to command details structure or NULL 4781 **/ 4782int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 4783 u16 buff_size, u8 flags, 4784 struct i40e_asq_cmd_details *cmd_details) 4785{ 4786 struct i40e_aqc_get_applied_profiles *cmd; 4787 struct libie_aq_desc desc; 4788 int status; 4789 4790 i40e_fill_default_direct_cmd_desc(&desc, 4791 i40e_aqc_opc_get_personalization_profile_list); 4792 4793 cmd = libie_aq_raw(&desc); 4794 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_BUF); 4795 if (buff_size > I40E_AQ_LARGE_BUF) 4796 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4797 desc.datalen = cpu_to_le16(buff_size); 4798 4799 cmd->flags = flags; 4800 4801 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4802 4803 return status; 4804} 4805 4806/** 4807 * i40e_find_segment_in_package 4808 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 4809 * @pkg_hdr: pointer to the package header to be searched 4810 * 4811 * This function searches a package file for a particular segment type. On 4812 * success it returns a pointer to the segment header, otherwise it will 4813 * return NULL. 4814 **/ 4815struct i40e_generic_seg_header * 4816i40e_find_segment_in_package(u32 segment_type, 4817 struct i40e_package_header *pkg_hdr) 4818{ 4819 struct i40e_generic_seg_header *segment; 4820 u32 i; 4821 4822 /* Search all package segments for the requested segment type */ 4823 for (i = 0; i < pkg_hdr->segment_count; i++) { 4824 segment = 4825 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 4826 pkg_hdr->segment_offset[i]); 4827 4828 if (segment->type == segment_type) 4829 return segment; 4830 } 4831 4832 return NULL; 4833} 4834 4835/* Get section table in profile */ 4836#define I40E_SECTION_TABLE(profile, sec_tbl) \ 4837 do { \ 4838 struct i40e_profile_segment *p = (profile); \ 4839 u32 count; \ 4840 u32 *nvm; \ 4841 count = p->device_table_count; \ 4842 nvm = (u32 *)&p->device_table[count]; \ 4843 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 4844 } while (0) 4845 4846/* Get section header in profile */ 4847#define I40E_SECTION_HEADER(profile, offset) \ 4848 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 4849 4850/** 4851 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 4852 * @hw: pointer to the hw struct 4853 * @aq: command buffer containing all data to execute AQ 4854 **/ 4855static int i40e_ddp_exec_aq_section(struct i40e_hw *hw, 4856 struct i40e_profile_aq_section *aq) 4857{ 4858 struct libie_aq_desc desc; 4859 u8 *msg = NULL; 4860 u16 msglen; 4861 int status; 4862 4863 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 4864 desc.flags |= cpu_to_le16(aq->flags); 4865 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw)); 4866 4867 msglen = aq->datalen; 4868 if (msglen) { 4869 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | 4870 LIBIE_AQ_FLAG_RD)); 4871 if (msglen > I40E_AQ_LARGE_BUF) 4872 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_LB); 4873 desc.datalen = cpu_to_le16(msglen); 4874 msg = &aq->data[0]; 4875 } 4876 4877 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 4878 4879 if (status) { 4880 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4881 "unable to exec DDP AQ opcode %u, error %d\n", 4882 aq->opcode, status); 4883 return status; 4884 } 4885 4886 /* copy returned desc to aq_buf */ 4887 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw)); 4888 4889 return 0; 4890} 4891 4892/** 4893 * i40e_validate_profile 4894 * @hw: pointer to the hardware structure 4895 * @profile: pointer to the profile segment of the package to be validated 4896 * @track_id: package tracking id 4897 * @rollback: flag if the profile is for rollback. 4898 * 4899 * Validates supported devices and profile's sections. 4900 */ 4901static int 4902i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 4903 u32 track_id, bool rollback) 4904{ 4905 struct i40e_profile_section_header *sec = NULL; 4906 struct i40e_section_table *sec_tbl; 4907 u32 vendor_dev_id; 4908 int status = 0; 4909 u32 dev_cnt; 4910 u32 sec_off; 4911 u32 i; 4912 4913 if (track_id == I40E_DDP_TRACKID_INVALID) { 4914 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 4915 return -EOPNOTSUPP; 4916 } 4917 4918 dev_cnt = profile->device_table_count; 4919 for (i = 0; i < dev_cnt; i++) { 4920 vendor_dev_id = profile->device_table[i].vendor_dev_id; 4921 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL && 4922 hw->device_id == (vendor_dev_id & 0xFFFF)) 4923 break; 4924 } 4925 if (dev_cnt && i == dev_cnt) { 4926 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4927 "Device doesn't support DDP\n"); 4928 return -ENODEV; 4929 } 4930 4931 I40E_SECTION_TABLE(profile, sec_tbl); 4932 4933 /* Validate sections types */ 4934 for (i = 0; i < sec_tbl->section_count; i++) { 4935 sec_off = sec_tbl->section_offset[i]; 4936 sec = I40E_SECTION_HEADER(profile, sec_off); 4937 if (rollback) { 4938 if (sec->section.type == SECTION_TYPE_MMIO || 4939 sec->section.type == SECTION_TYPE_AQ || 4940 sec->section.type == SECTION_TYPE_RB_AQ) { 4941 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4942 "Not a roll-back package\n"); 4943 return -EOPNOTSUPP; 4944 } 4945 } else { 4946 if (sec->section.type == SECTION_TYPE_RB_AQ || 4947 sec->section.type == SECTION_TYPE_RB_MMIO) { 4948 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4949 "Not an original package\n"); 4950 return -EOPNOTSUPP; 4951 } 4952 } 4953 } 4954 4955 return status; 4956} 4957 4958/** 4959 * i40e_write_profile 4960 * @hw: pointer to the hardware structure 4961 * @profile: pointer to the profile segment of the package to be downloaded 4962 * @track_id: package tracking id 4963 * 4964 * Handles the download of a complete package. 4965 */ 4966int 4967i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 4968 u32 track_id) 4969{ 4970 struct i40e_profile_section_header *sec = NULL; 4971 struct i40e_profile_aq_section *ddp_aq; 4972 struct i40e_section_table *sec_tbl; 4973 u32 offset = 0, info = 0; 4974 u32 section_size = 0; 4975 int status = 0; 4976 u32 sec_off; 4977 u32 i; 4978 4979 status = i40e_validate_profile(hw, profile, track_id, false); 4980 if (status) 4981 return status; 4982 4983 I40E_SECTION_TABLE(profile, sec_tbl); 4984 4985 for (i = 0; i < sec_tbl->section_count; i++) { 4986 sec_off = sec_tbl->section_offset[i]; 4987 sec = I40E_SECTION_HEADER(profile, sec_off); 4988 /* Process generic admin command */ 4989 if (sec->section.type == SECTION_TYPE_AQ) { 4990 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 4991 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 4992 if (status) { 4993 i40e_debug(hw, I40E_DEBUG_PACKAGE, 4994 "Failed to execute aq: section %d, opcode %u\n", 4995 i, ddp_aq->opcode); 4996 break; 4997 } 4998 sec->section.type = SECTION_TYPE_RB_AQ; 4999 } 5000 5001 /* Skip any non-mmio sections */ 5002 if (sec->section.type != SECTION_TYPE_MMIO) 5003 continue; 5004 5005 section_size = sec->section.size + 5006 sizeof(struct i40e_profile_section_header); 5007 5008 /* Write MMIO section */ 5009 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5010 track_id, &offset, &info, NULL); 5011 if (status) { 5012 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5013 "Failed to write profile: section %d, offset %d, info %d\n", 5014 i, offset, info); 5015 break; 5016 } 5017 } 5018 return status; 5019} 5020 5021/** 5022 * i40e_rollback_profile 5023 * @hw: pointer to the hardware structure 5024 * @profile: pointer to the profile segment of the package to be removed 5025 * @track_id: package tracking id 5026 * 5027 * Rolls back previously loaded package. 5028 */ 5029int 5030i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5031 u32 track_id) 5032{ 5033 struct i40e_profile_section_header *sec = NULL; 5034 struct i40e_section_table *sec_tbl; 5035 u32 offset = 0, info = 0; 5036 u32 section_size = 0; 5037 int status = 0; 5038 u32 sec_off; 5039 int i; 5040 5041 status = i40e_validate_profile(hw, profile, track_id, true); 5042 if (status) 5043 return status; 5044 5045 I40E_SECTION_TABLE(profile, sec_tbl); 5046 5047 /* For rollback write sections in reverse */ 5048 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 5049 sec_off = sec_tbl->section_offset[i]; 5050 sec = I40E_SECTION_HEADER(profile, sec_off); 5051 5052 /* Skip any non-rollback sections */ 5053 if (sec->section.type != SECTION_TYPE_RB_MMIO) 5054 continue; 5055 5056 section_size = sec->section.size + 5057 sizeof(struct i40e_profile_section_header); 5058 5059 /* Write roll-back MMIO section */ 5060 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5061 track_id, &offset, &info, NULL); 5062 if (status) { 5063 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5064 "Failed to write profile: section %d, offset %d, info %d\n", 5065 i, offset, info); 5066 break; 5067 } 5068 } 5069 return status; 5070} 5071 5072/** 5073 * i40e_aq_add_cloud_filters 5074 * @hw: pointer to the hardware structure 5075 * @seid: VSI seid to add cloud filters from 5076 * @filters: Buffer which contains the filters to be added 5077 * @filter_count: number of filters contained in the buffer 5078 * 5079 * Set the cloud filters for a given VSI. The contents of the 5080 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5081 * of the function. 5082 * 5083 **/ 5084int 5085i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5086 struct i40e_aqc_cloud_filters_element_data *filters, 5087 u8 filter_count) 5088{ 5089 struct i40e_aqc_add_remove_cloud_filters *cmd; 5090 struct libie_aq_desc desc; 5091 u16 buff_len; 5092 int status; 5093 5094 i40e_fill_default_direct_cmd_desc(&desc, 5095 i40e_aqc_opc_add_cloud_filters); 5096 5097 cmd = libie_aq_raw(&desc); 5098 buff_len = filter_count * sizeof(*filters); 5099 desc.datalen = cpu_to_le16(buff_len); 5100 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5101 cmd->num_filters = filter_count; 5102 cmd->seid = cpu_to_le16(seid); 5103 5104 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5105 5106 return status; 5107} 5108 5109/** 5110 * i40e_aq_add_cloud_filters_bb 5111 * @hw: pointer to the hardware structure 5112 * @seid: VSI seid to add cloud filters from 5113 * @filters: Buffer which contains the filters in big buffer to be added 5114 * @filter_count: number of filters contained in the buffer 5115 * 5116 * Set the big buffer cloud filters for a given VSI. The contents of the 5117 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5118 * function. 5119 * 5120 **/ 5121int 5122i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5123 struct i40e_aqc_cloud_filters_element_bb *filters, 5124 u8 filter_count) 5125{ 5126 struct i40e_aqc_add_remove_cloud_filters *cmd; 5127 struct libie_aq_desc desc; 5128 u16 buff_len; 5129 int status; 5130 int i; 5131 5132 i40e_fill_default_direct_cmd_desc(&desc, 5133 i40e_aqc_opc_add_cloud_filters); 5134 5135 cmd = libie_aq_raw(&desc); 5136 buff_len = filter_count * sizeof(*filters); 5137 desc.datalen = cpu_to_le16(buff_len); 5138 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5139 cmd->num_filters = filter_count; 5140 cmd->seid = cpu_to_le16(seid); 5141 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5142 5143 for (i = 0; i < filter_count; i++) { 5144 u16 tnl_type; 5145 u32 ti; 5146 5147 tnl_type = le16_get_bits(filters[i].element.flags, 5148 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5149 5150 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5151 * one more byte further than normally used for Tenant ID in 5152 * other tunnel types. 5153 */ 5154 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5155 ti = le32_to_cpu(filters[i].element.tenant_id); 5156 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5157 } 5158 } 5159 5160 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5161 5162 return status; 5163} 5164 5165/** 5166 * i40e_aq_rem_cloud_filters 5167 * @hw: pointer to the hardware structure 5168 * @seid: VSI seid to remove cloud filters from 5169 * @filters: Buffer which contains the filters to be removed 5170 * @filter_count: number of filters contained in the buffer 5171 * 5172 * Remove the cloud filters for a given VSI. The contents of the 5173 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5174 * of the function. 5175 * 5176 **/ 5177int 5178i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5179 struct i40e_aqc_cloud_filters_element_data *filters, 5180 u8 filter_count) 5181{ 5182 struct i40e_aqc_add_remove_cloud_filters *cmd; 5183 struct libie_aq_desc desc; 5184 u16 buff_len; 5185 int status; 5186 5187 i40e_fill_default_direct_cmd_desc(&desc, 5188 i40e_aqc_opc_remove_cloud_filters); 5189 5190 cmd = libie_aq_raw(&desc); 5191 buff_len = filter_count * sizeof(*filters); 5192 desc.datalen = cpu_to_le16(buff_len); 5193 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5194 cmd->num_filters = filter_count; 5195 cmd->seid = cpu_to_le16(seid); 5196 5197 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5198 5199 return status; 5200} 5201 5202/** 5203 * i40e_aq_rem_cloud_filters_bb 5204 * @hw: pointer to the hardware structure 5205 * @seid: VSI seid to remove cloud filters from 5206 * @filters: Buffer which contains the filters in big buffer to be removed 5207 * @filter_count: number of filters contained in the buffer 5208 * 5209 * Remove the big buffer cloud filters for a given VSI. The contents of the 5210 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5211 * function. 5212 * 5213 **/ 5214int 5215i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5216 struct i40e_aqc_cloud_filters_element_bb *filters, 5217 u8 filter_count) 5218{ 5219 struct i40e_aqc_add_remove_cloud_filters *cmd; 5220 struct libie_aq_desc desc; 5221 u16 buff_len; 5222 int status; 5223 int i; 5224 5225 i40e_fill_default_direct_cmd_desc(&desc, 5226 i40e_aqc_opc_remove_cloud_filters); 5227 5228 cmd = libie_aq_raw(&desc); 5229 buff_len = filter_count * sizeof(*filters); 5230 desc.datalen = cpu_to_le16(buff_len); 5231 desc.flags |= cpu_to_le16((u16)(LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_RD)); 5232 cmd->num_filters = filter_count; 5233 cmd->seid = cpu_to_le16(seid); 5234 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5235 5236 for (i = 0; i < filter_count; i++) { 5237 u16 tnl_type; 5238 u32 ti; 5239 5240 tnl_type = le16_get_bits(filters[i].element.flags, 5241 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5242 5243 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5244 * one more byte further than normally used for Tenant ID in 5245 * other tunnel types. 5246 */ 5247 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5248 ti = le32_to_cpu(filters[i].element.tenant_id); 5249 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5250 } 5251 } 5252 5253 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5254 5255 return status; 5256}
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