mac.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4#include <linux/bitfield.h>
   5
   6#include "e1000.h"
   7
   8/**
   9 *  e1000e_get_bus_info_pcie - Get PCIe bus information
  10 *  @hw: pointer to the HW structure
  11 *
  12 *  Determines and stores the system bus information for a particular
  13 *  network interface.  The following bus information is determined and stored:
  14 *  bus speed, bus width, type (PCIe), and PCIe function.
  15 **/
  16s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
  17{
  18	struct pci_dev *pdev = hw->adapter->pdev;
  19	struct e1000_mac_info *mac = &hw->mac;
  20	struct e1000_bus_info *bus = &hw->bus;
  21	u16 pcie_link_status;
  22
  23	if (!pci_pcie_cap(pdev)) {
  24		bus->width = e1000_bus_width_unknown;
  25	} else {
  26		pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &pcie_link_status);
  27		bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW,
  28							     pcie_link_status);
  29	}
  30
  31	mac->ops.set_lan_id(hw);
  32
  33	return 0;
  34}
  35
  36/**
  37 *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
  38 *
  39 *  @hw: pointer to the HW structure
  40 *
  41 *  Determines the LAN function id by reading memory-mapped registers
  42 *  and swaps the port value if requested.
  43 **/
  44void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
  45{
  46	struct e1000_bus_info *bus = &hw->bus;
  47	u32 reg;
  48
  49	/* The status register reports the correct function number
  50	 * for the device regardless of function swap state.
  51	 */
  52	reg = er32(STATUS);
  53	bus->func = FIELD_GET(E1000_STATUS_FUNC_MASK, reg);
  54}
  55
  56/**
  57 *  e1000_set_lan_id_single_port - Set LAN id for a single port device
  58 *  @hw: pointer to the HW structure
  59 *
  60 *  Sets the LAN function id to zero for a single port device.
  61 **/
  62void e1000_set_lan_id_single_port(struct e1000_hw *hw)
  63{
  64	struct e1000_bus_info *bus = &hw->bus;
  65
  66	bus->func = 0;
  67}
  68
  69/**
  70 *  e1000_clear_vfta_generic - Clear VLAN filter table
  71 *  @hw: pointer to the HW structure
  72 *
  73 *  Clears the register array which contains the VLAN filter table by
  74 *  setting all the values to 0.
  75 **/
  76void e1000_clear_vfta_generic(struct e1000_hw *hw)
  77{
  78	u32 offset;
  79
  80	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
  81		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
  82		e1e_flush();
  83	}
  84}
  85
  86/**
  87 *  e1000_write_vfta_generic - Write value to VLAN filter table
  88 *  @hw: pointer to the HW structure
  89 *  @offset: register offset in VLAN filter table
  90 *  @value: register value written to VLAN filter table
  91 *
  92 *  Writes value at the given offset in the register array which stores
  93 *  the VLAN filter table.
  94 **/
  95void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
  96{
  97	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
  98	e1e_flush();
  99}
 100
 101/**
 102 *  e1000e_init_rx_addrs - Initialize receive address's
 103 *  @hw: pointer to the HW structure
 104 *  @rar_count: receive address registers
 105 *
 106 *  Setup the receive address registers by setting the base receive address
 107 *  register to the devices MAC address and clearing all the other receive
 108 *  address registers to 0.
 109 **/
 110void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
 111{
 112	u32 i;
 113	u8 mac_addr[ETH_ALEN] = { 0 };
 114
 115	/* Setup the receive address */
 116	e_dbg("Programming MAC Address into RAR[0]\n");
 117
 118	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
 119
 120	/* Zero out the other (rar_entry_count - 1) receive addresses */
 121	e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
 122	for (i = 1; i < rar_count; i++)
 123		hw->mac.ops.rar_set(hw, mac_addr, i);
 124}
 125
 126/**
 127 *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
 128 *  @hw: pointer to the HW structure
 129 *
 130 *  Checks the nvm for an alternate MAC address.  An alternate MAC address
 131 *  can be setup by pre-boot software and must be treated like a permanent
 132 *  address and must override the actual permanent MAC address. If an
 133 *  alternate MAC address is found it is programmed into RAR0, replacing
 134 *  the permanent address that was installed into RAR0 by the Si on reset.
 135 *  This function will return SUCCESS unless it encounters an error while
 136 *  reading the EEPROM.
 137 **/
 138s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
 139{
 140	u32 i;
 141	s32 ret_val;
 142	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
 143	u8 alt_mac_addr[ETH_ALEN];
 144
 145	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
 146	if (ret_val)
 147		return ret_val;
 148
 149	/* not supported on 82573 */
 150	if (hw->mac.type == e1000_82573)
 151		return 0;
 152
 153	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
 154				 &nvm_alt_mac_addr_offset);
 155	if (ret_val) {
 156		e_dbg("NVM Read Error\n");
 157		return ret_val;
 158	}
 159
 160	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
 161	    (nvm_alt_mac_addr_offset == 0x0000))
 162		/* There is no Alternate MAC Address */
 163		return 0;
 164
 165	if (hw->bus.func == E1000_FUNC_1)
 166		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
 167	for (i = 0; i < ETH_ALEN; i += 2) {
 168		offset = nvm_alt_mac_addr_offset + (i >> 1);
 169		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
 170		if (ret_val) {
 171			e_dbg("NVM Read Error\n");
 172			return ret_val;
 173		}
 174
 175		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
 176		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
 177	}
 178
 179	/* if multicast bit is set, the alternate address will not be used */
 180	if (is_multicast_ether_addr(alt_mac_addr)) {
 181		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
 182		return 0;
 183	}
 184
 185	/* We have a valid alternate MAC address, and we want to treat it the
 186	 * same as the normal permanent MAC address stored by the HW into the
 187	 * RAR. Do this by mapping this address into RAR0.
 188	 */
 189	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
 190
 191	return 0;
 192}
 193
 194u32 e1000e_rar_get_count_generic(struct e1000_hw *hw)
 195{
 196	return hw->mac.rar_entry_count;
 197}
 198
 199/**
 200 *  e1000e_rar_set_generic - Set receive address register
 201 *  @hw: pointer to the HW structure
 202 *  @addr: pointer to the receive address
 203 *  @index: receive address array register
 204 *
 205 *  Sets the receive address array register at index to the address passed
 206 *  in by addr.
 207 **/
 208int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
 209{
 210	u32 rar_low, rar_high;
 211
 212	/* HW expects these in little endian so we reverse the byte order
 213	 * from network order (big endian) to little endian
 214	 */
 215	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
 216		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
 217
 218	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
 219
 220	/* If MAC address zero, no need to set the AV bit */
 221	if (rar_low || rar_high)
 222		rar_high |= E1000_RAH_AV;
 223
 224	/* Some bridges will combine consecutive 32-bit writes into
 225	 * a single burst write, which will malfunction on some parts.
 226	 * The flushes avoid this.
 227	 */
 228	ew32(RAL(index), rar_low);
 229	e1e_flush();
 230	ew32(RAH(index), rar_high);
 231	e1e_flush();
 232
 233	return 0;
 234}
 235
 236/**
 237 *  e1000_hash_mc_addr - Generate a multicast hash value
 238 *  @hw: pointer to the HW structure
 239 *  @mc_addr: pointer to a multicast address
 240 *
 241 *  Generates a multicast address hash value which is used to determine
 242 *  the multicast filter table array address and new table value.
 243 **/
 244static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
 245{
 246	u32 hash_value, hash_mask;
 247	u8 bit_shift = 0;
 248
 249	/* Register count multiplied by bits per register */
 250	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
 251
 252	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts
 253	 * where 0xFF would still fall within the hash mask.
 254	 */
 255	while (hash_mask >> bit_shift != 0xFF)
 256		bit_shift++;
 257
 258	/* The portion of the address that is used for the hash table
 259	 * is determined by the mc_filter_type setting.
 260	 * The algorithm is such that there is a total of 8 bits of shifting.
 261	 * The bit_shift for a mc_filter_type of 0 represents the number of
 262	 * left-shifts where the MSB of mc_addr[5] would still fall within
 263	 * the hash_mask.  Case 0 does this exactly.  Since there are a total
 264	 * of 8 bits of shifting, then mc_addr[4] will shift right the
 265	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the
 266	 * cases are a variation of this algorithm...essentially raising the
 267	 * number of bits to shift mc_addr[5] left, while still keeping the
 268	 * 8-bit shifting total.
 269	 *
 270	 * For example, given the following Destination MAC Address and an
 271	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
 272	 * we can see that the bit_shift for case 0 is 4.  These are the hash
 273	 * values resulting from each mc_filter_type...
 274	 * [0] [1] [2] [3] [4] [5]
 275	 * 01  AA  00  12  34  56
 276	 * LSB           MSB
 277	 *
 278	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
 279	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
 280	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
 281	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
 282	 */
 283	switch (hw->mac.mc_filter_type) {
 284	default:
 285	case 0:
 286		break;
 287	case 1:
 288		bit_shift += 1;
 289		break;
 290	case 2:
 291		bit_shift += 2;
 292		break;
 293	case 3:
 294		bit_shift += 4;
 295		break;
 296	}
 297
 298	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
 299				   (((u16)mc_addr[5]) << bit_shift)));
 300
 301	return hash_value;
 302}
 303
 304/**
 305 *  e1000e_update_mc_addr_list_generic - Update Multicast addresses
 306 *  @hw: pointer to the HW structure
 307 *  @mc_addr_list: array of multicast addresses to program
 308 *  @mc_addr_count: number of multicast addresses to program
 309 *
 310 *  Updates entire Multicast Table Array.
 311 *  The caller must have a packed mc_addr_list of multicast addresses.
 312 **/
 313void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
 314					u8 *mc_addr_list, u32 mc_addr_count)
 315{
 316	u32 hash_value, hash_bit, hash_reg;
 317	int i;
 318
 319	/* clear mta_shadow */
 320	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
 321
 322	/* update mta_shadow from mc_addr_list */
 323	for (i = 0; (u32)i < mc_addr_count; i++) {
 324		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
 325
 326		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
 327		hash_bit = hash_value & 0x1F;
 328
 329		hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
 330		mc_addr_list += (ETH_ALEN);
 331	}
 332
 333	/* replace the entire MTA table */
 334	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) {
 335		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
 336
 337		if (IS_ENABLED(CONFIG_PREEMPT_RT)) {
 338			/*
 339			 * Do not queue up too many posted writes to prevent
 340			 * increased latency for other devices on the
 341			 * interconnect. Flush after each 8th posted write,
 342			 * to keep additional execution time low while still
 343			 * preventing increased latency.
 344			 */
 345			if (!(i % 8) && i)
 346				e1e_flush();
 347		}
 348	}
 349	e1e_flush();
 350}
 351
 352/**
 353 *  e1000e_clear_hw_cntrs_base - Clear base hardware counters
 354 *  @hw: pointer to the HW structure
 355 *
 356 *  Clears the base hardware counters by reading the counter registers.
 357 **/
 358void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
 359{
 360	er32(CRCERRS);
 361	er32(SYMERRS);
 362	er32(MPC);
 363	er32(SCC);
 364	er32(ECOL);
 365	er32(MCC);
 366	er32(LATECOL);
 367	er32(COLC);
 368	er32(DC);
 369	er32(SEC);
 370	er32(RLEC);
 371	er32(XONRXC);
 372	er32(XONTXC);
 373	er32(XOFFRXC);
 374	er32(XOFFTXC);
 375	er32(FCRUC);
 376	er32(GPRC);
 377	er32(BPRC);
 378	er32(MPRC);
 379	er32(GPTC);
 380	er32(GORCL);
 381	er32(GORCH);
 382	er32(GOTCL);
 383	er32(GOTCH);
 384	er32(RNBC);
 385	er32(RUC);
 386	er32(RFC);
 387	er32(ROC);
 388	er32(RJC);
 389	er32(TORL);
 390	er32(TORH);
 391	er32(TOTL);
 392	er32(TOTH);
 393	er32(TPR);
 394	er32(TPT);
 395	er32(MPTC);
 396	er32(BPTC);
 397}
 398
 399/**
 400 *  e1000e_check_for_copper_link - Check for link (Copper)
 401 *  @hw: pointer to the HW structure
 402 *
 403 *  Checks to see of the link status of the hardware has changed.  If a
 404 *  change in link status has been detected, then we read the PHY registers
 405 *  to get the current speed/duplex if link exists.
 406 **/
 407s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
 408{
 409	struct e1000_mac_info *mac = &hw->mac;
 410	s32 ret_val;
 411	bool link;
 412
 413	/* We only want to go out to the PHY registers to see if Auto-Neg
 414	 * has completed and/or if our link status has changed.  The
 415	 * get_link_status flag is set upon receiving a Link Status
 416	 * Change or Rx Sequence Error interrupt.
 417	 */
 418	if (!mac->get_link_status)
 419		return 0;
 420	mac->get_link_status = false;
 421
 422	/* First we want to see if the MII Status Register reports
 423	 * link.  If so, then we want to get the current speed/duplex
 424	 * of the PHY.
 425	 */
 426	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 427	if (ret_val || !link)
 428		goto out;
 429
 430	/* Check if there was DownShift, must be checked
 431	 * immediately after link-up
 432	 */
 433	e1000e_check_downshift(hw);
 434
 435	/* If we are forcing speed/duplex, then we simply return since
 436	 * we have already determined whether we have link or not.
 437	 */
 438	if (!mac->autoneg)
 439		return -E1000_ERR_CONFIG;
 440
 441	/* Auto-Neg is enabled.  Auto Speed Detection takes care
 442	 * of MAC speed/duplex configuration.  So we only need to
 443	 * configure Collision Distance in the MAC.
 444	 */
 445	mac->ops.config_collision_dist(hw);
 446
 447	/* Configure Flow Control now that Auto-Neg has completed.
 448	 * First, we need to restore the desired flow control
 449	 * settings because we may have had to re-autoneg with a
 450	 * different link partner.
 451	 */
 452	ret_val = e1000e_config_fc_after_link_up(hw);
 453	if (ret_val)
 454		e_dbg("Error configuring flow control\n");
 455
 456	return ret_val;
 457
 458out:
 459	mac->get_link_status = true;
 460	return ret_val;
 461}
 462
 463/**
 464 *  e1000e_check_for_fiber_link - Check for link (Fiber)
 465 *  @hw: pointer to the HW structure
 466 *
 467 *  Checks for link up on the hardware.  If link is not up and we have
 468 *  a signal, then we need to force link up.
 469 **/
 470s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
 471{
 472	struct e1000_mac_info *mac = &hw->mac;
 473	u32 rxcw;
 474	u32 ctrl;
 475	u32 status;
 476	s32 ret_val;
 477
 478	ctrl = er32(CTRL);
 479	status = er32(STATUS);
 480	rxcw = er32(RXCW);
 481
 482	/* If we don't have link (auto-negotiation failed or link partner
 483	 * cannot auto-negotiate), the cable is plugged in (we have signal),
 484	 * and our link partner is not trying to auto-negotiate with us (we
 485	 * are receiving idles or data), we need to force link up. We also
 486	 * need to give auto-negotiation time to complete, in case the cable
 487	 * was just plugged in. The autoneg_failed flag does this.
 488	 */
 489	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
 490	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
 491	    !(rxcw & E1000_RXCW_C)) {
 492		if (!mac->autoneg_failed) {
 493			mac->autoneg_failed = true;
 494			return 0;
 495		}
 496		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
 497
 498		/* Disable auto-negotiation in the TXCW register */
 499		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
 500
 501		/* Force link-up and also force full-duplex. */
 502		ctrl = er32(CTRL);
 503		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
 504		ew32(CTRL, ctrl);
 505
 506		/* Configure Flow Control after forcing link up. */
 507		ret_val = e1000e_config_fc_after_link_up(hw);
 508		if (ret_val) {
 509			e_dbg("Error configuring flow control\n");
 510			return ret_val;
 511		}
 512	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
 513		/* If we are forcing link and we are receiving /C/ ordered
 514		 * sets, re-enable auto-negotiation in the TXCW register
 515		 * and disable forced link in the Device Control register
 516		 * in an attempt to auto-negotiate with our link partner.
 517		 */
 518		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
 519		ew32(TXCW, mac->txcw);
 520		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
 521
 522		mac->serdes_has_link = true;
 523	}
 524
 525	return 0;
 526}
 527
 528/**
 529 *  e1000e_check_for_serdes_link - Check for link (Serdes)
 530 *  @hw: pointer to the HW structure
 531 *
 532 *  Checks for link up on the hardware.  If link is not up and we have
 533 *  a signal, then we need to force link up.
 534 **/
 535s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
 536{
 537	struct e1000_mac_info *mac = &hw->mac;
 538	u32 rxcw;
 539	u32 ctrl;
 540	u32 status;
 541	s32 ret_val;
 542
 543	ctrl = er32(CTRL);
 544	status = er32(STATUS);
 545	rxcw = er32(RXCW);
 546
 547	/* If we don't have link (auto-negotiation failed or link partner
 548	 * cannot auto-negotiate), and our link partner is not trying to
 549	 * auto-negotiate with us (we are receiving idles or data),
 550	 * we need to force link up. We also need to give auto-negotiation
 551	 * time to complete.
 552	 */
 553	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
 554	if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
 555		if (!mac->autoneg_failed) {
 556			mac->autoneg_failed = true;
 557			return 0;
 558		}
 559		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
 560
 561		/* Disable auto-negotiation in the TXCW register */
 562		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
 563
 564		/* Force link-up and also force full-duplex. */
 565		ctrl = er32(CTRL);
 566		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
 567		ew32(CTRL, ctrl);
 568
 569		/* Configure Flow Control after forcing link up. */
 570		ret_val = e1000e_config_fc_after_link_up(hw);
 571		if (ret_val) {
 572			e_dbg("Error configuring flow control\n");
 573			return ret_val;
 574		}
 575	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
 576		/* If we are forcing link and we are receiving /C/ ordered
 577		 * sets, re-enable auto-negotiation in the TXCW register
 578		 * and disable forced link in the Device Control register
 579		 * in an attempt to auto-negotiate with our link partner.
 580		 */
 581		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
 582		ew32(TXCW, mac->txcw);
 583		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
 584
 585		mac->serdes_has_link = true;
 586	} else if (!(E1000_TXCW_ANE & er32(TXCW))) {
 587		/* If we force link for non-auto-negotiation switch, check
 588		 * link status based on MAC synchronization for internal
 589		 * serdes media type.
 590		 */
 591		/* SYNCH bit and IV bit are sticky. */
 592		usleep_range(10, 20);
 593		rxcw = er32(RXCW);
 594		if (rxcw & E1000_RXCW_SYNCH) {
 595			if (!(rxcw & E1000_RXCW_IV)) {
 596				mac->serdes_has_link = true;
 597				e_dbg("SERDES: Link up - forced.\n");
 598			}
 599		} else {
 600			mac->serdes_has_link = false;
 601			e_dbg("SERDES: Link down - force failed.\n");
 602		}
 603	}
 604
 605	if (E1000_TXCW_ANE & er32(TXCW)) {
 606		status = er32(STATUS);
 607		if (status & E1000_STATUS_LU) {
 608			/* SYNCH bit and IV bit are sticky, so reread rxcw. */
 609			usleep_range(10, 20);
 610			rxcw = er32(RXCW);
 611			if (rxcw & E1000_RXCW_SYNCH) {
 612				if (!(rxcw & E1000_RXCW_IV)) {
 613					mac->serdes_has_link = true;
 614					e_dbg("SERDES: Link up - autoneg completed successfully.\n");
 615				} else {
 616					mac->serdes_has_link = false;
 617					e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n");
 618				}
 619			} else {
 620				mac->serdes_has_link = false;
 621				e_dbg("SERDES: Link down - no sync.\n");
 622			}
 623		} else {
 624			mac->serdes_has_link = false;
 625			e_dbg("SERDES: Link down - autoneg failed\n");
 626		}
 627	}
 628
 629	return 0;
 630}
 631
 632/**
 633 *  e1000_set_default_fc_generic - Set flow control default values
 634 *  @hw: pointer to the HW structure
 635 *
 636 *  Read the EEPROM for the default values for flow control and store the
 637 *  values.
 638 **/
 639static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
 640{
 641	s32 ret_val;
 642	u16 nvm_data;
 643
 644	/* Read and store word 0x0F of the EEPROM. This word contains bits
 645	 * that determine the hardware's default PAUSE (flow control) mode,
 646	 * a bit that determines whether the HW defaults to enabling or
 647	 * disabling auto-negotiation, and the direction of the
 648	 * SW defined pins. If there is no SW over-ride of the flow
 649	 * control setting, then the variable hw->fc will
 650	 * be initialized based on a value in the EEPROM.
 651	 */
 652	ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
 653
 654	if (ret_val) {
 655		e_dbg("NVM Read Error\n");
 656		return ret_val;
 657	}
 658
 659	if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
 660		hw->fc.requested_mode = e1000_fc_none;
 661	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
 662		hw->fc.requested_mode = e1000_fc_tx_pause;
 663	else
 664		hw->fc.requested_mode = e1000_fc_full;
 665
 666	return 0;
 667}
 668
 669/**
 670 *  e1000e_setup_link_generic - Setup flow control and link settings
 671 *  @hw: pointer to the HW structure
 672 *
 673 *  Determines which flow control settings to use, then configures flow
 674 *  control.  Calls the appropriate media-specific link configuration
 675 *  function.  Assuming the adapter has a valid link partner, a valid link
 676 *  should be established.  Assumes the hardware has previously been reset
 677 *  and the transmitter and receiver are not enabled.
 678 **/
 679s32 e1000e_setup_link_generic(struct e1000_hw *hw)
 680{
 681	s32 ret_val;
 682
 683	/* In the case of the phy reset being blocked, we already have a link.
 684	 * We do not need to set it up again.
 685	 */
 686	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
 687		return 0;
 688
 689	/* If requested flow control is set to default, set flow control
 690	 * based on the EEPROM flow control settings.
 691	 */
 692	if (hw->fc.requested_mode == e1000_fc_default) {
 693		ret_val = e1000_set_default_fc_generic(hw);
 694		if (ret_val)
 695			return ret_val;
 696	}
 697
 698	/* Save off the requested flow control mode for use later.  Depending
 699	 * on the link partner's capabilities, we may or may not use this mode.
 700	 */
 701	hw->fc.current_mode = hw->fc.requested_mode;
 702
 703	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
 704
 705	/* Call the necessary media_type subroutine to configure the link. */
 706	ret_val = hw->mac.ops.setup_physical_interface(hw);
 707	if (ret_val)
 708		return ret_val;
 709
 710	/* Initialize the flow control address, type, and PAUSE timer
 711	 * registers to their default values.  This is done even if flow
 712	 * control is disabled, because it does not hurt anything to
 713	 * initialize these registers.
 714	 */
 715	e_dbg("Initializing the Flow Control address, type and timer regs\n");
 716	ew32(FCT, FLOW_CONTROL_TYPE);
 717	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
 718	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
 719
 720	ew32(FCTTV, hw->fc.pause_time);
 721
 722	return e1000e_set_fc_watermarks(hw);
 723}
 724
 725/**
 726 *  e1000_commit_fc_settings_generic - Configure flow control
 727 *  @hw: pointer to the HW structure
 728 *
 729 *  Write the flow control settings to the Transmit Config Word Register (TXCW)
 730 *  base on the flow control settings in e1000_mac_info.
 731 **/
 732static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
 733{
 734	struct e1000_mac_info *mac = &hw->mac;
 735	u32 txcw;
 736
 737	/* Check for a software override of the flow control settings, and
 738	 * setup the device accordingly.  If auto-negotiation is enabled, then
 739	 * software will have to set the "PAUSE" bits to the correct value in
 740	 * the Transmit Config Word Register (TXCW) and re-start auto-
 741	 * negotiation.  However, if auto-negotiation is disabled, then
 742	 * software will have to manually configure the two flow control enable
 743	 * bits in the CTRL register.
 744	 *
 745	 * The possible values of the "fc" parameter are:
 746	 *      0:  Flow control is completely disabled
 747	 *      1:  Rx flow control is enabled (we can receive pause frames,
 748	 *          but not send pause frames).
 749	 *      2:  Tx flow control is enabled (we can send pause frames but we
 750	 *          do not support receiving pause frames).
 751	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
 752	 */
 753	switch (hw->fc.current_mode) {
 754	case e1000_fc_none:
 755		/* Flow control completely disabled by a software over-ride. */
 756		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
 757		break;
 758	case e1000_fc_rx_pause:
 759		/* Rx Flow control is enabled and Tx Flow control is disabled
 760		 * by a software over-ride. Since there really isn't a way to
 761		 * advertise that we are capable of Rx Pause ONLY, we will
 762		 * advertise that we support both symmetric and asymmetric Rx
 763		 * PAUSE.  Later, we will disable the adapter's ability to send
 764		 * PAUSE frames.
 765		 */
 766		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
 767		break;
 768	case e1000_fc_tx_pause:
 769		/* Tx Flow control is enabled, and Rx Flow control is disabled,
 770		 * by a software over-ride.
 771		 */
 772		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
 773		break;
 774	case e1000_fc_full:
 775		/* Flow control (both Rx and Tx) is enabled by a software
 776		 * over-ride.
 777		 */
 778		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
 779		break;
 780	default:
 781		e_dbg("Flow control param set incorrectly\n");
 782		return -E1000_ERR_CONFIG;
 783	}
 784
 785	ew32(TXCW, txcw);
 786	mac->txcw = txcw;
 787
 788	return 0;
 789}
 790
 791/**
 792 *  e1000_poll_fiber_serdes_link_generic - Poll for link up
 793 *  @hw: pointer to the HW structure
 794 *
 795 *  Polls for link up by reading the status register, if link fails to come
 796 *  up with auto-negotiation, then the link is forced if a signal is detected.
 797 **/
 798static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
 799{
 800	struct e1000_mac_info *mac = &hw->mac;
 801	u32 i, status;
 802	s32 ret_val;
 803
 804	/* If we have a signal (the cable is plugged in, or assumed true for
 805	 * serdes media) then poll for a "Link-Up" indication in the Device
 806	 * Status Register.  Time-out if a link isn't seen in 500 milliseconds
 807	 * seconds (Auto-negotiation should complete in less than 500
 808	 * milliseconds even if the other end is doing it in SW).
 809	 */
 810	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
 811		usleep_range(10000, 11000);
 812		status = er32(STATUS);
 813		if (status & E1000_STATUS_LU)
 814			break;
 815	}
 816	if (i == FIBER_LINK_UP_LIMIT) {
 817		e_dbg("Never got a valid link from auto-neg!!!\n");
 818		mac->autoneg_failed = true;
 819		/* AutoNeg failed to achieve a link, so we'll call
 820		 * mac->check_for_link. This routine will force the
 821		 * link up if we detect a signal. This will allow us to
 822		 * communicate with non-autonegotiating link partners.
 823		 */
 824		ret_val = mac->ops.check_for_link(hw);
 825		if (ret_val) {
 826			e_dbg("Error while checking for link\n");
 827			return ret_val;
 828		}
 829		mac->autoneg_failed = false;
 830	} else {
 831		mac->autoneg_failed = false;
 832		e_dbg("Valid Link Found\n");
 833	}
 834
 835	return 0;
 836}
 837
 838/**
 839 *  e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
 840 *  @hw: pointer to the HW structure
 841 *
 842 *  Configures collision distance and flow control for fiber and serdes
 843 *  links.  Upon successful setup, poll for link.
 844 **/
 845s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
 846{
 847	u32 ctrl;
 848	s32 ret_val;
 849
 850	ctrl = er32(CTRL);
 851
 852	/* Take the link out of reset */
 853	ctrl &= ~E1000_CTRL_LRST;
 854
 855	hw->mac.ops.config_collision_dist(hw);
 856
 857	ret_val = e1000_commit_fc_settings_generic(hw);
 858	if (ret_val)
 859		return ret_val;
 860
 861	/* Since auto-negotiation is enabled, take the link out of reset (the
 862	 * link will be in reset, because we previously reset the chip). This
 863	 * will restart auto-negotiation.  If auto-negotiation is successful
 864	 * then the link-up status bit will be set and the flow control enable
 865	 * bits (RFCE and TFCE) will be set according to their negotiated value.
 866	 */
 867	e_dbg("Auto-negotiation enabled\n");
 868
 869	ew32(CTRL, ctrl);
 870	e1e_flush();
 871	usleep_range(1000, 2000);
 872
 873	/* For these adapters, the SW definable pin 1 is set when the optics
 874	 * detect a signal.  If we have a signal, then poll for a "Link-Up"
 875	 * indication.
 876	 */
 877	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
 878	    (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
 879		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
 880	} else {
 881		e_dbg("No signal detected\n");
 882	}
 883
 884	return ret_val;
 885}
 886
 887/**
 888 *  e1000e_config_collision_dist_generic - Configure collision distance
 889 *  @hw: pointer to the HW structure
 890 *
 891 *  Configures the collision distance to the default value and is used
 892 *  during link setup.
 893 **/
 894void e1000e_config_collision_dist_generic(struct e1000_hw *hw)
 895{
 896	u32 tctl;
 897
 898	tctl = er32(TCTL);
 899
 900	tctl &= ~E1000_TCTL_COLD;
 901	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
 902
 903	ew32(TCTL, tctl);
 904	e1e_flush();
 905}
 906
 907/**
 908 *  e1000e_set_fc_watermarks - Set flow control high/low watermarks
 909 *  @hw: pointer to the HW structure
 910 *
 911 *  Sets the flow control high/low threshold (watermark) registers.  If
 912 *  flow control XON frame transmission is enabled, then set XON frame
 913 *  transmission as well.
 914 **/
 915s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
 916{
 917	u32 fcrtl = 0, fcrth = 0;
 918
 919	/* Set the flow control receive threshold registers.  Normally,
 920	 * these registers will be set to a default threshold that may be
 921	 * adjusted later by the driver's runtime code.  However, if the
 922	 * ability to transmit pause frames is not enabled, then these
 923	 * registers will be set to 0.
 924	 */
 925	if (hw->fc.current_mode & e1000_fc_tx_pause) {
 926		/* We need to set up the Receive Threshold high and low water
 927		 * marks as well as (optionally) enabling the transmission of
 928		 * XON frames.
 929		 */
 930		fcrtl = hw->fc.low_water;
 931		if (hw->fc.send_xon)
 932			fcrtl |= E1000_FCRTL_XONE;
 933
 934		fcrth = hw->fc.high_water;
 935	}
 936	ew32(FCRTL, fcrtl);
 937	ew32(FCRTH, fcrth);
 938
 939	return 0;
 940}
 941
 942/**
 943 *  e1000e_force_mac_fc - Force the MAC's flow control settings
 944 *  @hw: pointer to the HW structure
 945 *
 946 *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
 947 *  device control register to reflect the adapter settings.  TFCE and RFCE
 948 *  need to be explicitly set by software when a copper PHY is used because
 949 *  autonegotiation is managed by the PHY rather than the MAC.  Software must
 950 *  also configure these bits when link is forced on a fiber connection.
 951 **/
 952s32 e1000e_force_mac_fc(struct e1000_hw *hw)
 953{
 954	u32 ctrl;
 955
 956	ctrl = er32(CTRL);
 957
 958	/* Because we didn't get link via the internal auto-negotiation
 959	 * mechanism (we either forced link or we got link via PHY
 960	 * auto-neg), we have to manually enable/disable transmit an
 961	 * receive flow control.
 962	 *
 963	 * The "Case" statement below enables/disable flow control
 964	 * according to the "hw->fc.current_mode" parameter.
 965	 *
 966	 * The possible values of the "fc" parameter are:
 967	 *      0:  Flow control is completely disabled
 968	 *      1:  Rx flow control is enabled (we can receive pause
 969	 *          frames but not send pause frames).
 970	 *      2:  Tx flow control is enabled (we can send pause frames
 971	 *          but we do not receive pause frames).
 972	 *      3:  Both Rx and Tx flow control (symmetric) is enabled.
 973	 *  other:  No other values should be possible at this point.
 974	 */
 975	e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
 976
 977	switch (hw->fc.current_mode) {
 978	case e1000_fc_none:
 979		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
 980		break;
 981	case e1000_fc_rx_pause:
 982		ctrl &= (~E1000_CTRL_TFCE);
 983		ctrl |= E1000_CTRL_RFCE;
 984		break;
 985	case e1000_fc_tx_pause:
 986		ctrl &= (~E1000_CTRL_RFCE);
 987		ctrl |= E1000_CTRL_TFCE;
 988		break;
 989	case e1000_fc_full:
 990		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
 991		break;
 992	default:
 993		e_dbg("Flow control param set incorrectly\n");
 994		return -E1000_ERR_CONFIG;
 995	}
 996
 997	ew32(CTRL, ctrl);
 998
 999	return 0;
1000}
1001
1002/**
1003 *  e1000e_config_fc_after_link_up - Configures flow control after link
1004 *  @hw: pointer to the HW structure
1005 *
1006 *  Checks the status of auto-negotiation after link up to ensure that the
1007 *  speed and duplex were not forced.  If the link needed to be forced, then
1008 *  flow control needs to be forced also.  If auto-negotiation is enabled
1009 *  and did not fail, then we configure flow control based on our link
1010 *  partner.
1011 **/
1012s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1013{
1014	struct e1000_mac_info *mac = &hw->mac;
1015	s32 ret_val = 0;
1016	u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1017	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1018	u16 speed, duplex;
1019
1020	/* Check for the case where we have fiber media and auto-neg failed
1021	 * so we had to force link.  In this case, we need to force the
1022	 * configuration of the MAC to match the "fc" parameter.
1023	 */
1024	if (mac->autoneg_failed) {
1025		if (hw->phy.media_type == e1000_media_type_fiber ||
1026		    hw->phy.media_type == e1000_media_type_internal_serdes)
1027			ret_val = e1000e_force_mac_fc(hw);
1028	} else {
1029		if (hw->phy.media_type == e1000_media_type_copper)
1030			ret_val = e1000e_force_mac_fc(hw);
1031	}
1032
1033	if (ret_val) {
1034		e_dbg("Error forcing flow control settings\n");
1035		return ret_val;
1036	}
1037
1038	/* Check for the case where we have copper media and auto-neg is
1039	 * enabled.  In this case, we need to check and see if Auto-Neg
1040	 * has completed, and if so, how the PHY and link partner has
1041	 * flow control configured.
1042	 */
1043	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1044		/* Read the MII Status Register and check to see if AutoNeg
1045		 * has completed.  We read this twice because this reg has
1046		 * some "sticky" (latched) bits.
1047		 */
1048		ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg);
1049		if (ret_val)
1050			return ret_val;
1051		ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg);
1052		if (ret_val)
1053			return ret_val;
1054
1055		if (!(mii_status_reg & BMSR_ANEGCOMPLETE)) {
1056			e_dbg("Copper PHY and Auto Neg has not completed.\n");
1057			return ret_val;
1058		}
1059
1060		/* The AutoNeg process has completed, so we now need to
1061		 * read both the Auto Negotiation Advertisement
1062		 * Register (Address 4) and the Auto_Negotiation Base
1063		 * Page Ability Register (Address 5) to determine how
1064		 * flow control was negotiated.
1065		 */
1066		ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_nway_adv_reg);
1067		if (ret_val)
1068			return ret_val;
1069		ret_val = e1e_rphy(hw, MII_LPA, &mii_nway_lp_ability_reg);
1070		if (ret_val)
1071			return ret_val;
1072
1073		/* Two bits in the Auto Negotiation Advertisement Register
1074		 * (Address 4) and two bits in the Auto Negotiation Base
1075		 * Page Ability Register (Address 5) determine flow control
1076		 * for both the PHY and the link partner.  The following
1077		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1078		 * 1999, describes these PAUSE resolution bits and how flow
1079		 * control is determined based upon these settings.
1080		 * NOTE:  DC = Don't Care
1081		 *
1082		 *   LOCAL DEVICE  |   LINK PARTNER
1083		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1084		 *-------|---------|-------|---------|--------------------
1085		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1086		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1087		 *   0   |    1    |   1   |    0    | e1000_fc_none
1088		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1089		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1090		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1091		 *   1   |    1    |   0   |    0    | e1000_fc_none
1092		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1093		 *
1094		 * Are both PAUSE bits set to 1?  If so, this implies
1095		 * Symmetric Flow Control is enabled at both ends.  The
1096		 * ASM_DIR bits are irrelevant per the spec.
1097		 *
1098		 * For Symmetric Flow Control:
1099		 *
1100		 *   LOCAL DEVICE  |   LINK PARTNER
1101		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1102		 *-------|---------|-------|---------|--------------------
1103		 *   1   |   DC    |   1   |   DC    | E1000_fc_full
1104		 *
1105		 */
1106		if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1107		    (mii_nway_lp_ability_reg & LPA_PAUSE_CAP)) {
1108			/* Now we need to check if the user selected Rx ONLY
1109			 * of pause frames.  In this case, we had to advertise
1110			 * FULL flow control because we could not advertise Rx
1111			 * ONLY. Hence, we must now check to see if we need to
1112			 * turn OFF the TRANSMISSION of PAUSE frames.
1113			 */
1114			if (hw->fc.requested_mode == e1000_fc_full) {
1115				hw->fc.current_mode = e1000_fc_full;
1116				e_dbg("Flow Control = FULL.\n");
1117			} else {
1118				hw->fc.current_mode = e1000_fc_rx_pause;
1119				e_dbg("Flow Control = Rx PAUSE frames only.\n");
1120			}
1121		}
1122		/* For receiving PAUSE frames ONLY.
1123		 *
1124		 *   LOCAL DEVICE  |   LINK PARTNER
1125		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1126		 *-------|---------|-------|---------|--------------------
1127		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1128		 */
1129		else if (!(mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1130			 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) &&
1131			 (mii_nway_lp_ability_reg & LPA_PAUSE_CAP) &&
1132			 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) {
1133			hw->fc.current_mode = e1000_fc_tx_pause;
1134			e_dbg("Flow Control = Tx PAUSE frames only.\n");
1135		}
1136		/* For transmitting PAUSE frames ONLY.
1137		 *
1138		 *   LOCAL DEVICE  |   LINK PARTNER
1139		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1140		 *-------|---------|-------|---------|--------------------
1141		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1142		 */
1143		else if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1144			 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) &&
1145			 !(mii_nway_lp_ability_reg & LPA_PAUSE_CAP) &&
1146			 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) {
1147			hw->fc.current_mode = e1000_fc_rx_pause;
1148			e_dbg("Flow Control = Rx PAUSE frames only.\n");
1149		} else {
1150			/* Per the IEEE spec, at this point flow control
1151			 * should be disabled.
1152			 */
1153			hw->fc.current_mode = e1000_fc_none;
1154			e_dbg("Flow Control = NONE.\n");
1155		}
1156
1157		/* Now we need to do one last check...  If we auto-
1158		 * negotiated to HALF DUPLEX, flow control should not be
1159		 * enabled per IEEE 802.3 spec.
1160		 */
1161		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1162		if (ret_val) {
1163			e_dbg("Error getting link speed and duplex\n");
1164			return ret_val;
1165		}
1166
1167		if (duplex == HALF_DUPLEX)
1168			hw->fc.current_mode = e1000_fc_none;
1169
1170		/* Now we call a subroutine to actually force the MAC
1171		 * controller to use the correct flow control settings.
1172		 */
1173		ret_val = e1000e_force_mac_fc(hw);
1174		if (ret_val) {
1175			e_dbg("Error forcing flow control settings\n");
1176			return ret_val;
1177		}
1178	}
1179
1180	/* Check for the case where we have SerDes media and auto-neg is
1181	 * enabled.  In this case, we need to check and see if Auto-Neg
1182	 * has completed, and if so, how the PHY and link partner has
1183	 * flow control configured.
1184	 */
1185	if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1186	    mac->autoneg) {
1187		/* Read the PCS_LSTS and check to see if AutoNeg
1188		 * has completed.
1189		 */
1190		pcs_status_reg = er32(PCS_LSTAT);
1191
1192		if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1193			e_dbg("PCS Auto Neg has not completed.\n");
1194			return ret_val;
1195		}
1196
1197		/* The AutoNeg process has completed, so we now need to
1198		 * read both the Auto Negotiation Advertisement
1199		 * Register (PCS_ANADV) and the Auto_Negotiation Base
1200		 * Page Ability Register (PCS_LPAB) to determine how
1201		 * flow control was negotiated.
1202		 */
1203		pcs_adv_reg = er32(PCS_ANADV);
1204		pcs_lp_ability_reg = er32(PCS_LPAB);
1205
1206		/* Two bits in the Auto Negotiation Advertisement Register
1207		 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1208		 * Page Ability Register (PCS_LPAB) determine flow control
1209		 * for both the PHY and the link partner.  The following
1210		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1211		 * 1999, describes these PAUSE resolution bits and how flow
1212		 * control is determined based upon these settings.
1213		 * NOTE:  DC = Don't Care
1214		 *
1215		 *   LOCAL DEVICE  |   LINK PARTNER
1216		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1217		 *-------|---------|-------|---------|--------------------
1218		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1219		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1220		 *   0   |    1    |   1   |    0    | e1000_fc_none
1221		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1222		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1223		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1224		 *   1   |    1    |   0   |    0    | e1000_fc_none
1225		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1226		 *
1227		 * Are both PAUSE bits set to 1?  If so, this implies
1228		 * Symmetric Flow Control is enabled at both ends.  The
1229		 * ASM_DIR bits are irrelevant per the spec.
1230		 *
1231		 * For Symmetric Flow Control:
1232		 *
1233		 *   LOCAL DEVICE  |   LINK PARTNER
1234		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1235		 *-------|---------|-------|---------|--------------------
1236		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1237		 *
1238		 */
1239		if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1240		    (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1241			/* Now we need to check if the user selected Rx ONLY
1242			 * of pause frames.  In this case, we had to advertise
1243			 * FULL flow control because we could not advertise Rx
1244			 * ONLY. Hence, we must now check to see if we need to
1245			 * turn OFF the TRANSMISSION of PAUSE frames.
1246			 */
1247			if (hw->fc.requested_mode == e1000_fc_full) {
1248				hw->fc.current_mode = e1000_fc_full;
1249				e_dbg("Flow Control = FULL.\n");
1250			} else {
1251				hw->fc.current_mode = e1000_fc_rx_pause;
1252				e_dbg("Flow Control = Rx PAUSE frames only.\n");
1253			}
1254		}
1255		/* For receiving PAUSE frames ONLY.
1256		 *
1257		 *   LOCAL DEVICE  |   LINK PARTNER
1258		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1259		 *-------|---------|-------|---------|--------------------
1260		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1261		 */
1262		else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1263			 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1264			 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1265			 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1266			hw->fc.current_mode = e1000_fc_tx_pause;
1267			e_dbg("Flow Control = Tx PAUSE frames only.\n");
1268		}
1269		/* For transmitting PAUSE frames ONLY.
1270		 *
1271		 *   LOCAL DEVICE  |   LINK PARTNER
1272		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1273		 *-------|---------|-------|---------|--------------------
1274		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1275		 */
1276		else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1277			 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1278			 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1279			 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1280			hw->fc.current_mode = e1000_fc_rx_pause;
1281			e_dbg("Flow Control = Rx PAUSE frames only.\n");
1282		} else {
1283			/* Per the IEEE spec, at this point flow control
1284			 * should be disabled.
1285			 */
1286			hw->fc.current_mode = e1000_fc_none;
1287			e_dbg("Flow Control = NONE.\n");
1288		}
1289
1290		/* Now we call a subroutine to actually force the MAC
1291		 * controller to use the correct flow control settings.
1292		 */
1293		pcs_ctrl_reg = er32(PCS_LCTL);
1294		pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1295		ew32(PCS_LCTL, pcs_ctrl_reg);
1296
1297		ret_val = e1000e_force_mac_fc(hw);
1298		if (ret_val) {
1299			e_dbg("Error forcing flow control settings\n");
1300			return ret_val;
1301		}
1302	}
1303
1304	return 0;
1305}
1306
1307/**
1308 *  e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1309 *  @hw: pointer to the HW structure
1310 *  @speed: stores the current speed
1311 *  @duplex: stores the current duplex
1312 *
1313 *  Read the status register for the current speed/duplex and store the current
1314 *  speed and duplex for copper connections.
1315 **/
1316s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1317				       u16 *duplex)
1318{
1319	u32 status;
1320
1321	status = er32(STATUS);
1322	if (status & E1000_STATUS_SPEED_1000)
1323		*speed = SPEED_1000;
1324	else if (status & E1000_STATUS_SPEED_100)
1325		*speed = SPEED_100;
1326	else
1327		*speed = SPEED_10;
1328
1329	if (status & E1000_STATUS_FD)
1330		*duplex = FULL_DUPLEX;
1331	else
1332		*duplex = HALF_DUPLEX;
1333
1334	e_dbg("%u Mbps, %s Duplex\n",
1335	      *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
1336	      *duplex == FULL_DUPLEX ? "Full" : "Half");
1337
1338	return 0;
1339}
1340
1341/**
1342 *  e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1343 *  @hw: pointer to the HW structure
1344 *  @speed: stores the current speed
1345 *  @duplex: stores the current duplex
1346 *
1347 *  Sets the speed and duplex to gigabit full duplex (the only possible option)
1348 *  for fiber/serdes links.
1349 **/
1350s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw __always_unused
1351					     *hw, u16 *speed, u16 *duplex)
1352{
1353	*speed = SPEED_1000;
1354	*duplex = FULL_DUPLEX;
1355
1356	return 0;
1357}
1358
1359/**
1360 *  e1000e_get_hw_semaphore - Acquire hardware semaphore
1361 *  @hw: pointer to the HW structure
1362 *
1363 *  Acquire the HW semaphore to access the PHY or NVM
1364 **/
1365s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1366{
1367	u32 swsm;
1368	s32 timeout = hw->nvm.word_size + 1;
1369	s32 i = 0;
1370
1371	/* Get the SW semaphore */
1372	while (i < timeout) {
1373		swsm = er32(SWSM);
1374		if (!(swsm & E1000_SWSM_SMBI))
1375			break;
1376
1377		udelay(100);
1378		i++;
1379	}
1380
1381	if (i == timeout) {
1382		e_dbg("Driver can't access device - SMBI bit is set.\n");
1383		return -E1000_ERR_NVM;
1384	}
1385
1386	/* Get the FW semaphore. */
1387	for (i = 0; i < timeout; i++) {
1388		swsm = er32(SWSM);
1389		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1390
1391		/* Semaphore acquired if bit latched */
1392		if (er32(SWSM) & E1000_SWSM_SWESMBI)
1393			break;
1394
1395		udelay(100);
1396	}
1397
1398	if (i == timeout) {
1399		/* Release semaphores */
1400		e1000e_put_hw_semaphore(hw);
1401		e_dbg("Driver can't access the NVM\n");
1402		return -E1000_ERR_NVM;
1403	}
1404
1405	return 0;
1406}
1407
1408/**
1409 *  e1000e_put_hw_semaphore - Release hardware semaphore
1410 *  @hw: pointer to the HW structure
1411 *
1412 *  Release hardware semaphore used to access the PHY or NVM
1413 **/
1414void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1415{
1416	u32 swsm;
1417
1418	swsm = er32(SWSM);
1419	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1420	ew32(SWSM, swsm);
1421}
1422
1423/**
1424 *  e1000e_get_auto_rd_done - Check for auto read completion
1425 *  @hw: pointer to the HW structure
1426 *
1427 *  Check EEPROM for Auto Read done bit.
1428 **/
1429s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1430{
1431	s32 i = 0;
1432
1433	while (i < AUTO_READ_DONE_TIMEOUT) {
1434		if (er32(EECD) & E1000_EECD_AUTO_RD)
1435			break;
1436		usleep_range(1000, 2000);
1437		i++;
1438	}
1439
1440	if (i == AUTO_READ_DONE_TIMEOUT) {
1441		e_dbg("Auto read by HW from NVM has not completed.\n");
1442		return -E1000_ERR_RESET;
1443	}
1444
1445	return 0;
1446}
1447
1448/**
1449 *  e1000e_valid_led_default - Verify a valid default LED config
1450 *  @hw: pointer to the HW structure
1451 *  @data: pointer to the NVM (EEPROM)
1452 *
1453 *  Read the EEPROM for the current default LED configuration.  If the
1454 *  LED configuration is not valid, set to a valid LED configuration.
1455 **/
1456s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1457{
1458	s32 ret_val;
1459
1460	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1461	if (ret_val) {
1462		e_dbg("NVM Read Error\n");
1463		return ret_val;
1464	}
1465
1466	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1467		*data = ID_LED_DEFAULT;
1468
1469	return 0;
1470}
1471
1472/**
1473 *  e1000e_id_led_init_generic -
1474 *  @hw: pointer to the HW structure
1475 *
1476 **/
1477s32 e1000e_id_led_init_generic(struct e1000_hw *hw)
1478{
1479	struct e1000_mac_info *mac = &hw->mac;
1480	s32 ret_val;
1481	const u32 ledctl_mask = 0x000000FF;
1482	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1483	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1484	u16 data, i, temp;
1485	const u16 led_mask = 0x0F;
1486
1487	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1488	if (ret_val)
1489		return ret_val;
1490
1491	mac->ledctl_default = er32(LEDCTL);
1492	mac->ledctl_mode1 = mac->ledctl_default;
1493	mac->ledctl_mode2 = mac->ledctl_default;
1494
1495	for (i = 0; i < 4; i++) {
1496		temp = (data >> (i << 2)) & led_mask;
1497		switch (temp) {
1498		case ID_LED_ON1_DEF2:
1499		case ID_LED_ON1_ON2:
1500		case ID_LED_ON1_OFF2:
1501			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1502			mac->ledctl_mode1 |= ledctl_on << (i << 3);
1503			break;
1504		case ID_LED_OFF1_DEF2:
1505		case ID_LED_OFF1_ON2:
1506		case ID_LED_OFF1_OFF2:
1507			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1508			mac->ledctl_mode1 |= ledctl_off << (i << 3);
1509			break;
1510		default:
1511			/* Do nothing */
1512			break;
1513		}
1514		switch (temp) {
1515		case ID_LED_DEF1_ON2:
1516		case ID_LED_ON1_ON2:
1517		case ID_LED_OFF1_ON2:
1518			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1519			mac->ledctl_mode2 |= ledctl_on << (i << 3);
1520			break;
1521		case ID_LED_DEF1_OFF2:
1522		case ID_LED_ON1_OFF2:
1523		case ID_LED_OFF1_OFF2:
1524			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1525			mac->ledctl_mode2 |= ledctl_off << (i << 3);
1526			break;
1527		default:
1528			/* Do nothing */
1529			break;
1530		}
1531	}
1532
1533	return 0;
1534}
1535
1536/**
1537 *  e1000e_setup_led_generic - Configures SW controllable LED
1538 *  @hw: pointer to the HW structure
1539 *
1540 *  This prepares the SW controllable LED for use and saves the current state
1541 *  of the LED so it can be later restored.
1542 **/
1543s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1544{
1545	u32 ledctl;
1546
1547	if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1548		return -E1000_ERR_CONFIG;
1549
1550	if (hw->phy.media_type == e1000_media_type_fiber) {
1551		ledctl = er32(LEDCTL);
1552		hw->mac.ledctl_default = ledctl;
1553		/* Turn off LED0 */
1554		ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1555			    E1000_LEDCTL_LED0_MODE_MASK);
1556		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1557			   E1000_LEDCTL_LED0_MODE_SHIFT);
1558		ew32(LEDCTL, ledctl);
1559	} else if (hw->phy.media_type == e1000_media_type_copper) {
1560		ew32(LEDCTL, hw->mac.ledctl_mode1);
1561	}
1562
1563	return 0;
1564}
1565
1566/**
1567 *  e1000e_cleanup_led_generic - Set LED config to default operation
1568 *  @hw: pointer to the HW structure
1569 *
1570 *  Remove the current LED configuration and set the LED configuration
1571 *  to the default value, saved from the EEPROM.
1572 **/
1573s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1574{
1575	ew32(LEDCTL, hw->mac.ledctl_default);
1576	return 0;
1577}
1578
1579/**
1580 *  e1000e_blink_led_generic - Blink LED
1581 *  @hw: pointer to the HW structure
1582 *
1583 *  Blink the LEDs which are set to be on.
1584 **/
1585s32 e1000e_blink_led_generic(struct e1000_hw *hw)
1586{
1587	u32 ledctl_blink = 0;
1588	u32 i;
1589
1590	if (hw->phy.media_type == e1000_media_type_fiber) {
1591		/* always blink LED0 for PCI-E fiber */
1592		ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1593		    (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1594	} else {
1595		/* Set the blink bit for each LED that's "on" (0x0E)
1596		 * (or "off" if inverted) in ledctl_mode2.  The blink
1597		 * logic in hardware only works when mode is set to "on"
1598		 * so it must be changed accordingly when the mode is
1599		 * "off" and inverted.
1600		 */
1601		ledctl_blink = hw->mac.ledctl_mode2;
1602		for (i = 0; i < 32; i += 8) {
1603			u32 mode = (hw->mac.ledctl_mode2 >> i) &
1604			    E1000_LEDCTL_LED0_MODE_MASK;
1605			u32 led_default = hw->mac.ledctl_default >> i;
1606
1607			if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1608			     (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1609			    ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1610			     (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1611				ledctl_blink &=
1612				    ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1613				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1614						 E1000_LEDCTL_MODE_LED_ON) << i;
1615			}
1616		}
1617	}
1618
1619	ew32(LEDCTL, ledctl_blink);
1620
1621	return 0;
1622}
1623
1624/**
1625 *  e1000e_led_on_generic - Turn LED on
1626 *  @hw: pointer to the HW structure
1627 *
1628 *  Turn LED on.
1629 **/
1630s32 e1000e_led_on_generic(struct e1000_hw *hw)
1631{
1632	u32 ctrl;
1633
1634	switch (hw->phy.media_type) {
1635	case e1000_media_type_fiber:
1636		ctrl = er32(CTRL);
1637		ctrl &= ~E1000_CTRL_SWDPIN0;
1638		ctrl |= E1000_CTRL_SWDPIO0;
1639		ew32(CTRL, ctrl);
1640		break;
1641	case e1000_media_type_copper:
1642		ew32(LEDCTL, hw->mac.ledctl_mode2);
1643		break;
1644	default:
1645		break;
1646	}
1647
1648	return 0;
1649}
1650
1651/**
1652 *  e1000e_led_off_generic - Turn LED off
1653 *  @hw: pointer to the HW structure
1654 *
1655 *  Turn LED off.
1656 **/
1657s32 e1000e_led_off_generic(struct e1000_hw *hw)
1658{
1659	u32 ctrl;
1660
1661	switch (hw->phy.media_type) {
1662	case e1000_media_type_fiber:
1663		ctrl = er32(CTRL);
1664		ctrl |= E1000_CTRL_SWDPIN0;
1665		ctrl |= E1000_CTRL_SWDPIO0;
1666		ew32(CTRL, ctrl);
1667		break;
1668	case e1000_media_type_copper:
1669		ew32(LEDCTL, hw->mac.ledctl_mode1);
1670		break;
1671	default:
1672		break;
1673	}
1674
1675	return 0;
1676}
1677
1678/**
1679 *  e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1680 *  @hw: pointer to the HW structure
1681 *  @no_snoop: bitmap of snoop events
1682 *
1683 *  Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1684 **/
1685void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1686{
1687	u32 gcr;
1688
1689	if (no_snoop) {
1690		gcr = er32(GCR);
1691		gcr &= ~(PCIE_NO_SNOOP_ALL);
1692		gcr |= no_snoop;
1693		ew32(GCR, gcr);
1694	}
1695}
1696
1697/**
1698 *  e1000e_disable_pcie_master - Disables PCI-express master access
1699 *  @hw: pointer to the HW structure
1700 *
1701 *  Returns 0 if successful, else returns -10
1702 *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1703 *  the master requests to be disabled.
1704 *
1705 *  Disables PCI-Express master access and verifies there are no pending
1706 *  requests.
1707 **/
1708s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1709{
1710	u32 ctrl;
1711	s32 timeout = MASTER_DISABLE_TIMEOUT;
1712
1713	ctrl = er32(CTRL);
1714	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1715	ew32(CTRL, ctrl);
1716
1717	while (timeout) {
1718		if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
1719			break;
1720		usleep_range(100, 200);
1721		timeout--;
1722	}
1723
1724	if (!timeout) {
1725		e_dbg("Master requests are pending.\n");
1726		return -E1000_ERR_MASTER_REQUESTS_PENDING;
1727	}
1728
1729	return 0;
1730}
1731
1732/**
1733 *  e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1734 *  @hw: pointer to the HW structure
1735 *
1736 *  Reset the Adaptive Interframe Spacing throttle to default values.
1737 **/
1738void e1000e_reset_adaptive(struct e1000_hw *hw)
1739{
1740	struct e1000_mac_info *mac = &hw->mac;
1741
1742	if (!mac->adaptive_ifs) {
1743		e_dbg("Not in Adaptive IFS mode!\n");
1744		return;
1745	}
1746
1747	mac->current_ifs_val = 0;
1748	mac->ifs_min_val = IFS_MIN;
1749	mac->ifs_max_val = IFS_MAX;
1750	mac->ifs_step_size = IFS_STEP;
1751	mac->ifs_ratio = IFS_RATIO;
1752
1753	mac->in_ifs_mode = false;
1754	ew32(AIT, 0);
1755}
1756
1757/**
1758 *  e1000e_update_adaptive - Update Adaptive Interframe Spacing
1759 *  @hw: pointer to the HW structure
1760 *
1761 *  Update the Adaptive Interframe Spacing Throttle value based on the
1762 *  time between transmitted packets and time between collisions.
1763 **/
1764void e1000e_update_adaptive(struct e1000_hw *hw)
1765{
1766	struct e1000_mac_info *mac = &hw->mac;
1767
1768	if (!mac->adaptive_ifs) {
1769		e_dbg("Not in Adaptive IFS mode!\n");
1770		return;
1771	}
1772
1773	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1774		if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1775			mac->in_ifs_mode = true;
1776			if (mac->current_ifs_val < mac->ifs_max_val) {
1777				if (!mac->current_ifs_val)
1778					mac->current_ifs_val = mac->ifs_min_val;
1779				else
1780					mac->current_ifs_val +=
1781					    mac->ifs_step_size;
1782				ew32(AIT, mac->current_ifs_val);
1783			}
1784		}
1785	} else {
1786		if (mac->in_ifs_mode &&
1787		    (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1788			mac->current_ifs_val = 0;
1789			mac->in_ifs_mode = false;
1790			ew32(AIT, 0);
1791		}
1792	}
1793}