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ich8lan.c
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linux-6.19.14/drivers/net/ethernet/intel/e1000e/ich8lan.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4/* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41#include "e1000.h" 42 43/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44/* Offset 04h HSFSTS */ 45union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58}; 59 60/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61/* Offset 06h FLCTL */ 62union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71}; 72 73/* ICH Flash Region Access Permissions */ 74union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82}; 83 84/* ICH Flash Protected Region */ 85union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95}; 96 97static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142{ 143 return readw(hw->flash_address + reg); 144} 145 146static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147{ 148 return readl(hw->flash_address + reg); 149} 150 151static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152{ 153 writew(val, hw->flash_address + reg); 154} 155 156static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157{ 158 writel(val, hw->flash_address + reg); 159} 160 161#define er16flash(reg) __er16flash(hw, (reg)) 162#define er32flash(reg) __er32flash(hw, (reg)) 163#define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164#define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166/** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177{ 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Switching PHY interface always returns MDI error 226 * so disable retry mechanism to avoid wasting time 227 */ 228 e1000e_disable_phy_retry(hw); 229 230 /* Unforce SMBus mode in PHY */ 231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 232 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 233 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 234 235 e1000e_enable_phy_retry(hw); 236 237 /* Unforce SMBus mode in MAC */ 238 mac_reg = er32(CTRL_EXT); 239 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 240 ew32(CTRL_EXT, mac_reg); 241 } 242 } 243 244 return true; 245} 246 247/** 248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 249 * @hw: pointer to the HW structure 250 * 251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 252 * used to reset the PHY to a quiescent state when necessary. 253 **/ 254static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 255{ 256 u32 mac_reg; 257 258 /* Set Phy Config Counter to 50msec */ 259 mac_reg = er32(FEXTNVM3); 260 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 261 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 262 ew32(FEXTNVM3, mac_reg); 263 264 /* Toggle LANPHYPC Value bit */ 265 mac_reg = er32(CTRL); 266 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 267 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 268 ew32(CTRL, mac_reg); 269 e1e_flush(); 270 usleep_range(10, 20); 271 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 272 ew32(CTRL, mac_reg); 273 e1e_flush(); 274 275 if (hw->mac.type < e1000_pch_lpt) { 276 msleep(50); 277 } else { 278 u16 count = 20; 279 280 do { 281 usleep_range(5000, 6000); 282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 283 284 msleep(30); 285 } 286} 287 288/** 289 * e1000_reconfigure_k1_params - reconfigure Kumeran K1 parameters. 290 * @hw: pointer to the HW structure 291 * 292 * By default K1 is enabled after MAC reset, so this function only 293 * disables it. 294 * 295 * Context: PHY semaphore must be held by caller. 296 * Return: 0 on success, negative on failure 297 */ 298static s32 e1000_reconfigure_k1_params(struct e1000_hw *hw) 299{ 300 u16 phy_timeout; 301 u32 fextnvm12; 302 s32 ret_val; 303 304 if (hw->mac.type < e1000_pch_mtp) { 305 if (hw->adapter->flags2 & FLAG2_DISABLE_K1) 306 return e1000_configure_k1_ich8lan(hw, false); 307 return 0; 308 } 309 310 /* Change Kumeran K1 power down state from P0s to P1 */ 311 fextnvm12 = er32(FEXTNVM12); 312 fextnvm12 &= ~E1000_FEXTNVM12_PHYPD_CTRL_MASK; 313 fextnvm12 |= E1000_FEXTNVM12_PHYPD_CTRL_P1; 314 ew32(FEXTNVM12, fextnvm12); 315 316 /* Wait for the interface the settle */ 317 usleep_range(1000, 1100); 318 if (hw->adapter->flags2 & FLAG2_DISABLE_K1) 319 return e1000_configure_k1_ich8lan(hw, false); 320 321 /* Change K1 exit timeout */ 322 ret_val = e1e_rphy_locked(hw, I217_PHY_TIMEOUTS_REG, 323 &phy_timeout); 324 if (ret_val) 325 return ret_val; 326 327 phy_timeout &= ~I217_PHY_TIMEOUTS_K1_EXIT_TO_MASK; 328 phy_timeout |= 0xF00; 329 330 return e1e_wphy_locked(hw, I217_PHY_TIMEOUTS_REG, 331 phy_timeout); 332} 333 334/** 335 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 336 * @hw: pointer to the HW structure 337 * 338 * Workarounds/flow necessary for PHY initialization during driver load 339 * and resume paths. 340 **/ 341static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 342{ 343 struct e1000_adapter *adapter = hw->adapter; 344 u32 mac_reg, fwsm = er32(FWSM); 345 s32 ret_val; 346 347 /* Gate automatic PHY configuration by hardware on managed and 348 * non-managed 82579 and newer adapters. 349 */ 350 e1000_gate_hw_phy_config_ich8lan(hw, true); 351 352 /* It is not possible to be certain of the current state of ULP 353 * so forcibly disable it. 354 */ 355 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 356 ret_val = e1000_disable_ulp_lpt_lp(hw, true); 357 if (ret_val) 358 e_warn("Failed to disable ULP\n"); 359 360 ret_val = hw->phy.ops.acquire(hw); 361 if (ret_val) { 362 e_dbg("Failed to initialize PHY flow\n"); 363 goto out; 364 } 365 366 /* There is no guarantee that the PHY is accessible at this time 367 * so disable retry mechanism to avoid wasting time 368 */ 369 e1000e_disable_phy_retry(hw); 370 371 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 372 * inaccessible and resetting the PHY is not blocked, toggle the 373 * LANPHYPC Value bit to force the interconnect to PCIe mode. 374 */ 375 switch (hw->mac.type) { 376 case e1000_pch_mtp: 377 case e1000_pch_lnp: 378 case e1000_pch_ptp: 379 case e1000_pch_nvp: 380 /* At this point the PHY might be inaccessible so don't 381 * propagate the failure 382 */ 383 if (e1000_reconfigure_k1_params(hw)) 384 e_dbg("Failed to reconfigure K1 parameters\n"); 385 386 fallthrough; 387 case e1000_pch_lpt: 388 case e1000_pch_spt: 389 case e1000_pch_cnp: 390 case e1000_pch_tgp: 391 case e1000_pch_adp: 392 if (e1000_phy_is_accessible_pchlan(hw)) 393 break; 394 395 /* Before toggling LANPHYPC, see if PHY is accessible by 396 * forcing MAC to SMBus mode first. 397 */ 398 mac_reg = er32(CTRL_EXT); 399 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 400 ew32(CTRL_EXT, mac_reg); 401 402 /* Wait 50 milliseconds for MAC to finish any retries 403 * that it might be trying to perform from previous 404 * attempts to acknowledge any phy read requests. 405 */ 406 msleep(50); 407 408 fallthrough; 409 case e1000_pch2lan: 410 if (e1000_phy_is_accessible_pchlan(hw)) 411 break; 412 413 fallthrough; 414 case e1000_pchlan: 415 if ((hw->mac.type == e1000_pchlan) && 416 (fwsm & E1000_ICH_FWSM_FW_VALID)) 417 break; 418 419 if (hw->phy.ops.check_reset_block(hw)) { 420 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 421 ret_val = -E1000_ERR_PHY; 422 break; 423 } 424 425 /* Toggle LANPHYPC Value bit */ 426 e1000_toggle_lanphypc_pch_lpt(hw); 427 if (hw->mac.type >= e1000_pch_lpt) { 428 if (e1000_phy_is_accessible_pchlan(hw)) 429 break; 430 431 /* Toggling LANPHYPC brings the PHY out of SMBus mode 432 * so ensure that the MAC is also out of SMBus mode 433 */ 434 mac_reg = er32(CTRL_EXT); 435 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 436 ew32(CTRL_EXT, mac_reg); 437 438 if (e1000_phy_is_accessible_pchlan(hw)) 439 break; 440 441 ret_val = -E1000_ERR_PHY; 442 } 443 break; 444 default: 445 break; 446 } 447 448 e1000e_enable_phy_retry(hw); 449 450 hw->phy.ops.release(hw); 451 if (!ret_val) { 452 453 /* Check to see if able to reset PHY. Print error if not */ 454 if (hw->phy.ops.check_reset_block(hw)) { 455 e_err("Reset blocked by ME\n"); 456 goto out; 457 } 458 459 /* Reset the PHY before any access to it. Doing so, ensures 460 * that the PHY is in a known good state before we read/write 461 * PHY registers. The generic reset is sufficient here, 462 * because we haven't determined the PHY type yet. 463 */ 464 ret_val = e1000e_phy_hw_reset_generic(hw); 465 if (ret_val) 466 goto out; 467 468 /* On a successful reset, possibly need to wait for the PHY 469 * to quiesce to an accessible state before returning control 470 * to the calling function. If the PHY does not quiesce, then 471 * return E1000E_BLK_PHY_RESET, as this is the condition that 472 * the PHY is in. 473 */ 474 ret_val = hw->phy.ops.check_reset_block(hw); 475 if (ret_val) { 476 e_err("ME blocked access to PHY after reset\n"); 477 goto out; 478 } 479 480 if (hw->mac.type >= e1000_pch_mtp) { 481 ret_val = hw->phy.ops.acquire(hw); 482 if (ret_val) { 483 e_err("Failed to reconfigure K1 parameters\n"); 484 goto out; 485 } 486 ret_val = e1000_reconfigure_k1_params(hw); 487 hw->phy.ops.release(hw); 488 } 489 } 490 491out: 492 /* Ungate automatic PHY configuration on non-managed 82579 */ 493 if ((hw->mac.type == e1000_pch2lan) && 494 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 495 usleep_range(10000, 11000); 496 e1000_gate_hw_phy_config_ich8lan(hw, false); 497 } 498 499 return ret_val; 500} 501 502/** 503 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 504 * @hw: pointer to the HW structure 505 * 506 * Initialize family-specific PHY parameters and function pointers. 507 **/ 508static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 509{ 510 struct e1000_phy_info *phy = &hw->phy; 511 s32 ret_val; 512 513 phy->addr = 1; 514 phy->reset_delay_us = 100; 515 516 phy->ops.set_page = e1000_set_page_igp; 517 phy->ops.read_reg = e1000_read_phy_reg_hv; 518 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 519 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 520 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 521 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 522 phy->ops.write_reg = e1000_write_phy_reg_hv; 523 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 524 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 525 phy->ops.power_up = e1000_power_up_phy_copper; 526 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 527 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 528 529 phy->id = e1000_phy_unknown; 530 531 if (hw->mac.type == e1000_pch_mtp) { 532 phy->retry_count = 2; 533 e1000e_enable_phy_retry(hw); 534 } 535 536 ret_val = e1000_init_phy_workarounds_pchlan(hw); 537 if (ret_val) 538 return ret_val; 539 540 if (phy->id == e1000_phy_unknown) 541 switch (hw->mac.type) { 542 default: 543 ret_val = e1000e_get_phy_id(hw); 544 if (ret_val) 545 return ret_val; 546 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 547 break; 548 fallthrough; 549 case e1000_pch2lan: 550 case e1000_pch_lpt: 551 case e1000_pch_spt: 552 case e1000_pch_cnp: 553 case e1000_pch_tgp: 554 case e1000_pch_adp: 555 case e1000_pch_mtp: 556 case e1000_pch_lnp: 557 case e1000_pch_ptp: 558 case e1000_pch_nvp: 559 /* In case the PHY needs to be in mdio slow mode, 560 * set slow mode and try to get the PHY id again. 561 */ 562 ret_val = e1000_set_mdio_slow_mode_hv(hw); 563 if (ret_val) 564 return ret_val; 565 ret_val = e1000e_get_phy_id(hw); 566 if (ret_val) 567 return ret_val; 568 break; 569 } 570 phy->type = e1000e_get_phy_type_from_id(phy->id); 571 572 switch (phy->type) { 573 case e1000_phy_82577: 574 case e1000_phy_82579: 575 case e1000_phy_i217: 576 phy->ops.check_polarity = e1000_check_polarity_82577; 577 phy->ops.force_speed_duplex = 578 e1000_phy_force_speed_duplex_82577; 579 phy->ops.get_cable_length = e1000_get_cable_length_82577; 580 phy->ops.get_info = e1000_get_phy_info_82577; 581 phy->ops.commit = e1000e_phy_sw_reset; 582 break; 583 case e1000_phy_82578: 584 phy->ops.check_polarity = e1000_check_polarity_m88; 585 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 586 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 587 phy->ops.get_info = e1000e_get_phy_info_m88; 588 break; 589 default: 590 ret_val = -E1000_ERR_PHY; 591 break; 592 } 593 594 return ret_val; 595} 596 597/** 598 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 599 * @hw: pointer to the HW structure 600 * 601 * Initialize family-specific PHY parameters and function pointers. 602 **/ 603static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 604{ 605 struct e1000_phy_info *phy = &hw->phy; 606 s32 ret_val; 607 u16 i = 0; 608 609 phy->addr = 1; 610 phy->reset_delay_us = 100; 611 612 phy->ops.power_up = e1000_power_up_phy_copper; 613 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 614 615 /* We may need to do this twice - once for IGP and if that fails, 616 * we'll set BM func pointers and try again 617 */ 618 ret_val = e1000e_determine_phy_address(hw); 619 if (ret_val) { 620 phy->ops.write_reg = e1000e_write_phy_reg_bm; 621 phy->ops.read_reg = e1000e_read_phy_reg_bm; 622 ret_val = e1000e_determine_phy_address(hw); 623 if (ret_val) { 624 e_dbg("Cannot determine PHY addr. Erroring out\n"); 625 return ret_val; 626 } 627 } 628 629 phy->id = 0; 630 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 631 (i++ < 100)) { 632 usleep_range(1000, 1100); 633 ret_val = e1000e_get_phy_id(hw); 634 if (ret_val) 635 return ret_val; 636 } 637 638 /* Verify phy id */ 639 switch (phy->id) { 640 case IGP03E1000_E_PHY_ID: 641 phy->type = e1000_phy_igp_3; 642 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 643 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 644 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 645 phy->ops.get_info = e1000e_get_phy_info_igp; 646 phy->ops.check_polarity = e1000_check_polarity_igp; 647 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 648 break; 649 case IFE_E_PHY_ID: 650 case IFE_PLUS_E_PHY_ID: 651 case IFE_C_E_PHY_ID: 652 phy->type = e1000_phy_ife; 653 phy->autoneg_mask = E1000_ALL_NOT_GIG; 654 phy->ops.get_info = e1000_get_phy_info_ife; 655 phy->ops.check_polarity = e1000_check_polarity_ife; 656 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 657 break; 658 case BME1000_E_PHY_ID: 659 phy->type = e1000_phy_bm; 660 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 661 phy->ops.read_reg = e1000e_read_phy_reg_bm; 662 phy->ops.write_reg = e1000e_write_phy_reg_bm; 663 phy->ops.commit = e1000e_phy_sw_reset; 664 phy->ops.get_info = e1000e_get_phy_info_m88; 665 phy->ops.check_polarity = e1000_check_polarity_m88; 666 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 667 break; 668 default: 669 return -E1000_ERR_PHY; 670 } 671 672 return 0; 673} 674 675/** 676 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 677 * @hw: pointer to the HW structure 678 * 679 * Initialize family-specific NVM parameters and function 680 * pointers. 681 **/ 682static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 683{ 684 struct e1000_nvm_info *nvm = &hw->nvm; 685 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 686 u32 gfpreg, sector_base_addr, sector_end_addr; 687 u16 i; 688 u32 nvm_size; 689 690 nvm->type = e1000_nvm_flash_sw; 691 692 if (hw->mac.type >= e1000_pch_spt) { 693 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 694 * STRAP register. This is because in SPT the GbE Flash region 695 * is no longer accessed through the flash registers. Instead, 696 * the mechanism has changed, and the Flash region access 697 * registers are now implemented in GbE memory space. 698 */ 699 nvm->flash_base_addr = 0; 700 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 701 * NVM_SIZE_MULTIPLIER; 702 nvm->flash_bank_size = nvm_size / 2; 703 /* Adjust to word count */ 704 nvm->flash_bank_size /= sizeof(u16); 705 /* Set the base address for flash register access */ 706 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 707 } else { 708 /* Can't read flash registers if register set isn't mapped. */ 709 if (!hw->flash_address) { 710 e_dbg("ERROR: Flash registers not mapped\n"); 711 return -E1000_ERR_CONFIG; 712 } 713 714 gfpreg = er32flash(ICH_FLASH_GFPREG); 715 716 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 717 * Add 1 to sector_end_addr since this sector is included in 718 * the overall size. 719 */ 720 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 721 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 722 723 /* flash_base_addr is byte-aligned */ 724 nvm->flash_base_addr = sector_base_addr 725 << FLASH_SECTOR_ADDR_SHIFT; 726 727 /* find total size of the NVM, then cut in half since the total 728 * size represents two separate NVM banks. 729 */ 730 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 731 << FLASH_SECTOR_ADDR_SHIFT); 732 nvm->flash_bank_size /= 2; 733 /* Adjust to word count */ 734 nvm->flash_bank_size /= sizeof(u16); 735 } 736 737 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 738 739 /* Clear shadow ram */ 740 for (i = 0; i < nvm->word_size; i++) { 741 dev_spec->shadow_ram[i].modified = false; 742 dev_spec->shadow_ram[i].value = 0xFFFF; 743 } 744 745 return 0; 746} 747 748/** 749 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 750 * @hw: pointer to the HW structure 751 * 752 * Initialize family-specific MAC parameters and function 753 * pointers. 754 **/ 755static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 756{ 757 struct e1000_mac_info *mac = &hw->mac; 758 759 /* Set media type function pointer */ 760 hw->phy.media_type = e1000_media_type_copper; 761 762 /* Set mta register count */ 763 mac->mta_reg_count = 32; 764 /* Set rar entry count */ 765 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 766 if (mac->type == e1000_ich8lan) 767 mac->rar_entry_count--; 768 /* FWSM register */ 769 mac->has_fwsm = true; 770 /* ARC subsystem not supported */ 771 mac->arc_subsystem_valid = false; 772 /* Adaptive IFS supported */ 773 mac->adaptive_ifs = true; 774 775 /* LED and other operations */ 776 switch (mac->type) { 777 case e1000_ich8lan: 778 case e1000_ich9lan: 779 case e1000_ich10lan: 780 /* check management mode */ 781 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 782 /* ID LED init */ 783 mac->ops.id_led_init = e1000e_id_led_init_generic; 784 /* blink LED */ 785 mac->ops.blink_led = e1000e_blink_led_generic; 786 /* setup LED */ 787 mac->ops.setup_led = e1000e_setup_led_generic; 788 /* cleanup LED */ 789 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 790 /* turn on/off LED */ 791 mac->ops.led_on = e1000_led_on_ich8lan; 792 mac->ops.led_off = e1000_led_off_ich8lan; 793 break; 794 case e1000_pch2lan: 795 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 796 mac->ops.rar_set = e1000_rar_set_pch2lan; 797 fallthrough; 798 case e1000_pch_lpt: 799 case e1000_pch_spt: 800 case e1000_pch_cnp: 801 case e1000_pch_tgp: 802 case e1000_pch_adp: 803 case e1000_pch_mtp: 804 case e1000_pch_lnp: 805 case e1000_pch_ptp: 806 case e1000_pch_nvp: 807 case e1000_pchlan: 808 /* check management mode */ 809 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 810 /* ID LED init */ 811 mac->ops.id_led_init = e1000_id_led_init_pchlan; 812 /* setup LED */ 813 mac->ops.setup_led = e1000_setup_led_pchlan; 814 /* cleanup LED */ 815 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 816 /* turn on/off LED */ 817 mac->ops.led_on = e1000_led_on_pchlan; 818 mac->ops.led_off = e1000_led_off_pchlan; 819 break; 820 default: 821 break; 822 } 823 824 if (mac->type >= e1000_pch_lpt) { 825 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 826 mac->ops.rar_set = e1000_rar_set_pch_lpt; 827 mac->ops.setup_physical_interface = 828 e1000_setup_copper_link_pch_lpt; 829 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 830 } 831 832 /* Enable PCS Lock-loss workaround for ICH8 */ 833 if (mac->type == e1000_ich8lan) 834 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 835 836 return 0; 837} 838 839/** 840 * __e1000_access_emi_reg_locked - Read/write EMI register 841 * @hw: pointer to the HW structure 842 * @address: EMI address to program 843 * @data: pointer to value to read/write from/to the EMI address 844 * @read: boolean flag to indicate read or write 845 * 846 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 847 **/ 848static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 849 u16 *data, bool read) 850{ 851 s32 ret_val; 852 853 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 854 if (ret_val) 855 return ret_val; 856 857 if (read) 858 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 859 else 860 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 861 862 return ret_val; 863} 864 865/** 866 * e1000_read_emi_reg_locked - Read Extended Management Interface register 867 * @hw: pointer to the HW structure 868 * @addr: EMI address to program 869 * @data: value to be read from the EMI address 870 * 871 * Assumes the SW/FW/HW Semaphore is already acquired. 872 **/ 873s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 874{ 875 return __e1000_access_emi_reg_locked(hw, addr, data, true); 876} 877 878/** 879 * e1000_write_emi_reg_locked - Write Extended Management Interface register 880 * @hw: pointer to the HW structure 881 * @addr: EMI address to program 882 * @data: value to be written to the EMI address 883 * 884 * Assumes the SW/FW/HW Semaphore is already acquired. 885 **/ 886s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 887{ 888 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 889} 890 891/** 892 * e1000_set_eee_pchlan - Enable/disable EEE support 893 * @hw: pointer to the HW structure 894 * 895 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 896 * the link and the EEE capabilities of the link partner. The LPI Control 897 * register bits will remain set only if/when link is up. 898 * 899 * EEE LPI must not be asserted earlier than one second after link is up. 900 * On 82579, EEE LPI should not be enabled until such time otherwise there 901 * can be link issues with some switches. Other devices can have EEE LPI 902 * enabled immediately upon link up since they have a timer in hardware which 903 * prevents LPI from being asserted too early. 904 **/ 905s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 906{ 907 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 908 s32 ret_val; 909 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 910 911 switch (hw->phy.type) { 912 case e1000_phy_82579: 913 lpa = I82579_EEE_LP_ABILITY; 914 pcs_status = I82579_EEE_PCS_STATUS; 915 adv_addr = I82579_EEE_ADVERTISEMENT; 916 break; 917 case e1000_phy_i217: 918 lpa = I217_EEE_LP_ABILITY; 919 pcs_status = I217_EEE_PCS_STATUS; 920 adv_addr = I217_EEE_ADVERTISEMENT; 921 break; 922 default: 923 return 0; 924 } 925 926 ret_val = hw->phy.ops.acquire(hw); 927 if (ret_val) 928 return ret_val; 929 930 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 931 if (ret_val) 932 goto release; 933 934 /* Clear bits that enable EEE in various speeds */ 935 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 936 937 /* Enable EEE if not disabled by user */ 938 if (!dev_spec->eee_disable) { 939 /* Save off link partner's EEE ability */ 940 ret_val = e1000_read_emi_reg_locked(hw, lpa, 941 &dev_spec->eee_lp_ability); 942 if (ret_val) 943 goto release; 944 945 /* Read EEE advertisement */ 946 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 947 if (ret_val) 948 goto release; 949 950 /* Enable EEE only for speeds in which the link partner is 951 * EEE capable and for which we advertise EEE. 952 */ 953 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 954 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 955 956 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 957 e1e_rphy_locked(hw, MII_LPA, &data); 958 if (data & LPA_100FULL) 959 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 960 else 961 /* EEE is not supported in 100Half, so ignore 962 * partner's EEE in 100 ability if full-duplex 963 * is not advertised. 964 */ 965 dev_spec->eee_lp_ability &= 966 ~I82579_EEE_100_SUPPORTED; 967 } 968 } 969 970 if (hw->phy.type == e1000_phy_82579) { 971 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 972 &data); 973 if (ret_val) 974 goto release; 975 976 data &= ~I82579_LPI_100_PLL_SHUT; 977 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 978 data); 979 } 980 981 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 982 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 983 if (ret_val) 984 goto release; 985 986 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 987release: 988 hw->phy.ops.release(hw); 989 990 return ret_val; 991} 992 993/** 994 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 995 * @hw: pointer to the HW structure 996 * @link: link up bool flag 997 * 998 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 999 * preventing further DMA write requests. Workaround the issue by disabling 1000 * the de-assertion of the clock request when in 1Gpbs mode. 1001 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 1002 * speeds in order to avoid Tx hangs. 1003 **/ 1004static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 1005{ 1006 u32 fextnvm6 = er32(FEXTNVM6); 1007 u32 status = er32(STATUS); 1008 s32 ret_val = 0; 1009 u16 reg; 1010 1011 if (link && (status & E1000_STATUS_SPEED_1000)) { 1012 ret_val = hw->phy.ops.acquire(hw); 1013 if (ret_val) 1014 return ret_val; 1015 1016 ret_val = 1017 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1018 ®); 1019 if (ret_val) 1020 goto release; 1021 1022 ret_val = 1023 e1000e_write_kmrn_reg_locked(hw, 1024 E1000_KMRNCTRLSTA_K1_CONFIG, 1025 reg & 1026 ~E1000_KMRNCTRLSTA_K1_ENABLE); 1027 if (ret_val) 1028 goto release; 1029 1030 usleep_range(10, 20); 1031 1032 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 1033 1034 ret_val = 1035 e1000e_write_kmrn_reg_locked(hw, 1036 E1000_KMRNCTRLSTA_K1_CONFIG, 1037 reg); 1038release: 1039 hw->phy.ops.release(hw); 1040 } else { 1041 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 1042 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 1043 1044 if ((hw->phy.revision > 5) || !link || 1045 ((status & E1000_STATUS_SPEED_100) && 1046 (status & E1000_STATUS_FD))) 1047 goto update_fextnvm6; 1048 1049 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 1050 if (ret_val) 1051 return ret_val; 1052 1053 /* Clear link status transmit timeout */ 1054 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 1055 1056 if (status & E1000_STATUS_SPEED_100) { 1057 /* Set inband Tx timeout to 5x10us for 100Half */ 1058 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1059 1060 /* Do not extend the K1 entry latency for 100Half */ 1061 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1062 } else { 1063 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 1064 reg |= 50 << 1065 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1066 1067 /* Extend the K1 entry latency for 10 Mbps */ 1068 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1069 } 1070 1071 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 1072 if (ret_val) 1073 return ret_val; 1074 1075update_fextnvm6: 1076 ew32(FEXTNVM6, fextnvm6); 1077 } 1078 1079 return ret_val; 1080} 1081 1082/** 1083 * e1000_platform_pm_pch_lpt - Set platform power management values 1084 * @hw: pointer to the HW structure 1085 * @link: bool indicating link status 1086 * 1087 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1088 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1089 * when link is up (which must not exceed the maximum latency supported 1090 * by the platform), otherwise specify there is no LTR requirement. 1091 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1092 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1093 * Capability register set, on this device LTR is set by writing the 1094 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1095 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1096 * message to the PMC. 1097 **/ 1098static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1099{ 1100 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1101 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1102 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */ 1103 u32 lat_enc_d = 0; /* latency decoded */ 1104 u16 lat_enc = 0; /* latency encoded */ 1105 1106 if (link) { 1107 u16 speed, duplex, scale = 0; 1108 u16 max_snoop, max_nosnoop; 1109 u16 max_ltr_enc; /* max LTR latency encoded */ 1110 u64 value; 1111 u32 rxa; 1112 1113 if (!hw->adapter->max_frame_size) { 1114 e_dbg("max_frame_size not set.\n"); 1115 return -E1000_ERR_CONFIG; 1116 } 1117 1118 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1119 if (!speed) { 1120 e_dbg("Speed not set.\n"); 1121 return -E1000_ERR_CONFIG; 1122 } 1123 1124 /* Rx Packet Buffer Allocation size (KB) */ 1125 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1126 1127 /* Determine the maximum latency tolerated by the device. 1128 * 1129 * Per the PCIe spec, the tolerated latencies are encoded as 1130 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1131 * a 10-bit value (0-1023) to provide a range from 1 ns to 1132 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1133 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1134 */ 1135 rxa *= 512; 1136 value = (rxa > hw->adapter->max_frame_size) ? 1137 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1138 0; 1139 1140 while (value > PCI_LTR_VALUE_MASK) { 1141 scale++; 1142 value = DIV_ROUND_UP(value, BIT(5)); 1143 } 1144 if (scale > E1000_LTRV_SCALE_MAX) { 1145 e_dbg("Invalid LTR latency scale %d\n", scale); 1146 return -E1000_ERR_CONFIG; 1147 } 1148 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1149 1150 /* Determine the maximum latency tolerated by the platform */ 1151 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1152 &max_snoop); 1153 pci_read_config_word(hw->adapter->pdev, 1154 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1155 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1156 1157 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) * 1158 (1U << (E1000_LTRV_SCALE_FACTOR * 1159 FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc))); 1160 1161 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) * 1162 (1U << (E1000_LTRV_SCALE_FACTOR * 1163 FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc))); 1164 1165 if (lat_enc_d > max_ltr_enc_d) 1166 lat_enc = max_ltr_enc; 1167 } 1168 1169 /* Set Snoop and No-Snoop latencies the same */ 1170 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1171 ew32(LTRV, reg); 1172 1173 return 0; 1174} 1175 1176/** 1177 * e1000e_force_smbus - Force interfaces to transition to SMBUS mode. 1178 * @hw: pointer to the HW structure 1179 * 1180 * Force the MAC and the PHY to SMBUS mode. Assumes semaphore already 1181 * acquired. 1182 * 1183 * Return: 0 on success, negative errno on failure. 1184 **/ 1185static s32 e1000e_force_smbus(struct e1000_hw *hw) 1186{ 1187 u16 smb_ctrl = 0; 1188 u32 ctrl_ext; 1189 s32 ret_val; 1190 1191 /* Switching PHY interface always returns MDI error 1192 * so disable retry mechanism to avoid wasting time 1193 */ 1194 e1000e_disable_phy_retry(hw); 1195 1196 /* Force SMBus mode in the PHY */ 1197 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &smb_ctrl); 1198 if (ret_val) { 1199 e1000e_enable_phy_retry(hw); 1200 return ret_val; 1201 } 1202 1203 smb_ctrl |= CV_SMB_CTRL_FORCE_SMBUS; 1204 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, smb_ctrl); 1205 1206 e1000e_enable_phy_retry(hw); 1207 1208 /* Force SMBus mode in the MAC */ 1209 ctrl_ext = er32(CTRL_EXT); 1210 ctrl_ext |= E1000_CTRL_EXT_FORCE_SMBUS; 1211 ew32(CTRL_EXT, ctrl_ext); 1212 1213 return 0; 1214} 1215 1216/** 1217 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1218 * @hw: pointer to the HW structure 1219 * @to_sx: boolean indicating a system power state transition to Sx 1220 * 1221 * When link is down, configure ULP mode to significantly reduce the power 1222 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1223 * ME firmware to start the ULP configuration. If not on an ME enabled 1224 * system, configure the ULP mode by software. 1225 */ 1226s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1227{ 1228 u32 mac_reg; 1229 s32 ret_val = 0; 1230 u16 phy_reg; 1231 u16 oem_reg = 0; 1232 1233 if ((hw->mac.type < e1000_pch_lpt) || 1234 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1235 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1236 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1237 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1238 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1239 return 0; 1240 1241 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1242 /* Request ME configure ULP mode in the PHY */ 1243 mac_reg = er32(H2ME); 1244 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1245 ew32(H2ME, mac_reg); 1246 1247 goto out; 1248 } 1249 1250 if (!to_sx) { 1251 int i = 0; 1252 1253 /* Poll up to 5 seconds for Cable Disconnected indication */ 1254 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1255 /* Bail if link is re-acquired */ 1256 if (er32(STATUS) & E1000_STATUS_LU) 1257 return -E1000_ERR_PHY; 1258 1259 if (i++ == 100) 1260 break; 1261 1262 msleep(50); 1263 } 1264 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1265 (er32(FEXT) & 1266 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1267 } 1268 1269 ret_val = hw->phy.ops.acquire(hw); 1270 if (ret_val) 1271 goto out; 1272 1273 ret_val = e1000e_force_smbus(hw); 1274 if (ret_val) { 1275 e_dbg("Failed to force SMBUS: %d\n", ret_val); 1276 goto release; 1277 } 1278 1279 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1280 * LPLU and disable Gig speed when entering ULP 1281 */ 1282 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1283 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1284 &oem_reg); 1285 if (ret_val) 1286 goto release; 1287 1288 phy_reg = oem_reg; 1289 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1290 1291 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1292 phy_reg); 1293 1294 if (ret_val) 1295 goto release; 1296 } 1297 1298 /* Set Inband ULP Exit, Reset to SMBus mode and 1299 * Disable SMBus Release on PERST# in PHY 1300 */ 1301 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1302 if (ret_val) 1303 goto release; 1304 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1305 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1306 if (to_sx) { 1307 if (er32(WUFC) & E1000_WUFC_LNKC) 1308 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1309 else 1310 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1311 1312 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1313 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1314 } else { 1315 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1316 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1317 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1318 } 1319 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1320 1321 /* Set Disable SMBus Release on PERST# in MAC */ 1322 mac_reg = er32(FEXTNVM7); 1323 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1324 ew32(FEXTNVM7, mac_reg); 1325 1326 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1327 phy_reg |= I218_ULP_CONFIG1_START; 1328 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1329 1330 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1331 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1332 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1333 oem_reg); 1334 if (ret_val) 1335 goto release; 1336 } 1337 1338release: 1339 hw->phy.ops.release(hw); 1340out: 1341 if (ret_val) 1342 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1343 else 1344 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1345 1346 return ret_val; 1347} 1348 1349/** 1350 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1351 * @hw: pointer to the HW structure 1352 * @force: boolean indicating whether or not to force disabling ULP 1353 * 1354 * Un-configure ULP mode when link is up, the system is transitioned from 1355 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1356 * system, poll for an indication from ME that ULP has been un-configured. 1357 * If not on an ME enabled system, un-configure the ULP mode by software. 1358 * 1359 * During nominal operation, this function is called when link is acquired 1360 * to disable ULP mode (force=false); otherwise, for example when unloading 1361 * the driver or during Sx->S0 transitions, this is called with force=true 1362 * to forcibly disable ULP. 1363 */ 1364static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1365{ 1366 s32 ret_val = 0; 1367 u32 mac_reg; 1368 u16 phy_reg; 1369 int i = 0; 1370 1371 if ((hw->mac.type < e1000_pch_lpt) || 1372 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1373 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1374 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1375 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1376 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1377 return 0; 1378 1379 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1380 struct e1000_adapter *adapter = hw->adapter; 1381 bool firmware_bug = false; 1382 1383 if (force) { 1384 /* Request ME un-configure ULP mode in the PHY */ 1385 mac_reg = er32(H2ME); 1386 mac_reg &= ~E1000_H2ME_ULP; 1387 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1388 ew32(H2ME, mac_reg); 1389 } 1390 1391 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE. 1392 * If this takes more than 1 second, show a warning indicating a 1393 * firmware bug 1394 */ 1395 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1396 if (i++ == 250) { 1397 ret_val = -E1000_ERR_PHY; 1398 goto out; 1399 } 1400 if (i > 100 && !firmware_bug) 1401 firmware_bug = true; 1402 1403 usleep_range(10000, 11000); 1404 } 1405 if (firmware_bug) 1406 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n", 1407 i * 10); 1408 else 1409 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n", 1410 i * 10); 1411 1412 if (force) { 1413 mac_reg = er32(H2ME); 1414 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1415 ew32(H2ME, mac_reg); 1416 } else { 1417 /* Clear H2ME.ULP after ME ULP configuration */ 1418 mac_reg = er32(H2ME); 1419 mac_reg &= ~E1000_H2ME_ULP; 1420 ew32(H2ME, mac_reg); 1421 } 1422 1423 goto out; 1424 } 1425 1426 ret_val = hw->phy.ops.acquire(hw); 1427 if (ret_val) 1428 goto out; 1429 1430 if (force) 1431 /* Toggle LANPHYPC Value bit */ 1432 e1000_toggle_lanphypc_pch_lpt(hw); 1433 1434 /* Switching PHY interface always returns MDI error 1435 * so disable retry mechanism to avoid wasting time 1436 */ 1437 e1000e_disable_phy_retry(hw); 1438 1439 /* Unforce SMBus mode in PHY */ 1440 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1441 if (ret_val) { 1442 /* The MAC might be in PCIe mode, so temporarily force to 1443 * SMBus mode in order to access the PHY. 1444 */ 1445 mac_reg = er32(CTRL_EXT); 1446 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1447 ew32(CTRL_EXT, mac_reg); 1448 1449 msleep(50); 1450 1451 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1452 &phy_reg); 1453 if (ret_val) 1454 goto release; 1455 } 1456 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1457 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1458 1459 e1000e_enable_phy_retry(hw); 1460 1461 /* Unforce SMBus mode in MAC */ 1462 mac_reg = er32(CTRL_EXT); 1463 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1464 ew32(CTRL_EXT, mac_reg); 1465 1466 /* When ULP mode was previously entered, K1 was disabled by the 1467 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1468 */ 1469 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1470 if (ret_val) 1471 goto release; 1472 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1473 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1474 1475 /* Clear ULP enabled configuration */ 1476 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1477 if (ret_val) 1478 goto release; 1479 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1480 I218_ULP_CONFIG1_STICKY_ULP | 1481 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1482 I218_ULP_CONFIG1_WOL_HOST | 1483 I218_ULP_CONFIG1_INBAND_EXIT | 1484 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1485 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1486 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1487 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1488 1489 /* Commit ULP changes by starting auto ULP configuration */ 1490 phy_reg |= I218_ULP_CONFIG1_START; 1491 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1492 1493 /* Clear Disable SMBus Release on PERST# in MAC */ 1494 mac_reg = er32(FEXTNVM7); 1495 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1496 ew32(FEXTNVM7, mac_reg); 1497 1498release: 1499 hw->phy.ops.release(hw); 1500 if (force) { 1501 e1000_phy_hw_reset(hw); 1502 msleep(50); 1503 } 1504out: 1505 if (ret_val) 1506 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1507 else 1508 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1509 1510 return ret_val; 1511} 1512 1513/** 1514 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1515 * @hw: pointer to the HW structure 1516 * 1517 * Checks to see of the link status of the hardware has changed. If a 1518 * change in link status has been detected, then we read the PHY registers 1519 * to get the current speed/duplex if link exists. 1520 **/ 1521static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1522{ 1523 struct e1000_mac_info *mac = &hw->mac; 1524 s32 ret_val, tipg_reg = 0; 1525 u16 emi_addr, emi_val = 0; 1526 bool link; 1527 u16 phy_reg; 1528 1529 /* We only want to go out to the PHY registers to see if Auto-Neg 1530 * has completed and/or if our link status has changed. The 1531 * get_link_status flag is set upon receiving a Link Status 1532 * Change or Rx Sequence Error interrupt. 1533 */ 1534 if (!mac->get_link_status) 1535 return 0; 1536 mac->get_link_status = false; 1537 1538 /* First we want to see if the MII Status Register reports 1539 * link. If so, then we want to get the current speed/duplex 1540 * of the PHY. 1541 */ 1542 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1543 if (ret_val) 1544 goto out; 1545 1546 if (hw->mac.type == e1000_pchlan) { 1547 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1548 if (ret_val) 1549 goto out; 1550 } 1551 1552 /* When connected at 10Mbps half-duplex, some parts are excessively 1553 * aggressive resulting in many collisions. To avoid this, increase 1554 * the IPG and reduce Rx latency in the PHY. 1555 */ 1556 if ((hw->mac.type >= e1000_pch2lan) && link) { 1557 u16 speed, duplex; 1558 1559 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1560 tipg_reg = er32(TIPG); 1561 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1562 1563 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1564 tipg_reg |= 0xFF; 1565 /* Reduce Rx latency in analog PHY */ 1566 emi_val = 0; 1567 } else if (hw->mac.type >= e1000_pch_spt && 1568 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1569 tipg_reg |= 0xC; 1570 emi_val = 1; 1571 } else { 1572 1573 /* Roll back the default values */ 1574 tipg_reg |= 0x08; 1575 emi_val = 1; 1576 } 1577 1578 ew32(TIPG, tipg_reg); 1579 1580 ret_val = hw->phy.ops.acquire(hw); 1581 if (ret_val) 1582 goto out; 1583 1584 if (hw->mac.type == e1000_pch2lan) 1585 emi_addr = I82579_RX_CONFIG; 1586 else 1587 emi_addr = I217_RX_CONFIG; 1588 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1589 1590 if (hw->mac.type >= e1000_pch_lpt) { 1591 u16 phy_reg; 1592 1593 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1594 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1595 if (speed == SPEED_100 || speed == SPEED_10) 1596 phy_reg |= 0x3E8; 1597 else 1598 phy_reg |= 0xFA; 1599 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1600 1601 if (speed == SPEED_1000) { 1602 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1603 &phy_reg); 1604 1605 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1606 1607 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1608 phy_reg); 1609 } 1610 } 1611 hw->phy.ops.release(hw); 1612 1613 if (ret_val) 1614 goto out; 1615 1616 if (hw->mac.type >= e1000_pch_spt) { 1617 u16 data; 1618 u16 ptr_gap; 1619 1620 if (speed == SPEED_1000) { 1621 ret_val = hw->phy.ops.acquire(hw); 1622 if (ret_val) 1623 goto out; 1624 1625 ret_val = e1e_rphy_locked(hw, 1626 PHY_REG(776, 20), 1627 &data); 1628 if (ret_val) { 1629 hw->phy.ops.release(hw); 1630 goto out; 1631 } 1632 1633 ptr_gap = (data & (0x3FF << 2)) >> 2; 1634 if (ptr_gap < 0x18) { 1635 data &= ~(0x3FF << 2); 1636 data |= (0x18 << 2); 1637 ret_val = 1638 e1e_wphy_locked(hw, 1639 PHY_REG(776, 20), 1640 data); 1641 } 1642 hw->phy.ops.release(hw); 1643 if (ret_val) 1644 goto out; 1645 } else { 1646 ret_val = hw->phy.ops.acquire(hw); 1647 if (ret_val) 1648 goto out; 1649 1650 ret_val = e1e_wphy_locked(hw, 1651 PHY_REG(776, 20), 1652 0xC023); 1653 hw->phy.ops.release(hw); 1654 if (ret_val) 1655 goto out; 1656 1657 } 1658 } 1659 } 1660 1661 /* I217 Packet Loss issue: 1662 * ensure that FEXTNVM4 Beacon Duration is set correctly 1663 * on power up. 1664 * Set the Beacon Duration for I217 to 8 usec 1665 */ 1666 if (hw->mac.type >= e1000_pch_lpt) { 1667 u32 mac_reg; 1668 1669 mac_reg = er32(FEXTNVM4); 1670 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1671 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1672 ew32(FEXTNVM4, mac_reg); 1673 } 1674 1675 /* Work-around I218 hang issue */ 1676 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1677 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1678 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1679 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1680 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1681 if (ret_val) 1682 goto out; 1683 } 1684 if (hw->mac.type >= e1000_pch_lpt) { 1685 /* Set platform power management values for 1686 * Latency Tolerance Reporting (LTR) 1687 */ 1688 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1689 if (ret_val) 1690 goto out; 1691 } 1692 1693 /* Clear link partner's EEE ability */ 1694 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1695 1696 if (hw->mac.type >= e1000_pch_lpt) { 1697 u32 fextnvm6 = er32(FEXTNVM6); 1698 1699 if (hw->mac.type == e1000_pch_spt) { 1700 /* FEXTNVM6 K1-off workaround - for SPT only */ 1701 u32 pcieanacfg = er32(PCIEANACFG); 1702 1703 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1704 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1705 else 1706 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1707 } 1708 1709 ew32(FEXTNVM6, fextnvm6); 1710 } 1711 1712 if (!link) 1713 goto out; 1714 1715 switch (hw->mac.type) { 1716 case e1000_pch2lan: 1717 ret_val = e1000_k1_workaround_lv(hw); 1718 if (ret_val) 1719 return ret_val; 1720 fallthrough; 1721 case e1000_pchlan: 1722 if (hw->phy.type == e1000_phy_82578) { 1723 ret_val = e1000_link_stall_workaround_hv(hw); 1724 if (ret_val) 1725 return ret_val; 1726 } 1727 1728 /* Workaround for PCHx parts in half-duplex: 1729 * Set the number of preambles removed from the packet 1730 * when it is passed from the PHY to the MAC to prevent 1731 * the MAC from misinterpreting the packet type. 1732 */ 1733 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1734 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1735 1736 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1737 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1738 1739 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1740 break; 1741 default: 1742 break; 1743 } 1744 1745 /* Check if there was DownShift, must be checked 1746 * immediately after link-up 1747 */ 1748 e1000e_check_downshift(hw); 1749 1750 /* Enable/Disable EEE after link up */ 1751 if (hw->phy.type > e1000_phy_82579) { 1752 ret_val = e1000_set_eee_pchlan(hw); 1753 if (ret_val) 1754 return ret_val; 1755 } 1756 1757 /* If we are forcing speed/duplex, then we simply return since 1758 * we have already determined whether we have link or not. 1759 */ 1760 if (!mac->autoneg) 1761 return -E1000_ERR_CONFIG; 1762 1763 /* Auto-Neg is enabled. Auto Speed Detection takes care 1764 * of MAC speed/duplex configuration. So we only need to 1765 * configure Collision Distance in the MAC. 1766 */ 1767 mac->ops.config_collision_dist(hw); 1768 1769 /* Configure Flow Control now that Auto-Neg has completed. 1770 * First, we need to restore the desired flow control 1771 * settings because we may have had to re-autoneg with a 1772 * different link partner. 1773 */ 1774 ret_val = e1000e_config_fc_after_link_up(hw); 1775 if (ret_val) 1776 e_dbg("Error configuring flow control\n"); 1777 1778 return ret_val; 1779 1780out: 1781 mac->get_link_status = true; 1782 return ret_val; 1783} 1784 1785static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1786{ 1787 struct e1000_hw *hw = &adapter->hw; 1788 s32 rc; 1789 1790 rc = e1000_init_mac_params_ich8lan(hw); 1791 if (rc) 1792 return rc; 1793 1794 rc = e1000_init_nvm_params_ich8lan(hw); 1795 if (rc) 1796 return rc; 1797 1798 switch (hw->mac.type) { 1799 case e1000_ich8lan: 1800 case e1000_ich9lan: 1801 case e1000_ich10lan: 1802 rc = e1000_init_phy_params_ich8lan(hw); 1803 break; 1804 case e1000_pchlan: 1805 case e1000_pch2lan: 1806 case e1000_pch_lpt: 1807 case e1000_pch_spt: 1808 case e1000_pch_cnp: 1809 case e1000_pch_tgp: 1810 case e1000_pch_adp: 1811 case e1000_pch_mtp: 1812 case e1000_pch_lnp: 1813 case e1000_pch_ptp: 1814 case e1000_pch_nvp: 1815 rc = e1000_init_phy_params_pchlan(hw); 1816 break; 1817 default: 1818 break; 1819 } 1820 if (rc) 1821 return rc; 1822 1823 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1824 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1825 */ 1826 if ((adapter->hw.phy.type == e1000_phy_ife) || 1827 ((adapter->hw.mac.type >= e1000_pch2lan) && 1828 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1829 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1830 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1831 1832 hw->mac.ops.blink_led = NULL; 1833 } 1834 1835 if ((adapter->hw.mac.type == e1000_ich8lan) && 1836 (adapter->hw.phy.type != e1000_phy_ife)) 1837 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1838 1839 /* Enable workaround for 82579 w/ ME enabled */ 1840 if ((adapter->hw.mac.type == e1000_pch2lan) && 1841 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1842 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1843 1844 return 0; 1845} 1846 1847static DEFINE_MUTEX(nvm_mutex); 1848 1849/** 1850 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1851 * @hw: pointer to the HW structure 1852 * 1853 * Acquires the mutex for performing NVM operations. 1854 **/ 1855static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1856{ 1857 mutex_lock(&nvm_mutex); 1858 1859 return 0; 1860} 1861 1862/** 1863 * e1000_release_nvm_ich8lan - Release NVM mutex 1864 * @hw: pointer to the HW structure 1865 * 1866 * Releases the mutex used while performing NVM operations. 1867 **/ 1868static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1869{ 1870 mutex_unlock(&nvm_mutex); 1871} 1872 1873/** 1874 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1875 * @hw: pointer to the HW structure 1876 * 1877 * Acquires the software control flag for performing PHY and select 1878 * MAC CSR accesses. 1879 **/ 1880static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1881{ 1882 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1883 s32 ret_val = 0; 1884 1885 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1886 &hw->adapter->state)) { 1887 e_dbg("contention for Phy access\n"); 1888 return -E1000_ERR_PHY; 1889 } 1890 1891 while (timeout) { 1892 extcnf_ctrl = er32(EXTCNF_CTRL); 1893 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1894 break; 1895 1896 mdelay(1); 1897 timeout--; 1898 } 1899 1900 if (!timeout) { 1901 e_dbg("SW has already locked the resource.\n"); 1902 ret_val = -E1000_ERR_CONFIG; 1903 goto out; 1904 } 1905 1906 timeout = SW_FLAG_TIMEOUT; 1907 1908 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1909 ew32(EXTCNF_CTRL, extcnf_ctrl); 1910 1911 while (timeout) { 1912 extcnf_ctrl = er32(EXTCNF_CTRL); 1913 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1914 break; 1915 1916 mdelay(1); 1917 timeout--; 1918 } 1919 1920 if (!timeout) { 1921 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1922 er32(FWSM), extcnf_ctrl); 1923 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1924 ew32(EXTCNF_CTRL, extcnf_ctrl); 1925 ret_val = -E1000_ERR_CONFIG; 1926 goto out; 1927 } 1928 1929out: 1930 if (ret_val) 1931 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1932 1933 return ret_val; 1934} 1935 1936/** 1937 * e1000_release_swflag_ich8lan - Release software control flag 1938 * @hw: pointer to the HW structure 1939 * 1940 * Releases the software control flag for performing PHY and select 1941 * MAC CSR accesses. 1942 **/ 1943static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1944{ 1945 u32 extcnf_ctrl; 1946 1947 extcnf_ctrl = er32(EXTCNF_CTRL); 1948 1949 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1950 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1951 ew32(EXTCNF_CTRL, extcnf_ctrl); 1952 } else { 1953 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1954 } 1955 1956 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1957} 1958 1959/** 1960 * e1000_check_mng_mode_ich8lan - Checks management mode 1961 * @hw: pointer to the HW structure 1962 * 1963 * This checks if the adapter has any manageability enabled. 1964 * This is a function pointer entry point only called by read/write 1965 * routines for the PHY and NVM parts. 1966 **/ 1967static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1968{ 1969 u32 fwsm; 1970 1971 fwsm = er32(FWSM); 1972 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1973 ((fwsm & E1000_FWSM_MODE_MASK) == 1974 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1975} 1976 1977/** 1978 * e1000_check_mng_mode_pchlan - Checks management mode 1979 * @hw: pointer to the HW structure 1980 * 1981 * This checks if the adapter has iAMT enabled. 1982 * This is a function pointer entry point only called by read/write 1983 * routines for the PHY and NVM parts. 1984 **/ 1985static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1986{ 1987 u32 fwsm; 1988 1989 fwsm = er32(FWSM); 1990 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1991 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1992} 1993 1994/** 1995 * e1000_rar_set_pch2lan - Set receive address register 1996 * @hw: pointer to the HW structure 1997 * @addr: pointer to the receive address 1998 * @index: receive address array register 1999 * 2000 * Sets the receive address array register at index to the address passed 2001 * in by addr. For 82579, RAR[0] is the base address register that is to 2002 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 2003 * Use SHRA[0-3] in place of those reserved for ME. 2004 **/ 2005static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 2006{ 2007 u32 rar_low, rar_high; 2008 2009 /* HW expects these in little endian so we reverse the byte order 2010 * from network order (big endian) to little endian 2011 */ 2012 rar_low = ((u32)addr[0] | 2013 ((u32)addr[1] << 8) | 2014 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 2015 2016 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 2017 2018 /* If MAC address zero, no need to set the AV bit */ 2019 if (rar_low || rar_high) 2020 rar_high |= E1000_RAH_AV; 2021 2022 if (index == 0) { 2023 ew32(RAL(index), rar_low); 2024 e1e_flush(); 2025 ew32(RAH(index), rar_high); 2026 e1e_flush(); 2027 return 0; 2028 } 2029 2030 /* RAR[1-6] are owned by manageability. Skip those and program the 2031 * next address into the SHRA register array. 2032 */ 2033 if (index < (u32)(hw->mac.rar_entry_count)) { 2034 s32 ret_val; 2035 2036 ret_val = e1000_acquire_swflag_ich8lan(hw); 2037 if (ret_val) 2038 goto out; 2039 2040 ew32(SHRAL(index - 1), rar_low); 2041 e1e_flush(); 2042 ew32(SHRAH(index - 1), rar_high); 2043 e1e_flush(); 2044 2045 e1000_release_swflag_ich8lan(hw); 2046 2047 /* verify the register updates */ 2048 if ((er32(SHRAL(index - 1)) == rar_low) && 2049 (er32(SHRAH(index - 1)) == rar_high)) 2050 return 0; 2051 2052 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 2053 (index - 1), er32(FWSM)); 2054 } 2055 2056out: 2057 e_dbg("Failed to write receive address at index %d\n", index); 2058 return -E1000_ERR_CONFIG; 2059} 2060 2061/** 2062 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 2063 * @hw: pointer to the HW structure 2064 * 2065 * Get the number of available receive registers that the Host can 2066 * program. SHRA[0-10] are the shared receive address registers 2067 * that are shared between the Host and manageability engine (ME). 2068 * ME can reserve any number of addresses and the host needs to be 2069 * able to tell how many available registers it has access to. 2070 **/ 2071static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 2072{ 2073 u32 wlock_mac; 2074 u32 num_entries; 2075 2076 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2077 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2078 2079 switch (wlock_mac) { 2080 case 0: 2081 /* All SHRA[0..10] and RAR[0] available */ 2082 num_entries = hw->mac.rar_entry_count; 2083 break; 2084 case 1: 2085 /* Only RAR[0] available */ 2086 num_entries = 1; 2087 break; 2088 default: 2089 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 2090 num_entries = wlock_mac + 1; 2091 break; 2092 } 2093 2094 return num_entries; 2095} 2096 2097/** 2098 * e1000_rar_set_pch_lpt - Set receive address registers 2099 * @hw: pointer to the HW structure 2100 * @addr: pointer to the receive address 2101 * @index: receive address array register 2102 * 2103 * Sets the receive address register array at index to the address passed 2104 * in by addr. For LPT, RAR[0] is the base address register that is to 2105 * contain the MAC address. SHRA[0-10] are the shared receive address 2106 * registers that are shared between the Host and manageability engine (ME). 2107 **/ 2108static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 2109{ 2110 u32 rar_low, rar_high; 2111 u32 wlock_mac; 2112 2113 /* HW expects these in little endian so we reverse the byte order 2114 * from network order (big endian) to little endian 2115 */ 2116 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 2117 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 2118 2119 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 2120 2121 /* If MAC address zero, no need to set the AV bit */ 2122 if (rar_low || rar_high) 2123 rar_high |= E1000_RAH_AV; 2124 2125 if (index == 0) { 2126 ew32(RAL(index), rar_low); 2127 e1e_flush(); 2128 ew32(RAH(index), rar_high); 2129 e1e_flush(); 2130 return 0; 2131 } 2132 2133 /* The manageability engine (ME) can lock certain SHRAR registers that 2134 * it is using - those registers are unavailable for use. 2135 */ 2136 if (index < hw->mac.rar_entry_count) { 2137 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2138 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2139 2140 /* Check if all SHRAR registers are locked */ 2141 if (wlock_mac == 1) 2142 goto out; 2143 2144 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2145 s32 ret_val; 2146 2147 ret_val = e1000_acquire_swflag_ich8lan(hw); 2148 2149 if (ret_val) 2150 goto out; 2151 2152 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 2153 e1e_flush(); 2154 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 2155 e1e_flush(); 2156 2157 e1000_release_swflag_ich8lan(hw); 2158 2159 /* verify the register updates */ 2160 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 2161 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 2162 return 0; 2163 } 2164 } 2165 2166out: 2167 e_dbg("Failed to write receive address at index %d\n", index); 2168 return -E1000_ERR_CONFIG; 2169} 2170 2171/** 2172 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2173 * @hw: pointer to the HW structure 2174 * 2175 * Checks if firmware is blocking the reset of the PHY. 2176 * This is a function pointer entry point only called by 2177 * reset routines. 2178 **/ 2179static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2180{ 2181 bool blocked = false; 2182 int i = 0; 2183 2184 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2185 (i++ < 30)) 2186 usleep_range(10000, 11000); 2187 return blocked ? E1000_BLK_PHY_RESET : 0; 2188} 2189 2190/** 2191 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2192 * @hw: pointer to the HW structure 2193 * 2194 * Assumes semaphore already acquired. 2195 * 2196 **/ 2197static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2198{ 2199 u16 phy_data; 2200 u32 strap = er32(STRAP); 2201 u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap); 2202 s32 ret_val; 2203 2204 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2205 2206 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2207 if (ret_val) 2208 return ret_val; 2209 2210 phy_data &= ~HV_SMB_ADDR_MASK; 2211 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2212 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2213 2214 if (hw->phy.type == e1000_phy_i217) { 2215 /* Restore SMBus frequency */ 2216 if (freq--) { 2217 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2218 phy_data |= (freq & BIT(0)) << 2219 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2220 phy_data |= (freq & BIT(1)) << 2221 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2222 } else { 2223 e_dbg("Unsupported SMB frequency in PHY\n"); 2224 } 2225 } 2226 2227 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2228} 2229 2230/** 2231 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2232 * @hw: pointer to the HW structure 2233 * 2234 * SW should configure the LCD from the NVM extended configuration region 2235 * as a workaround for certain parts. 2236 **/ 2237static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2238{ 2239 struct e1000_phy_info *phy = &hw->phy; 2240 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2241 s32 ret_val = 0; 2242 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2243 2244 /* Initialize the PHY from the NVM on ICH platforms. This 2245 * is needed due to an issue where the NVM configuration is 2246 * not properly autoloaded after power transitions. 2247 * Therefore, after each PHY reset, we will load the 2248 * configuration data out of the NVM manually. 2249 */ 2250 switch (hw->mac.type) { 2251 case e1000_ich8lan: 2252 if (phy->type != e1000_phy_igp_3) 2253 return ret_val; 2254 2255 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2256 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2257 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2258 break; 2259 } 2260 fallthrough; 2261 case e1000_pchlan: 2262 case e1000_pch2lan: 2263 case e1000_pch_lpt: 2264 case e1000_pch_spt: 2265 case e1000_pch_cnp: 2266 case e1000_pch_tgp: 2267 case e1000_pch_adp: 2268 case e1000_pch_mtp: 2269 case e1000_pch_lnp: 2270 case e1000_pch_ptp: 2271 case e1000_pch_nvp: 2272 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2273 break; 2274 default: 2275 return ret_val; 2276 } 2277 2278 ret_val = hw->phy.ops.acquire(hw); 2279 if (ret_val) 2280 return ret_val; 2281 2282 data = er32(FEXTNVM); 2283 if (!(data & sw_cfg_mask)) 2284 goto release; 2285 2286 /* Make sure HW does not configure LCD from PHY 2287 * extended configuration before SW configuration 2288 */ 2289 data = er32(EXTCNF_CTRL); 2290 if ((hw->mac.type < e1000_pch2lan) && 2291 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2292 goto release; 2293 2294 cnf_size = er32(EXTCNF_SIZE); 2295 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2296 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2297 if (!cnf_size) 2298 goto release; 2299 2300 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2301 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2302 2303 if (((hw->mac.type == e1000_pchlan) && 2304 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2305 (hw->mac.type > e1000_pchlan)) { 2306 /* HW configures the SMBus address and LEDs when the 2307 * OEM and LCD Write Enable bits are set in the NVM. 2308 * When both NVM bits are cleared, SW will configure 2309 * them instead. 2310 */ 2311 ret_val = e1000_write_smbus_addr(hw); 2312 if (ret_val) 2313 goto release; 2314 2315 data = er32(LEDCTL); 2316 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2317 (u16)data); 2318 if (ret_val) 2319 goto release; 2320 } 2321 2322 /* Configure LCD from extended configuration region. */ 2323 2324 /* cnf_base_addr is in DWORD */ 2325 word_addr = (u16)(cnf_base_addr << 1); 2326 2327 for (i = 0; i < cnf_size; i++) { 2328 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2329 if (ret_val) 2330 goto release; 2331 2332 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2333 1, ®_addr); 2334 if (ret_val) 2335 goto release; 2336 2337 /* Save off the PHY page for future writes. */ 2338 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2339 phy_page = reg_data; 2340 continue; 2341 } 2342 2343 reg_addr &= PHY_REG_MASK; 2344 reg_addr |= phy_page; 2345 2346 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2347 if (ret_val) 2348 goto release; 2349 } 2350 2351release: 2352 hw->phy.ops.release(hw); 2353 return ret_val; 2354} 2355 2356/** 2357 * e1000_k1_gig_workaround_hv - K1 Si workaround 2358 * @hw: pointer to the HW structure 2359 * @link: link up bool flag 2360 * 2361 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2362 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2363 * If link is down, the function will restore the default K1 setting located 2364 * in the NVM. 2365 **/ 2366static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2367{ 2368 s32 ret_val = 0; 2369 u16 status_reg = 0; 2370 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2371 2372 if (hw->mac.type != e1000_pchlan) 2373 return 0; 2374 2375 /* Wrap the whole flow with the sw flag */ 2376 ret_val = hw->phy.ops.acquire(hw); 2377 if (ret_val) 2378 return ret_val; 2379 2380 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2381 if (link) { 2382 if (hw->phy.type == e1000_phy_82578) { 2383 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2384 &status_reg); 2385 if (ret_val) 2386 goto release; 2387 2388 status_reg &= (BM_CS_STATUS_LINK_UP | 2389 BM_CS_STATUS_RESOLVED | 2390 BM_CS_STATUS_SPEED_MASK); 2391 2392 if (status_reg == (BM_CS_STATUS_LINK_UP | 2393 BM_CS_STATUS_RESOLVED | 2394 BM_CS_STATUS_SPEED_1000)) 2395 k1_enable = false; 2396 } 2397 2398 if (hw->phy.type == e1000_phy_82577) { 2399 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2400 if (ret_val) 2401 goto release; 2402 2403 status_reg &= (HV_M_STATUS_LINK_UP | 2404 HV_M_STATUS_AUTONEG_COMPLETE | 2405 HV_M_STATUS_SPEED_MASK); 2406 2407 if (status_reg == (HV_M_STATUS_LINK_UP | 2408 HV_M_STATUS_AUTONEG_COMPLETE | 2409 HV_M_STATUS_SPEED_1000)) 2410 k1_enable = false; 2411 } 2412 2413 /* Link stall fix for link up */ 2414 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2415 if (ret_val) 2416 goto release; 2417 2418 } else { 2419 /* Link stall fix for link down */ 2420 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2421 if (ret_val) 2422 goto release; 2423 } 2424 2425 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2426 2427release: 2428 hw->phy.ops.release(hw); 2429 2430 return ret_val; 2431} 2432 2433/** 2434 * e1000_configure_k1_ich8lan - Configure K1 power state 2435 * @hw: pointer to the HW structure 2436 * @k1_enable: K1 state to configure 2437 * 2438 * Configure the K1 power state based on the provided parameter. 2439 * Assumes semaphore already acquired. 2440 * 2441 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2442 **/ 2443s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2444{ 2445 s32 ret_val; 2446 u32 ctrl_reg = 0; 2447 u32 ctrl_ext = 0; 2448 u32 reg = 0; 2449 u16 kmrn_reg = 0; 2450 2451 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2452 &kmrn_reg); 2453 if (ret_val) 2454 return ret_val; 2455 2456 if (k1_enable) 2457 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2458 else 2459 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2460 2461 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2462 kmrn_reg); 2463 if (ret_val) 2464 return ret_val; 2465 2466 usleep_range(20, 40); 2467 ctrl_ext = er32(CTRL_EXT); 2468 ctrl_reg = er32(CTRL); 2469 2470 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2471 reg |= E1000_CTRL_FRCSPD; 2472 ew32(CTRL, reg); 2473 2474 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2475 e1e_flush(); 2476 usleep_range(20, 40); 2477 ew32(CTRL, ctrl_reg); 2478 ew32(CTRL_EXT, ctrl_ext); 2479 e1e_flush(); 2480 usleep_range(20, 40); 2481 2482 return 0; 2483} 2484 2485/** 2486 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2487 * @hw: pointer to the HW structure 2488 * @d0_state: boolean if entering d0 or d3 device state 2489 * 2490 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2491 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2492 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2493 **/ 2494static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2495{ 2496 s32 ret_val = 0; 2497 u32 mac_reg; 2498 u16 oem_reg; 2499 2500 if (hw->mac.type < e1000_pchlan) 2501 return ret_val; 2502 2503 ret_val = hw->phy.ops.acquire(hw); 2504 if (ret_val) 2505 return ret_val; 2506 2507 if (hw->mac.type == e1000_pchlan) { 2508 mac_reg = er32(EXTCNF_CTRL); 2509 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2510 goto release; 2511 } 2512 2513 mac_reg = er32(FEXTNVM); 2514 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2515 goto release; 2516 2517 mac_reg = er32(PHY_CTRL); 2518 2519 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2520 if (ret_val) 2521 goto release; 2522 2523 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2524 2525 if (d0_state) { 2526 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2527 oem_reg |= HV_OEM_BITS_GBE_DIS; 2528 2529 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2530 oem_reg |= HV_OEM_BITS_LPLU; 2531 } else { 2532 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2533 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2534 oem_reg |= HV_OEM_BITS_GBE_DIS; 2535 2536 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2537 E1000_PHY_CTRL_NOND0A_LPLU)) 2538 oem_reg |= HV_OEM_BITS_LPLU; 2539 } 2540 2541 /* Set Restart auto-neg to activate the bits */ 2542 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2543 !hw->phy.ops.check_reset_block(hw)) 2544 oem_reg |= HV_OEM_BITS_RESTART_AN; 2545 2546 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2547 2548release: 2549 hw->phy.ops.release(hw); 2550 2551 return ret_val; 2552} 2553 2554/** 2555 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2556 * @hw: pointer to the HW structure 2557 **/ 2558static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2559{ 2560 s32 ret_val; 2561 u16 data; 2562 2563 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2564 if (ret_val) 2565 return ret_val; 2566 2567 data |= HV_KMRN_MDIO_SLOW; 2568 2569 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2570 2571 return ret_val; 2572} 2573 2574/** 2575 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds 2576 * @hw: pointer to the HW structure 2577 * 2578 * A series of PHY workarounds to be done after every PHY reset. 2579 **/ 2580static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2581{ 2582 s32 ret_val = 0; 2583 u16 phy_data; 2584 2585 if (hw->mac.type != e1000_pchlan) 2586 return 0; 2587 2588 /* Set MDIO slow mode before any other MDIO access */ 2589 if (hw->phy.type == e1000_phy_82577) { 2590 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2591 if (ret_val) 2592 return ret_val; 2593 } 2594 2595 if (((hw->phy.type == e1000_phy_82577) && 2596 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2597 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2598 /* Disable generation of early preamble */ 2599 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2600 if (ret_val) 2601 return ret_val; 2602 2603 /* Preamble tuning for SSC */ 2604 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2605 if (ret_val) 2606 return ret_val; 2607 } 2608 2609 if (hw->phy.type == e1000_phy_82578) { 2610 /* Return registers to default by doing a soft reset then 2611 * writing 0x3140 to the control register. 2612 */ 2613 if (hw->phy.revision < 2) { 2614 e1000e_phy_sw_reset(hw); 2615 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2616 if (ret_val) 2617 return ret_val; 2618 } 2619 } 2620 2621 /* Select page 0 */ 2622 ret_val = hw->phy.ops.acquire(hw); 2623 if (ret_val) 2624 return ret_val; 2625 2626 hw->phy.addr = 1; 2627 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2628 hw->phy.ops.release(hw); 2629 if (ret_val) 2630 return ret_val; 2631 2632 /* Configure the K1 Si workaround during phy reset assuming there is 2633 * link so that it disables K1 if link is in 1Gbps. 2634 */ 2635 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2636 if (ret_val) 2637 return ret_val; 2638 2639 /* Workaround for link disconnects on a busy hub in half duplex */ 2640 ret_val = hw->phy.ops.acquire(hw); 2641 if (ret_val) 2642 return ret_val; 2643 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2644 if (ret_val) 2645 goto release; 2646 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2647 if (ret_val) 2648 goto release; 2649 2650 /* set MSE higher to enable link to stay up when noise is high */ 2651 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2652release: 2653 hw->phy.ops.release(hw); 2654 2655 return ret_val; 2656} 2657 2658/** 2659 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2660 * @hw: pointer to the HW structure 2661 **/ 2662void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2663{ 2664 u32 mac_reg; 2665 u16 i, phy_reg = 0; 2666 s32 ret_val; 2667 2668 ret_val = hw->phy.ops.acquire(hw); 2669 if (ret_val) 2670 return; 2671 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2672 if (ret_val) 2673 goto release; 2674 2675 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2676 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2677 mac_reg = er32(RAL(i)); 2678 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2679 (u16)(mac_reg & 0xFFFF)); 2680 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2681 (u16)((mac_reg >> 16) & 0xFFFF)); 2682 2683 mac_reg = er32(RAH(i)); 2684 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2685 (u16)(mac_reg & 0xFFFF)); 2686 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2687 (u16)((mac_reg & E1000_RAH_AV) >> 16)); 2688 } 2689 2690 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2691 2692release: 2693 hw->phy.ops.release(hw); 2694} 2695 2696/** 2697 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2698 * with 82579 PHY 2699 * @hw: pointer to the HW structure 2700 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2701 **/ 2702s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2703{ 2704 s32 ret_val = 0; 2705 u16 phy_reg, data; 2706 u32 mac_reg; 2707 u16 i; 2708 2709 if (hw->mac.type < e1000_pch2lan) 2710 return 0; 2711 2712 /* disable Rx path while enabling/disabling workaround */ 2713 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2714 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2715 if (ret_val) 2716 return ret_val; 2717 2718 if (enable) { 2719 /* Write Rx addresses (rar_entry_count for RAL/H, and 2720 * SHRAL/H) and initial CRC values to the MAC 2721 */ 2722 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2723 u8 mac_addr[ETH_ALEN] = { 0 }; 2724 u32 addr_high, addr_low; 2725 2726 addr_high = er32(RAH(i)); 2727 if (!(addr_high & E1000_RAH_AV)) 2728 continue; 2729 addr_low = er32(RAL(i)); 2730 mac_addr[0] = (addr_low & 0xFF); 2731 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2732 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2733 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2734 mac_addr[4] = (addr_high & 0xFF); 2735 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2736 2737 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2738 } 2739 2740 /* Write Rx addresses to the PHY */ 2741 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2742 2743 /* Enable jumbo frame workaround in the MAC */ 2744 mac_reg = er32(FFLT_DBG); 2745 mac_reg &= ~BIT(14); 2746 mac_reg |= (7 << 15); 2747 ew32(FFLT_DBG, mac_reg); 2748 2749 mac_reg = er32(RCTL); 2750 mac_reg |= E1000_RCTL_SECRC; 2751 ew32(RCTL, mac_reg); 2752 2753 ret_val = e1000e_read_kmrn_reg(hw, 2754 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2755 &data); 2756 if (ret_val) 2757 return ret_val; 2758 ret_val = e1000e_write_kmrn_reg(hw, 2759 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2760 data | BIT(0)); 2761 if (ret_val) 2762 return ret_val; 2763 ret_val = e1000e_read_kmrn_reg(hw, 2764 E1000_KMRNCTRLSTA_HD_CTRL, 2765 &data); 2766 if (ret_val) 2767 return ret_val; 2768 data &= ~(0xF << 8); 2769 data |= (0xB << 8); 2770 ret_val = e1000e_write_kmrn_reg(hw, 2771 E1000_KMRNCTRLSTA_HD_CTRL, 2772 data); 2773 if (ret_val) 2774 return ret_val; 2775 2776 /* Enable jumbo frame workaround in the PHY */ 2777 e1e_rphy(hw, PHY_REG(769, 23), &data); 2778 data &= ~(0x7F << 5); 2779 data |= (0x37 << 5); 2780 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2781 if (ret_val) 2782 return ret_val; 2783 e1e_rphy(hw, PHY_REG(769, 16), &data); 2784 data &= ~BIT(13); 2785 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2786 if (ret_val) 2787 return ret_val; 2788 e1e_rphy(hw, PHY_REG(776, 20), &data); 2789 data &= ~(0x3FF << 2); 2790 data |= (E1000_TX_PTR_GAP << 2); 2791 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2792 if (ret_val) 2793 return ret_val; 2794 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2795 if (ret_val) 2796 return ret_val; 2797 e1e_rphy(hw, HV_PM_CTRL, &data); 2798 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2799 if (ret_val) 2800 return ret_val; 2801 } else { 2802 /* Write MAC register values back to h/w defaults */ 2803 mac_reg = er32(FFLT_DBG); 2804 mac_reg &= ~(0xF << 14); 2805 ew32(FFLT_DBG, mac_reg); 2806 2807 mac_reg = er32(RCTL); 2808 mac_reg &= ~E1000_RCTL_SECRC; 2809 ew32(RCTL, mac_reg); 2810 2811 ret_val = e1000e_read_kmrn_reg(hw, 2812 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2813 &data); 2814 if (ret_val) 2815 return ret_val; 2816 ret_val = e1000e_write_kmrn_reg(hw, 2817 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2818 data & ~BIT(0)); 2819 if (ret_val) 2820 return ret_val; 2821 ret_val = e1000e_read_kmrn_reg(hw, 2822 E1000_KMRNCTRLSTA_HD_CTRL, 2823 &data); 2824 if (ret_val) 2825 return ret_val; 2826 data &= ~(0xF << 8); 2827 data |= (0xB << 8); 2828 ret_val = e1000e_write_kmrn_reg(hw, 2829 E1000_KMRNCTRLSTA_HD_CTRL, 2830 data); 2831 if (ret_val) 2832 return ret_val; 2833 2834 /* Write PHY register values back to h/w defaults */ 2835 e1e_rphy(hw, PHY_REG(769, 23), &data); 2836 data &= ~(0x7F << 5); 2837 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2838 if (ret_val) 2839 return ret_val; 2840 e1e_rphy(hw, PHY_REG(769, 16), &data); 2841 data |= BIT(13); 2842 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2843 if (ret_val) 2844 return ret_val; 2845 e1e_rphy(hw, PHY_REG(776, 20), &data); 2846 data &= ~(0x3FF << 2); 2847 data |= (0x8 << 2); 2848 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2849 if (ret_val) 2850 return ret_val; 2851 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2852 if (ret_val) 2853 return ret_val; 2854 e1e_rphy(hw, HV_PM_CTRL, &data); 2855 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2856 if (ret_val) 2857 return ret_val; 2858 } 2859 2860 /* re-enable Rx path after enabling/disabling workaround */ 2861 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2862} 2863 2864/** 2865 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds 2866 * @hw: pointer to the HW structure 2867 * 2868 * A series of PHY workarounds to be done after every PHY reset. 2869 **/ 2870static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2871{ 2872 s32 ret_val = 0; 2873 2874 if (hw->mac.type != e1000_pch2lan) 2875 return 0; 2876 2877 /* Set MDIO slow mode before any other MDIO access */ 2878 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2879 if (ret_val) 2880 return ret_val; 2881 2882 ret_val = hw->phy.ops.acquire(hw); 2883 if (ret_val) 2884 return ret_val; 2885 /* set MSE higher to enable link to stay up when noise is high */ 2886 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2887 if (ret_val) 2888 goto release; 2889 /* drop link after 5 times MSE threshold was reached */ 2890 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2891release: 2892 hw->phy.ops.release(hw); 2893 2894 return ret_val; 2895} 2896 2897/** 2898 * e1000_k1_workaround_lv - K1 Si workaround 2899 * @hw: pointer to the HW structure 2900 * 2901 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2902 * Disable K1 in 1000Mbps and 100Mbps 2903 **/ 2904static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2905{ 2906 s32 ret_val = 0; 2907 u16 status_reg = 0; 2908 2909 if (hw->mac.type != e1000_pch2lan) 2910 return 0; 2911 2912 /* Set K1 beacon duration based on 10Mbs speed */ 2913 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2914 if (ret_val) 2915 return ret_val; 2916 2917 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2918 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2919 if (status_reg & 2920 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2921 u16 pm_phy_reg; 2922 2923 /* LV 1G/100 Packet drop issue wa */ 2924 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2925 if (ret_val) 2926 return ret_val; 2927 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2928 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2929 if (ret_val) 2930 return ret_val; 2931 } else { 2932 u32 mac_reg; 2933 2934 mac_reg = er32(FEXTNVM4); 2935 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2936 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2937 ew32(FEXTNVM4, mac_reg); 2938 } 2939 } 2940 2941 return ret_val; 2942} 2943 2944/** 2945 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2946 * @hw: pointer to the HW structure 2947 * @gate: boolean set to true to gate, false to ungate 2948 * 2949 * Gate/ungate the automatic PHY configuration via hardware; perform 2950 * the configuration via software instead. 2951 **/ 2952static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2953{ 2954 u32 extcnf_ctrl; 2955 2956 if (hw->mac.type < e1000_pch2lan) 2957 return; 2958 2959 extcnf_ctrl = er32(EXTCNF_CTRL); 2960 2961 if (gate) 2962 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2963 else 2964 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2965 2966 ew32(EXTCNF_CTRL, extcnf_ctrl); 2967} 2968 2969/** 2970 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2971 * @hw: pointer to the HW structure 2972 * 2973 * Check the appropriate indication the MAC has finished configuring the 2974 * PHY after a software reset. 2975 **/ 2976static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2977{ 2978 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2979 2980 /* Wait for basic configuration completes before proceeding */ 2981 do { 2982 data = er32(STATUS); 2983 data &= E1000_STATUS_LAN_INIT_DONE; 2984 usleep_range(100, 200); 2985 } while ((!data) && --loop); 2986 2987 /* If basic configuration is incomplete before the above loop 2988 * count reaches 0, loading the configuration from NVM will 2989 * leave the PHY in a bad state possibly resulting in no link. 2990 */ 2991 if (loop == 0) 2992 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2993 2994 /* Clear the Init Done bit for the next init event */ 2995 data = er32(STATUS); 2996 data &= ~E1000_STATUS_LAN_INIT_DONE; 2997 ew32(STATUS, data); 2998} 2999 3000/** 3001 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 3002 * @hw: pointer to the HW structure 3003 **/ 3004static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 3005{ 3006 s32 ret_val = 0; 3007 u16 reg; 3008 3009 if (hw->phy.ops.check_reset_block(hw)) 3010 return 0; 3011 3012 /* Allow time for h/w to get to quiescent state after reset */ 3013 usleep_range(10000, 11000); 3014 3015 /* Perform any necessary post-reset workarounds */ 3016 switch (hw->mac.type) { 3017 case e1000_pchlan: 3018 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 3019 if (ret_val) 3020 return ret_val; 3021 break; 3022 case e1000_pch2lan: 3023 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 3024 if (ret_val) 3025 return ret_val; 3026 break; 3027 default: 3028 break; 3029 } 3030 3031 /* Clear the host wakeup bit after lcd reset */ 3032 if (hw->mac.type >= e1000_pchlan) { 3033 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 3034 reg &= ~BM_WUC_HOST_WU_BIT; 3035 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 3036 } 3037 3038 /* Configure the LCD with the extended configuration region in NVM */ 3039 ret_val = e1000_sw_lcd_config_ich8lan(hw); 3040 if (ret_val) 3041 return ret_val; 3042 3043 /* Configure the LCD with the OEM bits in NVM */ 3044 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 3045 3046 if (hw->mac.type == e1000_pch2lan) { 3047 /* Ungate automatic PHY configuration on non-managed 82579 */ 3048 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 3049 usleep_range(10000, 11000); 3050 e1000_gate_hw_phy_config_ich8lan(hw, false); 3051 } 3052 3053 /* Set EEE LPI Update Timer to 200usec */ 3054 ret_val = hw->phy.ops.acquire(hw); 3055 if (ret_val) 3056 return ret_val; 3057 ret_val = e1000_write_emi_reg_locked(hw, 3058 I82579_LPI_UPDATE_TIMER, 3059 0x1387); 3060 hw->phy.ops.release(hw); 3061 } 3062 3063 return ret_val; 3064} 3065 3066/** 3067 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 3068 * @hw: pointer to the HW structure 3069 * 3070 * Resets the PHY 3071 * This is a function pointer entry point called by drivers 3072 * or other shared routines. 3073 **/ 3074static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 3075{ 3076 s32 ret_val = 0; 3077 3078 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 3079 if ((hw->mac.type == e1000_pch2lan) && 3080 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 3081 e1000_gate_hw_phy_config_ich8lan(hw, true); 3082 3083 ret_val = e1000e_phy_hw_reset_generic(hw); 3084 if (ret_val) 3085 return ret_val; 3086 3087 return e1000_post_phy_reset_ich8lan(hw); 3088} 3089 3090/** 3091 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 3092 * @hw: pointer to the HW structure 3093 * @active: true to enable LPLU, false to disable 3094 * 3095 * Sets the LPLU state according to the active flag. For PCH, if OEM write 3096 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 3097 * the phy speed. This function will manually set the LPLU bit and restart 3098 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 3099 * since it configures the same bit. 3100 **/ 3101static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 3102{ 3103 s32 ret_val; 3104 u16 oem_reg; 3105 3106 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 3107 if (ret_val) 3108 return ret_val; 3109 3110 if (active) 3111 oem_reg |= HV_OEM_BITS_LPLU; 3112 else 3113 oem_reg &= ~HV_OEM_BITS_LPLU; 3114 3115 if (!hw->phy.ops.check_reset_block(hw)) 3116 oem_reg |= HV_OEM_BITS_RESTART_AN; 3117 3118 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 3119} 3120 3121/** 3122 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 3123 * @hw: pointer to the HW structure 3124 * @active: true to enable LPLU, false to disable 3125 * 3126 * Sets the LPLU D0 state according to the active flag. When 3127 * activating LPLU this function also disables smart speed 3128 * and vice versa. LPLU will not be activated unless the 3129 * device autonegotiation advertisement meets standards of 3130 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3131 * This is a function pointer entry point only called by 3132 * PHY setup routines. 3133 **/ 3134static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3135{ 3136 struct e1000_phy_info *phy = &hw->phy; 3137 u32 phy_ctrl; 3138 s32 ret_val = 0; 3139 u16 data; 3140 3141 if (phy->type == e1000_phy_ife) 3142 return 0; 3143 3144 phy_ctrl = er32(PHY_CTRL); 3145 3146 if (active) { 3147 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3148 ew32(PHY_CTRL, phy_ctrl); 3149 3150 if (phy->type != e1000_phy_igp_3) 3151 return 0; 3152 3153 /* Call gig speed drop workaround on LPLU before accessing 3154 * any PHY registers 3155 */ 3156 if (hw->mac.type == e1000_ich8lan) 3157 e1000e_gig_downshift_workaround_ich8lan(hw); 3158 3159 /* When LPLU is enabled, we should disable SmartSpeed */ 3160 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3161 if (ret_val) 3162 return ret_val; 3163 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3164 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3165 if (ret_val) 3166 return ret_val; 3167 } else { 3168 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3169 ew32(PHY_CTRL, phy_ctrl); 3170 3171 if (phy->type != e1000_phy_igp_3) 3172 return 0; 3173 3174 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3175 * during Dx states where the power conservation is most 3176 * important. During driver activity we should enable 3177 * SmartSpeed, so performance is maintained. 3178 */ 3179 if (phy->smart_speed == e1000_smart_speed_on) { 3180 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3181 &data); 3182 if (ret_val) 3183 return ret_val; 3184 3185 data |= IGP01E1000_PSCFR_SMART_SPEED; 3186 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3187 data); 3188 if (ret_val) 3189 return ret_val; 3190 } else if (phy->smart_speed == e1000_smart_speed_off) { 3191 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3192 &data); 3193 if (ret_val) 3194 return ret_val; 3195 3196 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3197 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3198 data); 3199 if (ret_val) 3200 return ret_val; 3201 } 3202 } 3203 3204 return 0; 3205} 3206 3207/** 3208 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3209 * @hw: pointer to the HW structure 3210 * @active: true to enable LPLU, false to disable 3211 * 3212 * Sets the LPLU D3 state according to the active flag. When 3213 * activating LPLU this function also disables smart speed 3214 * and vice versa. LPLU will not be activated unless the 3215 * device autonegotiation advertisement meets standards of 3216 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3217 * This is a function pointer entry point only called by 3218 * PHY setup routines. 3219 **/ 3220static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3221{ 3222 struct e1000_phy_info *phy = &hw->phy; 3223 u32 phy_ctrl; 3224 s32 ret_val = 0; 3225 u16 data; 3226 3227 phy_ctrl = er32(PHY_CTRL); 3228 3229 if (!active) { 3230 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3231 ew32(PHY_CTRL, phy_ctrl); 3232 3233 if (phy->type != e1000_phy_igp_3) 3234 return 0; 3235 3236 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3237 * during Dx states where the power conservation is most 3238 * important. During driver activity we should enable 3239 * SmartSpeed, so performance is maintained. 3240 */ 3241 if (phy->smart_speed == e1000_smart_speed_on) { 3242 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3243 &data); 3244 if (ret_val) 3245 return ret_val; 3246 3247 data |= IGP01E1000_PSCFR_SMART_SPEED; 3248 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3249 data); 3250 if (ret_val) 3251 return ret_val; 3252 } else if (phy->smart_speed == e1000_smart_speed_off) { 3253 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3254 &data); 3255 if (ret_val) 3256 return ret_val; 3257 3258 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3259 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3260 data); 3261 if (ret_val) 3262 return ret_val; 3263 } 3264 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3265 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3266 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3267 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3268 ew32(PHY_CTRL, phy_ctrl); 3269 3270 if (phy->type != e1000_phy_igp_3) 3271 return 0; 3272 3273 /* Call gig speed drop workaround on LPLU before accessing 3274 * any PHY registers 3275 */ 3276 if (hw->mac.type == e1000_ich8lan) 3277 e1000e_gig_downshift_workaround_ich8lan(hw); 3278 3279 /* When LPLU is enabled, we should disable SmartSpeed */ 3280 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3281 if (ret_val) 3282 return ret_val; 3283 3284 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3285 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3286 } 3287 3288 return ret_val; 3289} 3290 3291/** 3292 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3293 * @hw: pointer to the HW structure 3294 * @bank: pointer to the variable that returns the active bank 3295 * 3296 * Reads signature byte from the NVM using the flash access registers. 3297 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3298 **/ 3299static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3300{ 3301 u32 eecd; 3302 struct e1000_nvm_info *nvm = &hw->nvm; 3303 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3304 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3305 u32 nvm_dword = 0; 3306 u8 sig_byte = 0; 3307 s32 ret_val; 3308 3309 switch (hw->mac.type) { 3310 case e1000_pch_spt: 3311 case e1000_pch_cnp: 3312 case e1000_pch_tgp: 3313 case e1000_pch_adp: 3314 case e1000_pch_mtp: 3315 case e1000_pch_lnp: 3316 case e1000_pch_ptp: 3317 case e1000_pch_nvp: 3318 bank1_offset = nvm->flash_bank_size; 3319 act_offset = E1000_ICH_NVM_SIG_WORD; 3320 3321 /* set bank to 0 in case flash read fails */ 3322 *bank = 0; 3323 3324 /* Check bank 0 */ 3325 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3326 &nvm_dword); 3327 if (ret_val) 3328 return ret_val; 3329 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3330 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3331 E1000_ICH_NVM_SIG_VALUE) { 3332 *bank = 0; 3333 return 0; 3334 } 3335 3336 /* Check bank 1 */ 3337 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3338 bank1_offset, 3339 &nvm_dword); 3340 if (ret_val) 3341 return ret_val; 3342 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3343 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3344 E1000_ICH_NVM_SIG_VALUE) { 3345 *bank = 1; 3346 return 0; 3347 } 3348 3349 e_dbg("ERROR: No valid NVM bank present\n"); 3350 return -E1000_ERR_NVM; 3351 case e1000_ich8lan: 3352 case e1000_ich9lan: 3353 eecd = er32(EECD); 3354 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3355 E1000_EECD_SEC1VAL_VALID_MASK) { 3356 if (eecd & E1000_EECD_SEC1VAL) 3357 *bank = 1; 3358 else 3359 *bank = 0; 3360 3361 return 0; 3362 } 3363 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3364 fallthrough; 3365 default: 3366 /* set bank to 0 in case flash read fails */ 3367 *bank = 0; 3368 3369 /* Check bank 0 */ 3370 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3371 &sig_byte); 3372 if (ret_val) 3373 return ret_val; 3374 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3375 E1000_ICH_NVM_SIG_VALUE) { 3376 *bank = 0; 3377 return 0; 3378 } 3379 3380 /* Check bank 1 */ 3381 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3382 bank1_offset, 3383 &sig_byte); 3384 if (ret_val) 3385 return ret_val; 3386 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3387 E1000_ICH_NVM_SIG_VALUE) { 3388 *bank = 1; 3389 return 0; 3390 } 3391 3392 e_dbg("ERROR: No valid NVM bank present\n"); 3393 return -E1000_ERR_NVM; 3394 } 3395} 3396 3397/** 3398 * e1000_read_nvm_spt - NVM access for SPT 3399 * @hw: pointer to the HW structure 3400 * @offset: The offset (in bytes) of the word(s) to read. 3401 * @words: Size of data to read in words. 3402 * @data: pointer to the word(s) to read at offset. 3403 * 3404 * Reads a word(s) from the NVM 3405 **/ 3406static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3407 u16 *data) 3408{ 3409 struct e1000_nvm_info *nvm = &hw->nvm; 3410 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3411 u32 act_offset; 3412 s32 ret_val = 0; 3413 u32 bank = 0; 3414 u32 dword = 0; 3415 u16 offset_to_read; 3416 u16 i; 3417 3418 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3419 (words == 0)) { 3420 e_dbg("nvm parameter(s) out of bounds\n"); 3421 ret_val = -E1000_ERR_NVM; 3422 goto out; 3423 } 3424 3425 nvm->ops.acquire(hw); 3426 3427 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3428 if (ret_val) { 3429 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3430 bank = 0; 3431 } 3432 3433 act_offset = (bank) ? nvm->flash_bank_size : 0; 3434 act_offset += offset; 3435 3436 ret_val = 0; 3437 3438 for (i = 0; i < words; i += 2) { 3439 if (words - i == 1) { 3440 if (dev_spec->shadow_ram[offset + i].modified) { 3441 data[i] = 3442 dev_spec->shadow_ram[offset + i].value; 3443 } else { 3444 offset_to_read = act_offset + i - 3445 ((act_offset + i) % 2); 3446 ret_val = 3447 e1000_read_flash_dword_ich8lan(hw, 3448 offset_to_read, 3449 &dword); 3450 if (ret_val) 3451 break; 3452 if ((act_offset + i) % 2 == 0) 3453 data[i] = (u16)(dword & 0xFFFF); 3454 else 3455 data[i] = (u16)((dword >> 16) & 0xFFFF); 3456 } 3457 } else { 3458 offset_to_read = act_offset + i; 3459 if (!(dev_spec->shadow_ram[offset + i].modified) || 3460 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3461 ret_val = 3462 e1000_read_flash_dword_ich8lan(hw, 3463 offset_to_read, 3464 &dword); 3465 if (ret_val) 3466 break; 3467 } 3468 if (dev_spec->shadow_ram[offset + i].modified) 3469 data[i] = 3470 dev_spec->shadow_ram[offset + i].value; 3471 else 3472 data[i] = (u16)(dword & 0xFFFF); 3473 if (dev_spec->shadow_ram[offset + i].modified) 3474 data[i + 1] = 3475 dev_spec->shadow_ram[offset + i + 1].value; 3476 else 3477 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3478 } 3479 } 3480 3481 nvm->ops.release(hw); 3482 3483out: 3484 if (ret_val) 3485 e_dbg("NVM read error: %d\n", ret_val); 3486 3487 return ret_val; 3488} 3489 3490/** 3491 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3492 * @hw: pointer to the HW structure 3493 * @offset: The offset (in bytes) of the word(s) to read. 3494 * @words: Size of data to read in words 3495 * @data: Pointer to the word(s) to read at offset. 3496 * 3497 * Reads a word(s) from the NVM using the flash access registers. 3498 **/ 3499static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3500 u16 *data) 3501{ 3502 struct e1000_nvm_info *nvm = &hw->nvm; 3503 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3504 u32 act_offset; 3505 s32 ret_val = 0; 3506 u32 bank = 0; 3507 u16 i, word; 3508 3509 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3510 (words == 0)) { 3511 e_dbg("nvm parameter(s) out of bounds\n"); 3512 ret_val = -E1000_ERR_NVM; 3513 goto out; 3514 } 3515 3516 nvm->ops.acquire(hw); 3517 3518 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3519 if (ret_val) { 3520 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3521 bank = 0; 3522 } 3523 3524 act_offset = (bank) ? nvm->flash_bank_size : 0; 3525 act_offset += offset; 3526 3527 ret_val = 0; 3528 for (i = 0; i < words; i++) { 3529 if (dev_spec->shadow_ram[offset + i].modified) { 3530 data[i] = dev_spec->shadow_ram[offset + i].value; 3531 } else { 3532 ret_val = e1000_read_flash_word_ich8lan(hw, 3533 act_offset + i, 3534 &word); 3535 if (ret_val) 3536 break; 3537 data[i] = word; 3538 } 3539 } 3540 3541 nvm->ops.release(hw); 3542 3543out: 3544 if (ret_val) 3545 e_dbg("NVM read error: %d\n", ret_val); 3546 3547 return ret_val; 3548} 3549 3550/** 3551 * e1000_flash_cycle_init_ich8lan - Initialize flash 3552 * @hw: pointer to the HW structure 3553 * 3554 * This function does initial flash setup so that a new read/write/erase cycle 3555 * can be started. 3556 **/ 3557static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3558{ 3559 union ich8_hws_flash_status hsfsts; 3560 s32 ret_val = -E1000_ERR_NVM; 3561 3562 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3563 3564 /* Check if the flash descriptor is valid */ 3565 if (!hsfsts.hsf_status.fldesvalid) { 3566 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3567 return -E1000_ERR_NVM; 3568 } 3569 3570 /* Clear FCERR and DAEL in hw status by writing 1 */ 3571 hsfsts.hsf_status.flcerr = 1; 3572 hsfsts.hsf_status.dael = 1; 3573 if (hw->mac.type >= e1000_pch_spt) 3574 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3575 else 3576 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3577 3578 /* Either we should have a hardware SPI cycle in progress 3579 * bit to check against, in order to start a new cycle or 3580 * FDONE bit should be changed in the hardware so that it 3581 * is 1 after hardware reset, which can then be used as an 3582 * indication whether a cycle is in progress or has been 3583 * completed. 3584 */ 3585 3586 if (!hsfsts.hsf_status.flcinprog) { 3587 /* There is no cycle running at present, 3588 * so we can start a cycle. 3589 * Begin by setting Flash Cycle Done. 3590 */ 3591 hsfsts.hsf_status.flcdone = 1; 3592 if (hw->mac.type >= e1000_pch_spt) 3593 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3594 else 3595 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3596 ret_val = 0; 3597 } else { 3598 s32 i; 3599 3600 /* Otherwise poll for sometime so the current 3601 * cycle has a chance to end before giving up. 3602 */ 3603 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3604 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3605 if (!hsfsts.hsf_status.flcinprog) { 3606 ret_val = 0; 3607 break; 3608 } 3609 udelay(1); 3610 } 3611 if (!ret_val) { 3612 /* Successful in waiting for previous cycle to timeout, 3613 * now set the Flash Cycle Done. 3614 */ 3615 hsfsts.hsf_status.flcdone = 1; 3616 if (hw->mac.type >= e1000_pch_spt) 3617 ew32flash(ICH_FLASH_HSFSTS, 3618 hsfsts.regval & 0xFFFF); 3619 else 3620 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3621 } else { 3622 e_dbg("Flash controller busy, cannot get access\n"); 3623 } 3624 } 3625 3626 return ret_val; 3627} 3628 3629/** 3630 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3631 * @hw: pointer to the HW structure 3632 * @timeout: maximum time to wait for completion 3633 * 3634 * This function starts a flash cycle and waits for its completion. 3635 **/ 3636static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3637{ 3638 union ich8_hws_flash_ctrl hsflctl; 3639 union ich8_hws_flash_status hsfsts; 3640 u32 i = 0; 3641 3642 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3643 if (hw->mac.type >= e1000_pch_spt) 3644 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3645 else 3646 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3647 hsflctl.hsf_ctrl.flcgo = 1; 3648 3649 if (hw->mac.type >= e1000_pch_spt) 3650 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3651 else 3652 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3653 3654 /* wait till FDONE bit is set to 1 */ 3655 do { 3656 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3657 if (hsfsts.hsf_status.flcdone) 3658 break; 3659 udelay(1); 3660 } while (i++ < timeout); 3661 3662 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3663 return 0; 3664 3665 return -E1000_ERR_NVM; 3666} 3667 3668/** 3669 * e1000_read_flash_dword_ich8lan - Read dword from flash 3670 * @hw: pointer to the HW structure 3671 * @offset: offset to data location 3672 * @data: pointer to the location for storing the data 3673 * 3674 * Reads the flash dword at offset into data. Offset is converted 3675 * to bytes before read. 3676 **/ 3677static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3678 u32 *data) 3679{ 3680 /* Must convert word offset into bytes. */ 3681 offset <<= 1; 3682 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3683} 3684 3685/** 3686 * e1000_read_flash_word_ich8lan - Read word from flash 3687 * @hw: pointer to the HW structure 3688 * @offset: offset to data location 3689 * @data: pointer to the location for storing the data 3690 * 3691 * Reads the flash word at offset into data. Offset is converted 3692 * to bytes before read. 3693 **/ 3694static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3695 u16 *data) 3696{ 3697 /* Must convert offset into bytes. */ 3698 offset <<= 1; 3699 3700 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3701} 3702 3703/** 3704 * e1000_read_flash_byte_ich8lan - Read byte from flash 3705 * @hw: pointer to the HW structure 3706 * @offset: The offset of the byte to read. 3707 * @data: Pointer to a byte to store the value read. 3708 * 3709 * Reads a single byte from the NVM using the flash access registers. 3710 **/ 3711static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3712 u8 *data) 3713{ 3714 s32 ret_val; 3715 u16 word = 0; 3716 3717 /* In SPT, only 32 bits access is supported, 3718 * so this function should not be called. 3719 */ 3720 if (hw->mac.type >= e1000_pch_spt) 3721 return -E1000_ERR_NVM; 3722 else 3723 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3724 3725 if (ret_val) 3726 return ret_val; 3727 3728 *data = (u8)word; 3729 3730 return 0; 3731} 3732 3733/** 3734 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3735 * @hw: pointer to the HW structure 3736 * @offset: The offset (in bytes) of the byte or word to read. 3737 * @size: Size of data to read, 1=byte 2=word 3738 * @data: Pointer to the word to store the value read. 3739 * 3740 * Reads a byte or word from the NVM using the flash access registers. 3741 **/ 3742static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3743 u8 size, u16 *data) 3744{ 3745 union ich8_hws_flash_status hsfsts; 3746 union ich8_hws_flash_ctrl hsflctl; 3747 u32 flash_linear_addr; 3748 u32 flash_data = 0; 3749 s32 ret_val = -E1000_ERR_NVM; 3750 u8 count = 0; 3751 3752 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3753 return -E1000_ERR_NVM; 3754 3755 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3756 hw->nvm.flash_base_addr); 3757 3758 do { 3759 udelay(1); 3760 /* Steps */ 3761 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3762 if (ret_val) 3763 break; 3764 3765 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3766 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3767 hsflctl.hsf_ctrl.fldbcount = size - 1; 3768 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3769 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3770 3771 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3772 3773 ret_val = 3774 e1000_flash_cycle_ich8lan(hw, 3775 ICH_FLASH_READ_COMMAND_TIMEOUT); 3776 3777 /* Check if FCERR is set to 1, if set to 1, clear it 3778 * and try the whole sequence a few more times, else 3779 * read in (shift in) the Flash Data0, the order is 3780 * least significant byte first msb to lsb 3781 */ 3782 if (!ret_val) { 3783 flash_data = er32flash(ICH_FLASH_FDATA0); 3784 if (size == 1) 3785 *data = (u8)(flash_data & 0x000000FF); 3786 else if (size == 2) 3787 *data = (u16)(flash_data & 0x0000FFFF); 3788 break; 3789 } else { 3790 /* If we've gotten here, then things are probably 3791 * completely hosed, but if the error condition is 3792 * detected, it won't hurt to give it another try... 3793 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3794 */ 3795 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3796 if (hsfsts.hsf_status.flcerr) { 3797 /* Repeat for some time before giving up. */ 3798 continue; 3799 } else if (!hsfsts.hsf_status.flcdone) { 3800 e_dbg("Timeout error - flash cycle did not complete.\n"); 3801 break; 3802 } 3803 } 3804 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3805 3806 return ret_val; 3807} 3808 3809/** 3810 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3811 * @hw: pointer to the HW structure 3812 * @offset: The offset (in bytes) of the dword to read. 3813 * @data: Pointer to the dword to store the value read. 3814 * 3815 * Reads a byte or word from the NVM using the flash access registers. 3816 **/ 3817 3818static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3819 u32 *data) 3820{ 3821 union ich8_hws_flash_status hsfsts; 3822 union ich8_hws_flash_ctrl hsflctl; 3823 u32 flash_linear_addr; 3824 s32 ret_val = -E1000_ERR_NVM; 3825 u8 count = 0; 3826 3827 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3828 return -E1000_ERR_NVM; 3829 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3830 hw->nvm.flash_base_addr); 3831 3832 do { 3833 udelay(1); 3834 /* Steps */ 3835 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3836 if (ret_val) 3837 break; 3838 /* In SPT, This register is in Lan memory space, not flash. 3839 * Therefore, only 32 bit access is supported 3840 */ 3841 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3842 3843 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3844 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3845 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3846 /* In SPT, This register is in Lan memory space, not flash. 3847 * Therefore, only 32 bit access is supported 3848 */ 3849 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3850 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3851 3852 ret_val = 3853 e1000_flash_cycle_ich8lan(hw, 3854 ICH_FLASH_READ_COMMAND_TIMEOUT); 3855 3856 /* Check if FCERR is set to 1, if set to 1, clear it 3857 * and try the whole sequence a few more times, else 3858 * read in (shift in) the Flash Data0, the order is 3859 * least significant byte first msb to lsb 3860 */ 3861 if (!ret_val) { 3862 *data = er32flash(ICH_FLASH_FDATA0); 3863 break; 3864 } else { 3865 /* If we've gotten here, then things are probably 3866 * completely hosed, but if the error condition is 3867 * detected, it won't hurt to give it another try... 3868 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3869 */ 3870 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3871 if (hsfsts.hsf_status.flcerr) { 3872 /* Repeat for some time before giving up. */ 3873 continue; 3874 } else if (!hsfsts.hsf_status.flcdone) { 3875 e_dbg("Timeout error - flash cycle did not complete.\n"); 3876 break; 3877 } 3878 } 3879 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3880 3881 return ret_val; 3882} 3883 3884/** 3885 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3886 * @hw: pointer to the HW structure 3887 * @offset: The offset (in bytes) of the word(s) to write. 3888 * @words: Size of data to write in words 3889 * @data: Pointer to the word(s) to write at offset. 3890 * 3891 * Writes a byte or word to the NVM using the flash access registers. 3892 **/ 3893static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3894 u16 *data) 3895{ 3896 struct e1000_nvm_info *nvm = &hw->nvm; 3897 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3898 u16 i; 3899 3900 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3901 (words == 0)) { 3902 e_dbg("nvm parameter(s) out of bounds\n"); 3903 return -E1000_ERR_NVM; 3904 } 3905 3906 nvm->ops.acquire(hw); 3907 3908 for (i = 0; i < words; i++) { 3909 dev_spec->shadow_ram[offset + i].modified = true; 3910 dev_spec->shadow_ram[offset + i].value = data[i]; 3911 } 3912 3913 nvm->ops.release(hw); 3914 3915 return 0; 3916} 3917 3918/** 3919 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3920 * @hw: pointer to the HW structure 3921 * 3922 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3923 * which writes the checksum to the shadow ram. The changes in the shadow 3924 * ram are then committed to the EEPROM by processing each bank at a time 3925 * checking for the modified bit and writing only the pending changes. 3926 * After a successful commit, the shadow ram is cleared and is ready for 3927 * future writes. 3928 **/ 3929static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3930{ 3931 struct e1000_nvm_info *nvm = &hw->nvm; 3932 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3933 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3934 s32 ret_val; 3935 u32 dword = 0; 3936 3937 ret_val = e1000e_update_nvm_checksum_generic(hw); 3938 if (ret_val) 3939 goto out; 3940 3941 if (nvm->type != e1000_nvm_flash_sw) 3942 goto out; 3943 3944 nvm->ops.acquire(hw); 3945 3946 /* We're writing to the opposite bank so if we're on bank 1, 3947 * write to bank 0 etc. We also need to erase the segment that 3948 * is going to be written 3949 */ 3950 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3951 if (ret_val) { 3952 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3953 bank = 0; 3954 } 3955 3956 if (bank == 0) { 3957 new_bank_offset = nvm->flash_bank_size; 3958 old_bank_offset = 0; 3959 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3960 if (ret_val) 3961 goto release; 3962 } else { 3963 old_bank_offset = nvm->flash_bank_size; 3964 new_bank_offset = 0; 3965 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3966 if (ret_val) 3967 goto release; 3968 } 3969 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3970 /* Determine whether to write the value stored 3971 * in the other NVM bank or a modified value stored 3972 * in the shadow RAM 3973 */ 3974 ret_val = e1000_read_flash_dword_ich8lan(hw, 3975 i + old_bank_offset, 3976 &dword); 3977 3978 if (dev_spec->shadow_ram[i].modified) { 3979 dword &= 0xffff0000; 3980 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3981 } 3982 if (dev_spec->shadow_ram[i + 1].modified) { 3983 dword &= 0x0000ffff; 3984 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3985 << 16); 3986 } 3987 if (ret_val) 3988 break; 3989 3990 /* If the word is 0x13, then make sure the signature bits 3991 * (15:14) are 11b until the commit has completed. 3992 * This will allow us to write 10b which indicates the 3993 * signature is valid. We want to do this after the write 3994 * has completed so that we don't mark the segment valid 3995 * while the write is still in progress 3996 */ 3997 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3998 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3999 4000 /* Convert offset to bytes. */ 4001 act_offset = (i + new_bank_offset) << 1; 4002 4003 usleep_range(100, 200); 4004 4005 /* Write the data to the new bank. Offset in words */ 4006 act_offset = i + new_bank_offset; 4007 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 4008 dword); 4009 if (ret_val) 4010 break; 4011 } 4012 4013 /* Don't bother writing the segment valid bits if sector 4014 * programming failed. 4015 */ 4016 if (ret_val) { 4017 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4018 e_dbg("Flash commit failed.\n"); 4019 goto release; 4020 } 4021 4022 /* Finally validate the new segment by setting bit 15:14 4023 * to 10b in word 0x13 , this can be done without an 4024 * erase as well since these bits are 11 to start with 4025 * and we need to change bit 14 to 0b 4026 */ 4027 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4028 4029 /*offset in words but we read dword */ 4030 --act_offset; 4031 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4032 4033 if (ret_val) 4034 goto release; 4035 4036 dword &= 0xBFFFFFFF; 4037 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4038 4039 if (ret_val) 4040 goto release; 4041 4042 /* offset in words but we read dword */ 4043 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 4044 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 4045 4046 if (ret_val) 4047 goto release; 4048 4049 dword &= 0x00FFFFFF; 4050 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 4051 4052 if (ret_val) 4053 goto release; 4054 4055 /* Great! Everything worked, we can now clear the cached entries. */ 4056 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4057 dev_spec->shadow_ram[i].modified = false; 4058 dev_spec->shadow_ram[i].value = 0xFFFF; 4059 } 4060 4061release: 4062 nvm->ops.release(hw); 4063 4064 /* Reload the EEPROM, or else modifications will not appear 4065 * until after the next adapter reset. 4066 */ 4067 if (!ret_val) { 4068 nvm->ops.reload(hw); 4069 usleep_range(10000, 11000); 4070 } 4071 4072out: 4073 if (ret_val) 4074 e_dbg("NVM update error: %d\n", ret_val); 4075 4076 return ret_val; 4077} 4078 4079/** 4080 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 4081 * @hw: pointer to the HW structure 4082 * 4083 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4084 * which writes the checksum to the shadow ram. The changes in the shadow 4085 * ram are then committed to the EEPROM by processing each bank at a time 4086 * checking for the modified bit and writing only the pending changes. 4087 * After a successful commit, the shadow ram is cleared and is ready for 4088 * future writes. 4089 **/ 4090static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 4091{ 4092 struct e1000_nvm_info *nvm = &hw->nvm; 4093 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4094 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4095 s32 ret_val; 4096 u16 data = 0; 4097 4098 ret_val = e1000e_update_nvm_checksum_generic(hw); 4099 if (ret_val) 4100 goto out; 4101 4102 if (nvm->type != e1000_nvm_flash_sw) 4103 goto out; 4104 4105 nvm->ops.acquire(hw); 4106 4107 /* We're writing to the opposite bank so if we're on bank 1, 4108 * write to bank 0 etc. We also need to erase the segment that 4109 * is going to be written 4110 */ 4111 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4112 if (ret_val) { 4113 e_dbg("Could not detect valid bank, assuming bank 0\n"); 4114 bank = 0; 4115 } 4116 4117 if (bank == 0) { 4118 new_bank_offset = nvm->flash_bank_size; 4119 old_bank_offset = 0; 4120 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4121 if (ret_val) 4122 goto release; 4123 } else { 4124 old_bank_offset = nvm->flash_bank_size; 4125 new_bank_offset = 0; 4126 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4127 if (ret_val) 4128 goto release; 4129 } 4130 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4131 if (dev_spec->shadow_ram[i].modified) { 4132 data = dev_spec->shadow_ram[i].value; 4133 } else { 4134 ret_val = e1000_read_flash_word_ich8lan(hw, i + 4135 old_bank_offset, 4136 &data); 4137 if (ret_val) 4138 break; 4139 } 4140 4141 /* If the word is 0x13, then make sure the signature bits 4142 * (15:14) are 11b until the commit has completed. 4143 * This will allow us to write 10b which indicates the 4144 * signature is valid. We want to do this after the write 4145 * has completed so that we don't mark the segment valid 4146 * while the write is still in progress 4147 */ 4148 if (i == E1000_ICH_NVM_SIG_WORD) 4149 data |= E1000_ICH_NVM_SIG_MASK; 4150 4151 /* Convert offset to bytes. */ 4152 act_offset = (i + new_bank_offset) << 1; 4153 4154 usleep_range(100, 200); 4155 /* Write the bytes to the new bank. */ 4156 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4157 act_offset, 4158 (u8)data); 4159 if (ret_val) 4160 break; 4161 4162 usleep_range(100, 200); 4163 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4164 act_offset + 1, 4165 (u8)(data >> 8)); 4166 if (ret_val) 4167 break; 4168 } 4169 4170 /* Don't bother writing the segment valid bits if sector 4171 * programming failed. 4172 */ 4173 if (ret_val) { 4174 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4175 e_dbg("Flash commit failed.\n"); 4176 goto release; 4177 } 4178 4179 /* Finally validate the new segment by setting bit 15:14 4180 * to 10b in word 0x13 , this can be done without an 4181 * erase as well since these bits are 11 to start with 4182 * and we need to change bit 14 to 0b 4183 */ 4184 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4185 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4186 if (ret_val) 4187 goto release; 4188 4189 data &= 0xBFFF; 4190 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4191 act_offset * 2 + 1, 4192 (u8)(data >> 8)); 4193 if (ret_val) 4194 goto release; 4195 4196 /* And invalidate the previously valid segment by setting 4197 * its signature word (0x13) high_byte to 0b. This can be 4198 * done without an erase because flash erase sets all bits 4199 * to 1's. We can write 1's to 0's without an erase 4200 */ 4201 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4202 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4203 if (ret_val) 4204 goto release; 4205 4206 /* Great! Everything worked, we can now clear the cached entries. */ 4207 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4208 dev_spec->shadow_ram[i].modified = false; 4209 dev_spec->shadow_ram[i].value = 0xFFFF; 4210 } 4211 4212release: 4213 nvm->ops.release(hw); 4214 4215 /* Reload the EEPROM, or else modifications will not appear 4216 * until after the next adapter reset. 4217 */ 4218 if (!ret_val) { 4219 nvm->ops.reload(hw); 4220 usleep_range(10000, 11000); 4221 } 4222 4223out: 4224 if (ret_val) 4225 e_dbg("NVM update error: %d\n", ret_val); 4226 4227 return ret_val; 4228} 4229 4230/** 4231 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4232 * @hw: pointer to the HW structure 4233 * 4234 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4235 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4236 * calculated, in which case we need to calculate the checksum and set bit 6. 4237 **/ 4238static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4239{ 4240 s32 ret_val; 4241 u16 data; 4242 u16 word; 4243 u16 valid_csum_mask; 4244 4245 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4246 * the checksum needs to be fixed. This bit is an indication that 4247 * the NVM was prepared by OEM software and did not calculate 4248 * the checksum...a likely scenario. 4249 */ 4250 switch (hw->mac.type) { 4251 case e1000_pch_lpt: 4252 case e1000_pch_spt: 4253 case e1000_pch_cnp: 4254 case e1000_pch_tgp: 4255 case e1000_pch_adp: 4256 case e1000_pch_mtp: 4257 case e1000_pch_lnp: 4258 case e1000_pch_ptp: 4259 case e1000_pch_nvp: 4260 word = NVM_COMPAT; 4261 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4262 break; 4263 default: 4264 word = NVM_FUTURE_INIT_WORD1; 4265 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4266 break; 4267 } 4268 4269 ret_val = e1000_read_nvm(hw, word, 1, &data); 4270 if (ret_val) 4271 return ret_val; 4272 4273 if (!(data & valid_csum_mask)) { 4274 e_dbg("NVM Checksum valid bit not set\n"); 4275 4276 if (hw->mac.type < e1000_pch_tgp) { 4277 data |= valid_csum_mask; 4278 ret_val = e1000_write_nvm(hw, word, 1, &data); 4279 if (ret_val) 4280 return ret_val; 4281 ret_val = e1000e_update_nvm_checksum(hw); 4282 if (ret_val) 4283 return ret_val; 4284 } else if (hw->mac.type == e1000_pch_tgp) { 4285 return 0; 4286 } 4287 } 4288 4289 return e1000e_validate_nvm_checksum_generic(hw); 4290} 4291 4292/** 4293 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4294 * @hw: pointer to the HW structure 4295 * 4296 * To prevent malicious write/erase of the NVM, set it to be read-only 4297 * so that the hardware ignores all write/erase cycles of the NVM via 4298 * the flash control registers. The shadow-ram copy of the NVM will 4299 * still be updated, however any updates to this copy will not stick 4300 * across driver reloads. 4301 **/ 4302void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4303{ 4304 struct e1000_nvm_info *nvm = &hw->nvm; 4305 union ich8_flash_protected_range pr0; 4306 union ich8_hws_flash_status hsfsts; 4307 u32 gfpreg; 4308 4309 nvm->ops.acquire(hw); 4310 4311 gfpreg = er32flash(ICH_FLASH_GFPREG); 4312 4313 /* Write-protect GbE Sector of NVM */ 4314 pr0.regval = er32flash(ICH_FLASH_PR0); 4315 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4316 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4317 pr0.range.wpe = true; 4318 ew32flash(ICH_FLASH_PR0, pr0.regval); 4319 4320 /* Lock down a subset of GbE Flash Control Registers, e.g. 4321 * PR0 to prevent the write-protection from being lifted. 4322 * Once FLOCKDN is set, the registers protected by it cannot 4323 * be written until FLOCKDN is cleared by a hardware reset. 4324 */ 4325 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4326 hsfsts.hsf_status.flockdn = true; 4327 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4328 4329 nvm->ops.release(hw); 4330} 4331 4332/** 4333 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4334 * @hw: pointer to the HW structure 4335 * @offset: The offset (in bytes) of the byte/word to read. 4336 * @size: Size of data to read, 1=byte 2=word 4337 * @data: The byte(s) to write to the NVM. 4338 * 4339 * Writes one/two bytes to the NVM using the flash access registers. 4340 **/ 4341static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4342 u8 size, u16 data) 4343{ 4344 union ich8_hws_flash_status hsfsts; 4345 union ich8_hws_flash_ctrl hsflctl; 4346 u32 flash_linear_addr; 4347 u32 flash_data = 0; 4348 s32 ret_val; 4349 u8 count = 0; 4350 4351 if (hw->mac.type >= e1000_pch_spt) { 4352 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4353 return -E1000_ERR_NVM; 4354 } else { 4355 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4356 return -E1000_ERR_NVM; 4357 } 4358 4359 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4360 hw->nvm.flash_base_addr); 4361 4362 do { 4363 udelay(1); 4364 /* Steps */ 4365 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4366 if (ret_val) 4367 break; 4368 /* In SPT, This register is in Lan memory space, not 4369 * flash. Therefore, only 32 bit access is supported 4370 */ 4371 if (hw->mac.type >= e1000_pch_spt) 4372 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4373 else 4374 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4375 4376 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4377 hsflctl.hsf_ctrl.fldbcount = size - 1; 4378 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4379 /* In SPT, This register is in Lan memory space, 4380 * not flash. Therefore, only 32 bit access is 4381 * supported 4382 */ 4383 if (hw->mac.type >= e1000_pch_spt) 4384 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4385 else 4386 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4387 4388 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4389 4390 if (size == 1) 4391 flash_data = (u32)data & 0x00FF; 4392 else 4393 flash_data = (u32)data; 4394 4395 ew32flash(ICH_FLASH_FDATA0, flash_data); 4396 4397 /* check if FCERR is set to 1 , if set to 1, clear it 4398 * and try the whole sequence a few more times else done 4399 */ 4400 ret_val = 4401 e1000_flash_cycle_ich8lan(hw, 4402 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4403 if (!ret_val) 4404 break; 4405 4406 /* If we're here, then things are most likely 4407 * completely hosed, but if the error condition 4408 * is detected, it won't hurt to give it another 4409 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4410 */ 4411 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4412 if (hsfsts.hsf_status.flcerr) 4413 /* Repeat for some time before giving up. */ 4414 continue; 4415 if (!hsfsts.hsf_status.flcdone) { 4416 e_dbg("Timeout error - flash cycle did not complete.\n"); 4417 break; 4418 } 4419 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4420 4421 return ret_val; 4422} 4423 4424/** 4425* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4426* @hw: pointer to the HW structure 4427* @offset: The offset (in bytes) of the dwords to read. 4428* @data: The 4 bytes to write to the NVM. 4429* 4430* Writes one/two/four bytes to the NVM using the flash access registers. 4431**/ 4432static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4433 u32 data) 4434{ 4435 union ich8_hws_flash_status hsfsts; 4436 union ich8_hws_flash_ctrl hsflctl; 4437 u32 flash_linear_addr; 4438 s32 ret_val; 4439 u8 count = 0; 4440 4441 if (hw->mac.type >= e1000_pch_spt) { 4442 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4443 return -E1000_ERR_NVM; 4444 } 4445 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4446 hw->nvm.flash_base_addr); 4447 do { 4448 udelay(1); 4449 /* Steps */ 4450 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4451 if (ret_val) 4452 break; 4453 4454 /* In SPT, This register is in Lan memory space, not 4455 * flash. Therefore, only 32 bit access is supported 4456 */ 4457 if (hw->mac.type >= e1000_pch_spt) 4458 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4459 >> 16; 4460 else 4461 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4462 4463 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4464 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4465 4466 /* In SPT, This register is in Lan memory space, 4467 * not flash. Therefore, only 32 bit access is 4468 * supported 4469 */ 4470 if (hw->mac.type >= e1000_pch_spt) 4471 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4472 else 4473 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4474 4475 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4476 4477 ew32flash(ICH_FLASH_FDATA0, data); 4478 4479 /* check if FCERR is set to 1 , if set to 1, clear it 4480 * and try the whole sequence a few more times else done 4481 */ 4482 ret_val = 4483 e1000_flash_cycle_ich8lan(hw, 4484 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4485 4486 if (!ret_val) 4487 break; 4488 4489 /* If we're here, then things are most likely 4490 * completely hosed, but if the error condition 4491 * is detected, it won't hurt to give it another 4492 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4493 */ 4494 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4495 4496 if (hsfsts.hsf_status.flcerr) 4497 /* Repeat for some time before giving up. */ 4498 continue; 4499 if (!hsfsts.hsf_status.flcdone) { 4500 e_dbg("Timeout error - flash cycle did not complete.\n"); 4501 break; 4502 } 4503 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4504 4505 return ret_val; 4506} 4507 4508/** 4509 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4510 * @hw: pointer to the HW structure 4511 * @offset: The index of the byte to read. 4512 * @data: The byte to write to the NVM. 4513 * 4514 * Writes a single byte to the NVM using the flash access registers. 4515 **/ 4516static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4517 u8 data) 4518{ 4519 u16 word = (u16)data; 4520 4521 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4522} 4523 4524/** 4525* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4526* @hw: pointer to the HW structure 4527* @offset: The offset of the word to write. 4528* @dword: The dword to write to the NVM. 4529* 4530* Writes a single dword to the NVM using the flash access registers. 4531* Goes through a retry algorithm before giving up. 4532**/ 4533static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4534 u32 offset, u32 dword) 4535{ 4536 s32 ret_val; 4537 u16 program_retries; 4538 4539 /* Must convert word offset into bytes. */ 4540 offset <<= 1; 4541 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4542 4543 if (!ret_val) 4544 return ret_val; 4545 for (program_retries = 0; program_retries < 100; program_retries++) { 4546 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4547 usleep_range(100, 200); 4548 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4549 if (!ret_val) 4550 break; 4551 } 4552 if (program_retries == 100) 4553 return -E1000_ERR_NVM; 4554 4555 return 0; 4556} 4557 4558/** 4559 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4560 * @hw: pointer to the HW structure 4561 * @offset: The offset of the byte to write. 4562 * @byte: The byte to write to the NVM. 4563 * 4564 * Writes a single byte to the NVM using the flash access registers. 4565 * Goes through a retry algorithm before giving up. 4566 **/ 4567static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4568 u32 offset, u8 byte) 4569{ 4570 s32 ret_val; 4571 u16 program_retries; 4572 4573 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4574 if (!ret_val) 4575 return ret_val; 4576 4577 for (program_retries = 0; program_retries < 100; program_retries++) { 4578 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4579 usleep_range(100, 200); 4580 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4581 if (!ret_val) 4582 break; 4583 } 4584 if (program_retries == 100) 4585 return -E1000_ERR_NVM; 4586 4587 return 0; 4588} 4589 4590/** 4591 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4592 * @hw: pointer to the HW structure 4593 * @bank: 0 for first bank, 1 for second bank, etc. 4594 * 4595 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4596 * bank N is 4096 * N + flash_reg_addr. 4597 **/ 4598static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4599{ 4600 struct e1000_nvm_info *nvm = &hw->nvm; 4601 union ich8_hws_flash_status hsfsts; 4602 union ich8_hws_flash_ctrl hsflctl; 4603 u32 flash_linear_addr; 4604 /* bank size is in 16bit words - adjust to bytes */ 4605 u32 flash_bank_size = nvm->flash_bank_size * 2; 4606 s32 ret_val; 4607 s32 count = 0; 4608 s32 j, iteration, sector_size; 4609 4610 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4611 4612 /* Determine HW Sector size: Read BERASE bits of hw flash status 4613 * register 4614 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4615 * consecutive sectors. The start index for the nth Hw sector 4616 * can be calculated as = bank * 4096 + n * 256 4617 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4618 * The start index for the nth Hw sector can be calculated 4619 * as = bank * 4096 4620 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4621 * (ich9 only, otherwise error condition) 4622 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4623 */ 4624 switch (hsfsts.hsf_status.berasesz) { 4625 case 0: 4626 /* Hw sector size 256 */ 4627 sector_size = ICH_FLASH_SEG_SIZE_256; 4628 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4629 break; 4630 case 1: 4631 sector_size = ICH_FLASH_SEG_SIZE_4K; 4632 iteration = 1; 4633 break; 4634 case 2: 4635 sector_size = ICH_FLASH_SEG_SIZE_8K; 4636 iteration = 1; 4637 break; 4638 case 3: 4639 sector_size = ICH_FLASH_SEG_SIZE_64K; 4640 iteration = 1; 4641 break; 4642 default: 4643 return -E1000_ERR_NVM; 4644 } 4645 4646 /* Start with the base address, then add the sector offset. */ 4647 flash_linear_addr = hw->nvm.flash_base_addr; 4648 flash_linear_addr += (bank) ? flash_bank_size : 0; 4649 4650 for (j = 0; j < iteration; j++) { 4651 do { 4652 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4653 4654 /* Steps */ 4655 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4656 if (ret_val) 4657 return ret_val; 4658 4659 /* Write a value 11 (block Erase) in Flash 4660 * Cycle field in hw flash control 4661 */ 4662 if (hw->mac.type >= e1000_pch_spt) 4663 hsflctl.regval = 4664 er32flash(ICH_FLASH_HSFSTS) >> 16; 4665 else 4666 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4667 4668 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4669 if (hw->mac.type >= e1000_pch_spt) 4670 ew32flash(ICH_FLASH_HSFSTS, 4671 hsflctl.regval << 16); 4672 else 4673 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4674 4675 /* Write the last 24 bits of an index within the 4676 * block into Flash Linear address field in Flash 4677 * Address. 4678 */ 4679 flash_linear_addr += (j * sector_size); 4680 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4681 4682 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4683 if (!ret_val) 4684 break; 4685 4686 /* Check if FCERR is set to 1. If 1, 4687 * clear it and try the whole sequence 4688 * a few more times else Done 4689 */ 4690 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4691 if (hsfsts.hsf_status.flcerr) 4692 /* repeat for some time before giving up */ 4693 continue; 4694 else if (!hsfsts.hsf_status.flcdone) 4695 return ret_val; 4696 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4697 } 4698 4699 return 0; 4700} 4701 4702/** 4703 * e1000_valid_led_default_ich8lan - Set the default LED settings 4704 * @hw: pointer to the HW structure 4705 * @data: Pointer to the LED settings 4706 * 4707 * Reads the LED default settings from the NVM to data. If the NVM LED 4708 * settings is all 0's or F's, set the LED default to a valid LED default 4709 * setting. 4710 **/ 4711static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4712{ 4713 s32 ret_val; 4714 4715 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4716 if (ret_val) { 4717 e_dbg("NVM Read Error\n"); 4718 return ret_val; 4719 } 4720 4721 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4722 *data = ID_LED_DEFAULT_ICH8LAN; 4723 4724 return 0; 4725} 4726 4727/** 4728 * e1000_id_led_init_pchlan - store LED configurations 4729 * @hw: pointer to the HW structure 4730 * 4731 * PCH does not control LEDs via the LEDCTL register, rather it uses 4732 * the PHY LED configuration register. 4733 * 4734 * PCH also does not have an "always on" or "always off" mode which 4735 * complicates the ID feature. Instead of using the "on" mode to indicate 4736 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4737 * use "link_up" mode. The LEDs will still ID on request if there is no 4738 * link based on logic in e1000_led_[on|off]_pchlan(). 4739 **/ 4740static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4741{ 4742 struct e1000_mac_info *mac = &hw->mac; 4743 s32 ret_val; 4744 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4745 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4746 u16 data, i, temp, shift; 4747 4748 /* Get default ID LED modes */ 4749 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4750 if (ret_val) 4751 return ret_val; 4752 4753 mac->ledctl_default = er32(LEDCTL); 4754 mac->ledctl_mode1 = mac->ledctl_default; 4755 mac->ledctl_mode2 = mac->ledctl_default; 4756 4757 for (i = 0; i < 4; i++) { 4758 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4759 shift = (i * 5); 4760 switch (temp) { 4761 case ID_LED_ON1_DEF2: 4762 case ID_LED_ON1_ON2: 4763 case ID_LED_ON1_OFF2: 4764 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4765 mac->ledctl_mode1 |= (ledctl_on << shift); 4766 break; 4767 case ID_LED_OFF1_DEF2: 4768 case ID_LED_OFF1_ON2: 4769 case ID_LED_OFF1_OFF2: 4770 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4771 mac->ledctl_mode1 |= (ledctl_off << shift); 4772 break; 4773 default: 4774 /* Do nothing */ 4775 break; 4776 } 4777 switch (temp) { 4778 case ID_LED_DEF1_ON2: 4779 case ID_LED_ON1_ON2: 4780 case ID_LED_OFF1_ON2: 4781 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4782 mac->ledctl_mode2 |= (ledctl_on << shift); 4783 break; 4784 case ID_LED_DEF1_OFF2: 4785 case ID_LED_ON1_OFF2: 4786 case ID_LED_OFF1_OFF2: 4787 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4788 mac->ledctl_mode2 |= (ledctl_off << shift); 4789 break; 4790 default: 4791 /* Do nothing */ 4792 break; 4793 } 4794 } 4795 4796 return 0; 4797} 4798 4799/** 4800 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4801 * @hw: pointer to the HW structure 4802 * 4803 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4804 * register, so the bus width is hard coded. 4805 **/ 4806static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4807{ 4808 struct e1000_bus_info *bus = &hw->bus; 4809 s32 ret_val; 4810 4811 ret_val = e1000e_get_bus_info_pcie(hw); 4812 4813 /* ICH devices are "PCI Express"-ish. They have 4814 * a configuration space, but do not contain 4815 * PCI Express Capability registers, so bus width 4816 * must be hardcoded. 4817 */ 4818 if (bus->width == e1000_bus_width_unknown) 4819 bus->width = e1000_bus_width_pcie_x1; 4820 4821 return ret_val; 4822} 4823 4824/** 4825 * e1000_reset_hw_ich8lan - Reset the hardware 4826 * @hw: pointer to the HW structure 4827 * 4828 * Does a full reset of the hardware which includes a reset of the PHY and 4829 * MAC. 4830 **/ 4831static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4832{ 4833 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4834 u16 kum_cfg; 4835 u32 ctrl, reg; 4836 s32 ret_val; 4837 4838 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4839 * on the last TLP read/write transaction when MAC is reset. 4840 */ 4841 ret_val = e1000e_disable_pcie_master(hw); 4842 if (ret_val) 4843 e_dbg("PCI-E Master disable polling has failed.\n"); 4844 4845 e_dbg("Masking off all interrupts\n"); 4846 ew32(IMC, 0xffffffff); 4847 4848 /* Disable the Transmit and Receive units. Then delay to allow 4849 * any pending transactions to complete before we hit the MAC 4850 * with the global reset. 4851 */ 4852 ew32(RCTL, 0); 4853 ew32(TCTL, E1000_TCTL_PSP); 4854 e1e_flush(); 4855 4856 usleep_range(10000, 11000); 4857 4858 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4859 if (hw->mac.type == e1000_ich8lan) { 4860 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4861 ew32(PBA, E1000_PBA_8K); 4862 /* Set Packet Buffer Size to 16k. */ 4863 ew32(PBS, E1000_PBS_16K); 4864 } 4865 4866 if (hw->mac.type == e1000_pchlan) { 4867 /* Save the NVM K1 bit setting */ 4868 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4869 if (ret_val) 4870 return ret_val; 4871 4872 if (kum_cfg & E1000_NVM_K1_ENABLE) 4873 dev_spec->nvm_k1_enabled = true; 4874 else 4875 dev_spec->nvm_k1_enabled = false; 4876 } 4877 4878 ctrl = er32(CTRL); 4879 4880 if (!hw->phy.ops.check_reset_block(hw)) { 4881 /* Full-chip reset requires MAC and PHY reset at the same 4882 * time to make sure the interface between MAC and the 4883 * external PHY is reset. 4884 */ 4885 ctrl |= E1000_CTRL_PHY_RST; 4886 4887 /* Gate automatic PHY configuration by hardware on 4888 * non-managed 82579 4889 */ 4890 if ((hw->mac.type == e1000_pch2lan) && 4891 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4892 e1000_gate_hw_phy_config_ich8lan(hw, true); 4893 } 4894 ret_val = e1000_acquire_swflag_ich8lan(hw); 4895 e_dbg("Issuing a global reset to ich8lan\n"); 4896 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4897 /* cannot issue a flush here because it hangs the hardware */ 4898 msleep(20); 4899 4900 /* Set Phy Config Counter to 50msec */ 4901 if (hw->mac.type == e1000_pch2lan) { 4902 reg = er32(FEXTNVM3); 4903 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4904 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4905 ew32(FEXTNVM3, reg); 4906 } 4907 4908 if (!ret_val) 4909 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4910 4911 if (ctrl & E1000_CTRL_PHY_RST) { 4912 ret_val = hw->phy.ops.get_cfg_done(hw); 4913 if (ret_val) 4914 return ret_val; 4915 4916 ret_val = e1000_post_phy_reset_ich8lan(hw); 4917 if (ret_val) 4918 return ret_val; 4919 } 4920 4921 /* For PCH, this write will make sure that any noise 4922 * will be detected as a CRC error and be dropped rather than show up 4923 * as a bad packet to the DMA engine. 4924 */ 4925 if (hw->mac.type == e1000_pchlan) 4926 ew32(CRC_OFFSET, 0x65656565); 4927 4928 ew32(IMC, 0xffffffff); 4929 er32(ICR); 4930 4931 reg = er32(KABGTXD); 4932 reg |= E1000_KABGTXD_BGSQLBIAS; 4933 ew32(KABGTXD, reg); 4934 4935 /* The hardware reset value of the DPG_EN bit is 1. 4936 * Clear DPG_EN to prevent unexpected autonomous power gating. 4937 */ 4938 if (hw->mac.type >= e1000_pch_ptp) { 4939 reg = er32(CTRL_EXT); 4940 reg &= ~E1000_CTRL_EXT_DPG_EN; 4941 ew32(CTRL_EXT, reg); 4942 } 4943 4944 return 0; 4945} 4946 4947/** 4948 * e1000_init_hw_ich8lan - Initialize the hardware 4949 * @hw: pointer to the HW structure 4950 * 4951 * Prepares the hardware for transmit and receive by doing the following: 4952 * - initialize hardware bits 4953 * - initialize LED identification 4954 * - setup receive address registers 4955 * - setup flow control 4956 * - setup transmit descriptors 4957 * - clear statistics 4958 **/ 4959static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4960{ 4961 struct e1000_mac_info *mac = &hw->mac; 4962 u32 ctrl_ext, txdctl, snoop, fflt_dbg; 4963 s32 ret_val; 4964 u16 i; 4965 4966 e1000_initialize_hw_bits_ich8lan(hw); 4967 ret_val = hw->phy.ops.acquire(hw); 4968 if (ret_val) 4969 return ret_val; 4970 4971 ret_val = e1000_reconfigure_k1_params(hw); 4972 hw->phy.ops.release(hw); 4973 if (ret_val) { 4974 e_dbg("Error failed to reconfigure K1 parameters\n"); 4975 return ret_val; 4976 } 4977 4978 /* Initialize identification LED */ 4979 ret_val = mac->ops.id_led_init(hw); 4980 /* An error is not fatal and we should not stop init due to this */ 4981 if (ret_val) 4982 e_dbg("Error initializing identification LED\n"); 4983 4984 /* Setup the receive address. */ 4985 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4986 4987 /* Zero out the Multicast HASH table */ 4988 e_dbg("Zeroing the MTA\n"); 4989 for (i = 0; i < mac->mta_reg_count; i++) 4990 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4991 4992 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4993 * the ME. Disable wakeup by clearing the host wakeup bit. 4994 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4995 */ 4996 if (hw->phy.type == e1000_phy_82578) { 4997 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4998 i &= ~BM_WUC_HOST_WU_BIT; 4999 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 5000 ret_val = e1000_phy_hw_reset_ich8lan(hw); 5001 if (ret_val) 5002 return ret_val; 5003 } 5004 5005 /* Setup link and flow control */ 5006 ret_val = mac->ops.setup_link(hw); 5007 5008 /* Set the transmit descriptor write-back policy for both queues */ 5009 txdctl = er32(TXDCTL(0)); 5010 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5011 E1000_TXDCTL_FULL_TX_DESC_WB); 5012 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5013 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5014 ew32(TXDCTL(0), txdctl); 5015 txdctl = er32(TXDCTL(1)); 5016 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 5017 E1000_TXDCTL_FULL_TX_DESC_WB); 5018 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 5019 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 5020 ew32(TXDCTL(1), txdctl); 5021 5022 /* ICH8 has opposite polarity of no_snoop bits. 5023 * By default, we should use snoop behavior. 5024 */ 5025 if (mac->type == e1000_ich8lan) 5026 snoop = PCIE_ICH8_SNOOP_ALL; 5027 else 5028 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 5029 e1000e_set_pcie_no_snoop(hw, snoop); 5030 5031 /* Enable workaround for packet loss issue on TGP PCH 5032 * Do not gate DMA clock from the modPHY block 5033 */ 5034 if (mac->type >= e1000_pch_tgp) { 5035 fflt_dbg = er32(FFLT_DBG); 5036 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK; 5037 ew32(FFLT_DBG, fflt_dbg); 5038 } 5039 5040 ctrl_ext = er32(CTRL_EXT); 5041 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 5042 ew32(CTRL_EXT, ctrl_ext); 5043 5044 /* Clear all of the statistics registers (clear on read). It is 5045 * important that we do this after we have tried to establish link 5046 * because the symbol error count will increment wildly if there 5047 * is no link. 5048 */ 5049 e1000_clear_hw_cntrs_ich8lan(hw); 5050 5051 return ret_val; 5052} 5053 5054/** 5055 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 5056 * @hw: pointer to the HW structure 5057 * 5058 * Sets/Clears required hardware bits necessary for correctly setting up the 5059 * hardware for transmit and receive. 5060 **/ 5061static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 5062{ 5063 u32 reg; 5064 5065 /* Extended Device Control */ 5066 reg = er32(CTRL_EXT); 5067 reg |= BIT(22); 5068 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 5069 if (hw->mac.type >= e1000_pchlan) 5070 reg |= E1000_CTRL_EXT_PHYPDEN; 5071 ew32(CTRL_EXT, reg); 5072 5073 /* Transmit Descriptor Control 0 */ 5074 reg = er32(TXDCTL(0)); 5075 reg |= BIT(22); 5076 ew32(TXDCTL(0), reg); 5077 5078 /* Transmit Descriptor Control 1 */ 5079 reg = er32(TXDCTL(1)); 5080 reg |= BIT(22); 5081 ew32(TXDCTL(1), reg); 5082 5083 /* Transmit Arbitration Control 0 */ 5084 reg = er32(TARC(0)); 5085 if (hw->mac.type == e1000_ich8lan) 5086 reg |= BIT(28) | BIT(29); 5087 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 5088 ew32(TARC(0), reg); 5089 5090 /* Transmit Arbitration Control 1 */ 5091 reg = er32(TARC(1)); 5092 if (er32(TCTL) & E1000_TCTL_MULR) 5093 reg &= ~BIT(28); 5094 else 5095 reg |= BIT(28); 5096 reg |= BIT(24) | BIT(26) | BIT(30); 5097 ew32(TARC(1), reg); 5098 5099 /* Device Status */ 5100 if (hw->mac.type == e1000_ich8lan) { 5101 reg = er32(STATUS); 5102 reg &= ~BIT(31); 5103 ew32(STATUS, reg); 5104 } 5105 5106 /* work-around descriptor data corruption issue during nfs v2 udp 5107 * traffic, just disable the nfs filtering capability 5108 */ 5109 reg = er32(RFCTL); 5110 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 5111 5112 /* Disable IPv6 extension header parsing because some malformed 5113 * IPv6 headers can hang the Rx. 5114 */ 5115 if (hw->mac.type == e1000_ich8lan) 5116 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 5117 ew32(RFCTL, reg); 5118 5119 /* Enable ECC on Lynxpoint */ 5120 if (hw->mac.type >= e1000_pch_lpt) { 5121 reg = er32(PBECCSTS); 5122 reg |= E1000_PBECCSTS_ECC_ENABLE; 5123 ew32(PBECCSTS, reg); 5124 5125 reg = er32(CTRL); 5126 reg |= E1000_CTRL_MEHE; 5127 ew32(CTRL, reg); 5128 } 5129} 5130 5131/** 5132 * e1000_setup_link_ich8lan - Setup flow control and link settings 5133 * @hw: pointer to the HW structure 5134 * 5135 * Determines which flow control settings to use, then configures flow 5136 * control. Calls the appropriate media-specific link configuration 5137 * function. Assuming the adapter has a valid link partner, a valid link 5138 * should be established. Assumes the hardware has previously been reset 5139 * and the transmitter and receiver are not enabled. 5140 **/ 5141static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 5142{ 5143 s32 ret_val; 5144 5145 if (hw->phy.ops.check_reset_block(hw)) 5146 return 0; 5147 5148 /* ICH parts do not have a word in the NVM to determine 5149 * the default flow control setting, so we explicitly 5150 * set it to full. 5151 */ 5152 if (hw->fc.requested_mode == e1000_fc_default) { 5153 /* Workaround h/w hang when Tx flow control enabled */ 5154 if (hw->mac.type == e1000_pchlan) 5155 hw->fc.requested_mode = e1000_fc_rx_pause; 5156 else 5157 hw->fc.requested_mode = e1000_fc_full; 5158 } 5159 5160 /* Save off the requested flow control mode for use later. Depending 5161 * on the link partner's capabilities, we may or may not use this mode. 5162 */ 5163 hw->fc.current_mode = hw->fc.requested_mode; 5164 5165 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 5166 5167 /* Continue to configure the copper link. */ 5168 ret_val = hw->mac.ops.setup_physical_interface(hw); 5169 if (ret_val) 5170 return ret_val; 5171 5172 ew32(FCTTV, hw->fc.pause_time); 5173 if ((hw->phy.type == e1000_phy_82578) || 5174 (hw->phy.type == e1000_phy_82579) || 5175 (hw->phy.type == e1000_phy_i217) || 5176 (hw->phy.type == e1000_phy_82577)) { 5177 ew32(FCRTV_PCH, hw->fc.refresh_time); 5178 5179 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 5180 hw->fc.pause_time); 5181 if (ret_val) 5182 return ret_val; 5183 } 5184 5185 return e1000e_set_fc_watermarks(hw); 5186} 5187 5188/** 5189 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5190 * @hw: pointer to the HW structure 5191 * 5192 * Configures the kumeran interface to the PHY to wait the appropriate time 5193 * when polling the PHY, then call the generic setup_copper_link to finish 5194 * configuring the copper link. 5195 **/ 5196static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5197{ 5198 u32 ctrl; 5199 s32 ret_val; 5200 u16 reg_data; 5201 5202 ctrl = er32(CTRL); 5203 ctrl |= E1000_CTRL_SLU; 5204 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5205 ew32(CTRL, ctrl); 5206 5207 /* Set the mac to wait the maximum time between each iteration 5208 * and increase the max iterations when polling the phy; 5209 * this fixes erroneous timeouts at 10Mbps. 5210 */ 5211 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 5212 if (ret_val) 5213 return ret_val; 5214 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5215 ®_data); 5216 if (ret_val) 5217 return ret_val; 5218 reg_data |= 0x3F; 5219 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5220 reg_data); 5221 if (ret_val) 5222 return ret_val; 5223 5224 switch (hw->phy.type) { 5225 case e1000_phy_igp_3: 5226 ret_val = e1000e_copper_link_setup_igp(hw); 5227 if (ret_val) 5228 return ret_val; 5229 break; 5230 case e1000_phy_bm: 5231 case e1000_phy_82578: 5232 ret_val = e1000e_copper_link_setup_m88(hw); 5233 if (ret_val) 5234 return ret_val; 5235 break; 5236 case e1000_phy_82577: 5237 case e1000_phy_82579: 5238 ret_val = e1000_copper_link_setup_82577(hw); 5239 if (ret_val) 5240 return ret_val; 5241 break; 5242 case e1000_phy_ife: 5243 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5244 if (ret_val) 5245 return ret_val; 5246 5247 reg_data &= ~IFE_PMC_AUTO_MDIX; 5248 5249 switch (hw->phy.mdix) { 5250 case 1: 5251 reg_data &= ~IFE_PMC_FORCE_MDIX; 5252 break; 5253 case 2: 5254 reg_data |= IFE_PMC_FORCE_MDIX; 5255 break; 5256 case 0: 5257 default: 5258 reg_data |= IFE_PMC_AUTO_MDIX; 5259 break; 5260 } 5261 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5262 if (ret_val) 5263 return ret_val; 5264 break; 5265 default: 5266 break; 5267 } 5268 5269 return e1000e_setup_copper_link(hw); 5270} 5271 5272/** 5273 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5274 * @hw: pointer to the HW structure 5275 * 5276 * Calls the PHY specific link setup function and then calls the 5277 * generic setup_copper_link to finish configuring the link for 5278 * Lynxpoint PCH devices 5279 **/ 5280static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5281{ 5282 u32 ctrl; 5283 s32 ret_val; 5284 5285 ctrl = er32(CTRL); 5286 ctrl |= E1000_CTRL_SLU; 5287 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5288 ew32(CTRL, ctrl); 5289 5290 ret_val = e1000_copper_link_setup_82577(hw); 5291 if (ret_val) 5292 return ret_val; 5293 5294 return e1000e_setup_copper_link(hw); 5295} 5296 5297/** 5298 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5299 * @hw: pointer to the HW structure 5300 * @speed: pointer to store current link speed 5301 * @duplex: pointer to store the current link duplex 5302 * 5303 * Calls the generic get_speed_and_duplex to retrieve the current link 5304 * information and then calls the Kumeran lock loss workaround for links at 5305 * gigabit speeds. 5306 **/ 5307static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5308 u16 *duplex) 5309{ 5310 s32 ret_val; 5311 5312 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5313 if (ret_val) 5314 return ret_val; 5315 5316 if ((hw->mac.type == e1000_ich8lan) && 5317 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5318 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5319 } 5320 5321 return ret_val; 5322} 5323 5324/** 5325 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5326 * @hw: pointer to the HW structure 5327 * 5328 * Work-around for 82566 Kumeran PCS lock loss: 5329 * On link status change (i.e. PCI reset, speed change) and link is up and 5330 * speed is gigabit- 5331 * 0) if workaround is optionally disabled do nothing 5332 * 1) wait 1ms for Kumeran link to come up 5333 * 2) check Kumeran Diagnostic register PCS lock loss bit 5334 * 3) if not set the link is locked (all is good), otherwise... 5335 * 4) reset the PHY 5336 * 5) repeat up to 10 times 5337 * Note: this is only called for IGP3 copper when speed is 1gb. 5338 **/ 5339static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5340{ 5341 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5342 u32 phy_ctrl; 5343 s32 ret_val; 5344 u16 i, data; 5345 bool link; 5346 5347 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5348 return 0; 5349 5350 /* Make sure link is up before proceeding. If not just return. 5351 * Attempting this while link is negotiating fouled up link 5352 * stability 5353 */ 5354 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5355 if (!link) 5356 return 0; 5357 5358 for (i = 0; i < 10; i++) { 5359 /* read once to clear */ 5360 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5361 if (ret_val) 5362 return ret_val; 5363 /* and again to get new status */ 5364 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5365 if (ret_val) 5366 return ret_val; 5367 5368 /* check for PCS lock */ 5369 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5370 return 0; 5371 5372 /* Issue PHY reset */ 5373 e1000_phy_hw_reset(hw); 5374 mdelay(5); 5375 } 5376 /* Disable GigE link negotiation */ 5377 phy_ctrl = er32(PHY_CTRL); 5378 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5379 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5380 ew32(PHY_CTRL, phy_ctrl); 5381 5382 /* Call gig speed drop workaround on Gig disable before accessing 5383 * any PHY registers 5384 */ 5385 e1000e_gig_downshift_workaround_ich8lan(hw); 5386 5387 /* unable to acquire PCS lock */ 5388 return -E1000_ERR_PHY; 5389} 5390 5391/** 5392 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5393 * @hw: pointer to the HW structure 5394 * @state: boolean value used to set the current Kumeran workaround state 5395 * 5396 * If ICH8, set the current Kumeran workaround state (enabled - true 5397 * /disabled - false). 5398 **/ 5399void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5400 bool state) 5401{ 5402 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5403 5404 if (hw->mac.type != e1000_ich8lan) { 5405 e_dbg("Workaround applies to ICH8 only.\n"); 5406 return; 5407 } 5408 5409 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5410} 5411 5412/** 5413 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5414 * @hw: pointer to the HW structure 5415 * 5416 * Workaround for 82566 power-down on D3 entry: 5417 * 1) disable gigabit link 5418 * 2) write VR power-down enable 5419 * 3) read it back 5420 * Continue if successful, else issue LCD reset and repeat 5421 **/ 5422void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5423{ 5424 u32 reg; 5425 u16 data; 5426 u8 retry = 0; 5427 5428 if (hw->phy.type != e1000_phy_igp_3) 5429 return; 5430 5431 /* Try the workaround twice (if needed) */ 5432 do { 5433 /* Disable link */ 5434 reg = er32(PHY_CTRL); 5435 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5436 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5437 ew32(PHY_CTRL, reg); 5438 5439 /* Call gig speed drop workaround on Gig disable before 5440 * accessing any PHY registers 5441 */ 5442 if (hw->mac.type == e1000_ich8lan) 5443 e1000e_gig_downshift_workaround_ich8lan(hw); 5444 5445 /* Write VR power-down enable */ 5446 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5447 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5448 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5449 5450 /* Read it back and test */ 5451 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5452 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5453 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5454 break; 5455 5456 /* Issue PHY reset and repeat at most one more time */ 5457 reg = er32(CTRL); 5458 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5459 retry++; 5460 } while (retry); 5461} 5462 5463/** 5464 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5465 * @hw: pointer to the HW structure 5466 * 5467 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5468 * LPLU, Gig disable, MDIC PHY reset): 5469 * 1) Set Kumeran Near-end loopback 5470 * 2) Clear Kumeran Near-end loopback 5471 * Should only be called for ICH8[m] devices with any 1G Phy. 5472 **/ 5473void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5474{ 5475 s32 ret_val; 5476 u16 reg_data; 5477 5478 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5479 return; 5480 5481 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5482 ®_data); 5483 if (ret_val) 5484 return; 5485 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5486 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5487 reg_data); 5488 if (ret_val) 5489 return; 5490 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5491 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5492} 5493 5494/** 5495 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5496 * @hw: pointer to the HW structure 5497 * 5498 * During S0 to Sx transition, it is possible the link remains at gig 5499 * instead of negotiating to a lower speed. Before going to Sx, set 5500 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5501 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5502 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5503 * needs to be written. 5504 * Parts that support (and are linked to a partner which support) EEE in 5505 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5506 * than 10Mbps w/o EEE. 5507 **/ 5508void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5509{ 5510 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5511 u32 phy_ctrl; 5512 s32 ret_val; 5513 5514 phy_ctrl = er32(PHY_CTRL); 5515 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5516 5517 if (hw->phy.type == e1000_phy_i217) { 5518 u16 phy_reg, device_id = hw->adapter->pdev->device; 5519 5520 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5521 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5522 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5523 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5524 (hw->mac.type >= e1000_pch_spt)) { 5525 u32 fextnvm6 = er32(FEXTNVM6); 5526 5527 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5528 } 5529 5530 ret_val = hw->phy.ops.acquire(hw); 5531 if (ret_val) 5532 goto out; 5533 5534 if (!dev_spec->eee_disable) { 5535 u16 eee_advert; 5536 5537 ret_val = 5538 e1000_read_emi_reg_locked(hw, 5539 I217_EEE_ADVERTISEMENT, 5540 &eee_advert); 5541 if (ret_val) 5542 goto release; 5543 5544 /* Disable LPLU if both link partners support 100BaseT 5545 * EEE and 100Full is advertised on both ends of the 5546 * link, and enable Auto Enable LPI since there will 5547 * be no driver to enable LPI while in Sx. 5548 */ 5549 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5550 (dev_spec->eee_lp_ability & 5551 I82579_EEE_100_SUPPORTED) && 5552 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5553 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5554 E1000_PHY_CTRL_NOND0A_LPLU); 5555 5556 /* Set Auto Enable LPI after link up */ 5557 e1e_rphy_locked(hw, 5558 I217_LPI_GPIO_CTRL, &phy_reg); 5559 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5560 e1e_wphy_locked(hw, 5561 I217_LPI_GPIO_CTRL, phy_reg); 5562 } 5563 } 5564 5565 /* For i217 Intel Rapid Start Technology support, 5566 * when the system is going into Sx and no manageability engine 5567 * is present, the driver must configure proxy to reset only on 5568 * power good. LPI (Low Power Idle) state must also reset only 5569 * on power good, as well as the MTA (Multicast table array). 5570 * The SMBus release must also be disabled on LCD reset. 5571 */ 5572 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5573 /* Enable proxy to reset only on power good. */ 5574 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5575 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5576 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5577 5578 /* Set bit enable LPI (EEE) to reset only on 5579 * power good. 5580 */ 5581 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5582 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5583 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5584 5585 /* Disable the SMB release on LCD reset. */ 5586 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5587 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5588 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5589 } 5590 5591 /* Enable MTA to reset for Intel Rapid Start Technology 5592 * Support 5593 */ 5594 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5595 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5596 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5597 5598release: 5599 hw->phy.ops.release(hw); 5600 } 5601out: 5602 ew32(PHY_CTRL, phy_ctrl); 5603 5604 if (hw->mac.type == e1000_ich8lan) 5605 e1000e_gig_downshift_workaround_ich8lan(hw); 5606 5607 if (hw->mac.type >= e1000_pchlan) { 5608 e1000_oem_bits_config_ich8lan(hw, false); 5609 5610 /* Reset PHY to activate OEM bits on 82577/8 */ 5611 if (hw->mac.type == e1000_pchlan) 5612 e1000e_phy_hw_reset_generic(hw); 5613 5614 ret_val = hw->phy.ops.acquire(hw); 5615 if (ret_val) 5616 return; 5617 e1000_write_smbus_addr(hw); 5618 hw->phy.ops.release(hw); 5619 } 5620} 5621 5622/** 5623 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5624 * @hw: pointer to the HW structure 5625 * 5626 * During Sx to S0 transitions on non-managed devices or managed devices 5627 * on which PHY resets are not blocked, if the PHY registers cannot be 5628 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5629 * the PHY. 5630 * On i217, setup Intel Rapid Start Technology. 5631 **/ 5632void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5633{ 5634 s32 ret_val; 5635 5636 if (hw->mac.type < e1000_pch2lan) 5637 return; 5638 5639 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5640 if (ret_val) { 5641 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5642 return; 5643 } 5644 5645 /* For i217 Intel Rapid Start Technology support when the system 5646 * is transitioning from Sx and no manageability engine is present 5647 * configure SMBus to restore on reset, disable proxy, and enable 5648 * the reset on MTA (Multicast table array). 5649 */ 5650 if (hw->phy.type == e1000_phy_i217) { 5651 u16 phy_reg; 5652 5653 ret_val = hw->phy.ops.acquire(hw); 5654 if (ret_val) { 5655 e_dbg("Failed to setup iRST\n"); 5656 return; 5657 } 5658 5659 /* Clear Auto Enable LPI after link up */ 5660 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5661 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5662 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5663 5664 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5665 /* Restore clear on SMB if no manageability engine 5666 * is present 5667 */ 5668 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5669 if (ret_val) 5670 goto release; 5671 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5672 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5673 5674 /* Disable Proxy */ 5675 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5676 } 5677 /* Enable reset on MTA */ 5678 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5679 if (ret_val) 5680 goto release; 5681 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5682 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5683release: 5684 if (ret_val) 5685 e_dbg("Error %d in resume workarounds\n", ret_val); 5686 hw->phy.ops.release(hw); 5687 } 5688} 5689 5690/** 5691 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5692 * @hw: pointer to the HW structure 5693 * 5694 * Return the LED back to the default configuration. 5695 **/ 5696static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5697{ 5698 if (hw->phy.type == e1000_phy_ife) 5699 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5700 5701 ew32(LEDCTL, hw->mac.ledctl_default); 5702 return 0; 5703} 5704 5705/** 5706 * e1000_led_on_ich8lan - Turn LEDs on 5707 * @hw: pointer to the HW structure 5708 * 5709 * Turn on the LEDs. 5710 **/ 5711static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5712{ 5713 if (hw->phy.type == e1000_phy_ife) 5714 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5715 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5716 5717 ew32(LEDCTL, hw->mac.ledctl_mode2); 5718 return 0; 5719} 5720 5721/** 5722 * e1000_led_off_ich8lan - Turn LEDs off 5723 * @hw: pointer to the HW structure 5724 * 5725 * Turn off the LEDs. 5726 **/ 5727static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5728{ 5729 if (hw->phy.type == e1000_phy_ife) 5730 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5731 (IFE_PSCL_PROBE_MODE | 5732 IFE_PSCL_PROBE_LEDS_OFF)); 5733 5734 ew32(LEDCTL, hw->mac.ledctl_mode1); 5735 return 0; 5736} 5737 5738/** 5739 * e1000_setup_led_pchlan - Configures SW controllable LED 5740 * @hw: pointer to the HW structure 5741 * 5742 * This prepares the SW controllable LED for use. 5743 **/ 5744static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5745{ 5746 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5747} 5748 5749/** 5750 * e1000_cleanup_led_pchlan - Restore the default LED operation 5751 * @hw: pointer to the HW structure 5752 * 5753 * Return the LED back to the default configuration. 5754 **/ 5755static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5756{ 5757 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5758} 5759 5760/** 5761 * e1000_led_on_pchlan - Turn LEDs on 5762 * @hw: pointer to the HW structure 5763 * 5764 * Turn on the LEDs. 5765 **/ 5766static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5767{ 5768 u16 data = (u16)hw->mac.ledctl_mode2; 5769 u32 i, led; 5770 5771 /* If no link, then turn LED on by setting the invert bit 5772 * for each LED that's mode is "link_up" in ledctl_mode2. 5773 */ 5774 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5775 for (i = 0; i < 3; i++) { 5776 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5777 if ((led & E1000_PHY_LED0_MODE_MASK) != 5778 E1000_LEDCTL_MODE_LINK_UP) 5779 continue; 5780 if (led & E1000_PHY_LED0_IVRT) 5781 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5782 else 5783 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5784 } 5785 } 5786 5787 return e1e_wphy(hw, HV_LED_CONFIG, data); 5788} 5789 5790/** 5791 * e1000_led_off_pchlan - Turn LEDs off 5792 * @hw: pointer to the HW structure 5793 * 5794 * Turn off the LEDs. 5795 **/ 5796static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5797{ 5798 u16 data = (u16)hw->mac.ledctl_mode1; 5799 u32 i, led; 5800 5801 /* If no link, then turn LED off by clearing the invert bit 5802 * for each LED that's mode is "link_up" in ledctl_mode1. 5803 */ 5804 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5805 for (i = 0; i < 3; i++) { 5806 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5807 if ((led & E1000_PHY_LED0_MODE_MASK) != 5808 E1000_LEDCTL_MODE_LINK_UP) 5809 continue; 5810 if (led & E1000_PHY_LED0_IVRT) 5811 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5812 else 5813 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5814 } 5815 } 5816 5817 return e1e_wphy(hw, HV_LED_CONFIG, data); 5818} 5819 5820/** 5821 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5822 * @hw: pointer to the HW structure 5823 * 5824 * Read appropriate register for the config done bit for completion status 5825 * and configure the PHY through s/w for EEPROM-less parts. 5826 * 5827 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5828 * config done bit, so only an error is logged and continues. If we were 5829 * to return with error, EEPROM-less silicon would not be able to be reset 5830 * or change link. 5831 **/ 5832static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5833{ 5834 s32 ret_val = 0; 5835 u32 bank = 0; 5836 u32 status; 5837 5838 e1000e_get_cfg_done_generic(hw); 5839 5840 /* Wait for indication from h/w that it has completed basic config */ 5841 if (hw->mac.type >= e1000_ich10lan) { 5842 e1000_lan_init_done_ich8lan(hw); 5843 } else { 5844 ret_val = e1000e_get_auto_rd_done(hw); 5845 if (ret_val) { 5846 /* When auto config read does not complete, do not 5847 * return with an error. This can happen in situations 5848 * where there is no eeprom and prevents getting link. 5849 */ 5850 e_dbg("Auto Read Done did not complete\n"); 5851 ret_val = 0; 5852 } 5853 } 5854 5855 /* Clear PHY Reset Asserted bit */ 5856 status = er32(STATUS); 5857 if (status & E1000_STATUS_PHYRA) 5858 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5859 else 5860 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5861 5862 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5863 if (hw->mac.type <= e1000_ich9lan) { 5864 if (!(er32(EECD) & E1000_EECD_PRES) && 5865 (hw->phy.type == e1000_phy_igp_3)) { 5866 e1000e_phy_init_script_igp3(hw); 5867 } 5868 } else { 5869 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5870 /* Maybe we should do a basic PHY config */ 5871 e_dbg("EEPROM not present\n"); 5872 ret_val = -E1000_ERR_CONFIG; 5873 } 5874 } 5875 5876 return ret_val; 5877} 5878 5879/** 5880 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5881 * @hw: pointer to the HW structure 5882 * 5883 * In the case of a PHY power down to save power, or to turn off link during a 5884 * driver unload, or wake on lan is not enabled, remove the link. 5885 **/ 5886static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5887{ 5888 /* If the management interface is not enabled, then power down */ 5889 if (!(hw->mac.ops.check_mng_mode(hw) || 5890 hw->phy.ops.check_reset_block(hw))) 5891 e1000_power_down_phy_copper(hw); 5892} 5893 5894/** 5895 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5896 * @hw: pointer to the HW structure 5897 * 5898 * Clears hardware counters specific to the silicon family and calls 5899 * clear_hw_cntrs_generic to clear all general purpose counters. 5900 **/ 5901static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5902{ 5903 u16 phy_data; 5904 s32 ret_val; 5905 5906 e1000e_clear_hw_cntrs_base(hw); 5907 5908 er32(ALGNERRC); 5909 er32(RXERRC); 5910 er32(TNCRS); 5911 er32(CEXTERR); 5912 er32(TSCTC); 5913 er32(TSCTFC); 5914 5915 er32(MGTPRC); 5916 er32(MGTPDC); 5917 er32(MGTPTC); 5918 5919 er32(IAC); 5920 er32(ICRXOC); 5921 5922 /* Clear PHY statistics registers */ 5923 if ((hw->phy.type == e1000_phy_82578) || 5924 (hw->phy.type == e1000_phy_82579) || 5925 (hw->phy.type == e1000_phy_i217) || 5926 (hw->phy.type == e1000_phy_82577)) { 5927 ret_val = hw->phy.ops.acquire(hw); 5928 if (ret_val) 5929 return; 5930 ret_val = hw->phy.ops.set_page(hw, 5931 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5932 if (ret_val) 5933 goto release; 5934 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5935 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5936 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5937 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5938 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5939 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5940 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5941 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5942 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5943 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5944 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5945 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5946 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5947 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5948release: 5949 hw->phy.ops.release(hw); 5950 } 5951} 5952 5953static const struct e1000_mac_operations ich8_mac_ops = { 5954 /* check_mng_mode dependent on mac type */ 5955 .check_for_link = e1000_check_for_copper_link_ich8lan, 5956 /* cleanup_led dependent on mac type */ 5957 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5958 .get_bus_info = e1000_get_bus_info_ich8lan, 5959 .set_lan_id = e1000_set_lan_id_single_port, 5960 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5961 /* led_on dependent on mac type */ 5962 /* led_off dependent on mac type */ 5963 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5964 .reset_hw = e1000_reset_hw_ich8lan, 5965 .init_hw = e1000_init_hw_ich8lan, 5966 .setup_link = e1000_setup_link_ich8lan, 5967 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5968 /* id_led_init dependent on mac type */ 5969 .config_collision_dist = e1000e_config_collision_dist_generic, 5970 .rar_set = e1000e_rar_set_generic, 5971 .rar_get_count = e1000e_rar_get_count_generic, 5972}; 5973 5974static const struct e1000_phy_operations ich8_phy_ops = { 5975 .acquire = e1000_acquire_swflag_ich8lan, 5976 .check_reset_block = e1000_check_reset_block_ich8lan, 5977 .commit = NULL, 5978 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5979 .get_cable_length = e1000e_get_cable_length_igp_2, 5980 .read_reg = e1000e_read_phy_reg_igp, 5981 .release = e1000_release_swflag_ich8lan, 5982 .reset = e1000_phy_hw_reset_ich8lan, 5983 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5984 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5985 .write_reg = e1000e_write_phy_reg_igp, 5986}; 5987 5988static const struct e1000_nvm_operations ich8_nvm_ops = { 5989 .acquire = e1000_acquire_nvm_ich8lan, 5990 .read = e1000_read_nvm_ich8lan, 5991 .release = e1000_release_nvm_ich8lan, 5992 .reload = e1000e_reload_nvm_generic, 5993 .update = e1000_update_nvm_checksum_ich8lan, 5994 .valid_led_default = e1000_valid_led_default_ich8lan, 5995 .validate = e1000_validate_nvm_checksum_ich8lan, 5996 .write = e1000_write_nvm_ich8lan, 5997}; 5998 5999static const struct e1000_nvm_operations spt_nvm_ops = { 6000 .acquire = e1000_acquire_nvm_ich8lan, 6001 .release = e1000_release_nvm_ich8lan, 6002 .read = e1000_read_nvm_spt, 6003 .update = e1000_update_nvm_checksum_spt, 6004 .reload = e1000e_reload_nvm_generic, 6005 .valid_led_default = e1000_valid_led_default_ich8lan, 6006 .validate = e1000_validate_nvm_checksum_ich8lan, 6007 .write = e1000_write_nvm_ich8lan, 6008}; 6009 6010const struct e1000_info e1000_ich8_info = { 6011 .mac = e1000_ich8lan, 6012 .flags = FLAG_HAS_WOL 6013 | FLAG_IS_ICH 6014 | FLAG_HAS_CTRLEXT_ON_LOAD 6015 | FLAG_HAS_AMT 6016 | FLAG_HAS_FLASH 6017 | FLAG_APME_IN_WUC, 6018 .pba = 8, 6019 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 6020 .get_variants = e1000_get_variants_ich8lan, 6021 .mac_ops = &ich8_mac_ops, 6022 .phy_ops = &ich8_phy_ops, 6023 .nvm_ops = &ich8_nvm_ops, 6024}; 6025 6026const struct e1000_info e1000_ich9_info = { 6027 .mac = e1000_ich9lan, 6028 .flags = FLAG_HAS_JUMBO_FRAMES 6029 | FLAG_IS_ICH 6030 | FLAG_HAS_WOL 6031 | FLAG_HAS_CTRLEXT_ON_LOAD 6032 | FLAG_HAS_AMT 6033 | FLAG_HAS_FLASH 6034 | FLAG_APME_IN_WUC, 6035 .pba = 18, 6036 .max_hw_frame_size = DEFAULT_JUMBO, 6037 .get_variants = e1000_get_variants_ich8lan, 6038 .mac_ops = &ich8_mac_ops, 6039 .phy_ops = &ich8_phy_ops, 6040 .nvm_ops = &ich8_nvm_ops, 6041}; 6042 6043const struct e1000_info e1000_ich10_info = { 6044 .mac = e1000_ich10lan, 6045 .flags = FLAG_HAS_JUMBO_FRAMES 6046 | FLAG_IS_ICH 6047 | FLAG_HAS_WOL 6048 | FLAG_HAS_CTRLEXT_ON_LOAD 6049 | FLAG_HAS_AMT 6050 | FLAG_HAS_FLASH 6051 | FLAG_APME_IN_WUC, 6052 .pba = 18, 6053 .max_hw_frame_size = DEFAULT_JUMBO, 6054 .get_variants = e1000_get_variants_ich8lan, 6055 .mac_ops = &ich8_mac_ops, 6056 .phy_ops = &ich8_phy_ops, 6057 .nvm_ops = &ich8_nvm_ops, 6058}; 6059 6060const struct e1000_info e1000_pch_info = { 6061 .mac = e1000_pchlan, 6062 .flags = FLAG_IS_ICH 6063 | FLAG_HAS_WOL 6064 | FLAG_HAS_CTRLEXT_ON_LOAD 6065 | FLAG_HAS_AMT 6066 | FLAG_HAS_FLASH 6067 | FLAG_HAS_JUMBO_FRAMES 6068 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 6069 | FLAG_APME_IN_WUC, 6070 .flags2 = FLAG2_HAS_PHY_STATS, 6071 .pba = 26, 6072 .max_hw_frame_size = 4096, 6073 .get_variants = e1000_get_variants_ich8lan, 6074 .mac_ops = &ich8_mac_ops, 6075 .phy_ops = &ich8_phy_ops, 6076 .nvm_ops = &ich8_nvm_ops, 6077}; 6078 6079const struct e1000_info e1000_pch2_info = { 6080 .mac = e1000_pch2lan, 6081 .flags = FLAG_IS_ICH 6082 | FLAG_HAS_WOL 6083 | FLAG_HAS_HW_TIMESTAMP 6084 | FLAG_HAS_CTRLEXT_ON_LOAD 6085 | FLAG_HAS_AMT 6086 | FLAG_HAS_FLASH 6087 | FLAG_HAS_JUMBO_FRAMES 6088 | FLAG_APME_IN_WUC, 6089 .flags2 = FLAG2_HAS_PHY_STATS 6090 | FLAG2_HAS_EEE 6091 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6092 .pba = 26, 6093 .max_hw_frame_size = 9022, 6094 .get_variants = e1000_get_variants_ich8lan, 6095 .mac_ops = &ich8_mac_ops, 6096 .phy_ops = &ich8_phy_ops, 6097 .nvm_ops = &ich8_nvm_ops, 6098}; 6099 6100const struct e1000_info e1000_pch_lpt_info = { 6101 .mac = e1000_pch_lpt, 6102 .flags = FLAG_IS_ICH 6103 | FLAG_HAS_WOL 6104 | FLAG_HAS_HW_TIMESTAMP 6105 | FLAG_HAS_CTRLEXT_ON_LOAD 6106 | FLAG_HAS_AMT 6107 | FLAG_HAS_FLASH 6108 | FLAG_HAS_JUMBO_FRAMES 6109 | FLAG_APME_IN_WUC, 6110 .flags2 = FLAG2_HAS_PHY_STATS 6111 | FLAG2_HAS_EEE 6112 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6113 .pba = 26, 6114 .max_hw_frame_size = 9022, 6115 .get_variants = e1000_get_variants_ich8lan, 6116 .mac_ops = &ich8_mac_ops, 6117 .phy_ops = &ich8_phy_ops, 6118 .nvm_ops = &ich8_nvm_ops, 6119}; 6120 6121const struct e1000_info e1000_pch_spt_info = { 6122 .mac = e1000_pch_spt, 6123 .flags = FLAG_IS_ICH 6124 | FLAG_HAS_WOL 6125 | FLAG_HAS_HW_TIMESTAMP 6126 | FLAG_HAS_CTRLEXT_ON_LOAD 6127 | FLAG_HAS_AMT 6128 | FLAG_HAS_FLASH 6129 | FLAG_HAS_JUMBO_FRAMES 6130 | FLAG_APME_IN_WUC, 6131 .flags2 = FLAG2_HAS_PHY_STATS 6132 | FLAG2_HAS_EEE, 6133 .pba = 26, 6134 .max_hw_frame_size = 9022, 6135 .get_variants = e1000_get_variants_ich8lan, 6136 .mac_ops = &ich8_mac_ops, 6137 .phy_ops = &ich8_phy_ops, 6138 .nvm_ops = &spt_nvm_ops, 6139}; 6140 6141const struct e1000_info e1000_pch_cnp_info = { 6142 .mac = e1000_pch_cnp, 6143 .flags = FLAG_IS_ICH 6144 | FLAG_HAS_WOL 6145 | FLAG_HAS_HW_TIMESTAMP 6146 | FLAG_HAS_CTRLEXT_ON_LOAD 6147 | FLAG_HAS_AMT 6148 | FLAG_HAS_FLASH 6149 | FLAG_HAS_JUMBO_FRAMES 6150 | FLAG_APME_IN_WUC, 6151 .flags2 = FLAG2_HAS_PHY_STATS 6152 | FLAG2_HAS_EEE, 6153 .pba = 26, 6154 .max_hw_frame_size = 9022, 6155 .get_variants = e1000_get_variants_ich8lan, 6156 .mac_ops = &ich8_mac_ops, 6157 .phy_ops = &ich8_phy_ops, 6158 .nvm_ops = &spt_nvm_ops, 6159}; 6160 6161const struct e1000_info e1000_pch_tgp_info = { 6162 .mac = e1000_pch_tgp, 6163 .flags = FLAG_IS_ICH 6164 | FLAG_HAS_WOL 6165 | FLAG_HAS_HW_TIMESTAMP 6166 | FLAG_HAS_CTRLEXT_ON_LOAD 6167 | FLAG_HAS_AMT 6168 | FLAG_HAS_FLASH 6169 | FLAG_HAS_JUMBO_FRAMES 6170 | FLAG_APME_IN_WUC, 6171 .flags2 = FLAG2_HAS_PHY_STATS 6172 | FLAG2_HAS_EEE, 6173 .pba = 26, 6174 .max_hw_frame_size = 9022, 6175 .get_variants = e1000_get_variants_ich8lan, 6176 .mac_ops = &ich8_mac_ops, 6177 .phy_ops = &ich8_phy_ops, 6178 .nvm_ops = &spt_nvm_ops, 6179}; 6180 6181const struct e1000_info e1000_pch_adp_info = { 6182 .mac = e1000_pch_adp, 6183 .flags = FLAG_IS_ICH 6184 | FLAG_HAS_WOL 6185 | FLAG_HAS_HW_TIMESTAMP 6186 | FLAG_HAS_CTRLEXT_ON_LOAD 6187 | FLAG_HAS_AMT 6188 | FLAG_HAS_FLASH 6189 | FLAG_HAS_JUMBO_FRAMES 6190 | FLAG_APME_IN_WUC, 6191 .flags2 = FLAG2_HAS_PHY_STATS 6192 | FLAG2_HAS_EEE, 6193 .pba = 26, 6194 .max_hw_frame_size = 9022, 6195 .get_variants = e1000_get_variants_ich8lan, 6196 .mac_ops = &ich8_mac_ops, 6197 .phy_ops = &ich8_phy_ops, 6198 .nvm_ops = &spt_nvm_ops, 6199}; 6200 6201const struct e1000_info e1000_pch_mtp_info = { 6202 .mac = e1000_pch_mtp, 6203 .flags = FLAG_IS_ICH 6204 | FLAG_HAS_WOL 6205 | FLAG_HAS_HW_TIMESTAMP 6206 | FLAG_HAS_CTRLEXT_ON_LOAD 6207 | FLAG_HAS_AMT 6208 | FLAG_HAS_FLASH 6209 | FLAG_HAS_JUMBO_FRAMES 6210 | FLAG_APME_IN_WUC, 6211 .flags2 = FLAG2_HAS_PHY_STATS 6212 | FLAG2_HAS_EEE, 6213 .pba = 26, 6214 .max_hw_frame_size = 9022, 6215 .get_variants = e1000_get_variants_ich8lan, 6216 .mac_ops = &ich8_mac_ops, 6217 .phy_ops = &ich8_phy_ops, 6218 .nvm_ops = &spt_nvm_ops, 6219};
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