hinic3_nic_io.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
  3
  4#ifndef _HINIC3_NIC_IO_H_
  5#define _HINIC3_NIC_IO_H_
  6
  7#include <linux/bitfield.h>
  8
  9#include "hinic3_wq.h"
 10
 11struct hinic3_nic_dev;
 12
 13#define HINIC3_SQ_WQEBB_SHIFT      4
 14#define HINIC3_RQ_WQEBB_SHIFT      3
 15#define HINIC3_SQ_WQEBB_SIZE       BIT(HINIC3_SQ_WQEBB_SHIFT)
 16
 17/* ******************** RQ_CTRL ******************** */
 18enum hinic3_rq_wqe_type {
 19	HINIC3_NORMAL_RQ_WQE = 1,
 20};
 21
 22/* ******************** SQ_CTRL ******************** */
 23#define HINIC3_TX_MSS_DEFAULT  0x3E00
 24#define HINIC3_TX_MSS_MIN      0x50
 25#define HINIC3_MAX_SQ_SGE      18
 26
 27struct hinic3_io_queue {
 28	struct hinic3_wq  wq;
 29	u8                owner;
 30	u16               q_id;
 31	u16               msix_entry_idx;
 32	u8 __iomem        *db_addr;
 33	u16               *cons_idx_addr;
 34} ____cacheline_aligned;
 35
 36static inline u16 hinic3_get_sq_local_ci(const struct hinic3_io_queue *sq)
 37{
 38	const struct hinic3_wq *wq = &sq->wq;
 39
 40	return wq->cons_idx & wq->idx_mask;
 41}
 42
 43static inline u16 hinic3_get_sq_local_pi(const struct hinic3_io_queue *sq)
 44{
 45	const struct hinic3_wq *wq = &sq->wq;
 46
 47	return wq->prod_idx & wq->idx_mask;
 48}
 49
 50static inline u16 hinic3_get_sq_hw_ci(const struct hinic3_io_queue *sq)
 51{
 52	const struct hinic3_wq *wq = &sq->wq;
 53
 54	return READ_ONCE(*sq->cons_idx_addr) & wq->idx_mask;
 55}
 56
 57/* ******************** DB INFO ******************** */
 58#define DB_INFO_QID_MASK    GENMASK(12, 0)
 59#define DB_INFO_CFLAG_MASK  BIT(23)
 60#define DB_INFO_COS_MASK    GENMASK(26, 24)
 61#define DB_INFO_TYPE_MASK   GENMASK(31, 27)
 62#define DB_INFO_SET(val, member)  \
 63	FIELD_PREP(DB_INFO_##member##_MASK, val)
 64
 65#define DB_PI_LOW_MASK   0xFFU
 66#define DB_PI_HIGH_MASK  0xFFU
 67#define DB_PI_HI_SHIFT   8
 68#define DB_PI_LOW(pi)    ((pi) & DB_PI_LOW_MASK)
 69#define DB_PI_HIGH(pi)   (((pi) >> DB_PI_HI_SHIFT) & DB_PI_HIGH_MASK)
 70#define DB_ADDR(q, pi)   ((u64 __iomem *)((q)->db_addr) + DB_PI_LOW(pi))
 71#define DB_SRC_TYPE      1
 72
 73/* CFLAG_DATA_PATH */
 74#define DB_CFLAG_DP_SQ   0
 75#define DB_CFLAG_DP_RQ   1
 76
 77struct hinic3_nic_db {
 78	__le32 db_info;
 79	__le32 pi_hi;
 80};
 81
 82static inline void hinic3_write_db(struct hinic3_io_queue *queue, int cos,
 83				   u8 cflag, u16 pi)
 84{
 85	struct hinic3_nic_db db;
 86
 87	db.db_info =
 88		cpu_to_le32(DB_INFO_SET(DB_SRC_TYPE, TYPE) |
 89			    DB_INFO_SET(cflag, CFLAG) |
 90			    DB_INFO_SET(cos, COS) |
 91			    DB_INFO_SET(queue->q_id, QID));
 92	db.pi_hi = cpu_to_le32(DB_PI_HIGH(pi));
 93
 94	writeq(*((u64 *)&db), DB_ADDR(queue, pi));
 95}
 96
 97struct hinic3_dyna_qp_params {
 98	u16                    num_qps;
 99	u32                    sq_depth;
100	u32                    rq_depth;
101
102	struct hinic3_io_queue *sqs;
103	struct hinic3_io_queue *rqs;
104};
105
106struct hinic3_nic_io {
107	struct hinic3_io_queue *sq;
108	struct hinic3_io_queue *rq;
109
110	u16                    num_qps;
111	u16                    max_qps;
112
113	/* Base address for consumer index of all tx queues. Each queue is
114	 * given a full cache line to hold its consumer index. HW updates
115	 * current consumer index as it consumes tx WQEs.
116	 */
117	void                   *ci_vaddr_base;
118	dma_addr_t             ci_dma_base;
119
120	u8 __iomem             *sqs_db_addr;
121	u8 __iomem             *rqs_db_addr;
122
123	u16                    rx_buf_len;
124	u64                    feature_cap;
125};
126
127int hinic3_init_nic_io(struct hinic3_nic_dev *nic_dev);
128void hinic3_free_nic_io(struct hinic3_nic_dev *nic_dev);
129
130int hinic3_init_nicio_res(struct hinic3_nic_dev *nic_dev);
131void hinic3_free_nicio_res(struct hinic3_nic_dev *nic_dev);
132
133int hinic3_alloc_qps(struct hinic3_nic_dev *nic_dev,
134		     struct hinic3_dyna_qp_params *qp_params);
135void hinic3_free_qps(struct hinic3_nic_dev *nic_dev,
136		     struct hinic3_dyna_qp_params *qp_params);
137void hinic3_init_qps(struct hinic3_nic_dev *nic_dev,
138		     struct hinic3_dyna_qp_params *qp_params);
139void hinic3_uninit_qps(struct hinic3_nic_dev *nic_dev,
140		       struct hinic3_dyna_qp_params *qp_params);
141
142int hinic3_init_qp_ctxts(struct hinic3_nic_dev *nic_dev);
143void hinic3_free_qp_ctxts(struct hinic3_nic_dev *nic_dev);
144
145#endif