hinic3_hw_intf.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
  3
  4#ifndef _HINIC3_HW_INTF_H_
  5#define _HINIC3_HW_INTF_H_
  6
  7#include <linux/bits.h>
  8#include <linux/types.h>
  9
 10#define MGMT_MSG_CMD_OP_SET   1
 11#define MGMT_MSG_CMD_OP_GET   0
 12
 13#define MGMT_STATUS_PF_SET_VF_ALREADY  0x4
 14#define MGMT_STATUS_EXIST              0x6
 15#define MGMT_STATUS_CMD_UNSUPPORTED    0xFF
 16
 17#define MGMT_MSG_POLLING_TIMEOUT 0
 18
 19struct mgmt_msg_head {
 20	u8 status;
 21	u8 version;
 22	u8 rsvd0[6];
 23};
 24
 25struct mgmt_msg_params {
 26	const void  *buf_in;
 27	u32         in_size;
 28	void        *buf_out;
 29	u32         expected_out_size;
 30	u32         timeout_ms;
 31};
 32
 33/* CMDQ MODULE_TYPE */
 34enum mgmt_mod_type {
 35	/* HW communication module */
 36	MGMT_MOD_COMM   = 0,
 37	/* L2NIC module */
 38	MGMT_MOD_L2NIC  = 1,
 39	/* Configuration module */
 40	MGMT_MOD_CFGM   = 7,
 41	MGMT_MOD_HILINK = 14,
 42};
 43
 44static inline void mgmt_msg_params_init_default(struct mgmt_msg_params *msg_params,
 45						void *inout_buf, u32 buf_size)
 46{
 47	msg_params->buf_in = inout_buf;
 48	msg_params->buf_out = inout_buf;
 49	msg_params->in_size = buf_size;
 50	msg_params->expected_out_size = buf_size;
 51	msg_params->timeout_ms = 0;
 52}
 53
 54enum cfg_cmd {
 55	CFG_CMD_GET_DEV_CAP = 0,
 56};
 57
 58/* Device capabilities, defined by hw */
 59struct cfg_cmd_dev_cap {
 60	struct mgmt_msg_head head;
 61
 62	u16                  func_id;
 63	u16                  rsvd1;
 64
 65	/* Public resources */
 66	u8                   host_id;
 67	u8                   ep_id;
 68	u8                   er_id;
 69	u8                   port_id;
 70
 71	u16                  host_total_func;
 72	u8                   host_pf_num;
 73	u8                   pf_id_start;
 74	u16                  host_vf_num;
 75	u16                  vf_id_start;
 76	u8                   host_oq_id_mask_val;
 77	u8                   timer_en;
 78	u8                   host_valid_bitmap;
 79	u8                   rsvd_host;
 80
 81	u16                  svc_cap_en;
 82	u16                  max_vf;
 83	u8                   flexq_en;
 84	u8                   valid_cos_bitmap;
 85	u8                   port_cos_valid_bitmap;
 86	u8                   rsvd2[45];
 87
 88	/* l2nic */
 89	u16                  nic_max_sq_id;
 90	u16                  nic_max_rq_id;
 91	u16                  nic_default_num_queues;
 92
 93	u8                   rsvd3[250];
 94};
 95
 96/* COMM Commands between Driver to fw */
 97enum comm_cmd {
 98	/* Commands for clearing FLR and resources */
 99	COMM_CMD_FUNC_RESET              = 0,
100	COMM_CMD_FEATURE_NEGO            = 1,
101	COMM_CMD_FLUSH_DOORBELL          = 2,
102	COMM_CMD_START_FLUSH             = 3,
103	COMM_CMD_GET_GLOBAL_ATTR         = 5,
104	COMM_CMD_SET_FUNC_SVC_USED_STATE = 7,
105
106	/* Driver Configuration Commands */
107	COMM_CMD_SET_CMDQ_CTXT           = 20,
108	COMM_CMD_SET_VAT                 = 21,
109	COMM_CMD_CFG_PAGESIZE            = 22,
110	COMM_CMD_CFG_MSIX_CTRL_REG       = 23,
111	COMM_CMD_SET_CEQ_CTRL_REG        = 24,
112	COMM_CMD_SET_DMA_ATTR            = 25,
113};
114
115struct comm_cmd_cfg_msix_ctrl_reg {
116	struct mgmt_msg_head head;
117	u16                  func_id;
118	u8                   opcode;
119	u8                   rsvd1;
120	u16                  msix_index;
121	u8                   pending_cnt;
122	u8                   coalesce_timer_cnt;
123	u8                   resend_timer_cnt;
124	u8                   lli_timer_cnt;
125	u8                   lli_credit_cnt;
126	u8                   rsvd2[5];
127};
128
129enum comm_func_reset_bits {
130	COMM_FUNC_RESET_BIT_FLUSH        = BIT(0),
131	COMM_FUNC_RESET_BIT_MQM          = BIT(1),
132	COMM_FUNC_RESET_BIT_SMF          = BIT(2),
133	COMM_FUNC_RESET_BIT_PF_BW_CFG    = BIT(3),
134
135	COMM_FUNC_RESET_BIT_COMM         = BIT(10),
136	/* clear mbox and aeq, The COMM_FUNC_RESET_BIT_COMM bit must be set */
137	COMM_FUNC_RESET_BIT_COMM_MGMT_CH = BIT(11),
138	/* clear cmdq and ceq, The COMM_FUNC_RESET_BIT_COMM bit must be set */
139	COMM_FUNC_RESET_BIT_COMM_CMD_CH  = BIT(12),
140	COMM_FUNC_RESET_BIT_NIC          = BIT(13),
141};
142
143#define COMM_FUNC_RESET_FLAG \
144	(COMM_FUNC_RESET_BIT_COMM | COMM_FUNC_RESET_BIT_COMM_CMD_CH | \
145	 COMM_FUNC_RESET_BIT_FLUSH | COMM_FUNC_RESET_BIT_MQM | \
146	 COMM_FUNC_RESET_BIT_SMF | COMM_FUNC_RESET_BIT_PF_BW_CFG)
147
148struct comm_cmd_func_reset {
149	struct mgmt_msg_head head;
150	u16                  func_id;
151	u16                  rsvd1[3];
152	u64                  reset_flag;
153};
154
155#define COMM_MAX_FEATURE_QWORD  4
156struct comm_cmd_feature_nego {
157	struct mgmt_msg_head head;
158	u16                  func_id;
159	u8                   opcode;
160	u8                   rsvd;
161	u64                  s_feature[COMM_MAX_FEATURE_QWORD];
162};
163
164struct comm_global_attr {
165	u8  max_host_num;
166	u8  max_pf_num;
167	u16 vf_id_start;
168	/* for api cmd to mgmt cpu */
169	u8  mgmt_host_node_id;
170	u8  cmdq_num;
171	u8  rsvd1[34];
172};
173
174struct comm_cmd_get_glb_attr {
175	struct mgmt_msg_head    head;
176	struct comm_global_attr attr;
177};
178
179enum comm_func_svc_type {
180	COMM_FUNC_SVC_T_COMM = 0,
181	COMM_FUNC_SVC_T_NIC  = 1,
182};
183
184struct comm_cmd_set_func_svc_used_state {
185	struct mgmt_msg_head head;
186	u16                  func_id;
187	u16                  svc_type;
188	u8                   used_state;
189	u8                   rsvd[35];
190};
191
192struct comm_cmd_set_dma_attr {
193	struct mgmt_msg_head head;
194	u16                  func_id;
195	u8                   entry_idx;
196	u8                   st;
197	u8                   at;
198	u8                   ph;
199	u8                   no_snooping;
200	u8                   tph_en;
201	u32                  resv1;
202};
203
204struct comm_cmd_set_ceq_ctrl_reg {
205	struct mgmt_msg_head head;
206	u16                  func_id;
207	u16                  q_id;
208	u32                  ctrl0;
209	u32                  ctrl1;
210	u32                  rsvd1;
211};
212
213struct comm_cmd_cfg_wq_page_size {
214	struct mgmt_msg_head head;
215	u16                  func_id;
216	u8                   opcode;
217	/* real_size=4KB*2^page_size, range(0~20) must be checked by driver */
218	u8                   page_size;
219	u32                  rsvd1;
220};
221
222struct comm_cmd_set_root_ctxt {
223	struct mgmt_msg_head head;
224	u16                  func_id;
225	u8                   set_cmdq_depth;
226	u8                   cmdq_depth;
227	u16                  rx_buf_sz;
228	u8                   lro_en;
229	u8                   rsvd1;
230	u16                  sq_depth;
231	u16                  rq_depth;
232	u64                  rsvd2;
233};
234
235struct comm_cmdq_ctxt_info {
236	__le64 curr_wqe_page_pfn;
237	__le64 wq_block_pfn;
238};
239
240struct comm_cmd_set_cmdq_ctxt {
241	struct mgmt_msg_head       head;
242	u16                        func_id;
243	u8                         cmdq_id;
244	u8                         rsvd1[5];
245	struct comm_cmdq_ctxt_info ctxt;
246};
247
248struct comm_cmd_clear_resource {
249	struct mgmt_msg_head head;
250	u16                  func_id;
251	u16                  rsvd1[3];
252};
253
254/* Services supported by HW. HW uses these values when delivering events.
255 * HW supports multiple services that are not yet supported by driver
256 * (e.g. RoCE).
257 */
258enum hinic3_service_type {
259	HINIC3_SERVICE_T_NIC = 0,
260	/* MAX is only used by SW for array sizes. */
261	HINIC3_SERVICE_T_MAX = 1,
262};
263
264#endif