hinic_hw_qp_ctxt.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Huawei HiNIC PCI Express Linux driver
  4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
  5 */
  6
  7#ifndef HINIC_HW_QP_CTXT_H
  8#define HINIC_HW_QP_CTXT_H
  9
 10#include <linux/types.h>
 11
 12#include "hinic_hw_cmdq.h"
 13
 14#define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT       13
 15#define HINIC_SQ_CTXT_CEQ_ATTR_EN_SHIFT                 23
 16
 17#define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK        0x3FF
 18#define HINIC_SQ_CTXT_CEQ_ATTR_EN_MASK                  0x1
 19
 20#define HINIC_SQ_CTXT_CEQ_ATTR_SET(val, member)         \
 21	(((u32)(val) & HINIC_SQ_CTXT_CEQ_ATTR_##member##_MASK) \
 22	 << HINIC_SQ_CTXT_CEQ_ATTR_##member##_SHIFT)
 23
 24#define HINIC_SQ_CTXT_CI_IDX_SHIFT                      11
 25#define HINIC_SQ_CTXT_CI_WRAPPED_SHIFT                  23
 26
 27#define HINIC_SQ_CTXT_CI_IDX_MASK                       0xFFF
 28#define HINIC_SQ_CTXT_CI_WRAPPED_MASK                   0x1
 29
 30#define HINIC_SQ_CTXT_CI_SET(val, member)               \
 31	(((u32)(val) & HINIC_SQ_CTXT_CI_##member##_MASK) \
 32	 << HINIC_SQ_CTXT_CI_##member##_SHIFT)
 33
 34#define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT              0
 35#define HINIC_SQ_CTXT_WQ_PAGE_PI_SHIFT                  20
 36
 37#define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_MASK               0xFFFFF
 38#define HINIC_SQ_CTXT_WQ_PAGE_PI_MASK                   0xFFF
 39
 40#define HINIC_SQ_CTXT_WQ_PAGE_SET(val, member)          \
 41	(((u32)(val) & HINIC_SQ_CTXT_WQ_PAGE_##member##_MASK) \
 42	 << HINIC_SQ_CTXT_WQ_PAGE_##member##_SHIFT)
 43
 44#define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT        0
 45#define HINIC_SQ_CTXT_PREF_CACHE_MAX_SHIFT              14
 46#define HINIC_SQ_CTXT_PREF_CACHE_MIN_SHIFT              25
 47
 48#define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_MASK         0x3FFF
 49#define HINIC_SQ_CTXT_PREF_CACHE_MAX_MASK               0x7FF
 50#define HINIC_SQ_CTXT_PREF_CACHE_MIN_MASK               0x7F
 51
 52#define HINIC_SQ_CTXT_PREF_WQ_HI_PFN_SHIFT              0
 53#define HINIC_SQ_CTXT_PREF_CI_SHIFT                     20
 54
 55#define HINIC_SQ_CTXT_PREF_WQ_HI_PFN_MASK               0xFFFFF
 56#define HINIC_SQ_CTXT_PREF_CI_MASK                      0xFFF
 57
 58#define HINIC_SQ_CTXT_PREF_SET(val, member)             \
 59	(((u32)(val) & HINIC_SQ_CTXT_PREF_##member##_MASK) \
 60	 << HINIC_SQ_CTXT_PREF_##member##_SHIFT)
 61
 62#define HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT             0
 63
 64#define HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_MASK              0x7FFFFF
 65
 66#define HINIC_SQ_CTXT_WQ_BLOCK_SET(val, member)         \
 67	(((u32)(val) & HINIC_SQ_CTXT_WQ_BLOCK_##member##_MASK) \
 68	 << HINIC_SQ_CTXT_WQ_BLOCK_##member##_SHIFT)
 69
 70#define HINIC_RQ_CTXT_CEQ_ATTR_EN_SHIFT                 0
 71#define HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_SHIFT            1
 72
 73#define HINIC_RQ_CTXT_CEQ_ATTR_EN_MASK                  0x1
 74#define HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_MASK             0x1
 75
 76#define HINIC_RQ_CTXT_CEQ_ATTR_SET(val, member)         \
 77	(((u32)(val) & HINIC_RQ_CTXT_CEQ_ATTR_##member##_MASK) \
 78	 << HINIC_RQ_CTXT_CEQ_ATTR_##member##_SHIFT)
 79
 80#define HINIC_RQ_CTXT_PI_IDX_SHIFT                      0
 81#define HINIC_RQ_CTXT_PI_INTR_SHIFT                     22
 82
 83#define HINIC_RQ_CTXT_PI_IDX_MASK                       0xFFF
 84#define HINIC_RQ_CTXT_PI_INTR_MASK                      0x3FF
 85
 86#define HINIC_RQ_CTXT_PI_SET(val, member)               \
 87	(((u32)(val) & HINIC_RQ_CTXT_PI_##member##_MASK) << \
 88	 HINIC_RQ_CTXT_PI_##member##_SHIFT)
 89
 90#define HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT              0
 91#define HINIC_RQ_CTXT_WQ_PAGE_CI_SHIFT                  20
 92
 93#define HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_MASK               0xFFFFF
 94#define HINIC_RQ_CTXT_WQ_PAGE_CI_MASK                   0xFFF
 95
 96#define HINIC_RQ_CTXT_WQ_PAGE_SET(val, member)          \
 97	(((u32)(val) & HINIC_RQ_CTXT_WQ_PAGE_##member##_MASK) << \
 98	 HINIC_RQ_CTXT_WQ_PAGE_##member##_SHIFT)
 99
100#define HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT        0
101#define HINIC_RQ_CTXT_PREF_CACHE_MAX_SHIFT              14
102#define HINIC_RQ_CTXT_PREF_CACHE_MIN_SHIFT              25
103
104#define HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_MASK         0x3FFF
105#define HINIC_RQ_CTXT_PREF_CACHE_MAX_MASK               0x7FF
106#define HINIC_RQ_CTXT_PREF_CACHE_MIN_MASK               0x7F
107
108#define HINIC_RQ_CTXT_PREF_WQ_HI_PFN_SHIFT              0
109#define HINIC_RQ_CTXT_PREF_CI_SHIFT                     20
110
111#define HINIC_RQ_CTXT_PREF_WQ_HI_PFN_MASK               0xFFFFF
112#define HINIC_RQ_CTXT_PREF_CI_MASK                      0xFFF
113
114#define HINIC_RQ_CTXT_PREF_SET(val, member)             \
115	(((u32)(val) & HINIC_RQ_CTXT_PREF_##member##_MASK) << \
116	 HINIC_RQ_CTXT_PREF_##member##_SHIFT)
117
118#define HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT             0
119
120#define HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_MASK              0x7FFFFF
121
122#define HINIC_RQ_CTXT_WQ_BLOCK_SET(val, member)         \
123	(((u32)(val) & HINIC_RQ_CTXT_WQ_BLOCK_##member##_MASK) << \
124	 HINIC_RQ_CTXT_WQ_BLOCK_##member##_SHIFT)
125
126#define HINIC_SQ_CTXT_SIZE(num_sqs) (sizeof(struct hinic_qp_ctxt_header) \
127				     + (num_sqs) * sizeof(struct hinic_sq_ctxt))
128
129#define HINIC_RQ_CTXT_SIZE(num_rqs) (sizeof(struct hinic_qp_ctxt_header) \
130				     + (num_rqs) * sizeof(struct hinic_rq_ctxt))
131
132#define HINIC_WQ_PAGE_PFN_SHIFT         12
133#define HINIC_WQ_BLOCK_PFN_SHIFT        9
134
135#define HINIC_WQ_PAGE_PFN(page_addr)    ((page_addr) >> HINIC_WQ_PAGE_PFN_SHIFT)
136#define HINIC_WQ_BLOCK_PFN(page_addr)   ((page_addr) >> \
137					 HINIC_WQ_BLOCK_PFN_SHIFT)
138
139#define HINIC_Q_CTXT_MAX                \
140		((HINIC_CMDQ_BUF_SIZE - sizeof(struct hinic_qp_ctxt_header)) \
141		 / sizeof(struct hinic_sq_ctxt))
142
143enum hinic_qp_ctxt_type {
144	HINIC_QP_CTXT_TYPE_SQ,
145	HINIC_QP_CTXT_TYPE_RQ
146};
147
148struct hinic_qp_ctxt_header {
149	u16     num_queues;
150	u16     queue_type;
151	u32     addr_offset;
152};
153
154struct hinic_sq_ctxt {
155	u32     ceq_attr;
156
157	u32     ci_wrapped;
158
159	u32     wq_hi_pfn_pi;
160	u32     wq_lo_pfn;
161
162	u32     pref_cache;
163	u32     pref_wrapped;
164	u32     pref_wq_hi_pfn_ci;
165	u32     pref_wq_lo_pfn;
166
167	u32     rsvd0;
168	u32     rsvd1;
169
170	u32     wq_block_hi_pfn;
171	u32     wq_block_lo_pfn;
172};
173
174struct hinic_rq_ctxt {
175	u32     ceq_attr;
176
177	u32     pi_intr_attr;
178
179	u32     wq_hi_pfn_ci;
180	u32     wq_lo_pfn;
181
182	u32     pref_cache;
183	u32     pref_wrapped;
184
185	u32     pref_wq_hi_pfn_ci;
186	u32     pref_wq_lo_pfn;
187
188	u32     pi_paddr_hi;
189	u32     pi_paddr_lo;
190
191	u32     wq_block_hi_pfn;
192	u32     wq_block_lo_pfn;
193};
194
195struct hinic_clean_queue_ctxt {
196	struct hinic_qp_ctxt_header	cmdq_hdr;
197	u32				ctxt_size;
198};
199
200struct hinic_sq_ctxt_block {
201	struct hinic_qp_ctxt_header hdr;
202	struct hinic_sq_ctxt sq_ctxt[HINIC_Q_CTXT_MAX];
203};
204
205struct hinic_rq_ctxt_block {
206	struct hinic_qp_ctxt_header hdr;
207	struct hinic_rq_ctxt rq_ctxt[HINIC_Q_CTXT_MAX];
208};
209
210#endif