hinic_hw_csr.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Huawei HiNIC PCI Express Linux driver
  4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
  5 */
  6
  7#ifndef HINIC_HW_CSR_H
  8#define HINIC_HW_CSR_H
  9
 10/* HW interface registers */
 11#define HINIC_CSR_FUNC_ATTR0_ADDR                       0x0
 12#define HINIC_CSR_FUNC_ATTR1_ADDR                       0x4
 13#define HINIC_CSR_FUNC_ATTR2_ADDR			0x8
 14#define HINIC_CSR_FUNC_ATTR4_ADDR                       0x10
 15#define HINIC_CSR_FUNC_ATTR5_ADDR                       0x14
 16
 17#define HINIC_DMA_ATTR_BASE                             0xC80
 18#define HINIC_ELECTION_BASE                             0x4200
 19
 20#define HINIC_DMA_ATTR_STRIDE                           0x4
 21#define HINIC_CSR_DMA_ATTR_ADDR(idx)                    \
 22	(HINIC_DMA_ATTR_BASE + (idx) * HINIC_DMA_ATTR_STRIDE)
 23
 24#define HINIC_PPF_ELECTION_STRIDE                       0x4
 25
 26#define HINIC_CSR_PPF_ELECTION_ADDR(idx)                \
 27	(HINIC_ELECTION_BASE +  (idx) * HINIC_PPF_ELECTION_STRIDE)
 28
 29/* API CMD registers */
 30#define HINIC_CSR_API_CMD_BASE                          0xF000
 31
 32#define HINIC_CSR_API_CMD_STRIDE                        0x100
 33
 34#define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx)       \
 35	(HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
 36
 37#define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx)       \
 38	(HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
 39
 40#define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx)           \
 41	(HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
 42
 43#define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx)           \
 44	(HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
 45
 46#define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx)     \
 47	(HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
 48
 49#define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx)          \
 50	(HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
 51
 52#define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx)            \
 53	(HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
 54
 55#define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx)           \
 56	(HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
 57
 58#define HINIC_CSR_API_CMD_STATUS_ADDR(idx)              \
 59	(HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
 60
 61/* MSI-X registers */
 62#define HINIC_CSR_MSIX_CTRL_BASE                        0x2000
 63#define HINIC_CSR_MSIX_CNT_BASE                         0x2004
 64
 65#define HINIC_CSR_MSIX_STRIDE                           0x8
 66
 67#define HINIC_CSR_MSIX_CTRL_ADDR(idx)                   \
 68	(HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
 69
 70#define HINIC_CSR_MSIX_CNT_ADDR(idx)                    \
 71	(HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
 72
 73/* EQ registers */
 74#define HINIC_AEQ_MTT_OFF_BASE_ADDR                     0x200
 75#define HINIC_CEQ_MTT_OFF_BASE_ADDR                     0x400
 76
 77#define HINIC_EQ_MTT_OFF_STRIDE                         0x40
 78
 79#define HINIC_CSR_AEQ_MTT_OFF(id)                       \
 80	(HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
 81
 82#define HINIC_CSR_CEQ_MTT_OFF(id)                       \
 83	(HINIC_CEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
 84
 85#define HINIC_CSR_EQ_PAGE_OFF_STRIDE                    8
 86
 87#define HINIC_CSR_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)    \
 88	(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
 89	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
 90
 91#define HINIC_CSR_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)    \
 92	(HINIC_CSR_CEQ_MTT_OFF(q_id) +          \
 93	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
 94
 95#define HINIC_CSR_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)    \
 96	(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
 97	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
 98
 99#define HINIC_CSR_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)    \
100	(HINIC_CSR_CEQ_MTT_OFF(q_id) +  \
101	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
102
103#define HINIC_AEQ_CTRL_0_ADDR_BASE                      0xE00
104#define HINIC_AEQ_CTRL_1_ADDR_BASE                      0xE04
105#define HINIC_AEQ_CONS_IDX_ADDR_BASE                    0xE08
106#define HINIC_AEQ_PROD_IDX_ADDR_BASE                    0xE0C
107
108#define HINIC_CEQ_CTRL_0_ADDR_BASE                      0x1000
109#define HINIC_CEQ_CTRL_1_ADDR_BASE                      0x1004
110#define HINIC_CEQ_CONS_IDX_ADDR_BASE                    0x1008
111#define HINIC_CEQ_PROD_IDX_ADDR_BASE                    0x100C
112
113#define HINIC_EQ_OFF_STRIDE                             0x80
114
115#define HINIC_CSR_AEQ_CTRL_0_ADDR(idx)                  \
116	(HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
117
118#define HINIC_CSR_AEQ_CTRL_1_ADDR(idx)                  \
119	(HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
120
121#define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx)                \
122	(HINIC_AEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
123
124#define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx)                \
125	(HINIC_AEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
126
127#define HINIC_CSR_CEQ_CTRL_0_ADDR(idx)                  \
128	(HINIC_CEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
129
130#define HINIC_CSR_CEQ_CTRL_1_ADDR(idx)                  \
131	(HINIC_CEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
132
133#define HINIC_CSR_CEQ_CONS_IDX_ADDR(idx)                \
134	(HINIC_CEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
135
136#define HINIC_CSR_CEQ_PROD_IDX_ADDR(idx)                \
137	(HINIC_CEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
138
139#endif