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hclgevf_main.c
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linux-6.19.14/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
1// SPDX-License-Identifier: GPL-2.0+ 2// Copyright (c) 2016-2017 Hisilicon Limited. 3 4#include <linux/etherdevice.h> 5#include <linux/iopoll.h> 6#include <net/rtnetlink.h> 7#include "hclgevf_cmd.h" 8#include "hclgevf_main.h" 9#include "hclgevf_regs.h" 10#include "hclge_mbx.h" 11#include "hnae3.h" 12#include "hclgevf_devlink.h" 13#include "hclge_comm_rss.h" 14#include "hclgevf_trace.h" 15 16#define HCLGEVF_NAME "hclgevf" 17 18#define HCLGEVF_RESET_MAX_FAIL_CNT 5 19 20static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 21static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 22 unsigned long delay); 23 24static struct hnae3_ae_algo ae_algovf; 25 26static struct workqueue_struct *hclgevf_wq; 27 28static const struct pci_device_id ae_algovf_pci_tbl[] = { 29 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 30 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 31 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 32 /* required last entry */ 33 {0, } 34}; 35 36MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 37 38/* hclgevf_cmd_send - send command to command queue 39 * @hw: pointer to the hw struct 40 * @desc: prefilled descriptor for describing the command 41 * @num : the number of descriptors to be sent 42 * 43 * This is the main send command for command queue, it 44 * sends the queue, cleans the queue, etc 45 */ 46int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 47{ 48 return hclge_comm_cmd_send(&hw->hw, desc, num); 49} 50 51static void hclgevf_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 52 int num, bool is_special) 53{ 54 int i; 55 56 trace_hclge_vf_cmd_send(hw, desc, 0, num); 57 58 if (is_special) 59 return; 60 61 for (i = 1; i < num; i++) 62 trace_hclge_vf_cmd_send(hw, &desc[i], i, num); 63} 64 65static void hclgevf_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, 66 int num, bool is_special) 67{ 68 int i; 69 70 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 71 return; 72 73 trace_hclge_vf_cmd_get(hw, desc, 0, num); 74 75 if (is_special) 76 return; 77 78 for (i = 1; i < num; i++) 79 trace_hclge_vf_cmd_get(hw, &desc[i], i, num); 80} 81 82static const struct hclge_comm_cmq_ops hclgevf_cmq_ops = { 83 .trace_cmd_send = hclgevf_trace_cmd_send, 84 .trace_cmd_get = hclgevf_trace_cmd_get, 85}; 86 87void hclgevf_arq_init(struct hclgevf_dev *hdev) 88{ 89 struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 90 91 spin_lock(&cmdq->crq.lock); 92 /* initialize the pointers of async rx queue of mailbox */ 93 hdev->arq.hdev = hdev; 94 hdev->arq.head = 0; 95 hdev->arq.tail = 0; 96 atomic_set(&hdev->arq.count, 0); 97 spin_unlock(&cmdq->crq.lock); 98} 99 100struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 101{ 102 if (!handle->client) 103 return container_of(handle, struct hclgevf_dev, nic); 104 else if (handle->client->type == HNAE3_CLIENT_ROCE) 105 return container_of(handle, struct hclgevf_dev, roce); 106 else 107 return container_of(handle, struct hclgevf_dev, nic); 108} 109 110static void hclgevf_update_stats(struct hnae3_handle *handle) 111{ 112 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 113 int status; 114 115 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 116 if (status) 117 dev_err(&hdev->pdev->dev, 118 "VF update of TQPS stats fail, status = %d.\n", 119 status); 120} 121 122static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 123{ 124 if (strset == ETH_SS_TEST) 125 return -EOPNOTSUPP; 126 else if (strset == ETH_SS_STATS) 127 return hclge_comm_tqps_get_sset_count(handle); 128 129 return 0; 130} 131 132static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 133 u8 **data) 134{ 135 if (strset == ETH_SS_STATS) 136 hclge_comm_tqps_get_strings(handle, data); 137} 138 139static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 140{ 141 hclge_comm_tqps_get_stats(handle, data); 142} 143 144static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 145 u8 subcode) 146{ 147 if (msg) { 148 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 149 msg->code = code; 150 msg->subcode = subcode; 151 } 152} 153 154static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 155{ 156 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 157 u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 158 struct hclge_basic_info *basic_info; 159 struct hclge_vf_to_pf_msg send_msg; 160 unsigned long caps; 161 int status; 162 163 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 164 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 165 sizeof(resp_msg)); 166 if (status) { 167 dev_err(&hdev->pdev->dev, 168 "failed to get basic info from pf, ret = %d", status); 169 return status; 170 } 171 172 basic_info = (struct hclge_basic_info *)resp_msg; 173 174 hdev->hw_tc_map = basic_info->hw_tc_map; 175 hdev->mbx_api_version = le16_to_cpu(basic_info->mbx_api_version); 176 caps = le32_to_cpu(basic_info->pf_caps); 177 if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 178 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 179 180 return 0; 181} 182 183static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 184{ 185 struct hnae3_handle *nic = &hdev->nic; 186 struct hclge_vf_to_pf_msg send_msg; 187 u8 resp_msg; 188 int ret; 189 190 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 191 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 192 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 193 sizeof(u8)); 194 if (ret) { 195 dev_err(&hdev->pdev->dev, 196 "VF request to get port based vlan state failed %d", 197 ret); 198 return ret; 199 } 200 201 nic->port_base_vlan_state = resp_msg; 202 203 return 0; 204} 205 206static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 207{ 208#define HCLGEVF_TQPS_RSS_INFO_LEN 6 209 210 struct hclge_mbx_vf_queue_info *queue_info; 211 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 212 struct hclge_vf_to_pf_msg send_msg; 213 int status; 214 215 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 216 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 217 HCLGEVF_TQPS_RSS_INFO_LEN); 218 if (status) { 219 dev_err(&hdev->pdev->dev, 220 "VF request to get tqp info from PF failed %d", 221 status); 222 return status; 223 } 224 225 queue_info = (struct hclge_mbx_vf_queue_info *)resp_msg; 226 hdev->num_tqps = le16_to_cpu(queue_info->num_tqps); 227 hdev->rss_size_max = le16_to_cpu(queue_info->rss_size); 228 hdev->rx_buf_len = le16_to_cpu(queue_info->rx_buf_len); 229 230 return 0; 231} 232 233static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 234{ 235#define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 236 237 struct hclge_mbx_vf_queue_depth *queue_depth; 238 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 239 struct hclge_vf_to_pf_msg send_msg; 240 int ret; 241 242 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 243 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 244 HCLGEVF_TQPS_DEPTH_INFO_LEN); 245 if (ret) { 246 dev_err(&hdev->pdev->dev, 247 "VF request to get tqp depth info from PF failed %d", 248 ret); 249 return ret; 250 } 251 252 queue_depth = (struct hclge_mbx_vf_queue_depth *)resp_msg; 253 hdev->num_tx_desc = le16_to_cpu(queue_depth->num_tx_desc); 254 hdev->num_rx_desc = le16_to_cpu(queue_depth->num_rx_desc); 255 256 return 0; 257} 258 259static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 260{ 261 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 262 struct hclge_vf_to_pf_msg send_msg; 263 u16 qid_in_pf = 0; 264 u8 resp_data[2]; 265 int ret; 266 267 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 268 *(__le16 *)send_msg.data = cpu_to_le16(queue_id); 269 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 270 sizeof(resp_data)); 271 if (!ret) 272 qid_in_pf = le16_to_cpu(*(__le16 *)resp_data); 273 274 return qid_in_pf; 275} 276 277static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 278{ 279 struct hclge_vf_to_pf_msg send_msg; 280 u8 resp_msg[2]; 281 int ret; 282 283 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 284 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 285 sizeof(resp_msg)); 286 if (ret) { 287 dev_err(&hdev->pdev->dev, 288 "VF request to get the pf port media type failed %d", 289 ret); 290 return ret; 291 } 292 293 hdev->hw.mac.media_type = resp_msg[0]; 294 hdev->hw.mac.module_type = resp_msg[1]; 295 296 return 0; 297} 298 299static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 300{ 301 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 302 struct hclge_comm_tqp *tqp; 303 int i; 304 305 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 306 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 307 if (!hdev->htqp) 308 return -ENOMEM; 309 310 tqp = hdev->htqp; 311 312 for (i = 0; i < hdev->num_tqps; i++) { 313 tqp->dev = &hdev->pdev->dev; 314 tqp->index = i; 315 316 tqp->q.ae_algo = &ae_algovf; 317 tqp->q.buf_size = hdev->rx_buf_len; 318 tqp->q.tx_desc_num = hdev->num_tx_desc; 319 tqp->q.rx_desc_num = hdev->num_rx_desc; 320 321 /* need an extended offset to configure queues >= 322 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 323 */ 324 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 325 tqp->q.io_base = hdev->hw.hw.io_base + 326 HCLGEVF_TQP_REG_OFFSET + 327 i * HCLGEVF_TQP_REG_SIZE; 328 else 329 tqp->q.io_base = hdev->hw.hw.io_base + 330 HCLGEVF_TQP_REG_OFFSET + 331 HCLGEVF_TQP_EXT_REG_OFFSET + 332 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 333 HCLGEVF_TQP_REG_SIZE; 334 335 /* when device supports tx push and has device memory, 336 * the queue can execute push mode or doorbell mode on 337 * device memory. 338 */ 339 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 340 tqp->q.mem_base = hdev->hw.hw.mem_base + 341 HCLGEVF_TQP_MEM_OFFSET(hdev, i); 342 343 tqp++; 344 } 345 346 return 0; 347} 348 349static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 350{ 351 struct hnae3_handle *nic = &hdev->nic; 352 struct hnae3_knic_private_info *kinfo; 353 u16 new_tqps = hdev->num_tqps; 354 unsigned int i; 355 u8 num_tc = 0; 356 357 kinfo = &nic->kinfo; 358 kinfo->num_tx_desc = hdev->num_tx_desc; 359 kinfo->num_rx_desc = hdev->num_rx_desc; 360 kinfo->rx_buf_len = hdev->rx_buf_len; 361 for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++) 362 if (hdev->hw_tc_map & BIT(i)) 363 num_tc++; 364 365 num_tc = num_tc ? num_tc : 1; 366 kinfo->tc_info.num_tc = num_tc; 367 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 368 new_tqps = kinfo->rss_size * num_tc; 369 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 370 371 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 372 sizeof(struct hnae3_queue *), GFP_KERNEL); 373 if (!kinfo->tqp) 374 return -ENOMEM; 375 376 for (i = 0; i < hdev->num_tqps; i++) { 377 hdev->htqp[i].q.handle = &hdev->nic; 378 hdev->htqp[i].q.tqp_index = i; 379 kinfo->tqp[i] = &hdev->htqp[i].q; 380 } 381 382 /* after init the max rss_size and tqps, adjust the default tqp numbers 383 * and rss size with the actual vector numbers 384 */ 385 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 386 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 387 kinfo->rss_size); 388 389 return 0; 390} 391 392static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 393{ 394 struct hclge_vf_to_pf_msg send_msg; 395 int status; 396 397 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 398 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 399 if (status) 400 dev_err(&hdev->pdev->dev, 401 "VF failed to fetch link status(%d) from PF", status); 402} 403 404void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 405{ 406 struct hnae3_handle *rhandle = &hdev->roce; 407 struct hnae3_handle *handle = &hdev->nic; 408 struct hnae3_client *rclient; 409 struct hnae3_client *client; 410 411 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 412 return; 413 414 client = handle->client; 415 rclient = hdev->roce_client; 416 417 link_state = 418 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 419 if (link_state != hdev->hw.mac.link) { 420 hdev->hw.mac.link = link_state; 421 client->ops->link_status_change(handle, !!link_state); 422 if (rclient && rclient->ops->link_status_change) 423 rclient->ops->link_status_change(rhandle, !!link_state); 424 } 425 426 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 427} 428 429static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 430{ 431#define HCLGEVF_ADVERTISING 0 432#define HCLGEVF_SUPPORTED 1 433 434 struct hclge_vf_to_pf_msg send_msg; 435 436 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 437 send_msg.data[0] = HCLGEVF_ADVERTISING; 438 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 439 send_msg.data[0] = HCLGEVF_SUPPORTED; 440 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 441} 442 443static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 444{ 445 struct hnae3_handle *nic = &hdev->nic; 446 int ret; 447 448 nic->ae_algo = &ae_algovf; 449 nic->pdev = hdev->pdev; 450 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 451 MAX_NUMNODES); 452 nic->flags |= HNAE3_SUPPORT_VF; 453 nic->kinfo.io_base = hdev->hw.hw.io_base; 454 455 ret = hclgevf_knic_setup(hdev); 456 if (ret) 457 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 458 ret); 459 return ret; 460} 461 462static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 463{ 464 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 465 dev_warn(&hdev->pdev->dev, 466 "vector(vector_id %d) has been freed.\n", vector_id); 467 return; 468 } 469 470 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 471 hdev->num_msi_left += 1; 472 hdev->num_msi_used -= 1; 473} 474 475static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 476 struct hnae3_vector_info *vector_info) 477{ 478 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 479 struct hnae3_vector_info *vector = vector_info; 480 int alloc = 0; 481 int i, j; 482 483 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 484 vector_num = min(hdev->num_msi_left, vector_num); 485 486 for (j = 0; j < vector_num; j++) { 487 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 488 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 489 vector->vector = pci_irq_vector(hdev->pdev, i); 490 vector->io_addr = hdev->hw.hw.io_base + 491 HCLGEVF_VECTOR_REG_BASE + 492 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 493 hdev->vector_status[i] = 0; 494 hdev->vector_irq[i] = vector->vector; 495 496 vector++; 497 alloc++; 498 499 break; 500 } 501 } 502 } 503 hdev->num_msi_left -= alloc; 504 hdev->num_msi_used += alloc; 505 506 return alloc; 507} 508 509static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 510{ 511 int i; 512 513 for (i = 0; i < hdev->num_msi; i++) 514 if (vector == hdev->vector_irq[i]) 515 return i; 516 517 return -EINVAL; 518} 519 520/* for revision 0x20, vf shared the same rss config with pf */ 521static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 522{ 523#define HCLGEVF_RSS_MBX_RESP_LEN 8 524 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 525 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 526 struct hclge_vf_to_pf_msg send_msg; 527 u16 msg_num, hash_key_index; 528 u8 index; 529 int ret; 530 531 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 532 msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 533 HCLGEVF_RSS_MBX_RESP_LEN; 534 for (index = 0; index < msg_num; index++) { 535 send_msg.data[0] = index; 536 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 537 HCLGEVF_RSS_MBX_RESP_LEN); 538 if (ret) { 539 dev_err(&hdev->pdev->dev, 540 "VF get rss hash key from PF failed, ret=%d", 541 ret); 542 return ret; 543 } 544 545 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 546 if (index == msg_num - 1) 547 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 548 &resp_msg[0], 549 HCLGE_COMM_RSS_KEY_SIZE - hash_key_index); 550 else 551 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 552 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 553 } 554 555 return 0; 556} 557 558static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 559 u8 *hfunc) 560{ 561 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 562 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 563 int ret; 564 565 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 566 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 567 } else { 568 if (hfunc) 569 *hfunc = ETH_RSS_HASH_TOP; 570 if (key) { 571 ret = hclgevf_get_rss_hash_key(hdev); 572 if (ret) 573 return ret; 574 memcpy(key, rss_cfg->rss_hash_key, 575 HCLGE_COMM_RSS_KEY_SIZE); 576 } 577 } 578 579 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 580 hdev->ae_dev->dev_specs.rss_ind_tbl_size); 581 582 return 0; 583} 584 585static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 586 const u8 *key, const u8 hfunc) 587{ 588 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 589 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 590 int ret, i; 591 592 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 593 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, 594 hfunc); 595 if (ret) 596 return ret; 597 } 598 599 /* update the shadow RSS table with user specified qids */ 600 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 601 rss_cfg->rss_indirection_tbl[i] = indir[i]; 602 603 /* update the hardware */ 604 return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 605 rss_cfg->rss_indirection_tbl); 606} 607 608static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 609 const struct ethtool_rxfh_fields *nfc) 610{ 611 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 612 int ret; 613 614 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 615 return -EOPNOTSUPP; 616 617 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 618 &hdev->rss_cfg, nfc); 619 if (ret) 620 dev_err(&hdev->pdev->dev, 621 "failed to set rss tuple, ret = %d.\n", ret); 622 623 return ret; 624} 625 626static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 627 struct ethtool_rxfh_fields *nfc) 628{ 629 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 630 u8 tuple_sets; 631 int ret; 632 633 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 634 return -EOPNOTSUPP; 635 636 nfc->data = 0; 637 638 ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type, 639 &tuple_sets); 640 if (ret || !tuple_sets) 641 return ret; 642 643 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 644 645 return 0; 646} 647 648static int hclgevf_get_tc_size(struct hnae3_handle *handle) 649{ 650 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 651 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 652 653 return rss_cfg->rss_size; 654} 655 656static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 657 int vector_id, 658 struct hnae3_ring_chain_node *ring_chain) 659{ 660 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 661 struct hclge_vf_to_pf_msg send_msg; 662 struct hnae3_ring_chain_node *node; 663 int status; 664 int i = 0; 665 666 memset(&send_msg, 0, sizeof(send_msg)); 667 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 668 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 669 send_msg.vector_id = vector_id; 670 671 for (node = ring_chain; node; node = node->next) { 672 send_msg.param[i].ring_type = 673 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 674 675 send_msg.param[i].tqp_index = node->tqp_index; 676 send_msg.param[i].int_gl_index = 677 hnae3_get_field(node->int_gl_idx, 678 HNAE3_RING_GL_IDX_M, 679 HNAE3_RING_GL_IDX_S); 680 681 i++; 682 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 683 send_msg.ring_num = i; 684 685 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 686 NULL, 0); 687 if (status) { 688 dev_err(&hdev->pdev->dev, 689 "Map TQP fail, status is %d.\n", 690 status); 691 return status; 692 } 693 i = 0; 694 } 695 } 696 697 return 0; 698} 699 700static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 701 struct hnae3_ring_chain_node *ring_chain) 702{ 703 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 704 int vector_id; 705 706 vector_id = hclgevf_get_vector_index(hdev, vector); 707 if (vector_id < 0) { 708 dev_err(&handle->pdev->dev, 709 "Get vector index fail. ret =%d\n", vector_id); 710 return vector_id; 711 } 712 713 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 714} 715 716static int hclgevf_unmap_ring_from_vector( 717 struct hnae3_handle *handle, 718 int vector, 719 struct hnae3_ring_chain_node *ring_chain) 720{ 721 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 722 int ret, vector_id; 723 724 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 725 return 0; 726 727 vector_id = hclgevf_get_vector_index(hdev, vector); 728 if (vector_id < 0) { 729 dev_err(&handle->pdev->dev, 730 "Get vector index fail. ret =%d\n", vector_id); 731 return vector_id; 732 } 733 734 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 735 if (ret) 736 dev_err(&handle->pdev->dev, 737 "Unmap ring from vector fail. vector=%d, ret =%d\n", 738 vector_id, 739 ret); 740 741 return ret; 742} 743 744static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 745{ 746 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 747 int vector_id; 748 749 vector_id = hclgevf_get_vector_index(hdev, vector); 750 if (vector_id < 0) { 751 dev_err(&handle->pdev->dev, 752 "hclgevf_put_vector get vector index fail. ret =%d\n", 753 vector_id); 754 return vector_id; 755 } 756 757 hclgevf_free_vector(hdev, vector_id); 758 759 return 0; 760} 761 762static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 763 bool en_uc_pmc, bool en_mc_pmc, 764 bool en_bc_pmc) 765{ 766 struct hnae3_handle *handle = &hdev->nic; 767 struct hclge_vf_to_pf_msg send_msg; 768 int ret; 769 770 memset(&send_msg, 0, sizeof(send_msg)); 771 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 772 send_msg.en_bc = en_bc_pmc ? 1 : 0; 773 send_msg.en_uc = en_uc_pmc ? 1 : 0; 774 send_msg.en_mc = en_mc_pmc ? 1 : 0; 775 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 776 &handle->priv_flags) ? 1 : 0; 777 778 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 779 if (ret) 780 dev_err(&hdev->pdev->dev, 781 "Set promisc mode fail, status is %d.\n", ret); 782 783 return ret; 784} 785 786static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 787 bool en_mc_pmc) 788{ 789 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 790 bool en_bc_pmc; 791 792 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 793 794 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 795 en_bc_pmc); 796} 797 798static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 799{ 800 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 801 802 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 803 hclgevf_task_schedule(hdev, 0); 804} 805 806static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 807{ 808 struct hnae3_handle *handle = &hdev->nic; 809 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 810 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 811 int ret; 812 813 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 814 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 815 if (!ret) 816 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 817 } 818} 819 820static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 821 u16 stream_id, bool enable) 822{ 823 struct hclgevf_cfg_com_tqp_queue_cmd *req; 824 struct hclge_desc desc; 825 826 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 827 828 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 829 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 830 req->stream_id = cpu_to_le16(stream_id); 831 if (enable) 832 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 833 834 return hclgevf_cmd_send(&hdev->hw, &desc, 1); 835} 836 837static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 838{ 839 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 840 int ret; 841 u16 i; 842 843 for (i = 0; i < handle->kinfo.num_tqps; i++) { 844 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 845 if (ret) 846 return ret; 847 } 848 849 return 0; 850} 851 852static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 853{ 854 struct hclge_vf_to_pf_msg send_msg; 855 u8 host_mac[ETH_ALEN]; 856 int status; 857 858 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 859 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 860 ETH_ALEN); 861 if (status) { 862 dev_err(&hdev->pdev->dev, 863 "fail to get VF MAC from host %d", status); 864 return status; 865 } 866 867 ether_addr_copy(p, host_mac); 868 869 return 0; 870} 871 872static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 873{ 874 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 875 u8 host_mac_addr[ETH_ALEN]; 876 877 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 878 return; 879 880 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 881 if (hdev->has_pf_mac) 882 ether_addr_copy(p, host_mac_addr); 883 else 884 ether_addr_copy(p, hdev->hw.mac.mac_addr); 885} 886 887static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 888 bool is_first) 889{ 890 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 891 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 892 struct hclge_vf_to_pf_msg send_msg; 893 u8 *new_mac_addr = (u8 *)p; 894 int status; 895 896 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 897 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 898 ether_addr_copy(send_msg.data, new_mac_addr); 899 if (is_first && !hdev->has_pf_mac) 900 eth_zero_addr(&send_msg.data[ETH_ALEN]); 901 else 902 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 903 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 904 if (!status) 905 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 906 907 return status; 908} 909 910static struct hclgevf_mac_addr_node * 911hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 912{ 913 struct hclgevf_mac_addr_node *mac_node, *tmp; 914 915 list_for_each_entry_safe(mac_node, tmp, list, node) 916 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 917 return mac_node; 918 919 return NULL; 920} 921 922static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 923 enum HCLGEVF_MAC_NODE_STATE state) 924{ 925 switch (state) { 926 /* from set_rx_mode or tmp_add_list */ 927 case HCLGEVF_MAC_TO_ADD: 928 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 929 mac_node->state = HCLGEVF_MAC_ACTIVE; 930 break; 931 /* only from set_rx_mode */ 932 case HCLGEVF_MAC_TO_DEL: 933 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 934 list_del(&mac_node->node); 935 kfree(mac_node); 936 } else { 937 mac_node->state = HCLGEVF_MAC_TO_DEL; 938 } 939 break; 940 /* only from tmp_add_list, the mac_node->state won't be 941 * HCLGEVF_MAC_ACTIVE 942 */ 943 case HCLGEVF_MAC_ACTIVE: 944 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 945 mac_node->state = HCLGEVF_MAC_ACTIVE; 946 break; 947 } 948} 949 950static int hclgevf_update_mac_list(struct hnae3_handle *handle, 951 enum HCLGEVF_MAC_NODE_STATE state, 952 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 953 const unsigned char *addr) 954{ 955 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 956 struct hclgevf_mac_addr_node *mac_node; 957 struct list_head *list; 958 959 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 960 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 961 962 spin_lock_bh(&hdev->mac_table.mac_list_lock); 963 964 /* if the mac addr is already in the mac list, no need to add a new 965 * one into it, just check the mac addr state, convert it to a new 966 * state, or just remove it, or do nothing. 967 */ 968 mac_node = hclgevf_find_mac_node(list, addr); 969 if (mac_node) { 970 hclgevf_update_mac_node(mac_node, state); 971 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 972 return 0; 973 } 974 /* if this address is never added, unnecessary to delete */ 975 if (state == HCLGEVF_MAC_TO_DEL) { 976 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 977 return -ENOENT; 978 } 979 980 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 981 if (!mac_node) { 982 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 983 return -ENOMEM; 984 } 985 986 mac_node->state = state; 987 ether_addr_copy(mac_node->mac_addr, addr); 988 list_add_tail(&mac_node->node, list); 989 990 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 991 return 0; 992} 993 994static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 995 const unsigned char *addr) 996{ 997 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 998 HCLGEVF_MAC_ADDR_UC, addr); 999} 1000 1001static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1002 const unsigned char *addr) 1003{ 1004 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1005 HCLGEVF_MAC_ADDR_UC, addr); 1006} 1007 1008static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1009 const unsigned char *addr) 1010{ 1011 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1012 HCLGEVF_MAC_ADDR_MC, addr); 1013} 1014 1015static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1016 const unsigned char *addr) 1017{ 1018 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1019 HCLGEVF_MAC_ADDR_MC, addr); 1020} 1021 1022static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1023 struct hclgevf_mac_addr_node *mac_node, 1024 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1025{ 1026 struct hclge_vf_to_pf_msg send_msg; 1027 u8 code, subcode; 1028 1029 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1030 code = HCLGE_MBX_SET_UNICAST; 1031 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1032 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1033 else 1034 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1035 } else { 1036 code = HCLGE_MBX_SET_MULTICAST; 1037 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1038 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1039 else 1040 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1041 } 1042 1043 hclgevf_build_send_msg(&send_msg, code, subcode); 1044 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1045 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1046} 1047 1048static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1049 struct list_head *list, 1050 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1051{ 1052 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1053 struct hclgevf_mac_addr_node *mac_node, *tmp; 1054 int ret; 1055 1056 list_for_each_entry_safe(mac_node, tmp, list, node) { 1057 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1058 if (ret) { 1059 hnae3_format_mac_addr(format_mac_addr, 1060 mac_node->mac_addr); 1061 dev_err(&hdev->pdev->dev, 1062 "failed to configure mac %s, state = %d, ret = %d\n", 1063 format_mac_addr, mac_node->state, ret); 1064 return; 1065 } 1066 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1067 mac_node->state = HCLGEVF_MAC_ACTIVE; 1068 } else { 1069 list_del(&mac_node->node); 1070 kfree(mac_node); 1071 } 1072 } 1073} 1074 1075static void hclgevf_sync_from_add_list(struct list_head *add_list, 1076 struct list_head *mac_list) 1077{ 1078 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1079 1080 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1081 /* if the mac address from tmp_add_list is not in the 1082 * uc/mc_mac_list, it means have received a TO_DEL request 1083 * during the time window of sending mac config request to PF 1084 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1085 * then it will be removed at next time. If is TO_ADD, it means 1086 * send TO_ADD request failed, so just remove the mac node. 1087 */ 1088 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1089 if (new_node) { 1090 hclgevf_update_mac_node(new_node, mac_node->state); 1091 list_del(&mac_node->node); 1092 kfree(mac_node); 1093 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1094 mac_node->state = HCLGEVF_MAC_TO_DEL; 1095 list_move_tail(&mac_node->node, mac_list); 1096 } else { 1097 list_del(&mac_node->node); 1098 kfree(mac_node); 1099 } 1100 } 1101} 1102 1103static void hclgevf_sync_from_del_list(struct list_head *del_list, 1104 struct list_head *mac_list) 1105{ 1106 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1107 1108 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1109 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1110 if (new_node) { 1111 /* If the mac addr is exist in the mac list, it means 1112 * received a new request TO_ADD during the time window 1113 * of sending mac addr configurrequest to PF, so just 1114 * change the mac state to ACTIVE. 1115 */ 1116 new_node->state = HCLGEVF_MAC_ACTIVE; 1117 list_del(&mac_node->node); 1118 kfree(mac_node); 1119 } else { 1120 list_move_tail(&mac_node->node, mac_list); 1121 } 1122 } 1123} 1124 1125static void hclgevf_clear_list(struct list_head *list) 1126{ 1127 struct hclgevf_mac_addr_node *mac_node, *tmp; 1128 1129 list_for_each_entry_safe(mac_node, tmp, list, node) { 1130 list_del(&mac_node->node); 1131 kfree(mac_node); 1132 } 1133} 1134 1135static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1136 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1137{ 1138 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1139 struct list_head tmp_add_list, tmp_del_list; 1140 struct list_head *list; 1141 1142 INIT_LIST_HEAD(&tmp_add_list); 1143 INIT_LIST_HEAD(&tmp_del_list); 1144 1145 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1146 * we can add/delete these mac addr outside the spin lock 1147 */ 1148 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1149 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1150 1151 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1152 1153 list_for_each_entry_safe(mac_node, tmp, list, node) { 1154 switch (mac_node->state) { 1155 case HCLGEVF_MAC_TO_DEL: 1156 list_move_tail(&mac_node->node, &tmp_del_list); 1157 break; 1158 case HCLGEVF_MAC_TO_ADD: 1159 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1160 if (!new_node) 1161 goto stop_traverse; 1162 1163 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1164 new_node->state = mac_node->state; 1165 list_add_tail(&new_node->node, &tmp_add_list); 1166 break; 1167 default: 1168 break; 1169 } 1170 } 1171 1172stop_traverse: 1173 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1174 1175 /* delete first, in order to get max mac table space for adding */ 1176 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1177 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1178 1179 /* if some mac addresses were added/deleted fail, move back to the 1180 * mac_list, and retry at next time. 1181 */ 1182 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1183 1184 hclgevf_sync_from_del_list(&tmp_del_list, list); 1185 hclgevf_sync_from_add_list(&tmp_add_list, list); 1186 1187 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1188} 1189 1190static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1191{ 1192 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1193 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1194} 1195 1196static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1197{ 1198 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1199 1200 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1201 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1202 1203 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1204} 1205 1206static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1207{ 1208 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1209 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1210 struct hclge_vf_to_pf_msg send_msg; 1211 1212 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1213 return -EOPNOTSUPP; 1214 1215 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1216 HCLGE_MBX_ENABLE_VLAN_FILTER); 1217 send_msg.data[0] = enable ? 1 : 0; 1218 1219 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1220} 1221 1222static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1223 __be16 proto, u16 vlan_id, 1224 bool is_kill) 1225{ 1226 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1227 struct hclge_mbx_vlan_filter *vlan_filter; 1228 struct hclge_vf_to_pf_msg send_msg; 1229 int ret; 1230 1231 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1232 return -EINVAL; 1233 1234 if (proto != htons(ETH_P_8021Q)) 1235 return -EPROTONOSUPPORT; 1236 1237 /* When device is resetting or reset failed, firmware is unable to 1238 * handle mailbox. Just record the vlan id, and remove it after 1239 * reset finished. 1240 */ 1241 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1242 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1243 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1244 return -EBUSY; 1245 } else if (!is_kill && test_bit(vlan_id, hdev->vlan_del_fail_bmap)) { 1246 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1247 } 1248 1249 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1250 HCLGE_MBX_VLAN_FILTER); 1251 vlan_filter = (struct hclge_mbx_vlan_filter *)send_msg.data; 1252 vlan_filter->is_kill = is_kill; 1253 vlan_filter->vlan_id = cpu_to_le16(vlan_id); 1254 vlan_filter->proto = cpu_to_le16(be16_to_cpu(proto)); 1255 1256 /* when remove hw vlan filter failed, record the vlan id, 1257 * and try to remove it from hw later, to be consistence 1258 * with stack. 1259 */ 1260 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1261 if (is_kill && ret) 1262 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1263 1264 return ret; 1265} 1266 1267static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1268{ 1269#define HCLGEVF_MAX_SYNC_COUNT 60 1270 struct hnae3_handle *handle = &hdev->nic; 1271 int ret, sync_cnt = 0; 1272 u16 vlan_id; 1273 1274 if (bitmap_empty(hdev->vlan_del_fail_bmap, VLAN_N_VID)) 1275 return; 1276 1277 rtnl_lock(); 1278 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1279 while (vlan_id != VLAN_N_VID) { 1280 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1281 vlan_id, true); 1282 if (ret) 1283 break; 1284 1285 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1286 sync_cnt++; 1287 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1288 break; 1289 1290 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1291 } 1292 rtnl_unlock(); 1293} 1294 1295static int hclgevf_en_hw_strip_rxvtag_cmd(struct hclgevf_dev *hdev, bool enable) 1296{ 1297 struct hclge_vf_to_pf_msg send_msg; 1298 1299 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1300 HCLGE_MBX_VLAN_RX_OFF_CFG); 1301 send_msg.data[0] = enable ? 1 : 0; 1302 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1303} 1304 1305static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1306{ 1307 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1308 int ret; 1309 1310 ret = hclgevf_en_hw_strip_rxvtag_cmd(hdev, enable); 1311 if (ret) 1312 return ret; 1313 1314 hdev->rxvtag_strip_en = enable; 1315 return 0; 1316} 1317 1318static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1319{ 1320#define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1321 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1322 struct hclge_vf_to_pf_msg send_msg; 1323 u8 return_status = 0; 1324 int ret; 1325 u16 i; 1326 1327 /* disable vf queue before send queue reset msg to PF */ 1328 ret = hclgevf_tqp_enable(handle, false); 1329 if (ret) { 1330 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 1331 ret); 1332 return ret; 1333 } 1334 1335 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1336 1337 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 1338 sizeof(return_status)); 1339 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 1340 return ret; 1341 1342 for (i = 1; i < handle->kinfo.num_tqps; i++) { 1343 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1344 *(__le16 *)send_msg.data = cpu_to_le16(i); 1345 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1346 if (ret) 1347 return ret; 1348 } 1349 1350 return 0; 1351} 1352 1353static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1354{ 1355 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1356 struct hclge_mbx_mtu_info *mtu_info; 1357 struct hclge_vf_to_pf_msg send_msg; 1358 1359 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1360 mtu_info = (struct hclge_mbx_mtu_info *)send_msg.data; 1361 mtu_info->mtu = cpu_to_le32(new_mtu); 1362 1363 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1364} 1365 1366static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1367 enum hnae3_reset_notify_type type) 1368{ 1369 struct hnae3_client *client = hdev->nic_client; 1370 struct hnae3_handle *handle = &hdev->nic; 1371 int ret; 1372 1373 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1374 !client) 1375 return 0; 1376 1377 if (!client->ops->reset_notify) 1378 return -EOPNOTSUPP; 1379 1380 ret = client->ops->reset_notify(handle, type); 1381 if (ret) 1382 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1383 type, ret); 1384 1385 return ret; 1386} 1387 1388static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1389 enum hnae3_reset_notify_type type) 1390{ 1391 struct hnae3_client *client = hdev->roce_client; 1392 struct hnae3_handle *handle = &hdev->roce; 1393 int ret; 1394 1395 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1396 return 0; 1397 1398 if (!client->ops->reset_notify) 1399 return -EOPNOTSUPP; 1400 1401 ret = client->ops->reset_notify(handle, type); 1402 if (ret) 1403 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1404 type, ret); 1405 return ret; 1406} 1407 1408static void hclgevf_set_reset_pending(struct hclgevf_dev *hdev, 1409 enum hnae3_reset_type reset_type) 1410{ 1411 /* When an incorrect reset type is executed, the get_reset_level 1412 * function generates the HNAE3_NONE_RESET flag. As a result, this 1413 * type do not need to pending. 1414 */ 1415 if (reset_type != HNAE3_NONE_RESET) 1416 set_bit(reset_type, &hdev->reset_pending); 1417} 1418 1419static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1420{ 1421#define HCLGEVF_RESET_WAIT_US 20000 1422#define HCLGEVF_RESET_WAIT_CNT 2000 1423#define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1424 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1425 1426 u32 val; 1427 int ret; 1428 1429 if (hdev->reset_type == HNAE3_VF_RESET) 1430 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1431 HCLGEVF_VF_RST_ING, val, 1432 !(val & HCLGEVF_VF_RST_ING_BIT), 1433 HCLGEVF_RESET_WAIT_US, 1434 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1435 else 1436 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1437 HCLGEVF_RST_ING, val, 1438 !(val & HCLGEVF_RST_ING_BITS), 1439 HCLGEVF_RESET_WAIT_US, 1440 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1441 1442 /* hardware completion status should be available by this time */ 1443 if (ret) { 1444 dev_err(&hdev->pdev->dev, 1445 "couldn't get reset done status from h/w, timeout!\n"); 1446 return ret; 1447 } 1448 1449 /* we will wait a bit more to let reset of the stack to complete. This 1450 * might happen in case reset assertion was made by PF. Yes, this also 1451 * means we might end up waiting bit more even for VF reset. 1452 */ 1453 if (hdev->reset_type == HNAE3_VF_FULL_RESET) 1454 msleep(5000); 1455 else 1456 msleep(500); 1457 1458 return 0; 1459} 1460 1461static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1462{ 1463 u32 reg_val; 1464 1465 reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 1466 if (enable) 1467 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1468 else 1469 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1470 1471 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 1472 reg_val); 1473} 1474 1475static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1476{ 1477 int ret; 1478 1479 /* uninitialize the nic client */ 1480 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1481 if (ret) 1482 return ret; 1483 1484 /* re-initialize the hclge device */ 1485 ret = hclgevf_reset_hdev(hdev); 1486 if (ret) { 1487 dev_err(&hdev->pdev->dev, 1488 "hclge device re-init failed, VF is disabled!\n"); 1489 return ret; 1490 } 1491 1492 /* bring up the nic client again */ 1493 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1494 if (ret) 1495 return ret; 1496 1497 /* clear handshake status with IMP */ 1498 hclgevf_reset_handshake(hdev, false); 1499 1500 /* bring up the nic to enable TX/RX again */ 1501 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1502} 1503 1504static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1505{ 1506#define HCLGEVF_RESET_SYNC_TIME 100 1507 1508 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1509 struct hclge_vf_to_pf_msg send_msg; 1510 int ret; 1511 1512 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1513 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1514 if (ret) { 1515 dev_err(&hdev->pdev->dev, 1516 "failed to assert VF reset, ret = %d\n", ret); 1517 return ret; 1518 } 1519 hdev->rst_stats.vf_func_rst_cnt++; 1520 } 1521 1522 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1523 /* inform hardware that preparatory work is done */ 1524 msleep(HCLGEVF_RESET_SYNC_TIME); 1525 hclgevf_reset_handshake(hdev, true); 1526 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1527 hdev->reset_type); 1528 1529 return 0; 1530} 1531 1532static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1533{ 1534 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1535 hdev->rst_stats.vf_func_rst_cnt); 1536 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1537 hdev->rst_stats.flr_rst_cnt); 1538 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1539 hdev->rst_stats.vf_rst_cnt); 1540 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1541 hdev->rst_stats.rst_done_cnt); 1542 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1543 hdev->rst_stats.hw_rst_done_cnt); 1544 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1545 hdev->rst_stats.rst_cnt); 1546 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1547 hdev->rst_stats.rst_fail_cnt); 1548 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1549 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1550 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1551 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 1552 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1553 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 1554 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1555 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1556 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1557} 1558 1559static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1560{ 1561 /* recover handshake status with IMP when reset fail */ 1562 hclgevf_reset_handshake(hdev, true); 1563 hdev->rst_stats.rst_fail_cnt++; 1564 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1565 hdev->rst_stats.rst_fail_cnt); 1566 1567 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1568 hclgevf_set_reset_pending(hdev, hdev->reset_type); 1569 1570 if (hclgevf_is_reset_pending(hdev)) { 1571 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1572 hclgevf_reset_task_schedule(hdev); 1573 } else { 1574 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1575 hclgevf_dump_rst_info(hdev); 1576 } 1577} 1578 1579static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1580{ 1581 int ret; 1582 1583 hdev->rst_stats.rst_cnt++; 1584 1585 /* perform reset of the stack & ae device for a client */ 1586 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1587 if (ret) 1588 return ret; 1589 1590 rtnl_lock(); 1591 /* bring down the nic to stop any ongoing TX/RX */ 1592 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1593 rtnl_unlock(); 1594 if (ret) 1595 return ret; 1596 1597 return hclgevf_reset_prepare_wait(hdev); 1598} 1599 1600static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1601{ 1602 int ret; 1603 1604 hdev->rst_stats.hw_rst_done_cnt++; 1605 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1606 if (ret) 1607 return ret; 1608 1609 rtnl_lock(); 1610 /* now, re-initialize the nic client and ae device */ 1611 ret = hclgevf_reset_stack(hdev); 1612 rtnl_unlock(); 1613 if (ret) { 1614 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1615 return ret; 1616 } 1617 1618 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1619 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1620 * times 1621 */ 1622 if (ret && 1623 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1624 return ret; 1625 1626 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1627 if (ret) 1628 return ret; 1629 1630 hdev->last_reset_time = jiffies; 1631 hdev->rst_stats.rst_done_cnt++; 1632 hdev->rst_stats.rst_fail_cnt = 0; 1633 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1634 1635 return 0; 1636} 1637 1638static void hclgevf_reset(struct hclgevf_dev *hdev) 1639{ 1640 if (hclgevf_reset_prepare(hdev)) 1641 goto err_reset; 1642 1643 /* check if VF could successfully fetch the hardware reset completion 1644 * status from the hardware 1645 */ 1646 if (hclgevf_reset_wait(hdev)) { 1647 /* can't do much in this situation, will disable VF */ 1648 dev_err(&hdev->pdev->dev, 1649 "failed to fetch H/W reset completion status\n"); 1650 goto err_reset; 1651 } 1652 1653 if (hclgevf_reset_rebuild(hdev)) 1654 goto err_reset; 1655 1656 return; 1657 1658err_reset: 1659 hclgevf_reset_err_handle(hdev); 1660} 1661 1662static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr) 1663{ 1664 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1665 1666 /* return the highest priority reset level amongst all */ 1667 if (test_bit(HNAE3_VF_RESET, addr)) { 1668 rst_level = HNAE3_VF_RESET; 1669 clear_bit(HNAE3_VF_RESET, addr); 1670 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1671 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1672 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1673 rst_level = HNAE3_VF_FULL_RESET; 1674 clear_bit(HNAE3_VF_FULL_RESET, addr); 1675 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1676 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1677 rst_level = HNAE3_VF_PF_FUNC_RESET; 1678 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1679 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1680 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1681 rst_level = HNAE3_VF_FUNC_RESET; 1682 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1683 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1684 rst_level = HNAE3_FLR_RESET; 1685 clear_bit(HNAE3_FLR_RESET, addr); 1686 } 1687 1688 clear_bit(HNAE3_NONE_RESET, addr); 1689 1690 return rst_level; 1691} 1692 1693static void hclgevf_reset_event(struct pci_dev *pdev, 1694 struct hnae3_handle *handle) 1695{ 1696 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1697 struct hclgevf_dev *hdev = ae_dev->priv; 1698 1699 if (hdev->default_reset_request) 1700 hdev->reset_level = 1701 hclgevf_get_reset_level(&hdev->default_reset_request); 1702 else 1703 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1704 1705 dev_info(&hdev->pdev->dev, "received reset request from VF enet, reset level is %d\n", 1706 hdev->reset_level); 1707 1708 /* reset of this VF requested */ 1709 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1710 hclgevf_reset_task_schedule(hdev); 1711 1712 hdev->last_reset_time = jiffies; 1713} 1714 1715static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1716 enum hnae3_reset_type rst_type) 1717{ 1718#define HCLGEVF_SUPPORT_RESET_TYPE \ 1719 (BIT(HNAE3_VF_RESET) | BIT(HNAE3_VF_FUNC_RESET) | \ 1720 BIT(HNAE3_VF_PF_FUNC_RESET) | BIT(HNAE3_VF_FULL_RESET) | \ 1721 BIT(HNAE3_FLR_RESET) | BIT(HNAE3_VF_EXP_RESET)) 1722 1723 struct hclgevf_dev *hdev = ae_dev->priv; 1724 1725 if (!(BIT(rst_type) & HCLGEVF_SUPPORT_RESET_TYPE)) { 1726 /* To prevent reset triggered by hclge_reset_event */ 1727 set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); 1728 dev_info(&hdev->pdev->dev, "unsupported reset type %d\n", 1729 rst_type); 1730 return; 1731 } 1732 set_bit(rst_type, &hdev->default_reset_request); 1733} 1734 1735static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1736{ 1737 writel(en ? 1 : 0, vector->addr); 1738} 1739 1740static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 1741 enum hnae3_reset_type rst_type) 1742{ 1743#define HCLGEVF_RESET_RETRY_WAIT_MS 500 1744#define HCLGEVF_RESET_RETRY_CNT 5 1745 1746 struct hclgevf_dev *hdev = ae_dev->priv; 1747 int retry_cnt = 0; 1748 int ret; 1749 1750 while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 1751 down(&hdev->reset_sem); 1752 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1753 hdev->reset_type = rst_type; 1754 ret = hclgevf_reset_prepare(hdev); 1755 if (!ret && !hdev->reset_pending) 1756 break; 1757 1758 dev_err(&hdev->pdev->dev, 1759 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 1760 ret, hdev->reset_pending, retry_cnt); 1761 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1762 up(&hdev->reset_sem); 1763 msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 1764 } 1765 1766 /* disable misc vector before reset done */ 1767 hclgevf_enable_vector(&hdev->misc_vector, false); 1768 1769 if (hdev->reset_type == HNAE3_FLR_RESET) 1770 hdev->rst_stats.flr_rst_cnt++; 1771} 1772 1773static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 1774{ 1775 struct hclgevf_dev *hdev = ae_dev->priv; 1776 int ret; 1777 1778 hclgevf_enable_vector(&hdev->misc_vector, true); 1779 1780 ret = hclgevf_reset_rebuild(hdev); 1781 if (ret) 1782 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1783 ret); 1784 1785 hdev->reset_type = HNAE3_NONE_RESET; 1786 if (test_and_clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1787 up(&hdev->reset_sem); 1788} 1789 1790static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1791{ 1792 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1793 1794 return hdev->fw_version; 1795} 1796 1797static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1798{ 1799 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1800 1801 vector->vector_irq = pci_irq_vector(hdev->pdev, 1802 HCLGEVF_MISC_VECTOR_NUM); 1803 vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1804 /* vector status always valid for Vector 0 */ 1805 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1806 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1807 1808 hdev->num_msi_left -= 1; 1809 hdev->num_msi_used += 1; 1810} 1811 1812void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1813{ 1814 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1815 test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 1816 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1817 &hdev->state)) 1818 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1819} 1820 1821void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1822{ 1823 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1824 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1825 &hdev->state)) 1826 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1827} 1828 1829static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1830 unsigned long delay) 1831{ 1832 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1833 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1834 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1835} 1836 1837static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 1838{ 1839#define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1840 1841 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1842 return; 1843 1844 down(&hdev->reset_sem); 1845 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1846 1847 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1848 &hdev->reset_state)) { 1849 /* PF has intimated that it is about to reset the hardware. 1850 * We now have to poll & check if hardware has actually 1851 * completed the reset sequence. On hardware reset completion, 1852 * VF needs to reset the client and ae device. 1853 */ 1854 hdev->reset_attempts = 0; 1855 1856 hdev->last_reset_time = jiffies; 1857 hdev->reset_type = 1858 hclgevf_get_reset_level(&hdev->reset_pending); 1859 if (hdev->reset_type != HNAE3_NONE_RESET) 1860 hclgevf_reset(hdev); 1861 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1862 &hdev->reset_state)) { 1863 /* we could be here when either of below happens: 1864 * 1. reset was initiated due to watchdog timeout caused by 1865 * a. IMP was earlier reset and our TX got choked down and 1866 * which resulted in watchdog reacting and inducing VF 1867 * reset. This also means our cmdq would be unreliable. 1868 * b. problem in TX due to other lower layer(example link 1869 * layer not functioning properly etc.) 1870 * 2. VF reset might have been initiated due to some config 1871 * change. 1872 * 1873 * NOTE: Theres no clear way to detect above cases than to react 1874 * to the response of PF for this reset request. PF will ack the 1875 * 1b and 2. cases but we will not get any intimation about 1a 1876 * from PF as cmdq would be in unreliable state i.e. mailbox 1877 * communication between PF and VF would be broken. 1878 * 1879 * if we are never geting into pending state it means either: 1880 * 1. PF is not receiving our request which could be due to IMP 1881 * reset 1882 * 2. PF is screwed 1883 * We cannot do much for 2. but to check first we can try reset 1884 * our PCIe + stack and see if it alleviates the problem. 1885 */ 1886 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1887 /* prepare for full reset of stack + pcie interface */ 1888 hclgevf_set_reset_pending(hdev, HNAE3_VF_FULL_RESET); 1889 1890 /* "defer" schedule the reset task again */ 1891 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1892 } else { 1893 hdev->reset_attempts++; 1894 1895 hclgevf_set_reset_pending(hdev, hdev->reset_level); 1896 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1897 } 1898 hclgevf_reset_task_schedule(hdev); 1899 } 1900 1901 hdev->reset_type = HNAE3_NONE_RESET; 1902 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1903 up(&hdev->reset_sem); 1904} 1905 1906static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1907{ 1908 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1909 return; 1910 1911 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1912 return; 1913 1914 hclgevf_mbx_async_handler(hdev); 1915 1916 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1917} 1918 1919static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1920{ 1921 struct hclge_vf_to_pf_msg send_msg; 1922 int ret; 1923 1924 if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1925 return; 1926 1927 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 1928 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1929 if (ret) 1930 dev_err(&hdev->pdev->dev, 1931 "VF sends keep alive cmd failed(=%d)\n", ret); 1932} 1933 1934static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1935{ 1936 unsigned long delta = round_jiffies_relative(HZ); 1937 struct hnae3_handle *handle = &hdev->nic; 1938 1939 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state) || 1940 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1941 return; 1942 1943 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1944 delta = jiffies - hdev->last_serv_processed; 1945 1946 if (delta < round_jiffies_relative(HZ)) { 1947 delta = round_jiffies_relative(HZ) - delta; 1948 goto out; 1949 } 1950 } 1951 1952 hdev->serv_processed_cnt++; 1953 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1954 hclgevf_keep_alive(hdev); 1955 1956 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1957 hdev->last_serv_processed = jiffies; 1958 goto out; 1959 } 1960 1961 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1962 hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 1963 1964 /* VF does not need to request link status when this bit is set, because 1965 * PF will push its link status to VFs when link status changed. 1966 */ 1967 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 1968 hclgevf_request_link_info(hdev); 1969 1970 hclgevf_update_link_mode(hdev); 1971 1972 hclgevf_sync_vlan_filter(hdev); 1973 1974 hclgevf_sync_mac_table(hdev); 1975 1976 hclgevf_sync_promisc_mode(hdev); 1977 1978 hdev->last_serv_processed = jiffies; 1979 1980out: 1981 hclgevf_task_schedule(hdev, delta); 1982} 1983 1984static void hclgevf_service_task(struct work_struct *work) 1985{ 1986 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1987 service_task.work); 1988 1989 hclgevf_reset_service_task(hdev); 1990 hclgevf_mailbox_service_task(hdev); 1991 hclgevf_periodic_service_task(hdev); 1992 1993 /* Handle reset and mbx again in case periodical task delays the 1994 * handling by calling hclgevf_task_schedule() in 1995 * hclgevf_periodic_service_task() 1996 */ 1997 hclgevf_reset_service_task(hdev); 1998 hclgevf_mailbox_service_task(hdev); 1999} 2000 2001static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2002{ 2003 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 2004} 2005 2006static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2007 u32 *clearval) 2008{ 2009 u32 val, cmdq_stat_reg, rst_ing_reg; 2010 2011 /* fetch the events from their corresponding regs */ 2012 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2013 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 2014 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2015 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2016 dev_info(&hdev->pdev->dev, 2017 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2018 hclgevf_set_reset_pending(hdev, HNAE3_VF_RESET); 2019 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2020 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 2021 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2022 hdev->rst_stats.vf_rst_cnt++; 2023 /* set up VF hardware reset status, its PF will clear 2024 * this status when PF has initialized done. 2025 */ 2026 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2027 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2028 val | HCLGEVF_VF_RST_ING_BIT); 2029 return HCLGEVF_VECTOR0_EVENT_RST; 2030 } 2031 2032 /* check for vector0 mailbox(=CMDQ RX) event source */ 2033 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2034 /* for revision 0x21, clearing interrupt is writing bit 0 2035 * to the clear register, writing bit 1 means to keep the 2036 * old value. 2037 * for revision 0x20, the clear register is a read & write 2038 * register, so we should just write 0 to the bit we are 2039 * handling, and keep other bits as cmdq_stat_reg. 2040 */ 2041 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2042 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2043 else 2044 *clearval = cmdq_stat_reg & 2045 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2046 2047 return HCLGEVF_VECTOR0_EVENT_MBX; 2048 } 2049 2050 /* print other vector0 event source */ 2051 dev_info(&hdev->pdev->dev, 2052 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2053 cmdq_stat_reg); 2054 2055 return HCLGEVF_VECTOR0_EVENT_OTHER; 2056} 2057 2058static void hclgevf_reset_timer(struct timer_list *t) 2059{ 2060 struct hclgevf_dev *hdev = timer_container_of(hdev, t, reset_timer); 2061 2062 hclgevf_clear_event_cause(hdev, HCLGEVF_VECTOR0_EVENT_RST); 2063 hclgevf_reset_task_schedule(hdev); 2064} 2065 2066static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2067{ 2068#define HCLGEVF_RESET_DELAY 5 2069 2070 enum hclgevf_evt_cause event_cause; 2071 struct hclgevf_dev *hdev = data; 2072 u32 clearval; 2073 2074 hclgevf_enable_vector(&hdev->misc_vector, false); 2075 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2076 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2077 hclgevf_clear_event_cause(hdev, clearval); 2078 2079 switch (event_cause) { 2080 case HCLGEVF_VECTOR0_EVENT_RST: 2081 mod_timer(&hdev->reset_timer, 2082 jiffies + msecs_to_jiffies(HCLGEVF_RESET_DELAY)); 2083 break; 2084 case HCLGEVF_VECTOR0_EVENT_MBX: 2085 hclgevf_mbx_handler(hdev); 2086 break; 2087 default: 2088 break; 2089 } 2090 2091 hclgevf_enable_vector(&hdev->misc_vector, true); 2092 2093 return IRQ_HANDLED; 2094} 2095 2096static int hclgevf_configure(struct hclgevf_dev *hdev) 2097{ 2098 int ret; 2099 2100 hdev->gro_en = true; 2101 2102 ret = hclgevf_get_basic_info(hdev); 2103 if (ret) 2104 return ret; 2105 2106 /* get current port based vlan state from PF */ 2107 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2108 if (ret) 2109 return ret; 2110 2111 /* get queue configuration from PF */ 2112 ret = hclgevf_get_queue_info(hdev); 2113 if (ret) 2114 return ret; 2115 2116 /* get queue depth info from PF */ 2117 ret = hclgevf_get_queue_depth(hdev); 2118 if (ret) 2119 return ret; 2120 2121 return hclgevf_get_pf_media_type(hdev); 2122} 2123 2124static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2125{ 2126 struct pci_dev *pdev = ae_dev->pdev; 2127 struct hclgevf_dev *hdev; 2128 2129 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2130 if (!hdev) 2131 return -ENOMEM; 2132 2133 hdev->pdev = pdev; 2134 hdev->ae_dev = ae_dev; 2135 ae_dev->priv = hdev; 2136 2137 return 0; 2138} 2139 2140static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2141{ 2142 struct hnae3_handle *roce = &hdev->roce; 2143 struct hnae3_handle *nic = &hdev->nic; 2144 2145 roce->rinfo.num_vectors = hdev->num_roce_msix; 2146 2147 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2148 hdev->num_msi_left == 0) 2149 return -EINVAL; 2150 2151 roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2152 2153 roce->rinfo.netdev = nic->kinfo.netdev; 2154 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2155 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2156 2157 roce->pdev = nic->pdev; 2158 roce->ae_algo = nic->ae_algo; 2159 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2160 MAX_NUMNODES); 2161 return 0; 2162} 2163 2164static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2165{ 2166 struct hclgevf_cfg_gro_status_cmd *req; 2167 struct hclge_desc desc; 2168 int ret; 2169 2170 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 2171 return 0; 2172 2173 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, 2174 false); 2175 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2176 2177 req->gro_en = hdev->gro_en ? 1 : 0; 2178 2179 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2180 if (ret) 2181 dev_err(&hdev->pdev->dev, 2182 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2183 2184 return ret; 2185} 2186 2187static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2188{ 2189 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 2190 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 2191 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 2192 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 2193 int ret; 2194 2195 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2196 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, 2197 rss_cfg->rss_algo, 2198 rss_cfg->rss_hash_key); 2199 if (ret) 2200 return ret; 2201 2202 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, rss_cfg); 2203 if (ret) 2204 return ret; 2205 } 2206 2207 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 2208 rss_cfg->rss_indirection_tbl); 2209 if (ret) 2210 return ret; 2211 2212 hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map, 2213 tc_offset, tc_valid, tc_size); 2214 2215 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 2216 tc_valid, tc_size); 2217} 2218 2219static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev, 2220 bool rxvtag_strip_en) 2221{ 2222 struct hnae3_handle *nic = &hdev->nic; 2223 int ret; 2224 2225 ret = hclgevf_en_hw_strip_rxvtag(nic, rxvtag_strip_en); 2226 if (ret) { 2227 dev_err(&hdev->pdev->dev, 2228 "failed to enable rx vlan offload, ret = %d\n", ret); 2229 return ret; 2230 } 2231 2232 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2233 false); 2234} 2235 2236static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2237{ 2238#define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2239 2240 unsigned long last = hdev->serv_processed_cnt; 2241 int i = 0; 2242 2243 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2244 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2245 last == hdev->serv_processed_cnt) 2246 usleep_range(1, 1); 2247} 2248 2249static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2250{ 2251 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2252 2253 if (enable) { 2254 hclgevf_task_schedule(hdev, 0); 2255 } else { 2256 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2257 2258 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 2259 hclgevf_flush_link_update(hdev); 2260 } 2261} 2262 2263static int hclgevf_ae_start(struct hnae3_handle *handle) 2264{ 2265 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2266 2267 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2268 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2269 2270 hclge_comm_reset_tqp_stats(handle); 2271 2272 hclgevf_request_link_info(hdev); 2273 2274 hclgevf_update_link_mode(hdev); 2275 2276 return 0; 2277} 2278 2279static void hclgevf_ae_stop(struct hnae3_handle *handle) 2280{ 2281 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2282 2283 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2284 2285 if (hdev->reset_type != HNAE3_VF_RESET) 2286 hclgevf_reset_tqp(handle); 2287 2288 hclge_comm_reset_tqp_stats(handle); 2289 hclgevf_update_link_status(hdev, 0); 2290} 2291 2292static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2293{ 2294#define HCLGEVF_STATE_ALIVE 1 2295#define HCLGEVF_STATE_NOT_ALIVE 0 2296 2297 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2298 struct hclge_vf_to_pf_msg send_msg; 2299 2300 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2301 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2302 HCLGEVF_STATE_NOT_ALIVE; 2303 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2304} 2305 2306static int hclgevf_client_start(struct hnae3_handle *handle) 2307{ 2308 return hclgevf_set_alive(handle, true); 2309} 2310 2311static void hclgevf_client_stop(struct hnae3_handle *handle) 2312{ 2313 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2314 int ret; 2315 2316 ret = hclgevf_set_alive(handle, false); 2317 if (ret) 2318 dev_warn(&hdev->pdev->dev, 2319 "%s failed %d\n", __func__, ret); 2320} 2321 2322static void hclgevf_state_init(struct hclgevf_dev *hdev) 2323{ 2324 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2325 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2326 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2327 2328 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2329 /* timer needs to be initialized before misc irq */ 2330 timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0); 2331 2332 mutex_init(&hdev->mbx_resp.mbx_mutex); 2333 sema_init(&hdev->reset_sem, 1); 2334 2335 spin_lock_init(&hdev->mac_table.mac_list_lock); 2336 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2337 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2338 2339 /* bring the device down */ 2340 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2341} 2342 2343static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2344{ 2345 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2346 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2347 2348 if (hdev->service_task.work.func) 2349 cancel_delayed_work_sync(&hdev->service_task); 2350 2351 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2352} 2353 2354static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2355{ 2356 struct pci_dev *pdev = hdev->pdev; 2357 int vectors; 2358 int i; 2359 2360 if (hnae3_dev_roce_supported(hdev)) 2361 vectors = pci_alloc_irq_vectors(pdev, 2362 hdev->roce_base_msix_offset + 1, 2363 hdev->num_msi, 2364 PCI_IRQ_MSIX); 2365 else 2366 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2367 hdev->num_msi, 2368 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2369 2370 if (vectors < 0) { 2371 dev_err(&pdev->dev, 2372 "failed(%d) to allocate MSI/MSI-X vectors\n", 2373 vectors); 2374 return vectors; 2375 } 2376 if (vectors < hdev->num_msi) 2377 dev_warn(&hdev->pdev->dev, 2378 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2379 hdev->num_msi, vectors); 2380 2381 hdev->num_msi = vectors; 2382 hdev->num_msi_left = vectors; 2383 2384 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2385 sizeof(u16), GFP_KERNEL); 2386 if (!hdev->vector_status) { 2387 pci_free_irq_vectors(pdev); 2388 return -ENOMEM; 2389 } 2390 2391 for (i = 0; i < hdev->num_msi; i++) 2392 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2393 2394 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2395 sizeof(int), GFP_KERNEL); 2396 if (!hdev->vector_irq) { 2397 devm_kfree(&pdev->dev, hdev->vector_status); 2398 pci_free_irq_vectors(pdev); 2399 return -ENOMEM; 2400 } 2401 2402 return 0; 2403} 2404 2405static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2406{ 2407 struct pci_dev *pdev = hdev->pdev; 2408 2409 devm_kfree(&pdev->dev, hdev->vector_status); 2410 devm_kfree(&pdev->dev, hdev->vector_irq); 2411 pci_free_irq_vectors(pdev); 2412} 2413 2414static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2415{ 2416 int ret; 2417 2418 hclgevf_get_misc_vector(hdev); 2419 2420 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2421 HCLGEVF_NAME, pci_name(hdev->pdev)); 2422 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2423 0, hdev->misc_vector.name, hdev); 2424 if (ret) { 2425 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2426 hdev->misc_vector.vector_irq); 2427 return ret; 2428 } 2429 2430 hclgevf_clear_event_cause(hdev, 0); 2431 2432 /* enable misc. vector(vector 0) */ 2433 hclgevf_enable_vector(&hdev->misc_vector, true); 2434 2435 return ret; 2436} 2437 2438static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2439{ 2440 /* disable misc vector(vector 0) */ 2441 hclgevf_enable_vector(&hdev->misc_vector, false); 2442 synchronize_irq(hdev->misc_vector.vector_irq); 2443 free_irq(hdev->misc_vector.vector_irq, hdev); 2444 hclgevf_free_vector(hdev, 0); 2445} 2446 2447static void hclgevf_info_show(struct hclgevf_dev *hdev) 2448{ 2449 struct device *dev = &hdev->pdev->dev; 2450 2451 dev_info(dev, "VF info begin:\n"); 2452 2453 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2454 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2455 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2456 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2457 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2458 dev_info(dev, "PF media type of this VF: %u\n", 2459 hdev->hw.mac.media_type); 2460 2461 dev_info(dev, "VF info end.\n"); 2462} 2463 2464static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2465 struct hnae3_client *client) 2466{ 2467 struct hclgevf_dev *hdev = ae_dev->priv; 2468 u32 rst_cnt = hdev->rst_stats.rst_cnt; 2469 int ret; 2470 2471 ret = client->ops->init_instance(&hdev->nic); 2472 if (ret) 2473 return ret; 2474 2475 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2476 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2477 rst_cnt != hdev->rst_stats.rst_cnt) { 2478 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2479 2480 client->ops->uninit_instance(&hdev->nic, 0); 2481 return -EBUSY; 2482 } 2483 2484 hnae3_set_client_init_flag(client, ae_dev, 1); 2485 2486 if (netif_msg_drv(&hdev->nic)) 2487 hclgevf_info_show(hdev); 2488 2489 return 0; 2490} 2491 2492static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2493 struct hnae3_client *client) 2494{ 2495 struct hclgevf_dev *hdev = ae_dev->priv; 2496 int ret; 2497 2498 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2499 !hdev->nic_client) 2500 return 0; 2501 2502 ret = hclgevf_init_roce_base_info(hdev); 2503 if (ret) 2504 return ret; 2505 2506 ret = client->ops->init_instance(&hdev->roce); 2507 if (ret) 2508 return ret; 2509 2510 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2511 hnae3_set_client_init_flag(client, ae_dev, 1); 2512 2513 return 0; 2514} 2515 2516static int hclgevf_init_client_instance(struct hnae3_client *client, 2517 struct hnae3_ae_dev *ae_dev) 2518{ 2519 struct hclgevf_dev *hdev = ae_dev->priv; 2520 int ret; 2521 2522 switch (client->type) { 2523 case HNAE3_CLIENT_KNIC: 2524 hdev->nic_client = client; 2525 hdev->nic.client = client; 2526 2527 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2528 if (ret) 2529 goto clear_nic; 2530 2531 ret = hclgevf_init_roce_client_instance(ae_dev, 2532 hdev->roce_client); 2533 if (ret) 2534 goto clear_roce; 2535 2536 break; 2537 case HNAE3_CLIENT_ROCE: 2538 if (hnae3_dev_roce_supported(hdev)) { 2539 hdev->roce_client = client; 2540 hdev->roce.client = client; 2541 } 2542 2543 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2544 if (ret) 2545 goto clear_roce; 2546 2547 break; 2548 default: 2549 return -EINVAL; 2550 } 2551 2552 return 0; 2553 2554clear_nic: 2555 hdev->nic_client = NULL; 2556 hdev->nic.client = NULL; 2557 return ret; 2558clear_roce: 2559 hdev->roce_client = NULL; 2560 hdev->roce.client = NULL; 2561 return ret; 2562} 2563 2564static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2565 struct hnae3_ae_dev *ae_dev) 2566{ 2567 struct hclgevf_dev *hdev = ae_dev->priv; 2568 2569 /* un-init roce, if it exists */ 2570 if (hdev->roce_client) { 2571 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2572 msleep(HCLGEVF_WAIT_RESET_DONE); 2573 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2574 2575 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2576 hdev->roce_client = NULL; 2577 hdev->roce.client = NULL; 2578 } 2579 2580 /* un-init nic/unic, if this was not called by roce client */ 2581 if (client->ops->uninit_instance && hdev->nic_client && 2582 client->type != HNAE3_CLIENT_ROCE) { 2583 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2584 msleep(HCLGEVF_WAIT_RESET_DONE); 2585 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2586 2587 client->ops->uninit_instance(&hdev->nic, 0); 2588 hdev->nic_client = NULL; 2589 hdev->nic.client = NULL; 2590 } 2591} 2592 2593static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2594{ 2595 struct pci_dev *pdev = hdev->pdev; 2596 struct hclgevf_hw *hw = &hdev->hw; 2597 2598 /* for device does not have device memory, return directly */ 2599 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2600 return 0; 2601 2602 hw->hw.mem_base = 2603 devm_ioremap_wc(&pdev->dev, 2604 pci_resource_start(pdev, HCLGEVF_MEM_BAR), 2605 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2606 if (!hw->hw.mem_base) { 2607 dev_err(&pdev->dev, "failed to map device memory\n"); 2608 return -EFAULT; 2609 } 2610 2611 return 0; 2612} 2613 2614static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2615{ 2616 struct pci_dev *pdev = hdev->pdev; 2617 struct hclgevf_hw *hw; 2618 int ret; 2619 2620 ret = pci_enable_device(pdev); 2621 if (ret) { 2622 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2623 return ret; 2624 } 2625 2626 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2627 if (ret) { 2628 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting\n"); 2629 goto err_disable_device; 2630 } 2631 2632 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2633 if (ret) { 2634 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2635 goto err_disable_device; 2636 } 2637 2638 pci_set_master(pdev); 2639 hw = &hdev->hw; 2640 hw->hw.io_base = pci_iomap(pdev, 2, 0); 2641 if (!hw->hw.io_base) { 2642 dev_err(&pdev->dev, "can't map configuration register space\n"); 2643 ret = -ENOMEM; 2644 goto err_release_regions; 2645 } 2646 2647 ret = hclgevf_dev_mem_map(hdev); 2648 if (ret) 2649 goto err_unmap_io_base; 2650 2651 return 0; 2652 2653err_unmap_io_base: 2654 pci_iounmap(pdev, hdev->hw.hw.io_base); 2655err_release_regions: 2656 pci_release_regions(pdev); 2657err_disable_device: 2658 pci_disable_device(pdev); 2659 2660 return ret; 2661} 2662 2663static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2664{ 2665 struct pci_dev *pdev = hdev->pdev; 2666 2667 if (hdev->hw.hw.mem_base) 2668 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 2669 2670 pci_iounmap(pdev, hdev->hw.hw.io_base); 2671 pci_release_regions(pdev); 2672 pci_disable_device(pdev); 2673} 2674 2675static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2676{ 2677 struct hclgevf_query_res_cmd *req; 2678 struct hclge_desc desc; 2679 int ret; 2680 2681 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true); 2682 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2683 if (ret) { 2684 dev_err(&hdev->pdev->dev, 2685 "query vf resource failed, ret = %d.\n", ret); 2686 return ret; 2687 } 2688 2689 req = (struct hclgevf_query_res_cmd *)desc.data; 2690 2691 if (hnae3_dev_roce_supported(hdev)) { 2692 hdev->roce_base_msix_offset = 2693 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 2694 HCLGEVF_MSIX_OFT_ROCEE_M, 2695 HCLGEVF_MSIX_OFT_ROCEE_S); 2696 hdev->num_roce_msix = 2697 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2698 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2699 2700 /* nic's msix numbers is always equals to the roce's. */ 2701 hdev->num_nic_msix = hdev->num_roce_msix; 2702 2703 /* VF should have NIC vectors and Roce vectors, NIC vectors 2704 * are queued before Roce vectors. The offset is fixed to 64. 2705 */ 2706 hdev->num_msi = hdev->num_roce_msix + 2707 hdev->roce_base_msix_offset; 2708 } else { 2709 hdev->num_msi = 2710 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2711 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2712 2713 hdev->num_nic_msix = hdev->num_msi; 2714 } 2715 2716 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2717 dev_err(&hdev->pdev->dev, 2718 "Just %u msi resources, not enough for vf(min:2).\n", 2719 hdev->num_nic_msix); 2720 return -EINVAL; 2721 } 2722 2723 return 0; 2724} 2725 2726static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2727{ 2728#define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2729 2730 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2731 2732 ae_dev->dev_specs.max_non_tso_bd_num = 2733 HCLGEVF_MAX_NON_TSO_BD_NUM; 2734 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2735 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2736 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2737 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2738} 2739 2740static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 2741 struct hclge_desc *desc) 2742{ 2743 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2744 struct hclgevf_dev_specs_0_cmd *req0; 2745 struct hclgevf_dev_specs_1_cmd *req1; 2746 2747 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 2748 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 2749 2750 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 2751 ae_dev->dev_specs.rss_ind_tbl_size = 2752 le16_to_cpu(req0->rss_ind_tbl_size); 2753 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 2754 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 2755 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 2756 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 2757} 2758 2759static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 2760{ 2761 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 2762 2763 if (!dev_specs->max_non_tso_bd_num) 2764 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 2765 if (!dev_specs->rss_ind_tbl_size) 2766 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2767 if (!dev_specs->rss_key_size) 2768 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2769 if (!dev_specs->max_int_gl) 2770 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2771 if (!dev_specs->max_frm_size) 2772 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2773} 2774 2775static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 2776{ 2777 struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 2778 int ret; 2779 int i; 2780 2781 /* set default specifications as devices lower than version V3 do not 2782 * support querying specifications from firmware. 2783 */ 2784 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 2785 hclgevf_set_default_dev_specs(hdev); 2786 return 0; 2787 } 2788 2789 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2790 hclgevf_cmd_setup_basic_desc(&desc[i], 2791 HCLGE_OPC_QUERY_DEV_SPECS, true); 2792 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2793 } 2794 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 2795 2796 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 2797 if (ret) 2798 return ret; 2799 2800 hclgevf_parse_dev_specs(hdev, desc); 2801 hclgevf_check_dev_specs(hdev); 2802 2803 return 0; 2804} 2805 2806static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2807{ 2808 struct pci_dev *pdev = hdev->pdev; 2809 int ret = 0; 2810 2811 if ((hdev->reset_type == HNAE3_VF_FULL_RESET || 2812 hdev->reset_type == HNAE3_FLR_RESET) && 2813 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2814 hclgevf_misc_irq_uninit(hdev); 2815 hclgevf_uninit_msi(hdev); 2816 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2817 } 2818 2819 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2820 pci_set_master(pdev); 2821 ret = hclgevf_init_msi(hdev); 2822 if (ret) { 2823 dev_err(&pdev->dev, 2824 "failed(%d) to init MSI/MSI-X\n", ret); 2825 return ret; 2826 } 2827 2828 ret = hclgevf_misc_irq_init(hdev); 2829 if (ret) { 2830 hclgevf_uninit_msi(hdev); 2831 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2832 ret); 2833 return ret; 2834 } 2835 2836 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2837 } 2838 2839 return ret; 2840} 2841 2842static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2843{ 2844 struct hclge_vf_to_pf_msg send_msg; 2845 2846 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2847 HCLGE_MBX_VPORT_LIST_CLEAR); 2848 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2849} 2850 2851static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 2852{ 2853 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2854 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 2855} 2856 2857static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 2858{ 2859 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2860 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 2861} 2862 2863static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2864{ 2865 struct pci_dev *pdev = hdev->pdev; 2866 int ret; 2867 2868 ret = hclgevf_pci_reset(hdev); 2869 if (ret) { 2870 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2871 return ret; 2872 } 2873 2874 hclgevf_arq_init(hdev); 2875 2876 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2877 &hdev->fw_version, false, 2878 hdev->reset_pending); 2879 if (ret) { 2880 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2881 return ret; 2882 } 2883 2884 ret = hclgevf_rss_init_hw(hdev); 2885 if (ret) { 2886 dev_err(&hdev->pdev->dev, 2887 "failed(%d) to initialize RSS\n", ret); 2888 return ret; 2889 } 2890 2891 ret = hclgevf_config_gro(hdev); 2892 if (ret) 2893 return ret; 2894 2895 ret = hclgevf_init_vlan_config(hdev, hdev->rxvtag_strip_en); 2896 if (ret) { 2897 dev_err(&hdev->pdev->dev, 2898 "failed(%d) to initialize VLAN config\n", ret); 2899 return ret; 2900 } 2901 2902 /* get current port based vlan state from PF */ 2903 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2904 if (ret) 2905 return ret; 2906 2907 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 2908 2909 hclgevf_init_rxd_adv_layout(hdev); 2910 2911 dev_info(&hdev->pdev->dev, "Reset done\n"); 2912 2913 return 0; 2914} 2915 2916static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2917{ 2918 struct pci_dev *pdev = hdev->pdev; 2919 int ret; 2920 2921 ret = hclgevf_pci_init(hdev); 2922 if (ret) 2923 return ret; 2924 2925 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 2926 if (ret) 2927 goto err_cmd_queue_init; 2928 2929 hclgevf_arq_init(hdev); 2930 2931 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclgevf_cmq_ops); 2932 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2933 &hdev->fw_version, false, 2934 hdev->reset_pending); 2935 if (ret) 2936 goto err_cmd_init; 2937 2938 /* Get vf resource */ 2939 ret = hclgevf_query_vf_resource(hdev); 2940 if (ret) 2941 goto err_cmd_init; 2942 2943 ret = hclgevf_query_dev_specs(hdev); 2944 if (ret) { 2945 dev_err(&pdev->dev, 2946 "failed to query dev specifications, ret = %d\n", ret); 2947 goto err_cmd_init; 2948 } 2949 2950 ret = hclgevf_init_msi(hdev); 2951 if (ret) { 2952 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2953 goto err_cmd_init; 2954 } 2955 2956 hclgevf_state_init(hdev); 2957 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2958 hdev->reset_type = HNAE3_NONE_RESET; 2959 2960 ret = hclgevf_misc_irq_init(hdev); 2961 if (ret) 2962 goto err_misc_irq_init; 2963 2964 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2965 2966 ret = hclgevf_configure(hdev); 2967 if (ret) { 2968 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2969 goto err_config; 2970 } 2971 2972 ret = hclgevf_alloc_tqps(hdev); 2973 if (ret) { 2974 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2975 goto err_config; 2976 } 2977 2978 ret = hclgevf_set_handle_info(hdev); 2979 if (ret) 2980 goto err_config; 2981 2982 ret = hclgevf_config_gro(hdev); 2983 if (ret) 2984 goto err_config; 2985 2986 /* Initialize RSS for this VF */ 2987 ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev, 2988 &hdev->rss_cfg); 2989 if (ret) { 2990 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 2991 goto err_config; 2992 } 2993 2994 ret = hclgevf_rss_init_hw(hdev); 2995 if (ret) { 2996 dev_err(&hdev->pdev->dev, 2997 "failed(%d) to initialize RSS\n", ret); 2998 goto err_config; 2999 } 3000 3001 /* ensure vf tbl list as empty before init */ 3002 ret = hclgevf_clear_vport_list(hdev); 3003 if (ret) { 3004 dev_err(&pdev->dev, 3005 "failed to clear tbl list configuration, ret = %d.\n", 3006 ret); 3007 goto err_config; 3008 } 3009 3010 ret = hclgevf_init_vlan_config(hdev, true); 3011 if (ret) { 3012 dev_err(&hdev->pdev->dev, 3013 "failed(%d) to initialize VLAN config\n", ret); 3014 goto err_config; 3015 } 3016 3017 hclgevf_init_rxd_adv_layout(hdev); 3018 3019 ret = hclgevf_devlink_init(hdev); 3020 if (ret) 3021 goto err_config; 3022 3023 set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 3024 3025 hdev->last_reset_time = jiffies; 3026 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 3027 HCLGEVF_DRIVER_NAME); 3028 3029 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3030 3031 return 0; 3032 3033err_config: 3034 hclgevf_misc_irq_uninit(hdev); 3035err_misc_irq_init: 3036 hclgevf_state_uninit(hdev); 3037 hclgevf_uninit_msi(hdev); 3038err_cmd_init: 3039 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3040err_cmd_queue_init: 3041 hclgevf_pci_uninit(hdev); 3042 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3043 return ret; 3044} 3045 3046static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3047{ 3048 struct hclge_vf_to_pf_msg send_msg; 3049 3050 hclgevf_state_uninit(hdev); 3051 hclgevf_uninit_rxd_adv_layout(hdev); 3052 3053 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3054 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3055 3056 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3057 hclgevf_misc_irq_uninit(hdev); 3058 hclgevf_uninit_msi(hdev); 3059 } 3060 3061 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3062 hclgevf_devlink_uninit(hdev); 3063 hclgevf_pci_uninit(hdev); 3064 hclgevf_uninit_mac_list(hdev); 3065} 3066 3067static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3068{ 3069 struct pci_dev *pdev = ae_dev->pdev; 3070 int ret; 3071 3072 ret = hclgevf_alloc_hdev(ae_dev); 3073 if (ret) { 3074 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3075 return ret; 3076 } 3077 3078 ret = hclgevf_init_hdev(ae_dev->priv); 3079 if (ret) { 3080 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3081 return ret; 3082 } 3083 3084 return 0; 3085} 3086 3087static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3088{ 3089 struct hclgevf_dev *hdev = ae_dev->priv; 3090 3091 hclgevf_uninit_hdev(hdev); 3092 ae_dev->priv = NULL; 3093} 3094 3095static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3096{ 3097 return min(hdev->rss_size_max, hdev->num_tqps); 3098} 3099 3100/** 3101 * hclgevf_get_channels - Get the current channels enabled and max supported. 3102 * @handle: hardware information for network interface 3103 * @ch: ethtool channels structure 3104 * 3105 * We don't support separate tx and rx queues as channels. The other count 3106 * represents how many queues are being used for control. max_combined counts 3107 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3108 * q_vectors since we support a lot more queue pairs than q_vectors. 3109 **/ 3110static void hclgevf_get_channels(struct hnae3_handle *handle, 3111 struct ethtool_channels *ch) 3112{ 3113 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3114 3115 ch->max_combined = hclgevf_get_max_channels(hdev); 3116 ch->other_count = 0; 3117 ch->max_other = 0; 3118 ch->combined_count = handle->kinfo.rss_size; 3119} 3120 3121static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3122 u16 *alloc_tqps, u16 *max_rss_size) 3123{ 3124 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3125 3126 *alloc_tqps = hdev->num_tqps; 3127 *max_rss_size = hdev->rss_size_max; 3128} 3129 3130static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3131 u32 new_tqps_num) 3132{ 3133 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3134 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3135 u16 max_rss_size; 3136 3137 kinfo->req_rss_size = new_tqps_num; 3138 3139 max_rss_size = min_t(u16, hdev->rss_size_max, 3140 hdev->num_tqps / kinfo->tc_info.num_tc); 3141 3142 /* Use the user's configuration when it is not larger than 3143 * max_rss_size, otherwise, use the maximum specification value. 3144 */ 3145 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3146 kinfo->req_rss_size <= max_rss_size) 3147 kinfo->rss_size = kinfo->req_rss_size; 3148 else if (kinfo->rss_size > max_rss_size || 3149 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3150 kinfo->rss_size = max_rss_size; 3151 3152 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3153} 3154 3155static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3156 bool rxfh_configured) 3157{ 3158 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3159 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3160 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 3161 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 3162 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 3163 u16 cur_rss_size = kinfo->rss_size; 3164 u16 cur_tqps = kinfo->num_tqps; 3165 u32 *rss_indir; 3166 unsigned int i; 3167 int ret; 3168 3169 hclgevf_update_rss_size(handle, new_tqps_num); 3170 3171 hclge_comm_get_rss_tc_info(kinfo->rss_size, hdev->hw_tc_map, 3172 tc_offset, tc_valid, tc_size); 3173 ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 3174 tc_valid, tc_size); 3175 if (ret) 3176 return ret; 3177 3178 /* RSS indirection table has been configured by user */ 3179 if (rxfh_configured) 3180 goto out; 3181 3182 /* Reinitializes the rss indirect table according to the new RSS size */ 3183 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3184 sizeof(u32), GFP_KERNEL); 3185 if (!rss_indir) 3186 return -ENOMEM; 3187 3188 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3189 rss_indir[i] = i % kinfo->rss_size; 3190 3191 hdev->rss_cfg.rss_size = kinfo->rss_size; 3192 3193 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3194 if (ret) 3195 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3196 ret); 3197 3198 kfree(rss_indir); 3199 3200out: 3201 if (!ret) 3202 dev_info(&hdev->pdev->dev, 3203 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3204 cur_rss_size, kinfo->rss_size, 3205 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3206 3207 return ret; 3208} 3209 3210static int hclgevf_get_status(struct hnae3_handle *handle) 3211{ 3212 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3213 3214 return hdev->hw.mac.link; 3215} 3216 3217static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3218 u8 *auto_neg, u32 *speed, 3219 u8 *duplex, u32 *lane_num) 3220{ 3221 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3222 3223 if (speed) 3224 *speed = hdev->hw.mac.speed; 3225 if (duplex) 3226 *duplex = hdev->hw.mac.duplex; 3227 if (auto_neg) 3228 *auto_neg = AUTONEG_DISABLE; 3229} 3230 3231void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3232 u8 duplex) 3233{ 3234 hdev->hw.mac.speed = speed; 3235 hdev->hw.mac.duplex = duplex; 3236} 3237 3238static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3239{ 3240 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3241 bool gro_en_old = hdev->gro_en; 3242 int ret; 3243 3244 hdev->gro_en = enable; 3245 ret = hclgevf_config_gro(hdev); 3246 if (ret) 3247 hdev->gro_en = gro_en_old; 3248 3249 return ret; 3250} 3251 3252static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3253 u8 *module_type) 3254{ 3255 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3256 3257 if (media_type) 3258 *media_type = hdev->hw.mac.media_type; 3259 3260 if (module_type) 3261 *module_type = hdev->hw.mac.module_type; 3262} 3263 3264static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3265{ 3266 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3267 3268 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3269} 3270 3271static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3272{ 3273 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3274 3275 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3276} 3277 3278static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3279{ 3280 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3281 3282 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3283} 3284 3285static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3286{ 3287 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3288 3289 return hdev->rst_stats.hw_rst_done_cnt; 3290} 3291 3292static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3293 unsigned long *supported, 3294 unsigned long *advertising) 3295{ 3296 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3297 3298 *supported = hdev->hw.mac.supported; 3299 *advertising = hdev->hw.mac.advertising; 3300} 3301 3302void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3303 struct hclge_mbx_port_base_vlan *port_base_vlan) 3304{ 3305 struct hnae3_handle *nic = &hdev->nic; 3306 struct hclge_vf_to_pf_msg send_msg; 3307 int ret; 3308 3309 rtnl_lock(); 3310 3311 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3312 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3313 dev_warn(&hdev->pdev->dev, 3314 "is resetting when updating port based vlan info\n"); 3315 rtnl_unlock(); 3316 return; 3317 } 3318 3319 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3320 if (ret) { 3321 rtnl_unlock(); 3322 return; 3323 } 3324 3325 /* send msg to PF and wait update port based vlan info */ 3326 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3327 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3328 memcpy(send_msg.data, port_base_vlan, sizeof(*port_base_vlan)); 3329 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3330 if (!ret) { 3331 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3332 nic->port_base_vlan_state = state; 3333 else 3334 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3335 } 3336 3337 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3338 rtnl_unlock(); 3339} 3340 3341static const struct hnae3_ae_ops hclgevf_ops = { 3342 .init_ae_dev = hclgevf_init_ae_dev, 3343 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3344 .reset_prepare = hclgevf_reset_prepare_general, 3345 .reset_done = hclgevf_reset_done, 3346 .init_client_instance = hclgevf_init_client_instance, 3347 .uninit_client_instance = hclgevf_uninit_client_instance, 3348 .start = hclgevf_ae_start, 3349 .stop = hclgevf_ae_stop, 3350 .client_start = hclgevf_client_start, 3351 .client_stop = hclgevf_client_stop, 3352 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3353 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3354 .get_vector = hclgevf_get_vector, 3355 .put_vector = hclgevf_put_vector, 3356 .reset_queue = hclgevf_reset_tqp, 3357 .get_mac_addr = hclgevf_get_mac_addr, 3358 .set_mac_addr = hclgevf_set_mac_addr, 3359 .add_uc_addr = hclgevf_add_uc_addr, 3360 .rm_uc_addr = hclgevf_rm_uc_addr, 3361 .add_mc_addr = hclgevf_add_mc_addr, 3362 .rm_mc_addr = hclgevf_rm_mc_addr, 3363 .get_stats = hclgevf_get_stats, 3364 .update_stats = hclgevf_update_stats, 3365 .get_strings = hclgevf_get_strings, 3366 .get_sset_count = hclgevf_get_sset_count, 3367 .get_rss_key_size = hclge_comm_get_rss_key_size, 3368 .get_rss = hclgevf_get_rss, 3369 .set_rss = hclgevf_set_rss, 3370 .get_rss_tuple = hclgevf_get_rss_tuple, 3371 .set_rss_tuple = hclgevf_set_rss_tuple, 3372 .get_tc_size = hclgevf_get_tc_size, 3373 .get_fw_version = hclgevf_get_fw_version, 3374 .set_vlan_filter = hclgevf_set_vlan_filter, 3375 .enable_vlan_filter = hclgevf_enable_vlan_filter, 3376 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3377 .reset_event = hclgevf_reset_event, 3378 .set_default_reset_request = hclgevf_set_def_reset_request, 3379 .set_channels = hclgevf_set_channels, 3380 .get_channels = hclgevf_get_channels, 3381 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3382 .get_regs_len = hclgevf_get_regs_len, 3383 .get_regs = hclgevf_get_regs, 3384 .get_status = hclgevf_get_status, 3385 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3386 .get_media_type = hclgevf_get_media_type, 3387 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3388 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3389 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3390 .set_gro_en = hclgevf_gro_en, 3391 .set_mtu = hclgevf_set_mtu, 3392 .get_global_queue_id = hclgevf_get_qid_global, 3393 .set_timer_task = hclgevf_set_timer_task, 3394 .get_link_mode = hclgevf_get_link_mode, 3395 .set_promisc_mode = hclgevf_set_promisc_mode, 3396 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3397 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3398}; 3399 3400static struct hnae3_ae_algo ae_algovf = { 3401 .ops = &hclgevf_ops, 3402 .pdev_id_table = ae_algovf_pci_tbl, 3403}; 3404 3405static int __init hclgevf_init(void) 3406{ 3407 pr_info("%s is initializing\n", HCLGEVF_NAME); 3408 3409 hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 3410 if (!hclgevf_wq) { 3411 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3412 return -ENOMEM; 3413 } 3414 3415 hnae3_register_ae_algo(&ae_algovf); 3416 3417 return 0; 3418} 3419 3420static void __exit hclgevf_exit(void) 3421{ 3422 hnae3_acquire_unload_lock(); 3423 hnae3_unregister_ae_algo(&ae_algovf); 3424 destroy_workqueue(hclgevf_wq); 3425 hnae3_release_unload_lock(); 3426} 3427module_init(hclgevf_init); 3428module_exit(hclgevf_exit); 3429 3430MODULE_LICENSE("GPL"); 3431MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3432MODULE_DESCRIPTION("HCLGEVF Driver"); 3433MODULE_VERSION(HCLGEVF_MOD_VERSION);
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