hclge_mdio.c

  1// SPDX-License-Identifier: GPL-2.0+
  2// Copyright (c) 2016-2017 Hisilicon Limited.
  3
  4#include <linux/etherdevice.h>
  5#include <linux/kernel.h>
  6#include <linux/marvell_phy.h>
  7
  8#include "hclge_cmd.h"
  9#include "hclge_main.h"
 10#include "hclge_mdio.h"
 11
 12enum hclge_mdio_c22_op_seq {
 13	HCLGE_MDIO_C22_WRITE = 1,
 14	HCLGE_MDIO_C22_READ = 2
 15};
 16
 17#define HCLGE_MDIO_CTRL_START_B		0
 18#define HCLGE_MDIO_CTRL_ST_S		1
 19#define HCLGE_MDIO_CTRL_ST_M		(0x3 << HCLGE_MDIO_CTRL_ST_S)
 20#define HCLGE_MDIO_CTRL_OP_S		3
 21#define HCLGE_MDIO_CTRL_OP_M		(0x3 << HCLGE_MDIO_CTRL_OP_S)
 22
 23#define HCLGE_MDIO_PHYID_S		0
 24#define HCLGE_MDIO_PHYID_M		(0x1f << HCLGE_MDIO_PHYID_S)
 25
 26#define HCLGE_MDIO_PHYREG_S		0
 27#define HCLGE_MDIO_PHYREG_M		(0x1f << HCLGE_MDIO_PHYREG_S)
 28
 29#define HCLGE_MDIO_STA_B		0
 30
 31struct hclge_mdio_cfg_cmd {
 32	u8 ctrl_bit;
 33	u8 phyid;
 34	u8 phyad;
 35	u8 rsvd;
 36	__le16 reserve;
 37	__le16 data_wr;
 38	__le16 data_rd;
 39	__le16 sta;
 40};
 41
 42static int hclge_mdio_write(struct mii_bus *bus, int phyid, int regnum,
 43			    u16 data)
 44{
 45	struct hclge_mdio_cfg_cmd *mdio_cmd;
 46	struct hclge_dev *hdev = bus->priv;
 47	struct hclge_desc desc;
 48	int ret;
 49
 50	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))
 51		return -EBUSY;
 52
 53	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, false);
 54
 55	mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data;
 56
 57	hnae3_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,
 58			HCLGE_MDIO_PHYID_S, (u32)phyid);
 59	hnae3_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,
 60			HCLGE_MDIO_PHYREG_S, (u32)regnum);
 61
 62	hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);
 63	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,
 64			HCLGE_MDIO_CTRL_ST_S, 1);
 65	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M,
 66			HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_WRITE);
 67
 68	mdio_cmd->data_wr = cpu_to_le16(data);
 69
 70	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 71	if (ret) {
 72		dev_err(&hdev->pdev->dev,
 73			"mdio write fail when sending cmd, status is %d.\n",
 74			ret);
 75		return ret;
 76	}
 77
 78	return 0;
 79}
 80
 81static int hclge_mdio_read(struct mii_bus *bus, int phyid, int regnum)
 82{
 83	struct hclge_mdio_cfg_cmd *mdio_cmd;
 84	struct hclge_dev *hdev = bus->priv;
 85	struct hclge_desc desc;
 86	int ret;
 87
 88	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))
 89		return -EBUSY;
 90
 91	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, true);
 92
 93	mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data;
 94
 95	hnae3_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,
 96			HCLGE_MDIO_PHYID_S, (u32)phyid);
 97	hnae3_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,
 98			HCLGE_MDIO_PHYREG_S, (u32)regnum);
 99
100	hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);
101	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,
102			HCLGE_MDIO_CTRL_ST_S, 1);
103	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M,
104			HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_READ);
105
106	/* Read out phy data */
107	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
108	if (ret) {
109		dev_err(&hdev->pdev->dev,
110			"mdio read fail when get data, status is %d.\n",
111			ret);
112		return ret;
113	}
114
115	if (hnae3_get_bit(le16_to_cpu(mdio_cmd->sta), HCLGE_MDIO_STA_B)) {
116		dev_err(&hdev->pdev->dev, "mdio read data error\n");
117		return -EIO;
118	}
119
120	return le16_to_cpu(mdio_cmd->data_rd);
121}
122
123int hclge_mac_mdio_config(struct hclge_dev *hdev)
124{
125#define PHY_INEXISTENT	255
126
127	struct hclge_mac *mac = &hdev->hw.mac;
128	struct phy_device *phydev;
129	struct mii_bus *mdio_bus;
130	int ret;
131
132	if (hdev->hw.mac.phy_addr == PHY_INEXISTENT) {
133		dev_info(&hdev->pdev->dev,
134			 "no phy device is connected to mdio bus\n");
135		return 0;
136	} else if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR) {
137		dev_err(&hdev->pdev->dev, "phy_addr(%u) is too large.\n",
138			hdev->hw.mac.phy_addr);
139		return -EINVAL;
140	}
141
142	mdio_bus = devm_mdiobus_alloc(&hdev->pdev->dev);
143	if (!mdio_bus)
144		return -ENOMEM;
145
146	mdio_bus->name = "hisilicon MII bus";
147	mdio_bus->read = hclge_mdio_read;
148	mdio_bus->write = hclge_mdio_write;
149	snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "mii",
150		 dev_name(&hdev->pdev->dev));
151
152	mdio_bus->parent = &hdev->pdev->dev;
153	mdio_bus->priv = hdev;
154	mdio_bus->phy_mask = ~(1U << mac->phy_addr);
155	ret = mdiobus_register(mdio_bus);
156	if (ret) {
157		dev_err(mdio_bus->parent,
158			"failed to register MDIO bus, ret = %d\n", ret);
159		return ret;
160	}
161
162	phydev = mdiobus_get_phy(mdio_bus, mac->phy_addr);
163	if (!phydev) {
164		dev_err(mdio_bus->parent, "Failed to get phy device\n");
165		mdiobus_unregister(mdio_bus);
166		return -EIO;
167	}
168
169	mac->phydev = phydev;
170	mac->mdio_bus = mdio_bus;
171
172	return 0;
173}
174
175static void hclge_mac_adjust_link(struct net_device *netdev)
176{
177	struct hnae3_handle *h = *((void **)netdev_priv(netdev));
178	struct hclge_vport *vport = hclge_get_vport(h);
179	struct hclge_dev *hdev = vport->back;
180	int duplex, speed;
181	int ret;
182
183	/* When phy link down, do nothing */
184	if (netdev->phydev->link == 0)
185		return;
186
187	speed = netdev->phydev->speed;
188	duplex = netdev->phydev->duplex;
189
190	ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, 0);
191	if (ret)
192		netdev_err(netdev, "failed to adjust link.\n");
193
194	hdev->hw.mac.req_speed = (u32)speed;
195	hdev->hw.mac.req_duplex = (u8)duplex;
196
197	ret = hclge_cfg_flowctrl(hdev);
198	if (ret)
199		netdev_err(netdev, "failed to configure flow control.\n");
200}
201
202int hclge_mac_connect_phy(struct hnae3_handle *handle)
203{
204	struct hclge_vport *vport = hclge_get_vport(handle);
205	struct hclge_dev *hdev = vport->back;
206	struct net_device *netdev = hdev->vport[0].nic.netdev;
207	struct phy_device *phydev = hdev->hw.mac.phydev;
208	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
209	int ret;
210
211	if (!phydev)
212		return 0;
213
214	linkmode_clear_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
215
216	phydev->dev_flags |= MARVELL_PHY_LED0_LINK_LED1_ACTIVE;
217
218	ret = phy_connect_direct(netdev, phydev,
219				 hclge_mac_adjust_link,
220				 PHY_INTERFACE_MODE_SGMII);
221	if (ret) {
222		netdev_err(netdev, "phy_connect_direct err.\n");
223		return ret;
224	}
225
226	linkmode_copy(mask, hdev->hw.mac.supported);
227	linkmode_and(phydev->supported, phydev->supported, mask);
228	linkmode_copy(phydev->advertising, phydev->supported);
229
230	/* supported flag is Pause and Asym Pause, but default advertising
231	 * should be rx on, tx on, so need clear Asym Pause in advertising
232	 * flag
233	 */
234	linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
235			   phydev->advertising);
236
237	phy_attached_info(phydev);
238
239	return 0;
240}
241
242void hclge_mac_disconnect_phy(struct hnae3_handle *handle)
243{
244	struct hclge_vport *vport = hclge_get_vport(handle);
245	struct hclge_dev *hdev = vport->back;
246	struct phy_device *phydev = hdev->hw.mac.phydev;
247
248	if (!phydev)
249		return;
250
251	phy_disconnect(phydev);
252}
253
254void hclge_mac_start_phy(struct hclge_dev *hdev)
255{
256	struct phy_device *phydev = hdev->hw.mac.phydev;
257
258	if (!phydev)
259		return;
260
261	phy_loopback(phydev, false, 0);
262
263	phy_start(phydev);
264}
265
266void hclge_mac_stop_phy(struct hclge_dev *hdev)
267{
268	struct net_device *netdev = hdev->vport[0].nic.netdev;
269	struct phy_device *phydev = netdev->phydev;
270
271	if (!phydev)
272		return;
273
274	phy_stop(phydev);
275}
276
277int hclge_read_phy_reg(struct hclge_dev *hdev, u16 reg_addr, u16 *val)
278{
279	struct hclge_phy_reg_cmd *req;
280	struct hclge_desc desc;
281	int ret;
282
283	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PHY_REG, true);
284
285	req = (struct hclge_phy_reg_cmd *)desc.data;
286	req->reg_addr = cpu_to_le16(reg_addr);
287
288	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
289	if (ret) {
290		dev_err(&hdev->pdev->dev,
291			"failed to read phy reg, ret = %d.\n", ret);
292		return ret;
293	}
294
295	*val = le16_to_cpu(req->reg_val);
296	return 0;
297}
298
299int hclge_write_phy_reg(struct hclge_dev *hdev, u16 reg_addr, u16 val)
300{
301	struct hclge_phy_reg_cmd *req;
302	struct hclge_desc desc;
303	int ret;
304
305	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PHY_REG, false);
306
307	req = (struct hclge_phy_reg_cmd *)desc.data;
308	req->reg_addr = cpu_to_le16(reg_addr);
309	req->reg_val = cpu_to_le16(val);
310
311	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
312	if (ret)
313		dev_err(&hdev->pdev->dev,
314			"failed to write phy reg, ret = %d.\n", ret);
315
316	return ret;
317}