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hclge_main.c
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linux-6.19.14/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
1// SPDX-License-Identifier: GPL-2.0+ 2// Copyright (c) 2016-2017 Hisilicon Limited. 3 4#include <linux/acpi.h> 5#include <linux/device.h> 6#include <linux/etherdevice.h> 7#include <linux/init.h> 8#include <linux/interrupt.h> 9#include <linux/irq.h> 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/netdevice.h> 13#include <linux/pci.h> 14#include <linux/platform_device.h> 15#include <linux/if_vlan.h> 16#include <linux/crash_dump.h> 17 18#include <net/rtnetlink.h> 19 20#include "hclge_cmd.h" 21#include "hclge_dcb.h" 22#include "hclge_main.h" 23#include "hclge_mbx.h" 24#include "hclge_mdio.h" 25#include "hclge_regs.h" 26#include "hclge_tm.h" 27#include "hclge_err.h" 28#include "hnae3.h" 29#include "hclge_devlink.h" 30#include "hclge_comm_cmd.h" 31 32#include "hclge_trace.h" 33 34#define HCLGE_NAME "hclge" 35 36#define HCLGE_BUF_SIZE_UNIT 256U 37#define HCLGE_BUF_MUL_BY 2 38#define HCLGE_BUF_DIV_BY 2 39#define NEED_RESERVE_TC_NUM 2 40#define BUF_MAX_PERCENT 100 41#define BUF_RESERVE_PERCENT 90 42 43#define HCLGE_RESET_MAX_FAIL_CNT 5 44#define HCLGE_RESET_SYNC_TIME 100 45#define HCLGE_PF_RESET_SYNC_TIME 20 46#define HCLGE_PF_RESET_SYNC_CNT 1500 47 48#define HCLGE_LINK_STATUS_MS 10 49 50static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 51static int hclge_init_vlan_config(struct hclge_dev *hdev); 52static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 53static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 54static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 55static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 56static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 57static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 58 unsigned long *addr); 59static int hclge_set_default_loopback(struct hclge_dev *hdev); 60 61static void hclge_sync_mac_table(struct hclge_dev *hdev); 62static void hclge_restore_hw_table(struct hclge_dev *hdev); 63static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 64static void hclge_sync_fd_table(struct hclge_dev *hdev); 65static void hclge_update_fec_stats(struct hclge_dev *hdev); 66static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 67 int wait_cnt); 68static int hclge_update_port_info(struct hclge_dev *hdev); 69 70static struct hnae3_ae_algo ae_algo; 71 72static struct workqueue_struct *hclge_wq; 73 74static const struct pci_device_id ae_algo_pci_tbl[] = { 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 79 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 83 /* required last entry */ 84 {0, } 85}; 86 87MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 88 89static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 90 "External Loopback test", 91 "App Loopback test", 92 "Serdes serial Loopback test", 93 "Serdes parallel Loopback test", 94 "Phy Loopback test" 95}; 96 97static const struct hclge_comm_stats_str g_mac_stats_string[] = { 98 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 100 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 101 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 102 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 104 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 105 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 106 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 108 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 109 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 110 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 112 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 114 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 116 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 118 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 120 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 122 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 124 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 126 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 128 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 130 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 132 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 134 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 136 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 138 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 140 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 141 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 142 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 143 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 144 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 146 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 148 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 150 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 152 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 154 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 156 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 158 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 160 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 162 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 164 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 166 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 168 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 170 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 172 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 174 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 176 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 178 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 180 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 182 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 184 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 186 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 188 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 190 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 192 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 194 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 196 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 198 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 200 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 202 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 204 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 206 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 208 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 210 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 212 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 214 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 216 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 218 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 220 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 222 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 224 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 226 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 228 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 230 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 232 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 234 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 236 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 238 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 240 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 242 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 244 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 246 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 248 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 250 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 252 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 254 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 256 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 258 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 260 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 262 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 264 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 266 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 268 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 270 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 272 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 274 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 275 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 276 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 278 279 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 281 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 283 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 285 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 287 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 289 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 291 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 293 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 295 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 297 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 299 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 301 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 303}; 304 305static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 306 { 307 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 308 .ethter_type = cpu_to_le16(ETH_P_LLDP), 309 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 310 .i_port_bitmap = 0x1, 311 }, 312}; 313 314static const struct key_info meta_data_key_info[] = { 315 { PACKET_TYPE_ID, 6 }, 316 { IP_FRAGEMENT, 1 }, 317 { ROCE_TYPE, 1 }, 318 { NEXT_KEY, 5 }, 319 { VLAN_NUMBER, 2 }, 320 { SRC_VPORT, 12 }, 321 { DST_VPORT, 12 }, 322 { TUNNEL_PACKET, 1 }, 323}; 324 325static const struct key_info tuple_key_info[] = { 326 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 327 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 328 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 329 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 330 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 331 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 332 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 333 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 334 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 335 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 336 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 337 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 338 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 339 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 340 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 341 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 342 { INNER_DST_MAC, 48, KEY_OPT_MAC, 343 offsetof(struct hclge_fd_rule, tuples.dst_mac), 344 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 345 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 346 offsetof(struct hclge_fd_rule, tuples.src_mac), 347 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 348 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 349 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 350 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 351 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 352 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 353 offsetof(struct hclge_fd_rule, tuples.ether_proto), 354 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 355 { INNER_L2_RSV, 16, KEY_OPT_LE16, 356 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 357 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 358 { INNER_IP_TOS, 8, KEY_OPT_U8, 359 offsetof(struct hclge_fd_rule, tuples.ip_tos), 360 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 361 { INNER_IP_PROTO, 8, KEY_OPT_U8, 362 offsetof(struct hclge_fd_rule, tuples.ip_proto), 363 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 364 { INNER_SRC_IP, 32, KEY_OPT_IP, 365 offsetof(struct hclge_fd_rule, tuples.src_ip), 366 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 367 { INNER_DST_IP, 32, KEY_OPT_IP, 368 offsetof(struct hclge_fd_rule, tuples.dst_ip), 369 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 370 { INNER_L3_RSV, 16, KEY_OPT_LE16, 371 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 372 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 373 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 374 offsetof(struct hclge_fd_rule, tuples.src_port), 375 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 376 { INNER_DST_PORT, 16, KEY_OPT_LE16, 377 offsetof(struct hclge_fd_rule, tuples.dst_port), 378 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 379 { INNER_L4_RSV, 32, KEY_OPT_LE32, 380 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 381 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 382}; 383 384/** 385 * hclge_cmd_send - send command to command queue 386 * @hw: pointer to the hw struct 387 * @desc: prefilled descriptor for describing the command 388 * @num : the number of descriptors to be sent 389 * 390 * This is the main send command for command queue, it 391 * sends the queue, cleans the queue, etc 392 **/ 393int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 394{ 395 return hclge_comm_cmd_send(&hw->hw, desc, num); 396} 397 398static void hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 399 int num, bool is_special) 400{ 401 int i; 402 403 trace_hclge_pf_cmd_send(hw, desc, 0, num); 404 405 if (!is_special) { 406 for (i = 1; i < num; i++) 407 trace_hclge_pf_cmd_send(hw, &desc[i], i, num); 408 } else { 409 for (i = 1; i < num; i++) 410 trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i], 411 i, num); 412 } 413} 414 415static void hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, 416 int num, bool is_special) 417{ 418 int i; 419 420 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 421 return; 422 423 trace_hclge_pf_cmd_get(hw, desc, 0, num); 424 425 if (!is_special) { 426 for (i = 1; i < num; i++) 427 trace_hclge_pf_cmd_get(hw, &desc[i], i, num); 428 } else { 429 for (i = 1; i < num; i++) 430 trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i], 431 i, num); 432 } 433} 434 435static const struct hclge_comm_cmq_ops hclge_cmq_ops = { 436 .trace_cmd_send = hclge_trace_cmd_send, 437 .trace_cmd_get = hclge_trace_cmd_get, 438}; 439 440static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 441{ 442#define HCLGE_MAC_CMD_NUM 21 443 444 u64 *data = (u64 *)(&hdev->mac_stats); 445 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 446 __le64 *desc_data; 447 u32 data_size; 448 int ret; 449 u32 i; 450 451 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 452 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 453 if (ret) { 454 dev_err(&hdev->pdev->dev, 455 "Get MAC pkt stats fail, status = %d.\n", ret); 456 457 return ret; 458 } 459 460 /* The first desc has a 64-bit header, so data size need to minus 1 */ 461 data_size = sizeof(desc) / (sizeof(u64)) - 1; 462 463 desc_data = (__le64 *)(&desc[0].data[0]); 464 for (i = 0; i < data_size; i++) { 465 /* data memory is continuous becase only the first desc has a 466 * header in this command 467 */ 468 *data += le64_to_cpu(*desc_data); 469 data++; 470 desc_data++; 471 } 472 473 return 0; 474} 475 476static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 477{ 478#define HCLGE_REG_NUM_PER_DESC 4 479 480 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 481 u64 *data = (u64 *)(&hdev->mac_stats); 482 struct hclge_desc *desc; 483 __le64 *desc_data; 484 u32 data_size; 485 u32 desc_num; 486 int ret; 487 u32 i; 488 489 /* The first desc has a 64-bit header, so need to consider it */ 490 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 491 492 /* This may be called inside atomic sections, 493 * so GFP_ATOMIC is more suitable here 494 */ 495 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 496 if (!desc) 497 return -ENOMEM; 498 499 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 500 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 501 if (ret) { 502 kfree(desc); 503 return ret; 504 } 505 506 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 507 508 desc_data = (__le64 *)(&desc[0].data[0]); 509 for (i = 0; i < data_size; i++) { 510 /* data memory is continuous becase only the first desc has a 511 * header in this command 512 */ 513 *data += le64_to_cpu(*desc_data); 514 data++; 515 desc_data++; 516 } 517 518 kfree(desc); 519 520 return 0; 521} 522 523static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 524{ 525 struct hclge_desc desc; 526 int ret; 527 528 /* Driver needs total register number of both valid registers and 529 * reserved registers, but the old firmware only returns number 530 * of valid registers in device V2. To be compatible with these 531 * devices, driver uses a fixed value. 532 */ 533 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 534 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 535 return 0; 536 } 537 538 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 539 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 540 if (ret) { 541 dev_err(&hdev->pdev->dev, 542 "failed to query mac statistic reg number, ret = %d\n", 543 ret); 544 return ret; 545 } 546 547 *reg_num = le32_to_cpu(desc.data[0]); 548 if (*reg_num == 0) { 549 dev_err(&hdev->pdev->dev, 550 "mac statistic reg number is invalid!\n"); 551 return -ENODATA; 552 } 553 554 return 0; 555} 556 557int hclge_mac_update_stats(struct hclge_dev *hdev) 558{ 559 /* The firmware supports the new statistics acquisition method */ 560 if (hdev->ae_dev->dev_specs.mac_stats_num) 561 return hclge_mac_update_stats_complete(hdev); 562 else 563 return hclge_mac_update_stats_defective(hdev); 564} 565 566static int hclge_comm_get_count(struct hclge_dev *hdev, 567 const struct hclge_comm_stats_str strs[], 568 u32 size) 569{ 570 int count = 0; 571 u32 i; 572 573 for (i = 0; i < size; i++) 574 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 575 count++; 576 577 return count; 578} 579 580static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 581 const struct hclge_comm_stats_str strs[], 582 int size, u64 *data) 583{ 584 u64 *buf = data; 585 int i; 586 587 for (i = 0; i < size; i++) { 588 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 589 continue; 590 591 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 592 buf++; 593 } 594 595 return buf; 596} 597 598static void hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 599 const struct hclge_comm_stats_str strs[], 600 int size, u8 **data) 601{ 602 int i; 603 604 if (stringset != ETH_SS_STATS) 605 return; 606 607 for (i = 0; i < size; i++) { 608 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 609 continue; 610 611 ethtool_puts(data, strs[i].desc); 612 } 613} 614 615static void hclge_update_stats_for_all(struct hclge_dev *hdev) 616{ 617 struct hnae3_handle *handle; 618 int status; 619 620 handle = &hdev->vport[0].nic; 621 if (handle->client) { 622 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 623 if (status) { 624 dev_err(&hdev->pdev->dev, 625 "Update TQPS stats fail, status = %d.\n", 626 status); 627 } 628 } 629 630 hclge_update_fec_stats(hdev); 631 632 status = hclge_mac_update_stats(hdev); 633 if (status) 634 dev_err(&hdev->pdev->dev, 635 "Update MAC stats fail, status = %d.\n", status); 636} 637 638static void hclge_update_stats(struct hnae3_handle *handle) 639{ 640 struct hclge_vport *vport = hclge_get_vport(handle); 641 struct hclge_dev *hdev = vport->back; 642 int status; 643 644 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 645 return; 646 647 status = hclge_mac_update_stats(hdev); 648 if (status) 649 dev_err(&hdev->pdev->dev, 650 "Update MAC stats fail, status = %d.\n", 651 status); 652 653 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 654 if (status) 655 dev_err(&hdev->pdev->dev, 656 "Update TQPS stats fail, status = %d.\n", 657 status); 658 659 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 660} 661 662static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 663{ 664#define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 665 HNAE3_SUPPORT_PHY_LOOPBACK | \ 666 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 667 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 668 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 669 670 struct hclge_vport *vport = hclge_get_vport(handle); 671 struct hclge_dev *hdev = vport->back; 672 int count = 0; 673 674 /* Loopback test support rules: 675 * mac: only GE mode support 676 * serdes: all mac mode will support include GE/XGE/LGE/CGE 677 * phy: only support when phy device exist on board 678 */ 679 if (stringset == ETH_SS_TEST) { 680 /* clear loopback bit flags at first */ 681 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 682 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 683 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 684 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 685 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 686 count += 1; 687 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 688 } 689 690 if (hdev->ae_dev->dev_specs.hilink_version != 691 HCLGE_HILINK_H60) { 692 count += 1; 693 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 694 } 695 696 count += 1; 697 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 698 count += 1; 699 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 700 701 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 702 hdev->hw.mac.phydev->drv->set_loopback) || 703 hnae3_dev_phy_imp_supported(hdev)) { 704 count += 1; 705 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 706 } 707 } else if (stringset == ETH_SS_STATS) { 708 count = hclge_comm_get_count(hdev, g_mac_stats_string, 709 ARRAY_SIZE(g_mac_stats_string)) + 710 hclge_comm_tqps_get_sset_count(handle); 711 } 712 713 return count; 714} 715 716static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 717 u8 **data) 718{ 719 struct hclge_vport *vport = hclge_get_vport(handle); 720 struct hclge_dev *hdev = vport->back; 721 const char *str; 722 int size; 723 724 if (stringset == ETH_SS_STATS) { 725 size = ARRAY_SIZE(g_mac_stats_string); 726 hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 727 size, data); 728 hclge_comm_tqps_get_strings(handle, data); 729 } else if (stringset == ETH_SS_TEST) { 730 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 731 str = hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL]; 732 ethtool_puts(data, str); 733 } 734 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 735 str = hns3_nic_test_strs[HNAE3_LOOP_APP]; 736 ethtool_puts(data, str); 737 } 738 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 739 str = hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES]; 740 ethtool_puts(data, str); 741 } 742 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 743 str = hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES]; 744 ethtool_puts(data, str); 745 } 746 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 747 str = hns3_nic_test_strs[HNAE3_LOOP_PHY]; 748 ethtool_puts(data, str); 749 } 750 } 751} 752 753static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 754{ 755 struct hclge_vport *vport = hclge_get_vport(handle); 756 struct hclge_dev *hdev = vport->back; 757 u64 *p; 758 759 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 760 ARRAY_SIZE(g_mac_stats_string), data); 761 p = hclge_comm_tqps_get_stats(handle, p); 762} 763 764static void hclge_get_mac_stat(struct hnae3_handle *handle, 765 struct hns3_mac_stats *mac_stats) 766{ 767 struct hclge_vport *vport = hclge_get_vport(handle); 768 struct hclge_dev *hdev = vport->back; 769 770 hclge_update_stats(handle); 771 772 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 773 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 774} 775 776static int hclge_parse_func_status(struct hclge_dev *hdev, 777 struct hclge_func_status_cmd *status) 778{ 779#define HCLGE_MAC_ID_MASK 0xF 780 781 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 782 return -EINVAL; 783 784 /* Set the pf to main pf */ 785 if (status->pf_state & HCLGE_PF_STATE_MAIN) 786 hdev->flag |= HCLGE_FLAG_MAIN; 787 else 788 hdev->flag &= ~HCLGE_FLAG_MAIN; 789 790 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 791 return 0; 792} 793 794static int hclge_query_function_status(struct hclge_dev *hdev) 795{ 796#define HCLGE_QUERY_MAX_CNT 5 797 798 struct hclge_func_status_cmd *req; 799 struct hclge_desc desc; 800 int timeout = 0; 801 int ret; 802 803 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 804 req = (struct hclge_func_status_cmd *)desc.data; 805 806 do { 807 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 808 if (ret) { 809 dev_err(&hdev->pdev->dev, 810 "query function status failed %d.\n", ret); 811 return ret; 812 } 813 814 /* Check pf reset is done */ 815 if (req->pf_state) 816 break; 817 usleep_range(1000, 2000); 818 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 819 820 return hclge_parse_func_status(hdev, req); 821} 822 823static int hclge_query_pf_resource(struct hclge_dev *hdev) 824{ 825 struct hclge_pf_res_cmd *req; 826 struct hclge_desc desc; 827 int ret; 828 829 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 830 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 831 if (ret) { 832 dev_err(&hdev->pdev->dev, 833 "query pf resource failed %d.\n", ret); 834 return ret; 835 } 836 837 req = (struct hclge_pf_res_cmd *)desc.data; 838 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 839 le16_to_cpu(req->ext_tqp_num); 840 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 841 842 if (req->tx_buf_size) 843 hdev->tx_buf_size = 844 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 845 else 846 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 847 848 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 849 850 if (req->dv_buf_size) 851 hdev->dv_buf_size = 852 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 853 else 854 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 855 856 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 857 858 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 859 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 860 dev_err(&hdev->pdev->dev, 861 "only %u msi resources available, not enough for pf(min:2).\n", 862 hdev->num_nic_msi); 863 return -EINVAL; 864 } 865 866 if (hnae3_dev_roce_supported(hdev)) { 867 hdev->num_roce_msi = 868 le16_to_cpu(req->pf_intr_vector_number_roce); 869 870 /* PF should have NIC vectors and Roce vectors, 871 * NIC vectors are queued before Roce vectors. 872 */ 873 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 874 } else { 875 hdev->num_msi = hdev->num_nic_msi; 876 } 877 878 return 0; 879} 880 881static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 882{ 883 switch (speed_cmd) { 884 case HCLGE_FW_MAC_SPEED_10M: 885 *speed = HCLGE_MAC_SPEED_10M; 886 break; 887 case HCLGE_FW_MAC_SPEED_100M: 888 *speed = HCLGE_MAC_SPEED_100M; 889 break; 890 case HCLGE_FW_MAC_SPEED_1G: 891 *speed = HCLGE_MAC_SPEED_1G; 892 break; 893 case HCLGE_FW_MAC_SPEED_10G: 894 *speed = HCLGE_MAC_SPEED_10G; 895 break; 896 case HCLGE_FW_MAC_SPEED_25G: 897 *speed = HCLGE_MAC_SPEED_25G; 898 break; 899 case HCLGE_FW_MAC_SPEED_40G: 900 *speed = HCLGE_MAC_SPEED_40G; 901 break; 902 case HCLGE_FW_MAC_SPEED_50G: 903 *speed = HCLGE_MAC_SPEED_50G; 904 break; 905 case HCLGE_FW_MAC_SPEED_100G: 906 *speed = HCLGE_MAC_SPEED_100G; 907 break; 908 case HCLGE_FW_MAC_SPEED_200G: 909 *speed = HCLGE_MAC_SPEED_200G; 910 break; 911 default: 912 return -EINVAL; 913 } 914 915 return 0; 916} 917 918static const struct hclge_speed_bit_map speed_bit_map[] = { 919 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 920 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 921 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 922 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 923 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 924 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 925 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS}, 926 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS}, 927 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS}, 928}; 929 930static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 931{ 932 u16 i; 933 934 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 935 if (speed == speed_bit_map[i].speed) { 936 *speed_bit = speed_bit_map[i].speed_bit; 937 return 0; 938 } 939 } 940 941 return -EINVAL; 942} 943 944static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 945{ 946 struct hclge_vport *vport = hclge_get_vport(handle); 947 struct hclge_dev *hdev = vport->back; 948 u32 speed_ability = hdev->hw.mac.speed_ability; 949 u32 speed_bit = 0; 950 int ret; 951 952 ret = hclge_get_speed_bit(speed, &speed_bit); 953 if (ret) 954 return ret; 955 956 if (speed_bit & speed_ability) 957 return 0; 958 959 return -EINVAL; 960} 961 962static void hclge_update_fec_support(struct hclge_mac *mac) 963{ 964 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 965 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 966 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 967 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 968 969 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 970 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 971 mac->supported); 972 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 973 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 974 mac->supported); 975 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 976 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 977 mac->supported); 978 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 979 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 980 mac->supported); 981} 982 983static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = { 984 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT}, 985 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT}, 986 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT}, 987 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT}, 988 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT}, 989 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT}, 990 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT}, 991 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 992 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 993 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 994}; 995 996static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = { 997 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT}, 998 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT}, 999 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT}, 1000 {HCLGE_SUPPORT_100G_R4_BIT, 1001 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT}, 1002 {HCLGE_SUPPORT_100G_R2_BIT, 1003 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT}, 1004 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1005 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 1006 {HCLGE_SUPPORT_200G_R4_BIT, 1007 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 1008}; 1009 1010static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = { 1011 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT}, 1012 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT}, 1013 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT}, 1014 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT}, 1015 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT}, 1016 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT}, 1017 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT}, 1018 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1019 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 1020 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 1021}; 1022 1023static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = { 1024 {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, 1025 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, 1026 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT}, 1027 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT}, 1028 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT}, 1029 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT}, 1030 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT}, 1031 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT}, 1032 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1033 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 1034 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 1035}; 1036 1037static void hclge_convert_setting_sr(u16 speed_ability, 1038 unsigned long *link_mode) 1039{ 1040 int i; 1041 1042 for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) { 1043 if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit) 1044 linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode, 1045 link_mode); 1046 } 1047} 1048 1049static void hclge_convert_setting_lr(u16 speed_ability, 1050 unsigned long *link_mode) 1051{ 1052 int i; 1053 1054 for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) { 1055 if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit) 1056 linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode, 1057 link_mode); 1058 } 1059} 1060 1061static void hclge_convert_setting_cr(u16 speed_ability, 1062 unsigned long *link_mode) 1063{ 1064 int i; 1065 1066 for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) { 1067 if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit) 1068 linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode, 1069 link_mode); 1070 } 1071} 1072 1073static void hclge_convert_setting_kr(u16 speed_ability, 1074 unsigned long *link_mode) 1075{ 1076 int i; 1077 1078 for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) { 1079 if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit) 1080 linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode, 1081 link_mode); 1082 } 1083} 1084 1085static void hclge_convert_setting_fec(struct hclge_mac *mac) 1086{ 1087 /* If firmware has reported fec_ability, don't need to convert by speed */ 1088 if (mac->fec_ability) 1089 goto out; 1090 1091 switch (mac->speed) { 1092 case HCLGE_MAC_SPEED_10G: 1093 case HCLGE_MAC_SPEED_40G: 1094 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1095 BIT(HNAE3_FEC_NONE); 1096 break; 1097 case HCLGE_MAC_SPEED_25G: 1098 case HCLGE_MAC_SPEED_50G: 1099 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1100 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1101 break; 1102 case HCLGE_MAC_SPEED_100G: 1103 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1104 BIT(HNAE3_FEC_NONE); 1105 break; 1106 case HCLGE_MAC_SPEED_200G: 1107 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1108 BIT(HNAE3_FEC_LLRS); 1109 break; 1110 default: 1111 mac->fec_ability = 0; 1112 break; 1113 } 1114 1115out: 1116 hclge_update_fec_support(mac); 1117} 1118 1119static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1120 u16 speed_ability) 1121{ 1122 struct hclge_mac *mac = &hdev->hw.mac; 1123 1124 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1125 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1126 mac->supported); 1127 1128 hclge_convert_setting_sr(speed_ability, mac->supported); 1129 hclge_convert_setting_lr(speed_ability, mac->supported); 1130 hclge_convert_setting_cr(speed_ability, mac->supported); 1131 if (hnae3_dev_fec_supported(hdev)) 1132 hclge_convert_setting_fec(mac); 1133 1134 if (hnae3_dev_pause_supported(hdev)) 1135 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1136 1137 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1138 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1139} 1140 1141static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1142 u16 speed_ability) 1143{ 1144 struct hclge_mac *mac = &hdev->hw.mac; 1145 1146 hclge_convert_setting_kr(speed_ability, mac->supported); 1147 if (hnae3_dev_fec_supported(hdev)) 1148 hclge_convert_setting_fec(mac); 1149 1150 if (hnae3_dev_pause_supported(hdev)) 1151 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1152 1153 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1154 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1155} 1156 1157static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1158 u16 speed_ability) 1159{ 1160 unsigned long *supported = hdev->hw.mac.supported; 1161 1162 /* default to support all speed for GE port */ 1163 if (!speed_ability) 1164 speed_ability = HCLGE_SUPPORT_GE; 1165 1166 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1167 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1168 supported); 1169 1170 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1171 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1172 supported); 1173 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1174 supported); 1175 } 1176 1177 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1178 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1179 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1180 } 1181 1182 if (hnae3_dev_pause_supported(hdev)) { 1183 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1184 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1185 } 1186 1187 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1188 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1189} 1190 1191static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1192{ 1193 u8 media_type = hdev->hw.mac.media_type; 1194 1195 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1196 hclge_parse_fiber_link_mode(hdev, speed_ability); 1197 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1198 hclge_parse_copper_link_mode(hdev, speed_ability); 1199 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1200 hclge_parse_backplane_link_mode(hdev, speed_ability); 1201} 1202 1203static u32 hclge_get_max_speed(u16 speed_ability) 1204{ 1205 if (speed_ability & HCLGE_SUPPORT_200G_BITS) 1206 return HCLGE_MAC_SPEED_200G; 1207 1208 if (speed_ability & HCLGE_SUPPORT_100G_BITS) 1209 return HCLGE_MAC_SPEED_100G; 1210 1211 if (speed_ability & HCLGE_SUPPORT_50G_BITS) 1212 return HCLGE_MAC_SPEED_50G; 1213 1214 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1215 return HCLGE_MAC_SPEED_40G; 1216 1217 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1218 return HCLGE_MAC_SPEED_25G; 1219 1220 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1221 return HCLGE_MAC_SPEED_10G; 1222 1223 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1224 return HCLGE_MAC_SPEED_1G; 1225 1226 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1227 return HCLGE_MAC_SPEED_100M; 1228 1229 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1230 return HCLGE_MAC_SPEED_10M; 1231 1232 return HCLGE_MAC_SPEED_1G; 1233} 1234 1235static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1236{ 1237#define HCLGE_TX_SPARE_SIZE_UNIT 4096 1238#define SPEED_ABILITY_EXT_SHIFT 8 1239 1240 struct hclge_cfg_param_cmd *req; 1241 u64 mac_addr_tmp_high; 1242 u16 speed_ability_ext; 1243 u64 mac_addr_tmp; 1244 unsigned int i; 1245 1246 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1247 1248 /* get the configuration */ 1249 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1250 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1251 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1252 HCLGE_CFG_TQP_DESC_N_M, 1253 HCLGE_CFG_TQP_DESC_N_S); 1254 1255 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1256 HCLGE_CFG_PHY_ADDR_M, 1257 HCLGE_CFG_PHY_ADDR_S); 1258 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1259 HCLGE_CFG_MEDIA_TP_M, 1260 HCLGE_CFG_MEDIA_TP_S); 1261 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1262 HCLGE_CFG_RX_BUF_LEN_M, 1263 HCLGE_CFG_RX_BUF_LEN_S); 1264 /* get mac_address */ 1265 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1266 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1267 HCLGE_CFG_MAC_ADDR_H_M, 1268 HCLGE_CFG_MAC_ADDR_H_S); 1269 1270 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1271 1272 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1273 HCLGE_CFG_DEFAULT_SPEED_M, 1274 HCLGE_CFG_DEFAULT_SPEED_S); 1275 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1276 HCLGE_CFG_RSS_SIZE_M, 1277 HCLGE_CFG_RSS_SIZE_S); 1278 1279 for (i = 0; i < ETH_ALEN; i++) 1280 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1281 1282 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1283 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1284 1285 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1286 HCLGE_CFG_SPEED_ABILITY_M, 1287 HCLGE_CFG_SPEED_ABILITY_S); 1288 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1289 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1290 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1291 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1292 1293 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1294 HCLGE_CFG_VLAN_FLTR_CAP_M, 1295 HCLGE_CFG_VLAN_FLTR_CAP_S); 1296 1297 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1298 HCLGE_CFG_UMV_TBL_SPACE_M, 1299 HCLGE_CFG_UMV_TBL_SPACE_S); 1300 1301 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1302 HCLGE_CFG_PF_RSS_SIZE_M, 1303 HCLGE_CFG_PF_RSS_SIZE_S); 1304 1305 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1306 * power of 2, instead of reading out directly. This would 1307 * be more flexible for future changes and expansions. 1308 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1309 * it does not make sense if PF's field is 0. In this case, PF and VF 1310 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1311 */ 1312 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1313 1U << cfg->pf_rss_size_max : 1314 cfg->vf_rss_size_max; 1315 1316 /* The unit of the tx spare buffer size queried from configuration 1317 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1318 * needed here. 1319 */ 1320 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1321 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1322 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1323 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1324} 1325 1326/* hclge_get_cfg: query the static parameter from flash 1327 * @hdev: pointer to struct hclge_dev 1328 * @hcfg: the config structure to be getted 1329 */ 1330static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1331{ 1332 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1333 struct hclge_cfg_param_cmd *req; 1334 unsigned int i; 1335 int ret; 1336 1337 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1338 u32 offset = 0; 1339 1340 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1341 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1342 true); 1343 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1344 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1345 /* Len should be united by 4 bytes when send to hardware */ 1346 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1347 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1348 req->offset = cpu_to_le32(offset); 1349 } 1350 1351 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1352 if (ret) { 1353 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1354 return ret; 1355 } 1356 1357 hclge_parse_cfg(hcfg, desc); 1358 1359 return 0; 1360} 1361 1362static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1363{ 1364#define HCLGE_MAX_NON_TSO_BD_NUM 8U 1365 1366 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1367 1368 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1369 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1370 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1371 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1372 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1373 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1374 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1375 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1376 ae_dev->dev_specs.tnl_num = 0; 1377} 1378 1379static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1380 struct hclge_desc *desc) 1381{ 1382 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1383 struct hclge_dev_specs_0_cmd *req0; 1384 struct hclge_dev_specs_1_cmd *req1; 1385 1386 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1387 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1388 1389 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1390 ae_dev->dev_specs.rss_ind_tbl_size = 1391 le16_to_cpu(req0->rss_ind_tbl_size); 1392 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1393 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1394 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1395 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1396 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1397 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1398 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1399 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1400 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1401 ae_dev->dev_specs.hilink_version = req1->hilink_version; 1402} 1403 1404static void hclge_check_dev_specs(struct hclge_dev *hdev) 1405{ 1406 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1407 1408 if (!dev_specs->max_non_tso_bd_num) 1409 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1410 if (!dev_specs->rss_ind_tbl_size) 1411 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1412 if (!dev_specs->rss_key_size) 1413 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1414 if (!dev_specs->max_tm_rate) 1415 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1416 if (!dev_specs->max_qset_num) 1417 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1418 if (!dev_specs->max_int_gl) 1419 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1420 if (!dev_specs->max_frm_size) 1421 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1422 if (!dev_specs->umv_size) 1423 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1424} 1425 1426static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1427{ 1428 u32 reg_num = 0; 1429 int ret; 1430 1431 ret = hclge_mac_query_reg_num(hdev, ®_num); 1432 if (ret && ret != -EOPNOTSUPP) 1433 return ret; 1434 1435 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1436 return 0; 1437} 1438 1439static int hclge_query_dev_specs(struct hclge_dev *hdev) 1440{ 1441 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1442 int ret; 1443 int i; 1444 1445 ret = hclge_query_mac_stats_num(hdev); 1446 if (ret) 1447 return ret; 1448 1449 /* set default specifications as devices lower than version V3 do not 1450 * support querying specifications from firmware. 1451 */ 1452 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1453 hclge_set_default_dev_specs(hdev); 1454 return 0; 1455 } 1456 1457 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1458 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1459 true); 1460 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1461 } 1462 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1463 1464 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1465 if (ret) 1466 return ret; 1467 1468 hclge_parse_dev_specs(hdev, desc); 1469 hclge_check_dev_specs(hdev); 1470 1471 return 0; 1472} 1473 1474static int hclge_get_cap(struct hclge_dev *hdev) 1475{ 1476 int ret; 1477 1478 ret = hclge_query_function_status(hdev); 1479 if (ret) { 1480 dev_err(&hdev->pdev->dev, 1481 "query function status error %d.\n", ret); 1482 return ret; 1483 } 1484 1485 /* get pf resource */ 1486 return hclge_query_pf_resource(hdev); 1487} 1488 1489static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1490{ 1491#define HCLGE_MIN_TX_DESC 64 1492#define HCLGE_MIN_RX_DESC 64 1493 1494 if (!is_kdump_kernel()) 1495 return; 1496 1497 dev_info(&hdev->pdev->dev, 1498 "Running kdump kernel. Using minimal resources\n"); 1499 1500 /* minimal queue pairs equals to the number of vports */ 1501 hdev->num_tqps = hdev->num_req_vfs + 1; 1502 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1503 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1504} 1505 1506static void hclge_init_tc_config(struct hclge_dev *hdev) 1507{ 1508 unsigned int i; 1509 1510 if (hdev->tc_max > HNAE3_MAX_TC || 1511 hdev->tc_max < 1) { 1512 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1513 hdev->tc_max); 1514 hdev->tc_max = 1; 1515 } 1516 1517 /* Dev does not support DCB */ 1518 if (!hnae3_dev_dcb_supported(hdev)) { 1519 hdev->tc_max = 1; 1520 hdev->pfc_max = 0; 1521 } else { 1522 hdev->pfc_max = hdev->tc_max; 1523 } 1524 1525 hdev->tm_info.num_tc = 1; 1526 1527 /* Currently not support uncontiuous tc */ 1528 for (i = 0; i < hdev->tm_info.num_tc; i++) 1529 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1530 1531 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1532} 1533 1534static int hclge_configure(struct hclge_dev *hdev) 1535{ 1536 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1537 struct hclge_cfg cfg; 1538 int ret; 1539 1540 ret = hclge_get_cfg(hdev, &cfg); 1541 if (ret) 1542 return ret; 1543 1544 hdev->base_tqp_pid = 0; 1545 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1546 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1547 hdev->rx_buf_len = cfg.rx_buf_len; 1548 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1549 hdev->hw.mac.media_type = cfg.media_type; 1550 hdev->hw.mac.phy_addr = cfg.phy_addr; 1551 hdev->num_tx_desc = cfg.tqp_desc_num; 1552 hdev->num_rx_desc = cfg.tqp_desc_num; 1553 hdev->tm_info.num_pg = 1; 1554 hdev->tc_max = cfg.tc_num; 1555 hdev->tm_info.hw_pfc_map = 0; 1556 if (cfg.umv_space) 1557 hdev->wanted_umv_size = cfg.umv_space; 1558 else 1559 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1560 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1561 hdev->gro_en = true; 1562 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1563 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1564 1565 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1566 hdev->fd_en = true; 1567 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1568 } 1569 1570 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1571 if (ret) { 1572 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1573 cfg.default_speed, ret); 1574 return ret; 1575 } 1576 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1577 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1578 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1579 1580 hclge_parse_link_mode(hdev, cfg.speed_ability); 1581 1582 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1583 1584 hclge_init_tc_config(hdev); 1585 hclge_init_kdump_kernel_config(hdev); 1586 1587 return ret; 1588} 1589 1590static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1591 u16 tso_mss_max) 1592{ 1593 struct hclge_cfg_tso_status_cmd *req; 1594 struct hclge_desc desc; 1595 1596 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1597 1598 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1599 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1600 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1601 1602 return hclge_cmd_send(&hdev->hw, &desc, 1); 1603} 1604 1605static int hclge_config_gro(struct hclge_dev *hdev) 1606{ 1607 struct hclge_cfg_gro_status_cmd *req; 1608 struct hclge_desc desc; 1609 int ret; 1610 1611 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1612 return 0; 1613 1614 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1615 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1616 1617 req->gro_en = hdev->gro_en ? 1 : 0; 1618 1619 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1620 if (ret) 1621 dev_err(&hdev->pdev->dev, 1622 "GRO hardware config cmd failed, ret = %d\n", ret); 1623 1624 return ret; 1625} 1626 1627static int hclge_alloc_tqps(struct hclge_dev *hdev) 1628{ 1629 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1630 struct hclge_comm_tqp *tqp; 1631 int i; 1632 1633 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1634 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1635 if (!hdev->htqp) 1636 return -ENOMEM; 1637 1638 tqp = hdev->htqp; 1639 1640 for (i = 0; i < hdev->num_tqps; i++) { 1641 tqp->dev = &hdev->pdev->dev; 1642 tqp->index = i; 1643 1644 tqp->q.ae_algo = &ae_algo; 1645 tqp->q.buf_size = hdev->rx_buf_len; 1646 tqp->q.tx_desc_num = hdev->num_tx_desc; 1647 tqp->q.rx_desc_num = hdev->num_rx_desc; 1648 1649 /* need an extended offset to configure queues >= 1650 * HCLGE_TQP_MAX_SIZE_DEV_V2 1651 */ 1652 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1653 tqp->q.io_base = hdev->hw.hw.io_base + 1654 HCLGE_TQP_REG_OFFSET + 1655 i * HCLGE_TQP_REG_SIZE; 1656 else 1657 tqp->q.io_base = hdev->hw.hw.io_base + 1658 HCLGE_TQP_REG_OFFSET + 1659 HCLGE_TQP_EXT_REG_OFFSET + 1660 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1661 HCLGE_TQP_REG_SIZE; 1662 1663 /* when device supports tx push and has device memory, 1664 * the queue can execute push mode or doorbell mode on 1665 * device memory. 1666 */ 1667 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1668 tqp->q.mem_base = hdev->hw.hw.mem_base + 1669 HCLGE_TQP_MEM_OFFSET(hdev, i); 1670 1671 tqp++; 1672 } 1673 1674 return 0; 1675} 1676 1677static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1678 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1679{ 1680 struct hclge_tqp_map_cmd *req; 1681 struct hclge_desc desc; 1682 int ret; 1683 1684 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1685 1686 req = (struct hclge_tqp_map_cmd *)desc.data; 1687 req->tqp_id = cpu_to_le16(tqp_pid); 1688 req->tqp_vf = func_id; 1689 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1690 if (!is_pf) 1691 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1692 req->tqp_vid = cpu_to_le16(tqp_vid); 1693 1694 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1695 if (ret) 1696 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1697 1698 return ret; 1699} 1700 1701static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1702{ 1703 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1704 struct hclge_dev *hdev = vport->back; 1705 int i, alloced; 1706 1707 for (i = 0, alloced = 0; i < hdev->num_tqps && 1708 alloced < num_tqps; i++) { 1709 if (!hdev->htqp[i].alloced) { 1710 hdev->htqp[i].q.handle = &vport->nic; 1711 hdev->htqp[i].q.tqp_index = alloced; 1712 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1713 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1714 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1715 hdev->htqp[i].alloced = true; 1716 alloced++; 1717 } 1718 } 1719 vport->alloc_tqps = alloced; 1720 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1721 vport->alloc_tqps / hdev->tm_info.num_tc); 1722 1723 /* ensure one to one mapping between irq and queue at default */ 1724 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1725 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1726 1727 return 0; 1728} 1729 1730static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1731 u16 num_tx_desc, u16 num_rx_desc) 1732 1733{ 1734 struct hnae3_handle *nic = &vport->nic; 1735 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1736 struct hclge_dev *hdev = vport->back; 1737 int ret; 1738 1739 kinfo->num_tx_desc = num_tx_desc; 1740 kinfo->num_rx_desc = num_rx_desc; 1741 1742 kinfo->rx_buf_len = hdev->rx_buf_len; 1743 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1744 1745 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1746 sizeof(struct hnae3_queue *), GFP_KERNEL); 1747 if (!kinfo->tqp) 1748 return -ENOMEM; 1749 1750 ret = hclge_assign_tqp(vport, num_tqps); 1751 if (ret) 1752 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1753 1754 return ret; 1755} 1756 1757static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1758 struct hclge_vport *vport) 1759{ 1760 struct hnae3_handle *nic = &vport->nic; 1761 struct hnae3_knic_private_info *kinfo; 1762 u16 i; 1763 1764 kinfo = &nic->kinfo; 1765 for (i = 0; i < vport->alloc_tqps; i++) { 1766 struct hclge_comm_tqp *q = 1767 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1768 bool is_pf; 1769 int ret; 1770 1771 is_pf = !(vport->vport_id); 1772 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1773 i, is_pf); 1774 if (ret) 1775 return ret; 1776 } 1777 1778 return 0; 1779} 1780 1781static int hclge_map_tqp(struct hclge_dev *hdev) 1782{ 1783 struct hclge_vport *vport = hdev->vport; 1784 u16 i, num_vport; 1785 1786 num_vport = hdev->num_req_vfs + 1; 1787 for (i = 0; i < num_vport; i++) { 1788 int ret; 1789 1790 ret = hclge_map_tqp_to_vport(hdev, vport); 1791 if (ret) 1792 return ret; 1793 1794 vport++; 1795 } 1796 1797 return 0; 1798} 1799 1800static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1801{ 1802 struct hnae3_handle *nic = &vport->nic; 1803 struct hclge_dev *hdev = vport->back; 1804 int ret; 1805 1806 nic->pdev = hdev->pdev; 1807 nic->ae_algo = &ae_algo; 1808 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1809 MAX_NUMNODES); 1810 nic->kinfo.io_base = hdev->hw.hw.io_base; 1811 1812 ret = hclge_knic_setup(vport, num_tqps, 1813 hdev->num_tx_desc, hdev->num_rx_desc); 1814 if (ret) 1815 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1816 1817 return ret; 1818} 1819 1820static int hclge_alloc_vport(struct hclge_dev *hdev) 1821{ 1822 struct pci_dev *pdev = hdev->pdev; 1823 struct hclge_vport *vport; 1824 u32 tqp_main_vport; 1825 u32 tqp_per_vport; 1826 int num_vport, i; 1827 int ret; 1828 1829 /* We need to alloc a vport for main NIC of PF */ 1830 num_vport = hdev->num_req_vfs + 1; 1831 1832 if (hdev->num_tqps < num_vport) { 1833 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1834 hdev->num_tqps, num_vport); 1835 return -EINVAL; 1836 } 1837 1838 /* Alloc the same number of TQPs for every vport */ 1839 tqp_per_vport = hdev->num_tqps / num_vport; 1840 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1841 1842 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1843 GFP_KERNEL); 1844 if (!vport) 1845 return -ENOMEM; 1846 1847 hdev->vport = vport; 1848 hdev->num_alloc_vport = num_vport; 1849 1850 if (IS_ENABLED(CONFIG_PCI_IOV)) 1851 hdev->num_alloc_vfs = hdev->num_req_vfs; 1852 1853 for (i = 0; i < num_vport; i++) { 1854 vport->back = hdev; 1855 vport->vport_id = i; 1856 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1857 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1858 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1859 vport->port_base_vlan_cfg.tbl_sta = true; 1860 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1861 vport->req_vlan_fltr_en = true; 1862 INIT_LIST_HEAD(&vport->vlan_list); 1863 INIT_LIST_HEAD(&vport->uc_mac_list); 1864 INIT_LIST_HEAD(&vport->mc_mac_list); 1865 spin_lock_init(&vport->mac_list_lock); 1866 1867 if (i == 0) 1868 ret = hclge_vport_setup(vport, tqp_main_vport); 1869 else 1870 ret = hclge_vport_setup(vport, tqp_per_vport); 1871 if (ret) { 1872 dev_err(&pdev->dev, 1873 "vport setup failed for vport %d, %d\n", 1874 i, ret); 1875 return ret; 1876 } 1877 1878 vport++; 1879 } 1880 1881 return 0; 1882} 1883 1884static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1885 struct hclge_pkt_buf_alloc *buf_alloc) 1886{ 1887/* TX buffer size is unit by 128 byte */ 1888#define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1889#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1890 struct hclge_tx_buff_alloc_cmd *req; 1891 struct hclge_desc desc; 1892 int ret; 1893 u8 i; 1894 1895 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1896 1897 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1898 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1899 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1900 1901 req->tx_pkt_buff[i] = 1902 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1903 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1904 } 1905 1906 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1907 if (ret) 1908 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1909 ret); 1910 1911 return ret; 1912} 1913 1914static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1915 struct hclge_pkt_buf_alloc *buf_alloc) 1916{ 1917 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1918 1919 if (ret) 1920 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1921 1922 return ret; 1923} 1924 1925static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1926{ 1927 unsigned int i; 1928 u32 cnt = 0; 1929 1930 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1931 if (hdev->hw_tc_map & BIT(i)) 1932 cnt++; 1933 return cnt; 1934} 1935 1936/* Get the number of pfc enabled TCs, which have private buffer */ 1937static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1938 struct hclge_pkt_buf_alloc *buf_alloc) 1939{ 1940 struct hclge_priv_buf *priv; 1941 unsigned int i; 1942 int cnt = 0; 1943 1944 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1945 priv = &buf_alloc->priv_buf[i]; 1946 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1947 priv->enable) 1948 cnt++; 1949 } 1950 1951 return cnt; 1952} 1953 1954/* Get the number of pfc disabled TCs, which have private buffer */ 1955static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1956 struct hclge_pkt_buf_alloc *buf_alloc) 1957{ 1958 struct hclge_priv_buf *priv; 1959 unsigned int i; 1960 int cnt = 0; 1961 1962 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1963 priv = &buf_alloc->priv_buf[i]; 1964 if (hdev->hw_tc_map & BIT(i) && 1965 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1966 priv->enable) 1967 cnt++; 1968 } 1969 1970 return cnt; 1971} 1972 1973static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1974{ 1975 struct hclge_priv_buf *priv; 1976 u32 rx_priv = 0; 1977 int i; 1978 1979 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1980 priv = &buf_alloc->priv_buf[i]; 1981 if (priv->enable) 1982 rx_priv += priv->buf_size; 1983 } 1984 return rx_priv; 1985} 1986 1987static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1988{ 1989 u32 i, total_tx_size = 0; 1990 1991 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1992 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1993 1994 return total_tx_size; 1995} 1996 1997static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1998 struct hclge_pkt_buf_alloc *buf_alloc, 1999 u32 rx_all) 2000{ 2001 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2002 u32 tc_num = hclge_get_tc_num(hdev); 2003 u32 shared_buf, aligned_mps; 2004 u32 rx_priv; 2005 int i; 2006 2007 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2008 2009 if (hnae3_dev_dcb_supported(hdev)) 2010 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2011 hdev->dv_buf_size; 2012 else 2013 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2014 + hdev->dv_buf_size; 2015 2016 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2017 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2018 HCLGE_BUF_SIZE_UNIT); 2019 2020 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2021 if (rx_all < rx_priv + shared_std) 2022 return false; 2023 2024 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2025 buf_alloc->s_buf.buf_size = shared_buf; 2026 if (hnae3_dev_dcb_supported(hdev)) { 2027 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2028 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2029 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2030 HCLGE_BUF_SIZE_UNIT); 2031 } else { 2032 buf_alloc->s_buf.self.high = aligned_mps + 2033 HCLGE_NON_DCB_ADDITIONAL_BUF; 2034 buf_alloc->s_buf.self.low = aligned_mps; 2035 } 2036 2037 if (hnae3_dev_dcb_supported(hdev)) { 2038 hi_thrd = shared_buf - hdev->dv_buf_size; 2039 2040 if (tc_num <= NEED_RESERVE_TC_NUM) 2041 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2042 / BUF_MAX_PERCENT; 2043 2044 if (tc_num) 2045 hi_thrd = hi_thrd / tc_num; 2046 2047 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2048 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2049 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2050 } else { 2051 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2052 lo_thrd = aligned_mps; 2053 } 2054 2055 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2056 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2057 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2058 } 2059 2060 return true; 2061} 2062 2063static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2064 struct hclge_pkt_buf_alloc *buf_alloc) 2065{ 2066 u32 i, total_size; 2067 2068 total_size = hdev->pkt_buf_size; 2069 2070 /* alloc tx buffer for all enabled tc */ 2071 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2072 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2073 2074 if (hdev->hw_tc_map & BIT(i)) { 2075 if (total_size < hdev->tx_buf_size) 2076 return -ENOMEM; 2077 2078 priv->tx_buf_size = hdev->tx_buf_size; 2079 } else { 2080 priv->tx_buf_size = 0; 2081 } 2082 2083 total_size -= priv->tx_buf_size; 2084 } 2085 2086 return 0; 2087} 2088 2089static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2090 struct hclge_pkt_buf_alloc *buf_alloc) 2091{ 2092 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2093 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2094 unsigned int i; 2095 2096 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2097 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2098 2099 priv->enable = 0; 2100 priv->wl.low = 0; 2101 priv->wl.high = 0; 2102 priv->buf_size = 0; 2103 2104 if (!(hdev->hw_tc_map & BIT(i))) 2105 continue; 2106 2107 priv->enable = 1; 2108 2109 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2110 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2111 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2112 HCLGE_BUF_SIZE_UNIT); 2113 } else { 2114 priv->wl.low = 0; 2115 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2116 aligned_mps; 2117 } 2118 2119 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2120 } 2121 2122 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2123} 2124 2125static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2126 struct hclge_pkt_buf_alloc *buf_alloc) 2127{ 2128 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2129 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2130 int i; 2131 2132 /* let the last to be cleared first */ 2133 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2134 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2135 unsigned int mask = BIT((unsigned int)i); 2136 2137 if (hdev->hw_tc_map & mask && 2138 !(hdev->tm_info.hw_pfc_map & mask)) { 2139 /* Clear the no pfc TC private buffer */ 2140 priv->wl.low = 0; 2141 priv->wl.high = 0; 2142 priv->buf_size = 0; 2143 priv->enable = 0; 2144 no_pfc_priv_num--; 2145 } 2146 2147 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2148 no_pfc_priv_num == 0) 2149 break; 2150 } 2151 2152 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2153} 2154 2155static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2156 struct hclge_pkt_buf_alloc *buf_alloc) 2157{ 2158 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2159 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2160 int i; 2161 2162 /* let the last to be cleared first */ 2163 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2164 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2165 unsigned int mask = BIT((unsigned int)i); 2166 2167 if (hdev->hw_tc_map & mask && 2168 hdev->tm_info.hw_pfc_map & mask) { 2169 /* Reduce the number of pfc TC with private buffer */ 2170 priv->wl.low = 0; 2171 priv->enable = 0; 2172 priv->wl.high = 0; 2173 priv->buf_size = 0; 2174 pfc_priv_num--; 2175 } 2176 2177 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2178 pfc_priv_num == 0) 2179 break; 2180 } 2181 2182 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2183} 2184 2185static bool hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2186 struct hclge_pkt_buf_alloc *buf_alloc) 2187{ 2188#define COMPENSATE_BUFFER 0x3C00 2189#define COMPENSATE_HALF_MPS_NUM 5 2190#define PRIV_WL_GAP 0x1800 2191 2192 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2193 u32 tc_num = hclge_get_tc_num(hdev); 2194 u32 half_mps = hdev->mps >> 1; 2195 u32 min_rx_priv; 2196 unsigned int i; 2197 2198 if (tc_num) 2199 rx_priv = rx_priv / tc_num; 2200 2201 if (tc_num <= NEED_RESERVE_TC_NUM) 2202 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2203 2204 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2205 COMPENSATE_HALF_MPS_NUM * half_mps; 2206 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2207 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2208 if (rx_priv < min_rx_priv) 2209 return false; 2210 2211 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2212 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2213 2214 priv->enable = 0; 2215 priv->wl.low = 0; 2216 priv->wl.high = 0; 2217 priv->buf_size = 0; 2218 2219 if (!(hdev->hw_tc_map & BIT(i))) 2220 continue; 2221 2222 priv->enable = 1; 2223 priv->buf_size = rx_priv; 2224 priv->wl.high = rx_priv - hdev->dv_buf_size; 2225 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2226 } 2227 2228 buf_alloc->s_buf.buf_size = 0; 2229 2230 return true; 2231} 2232 2233/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2234 * @hdev: pointer to struct hclge_dev 2235 * @buf_alloc: pointer to buffer calculation data 2236 * @return: 0: calculate successful, negative: fail 2237 */ 2238static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2239 struct hclge_pkt_buf_alloc *buf_alloc) 2240{ 2241 /* When DCB is not supported, rx private buffer is not allocated. */ 2242 if (!hnae3_dev_dcb_supported(hdev)) { 2243 u32 rx_all = hdev->pkt_buf_size; 2244 2245 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2246 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2247 return -ENOMEM; 2248 2249 return 0; 2250 } 2251 2252 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2253 return 0; 2254 2255 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2256 return 0; 2257 2258 /* try to decrease the buffer size */ 2259 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2260 return 0; 2261 2262 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2263 return 0; 2264 2265 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2266 return 0; 2267 2268 return -ENOMEM; 2269} 2270 2271static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2272 struct hclge_pkt_buf_alloc *buf_alloc) 2273{ 2274 struct hclge_rx_priv_buff_cmd *req; 2275 struct hclge_desc desc; 2276 int ret; 2277 int i; 2278 2279 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2280 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2281 2282 /* Alloc private buffer TCs */ 2283 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2284 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2285 2286 req->buf_num[i] = 2287 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2288 req->buf_num[i] |= 2289 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2290 } 2291 2292 req->shared_buf = 2293 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2294 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2295 2296 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2297 if (ret) 2298 dev_err(&hdev->pdev->dev, 2299 "rx private buffer alloc cmd failed %d\n", ret); 2300 2301 return ret; 2302} 2303 2304static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2305 struct hclge_pkt_buf_alloc *buf_alloc) 2306{ 2307 struct hclge_rx_priv_wl_buf *req; 2308 struct hclge_priv_buf *priv; 2309 struct hclge_desc desc[2]; 2310 int i, j; 2311 int ret; 2312 2313 for (i = 0; i < 2; i++) { 2314 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2315 false); 2316 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2317 2318 /* The first descriptor set the NEXT bit to 1 */ 2319 if (i == 0) 2320 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2321 else 2322 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2323 2324 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2325 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2326 2327 priv = &buf_alloc->priv_buf[idx]; 2328 req->tc_wl[j].high = 2329 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2330 req->tc_wl[j].high |= 2331 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2332 req->tc_wl[j].low = 2333 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2334 req->tc_wl[j].low |= 2335 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2336 } 2337 } 2338 2339 /* Send 2 descriptor at one time */ 2340 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2341 if (ret) 2342 dev_err(&hdev->pdev->dev, 2343 "rx private waterline config cmd failed %d\n", 2344 ret); 2345 return ret; 2346} 2347 2348static int hclge_common_thrd_config(struct hclge_dev *hdev, 2349 struct hclge_pkt_buf_alloc *buf_alloc) 2350{ 2351 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2352 struct hclge_rx_com_thrd *req; 2353 struct hclge_desc desc[2]; 2354 struct hclge_tc_thrd *tc; 2355 int i, j; 2356 int ret; 2357 2358 for (i = 0; i < 2; i++) { 2359 hclge_cmd_setup_basic_desc(&desc[i], 2360 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2361 req = (struct hclge_rx_com_thrd *)desc[i].data; 2362 2363 /* The first descriptor set the NEXT bit to 1 */ 2364 if (i == 0) 2365 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2366 else 2367 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2368 2369 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2370 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2371 2372 req->com_thrd[j].high = 2373 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2374 req->com_thrd[j].high |= 2375 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2376 req->com_thrd[j].low = 2377 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2378 req->com_thrd[j].low |= 2379 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2380 } 2381 } 2382 2383 /* Send 2 descriptors at one time */ 2384 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2385 if (ret) 2386 dev_err(&hdev->pdev->dev, 2387 "common threshold config cmd failed %d\n", ret); 2388 return ret; 2389} 2390 2391static int hclge_common_wl_config(struct hclge_dev *hdev, 2392 struct hclge_pkt_buf_alloc *buf_alloc) 2393{ 2394 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2395 struct hclge_rx_com_wl *req; 2396 struct hclge_desc desc; 2397 int ret; 2398 2399 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2400 2401 req = (struct hclge_rx_com_wl *)desc.data; 2402 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2403 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2404 2405 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2406 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2407 2408 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2409 if (ret) 2410 dev_err(&hdev->pdev->dev, 2411 "common waterline config cmd failed %d\n", ret); 2412 2413 return ret; 2414} 2415 2416int hclge_buffer_alloc(struct hclge_dev *hdev) 2417{ 2418 struct hclge_pkt_buf_alloc *pkt_buf; 2419 int ret; 2420 2421 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2422 if (!pkt_buf) 2423 return -ENOMEM; 2424 2425 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2426 if (ret) { 2427 dev_err(&hdev->pdev->dev, 2428 "could not calc tx buffer size for all TCs %d\n", ret); 2429 goto out; 2430 } 2431 2432 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2433 if (ret) { 2434 dev_err(&hdev->pdev->dev, 2435 "could not alloc tx buffers %d\n", ret); 2436 goto out; 2437 } 2438 2439 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2440 if (ret) { 2441 dev_err(&hdev->pdev->dev, 2442 "could not calc rx priv buffer size for all TCs %d\n", 2443 ret); 2444 goto out; 2445 } 2446 2447 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2448 if (ret) { 2449 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2450 ret); 2451 goto out; 2452 } 2453 2454 if (hnae3_dev_dcb_supported(hdev)) { 2455 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2456 if (ret) { 2457 dev_err(&hdev->pdev->dev, 2458 "could not configure rx private waterline %d\n", 2459 ret); 2460 goto out; 2461 } 2462 2463 ret = hclge_common_thrd_config(hdev, pkt_buf); 2464 if (ret) { 2465 dev_err(&hdev->pdev->dev, 2466 "could not configure common threshold %d\n", 2467 ret); 2468 goto out; 2469 } 2470 } 2471 2472 ret = hclge_common_wl_config(hdev, pkt_buf); 2473 if (ret) 2474 dev_err(&hdev->pdev->dev, 2475 "could not configure common waterline %d\n", ret); 2476 2477out: 2478 kfree(pkt_buf); 2479 return ret; 2480} 2481 2482static int hclge_init_roce_base_info(struct hclge_vport *vport) 2483{ 2484 struct hnae3_handle *roce = &vport->roce; 2485 struct hnae3_handle *nic = &vport->nic; 2486 struct hclge_dev *hdev = vport->back; 2487 2488 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2489 2490 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2491 return -EINVAL; 2492 2493 roce->rinfo.base_vector = hdev->num_nic_msi; 2494 2495 roce->rinfo.netdev = nic->kinfo.netdev; 2496 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2497 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2498 2499 roce->pdev = nic->pdev; 2500 roce->ae_algo = nic->ae_algo; 2501 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2502 MAX_NUMNODES); 2503 2504 return 0; 2505} 2506 2507static int hclge_init_msi(struct hclge_dev *hdev) 2508{ 2509 struct pci_dev *pdev = hdev->pdev; 2510 int vectors; 2511 int i; 2512 2513 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2514 hdev->num_msi, 2515 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2516 if (vectors < 0) { 2517 dev_err(&pdev->dev, 2518 "failed(%d) to allocate MSI/MSI-X vectors\n", 2519 vectors); 2520 return vectors; 2521 } 2522 if (vectors < hdev->num_msi) 2523 dev_warn(&hdev->pdev->dev, 2524 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2525 hdev->num_msi, vectors); 2526 2527 hdev->num_msi = vectors; 2528 hdev->num_msi_left = vectors; 2529 2530 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2531 sizeof(u16), GFP_KERNEL); 2532 if (!hdev->vector_status) { 2533 pci_free_irq_vectors(pdev); 2534 return -ENOMEM; 2535 } 2536 2537 for (i = 0; i < hdev->num_msi; i++) 2538 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2539 2540 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2541 sizeof(int), GFP_KERNEL); 2542 if (!hdev->vector_irq) { 2543 pci_free_irq_vectors(pdev); 2544 return -ENOMEM; 2545 } 2546 2547 return 0; 2548} 2549 2550static u8 hclge_check_speed_dup(u8 duplex, int speed) 2551{ 2552 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2553 duplex = HCLGE_MAC_FULL; 2554 2555 return duplex; 2556} 2557 2558static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2559 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2560 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2561 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2562 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2563 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2564 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2565 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2566 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2567 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2568}; 2569 2570static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2571{ 2572 u16 i; 2573 2574 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2575 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2576 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2577 return 0; 2578 } 2579 } 2580 2581 return -EINVAL; 2582} 2583 2584static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2585 u8 duplex, u8 lane_num) 2586{ 2587 struct hclge_config_mac_speed_dup_cmd *req; 2588 struct hclge_desc desc; 2589 u32 speed_fw; 2590 int ret; 2591 2592 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2593 2594 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2595 2596 if (duplex) 2597 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2598 2599 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2600 if (ret) { 2601 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2602 return ret; 2603 } 2604 2605 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2606 speed_fw); 2607 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2608 1); 2609 req->lane_num = lane_num; 2610 2611 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2612 if (ret) { 2613 dev_err(&hdev->pdev->dev, 2614 "mac speed/duplex config cmd failed %d.\n", ret); 2615 return ret; 2616 } 2617 2618 return 0; 2619} 2620 2621int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2622{ 2623 struct hclge_mac *mac = &hdev->hw.mac; 2624 int ret; 2625 2626 duplex = hclge_check_speed_dup(duplex, speed); 2627 if (!mac->support_autoneg && mac->speed == (u32)speed && 2628 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2629 return 0; 2630 2631 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2632 if (ret) 2633 return ret; 2634 2635 hdev->hw.mac.speed = speed; 2636 hdev->hw.mac.duplex = duplex; 2637 if (!lane_num) 2638 hdev->hw.mac.lane_num = lane_num; 2639 2640 return 0; 2641} 2642 2643static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2644 u8 duplex, u8 lane_num) 2645{ 2646 struct hclge_vport *vport = hclge_get_vport(handle); 2647 struct hclge_dev *hdev = vport->back; 2648 int ret; 2649 2650 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2651 2652 if (ret) 2653 return ret; 2654 2655 hdev->hw.mac.req_speed = (u32)speed; 2656 hdev->hw.mac.req_duplex = duplex; 2657 2658 return 0; 2659} 2660 2661static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2662{ 2663 struct hclge_config_auto_neg_cmd *req; 2664 struct hclge_desc desc; 2665 u32 flag = 0; 2666 int ret; 2667 2668 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2669 2670 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2671 if (enable) 2672 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2673 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2674 2675 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2676 if (ret) 2677 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2678 ret); 2679 2680 return ret; 2681} 2682 2683static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2684{ 2685 struct hclge_vport *vport = hclge_get_vport(handle); 2686 struct hclge_dev *hdev = vport->back; 2687 2688 if (!hdev->hw.mac.support_autoneg) { 2689 if (enable) { 2690 dev_err(&hdev->pdev->dev, 2691 "autoneg is not supported by current port\n"); 2692 return -EOPNOTSUPP; 2693 } else { 2694 return 0; 2695 } 2696 } 2697 2698 return hclge_set_autoneg_en(hdev, enable); 2699} 2700 2701static int hclge_get_autoneg(struct hnae3_handle *handle) 2702{ 2703 struct hclge_vport *vport = hclge_get_vport(handle); 2704 struct hclge_dev *hdev = vport->back; 2705 struct phy_device *phydev = hdev->hw.mac.phydev; 2706 2707 if (phydev) 2708 return phydev->autoneg; 2709 2710 return hdev->hw.mac.autoneg; 2711} 2712 2713static int hclge_restart_autoneg(struct hnae3_handle *handle) 2714{ 2715 struct hclge_vport *vport = hclge_get_vport(handle); 2716 struct hclge_dev *hdev = vport->back; 2717 int ret; 2718 2719 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2720 2721 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2722 if (ret) 2723 return ret; 2724 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2725} 2726 2727static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2728{ 2729 struct hclge_vport *vport = hclge_get_vport(handle); 2730 struct hclge_dev *hdev = vport->back; 2731 2732 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2733 return hclge_set_autoneg_en(hdev, !halt); 2734 2735 return 0; 2736} 2737 2738static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2739 struct hclge_desc *desc, u32 desc_len) 2740{ 2741 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2742 u32 desc_index = 0; 2743 u32 data_index = 0; 2744 u32 i; 2745 2746 for (i = 0; i < lane_size; i++) { 2747 if (data_index >= HCLGE_DESC_DATA_LEN) { 2748 desc_index++; 2749 data_index = 0; 2750 } 2751 2752 if (desc_index >= desc_len) 2753 return; 2754 2755 hdev->fec_stats.per_lanes[i] += 2756 le32_to_cpu(desc[desc_index].data[data_index]); 2757 data_index++; 2758 } 2759} 2760 2761static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2762 struct hclge_desc *desc, u32 desc_len) 2763{ 2764 struct hclge_query_fec_stats_cmd *req; 2765 2766 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2767 2768 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2769 hdev->fec_stats.rs_corr_blocks += 2770 le32_to_cpu(req->rs_fec_corr_blocks); 2771 hdev->fec_stats.rs_uncorr_blocks += 2772 le32_to_cpu(req->rs_fec_uncorr_blocks); 2773 hdev->fec_stats.rs_error_blocks += 2774 le32_to_cpu(req->rs_fec_error_blocks); 2775 hdev->fec_stats.base_r_corr_blocks += 2776 le32_to_cpu(req->base_r_fec_corr_blocks); 2777 hdev->fec_stats.base_r_uncorr_blocks += 2778 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2779 2780 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2781} 2782 2783static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2784{ 2785 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2786 int ret; 2787 u32 i; 2788 2789 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2790 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2791 true); 2792 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2793 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2794 } 2795 2796 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2797 if (ret) 2798 return ret; 2799 2800 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2801 2802 return 0; 2803} 2804 2805static void hclge_update_fec_stats(struct hclge_dev *hdev) 2806{ 2807 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2808 int ret; 2809 2810 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2811 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2812 return; 2813 2814 ret = hclge_update_fec_stats_hw(hdev); 2815 if (ret) 2816 dev_err(&hdev->pdev->dev, 2817 "failed to update fec stats, ret = %d\n", ret); 2818 2819 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2820} 2821 2822static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2823 struct ethtool_fec_stats *fec_stats) 2824{ 2825 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2826 fec_stats->uncorrectable_blocks.total = 2827 hdev->fec_stats.rs_uncorr_blocks; 2828} 2829 2830static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2831 struct ethtool_fec_stats *fec_stats) 2832{ 2833 u32 i; 2834 2835 if (hdev->fec_stats.base_r_lane_num == 0 || 2836 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2837 dev_err(&hdev->pdev->dev, 2838 "fec stats lane number(%llu) is invalid\n", 2839 hdev->fec_stats.base_r_lane_num); 2840 return; 2841 } 2842 2843 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2844 fec_stats->corrected_blocks.lanes[i] = 2845 hdev->fec_stats.base_r_corr_per_lanes[i]; 2846 fec_stats->uncorrectable_blocks.lanes[i] = 2847 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2848 } 2849} 2850 2851static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2852 struct ethtool_fec_stats *fec_stats) 2853{ 2854 u32 fec_mode = hdev->hw.mac.fec_mode; 2855 2856 switch (fec_mode) { 2857 case BIT(HNAE3_FEC_RS): 2858 case BIT(HNAE3_FEC_LLRS): 2859 hclge_get_fec_stats_total(hdev, fec_stats); 2860 break; 2861 case BIT(HNAE3_FEC_BASER): 2862 hclge_get_fec_stats_lanes(hdev, fec_stats); 2863 break; 2864 default: 2865 dev_err(&hdev->pdev->dev, 2866 "fec stats is not supported by current fec mode(0x%x)\n", 2867 fec_mode); 2868 break; 2869 } 2870} 2871 2872static void hclge_get_fec_stats(struct hnae3_handle *handle, 2873 struct ethtool_fec_stats *fec_stats) 2874{ 2875 struct hclge_vport *vport = hclge_get_vport(handle); 2876 struct hclge_dev *hdev = vport->back; 2877 u32 fec_mode = hdev->hw.mac.fec_mode; 2878 2879 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2880 fec_mode == BIT(HNAE3_FEC_AUTO) || 2881 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2882 return; 2883 2884 hclge_update_fec_stats(hdev); 2885 2886 hclge_comm_get_fec_stats(hdev, fec_stats); 2887} 2888 2889static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2890{ 2891 struct hclge_config_fec_cmd *req; 2892 struct hclge_desc desc; 2893 int ret; 2894 2895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2896 2897 req = (struct hclge_config_fec_cmd *)desc.data; 2898 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2899 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2900 if (fec_mode & BIT(HNAE3_FEC_RS)) 2901 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2902 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2903 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2904 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2905 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2906 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2907 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2908 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2909 2910 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2911 if (ret) 2912 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2913 2914 return ret; 2915} 2916 2917static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2918{ 2919 struct hclge_vport *vport = hclge_get_vport(handle); 2920 struct hclge_dev *hdev = vport->back; 2921 struct hclge_mac *mac = &hdev->hw.mac; 2922 int ret; 2923 2924 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2925 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2926 return -EINVAL; 2927 } 2928 2929 ret = hclge_set_fec_hw(hdev, fec_mode); 2930 if (ret) 2931 return ret; 2932 2933 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2934 return 0; 2935} 2936 2937static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2938 u8 *fec_mode) 2939{ 2940 struct hclge_vport *vport = hclge_get_vport(handle); 2941 struct hclge_dev *hdev = vport->back; 2942 struct hclge_mac *mac = &hdev->hw.mac; 2943 2944 if (fec_ability) 2945 *fec_ability = mac->fec_ability; 2946 if (fec_mode) 2947 *fec_mode = mac->fec_mode; 2948} 2949 2950static int hclge_mac_init(struct hclge_dev *hdev) 2951{ 2952 struct hclge_mac *mac = &hdev->hw.mac; 2953 int ret; 2954 2955 hdev->support_sfp_query = true; 2956 2957 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2958 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2959 2960 if (hdev->hw.mac.support_autoneg) { 2961 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2962 if (ret) 2963 return ret; 2964 } 2965 2966 if (!hdev->hw.mac.autoneg) { 2967 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed, 2968 hdev->hw.mac.req_duplex, 2969 hdev->hw.mac.lane_num); 2970 if (ret) 2971 return ret; 2972 } 2973 2974 mac->link = 0; 2975 2976 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2977 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2978 if (ret) 2979 return ret; 2980 } 2981 2982 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2983 if (ret) { 2984 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2985 return ret; 2986 } 2987 2988 ret = hclge_set_default_loopback(hdev); 2989 if (ret) 2990 return ret; 2991 2992 ret = hclge_buffer_alloc(hdev); 2993 if (ret) 2994 dev_err(&hdev->pdev->dev, 2995 "allocate buffer fail, ret=%d\n", ret); 2996 2997 return ret; 2998} 2999 3000static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 3001{ 3002 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3003 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 3004 hdev->last_mbx_scheduled = jiffies; 3005 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3006 } 3007} 3008 3009static void hclge_reset_task_schedule(struct hclge_dev *hdev) 3010{ 3011 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3012 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 3013 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 3014 hdev->last_rst_scheduled = jiffies; 3015 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3016 } 3017} 3018 3019static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 3020{ 3021 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3022 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 3023 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3024} 3025 3026void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 3027{ 3028 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3029 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 3030 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 3031} 3032 3033static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 3034{ 3035 struct hclge_link_status_cmd *req; 3036 struct hclge_desc desc; 3037 int ret; 3038 3039 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 3040 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3041 if (ret) { 3042 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 3043 ret); 3044 return ret; 3045 } 3046 3047 req = (struct hclge_link_status_cmd *)desc.data; 3048 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3049 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3050 3051 return 0; 3052} 3053 3054static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3055{ 3056 struct phy_device *phydev = hdev->hw.mac.phydev; 3057 3058 *link_status = HCLGE_LINK_STATUS_DOWN; 3059 3060 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3061 return 0; 3062 3063 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3064 return 0; 3065 3066 return hclge_get_mac_link_status(hdev, link_status); 3067} 3068 3069static void hclge_push_link_status(struct hclge_dev *hdev) 3070{ 3071 struct hclge_vport *vport; 3072 int ret; 3073 u16 i; 3074 3075 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3076 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3077 3078 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3079 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3080 continue; 3081 3082 ret = hclge_push_vf_link_status(vport); 3083 if (ret) { 3084 dev_err(&hdev->pdev->dev, 3085 "failed to push link status to vf%u, ret = %d\n", 3086 i, ret); 3087 } 3088 } 3089} 3090 3091static void hclge_update_link_status(struct hclge_dev *hdev) 3092{ 3093 struct hnae3_handle *handle = &hdev->vport[0].nic; 3094 struct hnae3_client *client = hdev->nic_client; 3095 int state; 3096 int ret; 3097 3098 if (!client) 3099 return; 3100 3101 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3102 return; 3103 3104 ret = hclge_get_mac_phy_link(hdev, &state); 3105 if (ret) { 3106 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3107 return; 3108 } 3109 3110 if (state != hdev->hw.mac.link) { 3111 hdev->hw.mac.link = state; 3112 if (state == HCLGE_LINK_STATUS_UP) 3113 hclge_update_port_info(hdev); 3114 3115 client->ops->link_status_change(handle, state); 3116 hclge_config_mac_tnl_int(hdev, state); 3117 3118 if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) { 3119 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3120 struct hnae3_client *rclient = hdev->roce_client; 3121 3122 if (rclient && rclient->ops->link_status_change) 3123 rclient->ops->link_status_change(rhandle, 3124 state); 3125 } 3126 3127 hclge_push_link_status(hdev); 3128 } 3129 3130 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3131} 3132 3133static void hclge_update_speed_advertising(struct hclge_mac *mac) 3134{ 3135 u32 speed_ability; 3136 3137 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3138 return; 3139 3140 switch (mac->module_type) { 3141 case HNAE3_MODULE_TYPE_FIBRE_LR: 3142 hclge_convert_setting_lr(speed_ability, mac->advertising); 3143 break; 3144 case HNAE3_MODULE_TYPE_FIBRE_SR: 3145 case HNAE3_MODULE_TYPE_AOC: 3146 hclge_convert_setting_sr(speed_ability, mac->advertising); 3147 break; 3148 case HNAE3_MODULE_TYPE_CR: 3149 hclge_convert_setting_cr(speed_ability, mac->advertising); 3150 break; 3151 case HNAE3_MODULE_TYPE_KR: 3152 hclge_convert_setting_kr(speed_ability, mac->advertising); 3153 break; 3154 default: 3155 break; 3156 } 3157} 3158 3159static void hclge_update_fec_advertising(struct hclge_mac *mac) 3160{ 3161 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3162 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3163 mac->advertising); 3164 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3165 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3166 mac->advertising); 3167 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3168 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3169 mac->advertising); 3170 else 3171 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3172 mac->advertising); 3173} 3174 3175static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3176{ 3177 struct hclge_mac *mac = &hdev->hw.mac; 3178 bool rx_en, tx_en; 3179 3180 switch (hdev->fc_mode_last_time) { 3181 case HCLGE_FC_RX_PAUSE: 3182 rx_en = true; 3183 tx_en = false; 3184 break; 3185 case HCLGE_FC_TX_PAUSE: 3186 rx_en = false; 3187 tx_en = true; 3188 break; 3189 case HCLGE_FC_FULL: 3190 rx_en = true; 3191 tx_en = true; 3192 break; 3193 default: 3194 rx_en = false; 3195 tx_en = false; 3196 break; 3197 } 3198 3199 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3200} 3201 3202static void hclge_update_advertising(struct hclge_dev *hdev) 3203{ 3204 struct hclge_mac *mac = &hdev->hw.mac; 3205 3206 linkmode_zero(mac->advertising); 3207 hclge_update_speed_advertising(mac); 3208 hclge_update_fec_advertising(mac); 3209 hclge_update_pause_advertising(hdev); 3210} 3211 3212static void hclge_update_port_capability(struct hclge_dev *hdev, 3213 struct hclge_mac *mac) 3214{ 3215 if (hnae3_dev_fec_supported(hdev)) 3216 hclge_convert_setting_fec(mac); 3217 3218 /* firmware can not identify back plane type, the media type 3219 * read from configuration can help deal it 3220 */ 3221 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3222 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3223 mac->module_type = HNAE3_MODULE_TYPE_KR; 3224 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3225 mac->module_type = HNAE3_MODULE_TYPE_TP; 3226 3227 if (mac->support_autoneg) { 3228 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3229 linkmode_copy(mac->advertising, mac->supported); 3230 } else { 3231 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3232 mac->supported); 3233 hclge_update_advertising(hdev); 3234 } 3235} 3236 3237static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3238{ 3239 struct hclge_sfp_info_cmd *resp; 3240 struct hclge_desc desc; 3241 int ret; 3242 3243 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3244 resp = (struct hclge_sfp_info_cmd *)desc.data; 3245 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3246 if (ret == -EOPNOTSUPP) { 3247 dev_warn(&hdev->pdev->dev, 3248 "IMP do not support get SFP speed %d\n", ret); 3249 return ret; 3250 } else if (ret) { 3251 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3252 return ret; 3253 } 3254 3255 *speed = le32_to_cpu(resp->speed); 3256 3257 return 0; 3258} 3259 3260static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3261{ 3262 struct hclge_sfp_info_cmd *resp; 3263 struct hclge_desc desc; 3264 int ret; 3265 3266 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3267 resp = (struct hclge_sfp_info_cmd *)desc.data; 3268 3269 resp->query_type = QUERY_ACTIVE_SPEED; 3270 3271 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3272 if (ret == -EOPNOTSUPP) { 3273 dev_warn(&hdev->pdev->dev, 3274 "IMP does not support get SFP info %d\n", ret); 3275 return ret; 3276 } else if (ret) { 3277 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3278 return ret; 3279 } 3280 3281 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3282 * set to mac->speed. 3283 */ 3284 if (!le32_to_cpu(resp->speed)) 3285 return 0; 3286 3287 mac->speed = le32_to_cpu(resp->speed); 3288 /* if resp->speed_ability is 0, it means it's an old version 3289 * firmware, do not update these params 3290 */ 3291 if (resp->speed_ability) { 3292 mac->module_type = le32_to_cpu(resp->module_type); 3293 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3294 mac->autoneg = resp->autoneg; 3295 mac->support_autoneg = resp->autoneg_ability; 3296 mac->speed_type = QUERY_ACTIVE_SPEED; 3297 mac->lane_num = resp->lane_num; 3298 if (!resp->active_fec) 3299 mac->fec_mode = 0; 3300 else 3301 mac->fec_mode = BIT(resp->active_fec); 3302 mac->fec_ability = resp->fec_ability; 3303 } else { 3304 mac->speed_type = QUERY_SFP_SPEED; 3305 } 3306 3307 return 0; 3308} 3309 3310static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3311 struct ethtool_link_ksettings *cmd) 3312{ 3313 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3314 struct hclge_vport *vport = hclge_get_vport(handle); 3315 struct hclge_phy_link_ksetting_0_cmd *req0; 3316 struct hclge_phy_link_ksetting_1_cmd *req1; 3317 u32 supported, advertising, lp_advertising; 3318 struct hclge_dev *hdev = vport->back; 3319 int ret; 3320 3321 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3322 true); 3323 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3324 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3325 true); 3326 3327 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3328 if (ret) { 3329 dev_err(&hdev->pdev->dev, 3330 "failed to get phy link ksetting, ret = %d.\n", ret); 3331 return ret; 3332 } 3333 3334 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3335 cmd->base.autoneg = req0->autoneg; 3336 cmd->base.speed = le32_to_cpu(req0->speed); 3337 cmd->base.duplex = req0->duplex; 3338 cmd->base.port = req0->port; 3339 cmd->base.transceiver = req0->transceiver; 3340 cmd->base.phy_address = req0->phy_address; 3341 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3342 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3343 supported = le32_to_cpu(req0->supported); 3344 advertising = le32_to_cpu(req0->advertising); 3345 lp_advertising = le32_to_cpu(req0->lp_advertising); 3346 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3347 supported); 3348 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3349 advertising); 3350 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3351 lp_advertising); 3352 3353 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3354 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3355 cmd->base.master_slave_state = req1->master_slave_state; 3356 3357 return 0; 3358} 3359 3360static int 3361hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3362 const struct ethtool_link_ksettings *cmd) 3363{ 3364 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3365 struct hclge_vport *vport = hclge_get_vport(handle); 3366 struct hclge_phy_link_ksetting_0_cmd *req0; 3367 struct hclge_phy_link_ksetting_1_cmd *req1; 3368 struct hclge_dev *hdev = vport->back; 3369 u32 advertising; 3370 int ret; 3371 3372 if (cmd->base.autoneg == AUTONEG_DISABLE && 3373 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3374 (cmd->base.duplex != DUPLEX_HALF && 3375 cmd->base.duplex != DUPLEX_FULL))) 3376 return -EINVAL; 3377 3378 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3379 false); 3380 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3381 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3382 false); 3383 3384 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3385 req0->autoneg = cmd->base.autoneg; 3386 req0->speed = cpu_to_le32(cmd->base.speed); 3387 req0->duplex = cmd->base.duplex; 3388 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3389 cmd->link_modes.advertising); 3390 req0->advertising = cpu_to_le32(advertising); 3391 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3392 3393 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3394 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3395 3396 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3397 if (ret) { 3398 dev_err(&hdev->pdev->dev, 3399 "failed to set phy link ksettings, ret = %d.\n", ret); 3400 return ret; 3401 } 3402 3403 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3404 hdev->hw.mac.req_speed = cmd->base.speed; 3405 hdev->hw.mac.req_duplex = cmd->base.duplex; 3406 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3407 3408 return 0; 3409} 3410 3411static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3412{ 3413 struct ethtool_link_ksettings cmd; 3414 int ret; 3415 3416 if (!hnae3_dev_phy_imp_supported(hdev)) 3417 return 0; 3418 3419 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3420 if (ret) 3421 return ret; 3422 3423 hdev->hw.mac.autoneg = cmd.base.autoneg; 3424 hdev->hw.mac.speed = cmd.base.speed; 3425 hdev->hw.mac.duplex = cmd.base.duplex; 3426 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3427 3428 return 0; 3429} 3430 3431static int hclge_tp_port_init(struct hclge_dev *hdev) 3432{ 3433 struct ethtool_link_ksettings cmd; 3434 3435 if (!hnae3_dev_phy_imp_supported(hdev)) 3436 return 0; 3437 3438 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3439 cmd.base.speed = hdev->hw.mac.req_speed; 3440 cmd.base.duplex = hdev->hw.mac.req_duplex; 3441 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3442 3443 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3444} 3445 3446static int hclge_update_port_info(struct hclge_dev *hdev) 3447{ 3448 struct hclge_mac *mac = &hdev->hw.mac; 3449 u32 speed; 3450 int ret; 3451 3452 /* get the port info from SFP cmd if not copper port */ 3453 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3454 return hclge_update_tp_port_info(hdev); 3455 3456 /* if IMP does not support get SFP/qSFP info, return directly */ 3457 if (!hdev->support_sfp_query) 3458 return 0; 3459 3460 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3461 speed = mac->speed; 3462 ret = hclge_get_sfp_info(hdev, mac); 3463 } else { 3464 speed = HCLGE_MAC_SPEED_UNKNOWN; 3465 ret = hclge_get_sfp_speed(hdev, &speed); 3466 } 3467 3468 if (ret == -EOPNOTSUPP) { 3469 hdev->support_sfp_query = false; 3470 return ret; 3471 } else if (ret) { 3472 return ret; 3473 } 3474 3475 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3476 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3477 hclge_update_port_capability(hdev, mac); 3478 if (mac->speed != speed) 3479 (void)hclge_tm_port_shaper_cfg(hdev); 3480 return 0; 3481 } 3482 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3483 HCLGE_MAC_FULL, mac->lane_num); 3484 } else { 3485 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3486 return 0; /* do nothing if no SFP */ 3487 3488 /* must config full duplex for SFP */ 3489 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3490 } 3491} 3492 3493static int hclge_get_status(struct hnae3_handle *handle) 3494{ 3495 struct hclge_vport *vport = hclge_get_vport(handle); 3496 struct hclge_dev *hdev = vport->back; 3497 3498 hclge_update_link_status(hdev); 3499 3500 return hdev->hw.mac.link; 3501} 3502 3503struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3504{ 3505 if (!pci_num_vf(hdev->pdev)) { 3506 dev_err(&hdev->pdev->dev, 3507 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3508 return NULL; 3509 } 3510 3511 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3512 dev_err(&hdev->pdev->dev, 3513 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3514 vf, pci_num_vf(hdev->pdev)); 3515 return NULL; 3516 } 3517 3518 /* VF start from 1 in vport */ 3519 vf += HCLGE_VF_VPORT_START_NUM; 3520 return &hdev->vport[vf]; 3521} 3522 3523static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3524 struct ifla_vf_info *ivf) 3525{ 3526 struct hclge_vport *vport = hclge_get_vport(handle); 3527 struct hclge_dev *hdev = vport->back; 3528 3529 vport = hclge_get_vf_vport(hdev, vf); 3530 if (!vport) 3531 return -EINVAL; 3532 3533 ivf->vf = vf; 3534 ivf->linkstate = vport->vf_info.link_state; 3535 ivf->spoofchk = vport->vf_info.spoofchk; 3536 ivf->trusted = vport->vf_info.trusted; 3537 ivf->min_tx_rate = 0; 3538 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3539 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3540 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3541 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3542 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3543 3544 return 0; 3545} 3546 3547static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3548 int link_state) 3549{ 3550 struct hclge_vport *vport = hclge_get_vport(handle); 3551 struct hclge_dev *hdev = vport->back; 3552 int link_state_old; 3553 int ret; 3554 3555 vport = hclge_get_vf_vport(hdev, vf); 3556 if (!vport) 3557 return -EINVAL; 3558 3559 link_state_old = vport->vf_info.link_state; 3560 vport->vf_info.link_state = link_state; 3561 3562 /* return success directly if the VF is unalive, VF will 3563 * query link state itself when it starts work. 3564 */ 3565 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3566 return 0; 3567 3568 ret = hclge_push_vf_link_status(vport); 3569 if (ret) { 3570 vport->vf_info.link_state = link_state_old; 3571 dev_err(&hdev->pdev->dev, 3572 "failed to push vf%d link status, ret = %d\n", vf, ret); 3573 } 3574 3575 return ret; 3576} 3577 3578static void hclge_set_reset_pending(struct hclge_dev *hdev, 3579 enum hnae3_reset_type reset_type) 3580{ 3581 /* When an incorrect reset type is executed, the get_reset_level 3582 * function generates the HNAE3_NONE_RESET flag. As a result, this 3583 * type do not need to pending. 3584 */ 3585 if (reset_type != HNAE3_NONE_RESET) 3586 set_bit(reset_type, &hdev->reset_pending); 3587} 3588 3589static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3590{ 3591 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3592 3593 /* fetch the events from their corresponding regs */ 3594 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3595 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3596 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3597 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3598 3599 /* Assumption: If by any chance reset and mailbox events are reported 3600 * together then we will only process reset event in this go and will 3601 * defer the processing of the mailbox events. Since, we would have not 3602 * cleared RX CMDQ event this time we would receive again another 3603 * interrupt from H/W just for the mailbox. 3604 * 3605 * check for vector0 reset event sources 3606 */ 3607 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3608 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3609 hclge_set_reset_pending(hdev, HNAE3_IMP_RESET); 3610 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3611 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3612 hdev->rst_stats.imp_rst_cnt++; 3613 return HCLGE_VECTOR0_EVENT_RST; 3614 } 3615 3616 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3617 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3618 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3619 hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET); 3620 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3621 hdev->rst_stats.global_rst_cnt++; 3622 return HCLGE_VECTOR0_EVENT_RST; 3623 } 3624 3625 /* check for vector0 msix event and hardware error event source */ 3626 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3627 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3628 return HCLGE_VECTOR0_EVENT_ERR; 3629 3630 /* check for vector0 ptp event source */ 3631 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3632 *clearval = msix_src_reg; 3633 return HCLGE_VECTOR0_EVENT_PTP; 3634 } 3635 3636 /* check for vector0 mailbox(=CMDQ RX) event source */ 3637 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3638 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3639 *clearval = cmdq_src_reg; 3640 return HCLGE_VECTOR0_EVENT_MBX; 3641 } 3642 3643 /* print other vector0 event source */ 3644 dev_info(&hdev->pdev->dev, 3645 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3646 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3647 3648 return HCLGE_VECTOR0_EVENT_OTHER; 3649} 3650 3651static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3652 u32 regclr) 3653{ 3654#define HCLGE_IMP_RESET_DELAY 5 3655 3656 switch (event_type) { 3657 case HCLGE_VECTOR0_EVENT_PTP: 3658 case HCLGE_VECTOR0_EVENT_RST: 3659 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3660 mdelay(HCLGE_IMP_RESET_DELAY); 3661 3662 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3663 break; 3664 case HCLGE_VECTOR0_EVENT_MBX: 3665 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3666 break; 3667 default: 3668 break; 3669 } 3670} 3671 3672static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3673{ 3674 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3675 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3676 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3677 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3678 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3679} 3680 3681static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3682{ 3683 writel(enable ? 1 : 0, vector->addr); 3684} 3685 3686static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3687{ 3688 struct hclge_dev *hdev = data; 3689 unsigned long flags; 3690 u32 clearval = 0; 3691 u32 event_cause; 3692 3693 hclge_enable_vector(&hdev->misc_vector, false); 3694 event_cause = hclge_check_event_cause(hdev, &clearval); 3695 3696 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3697 switch (event_cause) { 3698 case HCLGE_VECTOR0_EVENT_ERR: 3699 hclge_errhand_task_schedule(hdev); 3700 break; 3701 case HCLGE_VECTOR0_EVENT_RST: 3702 hclge_reset_task_schedule(hdev); 3703 break; 3704 case HCLGE_VECTOR0_EVENT_PTP: 3705 spin_lock_irqsave(&hdev->ptp->lock, flags); 3706 hclge_ptp_clean_tx_hwts(hdev); 3707 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3708 break; 3709 case HCLGE_VECTOR0_EVENT_MBX: 3710 /* If we are here then, 3711 * 1. Either we are not handling any mbx task and we are not 3712 * scheduled as well 3713 * OR 3714 * 2. We could be handling a mbx task but nothing more is 3715 * scheduled. 3716 * In both cases, we should schedule mbx task as there are more 3717 * mbx messages reported by this interrupt. 3718 */ 3719 hclge_mbx_task_schedule(hdev); 3720 break; 3721 default: 3722 dev_warn(&hdev->pdev->dev, 3723 "received unknown or unhandled event of vector0\n"); 3724 break; 3725 } 3726 3727 hclge_clear_event_cause(hdev, event_cause, clearval); 3728 3729 /* Enable interrupt if it is not caused by reset event or error event */ 3730 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3731 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3732 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3733 hclge_enable_vector(&hdev->misc_vector, true); 3734 3735 return IRQ_HANDLED; 3736} 3737 3738static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3739{ 3740 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3741 dev_warn(&hdev->pdev->dev, 3742 "vector(vector_id %d) has been freed.\n", vector_id); 3743 return; 3744 } 3745 3746 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3747 hdev->num_msi_left += 1; 3748 hdev->num_msi_used -= 1; 3749} 3750 3751static void hclge_get_misc_vector(struct hclge_dev *hdev) 3752{ 3753 struct hclge_misc_vector *vector = &hdev->misc_vector; 3754 3755 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3756 3757 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3758 hdev->vector_status[0] = 0; 3759 3760 hdev->num_msi_left -= 1; 3761 hdev->num_msi_used += 1; 3762} 3763 3764static int hclge_misc_irq_init(struct hclge_dev *hdev) 3765{ 3766 int ret; 3767 3768 hclge_get_misc_vector(hdev); 3769 3770 /* this would be explicitly freed in the end */ 3771 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3772 HCLGE_NAME, pci_name(hdev->pdev)); 3773 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3774 IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev); 3775 if (ret) { 3776 hclge_free_vector(hdev, 0); 3777 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3778 hdev->misc_vector.vector_irq); 3779 } 3780 3781 return ret; 3782} 3783 3784static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3785{ 3786 free_irq(hdev->misc_vector.vector_irq, hdev); 3787 hclge_free_vector(hdev, 0); 3788} 3789 3790int hclge_notify_client(struct hclge_dev *hdev, 3791 enum hnae3_reset_notify_type type) 3792{ 3793 struct hnae3_handle *handle = &hdev->vport[0].nic; 3794 struct hnae3_client *client = hdev->nic_client; 3795 int ret; 3796 3797 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3798 return 0; 3799 3800 if (!client->ops->reset_notify) 3801 return -EOPNOTSUPP; 3802 3803 ret = client->ops->reset_notify(handle, type); 3804 if (ret) 3805 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3806 type, ret); 3807 3808 return ret; 3809} 3810 3811static int hclge_notify_roce_client(struct hclge_dev *hdev, 3812 enum hnae3_reset_notify_type type) 3813{ 3814 struct hnae3_handle *handle = &hdev->vport[0].roce; 3815 struct hnae3_client *client = hdev->roce_client; 3816 int ret; 3817 3818 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3819 return 0; 3820 3821 if (!client->ops->reset_notify) 3822 return -EOPNOTSUPP; 3823 3824 ret = client->ops->reset_notify(handle, type); 3825 if (ret) 3826 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3827 type, ret); 3828 3829 return ret; 3830} 3831 3832static int hclge_reset_wait(struct hclge_dev *hdev) 3833{ 3834#define HCLGE_RESET_WATI_MS 100 3835#define HCLGE_RESET_WAIT_CNT 350 3836 3837 u32 val, reg, reg_bit; 3838 u32 cnt = 0; 3839 3840 switch (hdev->reset_type) { 3841 case HNAE3_IMP_RESET: 3842 reg = HCLGE_GLOBAL_RESET_REG; 3843 reg_bit = HCLGE_IMP_RESET_BIT; 3844 break; 3845 case HNAE3_GLOBAL_RESET: 3846 reg = HCLGE_GLOBAL_RESET_REG; 3847 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3848 break; 3849 case HNAE3_FUNC_RESET: 3850 reg = HCLGE_FUN_RST_ING; 3851 reg_bit = HCLGE_FUN_RST_ING_B; 3852 break; 3853 default: 3854 dev_err(&hdev->pdev->dev, 3855 "Wait for unsupported reset type: %d\n", 3856 hdev->reset_type); 3857 return -EINVAL; 3858 } 3859 3860 val = hclge_read_dev(&hdev->hw, reg); 3861 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3862 msleep(HCLGE_RESET_WATI_MS); 3863 val = hclge_read_dev(&hdev->hw, reg); 3864 cnt++; 3865 } 3866 3867 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3868 dev_warn(&hdev->pdev->dev, 3869 "Wait for reset timeout: %d\n", hdev->reset_type); 3870 return -EBUSY; 3871 } 3872 3873 return 0; 3874} 3875 3876static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3877{ 3878 struct hclge_vf_rst_cmd *req; 3879 struct hclge_desc desc; 3880 3881 req = (struct hclge_vf_rst_cmd *)desc.data; 3882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3883 req->dest_vfid = func_id; 3884 3885 if (reset) 3886 req->vf_rst = 0x1; 3887 3888 return hclge_cmd_send(&hdev->hw, &desc, 1); 3889} 3890 3891static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3892{ 3893 int i; 3894 3895 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3896 struct hclge_vport *vport = &hdev->vport[i]; 3897 int ret; 3898 3899 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3900 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3901 if (ret) { 3902 dev_err(&hdev->pdev->dev, 3903 "set vf(%u) rst failed %d!\n", 3904 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3905 ret); 3906 return ret; 3907 } 3908 3909 if (!reset || 3910 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3911 continue; 3912 3913 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3914 hdev->reset_type == HNAE3_FUNC_RESET) { 3915 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3916 &vport->need_notify); 3917 continue; 3918 } 3919 3920 /* Inform VF to process the reset. 3921 * hclge_inform_reset_assert_to_vf may fail if VF 3922 * driver is not loaded. 3923 */ 3924 ret = hclge_inform_reset_assert_to_vf(vport); 3925 if (ret) 3926 dev_warn(&hdev->pdev->dev, 3927 "inform reset to vf(%u) failed %d!\n", 3928 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3929 ret); 3930 } 3931 3932 return 0; 3933} 3934 3935static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3936{ 3937 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3938 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3939 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3940 return; 3941 3942 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3943 HCLGE_MBX_SCHED_TIMEOUT)) 3944 dev_warn(&hdev->pdev->dev, 3945 "mbx service task is scheduled after %ums on cpu%u!\n", 3946 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3947 smp_processor_id()); 3948 3949 hclge_mbx_handler(hdev); 3950 3951 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3952} 3953 3954static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3955{ 3956 struct hclge_pf_rst_sync_cmd *req; 3957 struct hclge_desc desc; 3958 int cnt = 0; 3959 int ret; 3960 3961 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3962 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3963 3964 do { 3965 /* vf need to down netdev by mbx during PF or FLR reset */ 3966 hclge_mailbox_service_task(hdev); 3967 3968 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3969 /* for compatible with old firmware, wait 3970 * 100 ms for VF to stop IO 3971 */ 3972 if (ret == -EOPNOTSUPP) { 3973 msleep(HCLGE_RESET_SYNC_TIME); 3974 return; 3975 } else if (ret) { 3976 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3977 ret); 3978 return; 3979 } else if (req->all_vf_ready) { 3980 return; 3981 } 3982 msleep(HCLGE_PF_RESET_SYNC_TIME); 3983 hclge_comm_cmd_reuse_desc(&desc, true); 3984 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3985 3986 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3987} 3988 3989void hclge_report_hw_error(struct hclge_dev *hdev, 3990 enum hnae3_hw_error_type type) 3991{ 3992 struct hnae3_client *client = hdev->nic_client; 3993 3994 if (!client || !client->ops->process_hw_error || 3995 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3996 return; 3997 3998 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3999} 4000 4001static void hclge_handle_imp_error(struct hclge_dev *hdev) 4002{ 4003 u32 reg_val; 4004 4005 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4006 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 4007 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 4008 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 4009 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4010 } 4011 4012 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 4013 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 4014 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4015 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4016 } 4017} 4018 4019int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4020{ 4021 struct hclge_desc desc; 4022 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4023 int ret; 4024 4025 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4026 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4027 req->fun_reset_vfid = func_id; 4028 4029 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4030 if (ret) 4031 dev_err(&hdev->pdev->dev, 4032 "send function reset cmd fail, status =%d\n", ret); 4033 4034 return ret; 4035} 4036 4037static void hclge_do_reset(struct hclge_dev *hdev) 4038{ 4039 struct hnae3_handle *handle = &hdev->vport[0].nic; 4040 struct pci_dev *pdev = hdev->pdev; 4041 u32 val; 4042 4043 if (hclge_get_hw_reset_stat(handle)) { 4044 dev_info(&pdev->dev, "hardware reset not finish\n"); 4045 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4046 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4047 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4048 return; 4049 } 4050 4051 switch (hdev->reset_type) { 4052 case HNAE3_IMP_RESET: 4053 dev_info(&pdev->dev, "IMP reset requested\n"); 4054 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4055 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4056 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4057 break; 4058 case HNAE3_GLOBAL_RESET: 4059 dev_info(&pdev->dev, "global reset requested\n"); 4060 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4061 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4062 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4063 break; 4064 case HNAE3_FUNC_RESET: 4065 dev_info(&pdev->dev, "PF reset requested\n"); 4066 /* schedule again to check later */ 4067 hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET); 4068 hclge_reset_task_schedule(hdev); 4069 break; 4070 default: 4071 dev_warn(&pdev->dev, 4072 "unsupported reset type: %d\n", hdev->reset_type); 4073 break; 4074 } 4075} 4076 4077static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4078 unsigned long *addr) 4079{ 4080 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4081 struct hclge_dev *hdev = ae_dev->priv; 4082 4083 /* return the highest priority reset level amongst all */ 4084 if (test_bit(HNAE3_IMP_RESET, addr)) { 4085 rst_level = HNAE3_IMP_RESET; 4086 clear_bit(HNAE3_IMP_RESET, addr); 4087 clear_bit(HNAE3_GLOBAL_RESET, addr); 4088 clear_bit(HNAE3_FUNC_RESET, addr); 4089 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4090 rst_level = HNAE3_GLOBAL_RESET; 4091 clear_bit(HNAE3_GLOBAL_RESET, addr); 4092 clear_bit(HNAE3_FUNC_RESET, addr); 4093 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4094 rst_level = HNAE3_FUNC_RESET; 4095 clear_bit(HNAE3_FUNC_RESET, addr); 4096 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4097 rst_level = HNAE3_FLR_RESET; 4098 clear_bit(HNAE3_FLR_RESET, addr); 4099 } 4100 4101 clear_bit(HNAE3_NONE_RESET, addr); 4102 4103 if (hdev->reset_type != HNAE3_NONE_RESET && 4104 rst_level < hdev->reset_type) 4105 return HNAE3_NONE_RESET; 4106 4107 return rst_level; 4108} 4109 4110static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4111{ 4112 u32 clearval = 0; 4113 4114 switch (hdev->reset_type) { 4115 case HNAE3_IMP_RESET: 4116 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4117 break; 4118 case HNAE3_GLOBAL_RESET: 4119 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4120 break; 4121 default: 4122 break; 4123 } 4124 4125 if (!clearval) 4126 return; 4127 4128 /* For revision 0x20, the reset interrupt source 4129 * can only be cleared after hardware reset done 4130 */ 4131 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4132 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4133 clearval); 4134 4135 hclge_enable_vector(&hdev->misc_vector, true); 4136} 4137 4138static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4139{ 4140 u32 reg_val; 4141 4142 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4143 if (enable) 4144 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4145 else 4146 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4147 4148 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4149} 4150 4151static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4152{ 4153 int ret; 4154 4155 ret = hclge_set_all_vf_rst(hdev, true); 4156 if (ret) 4157 return ret; 4158 4159 hclge_func_reset_sync_vf(hdev); 4160 4161 return 0; 4162} 4163 4164static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4165{ 4166 u32 reg_val; 4167 int ret = 0; 4168 4169 switch (hdev->reset_type) { 4170 case HNAE3_FUNC_RESET: 4171 ret = hclge_func_reset_notify_vf(hdev); 4172 if (ret) 4173 return ret; 4174 4175 ret = hclge_func_reset_cmd(hdev, 0); 4176 if (ret) { 4177 dev_err(&hdev->pdev->dev, 4178 "asserting function reset fail %d!\n", ret); 4179 return ret; 4180 } 4181 4182 /* After performaning pf reset, it is not necessary to do the 4183 * mailbox handling or send any command to firmware, because 4184 * any mailbox handling or command to firmware is only valid 4185 * after hclge_comm_cmd_init is called. 4186 */ 4187 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4188 hdev->rst_stats.pf_rst_cnt++; 4189 break; 4190 case HNAE3_FLR_RESET: 4191 ret = hclge_func_reset_notify_vf(hdev); 4192 if (ret) 4193 return ret; 4194 break; 4195 case HNAE3_IMP_RESET: 4196 hclge_handle_imp_error(hdev); 4197 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4198 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4199 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4200 break; 4201 default: 4202 break; 4203 } 4204 4205 /* inform hardware that preparatory work is done */ 4206 msleep(HCLGE_RESET_SYNC_TIME); 4207 hclge_reset_handshake(hdev, true); 4208 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4209 4210 return ret; 4211} 4212 4213static void hclge_show_rst_info(struct hclge_dev *hdev) 4214{ 4215 char *buf; 4216 4217 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4218 if (!buf) 4219 return; 4220 4221 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4222 4223 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4224 4225 kfree(buf); 4226} 4227 4228static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4229{ 4230#define MAX_RESET_FAIL_CNT 5 4231 4232 if (hdev->reset_pending) { 4233 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4234 hdev->reset_pending); 4235 return true; 4236 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4237 HCLGE_RESET_INT_M) { 4238 dev_info(&hdev->pdev->dev, 4239 "reset failed because new reset interrupt\n"); 4240 hclge_clear_reset_cause(hdev); 4241 return false; 4242 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4243 hdev->rst_stats.reset_fail_cnt++; 4244 hclge_set_reset_pending(hdev, hdev->reset_type); 4245 dev_info(&hdev->pdev->dev, 4246 "re-schedule reset task(%u)\n", 4247 hdev->rst_stats.reset_fail_cnt); 4248 return true; 4249 } 4250 4251 hclge_clear_reset_cause(hdev); 4252 4253 /* recover the handshake status when reset fail */ 4254 hclge_reset_handshake(hdev, true); 4255 4256 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4257 4258 hclge_show_rst_info(hdev); 4259 4260 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4261 4262 return false; 4263} 4264 4265static void hclge_update_reset_level(struct hclge_dev *hdev) 4266{ 4267 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4268 enum hnae3_reset_type reset_level; 4269 4270 /* reset request will not be set during reset, so clear 4271 * pending reset request to avoid unnecessary reset 4272 * caused by the same reason. 4273 */ 4274 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4275 4276 /* if default_reset_request has a higher level reset request, 4277 * it should be handled as soon as possible. since some errors 4278 * need this kind of reset to fix. 4279 */ 4280 reset_level = hclge_get_reset_level(ae_dev, 4281 &hdev->default_reset_request); 4282 if (reset_level != HNAE3_NONE_RESET) 4283 set_bit(reset_level, &hdev->reset_request); 4284} 4285 4286static int hclge_set_rst_done(struct hclge_dev *hdev) 4287{ 4288 struct hclge_pf_rst_done_cmd *req; 4289 struct hclge_desc desc; 4290 int ret; 4291 4292 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4293 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4294 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4295 4296 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4297 /* To be compatible with the old firmware, which does not support 4298 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4299 * return success 4300 */ 4301 if (ret == -EOPNOTSUPP) { 4302 dev_warn(&hdev->pdev->dev, 4303 "current firmware does not support command(0x%x)!\n", 4304 HCLGE_OPC_PF_RST_DONE); 4305 return 0; 4306 } else if (ret) { 4307 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4308 ret); 4309 } 4310 4311 return ret; 4312} 4313 4314static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4315{ 4316 int ret = 0; 4317 4318 switch (hdev->reset_type) { 4319 case HNAE3_FUNC_RESET: 4320 case HNAE3_FLR_RESET: 4321 ret = hclge_set_all_vf_rst(hdev, false); 4322 break; 4323 case HNAE3_GLOBAL_RESET: 4324 case HNAE3_IMP_RESET: 4325 ret = hclge_set_rst_done(hdev); 4326 break; 4327 default: 4328 break; 4329 } 4330 4331 /* clear up the handshake status after re-initialize done */ 4332 hclge_reset_handshake(hdev, false); 4333 4334 return ret; 4335} 4336 4337static int hclge_reset_stack(struct hclge_dev *hdev) 4338{ 4339 int ret; 4340 4341 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4342 if (ret) 4343 return ret; 4344 4345 ret = hclge_reset_ae_dev(hdev->ae_dev); 4346 if (ret) 4347 return ret; 4348 4349 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4350} 4351 4352static int hclge_reset_prepare(struct hclge_dev *hdev) 4353{ 4354 int ret; 4355 4356 hdev->rst_stats.reset_cnt++; 4357 /* perform reset of the stack & ae device for a client */ 4358 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4359 if (ret) 4360 return ret; 4361 4362 rtnl_lock(); 4363 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4364 rtnl_unlock(); 4365 if (ret) 4366 return ret; 4367 4368 return hclge_reset_prepare_wait(hdev); 4369} 4370 4371static int hclge_reset_rebuild(struct hclge_dev *hdev) 4372{ 4373 int ret; 4374 4375 hdev->rst_stats.hw_reset_done_cnt++; 4376 4377 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4378 if (ret) 4379 return ret; 4380 4381 rtnl_lock(); 4382 ret = hclge_reset_stack(hdev); 4383 rtnl_unlock(); 4384 if (ret) 4385 return ret; 4386 4387 hclge_clear_reset_cause(hdev); 4388 4389 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4390 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4391 * times 4392 */ 4393 if (ret && 4394 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4395 return ret; 4396 4397 ret = hclge_reset_prepare_up(hdev); 4398 if (ret) 4399 return ret; 4400 4401 rtnl_lock(); 4402 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4403 rtnl_unlock(); 4404 if (ret) 4405 return ret; 4406 4407 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4408 if (ret) 4409 return ret; 4410 4411 hdev->last_reset_time = jiffies; 4412 hdev->rst_stats.reset_fail_cnt = 0; 4413 hdev->rst_stats.reset_done_cnt++; 4414 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4415 4416 hclge_update_reset_level(hdev); 4417 4418 return 0; 4419} 4420 4421static void hclge_reset(struct hclge_dev *hdev) 4422{ 4423 if (hclge_reset_prepare(hdev)) 4424 goto err_reset; 4425 4426 if (hclge_reset_wait(hdev)) 4427 goto err_reset; 4428 4429 if (hclge_reset_rebuild(hdev)) 4430 goto err_reset; 4431 4432 return; 4433 4434err_reset: 4435 if (hclge_reset_err_handle(hdev)) 4436 hclge_reset_task_schedule(hdev); 4437} 4438 4439static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4440{ 4441 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4442 struct hclge_dev *hdev = ae_dev->priv; 4443 4444 /* We might end up getting called broadly because of 2 below cases: 4445 * 1. Recoverable error was conveyed through APEI and only way to bring 4446 * normalcy is to reset. 4447 * 2. A new reset request from the stack due to timeout 4448 * 4449 * check if this is a new reset request and we are not here just because 4450 * last reset attempt did not succeed and watchdog hit us again. We will 4451 * know this if last reset request did not occur very recently (watchdog 4452 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4453 * In case of new request we reset the "reset level" to PF reset. 4454 * And if it is a repeat reset request of the most recent one then we 4455 * want to make sure we throttle the reset request. Therefore, we will 4456 * not allow it again before 3*HZ times. 4457 */ 4458 4459 if (time_before(jiffies, (hdev->last_reset_time + 4460 HCLGE_RESET_INTERVAL))) { 4461 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4462 return; 4463 } 4464 4465 if (hdev->default_reset_request) { 4466 hdev->reset_level = 4467 hclge_get_reset_level(ae_dev, 4468 &hdev->default_reset_request); 4469 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4470 hdev->reset_level = HNAE3_FUNC_RESET; 4471 } 4472 4473 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4474 hdev->reset_level); 4475 4476 /* request reset & schedule reset task */ 4477 set_bit(hdev->reset_level, &hdev->reset_request); 4478 hclge_reset_task_schedule(hdev); 4479 4480 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4481 hdev->reset_level++; 4482} 4483 4484static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4485 enum hnae3_reset_type rst_type) 4486{ 4487#define HCLGE_SUPPORT_RESET_TYPE \ 4488 (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \ 4489 BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET)) 4490 4491 struct hclge_dev *hdev = ae_dev->priv; 4492 4493 if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) { 4494 /* To prevent reset triggered by hclge_reset_event */ 4495 set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); 4496 dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n", 4497 rst_type); 4498 return; 4499 } 4500 4501 set_bit(rst_type, &hdev->default_reset_request); 4502} 4503 4504static void hclge_reset_timer(struct timer_list *t) 4505{ 4506 struct hclge_dev *hdev = timer_container_of(hdev, t, reset_timer); 4507 4508 /* if default_reset_request has no value, it means that this reset 4509 * request has already be handled, so just return here 4510 */ 4511 if (!hdev->default_reset_request) 4512 return; 4513 4514 dev_info(&hdev->pdev->dev, 4515 "triggering reset in reset timer\n"); 4516 hclge_reset_event(hdev->pdev, NULL); 4517} 4518 4519static void hclge_reset_subtask(struct hclge_dev *hdev) 4520{ 4521 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4522 4523 /* check if there is any ongoing reset in the hardware. This status can 4524 * be checked from reset_pending. If there is then, we need to wait for 4525 * hardware to complete reset. 4526 * a. If we are able to figure out in reasonable time that hardware 4527 * has fully resetted then, we can proceed with driver, client 4528 * reset. 4529 * b. else, we can come back later to check this status so re-sched 4530 * now. 4531 */ 4532 hdev->last_reset_time = jiffies; 4533 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4534 if (hdev->reset_type != HNAE3_NONE_RESET) 4535 hclge_reset(hdev); 4536 4537 /* check if we got any *new* reset requests to be honored */ 4538 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4539 if (hdev->reset_type != HNAE3_NONE_RESET) 4540 hclge_do_reset(hdev); 4541 4542 hdev->reset_type = HNAE3_NONE_RESET; 4543} 4544 4545static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4546{ 4547 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4548 enum hnae3_reset_type reset_type; 4549 4550 if (ae_dev->hw_err_reset_req) { 4551 reset_type = hclge_get_reset_level(ae_dev, 4552 &ae_dev->hw_err_reset_req); 4553 hclge_set_def_reset_request(ae_dev, reset_type); 4554 } 4555 4556 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4557 ae_dev->ops->reset_event(hdev->pdev, NULL); 4558 4559 /* enable interrupt after error handling complete */ 4560 hclge_enable_vector(&hdev->misc_vector, true); 4561} 4562 4563static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4564{ 4565 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4566 4567 ae_dev->hw_err_reset_req = 0; 4568 4569 if (hclge_find_error_source(hdev)) { 4570 hclge_handle_error_info_log(ae_dev); 4571 hclge_handle_mac_tnl(hdev); 4572 hclge_handle_vf_queue_err_ras(hdev); 4573 } 4574 4575 hclge_handle_err_reset_request(hdev); 4576} 4577 4578static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4579{ 4580 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4581 struct device *dev = &hdev->pdev->dev; 4582 u32 msix_sts_reg; 4583 4584 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4585 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4586 if (hclge_handle_hw_msix_error 4587 (hdev, &hdev->default_reset_request)) 4588 dev_info(dev, "received msix interrupt 0x%x\n", 4589 msix_sts_reg); 4590 } 4591 4592 hclge_handle_hw_ras_error(ae_dev); 4593 4594 hclge_handle_err_reset_request(hdev); 4595} 4596 4597static void hclge_errhand_service_task(struct hclge_dev *hdev) 4598{ 4599 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4600 return; 4601 4602 if (hnae3_dev_ras_imp_supported(hdev)) 4603 hclge_handle_err_recovery(hdev); 4604 else 4605 hclge_misc_err_recovery(hdev); 4606} 4607 4608static void hclge_reset_service_task(struct hclge_dev *hdev) 4609{ 4610 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4611 return; 4612 4613 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4614 HCLGE_RESET_SCHED_TIMEOUT)) 4615 dev_warn(&hdev->pdev->dev, 4616 "reset service task is scheduled after %ums on cpu%u!\n", 4617 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4618 smp_processor_id()); 4619 4620 down(&hdev->reset_sem); 4621 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4622 4623 hclge_reset_subtask(hdev); 4624 4625 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4626 up(&hdev->reset_sem); 4627} 4628 4629static void hclge_update_vport_alive(struct hclge_dev *hdev) 4630{ 4631#define HCLGE_ALIVE_SECONDS_NORMAL 8 4632 4633 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4634 int i; 4635 4636 /* start from vport 1 for PF is always alive */ 4637 for (i = 1; i < hdev->num_alloc_vport; i++) { 4638 struct hclge_vport *vport = &hdev->vport[i]; 4639 4640 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4641 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4642 continue; 4643 if (time_after(jiffies, vport->last_active_jiffies + 4644 alive_time)) { 4645 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4646 dev_warn(&hdev->pdev->dev, 4647 "VF %u heartbeat timeout\n", 4648 i - HCLGE_VF_VPORT_START_NUM); 4649 } 4650 } 4651} 4652 4653static void hclge_periodic_service_task(struct hclge_dev *hdev) 4654{ 4655 unsigned long delta = round_jiffies_relative(HZ); 4656 4657 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4658 return; 4659 4660 /* Always handle the link updating to make sure link state is 4661 * updated when it is triggered by mbx. 4662 */ 4663 hclge_update_link_status(hdev); 4664 hclge_sync_mac_table(hdev); 4665 hclge_sync_promisc_mode(hdev); 4666 hclge_sync_fd_table(hdev); 4667 4668 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4669 delta = jiffies - hdev->last_serv_processed; 4670 4671 if (delta < round_jiffies_relative(HZ)) { 4672 delta = round_jiffies_relative(HZ) - delta; 4673 goto out; 4674 } 4675 } 4676 4677 hdev->serv_processed_cnt++; 4678 hclge_update_vport_alive(hdev); 4679 4680 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4681 hdev->last_serv_processed = jiffies; 4682 goto out; 4683 } 4684 4685 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4686 hclge_update_stats_for_all(hdev); 4687 4688 hclge_update_port_info(hdev); 4689 hclge_sync_vlan_filter(hdev); 4690 4691 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4692 hclge_rfs_filter_expire(hdev); 4693 4694 hdev->last_serv_processed = jiffies; 4695 4696out: 4697 hclge_task_schedule(hdev, delta); 4698} 4699 4700static void hclge_ptp_service_task(struct hclge_dev *hdev) 4701{ 4702 unsigned long flags; 4703 4704 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4705 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4706 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4707 return; 4708 4709 /* to prevent concurrence with the irq handler */ 4710 spin_lock_irqsave(&hdev->ptp->lock, flags); 4711 4712 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4713 * handler may handle it just before spin_lock_irqsave(). 4714 */ 4715 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4716 hclge_ptp_clean_tx_hwts(hdev); 4717 4718 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4719} 4720 4721static void hclge_service_task(struct work_struct *work) 4722{ 4723 struct hclge_dev *hdev = 4724 container_of(work, struct hclge_dev, service_task.work); 4725 4726 hclge_errhand_service_task(hdev); 4727 hclge_reset_service_task(hdev); 4728 hclge_ptp_service_task(hdev); 4729 hclge_mailbox_service_task(hdev); 4730 hclge_periodic_service_task(hdev); 4731 4732 /* Handle error recovery, reset and mbx again in case periodical task 4733 * delays the handling by calling hclge_task_schedule() in 4734 * hclge_periodic_service_task(). 4735 */ 4736 hclge_errhand_service_task(hdev); 4737 hclge_reset_service_task(hdev); 4738 hclge_mailbox_service_task(hdev); 4739} 4740 4741struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4742{ 4743 /* VF handle has no client */ 4744 if (!handle->client) 4745 return container_of(handle, struct hclge_vport, nic); 4746 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4747 return container_of(handle, struct hclge_vport, roce); 4748 else 4749 return container_of(handle, struct hclge_vport, nic); 4750} 4751 4752static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4753 struct hnae3_vector_info *vector_info) 4754{ 4755#define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4756 4757 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4758 4759 /* need an extend offset to config vector >= 64 */ 4760 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4761 vector_info->io_addr = hdev->hw.hw.io_base + 4762 HCLGE_VECTOR_REG_BASE + 4763 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4764 else 4765 vector_info->io_addr = hdev->hw.hw.io_base + 4766 HCLGE_VECTOR_EXT_REG_BASE + 4767 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4768 HCLGE_VECTOR_REG_OFFSET_H + 4769 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4770 HCLGE_VECTOR_REG_OFFSET; 4771 4772 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4773 hdev->vector_irq[idx] = vector_info->vector; 4774} 4775 4776static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4777 struct hnae3_vector_info *vector_info) 4778{ 4779 struct hclge_vport *vport = hclge_get_vport(handle); 4780 struct hnae3_vector_info *vector = vector_info; 4781 struct hclge_dev *hdev = vport->back; 4782 int alloc = 0; 4783 u16 i = 0; 4784 u16 j; 4785 4786 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4787 vector_num = min(hdev->num_msi_left, vector_num); 4788 4789 for (j = 0; j < vector_num; j++) { 4790 while (++i < hdev->num_nic_msi) { 4791 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4792 hclge_get_vector_info(hdev, i, vector); 4793 vector++; 4794 alloc++; 4795 4796 break; 4797 } 4798 } 4799 } 4800 hdev->num_msi_left -= alloc; 4801 hdev->num_msi_used += alloc; 4802 4803 return alloc; 4804} 4805 4806static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4807{ 4808 int i; 4809 4810 for (i = 0; i < hdev->num_msi; i++) 4811 if (vector == hdev->vector_irq[i]) 4812 return i; 4813 4814 return -EINVAL; 4815} 4816 4817static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4818{ 4819 struct hclge_vport *vport = hclge_get_vport(handle); 4820 struct hclge_dev *hdev = vport->back; 4821 int vector_id; 4822 4823 vector_id = hclge_get_vector_index(hdev, vector); 4824 if (vector_id < 0) { 4825 dev_err(&hdev->pdev->dev, 4826 "Get vector index fail. vector = %d\n", vector); 4827 return vector_id; 4828 } 4829 4830 hclge_free_vector(hdev, vector_id); 4831 4832 return 0; 4833} 4834 4835static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4836 u8 *key, u8 *hfunc) 4837{ 4838 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4839 struct hclge_vport *vport = hclge_get_vport(handle); 4840 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4841 4842 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4843 4844 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4845 ae_dev->dev_specs.rss_ind_tbl_size); 4846 4847 return 0; 4848} 4849 4850static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4851 const u8 *key, const u8 hfunc) 4852{ 4853 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4854 struct hclge_vport *vport = hclge_get_vport(handle); 4855 struct hclge_dev *hdev = vport->back; 4856 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4857 int ret, i; 4858 4859 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4860 if (ret) { 4861 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4862 return ret; 4863 } 4864 4865 /* Update the shadow RSS table with user specified qids */ 4866 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4867 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4868 4869 /* Update the hardware */ 4870 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4871 rss_cfg->rss_indirection_tbl); 4872} 4873 4874static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4875 const struct ethtool_rxfh_fields *nfc) 4876{ 4877 struct hclge_vport *vport = hclge_get_vport(handle); 4878 struct hclge_dev *hdev = vport->back; 4879 int ret; 4880 4881 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4882 &hdev->rss_cfg, nfc); 4883 if (ret) { 4884 dev_err(&hdev->pdev->dev, 4885 "failed to set rss tuple, ret = %d.\n", ret); 4886 return ret; 4887 } 4888 4889 return 0; 4890} 4891 4892static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4893 struct ethtool_rxfh_fields *nfc) 4894{ 4895 struct hclge_vport *vport = hclge_get_vport(handle); 4896 u8 tuple_sets; 4897 int ret; 4898 4899 nfc->data = 0; 4900 4901 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4902 &tuple_sets); 4903 if (ret || !tuple_sets) 4904 return ret; 4905 4906 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4907 4908 return 0; 4909} 4910 4911static int hclge_get_tc_size(struct hnae3_handle *handle) 4912{ 4913 struct hclge_vport *vport = hclge_get_vport(handle); 4914 struct hclge_dev *hdev = vport->back; 4915 4916 return hdev->pf_rss_size_max; 4917} 4918 4919static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4920{ 4921 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4922 struct hclge_vport *vport = hdev->vport; 4923 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4924 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4925 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4926 struct hnae3_tc_info *tc_info; 4927 u16 roundup_size; 4928 u16 rss_size; 4929 int i; 4930 4931 tc_info = &vport->nic.kinfo.tc_info; 4932 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4933 rss_size = tc_info->tqp_count[i]; 4934 tc_valid[i] = 0; 4935 4936 if (!(hdev->hw_tc_map & BIT(i))) 4937 continue; 4938 4939 /* tc_size set to hardware is the log2 of roundup power of two 4940 * of rss_size, the acutal queue size is limited by indirection 4941 * table. 4942 */ 4943 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4944 rss_size == 0) { 4945 dev_err(&hdev->pdev->dev, 4946 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4947 rss_size); 4948 return -EINVAL; 4949 } 4950 4951 roundup_size = roundup_pow_of_two(rss_size); 4952 roundup_size = ilog2(roundup_size); 4953 4954 tc_valid[i] = 1; 4955 tc_size[i] = roundup_size; 4956 tc_offset[i] = tc_info->tqp_offset[i]; 4957 } 4958 4959 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4960 tc_size); 4961} 4962 4963int hclge_rss_init_hw(struct hclge_dev *hdev) 4964{ 4965 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4966 u8 *key = hdev->rss_cfg.rss_hash_key; 4967 u8 hfunc = hdev->rss_cfg.rss_algo; 4968 int ret; 4969 4970 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4971 rss_indir); 4972 if (ret) 4973 return ret; 4974 4975 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4976 if (ret) 4977 return ret; 4978 4979 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4980 if (ret) 4981 return ret; 4982 4983 return hclge_init_rss_tc_mode(hdev); 4984} 4985 4986int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4987 int vector_id, bool en, 4988 struct hnae3_ring_chain_node *ring_chain) 4989{ 4990 struct hclge_dev *hdev = vport->back; 4991 struct hnae3_ring_chain_node *node; 4992 struct hclge_desc desc; 4993 struct hclge_ctrl_vector_chain_cmd *req = 4994 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4995 enum hclge_comm_cmd_status status; 4996 enum hclge_opcode_type op; 4997 u16 tqp_type_and_id; 4998 int i; 4999 5000 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 5001 hclge_cmd_setup_basic_desc(&desc, op, false); 5002 req->int_vector_id_l = hnae3_get_field(vector_id, 5003 HCLGE_VECTOR_ID_L_M, 5004 HCLGE_VECTOR_ID_L_S); 5005 req->int_vector_id_h = hnae3_get_field(vector_id, 5006 HCLGE_VECTOR_ID_H_M, 5007 HCLGE_VECTOR_ID_H_S); 5008 5009 i = 0; 5010 for (node = ring_chain; node; node = node->next) { 5011 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 5012 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 5013 HCLGE_INT_TYPE_S, 5014 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 5015 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 5016 HCLGE_TQP_ID_S, node->tqp_index); 5017 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 5018 HCLGE_INT_GL_IDX_S, 5019 hnae3_get_field(node->int_gl_idx, 5020 HNAE3_RING_GL_IDX_M, 5021 HNAE3_RING_GL_IDX_S)); 5022 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 5023 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 5024 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 5025 req->vfid = vport->vport_id; 5026 5027 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5028 if (status) { 5029 dev_err(&hdev->pdev->dev, 5030 "Map TQP fail, status is %d.\n", 5031 status); 5032 return -EIO; 5033 } 5034 i = 0; 5035 5036 hclge_cmd_setup_basic_desc(&desc, 5037 op, 5038 false); 5039 req->int_vector_id_l = 5040 hnae3_get_field(vector_id, 5041 HCLGE_VECTOR_ID_L_M, 5042 HCLGE_VECTOR_ID_L_S); 5043 req->int_vector_id_h = 5044 hnae3_get_field(vector_id, 5045 HCLGE_VECTOR_ID_H_M, 5046 HCLGE_VECTOR_ID_H_S); 5047 } 5048 } 5049 5050 if (i > 0) { 5051 req->int_cause_num = i; 5052 req->vfid = vport->vport_id; 5053 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5054 if (status) { 5055 dev_err(&hdev->pdev->dev, 5056 "Map TQP fail, status is %d.\n", status); 5057 return -EIO; 5058 } 5059 } 5060 5061 return 0; 5062} 5063 5064static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5065 struct hnae3_ring_chain_node *ring_chain) 5066{ 5067 struct hclge_vport *vport = hclge_get_vport(handle); 5068 struct hclge_dev *hdev = vport->back; 5069 int vector_id; 5070 5071 vector_id = hclge_get_vector_index(hdev, vector); 5072 if (vector_id < 0) { 5073 dev_err(&hdev->pdev->dev, 5074 "failed to get vector index. vector=%d\n", vector); 5075 return vector_id; 5076 } 5077 5078 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5079} 5080 5081static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5082 struct hnae3_ring_chain_node *ring_chain) 5083{ 5084 struct hclge_vport *vport = hclge_get_vport(handle); 5085 struct hclge_dev *hdev = vport->back; 5086 int vector_id, ret; 5087 5088 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5089 return 0; 5090 5091 vector_id = hclge_get_vector_index(hdev, vector); 5092 if (vector_id < 0) { 5093 dev_err(&handle->pdev->dev, 5094 "Get vector index fail. ret =%d\n", vector_id); 5095 return vector_id; 5096 } 5097 5098 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5099 if (ret) 5100 dev_err(&handle->pdev->dev, 5101 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5102 vector_id, ret); 5103 5104 return ret; 5105} 5106 5107static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5108 bool en_uc, bool en_mc, bool en_bc) 5109{ 5110 struct hclge_vport *vport = &hdev->vport[vf_id]; 5111 struct hnae3_handle *handle = &vport->nic; 5112 struct hclge_promisc_cfg_cmd *req; 5113 struct hclge_desc desc; 5114 bool uc_tx_en = en_uc; 5115 u8 promisc_cfg = 0; 5116 int ret; 5117 5118 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5119 5120 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5121 req->vf_id = vf_id; 5122 5123 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5124 uc_tx_en = false; 5125 5126 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5127 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5128 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5129 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5130 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5131 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5132 req->extend_promisc = promisc_cfg; 5133 5134 /* to be compatible with DEVICE_VERSION_V1/2 */ 5135 promisc_cfg = 0; 5136 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5137 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5138 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5139 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5140 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5141 req->promisc = promisc_cfg; 5142 5143 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5144 if (ret) 5145 dev_err(&hdev->pdev->dev, 5146 "failed to set vport %u promisc mode, ret = %d.\n", 5147 vf_id, ret); 5148 5149 return ret; 5150} 5151 5152int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5153 bool en_mc_pmc, bool en_bc_pmc) 5154{ 5155 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5156 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5157} 5158 5159static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5160 bool en_mc_pmc) 5161{ 5162 struct hclge_vport *vport = hclge_get_vport(handle); 5163 struct hclge_dev *hdev = vport->back; 5164 bool en_bc_pmc = true; 5165 5166 /* For device whose version below V2, if broadcast promisc enabled, 5167 * vlan filter is always bypassed. So broadcast promisc should be 5168 * disabled until user enable promisc mode 5169 */ 5170 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5171 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5172 5173 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5174 en_bc_pmc); 5175} 5176 5177static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5178{ 5179 struct hclge_vport *vport = hclge_get_vport(handle); 5180 5181 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5182} 5183 5184static void hclge_sync_fd_state(struct hclge_dev *hdev) 5185{ 5186 if (hlist_empty(&hdev->fd_rule_list)) 5187 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5188} 5189 5190static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5191{ 5192 if (!test_bit(location, hdev->fd_bmap)) { 5193 set_bit(location, hdev->fd_bmap); 5194 hdev->hclge_fd_rule_num++; 5195 } 5196} 5197 5198static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5199{ 5200 if (test_bit(location, hdev->fd_bmap)) { 5201 clear_bit(location, hdev->fd_bmap); 5202 hdev->hclge_fd_rule_num--; 5203 } 5204} 5205 5206static void hclge_fd_free_node(struct hclge_dev *hdev, 5207 struct hclge_fd_rule *rule) 5208{ 5209 hlist_del(&rule->rule_node); 5210 kfree(rule); 5211 hclge_sync_fd_state(hdev); 5212} 5213 5214static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5215 struct hclge_fd_rule *old_rule, 5216 struct hclge_fd_rule *new_rule, 5217 enum HCLGE_FD_NODE_STATE state) 5218{ 5219 switch (state) { 5220 case HCLGE_FD_TO_ADD: 5221 case HCLGE_FD_ACTIVE: 5222 /* 1) if the new state is TO_ADD, just replace the old rule 5223 * with the same location, no matter its state, because the 5224 * new rule will be configured to the hardware. 5225 * 2) if the new state is ACTIVE, it means the new rule 5226 * has been configured to the hardware, so just replace 5227 * the old rule node with the same location. 5228 * 3) for it doesn't add a new node to the list, so it's 5229 * unnecessary to update the rule number and fd_bmap. 5230 */ 5231 new_rule->rule_node.next = old_rule->rule_node.next; 5232 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5233 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5234 kfree(new_rule); 5235 break; 5236 case HCLGE_FD_DELETED: 5237 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5238 hclge_fd_free_node(hdev, old_rule); 5239 break; 5240 case HCLGE_FD_TO_DEL: 5241 /* if new request is TO_DEL, and old rule is existent 5242 * 1) the state of old rule is TO_DEL, we need do nothing, 5243 * because we delete rule by location, other rule content 5244 * is unncessary. 5245 * 2) the state of old rule is ACTIVE, we need to change its 5246 * state to TO_DEL, so the rule will be deleted when periodic 5247 * task being scheduled. 5248 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5249 * been added to hardware, so we just delete the rule node from 5250 * fd_rule_list directly. 5251 */ 5252 if (old_rule->state == HCLGE_FD_TO_ADD) { 5253 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5254 hclge_fd_free_node(hdev, old_rule); 5255 return; 5256 } 5257 old_rule->state = HCLGE_FD_TO_DEL; 5258 break; 5259 } 5260} 5261 5262static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5263 u16 location, 5264 struct hclge_fd_rule **parent) 5265{ 5266 struct hclge_fd_rule *rule; 5267 struct hlist_node *node; 5268 5269 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5270 if (rule->location == location) 5271 return rule; 5272 else if (rule->location > location) 5273 return NULL; 5274 /* record the parent node, use to keep the nodes in fd_rule_list 5275 * in ascend order. 5276 */ 5277 *parent = rule; 5278 } 5279 5280 return NULL; 5281} 5282 5283/* insert fd rule node in ascend order according to rule->location */ 5284static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5285 struct hclge_fd_rule *rule, 5286 struct hclge_fd_rule *parent) 5287{ 5288 INIT_HLIST_NODE(&rule->rule_node); 5289 5290 if (parent) 5291 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5292 else 5293 hlist_add_head(&rule->rule_node, hlist); 5294} 5295 5296static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5297 struct hclge_fd_user_def_cfg *cfg) 5298{ 5299 struct hclge_fd_user_def_cfg_cmd *req; 5300 struct hclge_desc desc; 5301 u16 data = 0; 5302 int ret; 5303 5304 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5305 5306 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5307 5308 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5309 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5310 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5311 req->ol2_cfg = cpu_to_le16(data); 5312 5313 data = 0; 5314 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5315 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5316 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5317 req->ol3_cfg = cpu_to_le16(data); 5318 5319 data = 0; 5320 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5321 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5322 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5323 req->ol4_cfg = cpu_to_le16(data); 5324 5325 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5326 if (ret) 5327 dev_err(&hdev->pdev->dev, 5328 "failed to set fd user def data, ret= %d\n", ret); 5329 return ret; 5330} 5331 5332static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5333{ 5334 int ret; 5335 5336 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5337 return; 5338 5339 if (!locked) 5340 spin_lock_bh(&hdev->fd_rule_lock); 5341 5342 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5343 if (ret) 5344 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5345 5346 if (!locked) 5347 spin_unlock_bh(&hdev->fd_rule_lock); 5348} 5349 5350static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5351 struct hclge_fd_rule *rule) 5352{ 5353 struct hlist_head *hlist = &hdev->fd_rule_list; 5354 struct hclge_fd_rule *fd_rule, *parent = NULL; 5355 struct hclge_fd_user_def_info *info, *old_info; 5356 struct hclge_fd_user_def_cfg *cfg; 5357 5358 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5359 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5360 return 0; 5361 5362 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5363 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5364 info = &rule->ep.user_def; 5365 5366 if (!cfg->ref_cnt || cfg->offset == info->offset) 5367 return 0; 5368 5369 if (cfg->ref_cnt > 1) 5370 goto error; 5371 5372 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5373 if (fd_rule) { 5374 old_info = &fd_rule->ep.user_def; 5375 if (info->layer == old_info->layer) 5376 return 0; 5377 } 5378 5379error: 5380 dev_err(&hdev->pdev->dev, 5381 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5382 info->layer + 1); 5383 return -ENOSPC; 5384} 5385 5386static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5387 struct hclge_fd_rule *rule) 5388{ 5389 struct hclge_fd_user_def_cfg *cfg; 5390 5391 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5392 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5393 return; 5394 5395 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5396 if (!cfg->ref_cnt) { 5397 cfg->offset = rule->ep.user_def.offset; 5398 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5399 } 5400 cfg->ref_cnt++; 5401} 5402 5403static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5404 struct hclge_fd_rule *rule) 5405{ 5406 struct hclge_fd_user_def_cfg *cfg; 5407 5408 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5409 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5410 return; 5411 5412 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5413 if (!cfg->ref_cnt) 5414 return; 5415 5416 cfg->ref_cnt--; 5417 if (!cfg->ref_cnt) { 5418 cfg->offset = 0; 5419 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5420 } 5421} 5422 5423static void hclge_update_fd_list(struct hclge_dev *hdev, 5424 enum HCLGE_FD_NODE_STATE state, u16 location, 5425 struct hclge_fd_rule *new_rule) 5426{ 5427 struct hlist_head *hlist = &hdev->fd_rule_list; 5428 struct hclge_fd_rule *fd_rule, *parent = NULL; 5429 5430 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5431 if (fd_rule) { 5432 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5433 if (state == HCLGE_FD_ACTIVE) 5434 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5435 hclge_sync_fd_user_def_cfg(hdev, true); 5436 5437 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5438 return; 5439 } 5440 5441 /* it's unlikely to fail here, because we have checked the rule 5442 * exist before. 5443 */ 5444 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5445 dev_warn(&hdev->pdev->dev, 5446 "failed to delete fd rule %u, it's inexistent\n", 5447 location); 5448 return; 5449 } 5450 5451 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5452 hclge_sync_fd_user_def_cfg(hdev, true); 5453 5454 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5455 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5456 5457 if (state == HCLGE_FD_TO_ADD) { 5458 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5459 hclge_task_schedule(hdev, 0); 5460 } 5461} 5462 5463static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5464{ 5465 struct hclge_get_fd_mode_cmd *req; 5466 struct hclge_desc desc; 5467 int ret; 5468 5469 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5470 5471 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5472 5473 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5474 if (ret) { 5475 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5476 return ret; 5477 } 5478 5479 *fd_mode = req->mode; 5480 5481 return ret; 5482} 5483 5484static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5485 u32 *stage1_entry_num, 5486 u32 *stage2_entry_num, 5487 u16 *stage1_counter_num, 5488 u16 *stage2_counter_num) 5489{ 5490 struct hclge_get_fd_allocation_cmd *req; 5491 struct hclge_desc desc; 5492 int ret; 5493 5494 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5495 5496 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5497 5498 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5499 if (ret) { 5500 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5501 ret); 5502 return ret; 5503 } 5504 5505 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5506 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5507 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5508 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5509 5510 return ret; 5511} 5512 5513static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5514 enum HCLGE_FD_STAGE stage_num) 5515{ 5516 struct hclge_set_fd_key_config_cmd *req; 5517 struct hclge_fd_key_cfg *stage; 5518 struct hclge_desc desc; 5519 int ret; 5520 5521 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5522 5523 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5524 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5525 req->stage = stage_num; 5526 req->key_select = stage->key_sel; 5527 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5528 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5529 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5530 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5531 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5532 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5533 5534 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5535 if (ret) 5536 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5537 5538 return ret; 5539} 5540 5541static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5542{ 5543 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5544 5545 spin_lock_bh(&hdev->fd_rule_lock); 5546 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5547 spin_unlock_bh(&hdev->fd_rule_lock); 5548 5549 hclge_fd_set_user_def_cmd(hdev, cfg); 5550} 5551 5552static int hclge_init_fd_config(struct hclge_dev *hdev) 5553{ 5554#define LOW_2_WORDS 0x03 5555 struct hclge_fd_key_cfg *key_cfg; 5556 int ret; 5557 5558 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5559 return 0; 5560 5561 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5562 if (ret) 5563 return ret; 5564 5565 switch (hdev->fd_cfg.fd_mode) { 5566 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5567 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5568 break; 5569 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5570 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5571 break; 5572 default: 5573 dev_err(&hdev->pdev->dev, 5574 "Unsupported flow director mode %u\n", 5575 hdev->fd_cfg.fd_mode); 5576 return -EOPNOTSUPP; 5577 } 5578 5579 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5580 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5581 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5582 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5583 key_cfg->outer_sipv6_word_en = 0; 5584 key_cfg->outer_dipv6_word_en = 0; 5585 5586 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5587 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5588 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5589 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5590 5591 /* If use max 400bit key, we can support tuples for ether type */ 5592 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5593 key_cfg->tuple_active |= 5594 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5595 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5596 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5597 } 5598 5599 /* roce_type is used to filter roce frames 5600 * dst_vport is used to specify the rule 5601 */ 5602 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5603 5604 ret = hclge_get_fd_allocation(hdev, 5605 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5606 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5607 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5608 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5609 if (ret) 5610 return ret; 5611 5612 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5613} 5614 5615static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5616 int loc, u8 *key, bool is_add) 5617{ 5618 struct hclge_fd_tcam_config_1_cmd *req1; 5619 struct hclge_fd_tcam_config_2_cmd *req2; 5620 struct hclge_fd_tcam_config_3_cmd *req3; 5621 struct hclge_desc desc[3]; 5622 int ret; 5623 5624 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5625 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5626 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5627 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5628 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5629 5630 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5631 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5632 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5633 5634 req1->stage = stage; 5635 req1->xy_sel = sel_x ? 1 : 0; 5636 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5637 req1->index = cpu_to_le32(loc); 5638 req1->entry_vld = sel_x ? is_add : 0; 5639 5640 if (key) { 5641 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5642 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5643 sizeof(req2->tcam_data)); 5644 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5645 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5646 } 5647 5648 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5649 if (ret) 5650 dev_err(&hdev->pdev->dev, 5651 "config tcam key fail, ret=%d\n", 5652 ret); 5653 5654 return ret; 5655} 5656 5657static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5658 struct hclge_fd_ad_data *action) 5659{ 5660 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5661 struct hclge_fd_ad_config_cmd *req; 5662 struct hclge_desc desc; 5663 u64 ad_data = 0; 5664 int ret; 5665 5666 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5667 5668 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5669 req->index = cpu_to_le32(loc); 5670 req->stage = stage; 5671 5672 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5673 action->write_rule_id_to_bd); 5674 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5675 action->rule_id); 5676 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5677 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5678 action->override_tc); 5679 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5680 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5681 } 5682 hnae3_set_bit(ad_data, HCLGE_FD_AD_QID_H_B, 5683 action->queue_id >= HCLGE_TQP_MAX_SIZE_DEV_V2 ? 1 : 0); 5684 ad_data <<= 32; 5685 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5686 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5687 action->forward_to_direct_queue); 5688 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_L_M, HCLGE_FD_AD_QID_L_S, 5689 action->queue_id); 5690 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5691 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5692 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5693 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5694 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5695 action->next_input_key); 5696 5697 req->ad_data = cpu_to_le64(ad_data); 5698 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5699 if (ret) 5700 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5701 5702 return ret; 5703} 5704 5705static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5706 struct hclge_fd_rule *rule) 5707{ 5708 int offset, moffset, ip_offset; 5709 enum HCLGE_FD_KEY_OPT key_opt; 5710 u16 tmp_x_s, tmp_y_s; 5711 u32 tmp_x_l, tmp_y_l; 5712 u8 *p = (u8 *)rule; 5713 int i; 5714 5715 if (rule->unused_tuple & BIT(tuple_bit)) 5716 return true; 5717 5718 key_opt = tuple_key_info[tuple_bit].key_opt; 5719 offset = tuple_key_info[tuple_bit].offset; 5720 moffset = tuple_key_info[tuple_bit].moffset; 5721 5722 switch (key_opt) { 5723 case KEY_OPT_U8: 5724 calc_x(*key_x, p[offset], p[moffset]); 5725 calc_y(*key_y, p[offset], p[moffset]); 5726 5727 return true; 5728 case KEY_OPT_LE16: 5729 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5730 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5731 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5732 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5733 5734 return true; 5735 case KEY_OPT_LE32: 5736 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5737 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5738 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5739 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5740 5741 return true; 5742 case KEY_OPT_MAC: 5743 for (i = 0; i < ETH_ALEN; i++) { 5744 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5745 p[moffset + i]); 5746 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5747 p[moffset + i]); 5748 } 5749 5750 return true; 5751 case KEY_OPT_IP: 5752 ip_offset = IPV4_INDEX * sizeof(u32); 5753 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5754 *(u32 *)(&p[moffset + ip_offset])); 5755 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5756 *(u32 *)(&p[moffset + ip_offset])); 5757 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5758 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5759 5760 return true; 5761 default: 5762 return false; 5763 } 5764} 5765 5766static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5767 u8 vf_id, u8 network_port_id) 5768{ 5769 u32 port_number = 0; 5770 5771 if (port_type == HOST_PORT) { 5772 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5773 pf_id); 5774 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5775 vf_id); 5776 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5777 } else { 5778 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5779 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5780 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5781 } 5782 5783 return port_number; 5784} 5785 5786static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5787 __le32 *key_x, __le32 *key_y, 5788 struct hclge_fd_rule *rule) 5789{ 5790 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5791 u8 cur_pos = 0, tuple_size, shift_bits; 5792 unsigned int i; 5793 5794 for (i = 0; i < MAX_META_DATA; i++) { 5795 tuple_size = meta_data_key_info[i].key_length; 5796 tuple_bit = key_cfg->meta_data_active & BIT(i); 5797 5798 switch (tuple_bit) { 5799 case BIT(ROCE_TYPE): 5800 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5801 cur_pos += tuple_size; 5802 break; 5803 case BIT(DST_VPORT): 5804 port_number = hclge_get_port_number(HOST_PORT, 0, 5805 rule->vf_id, 0); 5806 hnae3_set_field(meta_data, 5807 GENMASK(cur_pos + tuple_size, cur_pos), 5808 cur_pos, port_number); 5809 cur_pos += tuple_size; 5810 break; 5811 default: 5812 break; 5813 } 5814 } 5815 5816 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5817 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5818 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5819 5820 *key_x = cpu_to_le32(tmp_x << shift_bits); 5821 *key_y = cpu_to_le32(tmp_y << shift_bits); 5822} 5823 5824/* A complete key is combined with meta data key and tuple key. 5825 * Meta data key is stored at the MSB region, and tuple key is stored at 5826 * the LSB region, unused bits will be filled 0. 5827 */ 5828static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5829 struct hclge_fd_rule *rule) 5830{ 5831 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5832 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5833 u8 *cur_key_x, *cur_key_y; 5834 u8 meta_data_region; 5835 u8 tuple_size; 5836 int ret; 5837 u32 i; 5838 5839 memset(key_x, 0, sizeof(key_x)); 5840 memset(key_y, 0, sizeof(key_y)); 5841 cur_key_x = key_x; 5842 cur_key_y = key_y; 5843 5844 for (i = 0; i < MAX_TUPLE; i++) { 5845 bool tuple_valid; 5846 5847 tuple_size = tuple_key_info[i].key_length / 8; 5848 if (!(key_cfg->tuple_active & BIT(i))) 5849 continue; 5850 5851 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5852 cur_key_y, rule); 5853 if (tuple_valid) { 5854 cur_key_x += tuple_size; 5855 cur_key_y += tuple_size; 5856 } 5857 } 5858 5859 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5860 MAX_META_DATA_LENGTH / 8; 5861 5862 hclge_fd_convert_meta_data(key_cfg, 5863 (__le32 *)(key_x + meta_data_region), 5864 (__le32 *)(key_y + meta_data_region), 5865 rule); 5866 5867 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5868 true); 5869 if (ret) { 5870 dev_err(&hdev->pdev->dev, 5871 "fd key_y config fail, loc=%u, ret=%d\n", 5872 rule->queue_id, ret); 5873 return ret; 5874 } 5875 5876 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5877 true); 5878 if (ret) 5879 dev_err(&hdev->pdev->dev, 5880 "fd key_x config fail, loc=%u, ret=%d\n", 5881 rule->queue_id, ret); 5882 return ret; 5883} 5884 5885static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5886 struct hclge_fd_rule *rule) 5887{ 5888 struct hclge_vport *vport = hdev->vport; 5889 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5890 struct hclge_fd_ad_data ad_data; 5891 5892 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5893 ad_data.ad_id = rule->location; 5894 5895 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5896 ad_data.drop_packet = true; 5897 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5898 ad_data.override_tc = true; 5899 ad_data.queue_id = 5900 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5901 ad_data.tc_size = 5902 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5903 } else { 5904 ad_data.forward_to_direct_queue = true; 5905 ad_data.queue_id = rule->queue_id; 5906 } 5907 5908 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5909 ad_data.use_counter = true; 5910 ad_data.counter_id = rule->vf_id % 5911 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5912 } else { 5913 ad_data.use_counter = false; 5914 ad_data.counter_id = 0; 5915 } 5916 5917 ad_data.use_next_stage = false; 5918 ad_data.next_input_key = 0; 5919 5920 ad_data.write_rule_id_to_bd = true; 5921 ad_data.rule_id = rule->location; 5922 5923 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5924} 5925 5926static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5927 u32 *unused_tuple) 5928{ 5929 if (!spec || !unused_tuple) 5930 return -EINVAL; 5931 5932 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5933 5934 if (!spec->ip4src) 5935 *unused_tuple |= BIT(INNER_SRC_IP); 5936 5937 if (!spec->ip4dst) 5938 *unused_tuple |= BIT(INNER_DST_IP); 5939 5940 if (!spec->psrc) 5941 *unused_tuple |= BIT(INNER_SRC_PORT); 5942 5943 if (!spec->pdst) 5944 *unused_tuple |= BIT(INNER_DST_PORT); 5945 5946 if (!spec->tos) 5947 *unused_tuple |= BIT(INNER_IP_TOS); 5948 5949 return 0; 5950} 5951 5952static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5953 u32 *unused_tuple) 5954{ 5955 if (!spec || !unused_tuple) 5956 return -EINVAL; 5957 5958 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5959 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5960 5961 if (!spec->ip4src) 5962 *unused_tuple |= BIT(INNER_SRC_IP); 5963 5964 if (!spec->ip4dst) 5965 *unused_tuple |= BIT(INNER_DST_IP); 5966 5967 if (!spec->tos) 5968 *unused_tuple |= BIT(INNER_IP_TOS); 5969 5970 if (!spec->proto) 5971 *unused_tuple |= BIT(INNER_IP_PROTO); 5972 5973 if (spec->l4_4_bytes) 5974 return -EOPNOTSUPP; 5975 5976 if (spec->ip_ver != ETH_RX_NFC_IP4) 5977 return -EOPNOTSUPP; 5978 5979 return 0; 5980} 5981 5982static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5983 u32 *unused_tuple) 5984{ 5985 if (!spec || !unused_tuple) 5986 return -EINVAL; 5987 5988 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5989 5990 /* check whether src/dst ip address used */ 5991 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5992 *unused_tuple |= BIT(INNER_SRC_IP); 5993 5994 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5995 *unused_tuple |= BIT(INNER_DST_IP); 5996 5997 if (!spec->psrc) 5998 *unused_tuple |= BIT(INNER_SRC_PORT); 5999 6000 if (!spec->pdst) 6001 *unused_tuple |= BIT(INNER_DST_PORT); 6002 6003 if (!spec->tclass) 6004 *unused_tuple |= BIT(INNER_IP_TOS); 6005 6006 return 0; 6007} 6008 6009static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 6010 u32 *unused_tuple) 6011{ 6012 if (!spec || !unused_tuple) 6013 return -EINVAL; 6014 6015 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6016 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 6017 6018 /* check whether src/dst ip address used */ 6019 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 6020 *unused_tuple |= BIT(INNER_SRC_IP); 6021 6022 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 6023 *unused_tuple |= BIT(INNER_DST_IP); 6024 6025 if (!spec->l4_proto) 6026 *unused_tuple |= BIT(INNER_IP_PROTO); 6027 6028 if (!spec->tclass) 6029 *unused_tuple |= BIT(INNER_IP_TOS); 6030 6031 if (spec->l4_4_bytes) 6032 return -EOPNOTSUPP; 6033 6034 return 0; 6035} 6036 6037static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 6038{ 6039 if (!spec || !unused_tuple) 6040 return -EINVAL; 6041 6042 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 6043 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 6044 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 6045 6046 if (is_zero_ether_addr(spec->h_source)) 6047 *unused_tuple |= BIT(INNER_SRC_MAC); 6048 6049 if (is_zero_ether_addr(spec->h_dest)) 6050 *unused_tuple |= BIT(INNER_DST_MAC); 6051 6052 if (!spec->h_proto) 6053 *unused_tuple |= BIT(INNER_ETH_TYPE); 6054 6055 return 0; 6056} 6057 6058static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 6059 struct ethtool_rx_flow_spec *fs, 6060 u32 *unused_tuple) 6061{ 6062 if (fs->flow_type & FLOW_EXT) { 6063 if (fs->h_ext.vlan_etype) { 6064 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 6065 return -EOPNOTSUPP; 6066 } 6067 6068 if (!fs->h_ext.vlan_tci) 6069 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6070 6071 if (fs->m_ext.vlan_tci && 6072 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 6073 dev_err(&hdev->pdev->dev, 6074 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6075 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6076 return -EINVAL; 6077 } 6078 } else { 6079 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6080 } 6081 6082 if (fs->flow_type & FLOW_MAC_EXT) { 6083 if (hdev->fd_cfg.fd_mode != 6084 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6085 dev_err(&hdev->pdev->dev, 6086 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6087 return -EOPNOTSUPP; 6088 } 6089 6090 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6091 *unused_tuple |= BIT(INNER_DST_MAC); 6092 else 6093 *unused_tuple &= ~BIT(INNER_DST_MAC); 6094 } 6095 6096 return 0; 6097} 6098 6099static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6100 struct hclge_fd_user_def_info *info) 6101{ 6102 switch (flow_type) { 6103 case ETHER_FLOW: 6104 info->layer = HCLGE_FD_USER_DEF_L2; 6105 *unused_tuple &= ~BIT(INNER_L2_RSV); 6106 break; 6107 case IP_USER_FLOW: 6108 case IPV6_USER_FLOW: 6109 info->layer = HCLGE_FD_USER_DEF_L3; 6110 *unused_tuple &= ~BIT(INNER_L3_RSV); 6111 break; 6112 case TCP_V4_FLOW: 6113 case UDP_V4_FLOW: 6114 case TCP_V6_FLOW: 6115 case UDP_V6_FLOW: 6116 info->layer = HCLGE_FD_USER_DEF_L4; 6117 *unused_tuple &= ~BIT(INNER_L4_RSV); 6118 break; 6119 default: 6120 return -EOPNOTSUPP; 6121 } 6122 6123 return 0; 6124} 6125 6126static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6127{ 6128 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6129} 6130 6131static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6132 struct ethtool_rx_flow_spec *fs, 6133 u32 *unused_tuple, 6134 struct hclge_fd_user_def_info *info) 6135{ 6136 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6137 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6138 u16 data, offset, data_mask, offset_mask; 6139 int ret; 6140 6141 info->layer = HCLGE_FD_USER_DEF_NONE; 6142 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6143 6144 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6145 return 0; 6146 6147 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6148 * for data, and bit32~47 is used for offset. 6149 */ 6150 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6151 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6152 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6153 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6154 6155 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6156 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6157 return -EOPNOTSUPP; 6158 } 6159 6160 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6161 dev_err(&hdev->pdev->dev, 6162 "user-def offset[%u] should be no more than %u\n", 6163 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6164 return -EINVAL; 6165 } 6166 6167 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6168 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6169 return -EINVAL; 6170 } 6171 6172 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6173 if (ret) { 6174 dev_err(&hdev->pdev->dev, 6175 "unsupported flow type for user-def bytes, ret = %d\n", 6176 ret); 6177 return ret; 6178 } 6179 6180 info->data = data; 6181 info->data_mask = data_mask; 6182 info->offset = offset; 6183 6184 return 0; 6185} 6186 6187static int hclge_fd_check_spec(struct hclge_dev *hdev, 6188 struct ethtool_rx_flow_spec *fs, 6189 u32 *unused_tuple, 6190 struct hclge_fd_user_def_info *info) 6191{ 6192 u32 flow_type; 6193 int ret; 6194 6195 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6196 dev_err(&hdev->pdev->dev, 6197 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6198 fs->location, 6199 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6200 return -EINVAL; 6201 } 6202 6203 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6204 if (ret) 6205 return ret; 6206 6207 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6208 switch (flow_type) { 6209 case SCTP_V4_FLOW: 6210 case TCP_V4_FLOW: 6211 case UDP_V4_FLOW: 6212 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6213 unused_tuple); 6214 break; 6215 case IP_USER_FLOW: 6216 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6217 unused_tuple); 6218 break; 6219 case SCTP_V6_FLOW: 6220 case TCP_V6_FLOW: 6221 case UDP_V6_FLOW: 6222 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6223 unused_tuple); 6224 break; 6225 case IPV6_USER_FLOW: 6226 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6227 unused_tuple); 6228 break; 6229 case ETHER_FLOW: 6230 if (hdev->fd_cfg.fd_mode != 6231 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6232 dev_err(&hdev->pdev->dev, 6233 "ETHER_FLOW is not supported in current fd mode!\n"); 6234 return -EOPNOTSUPP; 6235 } 6236 6237 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6238 unused_tuple); 6239 break; 6240 default: 6241 dev_err(&hdev->pdev->dev, 6242 "unsupported protocol type, protocol type = %#x\n", 6243 flow_type); 6244 return -EOPNOTSUPP; 6245 } 6246 6247 if (ret) { 6248 dev_err(&hdev->pdev->dev, 6249 "failed to check flow union tuple, ret = %d\n", 6250 ret); 6251 return ret; 6252 } 6253 6254 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6255} 6256 6257static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6258 struct hclge_fd_rule *rule, u8 ip_proto) 6259{ 6260 rule->tuples.src_ip[IPV4_INDEX] = 6261 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6262 rule->tuples_mask.src_ip[IPV4_INDEX] = 6263 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6264 6265 rule->tuples.dst_ip[IPV4_INDEX] = 6266 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6267 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6268 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6269 6270 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6271 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6272 6273 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6274 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6275 6276 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6277 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6278 6279 rule->tuples.ether_proto = ETH_P_IP; 6280 rule->tuples_mask.ether_proto = 0xFFFF; 6281 6282 rule->tuples.ip_proto = ip_proto; 6283 rule->tuples_mask.ip_proto = 0xFF; 6284} 6285 6286static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6287 struct hclge_fd_rule *rule) 6288{ 6289 rule->tuples.src_ip[IPV4_INDEX] = 6290 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6291 rule->tuples_mask.src_ip[IPV4_INDEX] = 6292 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6293 6294 rule->tuples.dst_ip[IPV4_INDEX] = 6295 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6296 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6297 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6298 6299 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6300 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6301 6302 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6303 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6304 6305 rule->tuples.ether_proto = ETH_P_IP; 6306 rule->tuples_mask.ether_proto = 0xFFFF; 6307} 6308 6309static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6310 struct hclge_fd_rule *rule, u8 ip_proto) 6311{ 6312 ipv6_addr_be32_to_cpu(rule->tuples.src_ip, 6313 fs->h_u.tcp_ip6_spec.ip6src); 6314 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, 6315 fs->m_u.tcp_ip6_spec.ip6src); 6316 6317 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, 6318 fs->h_u.tcp_ip6_spec.ip6dst); 6319 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, 6320 fs->m_u.tcp_ip6_spec.ip6dst); 6321 6322 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6323 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6324 6325 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6326 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6327 6328 rule->tuples.ether_proto = ETH_P_IPV6; 6329 rule->tuples_mask.ether_proto = 0xFFFF; 6330 6331 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6332 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6333 6334 rule->tuples.ip_proto = ip_proto; 6335 rule->tuples_mask.ip_proto = 0xFF; 6336} 6337 6338static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6339 struct hclge_fd_rule *rule) 6340{ 6341 ipv6_addr_be32_to_cpu(rule->tuples.src_ip, 6342 fs->h_u.usr_ip6_spec.ip6src); 6343 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, 6344 fs->m_u.usr_ip6_spec.ip6src); 6345 6346 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, 6347 fs->h_u.usr_ip6_spec.ip6dst); 6348 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, 6349 fs->m_u.usr_ip6_spec.ip6dst); 6350 6351 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6352 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6353 6354 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6355 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6356 6357 rule->tuples.ether_proto = ETH_P_IPV6; 6358 rule->tuples_mask.ether_proto = 0xFFFF; 6359} 6360 6361static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6362 struct hclge_fd_rule *rule) 6363{ 6364 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6365 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6366 6367 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6368 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6369 6370 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6371 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6372} 6373 6374static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6375 struct hclge_fd_rule *rule) 6376{ 6377 switch (info->layer) { 6378 case HCLGE_FD_USER_DEF_L2: 6379 rule->tuples.l2_user_def = info->data; 6380 rule->tuples_mask.l2_user_def = info->data_mask; 6381 break; 6382 case HCLGE_FD_USER_DEF_L3: 6383 rule->tuples.l3_user_def = info->data; 6384 rule->tuples_mask.l3_user_def = info->data_mask; 6385 break; 6386 case HCLGE_FD_USER_DEF_L4: 6387 rule->tuples.l4_user_def = (u32)info->data << 16; 6388 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6389 break; 6390 default: 6391 break; 6392 } 6393 6394 rule->ep.user_def = *info; 6395} 6396 6397static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6398 struct hclge_fd_rule *rule, 6399 struct hclge_fd_user_def_info *info) 6400{ 6401 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6402 6403 switch (flow_type) { 6404 case SCTP_V4_FLOW: 6405 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6406 break; 6407 case TCP_V4_FLOW: 6408 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6409 break; 6410 case UDP_V4_FLOW: 6411 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6412 break; 6413 case IP_USER_FLOW: 6414 hclge_fd_get_ip4_tuple(fs, rule); 6415 break; 6416 case SCTP_V6_FLOW: 6417 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6418 break; 6419 case TCP_V6_FLOW: 6420 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6421 break; 6422 case UDP_V6_FLOW: 6423 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6424 break; 6425 case IPV6_USER_FLOW: 6426 hclge_fd_get_ip6_tuple(fs, rule); 6427 break; 6428 case ETHER_FLOW: 6429 hclge_fd_get_ether_tuple(fs, rule); 6430 break; 6431 default: 6432 return -EOPNOTSUPP; 6433 } 6434 6435 if (fs->flow_type & FLOW_EXT) { 6436 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6437 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6438 hclge_fd_get_user_def_tuple(info, rule); 6439 } 6440 6441 if (fs->flow_type & FLOW_MAC_EXT) { 6442 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6443 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6444 } 6445 6446 return 0; 6447} 6448 6449static int hclge_fd_config_rule(struct hclge_dev *hdev, 6450 struct hclge_fd_rule *rule) 6451{ 6452 int ret; 6453 6454 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6455 if (ret) 6456 return ret; 6457 6458 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6459} 6460 6461static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6462 struct hclge_fd_rule *rule) 6463{ 6464 int ret; 6465 6466 spin_lock_bh(&hdev->fd_rule_lock); 6467 6468 if (hdev->fd_active_type != rule->rule_type && 6469 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6470 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6471 dev_err(&hdev->pdev->dev, 6472 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6473 rule->rule_type, hdev->fd_active_type); 6474 spin_unlock_bh(&hdev->fd_rule_lock); 6475 return -EINVAL; 6476 } 6477 6478 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6479 if (ret) 6480 goto out; 6481 6482 ret = hclge_clear_arfs_rules(hdev); 6483 if (ret) 6484 goto out; 6485 6486 ret = hclge_fd_config_rule(hdev, rule); 6487 if (ret) 6488 goto out; 6489 6490 rule->state = HCLGE_FD_ACTIVE; 6491 hdev->fd_active_type = rule->rule_type; 6492 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6493 6494out: 6495 spin_unlock_bh(&hdev->fd_rule_lock); 6496 return ret; 6497} 6498 6499static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6500{ 6501 struct hclge_vport *vport = hclge_get_vport(handle); 6502 struct hclge_dev *hdev = vport->back; 6503 6504 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6505} 6506 6507static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6508 u16 *vport_id, u8 *action, u16 *queue_id) 6509{ 6510 struct hclge_vport *vport = hdev->vport; 6511 6512 if (ring_cookie == RX_CLS_FLOW_DISC) { 6513 *action = HCLGE_FD_ACTION_DROP_PACKET; 6514 } else { 6515 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6516 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6517 u16 tqps; 6518 6519 /* To keep consistent with user's configuration, minus 1 when 6520 * printing 'vf', because vf id from ethtool is added 1 for vf. 6521 */ 6522 if (vf > hdev->num_req_vfs) { 6523 dev_err(&hdev->pdev->dev, 6524 "Error: vf id (%u) should be less than %u\n", 6525 vf - 1U, hdev->num_req_vfs); 6526 return -EINVAL; 6527 } 6528 6529 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6530 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6531 6532 if (ring >= tqps) { 6533 dev_err(&hdev->pdev->dev, 6534 "Error: queue id (%u) > max tqp num (%u)\n", 6535 ring, tqps - 1U); 6536 return -EINVAL; 6537 } 6538 6539 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6540 *queue_id = ring; 6541 } 6542 6543 return 0; 6544} 6545 6546static int hclge_add_fd_entry(struct hnae3_handle *handle, 6547 struct ethtool_rxnfc *cmd) 6548{ 6549 struct hclge_vport *vport = hclge_get_vport(handle); 6550 struct hclge_dev *hdev = vport->back; 6551 struct hclge_fd_user_def_info info; 6552 u16 dst_vport_id = 0, q_index = 0; 6553 struct ethtool_rx_flow_spec *fs; 6554 struct hclge_fd_rule *rule; 6555 u32 unused = 0; 6556 u8 action; 6557 int ret; 6558 6559 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6560 dev_err(&hdev->pdev->dev, 6561 "flow table director is not supported\n"); 6562 return -EOPNOTSUPP; 6563 } 6564 6565 if (!hdev->fd_en) { 6566 dev_err(&hdev->pdev->dev, 6567 "please enable flow director first\n"); 6568 return -EOPNOTSUPP; 6569 } 6570 6571 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6572 6573 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6574 if (ret) 6575 return ret; 6576 6577 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6578 &action, &q_index); 6579 if (ret) 6580 return ret; 6581 6582 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6583 if (!rule) 6584 return -ENOMEM; 6585 6586 ret = hclge_fd_get_tuple(fs, rule, &info); 6587 if (ret) { 6588 kfree(rule); 6589 return ret; 6590 } 6591 6592 rule->flow_type = fs->flow_type; 6593 rule->location = fs->location; 6594 rule->unused_tuple = unused; 6595 rule->vf_id = dst_vport_id; 6596 rule->queue_id = q_index; 6597 rule->action = action; 6598 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6599 6600 ret = hclge_add_fd_entry_common(hdev, rule); 6601 if (ret) 6602 kfree(rule); 6603 6604 return ret; 6605} 6606 6607static int hclge_del_fd_entry(struct hnae3_handle *handle, 6608 struct ethtool_rxnfc *cmd) 6609{ 6610 struct hclge_vport *vport = hclge_get_vport(handle); 6611 struct hclge_dev *hdev = vport->back; 6612 struct ethtool_rx_flow_spec *fs; 6613 int ret; 6614 6615 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6616 return -EOPNOTSUPP; 6617 6618 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6619 6620 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6621 return -EINVAL; 6622 6623 spin_lock_bh(&hdev->fd_rule_lock); 6624 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6625 !test_bit(fs->location, hdev->fd_bmap)) { 6626 dev_err(&hdev->pdev->dev, 6627 "Delete fail, rule %u is inexistent\n", fs->location); 6628 spin_unlock_bh(&hdev->fd_rule_lock); 6629 return -ENOENT; 6630 } 6631 6632 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6633 NULL, false); 6634 if (ret) 6635 goto out; 6636 6637 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6638 6639out: 6640 spin_unlock_bh(&hdev->fd_rule_lock); 6641 return ret; 6642} 6643 6644static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6645 bool clear_list) 6646{ 6647 struct hclge_fd_rule *rule; 6648 struct hlist_node *node; 6649 u16 location; 6650 6651 spin_lock_bh(&hdev->fd_rule_lock); 6652 6653 for_each_set_bit(location, hdev->fd_bmap, 6654 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6655 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6656 NULL, false); 6657 6658 if (clear_list) { 6659 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6660 rule_node) { 6661 hlist_del(&rule->rule_node); 6662 kfree(rule); 6663 } 6664 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6665 hdev->hclge_fd_rule_num = 0; 6666 bitmap_zero(hdev->fd_bmap, 6667 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6668 } 6669 6670 spin_unlock_bh(&hdev->fd_rule_lock); 6671} 6672 6673static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6674{ 6675 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6676 return; 6677 6678 hclge_clear_fd_rules_in_list(hdev, true); 6679 hclge_fd_disable_user_def(hdev); 6680} 6681 6682static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6683{ 6684 struct hclge_vport *vport = hclge_get_vport(handle); 6685 struct hclge_dev *hdev = vport->back; 6686 struct hclge_fd_rule *rule; 6687 struct hlist_node *node; 6688 6689 /* Return ok here, because reset error handling will check this 6690 * return value. If error is returned here, the reset process will 6691 * fail. 6692 */ 6693 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6694 return 0; 6695 6696 /* if fd is disabled, should not restore it when reset */ 6697 if (!hdev->fd_en) 6698 return 0; 6699 6700 spin_lock_bh(&hdev->fd_rule_lock); 6701 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6702 if (rule->state == HCLGE_FD_ACTIVE) 6703 rule->state = HCLGE_FD_TO_ADD; 6704 } 6705 spin_unlock_bh(&hdev->fd_rule_lock); 6706 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6707 6708 return 0; 6709} 6710 6711static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6712 struct ethtool_rxnfc *cmd) 6713{ 6714 struct hclge_vport *vport = hclge_get_vport(handle); 6715 struct hclge_dev *hdev = vport->back; 6716 6717 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6718 return -EOPNOTSUPP; 6719 6720 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6721 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6722 6723 return 0; 6724} 6725 6726static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6727 struct ethtool_tcpip4_spec *spec, 6728 struct ethtool_tcpip4_spec *spec_mask) 6729{ 6730 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6731 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6732 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6733 6734 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6735 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6736 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6737 6738 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6739 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6740 0 : cpu_to_be16(rule->tuples_mask.src_port); 6741 6742 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6743 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6744 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6745 6746 spec->tos = rule->tuples.ip_tos; 6747 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6748 0 : rule->tuples_mask.ip_tos; 6749} 6750 6751static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6752 struct ethtool_usrip4_spec *spec, 6753 struct ethtool_usrip4_spec *spec_mask) 6754{ 6755 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6756 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6757 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6758 6759 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6760 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6761 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6762 6763 spec->tos = rule->tuples.ip_tos; 6764 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6765 0 : rule->tuples_mask.ip_tos; 6766 6767 spec->proto = rule->tuples.ip_proto; 6768 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6769 0 : rule->tuples_mask.ip_proto; 6770 6771 spec->ip_ver = ETH_RX_NFC_IP4; 6772} 6773 6774static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6775 struct ethtool_tcpip6_spec *spec, 6776 struct ethtool_tcpip6_spec *spec_mask) 6777{ 6778 ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip); 6779 ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip); 6780 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6781 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6782 else 6783 ipv6_addr_cpu_to_be32(spec_mask->ip6src, 6784 rule->tuples_mask.src_ip); 6785 6786 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6787 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6788 else 6789 ipv6_addr_cpu_to_be32(spec_mask->ip6dst, 6790 rule->tuples_mask.dst_ip); 6791 6792 spec->tclass = rule->tuples.ip_tos; 6793 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6794 0 : rule->tuples_mask.ip_tos; 6795 6796 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6797 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6798 0 : cpu_to_be16(rule->tuples_mask.src_port); 6799 6800 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6801 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6802 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6803} 6804 6805static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6806 struct ethtool_usrip6_spec *spec, 6807 struct ethtool_usrip6_spec *spec_mask) 6808{ 6809 ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip); 6810 ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip); 6811 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6812 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6813 else 6814 ipv6_addr_cpu_to_be32(spec_mask->ip6src, 6815 rule->tuples_mask.src_ip); 6816 6817 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6818 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6819 else 6820 ipv6_addr_cpu_to_be32(spec_mask->ip6dst, 6821 rule->tuples_mask.dst_ip); 6822 6823 spec->tclass = rule->tuples.ip_tos; 6824 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6825 0 : rule->tuples_mask.ip_tos; 6826 6827 spec->l4_proto = rule->tuples.ip_proto; 6828 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6829 0 : rule->tuples_mask.ip_proto; 6830} 6831 6832static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6833 struct ethhdr *spec, 6834 struct ethhdr *spec_mask) 6835{ 6836 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6837 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6838 6839 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6840 eth_zero_addr(spec_mask->h_source); 6841 else 6842 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6843 6844 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6845 eth_zero_addr(spec_mask->h_dest); 6846 else 6847 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6848 6849 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6850 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6851 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6852} 6853 6854static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6855 struct hclge_fd_rule *rule) 6856{ 6857 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6858 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6859 fs->h_ext.data[0] = 0; 6860 fs->h_ext.data[1] = 0; 6861 fs->m_ext.data[0] = 0; 6862 fs->m_ext.data[1] = 0; 6863 } else { 6864 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6865 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6866 fs->m_ext.data[0] = 6867 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6868 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6869 } 6870} 6871 6872static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6873 struct hclge_fd_rule *rule) 6874{ 6875 if (fs->flow_type & FLOW_EXT) { 6876 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6877 fs->m_ext.vlan_tci = 6878 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6879 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6880 6881 hclge_fd_get_user_def_info(fs, rule); 6882 } 6883 6884 if (fs->flow_type & FLOW_MAC_EXT) { 6885 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6886 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6887 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6888 else 6889 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6890 rule->tuples_mask.dst_mac); 6891 } 6892} 6893 6894static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6895 u16 location) 6896{ 6897 struct hclge_fd_rule *rule = NULL; 6898 struct hlist_node *node2; 6899 6900 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6901 if (rule->location == location) 6902 return rule; 6903 else if (rule->location > location) 6904 return NULL; 6905 } 6906 6907 return NULL; 6908} 6909 6910static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6911 struct hclge_fd_rule *rule) 6912{ 6913 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6914 fs->ring_cookie = RX_CLS_FLOW_DISC; 6915 } else { 6916 u64 vf_id; 6917 6918 fs->ring_cookie = rule->queue_id; 6919 vf_id = rule->vf_id; 6920 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6921 fs->ring_cookie |= vf_id; 6922 } 6923} 6924 6925static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6926 struct ethtool_rxnfc *cmd) 6927{ 6928 struct hclge_vport *vport = hclge_get_vport(handle); 6929 struct hclge_fd_rule *rule = NULL; 6930 struct hclge_dev *hdev = vport->back; 6931 struct ethtool_rx_flow_spec *fs; 6932 6933 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6934 return -EOPNOTSUPP; 6935 6936 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6937 6938 spin_lock_bh(&hdev->fd_rule_lock); 6939 6940 rule = hclge_get_fd_rule(hdev, fs->location); 6941 if (!rule) { 6942 spin_unlock_bh(&hdev->fd_rule_lock); 6943 return -ENOENT; 6944 } 6945 6946 fs->flow_type = rule->flow_type; 6947 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6948 case SCTP_V4_FLOW: 6949 case TCP_V4_FLOW: 6950 case UDP_V4_FLOW: 6951 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6952 &fs->m_u.tcp_ip4_spec); 6953 break; 6954 case IP_USER_FLOW: 6955 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6956 &fs->m_u.usr_ip4_spec); 6957 break; 6958 case SCTP_V6_FLOW: 6959 case TCP_V6_FLOW: 6960 case UDP_V6_FLOW: 6961 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6962 &fs->m_u.tcp_ip6_spec); 6963 break; 6964 case IPV6_USER_FLOW: 6965 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6966 &fs->m_u.usr_ip6_spec); 6967 break; 6968 /* The flow type of fd rule has been checked before adding in to rule 6969 * list. As other flow types have been handled, it must be ETHER_FLOW 6970 * for the default case 6971 */ 6972 default: 6973 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6974 &fs->m_u.ether_spec); 6975 break; 6976 } 6977 6978 hclge_fd_get_ext_info(fs, rule); 6979 6980 hclge_fd_get_ring_cookie(fs, rule); 6981 6982 spin_unlock_bh(&hdev->fd_rule_lock); 6983 6984 return 0; 6985} 6986 6987static int hclge_get_all_rules(struct hnae3_handle *handle, 6988 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6989{ 6990 struct hclge_vport *vport = hclge_get_vport(handle); 6991 struct hclge_dev *hdev = vport->back; 6992 struct hclge_fd_rule *rule; 6993 struct hlist_node *node2; 6994 u32 cnt = 0; 6995 6996 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6997 return -EOPNOTSUPP; 6998 6999 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 7000 7001 spin_lock_bh(&hdev->fd_rule_lock); 7002 hlist_for_each_entry_safe(rule, node2, 7003 &hdev->fd_rule_list, rule_node) { 7004 if (cnt == cmd->rule_cnt) { 7005 spin_unlock_bh(&hdev->fd_rule_lock); 7006 return -EMSGSIZE; 7007 } 7008 7009 if (rule->state == HCLGE_FD_TO_DEL) 7010 continue; 7011 7012 rule_locs[cnt] = rule->location; 7013 cnt++; 7014 } 7015 7016 spin_unlock_bh(&hdev->fd_rule_lock); 7017 7018 cmd->rule_cnt = cnt; 7019 7020 return 0; 7021} 7022 7023static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 7024 struct hclge_fd_rule_tuples *tuples) 7025{ 7026#define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 7027#define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 7028 7029 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 7030 tuples->ip_proto = fkeys->basic.ip_proto; 7031 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 7032 7033 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 7034 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 7035 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 7036 } else { 7037 int i; 7038 7039 for (i = 0; i < IPV6_ADDR_WORDS; i++) { 7040 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 7041 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 7042 } 7043 } 7044} 7045 7046/* traverse all rules, check whether an existed rule has the same tuples */ 7047static struct hclge_fd_rule * 7048hclge_fd_search_flow_keys(struct hclge_dev *hdev, 7049 const struct hclge_fd_rule_tuples *tuples) 7050{ 7051 struct hclge_fd_rule *rule = NULL; 7052 struct hlist_node *node; 7053 7054 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7055 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 7056 return rule; 7057 } 7058 7059 return NULL; 7060} 7061 7062static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 7063 struct hclge_fd_rule *rule) 7064{ 7065 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 7066 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 7067 BIT(INNER_SRC_PORT); 7068 rule->action = 0; 7069 rule->vf_id = 0; 7070 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 7071 rule->state = HCLGE_FD_TO_ADD; 7072 if (tuples->ether_proto == ETH_P_IP) { 7073 if (tuples->ip_proto == IPPROTO_TCP) 7074 rule->flow_type = TCP_V4_FLOW; 7075 else 7076 rule->flow_type = UDP_V4_FLOW; 7077 } else { 7078 if (tuples->ip_proto == IPPROTO_TCP) 7079 rule->flow_type = TCP_V6_FLOW; 7080 else 7081 rule->flow_type = UDP_V6_FLOW; 7082 } 7083 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7084 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7085} 7086 7087static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7088 u16 flow_id, struct flow_keys *fkeys) 7089{ 7090 struct hclge_vport *vport = hclge_get_vport(handle); 7091 struct hclge_fd_rule_tuples new_tuples = {}; 7092 struct hclge_dev *hdev = vport->back; 7093 struct hclge_fd_rule *rule; 7094 u16 bit_id; 7095 7096 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7097 return -EOPNOTSUPP; 7098 7099 /* when there is already fd rule existed add by user, 7100 * arfs should not work 7101 */ 7102 spin_lock_bh(&hdev->fd_rule_lock); 7103 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7104 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7105 spin_unlock_bh(&hdev->fd_rule_lock); 7106 return -EOPNOTSUPP; 7107 } 7108 7109 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7110 7111 /* check is there flow director filter existed for this flow, 7112 * if not, create a new filter for it; 7113 * if filter exist with different queue id, modify the filter; 7114 * if filter exist with same queue id, do nothing 7115 */ 7116 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7117 if (!rule) { 7118 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7119 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7120 spin_unlock_bh(&hdev->fd_rule_lock); 7121 return -ENOSPC; 7122 } 7123 7124 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7125 if (!rule) { 7126 spin_unlock_bh(&hdev->fd_rule_lock); 7127 return -ENOMEM; 7128 } 7129 7130 rule->location = bit_id; 7131 rule->arfs.flow_id = flow_id; 7132 rule->queue_id = queue_id; 7133 hclge_fd_build_arfs_rule(&new_tuples, rule); 7134 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7135 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7136 } else if (rule->queue_id != queue_id) { 7137 rule->queue_id = queue_id; 7138 rule->state = HCLGE_FD_TO_ADD; 7139 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7140 hclge_task_schedule(hdev, 0); 7141 } 7142 spin_unlock_bh(&hdev->fd_rule_lock); 7143 return rule->location; 7144} 7145 7146static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7147{ 7148#ifdef CONFIG_RFS_ACCEL 7149 struct hnae3_handle *handle = &hdev->vport[0].nic; 7150 struct hclge_fd_rule *rule; 7151 struct hlist_node *node; 7152 7153 spin_lock_bh(&hdev->fd_rule_lock); 7154 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7155 spin_unlock_bh(&hdev->fd_rule_lock); 7156 return; 7157 } 7158 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7159 if (rule->state != HCLGE_FD_ACTIVE) 7160 continue; 7161 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7162 rule->arfs.flow_id, rule->location)) { 7163 rule->state = HCLGE_FD_TO_DEL; 7164 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7165 } 7166 } 7167 spin_unlock_bh(&hdev->fd_rule_lock); 7168#endif 7169} 7170 7171/* make sure being called after lock up with fd_rule_lock */ 7172static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7173{ 7174#ifdef CONFIG_RFS_ACCEL 7175 struct hclge_fd_rule *rule; 7176 struct hlist_node *node; 7177 int ret; 7178 7179 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7180 return 0; 7181 7182 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7183 switch (rule->state) { 7184 case HCLGE_FD_TO_DEL: 7185 case HCLGE_FD_ACTIVE: 7186 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7187 rule->location, NULL, false); 7188 if (ret) 7189 return ret; 7190 fallthrough; 7191 case HCLGE_FD_TO_ADD: 7192 hclge_fd_dec_rule_cnt(hdev, rule->location); 7193 hlist_del(&rule->rule_node); 7194 kfree(rule); 7195 break; 7196 default: 7197 break; 7198 } 7199 } 7200 hclge_sync_fd_state(hdev); 7201 7202#endif 7203 return 0; 7204} 7205 7206static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7207 struct hclge_fd_rule *rule) 7208{ 7209 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7210 struct flow_match_basic match; 7211 u16 ethtype_key, ethtype_mask; 7212 7213 flow_rule_match_basic(flow, &match); 7214 ethtype_key = ntohs(match.key->n_proto); 7215 ethtype_mask = ntohs(match.mask->n_proto); 7216 7217 if (ethtype_key == ETH_P_ALL) { 7218 ethtype_key = 0; 7219 ethtype_mask = 0; 7220 } 7221 rule->tuples.ether_proto = ethtype_key; 7222 rule->tuples_mask.ether_proto = ethtype_mask; 7223 rule->tuples.ip_proto = match.key->ip_proto; 7224 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7225 } else { 7226 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7227 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7228 } 7229} 7230 7231static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7232 struct hclge_fd_rule *rule) 7233{ 7234 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7235 struct flow_match_eth_addrs match; 7236 7237 flow_rule_match_eth_addrs(flow, &match); 7238 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7239 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7240 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7241 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7242 } else { 7243 rule->unused_tuple |= BIT(INNER_DST_MAC); 7244 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7245 } 7246} 7247 7248static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7249 struct hclge_fd_rule *rule) 7250{ 7251 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7252 struct flow_match_vlan match; 7253 7254 flow_rule_match_vlan(flow, &match); 7255 rule->tuples.vlan_tag1 = match.key->vlan_id | 7256 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7257 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7258 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7259 } else { 7260 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7261 } 7262} 7263 7264static int hclge_get_cls_key_ip(const struct flow_rule *flow, 7265 struct hclge_fd_rule *rule, 7266 struct netlink_ext_ack *extack) 7267{ 7268 u16 addr_type = 0; 7269 7270 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7271 struct flow_match_control match; 7272 7273 flow_rule_match_control(flow, &match); 7274 addr_type = match.key->addr_type; 7275 7276 if (flow_rule_has_control_flags(match.mask->flags, extack)) 7277 return -EOPNOTSUPP; 7278 } 7279 7280 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7281 struct flow_match_ipv4_addrs match; 7282 7283 flow_rule_match_ipv4_addrs(flow, &match); 7284 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7285 rule->tuples_mask.src_ip[IPV4_INDEX] = 7286 be32_to_cpu(match.mask->src); 7287 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7288 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7289 be32_to_cpu(match.mask->dst); 7290 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7291 struct flow_match_ipv6_addrs match; 7292 7293 flow_rule_match_ipv6_addrs(flow, &match); 7294 ipv6_addr_be32_to_cpu(rule->tuples.src_ip, 7295 match.key->src.s6_addr32); 7296 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, 7297 match.mask->src.s6_addr32); 7298 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, 7299 match.key->dst.s6_addr32); 7300 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, 7301 match.mask->dst.s6_addr32); 7302 } else { 7303 rule->unused_tuple |= BIT(INNER_SRC_IP); 7304 rule->unused_tuple |= BIT(INNER_DST_IP); 7305 } 7306 7307 return 0; 7308} 7309 7310static void hclge_get_cls_key_port(const struct flow_rule *flow, 7311 struct hclge_fd_rule *rule) 7312{ 7313 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7314 struct flow_match_ports match; 7315 7316 flow_rule_match_ports(flow, &match); 7317 7318 rule->tuples.src_port = be16_to_cpu(match.key->src); 7319 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7320 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7321 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7322 } else { 7323 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7324 rule->unused_tuple |= BIT(INNER_DST_PORT); 7325 } 7326} 7327 7328static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7329 struct flow_cls_offload *cls_flower, 7330 struct hclge_fd_rule *rule) 7331{ 7332 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7333 struct netlink_ext_ack *extack = cls_flower->common.extack; 7334 struct flow_dissector *dissector = flow->match.dissector; 7335 int ret; 7336 7337 if (dissector->used_keys & 7338 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 7339 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 7340 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7341 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 7342 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7343 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7344 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) { 7345 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n", 7346 dissector->used_keys); 7347 return -EOPNOTSUPP; 7348 } 7349 7350 hclge_get_cls_key_basic(flow, rule); 7351 hclge_get_cls_key_mac(flow, rule); 7352 hclge_get_cls_key_vlan(flow, rule); 7353 7354 ret = hclge_get_cls_key_ip(flow, rule, extack); 7355 if (ret) 7356 return ret; 7357 7358 hclge_get_cls_key_port(flow, rule); 7359 7360 return 0; 7361} 7362 7363static int hclge_check_cls_flower(struct hclge_dev *hdev, 7364 struct flow_cls_offload *cls_flower, int tc) 7365{ 7366 u32 prio = cls_flower->common.prio; 7367 7368 if (tc < 0 || tc > hdev->tc_max) { 7369 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7370 return -EINVAL; 7371 } 7372 7373 if (prio == 0 || 7374 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7375 dev_err(&hdev->pdev->dev, 7376 "prio %u should be in range[1, %u]\n", 7377 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7378 return -EINVAL; 7379 } 7380 7381 if (test_bit(prio - 1, hdev->fd_bmap)) { 7382 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7383 return -EINVAL; 7384 } 7385 return 0; 7386} 7387 7388static int hclge_add_cls_flower(struct hnae3_handle *handle, 7389 struct flow_cls_offload *cls_flower, 7390 int tc) 7391{ 7392 struct hclge_vport *vport = hclge_get_vport(handle); 7393 struct hclge_dev *hdev = vport->back; 7394 struct hclge_fd_rule *rule; 7395 int ret; 7396 7397 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7398 dev_err(&hdev->pdev->dev, 7399 "cls flower is not supported\n"); 7400 return -EOPNOTSUPP; 7401 } 7402 7403 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7404 if (ret) { 7405 dev_err(&hdev->pdev->dev, 7406 "failed to check cls flower params, ret = %d\n", ret); 7407 return ret; 7408 } 7409 7410 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7411 if (!rule) 7412 return -ENOMEM; 7413 7414 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7415 if (ret) { 7416 kfree(rule); 7417 return ret; 7418 } 7419 7420 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7421 rule->cls_flower.tc = tc; 7422 rule->location = cls_flower->common.prio - 1; 7423 rule->vf_id = 0; 7424 rule->cls_flower.cookie = cls_flower->cookie; 7425 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7426 7427 ret = hclge_add_fd_entry_common(hdev, rule); 7428 if (ret) 7429 kfree(rule); 7430 7431 return ret; 7432} 7433 7434static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7435 unsigned long cookie) 7436{ 7437 struct hclge_fd_rule *rule; 7438 struct hlist_node *node; 7439 7440 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7441 if (rule->cls_flower.cookie == cookie) 7442 return rule; 7443 } 7444 7445 return NULL; 7446} 7447 7448static int hclge_del_cls_flower(struct hnae3_handle *handle, 7449 struct flow_cls_offload *cls_flower) 7450{ 7451 struct hclge_vport *vport = hclge_get_vport(handle); 7452 struct hclge_dev *hdev = vport->back; 7453 struct hclge_fd_rule *rule; 7454 int ret; 7455 7456 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7457 return -EOPNOTSUPP; 7458 7459 spin_lock_bh(&hdev->fd_rule_lock); 7460 7461 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7462 if (!rule) { 7463 spin_unlock_bh(&hdev->fd_rule_lock); 7464 return -EINVAL; 7465 } 7466 7467 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7468 NULL, false); 7469 if (ret) { 7470 /* if tcam config fail, set rule state to TO_DEL, 7471 * so the rule will be deleted when periodic 7472 * task being scheduled. 7473 */ 7474 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL); 7475 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7476 spin_unlock_bh(&hdev->fd_rule_lock); 7477 return ret; 7478 } 7479 7480 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7481 spin_unlock_bh(&hdev->fd_rule_lock); 7482 7483 return 0; 7484} 7485 7486static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7487{ 7488 struct hclge_fd_rule *rule; 7489 struct hlist_node *node; 7490 int ret = 0; 7491 7492 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7493 return; 7494 7495 spin_lock_bh(&hdev->fd_rule_lock); 7496 7497 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7498 switch (rule->state) { 7499 case HCLGE_FD_TO_ADD: 7500 ret = hclge_fd_config_rule(hdev, rule); 7501 if (ret) 7502 goto out; 7503 rule->state = HCLGE_FD_ACTIVE; 7504 break; 7505 case HCLGE_FD_TO_DEL: 7506 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7507 rule->location, NULL, false); 7508 if (ret) 7509 goto out; 7510 hclge_fd_dec_rule_cnt(hdev, rule->location); 7511 hclge_fd_free_node(hdev, rule); 7512 break; 7513 default: 7514 break; 7515 } 7516 } 7517 7518out: 7519 if (ret) 7520 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7521 7522 spin_unlock_bh(&hdev->fd_rule_lock); 7523} 7524 7525static void hclge_sync_fd_table(struct hclge_dev *hdev) 7526{ 7527 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7528 return; 7529 7530 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7531 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7532 7533 hclge_clear_fd_rules_in_list(hdev, clear_list); 7534 } 7535 7536 hclge_sync_fd_user_def_cfg(hdev, false); 7537 7538 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7539} 7540 7541static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7542{ 7543 struct hclge_vport *vport = hclge_get_vport(handle); 7544 struct hclge_dev *hdev = vport->back; 7545 7546 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7547 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7548} 7549 7550static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7551{ 7552 struct hclge_vport *vport = hclge_get_vport(handle); 7553 struct hclge_dev *hdev = vport->back; 7554 7555 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7556} 7557 7558static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7559{ 7560 struct hclge_vport *vport = hclge_get_vport(handle); 7561 struct hclge_dev *hdev = vport->back; 7562 7563 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7564} 7565 7566static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7567{ 7568 struct hclge_vport *vport = hclge_get_vport(handle); 7569 struct hclge_dev *hdev = vport->back; 7570 7571 return hdev->rst_stats.hw_reset_done_cnt; 7572} 7573 7574static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7575{ 7576 struct hclge_vport *vport = hclge_get_vport(handle); 7577 struct hclge_dev *hdev = vport->back; 7578 7579 hdev->fd_en = enable; 7580 7581 if (!enable) 7582 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7583 else 7584 hclge_restore_fd_entries(handle); 7585 7586 hclge_task_schedule(hdev, 0); 7587} 7588 7589static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7590{ 7591#define HCLGE_LINK_STATUS_WAIT_CNT 3 7592 7593 struct hclge_desc desc; 7594 struct hclge_config_mac_mode_cmd *req = 7595 (struct hclge_config_mac_mode_cmd *)desc.data; 7596 u32 loop_en = 0; 7597 int ret; 7598 7599 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7600 7601 if (enable) { 7602 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7603 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7604 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7605 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7606 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7607 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7608 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7609 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7610 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7611 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7612 } 7613 7614 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7615 7616 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7617 if (ret) { 7618 dev_err(&hdev->pdev->dev, 7619 "mac enable fail, ret =%d.\n", ret); 7620 return; 7621 } 7622 7623 if (!enable) 7624 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7625 HCLGE_LINK_STATUS_WAIT_CNT); 7626} 7627 7628static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7629 u8 switch_param, u8 param_mask) 7630{ 7631 struct hclge_mac_vlan_switch_cmd *req; 7632 struct hclge_desc desc; 7633 u32 func_id; 7634 int ret; 7635 7636 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7637 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7638 7639 /* read current config parameter */ 7640 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7641 true); 7642 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7643 req->func_id = cpu_to_le32(func_id); 7644 7645 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7646 if (ret) { 7647 dev_err(&hdev->pdev->dev, 7648 "read mac vlan switch parameter fail, ret = %d\n", ret); 7649 return ret; 7650 } 7651 7652 /* modify and write new config parameter */ 7653 hclge_comm_cmd_reuse_desc(&desc, false); 7654 req->switch_param = (req->switch_param & param_mask) | switch_param; 7655 req->param_mask = param_mask; 7656 7657 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7658 if (ret) 7659 dev_err(&hdev->pdev->dev, 7660 "set mac vlan switch parameter fail, ret = %d\n", ret); 7661 return ret; 7662} 7663 7664static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7665 int link_ret) 7666{ 7667#define HCLGE_PHY_LINK_STATUS_NUM 200 7668 7669 struct phy_device *phydev = hdev->hw.mac.phydev; 7670 int i = 0; 7671 int ret; 7672 7673 do { 7674 ret = phy_read_status(phydev); 7675 if (ret) { 7676 dev_err(&hdev->pdev->dev, 7677 "phy update link status fail, ret = %d\n", ret); 7678 return; 7679 } 7680 7681 if (phydev->link == link_ret) 7682 break; 7683 7684 msleep(HCLGE_LINK_STATUS_MS); 7685 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7686} 7687 7688static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7689 int wait_cnt) 7690{ 7691 int link_status; 7692 int i = 0; 7693 int ret; 7694 7695 do { 7696 ret = hclge_get_mac_link_status(hdev, &link_status); 7697 if (ret) 7698 return ret; 7699 if (link_status == link_ret) 7700 return 0; 7701 7702 msleep(HCLGE_LINK_STATUS_MS); 7703 } while (++i < wait_cnt); 7704 return -EBUSY; 7705} 7706 7707static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7708 bool is_phy) 7709{ 7710#define HCLGE_MAC_LINK_STATUS_NUM 100 7711 7712 int link_ret; 7713 7714 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7715 7716 if (is_phy) 7717 hclge_phy_link_status_wait(hdev, link_ret); 7718 7719 return hclge_mac_link_status_wait(hdev, link_ret, 7720 HCLGE_MAC_LINK_STATUS_NUM); 7721} 7722 7723static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7724{ 7725 struct hclge_config_mac_mode_cmd *req; 7726 struct hclge_desc desc; 7727 u32 loop_en; 7728 int ret; 7729 7730 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7731 /* 1 Read out the MAC mode config at first */ 7732 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7733 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7734 if (ret) { 7735 dev_err(&hdev->pdev->dev, 7736 "mac loopback get fail, ret =%d.\n", ret); 7737 return ret; 7738 } 7739 7740 /* 2 Then setup the loopback flag */ 7741 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7742 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7743 7744 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7745 7746 /* 3 Config mac work mode with loopback flag 7747 * and its original configure parameters 7748 */ 7749 hclge_comm_cmd_reuse_desc(&desc, false); 7750 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7751 if (ret) 7752 dev_err(&hdev->pdev->dev, 7753 "mac loopback set fail, ret =%d.\n", ret); 7754 return ret; 7755} 7756 7757static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7758 enum hnae3_loop loop_mode) 7759{ 7760 struct hclge_common_lb_cmd *req; 7761 struct hclge_desc desc; 7762 u8 loop_mode_b; 7763 int ret; 7764 7765 req = (struct hclge_common_lb_cmd *)desc.data; 7766 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7767 7768 switch (loop_mode) { 7769 case HNAE3_LOOP_SERIAL_SERDES: 7770 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7771 break; 7772 case HNAE3_LOOP_PARALLEL_SERDES: 7773 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7774 break; 7775 case HNAE3_LOOP_PHY: 7776 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7777 break; 7778 default: 7779 dev_err(&hdev->pdev->dev, 7780 "unsupported loopback mode %d\n", loop_mode); 7781 return -ENOTSUPP; 7782 } 7783 7784 req->mask = loop_mode_b; 7785 if (en) 7786 req->enable = loop_mode_b; 7787 7788 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7789 if (ret) 7790 dev_err(&hdev->pdev->dev, 7791 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7792 loop_mode, ret); 7793 7794 return ret; 7795} 7796 7797static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7798{ 7799#define HCLGE_COMMON_LB_RETRY_MS 10 7800#define HCLGE_COMMON_LB_RETRY_NUM 100 7801 7802 struct hclge_common_lb_cmd *req; 7803 struct hclge_desc desc; 7804 u32 i = 0; 7805 int ret; 7806 7807 req = (struct hclge_common_lb_cmd *)desc.data; 7808 7809 do { 7810 msleep(HCLGE_COMMON_LB_RETRY_MS); 7811 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7812 true); 7813 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7814 if (ret) { 7815 dev_err(&hdev->pdev->dev, 7816 "failed to get loopback done status, ret = %d\n", 7817 ret); 7818 return ret; 7819 } 7820 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7821 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7822 7823 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7824 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7825 return -EBUSY; 7826 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7827 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7828 return -EIO; 7829 } 7830 7831 return 0; 7832} 7833 7834static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7835 enum hnae3_loop loop_mode) 7836{ 7837 int ret; 7838 7839 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7840 if (ret) 7841 return ret; 7842 7843 return hclge_cfg_common_loopback_wait(hdev); 7844} 7845 7846static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7847 enum hnae3_loop loop_mode) 7848{ 7849 int ret; 7850 7851 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7852 if (ret) 7853 return ret; 7854 7855 hclge_cfg_mac_mode(hdev, en); 7856 7857 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7858 if (ret) 7859 dev_err(&hdev->pdev->dev, 7860 "serdes loopback config mac mode timeout\n"); 7861 7862 return ret; 7863} 7864 7865static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7866 struct phy_device *phydev) 7867{ 7868 int ret; 7869 7870 if (!phydev->suspended) { 7871 ret = phy_suspend(phydev); 7872 if (ret) 7873 return ret; 7874 } 7875 7876 ret = phy_resume(phydev); 7877 if (ret) 7878 return ret; 7879 7880 return phy_loopback(phydev, true, 0); 7881} 7882 7883static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7884 struct phy_device *phydev) 7885{ 7886 int ret; 7887 7888 ret = phy_loopback(phydev, false, 0); 7889 if (ret) 7890 return ret; 7891 7892 return phy_suspend(phydev); 7893} 7894 7895static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7896{ 7897 struct phy_device *phydev = hdev->hw.mac.phydev; 7898 int ret; 7899 7900 if (!phydev) { 7901 if (hnae3_dev_phy_imp_supported(hdev)) 7902 return hclge_set_common_loopback(hdev, en, 7903 HNAE3_LOOP_PHY); 7904 return -ENOTSUPP; 7905 } 7906 7907 if (en) 7908 ret = hclge_enable_phy_loopback(hdev, phydev); 7909 else 7910 ret = hclge_disable_phy_loopback(hdev, phydev); 7911 if (ret) { 7912 dev_err(&hdev->pdev->dev, 7913 "set phy loopback fail, ret = %d\n", ret); 7914 return ret; 7915 } 7916 7917 hclge_cfg_mac_mode(hdev, en); 7918 7919 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7920 if (ret) 7921 dev_err(&hdev->pdev->dev, 7922 "phy loopback config mac mode timeout\n"); 7923 7924 return ret; 7925} 7926 7927static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7928 u16 stream_id, bool enable) 7929{ 7930 struct hclge_desc desc; 7931 struct hclge_cfg_com_tqp_queue_cmd *req = 7932 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7933 7934 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7935 req->tqp_id = cpu_to_le16(tqp_id); 7936 req->stream_id = cpu_to_le16(stream_id); 7937 if (enable) 7938 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7939 7940 return hclge_cmd_send(&hdev->hw, &desc, 1); 7941} 7942 7943static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7944{ 7945 struct hclge_vport *vport = hclge_get_vport(handle); 7946 struct hclge_dev *hdev = vport->back; 7947 int ret; 7948 u16 i; 7949 7950 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7951 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7952 if (ret) 7953 return ret; 7954 } 7955 return 0; 7956} 7957 7958static int hclge_set_loopback(struct hnae3_handle *handle, 7959 enum hnae3_loop loop_mode, bool en) 7960{ 7961 struct hclge_vport *vport = hclge_get_vport(handle); 7962 struct hclge_dev *hdev = vport->back; 7963 int ret = 0; 7964 7965 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7966 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7967 * the same, the packets are looped back in the SSU. If SSU loopback 7968 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7969 */ 7970 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7971 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7972 7973 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7974 HCLGE_SWITCH_ALW_LPBK_MASK); 7975 if (ret) 7976 return ret; 7977 } 7978 7979 switch (loop_mode) { 7980 case HNAE3_LOOP_APP: 7981 ret = hclge_set_app_loopback(hdev, en); 7982 break; 7983 case HNAE3_LOOP_SERIAL_SERDES: 7984 case HNAE3_LOOP_PARALLEL_SERDES: 7985 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7986 break; 7987 case HNAE3_LOOP_PHY: 7988 ret = hclge_set_phy_loopback(hdev, en); 7989 break; 7990 case HNAE3_LOOP_EXTERNAL: 7991 break; 7992 default: 7993 ret = -ENOTSUPP; 7994 dev_err(&hdev->pdev->dev, 7995 "loop_mode %d is not supported\n", loop_mode); 7996 break; 7997 } 7998 7999 if (ret) 8000 return ret; 8001 8002 ret = hclge_tqp_enable(handle, en); 8003 if (ret) 8004 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 8005 str_enable_disable(en), ret); 8006 8007 return ret; 8008} 8009 8010static int hclge_set_default_loopback(struct hclge_dev *hdev) 8011{ 8012 int ret; 8013 8014 ret = hclge_set_app_loopback(hdev, false); 8015 if (ret) 8016 return ret; 8017 8018 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 8019 if (ret) 8020 return ret; 8021 8022 return hclge_cfg_common_loopback(hdev, false, 8023 HNAE3_LOOP_PARALLEL_SERDES); 8024} 8025 8026static void hclge_flush_link_update(struct hclge_dev *hdev) 8027{ 8028#define HCLGE_FLUSH_LINK_TIMEOUT 100000 8029 8030 unsigned long last = hdev->serv_processed_cnt; 8031 int i = 0; 8032 8033 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 8034 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 8035 last == hdev->serv_processed_cnt) 8036 usleep_range(1, 1); 8037} 8038 8039static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 8040{ 8041 struct hclge_vport *vport = hclge_get_vport(handle); 8042 struct hclge_dev *hdev = vport->back; 8043 8044 if (enable) { 8045 hclge_task_schedule(hdev, 0); 8046 } else { 8047 /* Set the DOWN flag here to disable link updating */ 8048 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8049 8050 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 8051 hclge_flush_link_update(hdev); 8052 } 8053} 8054 8055static int hclge_ae_start(struct hnae3_handle *handle) 8056{ 8057 struct hclge_vport *vport = hclge_get_vport(handle); 8058 struct hclge_dev *hdev = vport->back; 8059 8060 /* mac enable */ 8061 hclge_cfg_mac_mode(hdev, true); 8062 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 8063 hdev->hw.mac.link = 0; 8064 8065 /* reset tqp stats */ 8066 hclge_comm_reset_tqp_stats(handle); 8067 8068 hclge_mac_start_phy(hdev); 8069 8070 return 0; 8071} 8072 8073static void hclge_ae_stop(struct hnae3_handle *handle) 8074{ 8075 struct hclge_vport *vport = hclge_get_vport(handle); 8076 struct hclge_dev *hdev = vport->back; 8077 8078 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8079 spin_lock_bh(&hdev->fd_rule_lock); 8080 hclge_clear_arfs_rules(hdev); 8081 spin_unlock_bh(&hdev->fd_rule_lock); 8082 8083 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8084 * so it only need to stop phy here. 8085 */ 8086 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 8087 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 8088 HCLGE_PFC_DISABLE); 8089 if (hdev->reset_type != HNAE3_FUNC_RESET && 8090 hdev->reset_type != HNAE3_FLR_RESET) { 8091 hclge_mac_stop_phy(hdev); 8092 hclge_update_link_status(hdev); 8093 return; 8094 } 8095 } 8096 8097 hclge_reset_tqp(handle); 8098 8099 hclge_config_mac_tnl_int(hdev, false); 8100 8101 /* Mac disable */ 8102 hclge_cfg_mac_mode(hdev, false); 8103 8104 hclge_mac_stop_phy(hdev); 8105 8106 /* reset tqp stats */ 8107 hclge_comm_reset_tqp_stats(handle); 8108 hclge_update_link_status(hdev); 8109} 8110 8111int hclge_vport_start(struct hclge_vport *vport) 8112{ 8113 struct hclge_dev *hdev = vport->back; 8114 8115 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8116 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8117 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8118 vport->last_active_jiffies = jiffies; 8119 vport->need_notify = 0; 8120 8121 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8122 if (vport->vport_id) { 8123 hclge_restore_mac_table_common(vport); 8124 hclge_restore_vport_vlan_table(vport); 8125 } else { 8126 hclge_restore_hw_table(hdev); 8127 } 8128 } 8129 8130 clear_bit(vport->vport_id, hdev->vport_config_block); 8131 8132 return 0; 8133} 8134 8135void hclge_vport_stop(struct hclge_vport *vport) 8136{ 8137 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8138 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8139 vport->need_notify = 0; 8140} 8141 8142static int hclge_client_start(struct hnae3_handle *handle) 8143{ 8144 struct hclge_vport *vport = hclge_get_vport(handle); 8145 8146 return hclge_vport_start(vport); 8147} 8148 8149static void hclge_client_stop(struct hnae3_handle *handle) 8150{ 8151 struct hclge_vport *vport = hclge_get_vport(handle); 8152 8153 hclge_vport_stop(vport); 8154} 8155 8156static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8157 u16 cmdq_resp, u8 resp_code, 8158 enum hclge_mac_vlan_tbl_opcode op) 8159{ 8160 struct hclge_dev *hdev = vport->back; 8161 8162 if (cmdq_resp) { 8163 dev_err(&hdev->pdev->dev, 8164 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8165 cmdq_resp); 8166 return -EIO; 8167 } 8168 8169 if (op == HCLGE_MAC_VLAN_ADD) { 8170 if (!resp_code || resp_code == 1) 8171 return 0; 8172 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8173 resp_code == HCLGE_ADD_MC_OVERFLOW) 8174 return -ENOSPC; 8175 8176 dev_err(&hdev->pdev->dev, 8177 "add mac addr failed for undefined, code=%u.\n", 8178 resp_code); 8179 return -EIO; 8180 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8181 if (!resp_code) { 8182 return 0; 8183 } else if (resp_code == 1) { 8184 dev_dbg(&hdev->pdev->dev, 8185 "remove mac addr failed for miss.\n"); 8186 return -ENOENT; 8187 } 8188 8189 dev_err(&hdev->pdev->dev, 8190 "remove mac addr failed for undefined, code=%u.\n", 8191 resp_code); 8192 return -EIO; 8193 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8194 if (!resp_code) { 8195 return 0; 8196 } else if (resp_code == 1) { 8197 dev_dbg(&hdev->pdev->dev, 8198 "lookup mac addr failed for miss.\n"); 8199 return -ENOENT; 8200 } 8201 8202 dev_err(&hdev->pdev->dev, 8203 "lookup mac addr failed for undefined, code=%u.\n", 8204 resp_code); 8205 return -EIO; 8206 } 8207 8208 dev_err(&hdev->pdev->dev, 8209 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8210 8211 return -EINVAL; 8212} 8213 8214static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8215{ 8216#define HCLGE_VF_NUM_IN_FIRST_DESC 192 8217 8218 unsigned int word_num; 8219 unsigned int bit_num; 8220 8221 if (vfid > 255 || vfid < 0) 8222 return -EIO; 8223 8224 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8225 word_num = vfid / 32; 8226 bit_num = vfid % 32; 8227 if (clr) 8228 desc[1].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 8229 else 8230 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8231 } else { 8232 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8233 bit_num = vfid % 32; 8234 if (clr) 8235 desc[2].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 8236 else 8237 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8238 } 8239 8240 return 0; 8241} 8242 8243static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8244{ 8245#define HCLGE_DESC_NUMBER 3 8246#define HCLGE_FUNC_NUMBER_PER_DESC 6 8247 int i, j; 8248 8249 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8250 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8251 if (desc[i].data[j]) 8252 return false; 8253 8254 return true; 8255} 8256 8257static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8258 const u8 *addr, bool is_mc) 8259{ 8260 const unsigned char *mac_addr = addr; 8261 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8262 (mac_addr[0]) | (mac_addr[1] << 8); 8263 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8264 8265 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8266 if (is_mc) { 8267 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8268 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8269 } 8270 8271 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8272 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8273} 8274 8275static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8276 struct hclge_mac_vlan_tbl_entry_cmd *req) 8277{ 8278 struct hclge_dev *hdev = vport->back; 8279 struct hclge_desc desc; 8280 u8 resp_code; 8281 u16 retval; 8282 int ret; 8283 8284 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8285 8286 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8287 8288 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8289 if (ret) { 8290 dev_err(&hdev->pdev->dev, 8291 "del mac addr failed for cmd_send, ret =%d.\n", 8292 ret); 8293 return ret; 8294 } 8295 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8296 retval = le16_to_cpu(desc.retval); 8297 8298 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8299 HCLGE_MAC_VLAN_REMOVE); 8300} 8301 8302static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8303 struct hclge_mac_vlan_tbl_entry_cmd *req, 8304 struct hclge_desc *desc, 8305 bool is_mc) 8306{ 8307 struct hclge_dev *hdev = vport->back; 8308 u8 resp_code; 8309 u16 retval; 8310 int ret; 8311 8312 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8313 if (is_mc) { 8314 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8315 memcpy(desc[0].data, 8316 req, 8317 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8318 hclge_cmd_setup_basic_desc(&desc[1], 8319 HCLGE_OPC_MAC_VLAN_ADD, 8320 true); 8321 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8322 hclge_cmd_setup_basic_desc(&desc[2], 8323 HCLGE_OPC_MAC_VLAN_ADD, 8324 true); 8325 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8326 } else { 8327 memcpy(desc[0].data, 8328 req, 8329 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8330 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8331 } 8332 if (ret) { 8333 dev_err(&hdev->pdev->dev, 8334 "lookup mac addr failed for cmd_send, ret =%d.\n", 8335 ret); 8336 return ret; 8337 } 8338 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8339 retval = le16_to_cpu(desc[0].retval); 8340 8341 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8342 HCLGE_MAC_VLAN_LKUP); 8343} 8344 8345static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8346 struct hclge_mac_vlan_tbl_entry_cmd *req, 8347 struct hclge_desc *mc_desc) 8348{ 8349 struct hclge_dev *hdev = vport->back; 8350 int cfg_status; 8351 u8 resp_code; 8352 u16 retval; 8353 int ret; 8354 8355 if (!mc_desc) { 8356 struct hclge_desc desc; 8357 8358 hclge_cmd_setup_basic_desc(&desc, 8359 HCLGE_OPC_MAC_VLAN_ADD, 8360 false); 8361 memcpy(desc.data, req, 8362 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8363 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8364 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8365 retval = le16_to_cpu(desc.retval); 8366 8367 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8368 resp_code, 8369 HCLGE_MAC_VLAN_ADD); 8370 } else { 8371 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8372 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8373 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8374 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8375 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8376 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8377 memcpy(mc_desc[0].data, req, 8378 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8379 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8380 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8381 retval = le16_to_cpu(mc_desc[0].retval); 8382 8383 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8384 resp_code, 8385 HCLGE_MAC_VLAN_ADD); 8386 } 8387 8388 if (ret) { 8389 dev_err(&hdev->pdev->dev, 8390 "add mac addr failed for cmd_send, ret =%d.\n", 8391 ret); 8392 return ret; 8393 } 8394 8395 return cfg_status; 8396} 8397 8398static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8399 u16 *allocated_size) 8400{ 8401 struct hclge_umv_spc_alc_cmd *req; 8402 struct hclge_desc desc; 8403 int ret; 8404 8405 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8406 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8407 8408 req->space_size = cpu_to_le32(space_size); 8409 8410 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8411 if (ret) { 8412 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8413 ret); 8414 return ret; 8415 } 8416 8417 *allocated_size = le32_to_cpu(desc.data[1]); 8418 8419 return 0; 8420} 8421 8422static int hclge_init_umv_space(struct hclge_dev *hdev) 8423{ 8424 u16 allocated_size = 0; 8425 int ret; 8426 8427 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8428 if (ret) 8429 return ret; 8430 8431 if (allocated_size < hdev->wanted_umv_size) 8432 dev_warn(&hdev->pdev->dev, 8433 "failed to alloc umv space, want %u, get %u\n", 8434 hdev->wanted_umv_size, allocated_size); 8435 8436 hdev->max_umv_size = allocated_size; 8437 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8438 hdev->share_umv_size = hdev->priv_umv_size + 8439 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8440 8441 if (hdev->ae_dev->dev_specs.mc_mac_size) 8442 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8443 8444 return 0; 8445} 8446 8447static void hclge_reset_umv_space(struct hclge_dev *hdev) 8448{ 8449 struct hclge_vport *vport; 8450 int i; 8451 8452 for (i = 0; i < hdev->num_alloc_vport; i++) { 8453 vport = &hdev->vport[i]; 8454 vport->used_umv_num = 0; 8455 } 8456 8457 mutex_lock(&hdev->vport_lock); 8458 hdev->share_umv_size = hdev->priv_umv_size + 8459 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8460 mutex_unlock(&hdev->vport_lock); 8461 8462 hdev->used_mc_mac_num = 0; 8463} 8464 8465static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8466{ 8467 struct hclge_dev *hdev = vport->back; 8468 bool is_full; 8469 8470 if (need_lock) 8471 mutex_lock(&hdev->vport_lock); 8472 8473 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8474 hdev->share_umv_size == 0); 8475 8476 if (need_lock) 8477 mutex_unlock(&hdev->vport_lock); 8478 8479 return is_full; 8480} 8481 8482static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8483{ 8484 struct hclge_dev *hdev = vport->back; 8485 8486 if (is_free) { 8487 if (vport->used_umv_num > hdev->priv_umv_size) 8488 hdev->share_umv_size++; 8489 8490 if (vport->used_umv_num > 0) 8491 vport->used_umv_num--; 8492 } else { 8493 if (vport->used_umv_num >= hdev->priv_umv_size && 8494 hdev->share_umv_size > 0) 8495 hdev->share_umv_size--; 8496 vport->used_umv_num++; 8497 } 8498} 8499 8500static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8501 const u8 *mac_addr) 8502{ 8503 struct hclge_mac_node *mac_node, *tmp; 8504 8505 list_for_each_entry_safe(mac_node, tmp, list, node) 8506 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8507 return mac_node; 8508 8509 return NULL; 8510} 8511 8512static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8513 enum HCLGE_MAC_NODE_STATE state) 8514{ 8515 switch (state) { 8516 /* from set_rx_mode or tmp_add_list */ 8517 case HCLGE_MAC_TO_ADD: 8518 if (mac_node->state == HCLGE_MAC_TO_DEL) 8519 mac_node->state = HCLGE_MAC_ACTIVE; 8520 break; 8521 /* only from set_rx_mode */ 8522 case HCLGE_MAC_TO_DEL: 8523 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8524 list_del(&mac_node->node); 8525 kfree(mac_node); 8526 } else { 8527 mac_node->state = HCLGE_MAC_TO_DEL; 8528 } 8529 break; 8530 /* only from tmp_add_list, the mac_node->state won't be 8531 * ACTIVE. 8532 */ 8533 case HCLGE_MAC_ACTIVE: 8534 if (mac_node->state == HCLGE_MAC_TO_ADD) 8535 mac_node->state = HCLGE_MAC_ACTIVE; 8536 8537 break; 8538 } 8539} 8540 8541int hclge_update_mac_list(struct hclge_vport *vport, 8542 enum HCLGE_MAC_NODE_STATE state, 8543 enum HCLGE_MAC_ADDR_TYPE mac_type, 8544 const unsigned char *addr) 8545{ 8546 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8547 struct hclge_dev *hdev = vport->back; 8548 struct hclge_mac_node *mac_node; 8549 struct list_head *list; 8550 8551 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8552 &vport->uc_mac_list : &vport->mc_mac_list; 8553 8554 spin_lock_bh(&vport->mac_list_lock); 8555 8556 /* if the mac addr is already in the mac list, no need to add a new 8557 * one into it, just check the mac addr state, convert it to a new 8558 * state, or just remove it, or do nothing. 8559 */ 8560 mac_node = hclge_find_mac_node(list, addr); 8561 if (mac_node) { 8562 hclge_update_mac_node(mac_node, state); 8563 spin_unlock_bh(&vport->mac_list_lock); 8564 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8565 return 0; 8566 } 8567 8568 /* if this address is never added, unnecessary to delete */ 8569 if (state == HCLGE_MAC_TO_DEL) { 8570 spin_unlock_bh(&vport->mac_list_lock); 8571 hnae3_format_mac_addr(format_mac_addr, addr); 8572 dev_err(&hdev->pdev->dev, 8573 "failed to delete address %s from mac list\n", 8574 format_mac_addr); 8575 return -ENOENT; 8576 } 8577 8578 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8579 if (!mac_node) { 8580 spin_unlock_bh(&vport->mac_list_lock); 8581 return -ENOMEM; 8582 } 8583 8584 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8585 8586 mac_node->state = state; 8587 ether_addr_copy(mac_node->mac_addr, addr); 8588 list_add_tail(&mac_node->node, list); 8589 8590 spin_unlock_bh(&vport->mac_list_lock); 8591 8592 return 0; 8593} 8594 8595static int hclge_add_uc_addr(struct hnae3_handle *handle, 8596 const unsigned char *addr) 8597{ 8598 struct hclge_vport *vport = hclge_get_vport(handle); 8599 8600 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8601 addr); 8602} 8603 8604int hclge_add_uc_addr_common(struct hclge_vport *vport, 8605 const unsigned char *addr) 8606{ 8607 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8608 struct hclge_dev *hdev = vport->back; 8609 struct hclge_mac_vlan_tbl_entry_cmd req; 8610 struct hclge_desc desc; 8611 u16 egress_port = 0; 8612 int ret; 8613 8614 /* mac addr check */ 8615 if (is_zero_ether_addr(addr) || 8616 is_broadcast_ether_addr(addr) || 8617 is_multicast_ether_addr(addr)) { 8618 hnae3_format_mac_addr(format_mac_addr, addr); 8619 dev_err(&hdev->pdev->dev, 8620 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8621 format_mac_addr, is_zero_ether_addr(addr), 8622 is_broadcast_ether_addr(addr), 8623 is_multicast_ether_addr(addr)); 8624 return -EINVAL; 8625 } 8626 8627 memset(&req, 0, sizeof(req)); 8628 8629 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8630 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8631 8632 req.egress_port = cpu_to_le16(egress_port); 8633 8634 hclge_prepare_mac_addr(&req, addr, false); 8635 8636 /* Lookup the mac address in the mac_vlan table, and add 8637 * it if the entry is inexistent. Repeated unicast entry 8638 * is not allowed in the mac vlan table. 8639 */ 8640 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8641 if (ret == -ENOENT) { 8642 mutex_lock(&hdev->vport_lock); 8643 if (!hclge_is_umv_space_full(vport, false)) { 8644 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8645 if (!ret) 8646 hclge_update_umv_space(vport, false); 8647 mutex_unlock(&hdev->vport_lock); 8648 return ret; 8649 } 8650 mutex_unlock(&hdev->vport_lock); 8651 8652 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8653 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8654 hdev->priv_umv_size); 8655 8656 return -ENOSPC; 8657 } 8658 8659 /* check if we just hit the duplicate */ 8660 if (!ret) 8661 return -EEXIST; 8662 8663 return ret; 8664} 8665 8666static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8667 const unsigned char *addr) 8668{ 8669 struct hclge_vport *vport = hclge_get_vport(handle); 8670 8671 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8672 addr); 8673} 8674 8675int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8676 const unsigned char *addr) 8677{ 8678 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8679 struct hclge_dev *hdev = vport->back; 8680 struct hclge_mac_vlan_tbl_entry_cmd req; 8681 int ret; 8682 8683 /* mac addr check */ 8684 if (is_zero_ether_addr(addr) || 8685 is_broadcast_ether_addr(addr) || 8686 is_multicast_ether_addr(addr)) { 8687 hnae3_format_mac_addr(format_mac_addr, addr); 8688 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8689 format_mac_addr); 8690 return -EINVAL; 8691 } 8692 8693 memset(&req, 0, sizeof(req)); 8694 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8695 hclge_prepare_mac_addr(&req, addr, false); 8696 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8697 if (!ret || ret == -ENOENT) { 8698 mutex_lock(&hdev->vport_lock); 8699 hclge_update_umv_space(vport, true); 8700 mutex_unlock(&hdev->vport_lock); 8701 return 0; 8702 } 8703 8704 return ret; 8705} 8706 8707static int hclge_add_mc_addr(struct hnae3_handle *handle, 8708 const unsigned char *addr) 8709{ 8710 struct hclge_vport *vport = hclge_get_vport(handle); 8711 8712 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8713 addr); 8714} 8715 8716int hclge_add_mc_addr_common(struct hclge_vport *vport, 8717 const unsigned char *addr) 8718{ 8719 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8720 struct hclge_dev *hdev = vport->back; 8721 struct hclge_mac_vlan_tbl_entry_cmd req; 8722 struct hclge_desc desc[3]; 8723 bool is_new_addr = false; 8724 int status; 8725 8726 /* mac addr check */ 8727 if (!is_multicast_ether_addr(addr)) { 8728 hnae3_format_mac_addr(format_mac_addr, addr); 8729 dev_err(&hdev->pdev->dev, 8730 "Add mc mac err! invalid mac:%s.\n", 8731 format_mac_addr); 8732 return -EINVAL; 8733 } 8734 memset(&req, 0, sizeof(req)); 8735 hclge_prepare_mac_addr(&req, addr, true); 8736 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8737 if (status) { 8738 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8739 hdev->used_mc_mac_num >= 8740 hdev->ae_dev->dev_specs.mc_mac_size) 8741 goto err_no_space; 8742 8743 is_new_addr = true; 8744 8745 /* This mac addr do not exist, add new entry for it */ 8746 memset(desc[0].data, 0, sizeof(desc[0].data)); 8747 memset(desc[1].data, 0, sizeof(desc[0].data)); 8748 memset(desc[2].data, 0, sizeof(desc[0].data)); 8749 } 8750 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8751 if (status) 8752 return status; 8753 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8754 if (status == -ENOSPC) 8755 goto err_no_space; 8756 else if (!status && is_new_addr) 8757 hdev->used_mc_mac_num++; 8758 8759 return status; 8760 8761err_no_space: 8762 /* if already overflow, not to print each time */ 8763 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8764 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8765 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8766 } 8767 8768 return -ENOSPC; 8769} 8770 8771static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8772 const unsigned char *addr) 8773{ 8774 struct hclge_vport *vport = hclge_get_vport(handle); 8775 8776 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8777 addr); 8778} 8779 8780int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8781 const unsigned char *addr) 8782{ 8783 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8784 struct hclge_dev *hdev = vport->back; 8785 struct hclge_mac_vlan_tbl_entry_cmd req; 8786 enum hclge_comm_cmd_status status; 8787 struct hclge_desc desc[3]; 8788 8789 /* mac addr check */ 8790 if (!is_multicast_ether_addr(addr)) { 8791 hnae3_format_mac_addr(format_mac_addr, addr); 8792 dev_dbg(&hdev->pdev->dev, 8793 "Remove mc mac err! invalid mac:%s.\n", 8794 format_mac_addr); 8795 return -EINVAL; 8796 } 8797 8798 memset(&req, 0, sizeof(req)); 8799 hclge_prepare_mac_addr(&req, addr, true); 8800 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8801 if (!status) { 8802 /* This mac addr exist, remove this handle's VFID for it */ 8803 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8804 if (status) 8805 return status; 8806 8807 if (hclge_is_all_function_id_zero(desc)) { 8808 /* All the vfid is zero, so need to delete this entry */ 8809 status = hclge_remove_mac_vlan_tbl(vport, &req); 8810 if (!status) 8811 hdev->used_mc_mac_num--; 8812 } else { 8813 /* Not all the vfid is zero, update the vfid */ 8814 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8815 } 8816 } else if (status == -ENOENT) { 8817 status = 0; 8818 } 8819 8820 return status; 8821} 8822 8823static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8824 struct list_head *list, 8825 enum HCLGE_MAC_ADDR_TYPE mac_type) 8826{ 8827 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8828 struct hclge_mac_node *mac_node, *tmp; 8829 int ret; 8830 8831 if (mac_type == HCLGE_MAC_ADDR_UC) 8832 sync = hclge_add_uc_addr_common; 8833 else 8834 sync = hclge_add_mc_addr_common; 8835 8836 list_for_each_entry_safe(mac_node, tmp, list, node) { 8837 ret = sync(vport, mac_node->mac_addr); 8838 if (!ret) { 8839 mac_node->state = HCLGE_MAC_ACTIVE; 8840 } else { 8841 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8842 &vport->state); 8843 8844 /* If one unicast mac address is existing in hardware, 8845 * we need to try whether other unicast mac addresses 8846 * are new addresses that can be added. 8847 * Multicast mac address can be reusable, even though 8848 * there is no space to add new multicast mac address, 8849 * we should check whether other mac addresses are 8850 * existing in hardware for reuse. 8851 */ 8852 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8853 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8854 break; 8855 } 8856 } 8857} 8858 8859static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8860 struct list_head *list, 8861 enum HCLGE_MAC_ADDR_TYPE mac_type) 8862{ 8863 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8864 struct hclge_mac_node *mac_node, *tmp; 8865 int ret; 8866 8867 if (mac_type == HCLGE_MAC_ADDR_UC) 8868 unsync = hclge_rm_uc_addr_common; 8869 else 8870 unsync = hclge_rm_mc_addr_common; 8871 8872 list_for_each_entry_safe(mac_node, tmp, list, node) { 8873 ret = unsync(vport, mac_node->mac_addr); 8874 if (!ret || ret == -ENOENT) { 8875 list_del(&mac_node->node); 8876 kfree(mac_node); 8877 } else { 8878 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8879 &vport->state); 8880 break; 8881 } 8882 } 8883} 8884 8885static bool hclge_sync_from_add_list(struct list_head *add_list, 8886 struct list_head *mac_list) 8887{ 8888 struct hclge_mac_node *mac_node, *tmp, *new_node; 8889 bool all_added = true; 8890 8891 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8892 if (mac_node->state == HCLGE_MAC_TO_ADD) 8893 all_added = false; 8894 8895 /* if the mac address from tmp_add_list is not in the 8896 * uc/mc_mac_list, it means have received a TO_DEL request 8897 * during the time window of adding the mac address into mac 8898 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8899 * then it will be removed at next time. else it must be TO_ADD, 8900 * this address hasn't been added into mac table, 8901 * so just remove the mac node. 8902 */ 8903 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8904 if (new_node) { 8905 hclge_update_mac_node(new_node, mac_node->state); 8906 list_del(&mac_node->node); 8907 kfree(mac_node); 8908 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8909 mac_node->state = HCLGE_MAC_TO_DEL; 8910 list_move_tail(&mac_node->node, mac_list); 8911 } else { 8912 list_del(&mac_node->node); 8913 kfree(mac_node); 8914 } 8915 } 8916 8917 return all_added; 8918} 8919 8920static void hclge_sync_from_del_list(struct list_head *del_list, 8921 struct list_head *mac_list) 8922{ 8923 struct hclge_mac_node *mac_node, *tmp, *new_node; 8924 8925 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8926 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8927 if (new_node) { 8928 /* If the mac addr exists in the mac list, it means 8929 * received a new TO_ADD request during the time window 8930 * of configuring the mac address. For the mac node 8931 * state is TO_ADD, and the address is already in the 8932 * in the hardware(due to delete fail), so we just need 8933 * to change the mac node state to ACTIVE. 8934 */ 8935 new_node->state = HCLGE_MAC_ACTIVE; 8936 list_del(&mac_node->node); 8937 kfree(mac_node); 8938 } else { 8939 list_move_tail(&mac_node->node, mac_list); 8940 } 8941 } 8942} 8943 8944static void hclge_update_overflow_flags(struct hclge_vport *vport, 8945 enum HCLGE_MAC_ADDR_TYPE mac_type, 8946 bool is_all_added) 8947{ 8948 if (mac_type == HCLGE_MAC_ADDR_UC) { 8949 if (is_all_added) 8950 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8951 else if (hclge_is_umv_space_full(vport, true)) 8952 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8953 } else { 8954 if (is_all_added) 8955 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8956 else 8957 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8958 } 8959} 8960 8961static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8962 enum HCLGE_MAC_ADDR_TYPE mac_type) 8963{ 8964 struct hclge_mac_node *mac_node, *tmp, *new_node; 8965 struct list_head tmp_add_list, tmp_del_list; 8966 struct list_head *list; 8967 bool all_added; 8968 8969 INIT_LIST_HEAD(&tmp_add_list); 8970 INIT_LIST_HEAD(&tmp_del_list); 8971 8972 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8973 * we can add/delete these mac addr outside the spin lock 8974 */ 8975 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8976 &vport->uc_mac_list : &vport->mc_mac_list; 8977 8978 spin_lock_bh(&vport->mac_list_lock); 8979 8980 list_for_each_entry_safe(mac_node, tmp, list, node) { 8981 switch (mac_node->state) { 8982 case HCLGE_MAC_TO_DEL: 8983 list_move_tail(&mac_node->node, &tmp_del_list); 8984 break; 8985 case HCLGE_MAC_TO_ADD: 8986 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8987 if (!new_node) 8988 goto stop_traverse; 8989 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8990 new_node->state = mac_node->state; 8991 list_add_tail(&new_node->node, &tmp_add_list); 8992 break; 8993 default: 8994 break; 8995 } 8996 } 8997 8998stop_traverse: 8999 spin_unlock_bh(&vport->mac_list_lock); 9000 9001 /* delete first, in order to get max mac table space for adding */ 9002 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9003 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 9004 9005 /* if some mac addresses were added/deleted fail, move back to the 9006 * mac_list, and retry at next time. 9007 */ 9008 spin_lock_bh(&vport->mac_list_lock); 9009 9010 hclge_sync_from_del_list(&tmp_del_list, list); 9011 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 9012 9013 spin_unlock_bh(&vport->mac_list_lock); 9014 9015 hclge_update_overflow_flags(vport, mac_type, all_added); 9016} 9017 9018static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 9019{ 9020 struct hclge_dev *hdev = vport->back; 9021 9022 if (test_bit(vport->vport_id, hdev->vport_config_block)) 9023 return false; 9024 9025 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 9026 return true; 9027 9028 return false; 9029} 9030 9031static void hclge_sync_mac_table(struct hclge_dev *hdev) 9032{ 9033 int i; 9034 9035 for (i = 0; i < hdev->num_alloc_vport; i++) { 9036 struct hclge_vport *vport = &hdev->vport[i]; 9037 9038 if (!hclge_need_sync_mac_table(vport)) 9039 continue; 9040 9041 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 9042 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 9043 } 9044} 9045 9046static void hclge_build_del_list(struct list_head *list, 9047 bool is_del_list, 9048 struct list_head *tmp_del_list) 9049{ 9050 struct hclge_mac_node *mac_cfg, *tmp; 9051 9052 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 9053 switch (mac_cfg->state) { 9054 case HCLGE_MAC_TO_DEL: 9055 case HCLGE_MAC_ACTIVE: 9056 list_move_tail(&mac_cfg->node, tmp_del_list); 9057 break; 9058 case HCLGE_MAC_TO_ADD: 9059 if (is_del_list) { 9060 list_del(&mac_cfg->node); 9061 kfree(mac_cfg); 9062 } 9063 break; 9064 } 9065 } 9066} 9067 9068static void hclge_unsync_del_list(struct hclge_vport *vport, 9069 int (*unsync)(struct hclge_vport *vport, 9070 const unsigned char *addr), 9071 bool is_del_list, 9072 struct list_head *tmp_del_list) 9073{ 9074 struct hclge_mac_node *mac_cfg, *tmp; 9075 int ret; 9076 9077 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 9078 ret = unsync(vport, mac_cfg->mac_addr); 9079 if (!ret || ret == -ENOENT) { 9080 /* clear all mac addr from hardware, but remain these 9081 * mac addr in the mac list, and restore them after 9082 * vf reset finished. 9083 */ 9084 if (!is_del_list && 9085 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9086 mac_cfg->state = HCLGE_MAC_TO_ADD; 9087 } else { 9088 list_del(&mac_cfg->node); 9089 kfree(mac_cfg); 9090 } 9091 } else if (is_del_list) { 9092 mac_cfg->state = HCLGE_MAC_TO_DEL; 9093 } 9094 } 9095} 9096 9097void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9098 enum HCLGE_MAC_ADDR_TYPE mac_type) 9099{ 9100 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9101 struct hclge_dev *hdev = vport->back; 9102 struct list_head tmp_del_list, *list; 9103 9104 if (mac_type == HCLGE_MAC_ADDR_UC) { 9105 list = &vport->uc_mac_list; 9106 unsync = hclge_rm_uc_addr_common; 9107 } else { 9108 list = &vport->mc_mac_list; 9109 unsync = hclge_rm_mc_addr_common; 9110 } 9111 9112 INIT_LIST_HEAD(&tmp_del_list); 9113 9114 if (!is_del_list) 9115 set_bit(vport->vport_id, hdev->vport_config_block); 9116 9117 spin_lock_bh(&vport->mac_list_lock); 9118 9119 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9120 9121 spin_unlock_bh(&vport->mac_list_lock); 9122 9123 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9124 9125 spin_lock_bh(&vport->mac_list_lock); 9126 9127 hclge_sync_from_del_list(&tmp_del_list, list); 9128 9129 spin_unlock_bh(&vport->mac_list_lock); 9130} 9131 9132/* remove all mac address when uninitailize */ 9133static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9134 enum HCLGE_MAC_ADDR_TYPE mac_type) 9135{ 9136 struct hclge_mac_node *mac_node, *tmp; 9137 struct hclge_dev *hdev = vport->back; 9138 struct list_head tmp_del_list, *list; 9139 9140 INIT_LIST_HEAD(&tmp_del_list); 9141 9142 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9143 &vport->uc_mac_list : &vport->mc_mac_list; 9144 9145 spin_lock_bh(&vport->mac_list_lock); 9146 9147 list_for_each_entry_safe(mac_node, tmp, list, node) { 9148 switch (mac_node->state) { 9149 case HCLGE_MAC_TO_DEL: 9150 case HCLGE_MAC_ACTIVE: 9151 list_move_tail(&mac_node->node, &tmp_del_list); 9152 break; 9153 case HCLGE_MAC_TO_ADD: 9154 list_del(&mac_node->node); 9155 kfree(mac_node); 9156 break; 9157 } 9158 } 9159 9160 spin_unlock_bh(&vport->mac_list_lock); 9161 9162 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9163 9164 if (!list_empty(&tmp_del_list)) 9165 dev_warn(&hdev->pdev->dev, 9166 "uninit %s mac list for vport %u not completely.\n", 9167 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9168 vport->vport_id); 9169 9170 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9171 list_del(&mac_node->node); 9172 kfree(mac_node); 9173 } 9174} 9175 9176static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9177{ 9178 struct hclge_vport *vport; 9179 int i; 9180 9181 for (i = 0; i < hdev->num_alloc_vport; i++) { 9182 vport = &hdev->vport[i]; 9183 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9184 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9185 } 9186} 9187 9188static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9189 u16 cmdq_resp, u8 resp_code) 9190{ 9191#define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9192#define HCLGE_ETHERTYPE_ALREADY_ADD 1 9193#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9194#define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9195 9196 int return_status; 9197 9198 if (cmdq_resp) { 9199 dev_err(&hdev->pdev->dev, 9200 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9201 cmdq_resp); 9202 return -EIO; 9203 } 9204 9205 switch (resp_code) { 9206 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9207 case HCLGE_ETHERTYPE_ALREADY_ADD: 9208 return_status = 0; 9209 break; 9210 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9211 dev_err(&hdev->pdev->dev, 9212 "add mac ethertype failed for manager table overflow.\n"); 9213 return_status = -EIO; 9214 break; 9215 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9216 dev_err(&hdev->pdev->dev, 9217 "add mac ethertype failed for key conflict.\n"); 9218 return_status = -EIO; 9219 break; 9220 default: 9221 dev_err(&hdev->pdev->dev, 9222 "add mac ethertype failed for undefined, code=%u.\n", 9223 resp_code); 9224 return_status = -EIO; 9225 } 9226 9227 return return_status; 9228} 9229 9230static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9231 u8 *mac_addr) 9232{ 9233 struct hclge_vport *vport = hclge_get_vport(handle); 9234 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9235 struct hclge_dev *hdev = vport->back; 9236 9237 vport = hclge_get_vf_vport(hdev, vf); 9238 if (!vport) 9239 return -EINVAL; 9240 9241 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9242 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9243 dev_info(&hdev->pdev->dev, 9244 "Specified MAC(=%s) is same as before, no change committed!\n", 9245 format_mac_addr); 9246 return 0; 9247 } 9248 9249 ether_addr_copy(vport->vf_info.mac, mac_addr); 9250 9251 /* there is a timewindow for PF to know VF unalive, it may 9252 * cause send mailbox fail, but it doesn't matter, VF will 9253 * query it when reinit. 9254 */ 9255 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9256 dev_info(&hdev->pdev->dev, 9257 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9258 vf, format_mac_addr); 9259 (void)hclge_inform_reset_assert_to_vf(vport); 9260 return 0; 9261 } 9262 9263 dev_info(&hdev->pdev->dev, 9264 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9265 vf, format_mac_addr); 9266 return 0; 9267} 9268 9269static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9270 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9271{ 9272 struct hclge_desc desc; 9273 u8 resp_code; 9274 u16 retval; 9275 int ret; 9276 9277 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9278 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9279 9280 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9281 if (ret) { 9282 dev_err(&hdev->pdev->dev, 9283 "add mac ethertype failed for cmd_send, ret =%d.\n", 9284 ret); 9285 return ret; 9286 } 9287 9288 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9289 retval = le16_to_cpu(desc.retval); 9290 9291 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9292} 9293 9294static int init_mgr_tbl(struct hclge_dev *hdev) 9295{ 9296 int ret; 9297 u32 i; 9298 9299 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9300 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9301 if (ret) { 9302 dev_err(&hdev->pdev->dev, 9303 "add mac ethertype failed, ret =%d.\n", 9304 ret); 9305 return ret; 9306 } 9307 } 9308 9309 return 0; 9310} 9311 9312static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9313{ 9314 struct hclge_vport *vport = hclge_get_vport(handle); 9315 struct hclge_dev *hdev = vport->back; 9316 9317 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9318} 9319 9320int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9321 const u8 *old_addr, const u8 *new_addr) 9322{ 9323 struct list_head *list = &vport->uc_mac_list; 9324 struct hclge_mac_node *old_node, *new_node; 9325 9326 new_node = hclge_find_mac_node(list, new_addr); 9327 if (!new_node) { 9328 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9329 if (!new_node) 9330 return -ENOMEM; 9331 9332 new_node->state = HCLGE_MAC_TO_ADD; 9333 ether_addr_copy(new_node->mac_addr, new_addr); 9334 list_add(&new_node->node, list); 9335 } else { 9336 if (new_node->state == HCLGE_MAC_TO_DEL) 9337 new_node->state = HCLGE_MAC_ACTIVE; 9338 9339 /* make sure the new addr is in the list head, avoid dev 9340 * addr may be not re-added into mac table for the umv space 9341 * limitation after global/imp reset which will clear mac 9342 * table by hardware. 9343 */ 9344 list_move(&new_node->node, list); 9345 } 9346 9347 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9348 old_node = hclge_find_mac_node(list, old_addr); 9349 if (old_node) { 9350 if (old_node->state == HCLGE_MAC_TO_ADD) { 9351 list_del(&old_node->node); 9352 kfree(old_node); 9353 } else { 9354 old_node->state = HCLGE_MAC_TO_DEL; 9355 } 9356 } 9357 } 9358 9359 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9360 9361 return 0; 9362} 9363 9364static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9365 bool is_first) 9366{ 9367 const unsigned char *new_addr = (const unsigned char *)p; 9368 struct hclge_vport *vport = hclge_get_vport(handle); 9369 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9370 struct hclge_dev *hdev = vport->back; 9371 unsigned char *old_addr = NULL; 9372 int ret; 9373 9374 /* mac addr check */ 9375 if (is_zero_ether_addr(new_addr) || 9376 is_broadcast_ether_addr(new_addr) || 9377 is_multicast_ether_addr(new_addr)) { 9378 hnae3_format_mac_addr(format_mac_addr, new_addr); 9379 dev_err(&hdev->pdev->dev, 9380 "change uc mac err! invalid mac: %s.\n", 9381 format_mac_addr); 9382 return -EINVAL; 9383 } 9384 9385 ret = hclge_pause_addr_cfg(hdev, new_addr); 9386 if (ret) { 9387 dev_err(&hdev->pdev->dev, 9388 "failed to configure mac pause address, ret = %d\n", 9389 ret); 9390 return ret; 9391 } 9392 9393 if (!is_first) 9394 old_addr = hdev->hw.mac.mac_addr; 9395 9396 spin_lock_bh(&vport->mac_list_lock); 9397 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9398 if (ret) { 9399 hnae3_format_mac_addr(format_mac_addr, new_addr); 9400 dev_err(&hdev->pdev->dev, 9401 "failed to change the mac addr:%s, ret = %d\n", 9402 format_mac_addr, ret); 9403 spin_unlock_bh(&vport->mac_list_lock); 9404 9405 if (!is_first) 9406 hclge_pause_addr_cfg(hdev, old_addr); 9407 9408 return ret; 9409 } 9410 /* we must update dev addr with spin lock protect, preventing dev addr 9411 * being removed by set_rx_mode path. 9412 */ 9413 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9414 spin_unlock_bh(&vport->mac_list_lock); 9415 9416 hclge_task_schedule(hdev, 0); 9417 9418 return 0; 9419} 9420 9421static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9422{ 9423 struct mii_ioctl_data *data = if_mii(ifr); 9424 9425 if (!hnae3_dev_phy_imp_supported(hdev)) 9426 return -EOPNOTSUPP; 9427 9428 switch (cmd) { 9429 case SIOCGMIIPHY: 9430 data->phy_id = hdev->hw.mac.phy_addr; 9431 /* this command reads phy id and register at the same time */ 9432 fallthrough; 9433 case SIOCGMIIREG: 9434 return hclge_read_phy_reg(hdev, data->reg_num, &data->val_out); 9435 9436 case SIOCSMIIREG: 9437 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9438 default: 9439 return -EOPNOTSUPP; 9440 } 9441} 9442 9443static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9444 int cmd) 9445{ 9446 struct hclge_vport *vport = hclge_get_vport(handle); 9447 struct hclge_dev *hdev = vport->back; 9448 9449 if (!hdev->hw.mac.phydev) 9450 return hclge_mii_ioctl(hdev, ifr, cmd); 9451 9452 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9453} 9454 9455static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9456 bool bypass_en) 9457{ 9458 struct hclge_port_vlan_filter_bypass_cmd *req; 9459 struct hclge_desc desc; 9460 int ret; 9461 9462 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9463 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9464 req->vf_id = vf_id; 9465 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9466 bypass_en ? 1 : 0); 9467 9468 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9469 if (ret) 9470 dev_err(&hdev->pdev->dev, 9471 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9472 vf_id, ret); 9473 9474 return ret; 9475} 9476 9477static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9478 u8 fe_type, bool filter_en, u8 vf_id) 9479{ 9480 struct hclge_vlan_filter_ctrl_cmd *req; 9481 struct hclge_desc desc; 9482 int ret; 9483 9484 /* read current vlan filter parameter */ 9485 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9486 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9487 req->vlan_type = vlan_type; 9488 req->vf_id = vf_id; 9489 9490 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9491 if (ret) { 9492 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9493 vf_id, ret); 9494 return ret; 9495 } 9496 9497 /* modify and write new config parameter */ 9498 hclge_comm_cmd_reuse_desc(&desc, false); 9499 req->vlan_fe = filter_en ? 9500 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9501 9502 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9503 if (ret) 9504 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9505 vf_id, ret); 9506 9507 return ret; 9508} 9509 9510static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9511{ 9512 struct hclge_dev *hdev = vport->back; 9513 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9514 int ret; 9515 9516 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9517 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9518 HCLGE_FILTER_FE_EGRESS_V1_B, 9519 enable, vport->vport_id); 9520 9521 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9522 HCLGE_FILTER_FE_EGRESS, enable, 9523 vport->vport_id); 9524 if (ret) 9525 return ret; 9526 9527 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9528 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9529 !enable); 9530 } else if (!vport->vport_id) { 9531 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9532 enable = false; 9533 9534 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9535 HCLGE_FILTER_FE_INGRESS, 9536 enable, 0); 9537 } 9538 9539 return ret; 9540} 9541 9542static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9543{ 9544 struct hnae3_handle *handle = &vport->nic; 9545 struct hclge_vport_vlan_cfg *vlan, *tmp; 9546 struct hclge_dev *hdev = vport->back; 9547 9548 if (vport->vport_id) { 9549 if (vport->port_base_vlan_cfg.state != 9550 HNAE3_PORT_BASE_VLAN_DISABLE) 9551 return true; 9552 9553 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9554 return false; 9555 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9556 return false; 9557 } 9558 9559 if (!vport->req_vlan_fltr_en) 9560 return false; 9561 9562 /* compatible with former device, always enable vlan filter */ 9563 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9564 return true; 9565 9566 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9567 if (vlan->vlan_id != 0) 9568 return true; 9569 9570 return false; 9571} 9572 9573static int __hclge_enable_vport_vlan_filter(struct hclge_vport *vport, 9574 bool request_en) 9575{ 9576 bool need_en; 9577 int ret; 9578 9579 need_en = hclge_need_enable_vport_vlan_filter(vport); 9580 if (need_en == vport->cur_vlan_fltr_en) 9581 return 0; 9582 9583 ret = hclge_set_vport_vlan_filter(vport, need_en); 9584 if (ret) 9585 return ret; 9586 9587 vport->cur_vlan_fltr_en = need_en; 9588 9589 return 0; 9590} 9591 9592int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9593{ 9594 struct hclge_dev *hdev = vport->back; 9595 int ret; 9596 9597 mutex_lock(&hdev->vport_lock); 9598 vport->req_vlan_fltr_en = request_en; 9599 ret = __hclge_enable_vport_vlan_filter(vport, request_en); 9600 mutex_unlock(&hdev->vport_lock); 9601 9602 return ret; 9603} 9604 9605static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9606{ 9607 struct hclge_vport *vport = hclge_get_vport(handle); 9608 9609 return hclge_enable_vport_vlan_filter(vport, enable); 9610} 9611 9612static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9613 bool is_kill, u16 vlan, 9614 struct hclge_desc *desc) 9615{ 9616 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9617 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9618 u8 vf_byte_val; 9619 u8 vf_byte_off; 9620 int ret; 9621 9622 hclge_cmd_setup_basic_desc(&desc[0], 9623 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9624 hclge_cmd_setup_basic_desc(&desc[1], 9625 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9626 9627 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9628 9629 vf_byte_off = vfid / 8; 9630 vf_byte_val = 1 << (vfid % 8); 9631 9632 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9633 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9634 9635 req0->vlan_id = cpu_to_le16(vlan); 9636 req0->vlan_cfg = is_kill; 9637 9638 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9639 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9640 else 9641 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9642 9643 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9644 if (ret) { 9645 dev_err(&hdev->pdev->dev, 9646 "Send vf vlan command fail, ret =%d.\n", 9647 ret); 9648 return ret; 9649 } 9650 9651 return 0; 9652} 9653 9654static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9655 bool is_kill, struct hclge_desc *desc) 9656{ 9657 struct hclge_vlan_filter_vf_cfg_cmd *req; 9658 9659 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9660 9661 if (!is_kill) { 9662#define HCLGE_VF_VLAN_NO_ENTRY 2 9663 if (!req->resp_code || req->resp_code == 1) 9664 return 0; 9665 9666 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9667 set_bit(vfid, hdev->vf_vlan_full); 9668 dev_warn(&hdev->pdev->dev, 9669 "vf vlan table is full, vf vlan filter is disabled\n"); 9670 return 0; 9671 } 9672 9673 dev_err(&hdev->pdev->dev, 9674 "Add vf vlan filter fail, ret =%u.\n", 9675 req->resp_code); 9676 } else { 9677#define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9678 if (!req->resp_code) 9679 return 0; 9680 9681 /* vf vlan filter is disabled when vf vlan table is full, 9682 * then new vlan id will not be added into vf vlan table. 9683 * Just return 0 without warning, avoid massive verbose 9684 * print logs when unload. 9685 */ 9686 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9687 return 0; 9688 9689 dev_err(&hdev->pdev->dev, 9690 "Kill vf vlan filter fail, ret =%u.\n", 9691 req->resp_code); 9692 } 9693 9694 return -EIO; 9695} 9696 9697static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9698 bool is_kill, u16 vlan) 9699{ 9700 struct hclge_vport *vport = &hdev->vport[vfid]; 9701 struct hclge_desc desc[2]; 9702 int ret; 9703 9704 /* if vf vlan table is full, firmware will close vf vlan filter, it 9705 * is unable and unnecessary to add new vlan id to vf vlan filter. 9706 * If spoof check is enable, and vf vlan is full, it shouldn't add 9707 * new vlan, because tx packets with these vlan id will be dropped. 9708 */ 9709 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9710 if (vport->vf_info.spoofchk && vlan) { 9711 dev_err(&hdev->pdev->dev, 9712 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9713 return -EPERM; 9714 } 9715 return 0; 9716 } 9717 9718 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9719 if (ret) 9720 return ret; 9721 9722 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9723} 9724 9725static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9726 u16 vlan_id, bool is_kill) 9727{ 9728 struct hclge_vlan_filter_pf_cfg_cmd *req; 9729 struct hclge_desc desc; 9730 u8 vlan_offset_byte_val; 9731 u8 vlan_offset_byte; 9732 u8 vlan_offset_160; 9733 int ret; 9734 9735 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9736 9737 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9738 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9739 HCLGE_VLAN_BYTE_SIZE; 9740 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9741 9742 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9743 req->vlan_offset = vlan_offset_160; 9744 req->vlan_cfg = is_kill; 9745 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9746 9747 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9748 if (ret) 9749 dev_err(&hdev->pdev->dev, 9750 "port vlan command, send fail, ret =%d.\n", ret); 9751 return ret; 9752} 9753 9754static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9755 u16 vlan_id, bool is_kill) 9756{ 9757 /* vlan 0 may be added twice when 8021q module is enabled */ 9758 if (!is_kill && !vlan_id && 9759 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9760 return false; 9761 9762 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9763 dev_warn(&hdev->pdev->dev, 9764 "Add port vlan failed, vport %u is already in vlan %u\n", 9765 vport_id, vlan_id); 9766 return false; 9767 } 9768 9769 if (is_kill && 9770 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9771 dev_warn(&hdev->pdev->dev, 9772 "Delete port vlan failed, vport %u is not in vlan %u\n", 9773 vport_id, vlan_id); 9774 return false; 9775 } 9776 9777 return true; 9778} 9779 9780static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9781 u16 vport_id, u16 vlan_id, 9782 bool is_kill) 9783{ 9784 u16 vport_idx, vport_num = 0; 9785 int ret; 9786 9787 if (is_kill && !vlan_id) 9788 return 0; 9789 9790 if (vlan_id >= VLAN_N_VID) 9791 return -EINVAL; 9792 9793 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9794 if (ret) { 9795 dev_err(&hdev->pdev->dev, 9796 "Set %u vport vlan filter config fail, ret =%d.\n", 9797 vport_id, ret); 9798 return ret; 9799 } 9800 9801 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9802 return 0; 9803 9804 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9805 vport_num++; 9806 9807 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9808 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9809 is_kill); 9810 9811 return ret; 9812} 9813 9814static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9815{ 9816 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9817 struct hclge_vport_vtag_tx_cfg_cmd *req; 9818 struct hclge_dev *hdev = vport->back; 9819 struct hclge_desc desc; 9820 u16 bmap_index; 9821 int status; 9822 9823 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9824 9825 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9826 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9827 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9828 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9829 vcfg->accept_tag1 ? 1 : 0); 9830 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9831 vcfg->accept_untag1 ? 1 : 0); 9832 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9833 vcfg->accept_tag2 ? 1 : 0); 9834 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9835 vcfg->accept_untag2 ? 1 : 0); 9836 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9837 vcfg->insert_tag1_en ? 1 : 0); 9838 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9839 vcfg->insert_tag2_en ? 1 : 0); 9840 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9841 vcfg->tag_shift_mode_en ? 1 : 0); 9842 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9843 9844 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9845 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9846 HCLGE_VF_NUM_PER_BYTE; 9847 req->vf_bitmap[bmap_index] = 9848 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9849 9850 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9851 if (status) 9852 dev_err(&hdev->pdev->dev, 9853 "Send port txvlan cfg command fail, ret =%d\n", 9854 status); 9855 9856 return status; 9857} 9858 9859static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9860{ 9861 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9862 struct hclge_vport_vtag_rx_cfg_cmd *req; 9863 struct hclge_dev *hdev = vport->back; 9864 struct hclge_desc desc; 9865 u16 bmap_index; 9866 int status; 9867 9868 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9869 9870 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9871 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9872 vcfg->strip_tag1_en ? 1 : 0); 9873 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9874 vcfg->strip_tag2_en ? 1 : 0); 9875 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9876 vcfg->vlan1_vlan_prionly ? 1 : 0); 9877 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9878 vcfg->vlan2_vlan_prionly ? 1 : 0); 9879 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9880 vcfg->strip_tag1_discard_en ? 1 : 0); 9881 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9882 vcfg->strip_tag2_discard_en ? 1 : 0); 9883 9884 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9885 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9886 HCLGE_VF_NUM_PER_BYTE; 9887 req->vf_bitmap[bmap_index] = 9888 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9889 9890 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9891 if (status) 9892 dev_err(&hdev->pdev->dev, 9893 "Send port rxvlan cfg command fail, ret =%d\n", 9894 status); 9895 9896 return status; 9897} 9898 9899static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9900 u16 port_base_vlan_state, 9901 u16 vlan_tag, u8 qos) 9902{ 9903 int ret; 9904 9905 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9906 vport->txvlan_cfg.accept_tag1 = true; 9907 vport->txvlan_cfg.insert_tag1_en = false; 9908 vport->txvlan_cfg.default_tag1 = 0; 9909 } else { 9910 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9911 9912 vport->txvlan_cfg.accept_tag1 = 9913 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9914 vport->txvlan_cfg.insert_tag1_en = true; 9915 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9916 vlan_tag; 9917 } 9918 9919 vport->txvlan_cfg.accept_untag1 = true; 9920 9921 /* accept_tag2 and accept_untag2 are not supported on 9922 * pdev revision(0x20), new revision support them, 9923 * this two fields can not be configured by user. 9924 */ 9925 vport->txvlan_cfg.accept_tag2 = true; 9926 vport->txvlan_cfg.accept_untag2 = true; 9927 vport->txvlan_cfg.insert_tag2_en = false; 9928 vport->txvlan_cfg.default_tag2 = 0; 9929 vport->txvlan_cfg.tag_shift_mode_en = true; 9930 9931 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9932 vport->rxvlan_cfg.strip_tag1_en = false; 9933 vport->rxvlan_cfg.strip_tag2_en = 9934 vport->rxvlan_cfg.rx_vlan_offload_en; 9935 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9936 } else { 9937 vport->rxvlan_cfg.strip_tag1_en = 9938 vport->rxvlan_cfg.rx_vlan_offload_en; 9939 vport->rxvlan_cfg.strip_tag2_en = true; 9940 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9941 } 9942 9943 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9944 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9945 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9946 9947 ret = hclge_set_vlan_tx_offload_cfg(vport); 9948 if (ret) 9949 return ret; 9950 9951 return hclge_set_vlan_rx_offload_cfg(vport); 9952} 9953 9954static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9955{ 9956 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9957 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9958 struct hclge_desc desc; 9959 int status; 9960 9961 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9962 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9963 rx_req->ot_fst_vlan_type = 9964 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9965 rx_req->ot_sec_vlan_type = 9966 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9967 rx_req->in_fst_vlan_type = 9968 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9969 rx_req->in_sec_vlan_type = 9970 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9971 9972 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9973 if (status) { 9974 dev_err(&hdev->pdev->dev, 9975 "Send rxvlan protocol type command fail, ret =%d\n", 9976 status); 9977 return status; 9978 } 9979 9980 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9981 9982 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9983 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9984 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9985 9986 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9987 if (status) 9988 dev_err(&hdev->pdev->dev, 9989 "Send txvlan protocol type command fail, ret =%d\n", 9990 status); 9991 9992 return status; 9993} 9994 9995static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9996{ 9997 struct hclge_vport *vport; 9998 bool enable = true; 9999 int ret; 10000 int i; 10001 10002 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10003 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 10004 HCLGE_FILTER_FE_EGRESS_V1_B, 10005 true, 0); 10006 10007 /* for revision 0x21, vf vlan filter is per function */ 10008 for (i = 0; i < hdev->num_alloc_vport; i++) { 10009 vport = &hdev->vport[i]; 10010 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 10011 HCLGE_FILTER_FE_EGRESS, true, 10012 vport->vport_id); 10013 if (ret) 10014 return ret; 10015 vport->cur_vlan_fltr_en = true; 10016 } 10017 10018 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 10019 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 10020 enable = false; 10021 10022 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 10023 HCLGE_FILTER_FE_INGRESS, enable, 0); 10024} 10025 10026static int hclge_init_vlan_type(struct hclge_dev *hdev) 10027{ 10028 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 10029 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 10030 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 10031 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 10032 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 10033 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 10034 10035 return hclge_set_vlan_protocol_type(hdev); 10036} 10037 10038static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 10039{ 10040 struct hclge_port_base_vlan_config *cfg; 10041 struct hclge_vport *vport; 10042 int ret; 10043 int i; 10044 10045 for (i = 0; i < hdev->num_alloc_vport; i++) { 10046 vport = &hdev->vport[i]; 10047 cfg = &vport->port_base_vlan_cfg; 10048 10049 ret = hclge_vlan_offload_cfg(vport, cfg->state, 10050 cfg->vlan_info.vlan_tag, 10051 cfg->vlan_info.qos); 10052 if (ret) 10053 return ret; 10054 } 10055 return 0; 10056} 10057 10058static int hclge_init_vlan_config(struct hclge_dev *hdev) 10059{ 10060 struct hnae3_handle *handle = &hdev->vport[0].nic; 10061 int ret; 10062 10063 ret = hclge_init_vlan_filter(hdev); 10064 if (ret) 10065 return ret; 10066 10067 ret = hclge_init_vlan_type(hdev); 10068 if (ret) 10069 return ret; 10070 10071 ret = hclge_init_vport_vlan_offload(hdev); 10072 if (ret) 10073 return ret; 10074 10075 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 10076} 10077 10078static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10079 bool writen_to_tbl) 10080{ 10081 struct hclge_vport_vlan_cfg *vlan, *tmp; 10082 struct hclge_dev *hdev = vport->back; 10083 10084 mutex_lock(&hdev->vport_lock); 10085 10086 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10087 if (vlan->vlan_id == vlan_id) { 10088 mutex_unlock(&hdev->vport_lock); 10089 return; 10090 } 10091 } 10092 10093 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10094 if (!vlan) { 10095 mutex_unlock(&hdev->vport_lock); 10096 return; 10097 } 10098 10099 vlan->hd_tbl_status = writen_to_tbl; 10100 vlan->vlan_id = vlan_id; 10101 10102 list_add_tail(&vlan->node, &vport->vlan_list); 10103 mutex_unlock(&hdev->vport_lock); 10104} 10105 10106static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10107{ 10108 struct hclge_vport_vlan_cfg *vlan, *tmp; 10109 struct hclge_dev *hdev = vport->back; 10110 int ret; 10111 10112 mutex_lock(&hdev->vport_lock); 10113 10114 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10115 if (!vlan->hd_tbl_status) { 10116 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10117 vport->vport_id, 10118 vlan->vlan_id, false); 10119 if (ret) { 10120 dev_err(&hdev->pdev->dev, 10121 "restore vport vlan list failed, ret=%d\n", 10122 ret); 10123 10124 mutex_unlock(&hdev->vport_lock); 10125 return ret; 10126 } 10127 } 10128 vlan->hd_tbl_status = true; 10129 } 10130 10131 mutex_unlock(&hdev->vport_lock); 10132 10133 return 0; 10134} 10135 10136static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10137 bool is_write_tbl) 10138{ 10139 struct hclge_vport_vlan_cfg *vlan, *tmp; 10140 struct hclge_dev *hdev = vport->back; 10141 10142 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10143 if (vlan->vlan_id == vlan_id) { 10144 if (is_write_tbl && vlan->hd_tbl_status) 10145 hclge_set_vlan_filter_hw(hdev, 10146 htons(ETH_P_8021Q), 10147 vport->vport_id, 10148 vlan_id, 10149 true); 10150 10151 list_del(&vlan->node); 10152 kfree(vlan); 10153 break; 10154 } 10155 } 10156} 10157 10158void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10159{ 10160 struct hclge_vport_vlan_cfg *vlan, *tmp; 10161 struct hclge_dev *hdev = vport->back; 10162 10163 mutex_lock(&hdev->vport_lock); 10164 10165 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10166 if (vlan->hd_tbl_status) 10167 hclge_set_vlan_filter_hw(hdev, 10168 htons(ETH_P_8021Q), 10169 vport->vport_id, 10170 vlan->vlan_id, 10171 true); 10172 10173 vlan->hd_tbl_status = false; 10174 if (is_del_list) { 10175 list_del(&vlan->node); 10176 kfree(vlan); 10177 } 10178 } 10179 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10180 mutex_unlock(&hdev->vport_lock); 10181} 10182 10183void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10184{ 10185 struct hclge_vport_vlan_cfg *vlan, *tmp; 10186 struct hclge_vport *vport; 10187 int i; 10188 10189 mutex_lock(&hdev->vport_lock); 10190 10191 for (i = 0; i < hdev->num_alloc_vport; i++) { 10192 vport = &hdev->vport[i]; 10193 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10194 list_del(&vlan->node); 10195 kfree(vlan); 10196 } 10197 } 10198 10199 mutex_unlock(&hdev->vport_lock); 10200} 10201 10202void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10203{ 10204 struct hclge_vlan_info *vlan_info; 10205 struct hclge_vport *vport; 10206 u16 vlan_proto; 10207 u16 vlan_id; 10208 u16 state; 10209 int vf_id; 10210 int ret; 10211 10212 /* PF should restore all vfs port base vlan */ 10213 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10214 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10215 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10216 &vport->port_base_vlan_cfg.vlan_info : 10217 &vport->port_base_vlan_cfg.old_vlan_info; 10218 10219 vlan_id = vlan_info->vlan_tag; 10220 vlan_proto = vlan_info->vlan_proto; 10221 state = vport->port_base_vlan_cfg.state; 10222 10223 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10224 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10225 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10226 vport->vport_id, 10227 vlan_id, false); 10228 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10229 } 10230 } 10231} 10232 10233void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10234{ 10235 struct hclge_vport_vlan_cfg *vlan, *tmp; 10236 struct hclge_dev *hdev = vport->back; 10237 int ret; 10238 10239 mutex_lock(&hdev->vport_lock); 10240 10241 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10242 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10243 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10244 vport->vport_id, 10245 vlan->vlan_id, false); 10246 if (ret) 10247 break; 10248 vlan->hd_tbl_status = true; 10249 } 10250 } 10251 10252 mutex_unlock(&hdev->vport_lock); 10253} 10254 10255/* For global reset and imp reset, hardware will clear the mac table, 10256 * so we change the mac address state from ACTIVE to TO_ADD, then they 10257 * can be restored in the service task after reset complete. Furtherly, 10258 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10259 * be restored after reset, so just remove these mac nodes from mac_list. 10260 */ 10261static void hclge_mac_node_convert_for_reset(struct list_head *list) 10262{ 10263 struct hclge_mac_node *mac_node, *tmp; 10264 10265 list_for_each_entry_safe(mac_node, tmp, list, node) { 10266 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10267 mac_node->state = HCLGE_MAC_TO_ADD; 10268 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10269 list_del(&mac_node->node); 10270 kfree(mac_node); 10271 } 10272 } 10273} 10274 10275void hclge_restore_mac_table_common(struct hclge_vport *vport) 10276{ 10277 spin_lock_bh(&vport->mac_list_lock); 10278 10279 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10280 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10281 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10282 10283 spin_unlock_bh(&vport->mac_list_lock); 10284} 10285 10286static void hclge_restore_hw_table(struct hclge_dev *hdev) 10287{ 10288 struct hclge_vport *vport = &hdev->vport[0]; 10289 struct hnae3_handle *handle = &vport->nic; 10290 10291 hclge_restore_mac_table_common(vport); 10292 hclge_restore_vport_port_base_vlan_config(hdev); 10293 hclge_restore_vport_vlan_table(vport); 10294 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10295 hclge_restore_fd_entries(handle); 10296} 10297 10298int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10299{ 10300 struct hclge_vport *vport = hclge_get_vport(handle); 10301 10302 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10303 vport->rxvlan_cfg.strip_tag1_en = false; 10304 vport->rxvlan_cfg.strip_tag2_en = enable; 10305 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10306 } else { 10307 vport->rxvlan_cfg.strip_tag1_en = enable; 10308 vport->rxvlan_cfg.strip_tag2_en = true; 10309 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10310 } 10311 10312 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10313 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10314 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10315 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10316 10317 return hclge_set_vlan_rx_offload_cfg(vport); 10318} 10319 10320static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10321{ 10322 struct hclge_dev *hdev = vport->back; 10323 10324 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10325 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10326} 10327 10328static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10329 u16 port_base_vlan_state, 10330 struct hclge_vlan_info *new_info, 10331 struct hclge_vlan_info *old_info) 10332{ 10333 struct hclge_dev *hdev = vport->back; 10334 int ret; 10335 10336 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10337 hclge_rm_vport_all_vlan_table(vport, false); 10338 /* force clear VLAN 0 */ 10339 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10340 if (ret) 10341 return ret; 10342 return hclge_set_vlan_filter_hw(hdev, 10343 htons(new_info->vlan_proto), 10344 vport->vport_id, 10345 new_info->vlan_tag, 10346 false); 10347 } 10348 10349 vport->port_base_vlan_cfg.tbl_sta = false; 10350 10351 /* force add VLAN 0 */ 10352 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10353 if (ret) 10354 return ret; 10355 10356 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10357 vport->vport_id, old_info->vlan_tag, 10358 true); 10359 if (ret) 10360 return ret; 10361 10362 return hclge_add_vport_all_vlan_table(vport); 10363} 10364 10365static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10366 const struct hclge_vlan_info *old_cfg) 10367{ 10368 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10369 return true; 10370 10371 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10372 return true; 10373 10374 return false; 10375} 10376 10377static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10378 struct hclge_vlan_info *new_info, 10379 struct hclge_vlan_info *old_info) 10380{ 10381 struct hclge_dev *hdev = vport->back; 10382 int ret; 10383 10384 /* add new VLAN tag */ 10385 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10386 vport->vport_id, new_info->vlan_tag, 10387 false); 10388 if (ret) 10389 return ret; 10390 10391 vport->port_base_vlan_cfg.tbl_sta = false; 10392 /* remove old VLAN tag */ 10393 if (old_info->vlan_tag == 0) 10394 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10395 true, 0); 10396 else 10397 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10398 vport->vport_id, 10399 old_info->vlan_tag, true); 10400 if (ret) 10401 dev_err(&hdev->pdev->dev, 10402 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10403 vport->vport_id, old_info->vlan_tag, ret); 10404 10405 return ret; 10406} 10407 10408int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10409 struct hclge_vlan_info *vlan_info) 10410{ 10411 struct hnae3_handle *nic = &vport->nic; 10412 struct hclge_vlan_info *old_vlan_info; 10413 int ret; 10414 10415 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10416 10417 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10418 vlan_info->qos); 10419 if (ret) 10420 return ret; 10421 10422 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10423 goto out; 10424 10425 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10426 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10427 old_vlan_info); 10428 else 10429 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10430 old_vlan_info); 10431 if (ret) 10432 return ret; 10433 10434out: 10435 vport->port_base_vlan_cfg.state = state; 10436 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10437 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10438 else 10439 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10440 10441 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10442 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10443 vport->port_base_vlan_cfg.tbl_sta = true; 10444 hclge_set_vport_vlan_fltr_change(vport); 10445 10446 return 0; 10447} 10448 10449static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10450 enum hnae3_port_base_vlan_state state, 10451 u16 vlan, u8 qos) 10452{ 10453 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10454 if (!vlan && !qos) 10455 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10456 10457 return HNAE3_PORT_BASE_VLAN_ENABLE; 10458 } 10459 10460 if (!vlan && !qos) 10461 return HNAE3_PORT_BASE_VLAN_DISABLE; 10462 10463 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10464 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10465 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10466 10467 return HNAE3_PORT_BASE_VLAN_MODIFY; 10468} 10469 10470static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10471 u16 vlan, u8 qos, __be16 proto) 10472{ 10473 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10474 struct hclge_vport *vport = hclge_get_vport(handle); 10475 struct hclge_dev *hdev = vport->back; 10476 struct hclge_vlan_info vlan_info; 10477 u16 state; 10478 int ret; 10479 10480 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10481 return -EOPNOTSUPP; 10482 10483 vport = hclge_get_vf_vport(hdev, vfid); 10484 if (!vport) 10485 return -EINVAL; 10486 10487 /* qos is a 3 bits value, so can not be bigger than 7 */ 10488 if (vlan > VLAN_N_VID - 1 || qos > 7) 10489 return -EINVAL; 10490 if (proto != htons(ETH_P_8021Q)) 10491 return -EPROTONOSUPPORT; 10492 10493 state = hclge_get_port_base_vlan_state(vport, 10494 vport->port_base_vlan_cfg.state, 10495 vlan, qos); 10496 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10497 return 0; 10498 10499 vlan_info.vlan_tag = vlan; 10500 vlan_info.qos = qos; 10501 vlan_info.vlan_proto = ntohs(proto); 10502 10503 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10504 if (ret) { 10505 dev_err(&hdev->pdev->dev, 10506 "failed to update port base vlan for vf %d, ret = %d\n", 10507 vfid, ret); 10508 return ret; 10509 } 10510 10511 /* there is a timewindow for PF to know VF unalive, it may 10512 * cause send mailbox fail, but it doesn't matter, VF will 10513 * query it when reinit. 10514 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10515 * VLAN state. 10516 */ 10517 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10518 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10519 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10520 vport->vport_id, 10521 state, 10522 &vlan_info); 10523 else 10524 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10525 &vport->need_notify); 10526 } 10527 return 0; 10528} 10529 10530static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10531{ 10532 struct hclge_vlan_info *vlan_info; 10533 struct hclge_vport *vport; 10534 int ret; 10535 int vf; 10536 10537 /* clear port base vlan for all vf */ 10538 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10539 vport = &hdev->vport[vf]; 10540 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10541 10542 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10543 vport->vport_id, 10544 vlan_info->vlan_tag, true); 10545 if (ret) 10546 dev_err(&hdev->pdev->dev, 10547 "failed to clear vf vlan for vf%d, ret = %d\n", 10548 vf - HCLGE_VF_VPORT_START_NUM, ret); 10549 } 10550} 10551 10552int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10553 u16 vlan_id, bool is_kill) 10554{ 10555 struct hclge_vport *vport = hclge_get_vport(handle); 10556 struct hclge_dev *hdev = vport->back; 10557 bool writen_to_tbl = false; 10558 int ret = 0; 10559 10560 if (vlan_id >= VLAN_N_VID) 10561 return -EINVAL; 10562 10563 /* When device is resetting or reset failed, firmware is unable to 10564 * handle mailbox. Just record the vlan id, and remove it after 10565 * reset finished. 10566 */ 10567 mutex_lock(&hdev->vport_lock); 10568 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10569 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10570 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10571 mutex_unlock(&hdev->vport_lock); 10572 return -EBUSY; 10573 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 10574 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10575 } 10576 mutex_unlock(&hdev->vport_lock); 10577 10578 /* when port base vlan enabled, we use port base vlan as the vlan 10579 * filter entry. In this case, we don't update vlan filter table 10580 * when user add new vlan or remove exist vlan, just update the vport 10581 * vlan list. The vlan id in vlan list will be writen in vlan filter 10582 * table until port base vlan disabled 10583 */ 10584 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10585 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10586 vlan_id, is_kill); 10587 writen_to_tbl = true; 10588 } 10589 10590 if (!ret) { 10591 if (!is_kill) { 10592 hclge_add_vport_vlan_table(vport, vlan_id, 10593 writen_to_tbl); 10594 } else if (is_kill && vlan_id != 0) { 10595 mutex_lock(&hdev->vport_lock); 10596 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10597 mutex_unlock(&hdev->vport_lock); 10598 } 10599 } else if (is_kill) { 10600 /* when remove hw vlan filter failed, record the vlan id, 10601 * and try to remove it from hw later, to be consistence 10602 * with stack 10603 */ 10604 mutex_lock(&hdev->vport_lock); 10605 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10606 mutex_unlock(&hdev->vport_lock); 10607 } 10608 10609 hclge_set_vport_vlan_fltr_change(vport); 10610 10611 return ret; 10612} 10613 10614static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10615{ 10616 struct hclge_vport *vport; 10617 int ret; 10618 u16 i; 10619 10620 for (i = 0; i < hdev->num_alloc_vport; i++) { 10621 vport = &hdev->vport[i]; 10622 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10623 &vport->state)) 10624 continue; 10625 10626 mutex_lock(&hdev->vport_lock); 10627 ret = __hclge_enable_vport_vlan_filter(vport, 10628 vport->req_vlan_fltr_en); 10629 if (ret) { 10630 dev_err(&hdev->pdev->dev, 10631 "failed to sync vlan filter state for vport%u, ret = %d\n", 10632 vport->vport_id, ret); 10633 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10634 &vport->state); 10635 mutex_unlock(&hdev->vport_lock); 10636 return; 10637 } 10638 mutex_unlock(&hdev->vport_lock); 10639 } 10640} 10641 10642static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10643{ 10644#define HCLGE_MAX_SYNC_COUNT 60 10645 10646 int i, ret, sync_cnt = 0; 10647 u16 vlan_id; 10648 10649 mutex_lock(&hdev->vport_lock); 10650 /* start from vport 1 for PF is always alive */ 10651 for (i = 0; i < hdev->num_alloc_vport; i++) { 10652 struct hclge_vport *vport = &hdev->vport[i]; 10653 10654 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10655 VLAN_N_VID); 10656 while (vlan_id != VLAN_N_VID) { 10657 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10658 vport->vport_id, vlan_id, 10659 true); 10660 if (ret && ret != -EINVAL) { 10661 mutex_unlock(&hdev->vport_lock); 10662 return; 10663 } 10664 10665 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10666 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10667 hclge_set_vport_vlan_fltr_change(vport); 10668 10669 sync_cnt++; 10670 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 10671 mutex_unlock(&hdev->vport_lock); 10672 return; 10673 } 10674 10675 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10676 VLAN_N_VID); 10677 } 10678 } 10679 mutex_unlock(&hdev->vport_lock); 10680 10681 hclge_sync_vlan_fltr_state(hdev); 10682} 10683 10684static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10685{ 10686 struct hclge_config_max_frm_size_cmd *req; 10687 struct hclge_desc desc; 10688 10689 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10690 10691 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10692 req->max_frm_size = cpu_to_le16(new_mps); 10693 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10694 10695 return hclge_cmd_send(&hdev->hw, &desc, 1); 10696} 10697 10698static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10699{ 10700 struct hclge_vport *vport = hclge_get_vport(handle); 10701 10702 return hclge_set_vport_mtu(vport, new_mtu); 10703} 10704 10705int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10706{ 10707 struct hclge_dev *hdev = vport->back; 10708 int i, max_frm_size, ret; 10709 10710 /* HW supprt 2 layer vlan */ 10711 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10712 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10713 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10714 return -EINVAL; 10715 10716 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10717 mutex_lock(&hdev->vport_lock); 10718 /* VF's mps must fit within hdev->mps */ 10719 if (vport->vport_id && (u32)max_frm_size > hdev->mps) { 10720 mutex_unlock(&hdev->vport_lock); 10721 return -EINVAL; 10722 } else if (vport->vport_id) { 10723 vport->mps = max_frm_size; 10724 mutex_unlock(&hdev->vport_lock); 10725 return 0; 10726 } 10727 10728 /* PF's mps must be greater then VF's mps */ 10729 for (i = 1; i < hdev->num_alloc_vport; i++) 10730 if ((u32)max_frm_size < hdev->vport[i].mps) { 10731 dev_err(&hdev->pdev->dev, 10732 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10733 i, hdev->vport[i].mps); 10734 mutex_unlock(&hdev->vport_lock); 10735 return -EINVAL; 10736 } 10737 10738 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10739 10740 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10741 if (ret) { 10742 dev_err(&hdev->pdev->dev, 10743 "Change mtu fail, ret =%d\n", ret); 10744 goto out; 10745 } 10746 10747 hdev->mps = max_frm_size; 10748 vport->mps = max_frm_size; 10749 10750 ret = hclge_buffer_alloc(hdev); 10751 if (ret) 10752 dev_err(&hdev->pdev->dev, 10753 "Allocate buffer fail, ret =%d\n", ret); 10754 10755out: 10756 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10757 mutex_unlock(&hdev->vport_lock); 10758 return ret; 10759} 10760 10761static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10762 bool enable) 10763{ 10764 struct hclge_reset_tqp_queue_cmd *req; 10765 struct hclge_desc desc; 10766 int ret; 10767 10768 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10769 10770 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10771 req->tqp_id = cpu_to_le16(queue_id); 10772 if (enable) 10773 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10774 10775 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10776 if (ret) { 10777 dev_err(&hdev->pdev->dev, 10778 "Send tqp reset cmd error, status =%d\n", ret); 10779 return ret; 10780 } 10781 10782 return 0; 10783} 10784 10785static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10786 u8 *reset_status) 10787{ 10788 struct hclge_reset_tqp_queue_cmd *req; 10789 struct hclge_desc desc; 10790 int ret; 10791 10792 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10793 10794 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10795 req->tqp_id = cpu_to_le16(queue_id); 10796 10797 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10798 if (ret) { 10799 dev_err(&hdev->pdev->dev, 10800 "Get reset status error, status =%d\n", ret); 10801 return ret; 10802 } 10803 10804 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10805 10806 return 0; 10807} 10808 10809u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10810{ 10811 struct hclge_comm_tqp *tqp; 10812 struct hnae3_queue *queue; 10813 10814 queue = handle->kinfo.tqp[queue_id]; 10815 tqp = container_of(queue, struct hclge_comm_tqp, q); 10816 10817 return tqp->index; 10818} 10819 10820static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10821{ 10822 struct hclge_vport *vport = hclge_get_vport(handle); 10823 struct hclge_dev *hdev = vport->back; 10824 u16 reset_try_times = 0; 10825 u8 reset_status; 10826 u16 queue_gid; 10827 int ret; 10828 u16 i; 10829 10830 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10831 queue_gid = hclge_covert_handle_qid_global(handle, i); 10832 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10833 if (ret) { 10834 dev_err(&hdev->pdev->dev, 10835 "failed to send reset tqp cmd, ret = %d\n", 10836 ret); 10837 return ret; 10838 } 10839 10840 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10841 ret = hclge_get_reset_status(hdev, queue_gid, 10842 &reset_status); 10843 if (ret) 10844 return ret; 10845 10846 if (reset_status) 10847 break; 10848 10849 /* Wait for tqp hw reset */ 10850 usleep_range(1000, 1200); 10851 } 10852 10853 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10854 dev_err(&hdev->pdev->dev, 10855 "wait for tqp hw reset timeout\n"); 10856 return -ETIME; 10857 } 10858 10859 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10860 if (ret) { 10861 dev_err(&hdev->pdev->dev, 10862 "failed to deassert soft reset, ret = %d\n", 10863 ret); 10864 return ret; 10865 } 10866 reset_try_times = 0; 10867 } 10868 return 0; 10869} 10870 10871static int hclge_reset_rcb(struct hnae3_handle *handle) 10872{ 10873#define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10874#define HCLGE_RESET_RCB_SUCCESS 1U 10875 10876 struct hclge_vport *vport = hclge_get_vport(handle); 10877 struct hclge_dev *hdev = vport->back; 10878 struct hclge_reset_cmd *req; 10879 struct hclge_desc desc; 10880 u8 return_status; 10881 u16 queue_gid; 10882 int ret; 10883 10884 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10885 10886 req = (struct hclge_reset_cmd *)desc.data; 10887 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10888 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10889 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10890 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10891 10892 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10893 if (ret) { 10894 dev_err(&hdev->pdev->dev, 10895 "failed to send rcb reset cmd, ret = %d\n", ret); 10896 return ret; 10897 } 10898 10899 return_status = req->fun_reset_rcb_return_status; 10900 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10901 return 0; 10902 10903 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10904 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10905 return_status); 10906 return -EIO; 10907 } 10908 10909 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10910 * again to reset all tqps 10911 */ 10912 return hclge_reset_tqp_cmd(handle); 10913} 10914 10915int hclge_reset_tqp(struct hnae3_handle *handle) 10916{ 10917 struct hclge_vport *vport = hclge_get_vport(handle); 10918 struct hclge_dev *hdev = vport->back; 10919 int ret; 10920 10921 /* only need to disable PF's tqp */ 10922 if (!vport->vport_id) { 10923 ret = hclge_tqp_enable(handle, false); 10924 if (ret) { 10925 dev_err(&hdev->pdev->dev, 10926 "failed to disable tqp, ret = %d\n", ret); 10927 return ret; 10928 } 10929 } 10930 10931 return hclge_reset_rcb(handle); 10932} 10933 10934static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10935{ 10936 struct hclge_vport *vport = hclge_get_vport(handle); 10937 struct hclge_dev *hdev = vport->back; 10938 10939 return hdev->fw_version; 10940} 10941 10942int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version) 10943{ 10944 struct hclge_comm_query_scc_cmd *resp; 10945 struct hclge_desc desc; 10946 int ret; 10947 10948 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_SCC_VER, 1); 10949 resp = (struct hclge_comm_query_scc_cmd *)desc.data; 10950 10951 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10952 if (ret) 10953 return ret; 10954 10955 *scc_version = le32_to_cpu(resp->scc_version); 10956 10957 return 0; 10958} 10959 10960static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10961{ 10962 struct phy_device *phydev = hdev->hw.mac.phydev; 10963 10964 if (!phydev) 10965 return; 10966 10967 phy_set_asym_pause(phydev, rx_en, tx_en); 10968} 10969 10970static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10971{ 10972 int ret; 10973 10974 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10975 return 0; 10976 10977 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10978 if (ret) 10979 dev_err(&hdev->pdev->dev, 10980 "configure pauseparam error, ret = %d.\n", ret); 10981 10982 return ret; 10983} 10984 10985int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10986{ 10987 struct phy_device *phydev = hdev->hw.mac.phydev; 10988 u16 remote_advertising = 0; 10989 u16 local_advertising; 10990 u32 rx_pause, tx_pause; 10991 u8 flowctl; 10992 10993 if (!phydev->link) 10994 return 0; 10995 10996 if (!phydev->autoneg) 10997 return hclge_mac_pause_setup_hw(hdev); 10998 10999 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 11000 11001 if (phydev->pause) 11002 remote_advertising = LPA_PAUSE_CAP; 11003 11004 if (phydev->asym_pause) 11005 remote_advertising |= LPA_PAUSE_ASYM; 11006 11007 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 11008 remote_advertising); 11009 tx_pause = flowctl & FLOW_CTRL_TX; 11010 rx_pause = flowctl & FLOW_CTRL_RX; 11011 11012 if (phydev->duplex == HCLGE_MAC_HALF) { 11013 tx_pause = 0; 11014 rx_pause = 0; 11015 } 11016 11017 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 11018} 11019 11020static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 11021 u32 *rx_en, u32 *tx_en) 11022{ 11023 struct hclge_vport *vport = hclge_get_vport(handle); 11024 struct hclge_dev *hdev = vport->back; 11025 u8 media_type = hdev->hw.mac.media_type; 11026 11027 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 11028 hclge_get_autoneg(handle) : 0; 11029 11030 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11031 *rx_en = 0; 11032 *tx_en = 0; 11033 return; 11034 } 11035 11036 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 11037 *rx_en = 1; 11038 *tx_en = 0; 11039 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 11040 *tx_en = 1; 11041 *rx_en = 0; 11042 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 11043 *rx_en = 1; 11044 *tx_en = 1; 11045 } else { 11046 *rx_en = 0; 11047 *tx_en = 0; 11048 } 11049} 11050 11051static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 11052 u32 rx_en, u32 tx_en) 11053{ 11054 if (rx_en && tx_en) 11055 hdev->fc_mode_last_time = HCLGE_FC_FULL; 11056 else if (rx_en && !tx_en) 11057 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 11058 else if (!rx_en && tx_en) 11059 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 11060 else 11061 hdev->fc_mode_last_time = HCLGE_FC_NONE; 11062 11063 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 11064} 11065 11066static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 11067 u32 rx_en, u32 tx_en) 11068{ 11069 struct hclge_vport *vport = hclge_get_vport(handle); 11070 struct hclge_dev *hdev = vport->back; 11071 struct phy_device *phydev = hdev->hw.mac.phydev; 11072 u32 fc_autoneg; 11073 11074 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 11075 fc_autoneg = hclge_get_autoneg(handle); 11076 if (auto_neg != fc_autoneg) { 11077 dev_info(&hdev->pdev->dev, 11078 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 11079 return -EOPNOTSUPP; 11080 } 11081 } 11082 11083 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11084 dev_info(&hdev->pdev->dev, 11085 "Priority flow control enabled. Cannot set link flow control.\n"); 11086 return -EOPNOTSUPP; 11087 } 11088 11089 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 11090 11091 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 11092 11093 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 11094 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 11095 11096 if (phydev) 11097 return phy_start_aneg(phydev); 11098 11099 return -EOPNOTSUPP; 11100} 11101 11102static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 11103 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 11104{ 11105 struct hclge_vport *vport = hclge_get_vport(handle); 11106 struct hclge_dev *hdev = vport->back; 11107 11108 if (speed) 11109 *speed = hdev->hw.mac.speed; 11110 if (duplex) 11111 *duplex = hdev->hw.mac.duplex; 11112 if (auto_neg) 11113 *auto_neg = hdev->hw.mac.autoneg; 11114 if (lane_num) 11115 *lane_num = hdev->hw.mac.lane_num; 11116} 11117 11118static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11119 u8 *module_type) 11120{ 11121 struct hclge_vport *vport = hclge_get_vport(handle); 11122 struct hclge_dev *hdev = vport->back; 11123 11124 /* When nic is down, the service task is not running, doesn't update 11125 * the port information per second. Query the port information before 11126 * return the media type, ensure getting the correct media information. 11127 */ 11128 hclge_update_port_info(hdev); 11129 11130 if (media_type) 11131 *media_type = hdev->hw.mac.media_type; 11132 11133 if (module_type) 11134 *module_type = hdev->hw.mac.module_type; 11135} 11136 11137static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11138 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11139{ 11140 struct hclge_vport *vport = hclge_get_vport(handle); 11141 struct hclge_dev *hdev = vport->back; 11142 struct phy_device *phydev = hdev->hw.mac.phydev; 11143 int mdix_ctrl, mdix, is_resolved; 11144 unsigned int retval; 11145 11146 if (!phydev) { 11147 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11148 *tp_mdix = ETH_TP_MDI_INVALID; 11149 return; 11150 } 11151 11152 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11153 11154 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11155 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11156 HCLGE_PHY_MDIX_CTRL_S); 11157 11158 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11159 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11160 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11161 11162 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11163 11164 switch (mdix_ctrl) { 11165 case 0x0: 11166 *tp_mdix_ctrl = ETH_TP_MDI; 11167 break; 11168 case 0x1: 11169 *tp_mdix_ctrl = ETH_TP_MDI_X; 11170 break; 11171 case 0x3: 11172 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11173 break; 11174 default: 11175 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11176 break; 11177 } 11178 11179 if (!is_resolved) 11180 *tp_mdix = ETH_TP_MDI_INVALID; 11181 else if (mdix) 11182 *tp_mdix = ETH_TP_MDI_X; 11183 else 11184 *tp_mdix = ETH_TP_MDI; 11185} 11186 11187static void hclge_info_show(struct hclge_dev *hdev) 11188{ 11189 struct hnae3_handle *handle = &hdev->vport->nic; 11190 struct device *dev = &hdev->pdev->dev; 11191 11192 dev_info(dev, "PF info begin:\n"); 11193 11194 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11195 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11196 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11197 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11198 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11199 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11200 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11201 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11202 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11203 dev_info(dev, "This is %s PF\n", 11204 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11205 dev_info(dev, "DCB %s\n", 11206 str_enable_disable(handle->kinfo.tc_info.dcb_ets_active)); 11207 dev_info(dev, "MQPRIO %s\n", 11208 str_enable_disable(handle->kinfo.tc_info.mqprio_active)); 11209 dev_info(dev, "Default tx spare buffer size: %u\n", 11210 hdev->tx_spare_buf_size); 11211 11212 dev_info(dev, "PF info end.\n"); 11213} 11214 11215static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11216 struct hclge_vport *vport) 11217{ 11218 struct hnae3_client *client = vport->nic.client; 11219 struct hclge_dev *hdev = ae_dev->priv; 11220 u32 rst_cnt = hdev->rst_stats.reset_cnt; 11221 int ret; 11222 11223 ret = client->ops->init_instance(&vport->nic); 11224 if (ret) 11225 return ret; 11226 11227 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11228 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11229 rst_cnt != hdev->rst_stats.reset_cnt) { 11230 ret = -EBUSY; 11231 goto init_nic_err; 11232 } 11233 11234 /* Enable nic hw error interrupts */ 11235 ret = hclge_config_nic_hw_error(hdev, true); 11236 if (ret) { 11237 dev_err(&ae_dev->pdev->dev, 11238 "fail(%d) to enable hw error interrupts\n", ret); 11239 goto init_nic_err; 11240 } 11241 11242 hnae3_set_client_init_flag(client, ae_dev, 1); 11243 11244 if (netif_msg_drv(&hdev->vport->nic)) 11245 hclge_info_show(hdev); 11246 11247 return ret; 11248 11249init_nic_err: 11250 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11251 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11252 msleep(HCLGE_WAIT_RESET_DONE); 11253 11254 client->ops->uninit_instance(&vport->nic, 0); 11255 11256 return ret; 11257} 11258 11259static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11260 struct hclge_vport *vport) 11261{ 11262 struct hclge_dev *hdev = ae_dev->priv; 11263 struct hnae3_client *client; 11264 u32 rst_cnt; 11265 int ret; 11266 11267 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11268 !hdev->nic_client) 11269 return 0; 11270 11271 client = hdev->roce_client; 11272 ret = hclge_init_roce_base_info(vport); 11273 if (ret) 11274 return ret; 11275 11276 rst_cnt = hdev->rst_stats.reset_cnt; 11277 ret = client->ops->init_instance(&vport->roce); 11278 if (ret) 11279 return ret; 11280 11281 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11282 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11283 rst_cnt != hdev->rst_stats.reset_cnt) { 11284 ret = -EBUSY; 11285 goto init_roce_err; 11286 } 11287 11288 /* Enable roce ras interrupts */ 11289 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11290 if (ret) { 11291 dev_err(&ae_dev->pdev->dev, 11292 "fail(%d) to enable roce ras interrupts\n", ret); 11293 goto init_roce_err; 11294 } 11295 11296 hnae3_set_client_init_flag(client, ae_dev, 1); 11297 11298 return 0; 11299 11300init_roce_err: 11301 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11302 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11303 msleep(HCLGE_WAIT_RESET_DONE); 11304 11305 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11306 11307 return ret; 11308} 11309 11310static int hclge_init_client_instance(struct hnae3_client *client, 11311 struct hnae3_ae_dev *ae_dev) 11312{ 11313 struct hclge_dev *hdev = ae_dev->priv; 11314 struct hclge_vport *vport = &hdev->vport[0]; 11315 int ret; 11316 11317 switch (client->type) { 11318 case HNAE3_CLIENT_KNIC: 11319 hdev->nic_client = client; 11320 vport->nic.client = client; 11321 ret = hclge_init_nic_client_instance(ae_dev, vport); 11322 if (ret) 11323 goto clear_nic; 11324 11325 ret = hclge_init_roce_client_instance(ae_dev, vport); 11326 if (ret) 11327 goto clear_roce; 11328 11329 break; 11330 case HNAE3_CLIENT_ROCE: 11331 if (hnae3_dev_roce_supported(hdev)) { 11332 hdev->roce_client = client; 11333 vport->roce.client = client; 11334 } 11335 11336 ret = hclge_init_roce_client_instance(ae_dev, vport); 11337 if (ret) 11338 goto clear_roce; 11339 11340 break; 11341 default: 11342 return -EINVAL; 11343 } 11344 11345 return 0; 11346 11347clear_nic: 11348 hdev->nic_client = NULL; 11349 vport->nic.client = NULL; 11350 return ret; 11351clear_roce: 11352 hdev->roce_client = NULL; 11353 vport->roce.client = NULL; 11354 return ret; 11355} 11356 11357static bool hclge_uninit_need_wait(struct hclge_dev *hdev) 11358{ 11359 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11360 test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 11361} 11362 11363static void hclge_uninit_client_instance(struct hnae3_client *client, 11364 struct hnae3_ae_dev *ae_dev) 11365{ 11366 struct hclge_dev *hdev = ae_dev->priv; 11367 struct hclge_vport *vport = &hdev->vport[0]; 11368 11369 if (hdev->roce_client) { 11370 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11371 while (hclge_uninit_need_wait(hdev)) 11372 msleep(HCLGE_WAIT_RESET_DONE); 11373 11374 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11375 hdev->roce_client = NULL; 11376 vport->roce.client = NULL; 11377 } 11378 if (client->type == HNAE3_CLIENT_ROCE) 11379 return; 11380 if (hdev->nic_client && client->ops->uninit_instance) { 11381 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11382 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11383 msleep(HCLGE_WAIT_RESET_DONE); 11384 11385 client->ops->uninit_instance(&vport->nic, 0); 11386 hdev->nic_client = NULL; 11387 vport->nic.client = NULL; 11388 } 11389} 11390 11391static int hclge_dev_mem_map(struct hclge_dev *hdev) 11392{ 11393 struct pci_dev *pdev = hdev->pdev; 11394 struct hclge_hw *hw = &hdev->hw; 11395 11396 /* for device does not have device memory, return directly */ 11397 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11398 return 0; 11399 11400 hw->hw.mem_base = 11401 devm_ioremap_wc(&pdev->dev, 11402 pci_resource_start(pdev, HCLGE_MEM_BAR), 11403 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11404 if (!hw->hw.mem_base) { 11405 dev_err(&pdev->dev, "failed to map device memory\n"); 11406 return -EFAULT; 11407 } 11408 11409 return 0; 11410} 11411 11412static int hclge_pci_init(struct hclge_dev *hdev) 11413{ 11414 struct pci_dev *pdev = hdev->pdev; 11415 struct hclge_hw *hw; 11416 int ret; 11417 11418 ret = pci_enable_device(pdev); 11419 if (ret) { 11420 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11421 return ret; 11422 } 11423 11424 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11425 if (ret) { 11426 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11427 if (ret) { 11428 dev_err(&pdev->dev, 11429 "can't set consistent PCI DMA\n"); 11430 goto err_disable_device; 11431 } 11432 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11433 } 11434 11435 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11436 if (ret) { 11437 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11438 goto err_disable_device; 11439 } 11440 11441 pci_set_master(pdev); 11442 hw = &hdev->hw; 11443 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11444 if (!hw->hw.io_base) { 11445 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11446 ret = -ENOMEM; 11447 goto err_release_regions; 11448 } 11449 11450 ret = hclge_dev_mem_map(hdev); 11451 if (ret) 11452 goto err_unmap_io_base; 11453 11454 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11455 11456 return 0; 11457 11458err_unmap_io_base: 11459 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11460err_release_regions: 11461 pci_release_regions(pdev); 11462err_disable_device: 11463 pci_disable_device(pdev); 11464 11465 return ret; 11466} 11467 11468static void hclge_pci_uninit(struct hclge_dev *hdev) 11469{ 11470 struct pci_dev *pdev = hdev->pdev; 11471 11472 if (hdev->hw.hw.mem_base) 11473 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11474 11475 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11476 pci_free_irq_vectors(pdev); 11477 pci_release_regions(pdev); 11478 pci_disable_device(pdev); 11479} 11480 11481static void hclge_state_init(struct hclge_dev *hdev) 11482{ 11483 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11484 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11485 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11486 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11487 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11488 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11489 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11490} 11491 11492static void hclge_state_uninit(struct hclge_dev *hdev) 11493{ 11494 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11495 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11496 11497 if (hdev->reset_timer.function) 11498 timer_delete_sync(&hdev->reset_timer); 11499 if (hdev->service_task.work.func) 11500 cancel_delayed_work_sync(&hdev->service_task); 11501} 11502 11503static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11504 enum hnae3_reset_type rst_type) 11505{ 11506#define HCLGE_RESET_RETRY_WAIT_MS 500 11507#define HCLGE_RESET_RETRY_CNT 5 11508 11509 struct hclge_dev *hdev = ae_dev->priv; 11510 int retry_cnt = 0; 11511 int ret; 11512 11513 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11514 down(&hdev->reset_sem); 11515 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11516 hdev->reset_type = rst_type; 11517 ret = hclge_reset_prepare(hdev); 11518 if (!ret && !hdev->reset_pending) 11519 break; 11520 11521 dev_err(&hdev->pdev->dev, 11522 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11523 ret, hdev->reset_pending, retry_cnt); 11524 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11525 up(&hdev->reset_sem); 11526 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11527 } 11528 11529 /* disable misc vector before reset done */ 11530 hclge_enable_vector(&hdev->misc_vector, false); 11531 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11532 11533 if (hdev->reset_type == HNAE3_FLR_RESET) 11534 hdev->rst_stats.flr_rst_cnt++; 11535} 11536 11537static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11538{ 11539 struct hclge_dev *hdev = ae_dev->priv; 11540 int ret; 11541 11542 hclge_enable_vector(&hdev->misc_vector, true); 11543 11544 ret = hclge_reset_rebuild(hdev); 11545 if (ret) 11546 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11547 11548 hdev->reset_type = HNAE3_NONE_RESET; 11549 if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11550 up(&hdev->reset_sem); 11551} 11552 11553static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11554{ 11555 u16 i; 11556 11557 for (i = 0; i < hdev->num_alloc_vport; i++) { 11558 struct hclge_vport *vport = &hdev->vport[i]; 11559 int ret; 11560 11561 /* Send cmd to clear vport's FUNC_RST_ING */ 11562 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11563 if (ret) 11564 dev_warn(&hdev->pdev->dev, 11565 "clear vport(%u) rst failed %d!\n", 11566 vport->vport_id, ret); 11567 } 11568} 11569 11570static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11571{ 11572 struct hclge_desc desc; 11573 int ret; 11574 11575 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11576 11577 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11578 /* This new command is only supported by new firmware, it will 11579 * fail with older firmware. Error value -EOPNOSUPP can only be 11580 * returned by older firmware running this command, to keep code 11581 * backward compatible we will override this value and return 11582 * success. 11583 */ 11584 if (ret && ret != -EOPNOTSUPP) { 11585 dev_err(&hdev->pdev->dev, 11586 "failed to clear hw resource, ret = %d\n", ret); 11587 return ret; 11588 } 11589 return 0; 11590} 11591 11592static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11593{ 11594 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11595 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11596} 11597 11598static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11599{ 11600 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11601 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11602} 11603 11604static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11605{ 11606 struct hclge_vport *vport = hclge_get_vport(handle); 11607 11608 return &vport->back->hw.mac.wol; 11609} 11610 11611static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11612 u32 *wol_supported) 11613{ 11614 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11615 struct hclge_desc desc; 11616 int ret; 11617 11618 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11619 true); 11620 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11621 11622 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11623 if (ret) { 11624 dev_err(&hdev->pdev->dev, 11625 "failed to query wol supported, ret = %d\n", ret); 11626 return ret; 11627 } 11628 11629 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11630 11631 return 0; 11632} 11633 11634static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11635 struct hclge_wol_info *wol_info) 11636{ 11637 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11638 struct hclge_desc desc; 11639 int ret; 11640 11641 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11642 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11643 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11644 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11645 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11646 11647 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11648 if (ret) 11649 dev_err(&hdev->pdev->dev, 11650 "failed to set wol config, ret = %d\n", ret); 11651 11652 return ret; 11653} 11654 11655static int hclge_update_wol(struct hclge_dev *hdev) 11656{ 11657 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11658 11659 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11660 return 0; 11661 11662 return hclge_set_wol_cfg(hdev, wol_info); 11663} 11664 11665static int hclge_init_wol(struct hclge_dev *hdev) 11666{ 11667 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11668 int ret; 11669 11670 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11671 return 0; 11672 11673 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11674 ret = hclge_get_wol_supported_mode(hdev, 11675 &wol_info->wol_support_mode); 11676 if (ret) { 11677 wol_info->wol_support_mode = 0; 11678 return ret; 11679 } 11680 11681 return hclge_update_wol(hdev); 11682} 11683 11684static void hclge_get_wol(struct hnae3_handle *handle, 11685 struct ethtool_wolinfo *wol) 11686{ 11687 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11688 11689 wol->supported = wol_info->wol_support_mode; 11690 wol->wolopts = wol_info->wol_current_mode; 11691 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11692 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11693} 11694 11695static int hclge_set_wol(struct hnae3_handle *handle, 11696 struct ethtool_wolinfo *wol) 11697{ 11698 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11699 struct hclge_vport *vport = hclge_get_vport(handle); 11700 u32 wol_mode; 11701 int ret; 11702 11703 wol_mode = wol->wolopts; 11704 if (wol_mode & ~wol_info->wol_support_mode) 11705 return -EINVAL; 11706 11707 wol_info->wol_current_mode = wol_mode; 11708 if (wol_mode & WAKE_MAGICSECURE) { 11709 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11710 wol_info->wol_sopass_size = SOPASS_MAX; 11711 } else { 11712 wol_info->wol_sopass_size = 0; 11713 } 11714 11715 ret = hclge_set_wol_cfg(vport->back, wol_info); 11716 if (ret) 11717 wol_info->wol_current_mode = 0; 11718 11719 return ret; 11720} 11721 11722static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11723{ 11724 struct pci_dev *pdev = ae_dev->pdev; 11725 struct hclge_dev *hdev; 11726 int ret; 11727 11728 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11729 if (!hdev) 11730 return -ENOMEM; 11731 11732 hdev->pdev = pdev; 11733 hdev->ae_dev = ae_dev; 11734 hdev->reset_type = HNAE3_NONE_RESET; 11735 hdev->reset_level = HNAE3_FUNC_RESET; 11736 ae_dev->priv = hdev; 11737 11738 /* HW supprt 2 layer vlan */ 11739 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11740 11741 mutex_init(&hdev->vport_lock); 11742 spin_lock_init(&hdev->fd_rule_lock); 11743 sema_init(&hdev->reset_sem, 1); 11744 11745 ret = hclge_pci_init(hdev); 11746 if (ret) 11747 goto out; 11748 11749 /* Firmware command queue initialize */ 11750 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11751 if (ret) 11752 goto err_pci_uninit; 11753 11754 /* Firmware command initialize */ 11755 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops); 11756 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11757 true, hdev->reset_pending); 11758 if (ret) 11759 goto err_cmd_uninit; 11760 11761 ret = hclge_clear_hw_resource(hdev); 11762 if (ret) 11763 goto err_cmd_uninit; 11764 11765 ret = hclge_get_cap(hdev); 11766 if (ret) 11767 goto err_cmd_uninit; 11768 11769 ret = hclge_query_dev_specs(hdev); 11770 if (ret) { 11771 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11772 ret); 11773 goto err_cmd_uninit; 11774 } 11775 11776 ret = hclge_configure(hdev); 11777 if (ret) { 11778 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11779 goto err_cmd_uninit; 11780 } 11781 11782 ret = hclge_init_msi(hdev); 11783 if (ret) { 11784 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11785 goto err_cmd_uninit; 11786 } 11787 11788 ret = hclge_misc_irq_init(hdev); 11789 if (ret) 11790 goto err_msi_uninit; 11791 11792 ret = hclge_alloc_tqps(hdev); 11793 if (ret) { 11794 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11795 goto err_msi_irq_uninit; 11796 } 11797 11798 ret = hclge_alloc_vport(hdev); 11799 if (ret) 11800 goto err_msi_irq_uninit; 11801 11802 ret = hclge_map_tqp(hdev); 11803 if (ret) 11804 goto err_msi_irq_uninit; 11805 11806 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11807 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 11808 if (hnae3_dev_phy_imp_supported(hdev)) 11809 ret = hclge_update_tp_port_info(hdev); 11810 else 11811 ret = hclge_mac_mdio_config(hdev); 11812 11813 if (ret) 11814 goto err_msi_irq_uninit; 11815 } 11816 11817 ret = hclge_init_umv_space(hdev); 11818 if (ret) 11819 goto err_mdiobus_unreg; 11820 11821 ret = hclge_mac_init(hdev); 11822 if (ret) { 11823 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11824 goto err_mdiobus_unreg; 11825 } 11826 11827 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11828 if (ret) { 11829 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11830 goto err_mdiobus_unreg; 11831 } 11832 11833 ret = hclge_config_gro(hdev); 11834 if (ret) 11835 goto err_mdiobus_unreg; 11836 11837 ret = hclge_init_vlan_config(hdev); 11838 if (ret) { 11839 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11840 goto err_mdiobus_unreg; 11841 } 11842 11843 ret = hclge_tm_schd_init(hdev); 11844 if (ret) { 11845 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11846 goto err_mdiobus_unreg; 11847 } 11848 11849 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11850 &hdev->rss_cfg); 11851 if (ret) { 11852 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11853 goto err_mdiobus_unreg; 11854 } 11855 11856 ret = hclge_rss_init_hw(hdev); 11857 if (ret) { 11858 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11859 goto err_mdiobus_unreg; 11860 } 11861 11862 ret = init_mgr_tbl(hdev); 11863 if (ret) { 11864 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11865 goto err_mdiobus_unreg; 11866 } 11867 11868 ret = hclge_init_fd_config(hdev); 11869 if (ret) { 11870 dev_err(&pdev->dev, 11871 "fd table init fail, ret=%d\n", ret); 11872 goto err_mdiobus_unreg; 11873 } 11874 11875 ret = hclge_ptp_init(hdev); 11876 if (ret) 11877 goto err_mdiobus_unreg; 11878 11879 ret = hclge_update_port_info(hdev); 11880 if (ret) 11881 goto err_ptp_uninit; 11882 11883 INIT_KFIFO(hdev->mac_tnl_log); 11884 11885 hclge_dcb_ops_set(hdev); 11886 11887 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11888 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11889 11890 hclge_clear_all_event_cause(hdev); 11891 hclge_clear_resetting_state(hdev); 11892 11893 /* Log and clear the hw errors those already occurred */ 11894 if (hnae3_dev_ras_imp_supported(hdev)) 11895 hclge_handle_occurred_error(hdev); 11896 else 11897 hclge_handle_all_hns_hw_errors(ae_dev); 11898 11899 /* request delayed reset for the error recovery because an immediate 11900 * global reset on a PF affecting pending initialization of other PFs 11901 */ 11902 if (ae_dev->hw_err_reset_req) { 11903 enum hnae3_reset_type reset_level; 11904 11905 reset_level = hclge_get_reset_level(ae_dev, 11906 &ae_dev->hw_err_reset_req); 11907 hclge_set_def_reset_request(ae_dev, reset_level); 11908 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11909 } 11910 11911 hclge_init_rxd_adv_layout(hdev); 11912 11913 ret = hclge_init_wol(hdev); 11914 if (ret) 11915 dev_warn(&pdev->dev, 11916 "failed to wake on lan init, ret = %d\n", ret); 11917 11918 ret = hclge_devlink_init(hdev); 11919 if (ret) 11920 goto err_ptp_uninit; 11921 11922 hclge_state_init(hdev); 11923 hdev->last_reset_time = jiffies; 11924 11925 /* Enable MISC vector(vector0) */ 11926 enable_irq(hdev->misc_vector.vector_irq); 11927 hclge_enable_vector(&hdev->misc_vector, true); 11928 11929 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11930 HCLGE_DRIVER_NAME); 11931 11932 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11933 return 0; 11934 11935err_ptp_uninit: 11936 hclge_ptp_uninit(hdev); 11937err_mdiobus_unreg: 11938 if (hdev->hw.mac.phydev) 11939 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11940err_msi_irq_uninit: 11941 hclge_misc_irq_uninit(hdev); 11942err_msi_uninit: 11943 pci_free_irq_vectors(pdev); 11944err_cmd_uninit: 11945 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11946err_pci_uninit: 11947 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11948 pci_release_regions(pdev); 11949 pci_disable_device(pdev); 11950out: 11951 mutex_destroy(&hdev->vport_lock); 11952 return ret; 11953} 11954 11955static void hclge_stats_clear(struct hclge_dev *hdev) 11956{ 11957 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11958 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11959} 11960 11961static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11962{ 11963 return hclge_config_switch_param(hdev, vf, enable, 11964 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11965} 11966 11967static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11968{ 11969 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11970 HCLGE_FILTER_FE_NIC_INGRESS_B, 11971 enable, vf); 11972} 11973 11974static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11975{ 11976 int ret; 11977 11978 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11979 if (ret) { 11980 dev_err(&hdev->pdev->dev, 11981 "Set vf %d mac spoof check %s failed, ret=%d\n", 11982 vf, str_on_off(enable), ret); 11983 return ret; 11984 } 11985 11986 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11987 if (ret) 11988 dev_err(&hdev->pdev->dev, 11989 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11990 vf, str_on_off(enable), ret); 11991 11992 return ret; 11993} 11994 11995static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11996 bool enable) 11997{ 11998 struct hclge_vport *vport = hclge_get_vport(handle); 11999 struct hclge_dev *hdev = vport->back; 12000 u32 new_spoofchk = enable ? 1 : 0; 12001 int ret; 12002 12003 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 12004 return -EOPNOTSUPP; 12005 12006 vport = hclge_get_vf_vport(hdev, vf); 12007 if (!vport) 12008 return -EINVAL; 12009 12010 if (vport->vf_info.spoofchk == new_spoofchk) 12011 return 0; 12012 12013 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 12014 dev_warn(&hdev->pdev->dev, 12015 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 12016 vf); 12017 else if (enable && hclge_is_umv_space_full(vport, true)) 12018 dev_warn(&hdev->pdev->dev, 12019 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 12020 vf); 12021 12022 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 12023 if (ret) 12024 return ret; 12025 12026 vport->vf_info.spoofchk = new_spoofchk; 12027 return 0; 12028} 12029 12030static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 12031{ 12032 struct hclge_vport *vport = hdev->vport; 12033 int ret; 12034 int i; 12035 12036 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 12037 return 0; 12038 12039 /* resume the vf spoof check state after reset */ 12040 for (i = 0; i < hdev->num_alloc_vport; i++) { 12041 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 12042 vport->vf_info.spoofchk); 12043 if (ret) 12044 return ret; 12045 12046 vport++; 12047 } 12048 12049 return 0; 12050} 12051 12052static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 12053{ 12054 struct hclge_vport *vport = hclge_get_vport(handle); 12055 struct hclge_dev *hdev = vport->back; 12056 u32 new_trusted = enable ? 1 : 0; 12057 12058 vport = hclge_get_vf_vport(hdev, vf); 12059 if (!vport) 12060 return -EINVAL; 12061 12062 if (vport->vf_info.trusted == new_trusted) 12063 return 0; 12064 12065 vport->vf_info.trusted = new_trusted; 12066 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12067 hclge_task_schedule(hdev, 0); 12068 12069 return 0; 12070} 12071 12072static void hclge_reset_vf_rate(struct hclge_dev *hdev) 12073{ 12074 int ret; 12075 int vf; 12076 12077 /* reset vf rate to default value */ 12078 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 12079 struct hclge_vport *vport = &hdev->vport[vf]; 12080 12081 vport->vf_info.max_tx_rate = 0; 12082 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 12083 if (ret) 12084 dev_err(&hdev->pdev->dev, 12085 "vf%d failed to reset to default, ret=%d\n", 12086 vf - HCLGE_VF_VPORT_START_NUM, ret); 12087 } 12088} 12089 12090static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 12091 int min_tx_rate, int max_tx_rate) 12092{ 12093 if (min_tx_rate != 0 || 12094 max_tx_rate < 0 || (u32)max_tx_rate > hdev->hw.mac.max_speed) { 12095 dev_err(&hdev->pdev->dev, 12096 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 12097 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 12098 return -EINVAL; 12099 } 12100 12101 return 0; 12102} 12103 12104static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 12105 int min_tx_rate, int max_tx_rate, bool force) 12106{ 12107 struct hclge_vport *vport = hclge_get_vport(handle); 12108 struct hclge_dev *hdev = vport->back; 12109 int ret; 12110 12111 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 12112 if (ret) 12113 return ret; 12114 12115 vport = hclge_get_vf_vport(hdev, vf); 12116 if (!vport) 12117 return -EINVAL; 12118 12119 if (!force && (u32)max_tx_rate == vport->vf_info.max_tx_rate) 12120 return 0; 12121 12122 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 12123 if (ret) 12124 return ret; 12125 12126 vport->vf_info.max_tx_rate = max_tx_rate; 12127 12128 return 0; 12129} 12130 12131static int hclge_resume_vf_rate(struct hclge_dev *hdev) 12132{ 12133 struct hnae3_handle *handle = &hdev->vport->nic; 12134 struct hclge_vport *vport; 12135 int ret; 12136 int vf; 12137 12138 /* resume the vf max_tx_rate after reset */ 12139 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12140 vport = hclge_get_vf_vport(hdev, vf); 12141 if (!vport) 12142 return -EINVAL; 12143 12144 /* zero means max rate, after reset, firmware already set it to 12145 * max rate, so just continue. 12146 */ 12147 if (!vport->vf_info.max_tx_rate) 12148 continue; 12149 12150 ret = hclge_set_vf_rate(handle, vf, 0, 12151 vport->vf_info.max_tx_rate, true); 12152 if (ret) { 12153 dev_err(&hdev->pdev->dev, 12154 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12155 vf, vport->vf_info.max_tx_rate, ret); 12156 return ret; 12157 } 12158 } 12159 12160 return 0; 12161} 12162 12163static void hclge_reset_vport_state(struct hclge_dev *hdev) 12164{ 12165 struct hclge_vport *vport = hdev->vport; 12166 int i; 12167 12168 for (i = 0; i < hdev->num_alloc_vport; i++) { 12169 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12170 vport++; 12171 } 12172} 12173 12174static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12175{ 12176 struct hclge_dev *hdev = ae_dev->priv; 12177 struct pci_dev *pdev = ae_dev->pdev; 12178 int ret; 12179 12180 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12181 12182 hclge_stats_clear(hdev); 12183 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12184 * so here should not clean table in memory. 12185 */ 12186 if (hdev->reset_type == HNAE3_IMP_RESET || 12187 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12188 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12189 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12190 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12191 hclge_reset_umv_space(hdev); 12192 } 12193 12194 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12195 true, hdev->reset_pending); 12196 if (ret) { 12197 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12198 return ret; 12199 } 12200 12201 ret = hclge_map_tqp(hdev); 12202 if (ret) { 12203 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12204 return ret; 12205 } 12206 12207 ret = hclge_mac_init(hdev); 12208 if (ret) { 12209 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12210 return ret; 12211 } 12212 12213 ret = hclge_tp_port_init(hdev); 12214 if (ret) { 12215 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12216 ret); 12217 return ret; 12218 } 12219 12220 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12221 if (ret) { 12222 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12223 return ret; 12224 } 12225 12226 ret = hclge_config_gro(hdev); 12227 if (ret) 12228 return ret; 12229 12230 ret = hclge_init_vlan_config(hdev); 12231 if (ret) { 12232 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12233 return ret; 12234 } 12235 12236 hclge_reset_tc_config(hdev); 12237 12238 ret = hclge_tm_init_hw(hdev, true); 12239 if (ret) { 12240 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12241 return ret; 12242 } 12243 12244 ret = hclge_rss_init_hw(hdev); 12245 if (ret) { 12246 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12247 return ret; 12248 } 12249 12250 ret = init_mgr_tbl(hdev); 12251 if (ret) { 12252 dev_err(&pdev->dev, 12253 "failed to reinit manager table, ret = %d\n", ret); 12254 return ret; 12255 } 12256 12257 ret = hclge_init_fd_config(hdev); 12258 if (ret) { 12259 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12260 return ret; 12261 } 12262 12263 ret = hclge_ptp_init(hdev); 12264 if (ret) 12265 return ret; 12266 12267 /* Log and clear the hw errors those already occurred */ 12268 if (hnae3_dev_ras_imp_supported(hdev)) 12269 hclge_handle_occurred_error(hdev); 12270 else 12271 hclge_handle_all_hns_hw_errors(ae_dev); 12272 12273 /* Re-enable the hw error interrupts because 12274 * the interrupts get disabled on global reset. 12275 */ 12276 ret = hclge_config_nic_hw_error(hdev, true); 12277 if (ret) { 12278 dev_err(&pdev->dev, 12279 "fail(%d) to re-enable NIC hw error interrupts\n", 12280 ret); 12281 return ret; 12282 } 12283 12284 if (hdev->roce_client) { 12285 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12286 if (ret) { 12287 dev_err(&pdev->dev, 12288 "fail(%d) to re-enable roce ras interrupts\n", 12289 ret); 12290 return ret; 12291 } 12292 } 12293 12294 hclge_reset_vport_state(hdev); 12295 ret = hclge_reset_vport_spoofchk(hdev); 12296 if (ret) 12297 return ret; 12298 12299 ret = hclge_resume_vf_rate(hdev); 12300 if (ret) 12301 return ret; 12302 12303 hclge_init_rxd_adv_layout(hdev); 12304 12305 ret = hclge_update_wol(hdev); 12306 if (ret) 12307 dev_warn(&pdev->dev, 12308 "failed to update wol config, ret = %d\n", ret); 12309 12310 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12311 HCLGE_DRIVER_NAME); 12312 12313 return 0; 12314} 12315 12316static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12317{ 12318 struct hclge_dev *hdev = ae_dev->priv; 12319 struct hclge_mac *mac = &hdev->hw.mac; 12320 12321 hclge_reset_vf_rate(hdev); 12322 hclge_clear_vf_vlan(hdev); 12323 hclge_state_uninit(hdev); 12324 hclge_ptp_uninit(hdev); 12325 hclge_uninit_rxd_adv_layout(hdev); 12326 hclge_uninit_mac_table(hdev); 12327 hclge_del_all_fd_entries(hdev); 12328 12329 if (mac->phydev) 12330 mdiobus_unregister(mac->mdio_bus); 12331 12332 /* Disable MISC vector(vector0) */ 12333 hclge_enable_vector(&hdev->misc_vector, false); 12334 disable_irq(hdev->misc_vector.vector_irq); 12335 12336 /* Disable all hw interrupts */ 12337 hclge_config_mac_tnl_int(hdev, false); 12338 hclge_config_nic_hw_error(hdev, false); 12339 hclge_config_rocee_ras_interrupt(hdev, false); 12340 12341 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12342 hclge_misc_irq_uninit(hdev); 12343 hclge_devlink_uninit(hdev); 12344 hclge_pci_uninit(hdev); 12345 hclge_uninit_vport_vlan_table(hdev); 12346 mutex_destroy(&hdev->vport_lock); 12347 ae_dev->priv = NULL; 12348} 12349 12350static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12351{ 12352 struct hclge_vport *vport = hclge_get_vport(handle); 12353 struct hclge_dev *hdev = vport->back; 12354 12355 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12356} 12357 12358static void hclge_get_channels(struct hnae3_handle *handle, 12359 struct ethtool_channels *ch) 12360{ 12361 ch->max_combined = hclge_get_max_channels(handle); 12362 ch->other_count = 1; 12363 ch->max_other = 1; 12364 ch->combined_count = handle->kinfo.rss_size; 12365} 12366 12367static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12368 u16 *alloc_tqps, u16 *max_rss_size) 12369{ 12370 struct hclge_vport *vport = hclge_get_vport(handle); 12371 struct hclge_dev *hdev = vport->back; 12372 12373 *alloc_tqps = vport->alloc_tqps; 12374 *max_rss_size = hdev->pf_rss_size_max; 12375} 12376 12377static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12378{ 12379 struct hclge_vport *vport = hclge_get_vport(handle); 12380 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12381 struct hclge_dev *hdev = vport->back; 12382 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12383 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12384 u16 roundup_size; 12385 unsigned int i; 12386 12387 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12388 roundup_size = ilog2(roundup_size); 12389 /* Set the RSS TC mode according to the new RSS size */ 12390 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12391 tc_valid[i] = 0; 12392 12393 if (!(hdev->hw_tc_map & BIT(i))) 12394 continue; 12395 12396 tc_valid[i] = 1; 12397 tc_size[i] = roundup_size; 12398 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12399 } 12400 12401 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12402 tc_size); 12403} 12404 12405static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12406 bool rxfh_configured) 12407{ 12408 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12409 struct hclge_vport *vport = hclge_get_vport(handle); 12410 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12411 struct hclge_dev *hdev = vport->back; 12412 u16 cur_rss_size = kinfo->rss_size; 12413 u16 cur_tqps = kinfo->num_tqps; 12414 u32 *rss_indir; 12415 unsigned int i; 12416 int ret; 12417 12418 kinfo->req_rss_size = new_tqps_num; 12419 12420 ret = hclge_tm_vport_map_update(hdev); 12421 if (ret) { 12422 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12423 return ret; 12424 } 12425 12426 ret = hclge_set_rss_tc_mode_cfg(handle); 12427 if (ret) 12428 return ret; 12429 12430 /* RSS indirection table has been configured by user */ 12431 if (rxfh_configured) 12432 goto out; 12433 12434 /* Reinitializes the rss indirect table according to the new RSS size */ 12435 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12436 GFP_KERNEL); 12437 if (!rss_indir) 12438 return -ENOMEM; 12439 12440 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12441 rss_indir[i] = i % kinfo->rss_size; 12442 12443 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12444 if (ret) 12445 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12446 ret); 12447 12448 kfree(rss_indir); 12449 12450out: 12451 if (!ret) 12452 dev_info(&hdev->pdev->dev, 12453 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12454 cur_rss_size, kinfo->rss_size, 12455 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12456 12457 return ret; 12458} 12459 12460static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12461{ 12462 struct hclge_set_led_state_cmd *req; 12463 struct hclge_desc desc; 12464 int ret; 12465 12466 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12467 12468 req = (struct hclge_set_led_state_cmd *)desc.data; 12469 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12470 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12471 12472 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12473 if (ret) 12474 dev_err(&hdev->pdev->dev, 12475 "Send set led state cmd error, ret =%d\n", ret); 12476 12477 return ret; 12478} 12479 12480enum hclge_led_status { 12481 HCLGE_LED_OFF, 12482 HCLGE_LED_ON, 12483 HCLGE_LED_NO_CHANGE = 0xFF, 12484}; 12485 12486static int hclge_set_led_id(struct hnae3_handle *handle, 12487 enum ethtool_phys_id_state status) 12488{ 12489 struct hclge_vport *vport = hclge_get_vport(handle); 12490 struct hclge_dev *hdev = vport->back; 12491 12492 switch (status) { 12493 case ETHTOOL_ID_ACTIVE: 12494 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12495 case ETHTOOL_ID_INACTIVE: 12496 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12497 default: 12498 return -EINVAL; 12499 } 12500} 12501 12502static void hclge_get_link_mode(struct hnae3_handle *handle, 12503 unsigned long *supported, 12504 unsigned long *advertising) 12505{ 12506 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12507 struct hclge_vport *vport = hclge_get_vport(handle); 12508 struct hclge_dev *hdev = vport->back; 12509 unsigned int idx = 0; 12510 12511 for (; idx < size; idx++) { 12512 supported[idx] = hdev->hw.mac.supported[idx]; 12513 advertising[idx] = hdev->hw.mac.advertising[idx]; 12514 } 12515} 12516 12517static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12518{ 12519 struct hclge_vport *vport = hclge_get_vport(handle); 12520 struct hclge_dev *hdev = vport->back; 12521 bool gro_en_old = hdev->gro_en; 12522 int ret; 12523 12524 hdev->gro_en = enable; 12525 ret = hclge_config_gro(hdev); 12526 if (ret) 12527 hdev->gro_en = gro_en_old; 12528 12529 return ret; 12530} 12531 12532static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12533{ 12534 struct hnae3_handle *handle = &vport->nic; 12535 struct hclge_dev *hdev = vport->back; 12536 bool uc_en = false; 12537 bool mc_en = false; 12538 u8 tmp_flags; 12539 bool bc_en; 12540 int ret; 12541 12542 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12543 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12544 vport->last_promisc_flags = vport->overflow_promisc_flags; 12545 } 12546 12547 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12548 &vport->state)) 12549 return 0; 12550 12551 /* for PF */ 12552 if (!vport->vport_id) { 12553 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12554 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12555 tmp_flags & HNAE3_MPE); 12556 if (!ret) 12557 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12558 &vport->state); 12559 else 12560 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12561 &vport->state); 12562 return ret; 12563 } 12564 12565 /* for VF */ 12566 if (vport->vf_info.trusted) { 12567 uc_en = vport->vf_info.request_uc_en > 0 || 12568 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12569 mc_en = vport->vf_info.request_mc_en > 0 || 12570 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12571 } 12572 bc_en = vport->vf_info.request_bc_en > 0; 12573 12574 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12575 mc_en, bc_en); 12576 if (ret) { 12577 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12578 return ret; 12579 } 12580 hclge_set_vport_vlan_fltr_change(vport); 12581 12582 return 0; 12583} 12584 12585static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12586{ 12587 struct hclge_vport *vport; 12588 int ret; 12589 u16 i; 12590 12591 for (i = 0; i < hdev->num_alloc_vport; i++) { 12592 vport = &hdev->vport[i]; 12593 12594 ret = hclge_sync_vport_promisc_mode(vport); 12595 if (ret) 12596 return; 12597 } 12598} 12599 12600static bool hclge_module_existed(struct hclge_dev *hdev) 12601{ 12602 struct hclge_desc desc; 12603 u32 existed; 12604 int ret; 12605 12606 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12607 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12608 if (ret) { 12609 dev_err(&hdev->pdev->dev, 12610 "failed to get SFP exist state, ret = %d\n", ret); 12611 return false; 12612 } 12613 12614 existed = le32_to_cpu(desc.data[0]); 12615 12616 return existed != 0; 12617} 12618 12619/* need 6 bds(total 140 bytes) in one reading 12620 * return the number of bytes actually read, 0 means read failed. 12621 */ 12622static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12623 u32 len, u8 *data) 12624{ 12625 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12626 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12627 u16 read_len; 12628 u16 copy_len; 12629 int ret; 12630 int i; 12631 12632 /* setup all 6 bds to read module eeprom info. */ 12633 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12634 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12635 true); 12636 12637 /* bd0~bd4 need next flag */ 12638 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12639 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12640 } 12641 12642 /* setup bd0, this bd contains offset and read length. */ 12643 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12644 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12645 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12646 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12647 12648 ret = hclge_cmd_send(&hdev->hw, desc, i); 12649 if (ret) { 12650 dev_err(&hdev->pdev->dev, 12651 "failed to get SFP eeprom info, ret = %d\n", ret); 12652 return 0; 12653 } 12654 12655 /* copy sfp info from bd0 to out buffer. */ 12656 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12657 memcpy(data, sfp_info_bd0->data, copy_len); 12658 read_len = copy_len; 12659 12660 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12661 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12662 if (read_len >= len) 12663 return read_len; 12664 12665 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12666 memcpy(data + read_len, desc[i].data, copy_len); 12667 read_len += copy_len; 12668 } 12669 12670 return read_len; 12671} 12672 12673static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12674 u32 len, u8 *data) 12675{ 12676 struct hclge_vport *vport = hclge_get_vport(handle); 12677 struct hclge_dev *hdev = vport->back; 12678 u32 read_len = 0; 12679 u16 data_len; 12680 12681 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12682 return -EOPNOTSUPP; 12683 12684 if (!hclge_module_existed(hdev)) 12685 return -ENXIO; 12686 12687 while (read_len < len) { 12688 data_len = hclge_get_sfp_eeprom_info(hdev, 12689 offset + read_len, 12690 len - read_len, 12691 data + read_len); 12692 if (!data_len) 12693 return -EIO; 12694 12695 read_len += data_len; 12696 } 12697 12698 return 0; 12699} 12700 12701static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12702 u32 *status_code) 12703{ 12704 struct hclge_vport *vport = hclge_get_vport(handle); 12705 struct hclge_dev *hdev = vport->back; 12706 struct hclge_desc desc; 12707 int ret; 12708 12709 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12710 return -EOPNOTSUPP; 12711 12712 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12713 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12714 if (ret) { 12715 dev_err(&hdev->pdev->dev, 12716 "failed to query link diagnosis info, ret = %d\n", ret); 12717 return ret; 12718 } 12719 12720 *status_code = le32_to_cpu(desc.data[0]); 12721 return 0; 12722} 12723 12724/* After disable sriov, VF still has some config and info need clean, 12725 * which configed by PF. 12726 */ 12727static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12728{ 12729 struct hclge_dev *hdev = vport->back; 12730 struct hclge_vlan_info vlan_info; 12731 int ret; 12732 12733 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12734 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12735 vport->need_notify = 0; 12736 vport->mps = 0; 12737 12738 /* after disable sriov, clean VF rate configured by PF */ 12739 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12740 if (ret) 12741 dev_err(&hdev->pdev->dev, 12742 "failed to clean vf%d rate config, ret = %d\n", 12743 vfid, ret); 12744 12745 vlan_info.vlan_tag = 0; 12746 vlan_info.qos = 0; 12747 vlan_info.vlan_proto = ETH_P_8021Q; 12748 ret = hclge_update_port_base_vlan_cfg(vport, 12749 HNAE3_PORT_BASE_VLAN_DISABLE, 12750 &vlan_info); 12751 if (ret) 12752 dev_err(&hdev->pdev->dev, 12753 "failed to clean vf%d port base vlan, ret = %d\n", 12754 vfid, ret); 12755 12756 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12757 if (ret) 12758 dev_err(&hdev->pdev->dev, 12759 "failed to clean vf%d spoof config, ret = %d\n", 12760 vfid, ret); 12761 12762 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12763} 12764 12765static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12766{ 12767 struct hclge_dev *hdev = ae_dev->priv; 12768 struct hclge_vport *vport; 12769 int i; 12770 12771 for (i = 0; i < num_vfs; i++) { 12772 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12773 12774 hclge_clear_vport_vf_info(vport, i); 12775 } 12776} 12777 12778static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12779 u8 *priority) 12780{ 12781 struct hclge_vport *vport = hclge_get_vport(h); 12782 12783 if (dscp >= HNAE3_MAX_DSCP) 12784 return -EINVAL; 12785 12786 if (tc_mode) 12787 *tc_mode = vport->nic.kinfo.tc_map_mode; 12788 if (priority) 12789 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12790 vport->nic.kinfo.dscp_prio[dscp]; 12791 12792 return 0; 12793} 12794 12795static const struct hnae3_ae_ops hclge_ops = { 12796 .init_ae_dev = hclge_init_ae_dev, 12797 .uninit_ae_dev = hclge_uninit_ae_dev, 12798 .reset_prepare = hclge_reset_prepare_general, 12799 .reset_done = hclge_reset_done, 12800 .init_client_instance = hclge_init_client_instance, 12801 .uninit_client_instance = hclge_uninit_client_instance, 12802 .map_ring_to_vector = hclge_map_ring_to_vector, 12803 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12804 .get_vector = hclge_get_vector, 12805 .put_vector = hclge_put_vector, 12806 .set_promisc_mode = hclge_set_promisc_mode, 12807 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12808 .set_loopback = hclge_set_loopback, 12809 .start = hclge_ae_start, 12810 .stop = hclge_ae_stop, 12811 .client_start = hclge_client_start, 12812 .client_stop = hclge_client_stop, 12813 .get_status = hclge_get_status, 12814 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12815 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12816 .get_media_type = hclge_get_media_type, 12817 .check_port_speed = hclge_check_port_speed, 12818 .get_fec_stats = hclge_get_fec_stats, 12819 .get_fec = hclge_get_fec, 12820 .set_fec = hclge_set_fec, 12821 .get_rss_key_size = hclge_comm_get_rss_key_size, 12822 .get_rss = hclge_get_rss, 12823 .set_rss = hclge_set_rss, 12824 .set_rss_tuple = hclge_set_rss_tuple, 12825 .get_rss_tuple = hclge_get_rss_tuple, 12826 .get_tc_size = hclge_get_tc_size, 12827 .get_mac_addr = hclge_get_mac_addr, 12828 .set_mac_addr = hclge_set_mac_addr, 12829 .do_ioctl = hclge_do_ioctl, 12830 .add_uc_addr = hclge_add_uc_addr, 12831 .rm_uc_addr = hclge_rm_uc_addr, 12832 .add_mc_addr = hclge_add_mc_addr, 12833 .rm_mc_addr = hclge_rm_mc_addr, 12834 .set_autoneg = hclge_set_autoneg, 12835 .get_autoneg = hclge_get_autoneg, 12836 .restart_autoneg = hclge_restart_autoneg, 12837 .halt_autoneg = hclge_halt_autoneg, 12838 .get_pauseparam = hclge_get_pauseparam, 12839 .set_pauseparam = hclge_set_pauseparam, 12840 .set_mtu = hclge_set_mtu, 12841 .reset_queue = hclge_reset_tqp, 12842 .get_stats = hclge_get_stats, 12843 .get_mac_stats = hclge_get_mac_stat, 12844 .update_stats = hclge_update_stats, 12845 .get_strings = hclge_get_strings, 12846 .get_sset_count = hclge_get_sset_count, 12847 .get_fw_version = hclge_get_fw_version, 12848 .get_mdix_mode = hclge_get_mdix_mode, 12849 .enable_vlan_filter = hclge_enable_vlan_filter, 12850 .set_vlan_filter = hclge_set_vlan_filter, 12851 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12852 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12853 .reset_event = hclge_reset_event, 12854 .get_reset_level = hclge_get_reset_level, 12855 .set_default_reset_request = hclge_set_def_reset_request, 12856 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12857 .set_channels = hclge_set_channels, 12858 .get_channels = hclge_get_channels, 12859 .get_regs_len = hclge_get_regs_len, 12860 .get_regs = hclge_get_regs, 12861 .set_led_id = hclge_set_led_id, 12862 .get_link_mode = hclge_get_link_mode, 12863 .add_fd_entry = hclge_add_fd_entry, 12864 .del_fd_entry = hclge_del_fd_entry, 12865 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12866 .get_fd_rule_info = hclge_get_fd_rule_info, 12867 .get_fd_all_rules = hclge_get_all_rules, 12868 .enable_fd = hclge_enable_fd, 12869 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12870 .dbg_get_read_func = hclge_dbg_get_read_func, 12871 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12872 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12873 .ae_dev_resetting = hclge_ae_dev_resetting, 12874 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12875 .set_gro_en = hclge_gro_en, 12876 .get_global_queue_id = hclge_covert_handle_qid_global, 12877 .set_timer_task = hclge_set_timer_task, 12878 .mac_connect_phy = hclge_mac_connect_phy, 12879 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12880 .get_vf_config = hclge_get_vf_config, 12881 .set_vf_link_state = hclge_set_vf_link_state, 12882 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12883 .set_vf_trust = hclge_set_vf_trust, 12884 .set_vf_rate = hclge_set_vf_rate, 12885 .set_vf_mac = hclge_set_vf_mac, 12886 .get_module_eeprom = hclge_get_module_eeprom, 12887 .get_cmdq_stat = hclge_get_cmdq_stat, 12888 .add_cls_flower = hclge_add_cls_flower, 12889 .del_cls_flower = hclge_del_cls_flower, 12890 .cls_flower_active = hclge_is_cls_flower_active, 12891 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12892 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12893 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12894 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12895 .get_ts_info = hclge_ptp_get_ts_info, 12896 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12897 .clean_vf_config = hclge_clean_vport_config, 12898 .get_dscp_prio = hclge_get_dscp_prio, 12899 .get_wol = hclge_get_wol, 12900 .set_wol = hclge_set_wol, 12901 .hwtstamp_get = hclge_ptp_get_cfg, 12902 .hwtstamp_set = hclge_ptp_set_cfg, 12903}; 12904 12905static struct hnae3_ae_algo ae_algo = { 12906 .ops = &hclge_ops, 12907 .pdev_id_table = ae_algo_pci_tbl, 12908}; 12909 12910static int __init hclge_init(void) 12911{ 12912 pr_debug("%s is initializing\n", HCLGE_NAME); 12913 12914 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, 12915 HCLGE_NAME); 12916 if (!hclge_wq) { 12917 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12918 return -ENOMEM; 12919 } 12920 12921 hnae3_register_ae_algo(&ae_algo); 12922 12923 return 0; 12924} 12925 12926static void __exit hclge_exit(void) 12927{ 12928 hnae3_acquire_unload_lock(); 12929 hnae3_unregister_ae_algo_prepare(&ae_algo); 12930 hnae3_unregister_ae_algo(&ae_algo); 12931 destroy_workqueue(hclge_wq); 12932 hnae3_release_unload_lock(); 12933} 12934module_init(hclge_init); 12935module_exit(hclge_exit); 12936 12937MODULE_LICENSE("GPL"); 12938MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12939MODULE_DESCRIPTION("HCLGE Driver"); 12940MODULE_VERSION(HCLGE_MOD_VERSION);
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