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hnae3.h
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linux-6.19.14/drivers/net/ethernet/hisilicon/hns3/hnae3.h
1/* SPDX-License-Identifier: GPL-2.0+ */ 2// Copyright (c) 2016-2017 Hisilicon Limited. 3 4#ifndef __HNAE3_H 5#define __HNAE3_H 6 7/* Names used in this framework: 8 * ae handle (handle): 9 * a set of queues provided by AE 10 * ring buffer queue (rbq): 11 * the channel between upper layer and the AE, can do tx and rx 12 * ring: 13 * a tx or rx channel within a rbq 14 * ring description (desc): 15 * an element in the ring with packet information 16 * buffer: 17 * a memory region referred by desc with the full packet payload 18 * 19 * "num" means a static number set as a parameter, "count" mean a dynamic 20 * number set while running 21 * "cb" means control block 22 */ 23 24#include <linux/acpi.h> 25#include <linux/dcbnl.h> 26#include <linux/delay.h> 27#include <linux/device.h> 28#include <linux/ethtool.h> 29#include <linux/module.h> 30#include <linux/netdevice.h> 31#include <linux/pci.h> 32#include <linux/pkt_sched.h> 33#include <linux/types.h> 34#include <linux/bitmap.h> 35#include <net/pkt_cls.h> 36#include <net/pkt_sched.h> 37 38#define HNAE3_MOD_VERSION "1.0" 39 40#define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 41 42/* Device version */ 43#define HNAE3_DEVICE_VERSION_V1 0x00020 44#define HNAE3_DEVICE_VERSION_V2 0x00021 45#define HNAE3_DEVICE_VERSION_V3 0x00030 46 47#define HNAE3_PCI_REVISION_BIT_SIZE 8 48 49/* Device IDs */ 50#define HNAE3_DEV_ID_GE 0xA220 51#define HNAE3_DEV_ID_25GE 0xA221 52#define HNAE3_DEV_ID_25GE_RDMA 0xA222 53#define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 54#define HNAE3_DEV_ID_50GE_RDMA 0xA224 55#define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 56#define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 57#define HNAE3_DEV_ID_200G_RDMA 0xA228 58#define HNAE3_DEV_ID_VF 0xA22E 59#define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 60 61#define HNAE3_CLASS_NAME_SIZE 16 62 63#define HNAE3_DEV_INITED_B 0x0 64#define HNAE3_DEV_SUPPORT_ROCE_B 0x1 65#define HNAE3_DEV_SUPPORT_DCB_B 0x2 66#define HNAE3_KNIC_CLIENT_INITED_B 0x3 67#define HNAE3_UNIC_CLIENT_INITED_B 0x4 68#define HNAE3_ROCE_CLIENT_INITED_B 0x5 69 70#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \ 71 BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 72 73#define hnae3_dev_roce_supported(hdev) \ 74 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 75 76#define hnae3_dev_dcb_supported(hdev) \ 77 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 78 79enum HNAE3_DEV_CAP_BITS { 80 HNAE3_DEV_SUPPORT_FD_B, 81 HNAE3_DEV_SUPPORT_GRO_B, 82 HNAE3_DEV_SUPPORT_FEC_B, 83 HNAE3_DEV_SUPPORT_UDP_GSO_B, 84 HNAE3_DEV_SUPPORT_QB_B, 85 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 86 HNAE3_DEV_SUPPORT_PTP_B, 87 HNAE3_DEV_SUPPORT_INT_QL_B, 88 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 89 HNAE3_DEV_SUPPORT_TX_PUSH_B, 90 HNAE3_DEV_SUPPORT_PHY_IMP_B, 91 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 92 HNAE3_DEV_SUPPORT_HW_PAD_B, 93 HNAE3_DEV_SUPPORT_STASH_B, 94 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 95 HNAE3_DEV_SUPPORT_PAUSE_B, 96 HNAE3_DEV_SUPPORT_RAS_IMP_B, 97 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 98 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 99 HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 100 HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, 101 HNAE3_DEV_SUPPORT_CQ_B, 102 HNAE3_DEV_SUPPORT_FEC_STATS_B, 103 HNAE3_DEV_SUPPORT_LANE_NUM_B, 104 HNAE3_DEV_SUPPORT_WOL_B, 105 HNAE3_DEV_SUPPORT_TM_FLUSH_B, 106 HNAE3_DEV_SUPPORT_VF_FAULT_B, 107 HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B, 108}; 109 110#define hnae3_ae_dev_fd_supported(ae_dev) \ 111 test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps) 112 113#define hnae3_ae_dev_gro_supported(ae_dev) \ 114 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps) 115 116#define hnae3_dev_fec_supported(hdev) \ 117 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 118 119#define hnae3_dev_udp_gso_supported(hdev) \ 120 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 121 122#define hnae3_dev_qb_supported(hdev) \ 123 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 124 125#define hnae3_dev_fd_forward_tc_supported(hdev) \ 126 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 127 128#define hnae3_dev_ptp_supported(hdev) \ 129 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 130 131#define hnae3_dev_int_ql_supported(hdev) \ 132 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 133 134#define hnae3_dev_hw_csum_supported(hdev) \ 135 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps) 136 137#define hnae3_dev_tx_push_supported(hdev) \ 138 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 139 140#define hnae3_dev_phy_imp_supported(hdev) \ 141 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 142 143#define hnae3_dev_ras_imp_supported(hdev) \ 144 test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps) 145 146#define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 147 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 148 149#define hnae3_dev_hw_pad_supported(hdev) \ 150 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 151 152#define hnae3_dev_stash_supported(hdev) \ 153 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 154 155#define hnae3_dev_pause_supported(hdev) \ 156 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps) 157 158#define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 159 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 160 161#define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \ 162 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps) 163 164#define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \ 165 test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps) 166 167#define hnae3_ae_dev_cq_supported(ae_dev) \ 168 test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps) 169 170#define hnae3_ae_dev_fec_stats_supported(ae_dev) \ 171 test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps) 172 173#define hnae3_ae_dev_lane_num_supported(ae_dev) \ 174 test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps) 175 176#define hnae3_ae_dev_wol_supported(ae_dev) \ 177 test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps) 178 179#define hnae3_ae_dev_tm_flush_supported(hdev) \ 180 test_bit(HNAE3_DEV_SUPPORT_TM_FLUSH_B, (hdev)->ae_dev->caps) 181 182#define hnae3_ae_dev_vf_fault_supported(ae_dev) \ 183 test_bit(HNAE3_DEV_SUPPORT_VF_FAULT_B, (ae_dev)->caps) 184 185#define hnae3_ae_dev_gen_reg_dfx_supported(hdev) \ 186 test_bit(HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B, (hdev)->ae_dev->caps) 187 188enum HNAE3_PF_CAP_BITS { 189 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0, 190}; 191#define ring_ptr_move_fw(ring, p) \ 192 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 193#define ring_ptr_move_bw(ring, p) \ 194 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 195 196struct hnae3_handle; 197 198struct hnae3_queue { 199 void __iomem *io_base; 200 void __iomem *mem_base; 201 struct hnae3_ae_algo *ae_algo; 202 struct hnae3_handle *handle; 203 int tqp_index; /* index in a handle */ 204 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 205 u16 tx_desc_num; /* total number of tx desc */ 206 u16 rx_desc_num; /* total number of rx desc */ 207}; 208 209struct hns3_mac_stats { 210 u64 tx_pause_cnt; 211 u64 rx_pause_cnt; 212}; 213 214/* hnae3 loop mode */ 215enum hnae3_loop { 216 HNAE3_LOOP_EXTERNAL, 217 HNAE3_LOOP_APP, 218 HNAE3_LOOP_SERIAL_SERDES, 219 HNAE3_LOOP_PARALLEL_SERDES, 220 HNAE3_LOOP_PHY, 221 HNAE3_LOOP_NONE, 222}; 223 224enum hnae3_client_type { 225 HNAE3_CLIENT_KNIC, 226 HNAE3_CLIENT_ROCE, 227}; 228 229/* mac media type */ 230enum hnae3_media_type { 231 HNAE3_MEDIA_TYPE_UNKNOWN, 232 HNAE3_MEDIA_TYPE_FIBER, 233 HNAE3_MEDIA_TYPE_COPPER, 234 HNAE3_MEDIA_TYPE_BACKPLANE, 235 HNAE3_MEDIA_TYPE_NONE, 236}; 237 238/* must be consistent with definition in firmware */ 239enum hnae3_module_type { 240 HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 241 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 242 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 243 HNAE3_MODULE_TYPE_AOC = 0x03, 244 HNAE3_MODULE_TYPE_CR = 0x04, 245 HNAE3_MODULE_TYPE_KR = 0x05, 246 HNAE3_MODULE_TYPE_TP = 0x06, 247}; 248 249enum hnae3_fec_mode { 250 HNAE3_FEC_AUTO = 0, 251 HNAE3_FEC_BASER, 252 HNAE3_FEC_RS, 253 HNAE3_FEC_LLRS, 254 HNAE3_FEC_NONE, 255 HNAE3_FEC_USER_DEF, 256}; 257 258enum hnae3_reset_notify_type { 259 HNAE3_UP_CLIENT, 260 HNAE3_DOWN_CLIENT, 261 HNAE3_INIT_CLIENT, 262 HNAE3_UNINIT_CLIENT, 263}; 264 265enum hnae3_hw_error_type { 266 HNAE3_PPU_POISON_ERROR, 267 HNAE3_CMDQ_ECC_ERROR, 268 HNAE3_IMP_RD_POISON_ERROR, 269 HNAE3_ROCEE_AXI_RESP_ERROR, 270}; 271 272enum hnae3_reset_type { 273 HNAE3_VF_RESET, 274 HNAE3_VF_FUNC_RESET, 275 HNAE3_VF_PF_FUNC_RESET, 276 HNAE3_VF_FULL_RESET, 277 HNAE3_FLR_RESET, 278 HNAE3_FUNC_RESET, 279 HNAE3_GLOBAL_RESET, 280 HNAE3_IMP_RESET, 281 HNAE3_NONE_RESET, 282 HNAE3_VF_EXP_RESET, 283 HNAE3_MAX_RESET, 284}; 285 286enum hnae3_port_base_vlan_state { 287 HNAE3_PORT_BASE_VLAN_DISABLE, 288 HNAE3_PORT_BASE_VLAN_ENABLE, 289 HNAE3_PORT_BASE_VLAN_MODIFY, 290 HNAE3_PORT_BASE_VLAN_NOCHANGE, 291}; 292 293enum hnae3_dbg_cmd { 294 HNAE3_DBG_CMD_TM_NODES, 295 HNAE3_DBG_CMD_TM_PRI, 296 HNAE3_DBG_CMD_TM_QSET, 297 HNAE3_DBG_CMD_TM_MAP, 298 HNAE3_DBG_CMD_TM_PG, 299 HNAE3_DBG_CMD_TM_PORT, 300 HNAE3_DBG_CMD_TC_SCH_INFO, 301 HNAE3_DBG_CMD_QOS_PAUSE_CFG, 302 HNAE3_DBG_CMD_QOS_PRI_MAP, 303 HNAE3_DBG_CMD_QOS_DSCP_MAP, 304 HNAE3_DBG_CMD_QOS_BUF_CFG, 305 HNAE3_DBG_CMD_DEV_INFO, 306 HNAE3_DBG_CMD_TX_BD, 307 HNAE3_DBG_CMD_RX_BD, 308 HNAE3_DBG_CMD_MAC_UC, 309 HNAE3_DBG_CMD_MAC_MC, 310 HNAE3_DBG_CMD_MNG_TBL, 311 HNAE3_DBG_CMD_LOOPBACK, 312 HNAE3_DBG_CMD_PTP_INFO, 313 HNAE3_DBG_CMD_INTERRUPT_INFO, 314 HNAE3_DBG_CMD_RESET_INFO, 315 HNAE3_DBG_CMD_IMP_INFO, 316 HNAE3_DBG_CMD_NCL_CONFIG, 317 HNAE3_DBG_CMD_REG_BIOS_COMMON, 318 HNAE3_DBG_CMD_REG_SSU, 319 HNAE3_DBG_CMD_REG_IGU_EGU, 320 HNAE3_DBG_CMD_REG_RPU, 321 HNAE3_DBG_CMD_REG_NCSI, 322 HNAE3_DBG_CMD_REG_RTC, 323 HNAE3_DBG_CMD_REG_PPP, 324 HNAE3_DBG_CMD_REG_RCB, 325 HNAE3_DBG_CMD_REG_TQP, 326 HNAE3_DBG_CMD_REG_MAC, 327 HNAE3_DBG_CMD_REG_DCB, 328 HNAE3_DBG_CMD_VLAN_CONFIG, 329 HNAE3_DBG_CMD_QUEUE_MAP, 330 HNAE3_DBG_CMD_RX_QUEUE_INFO, 331 HNAE3_DBG_CMD_TX_QUEUE_INFO, 332 HNAE3_DBG_CMD_FD_TCAM, 333 HNAE3_DBG_CMD_FD_COUNTER, 334 HNAE3_DBG_CMD_MAC_TNL_STATUS, 335 HNAE3_DBG_CMD_SERV_INFO, 336 HNAE3_DBG_CMD_UMV_INFO, 337 HNAE3_DBG_CMD_PAGE_POOL_INFO, 338 HNAE3_DBG_CMD_COAL_INFO, 339 HNAE3_DBG_CMD_UNKNOWN, 340}; 341 342#define hnae3_seq_file_to_ae_dev(s) (dev_get_drvdata((s)->private)) 343#define hnae3_seq_file_to_handle(s) \ 344 (((struct hnae3_ae_dev *)hnae3_seq_file_to_ae_dev(s))->handle) 345 346enum hnae3_tc_map_mode { 347 HNAE3_TC_MAP_MODE_PRIO, 348 HNAE3_TC_MAP_MODE_DSCP, 349}; 350 351struct hnae3_vector_info { 352 u8 __iomem *io_addr; 353 int vector; 354}; 355 356#define HNAE3_RING_TYPE_B 0 357#define HNAE3_RING_TYPE_TX 0 358#define HNAE3_RING_TYPE_RX 1 359#define HNAE3_RING_GL_IDX_S 0 360#define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 361#define HNAE3_RING_GL_RX 0 362#define HNAE3_RING_GL_TX 1 363 364#define HNAE3_FW_VERSION_BYTE3_SHIFT 24 365#define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 366#define HNAE3_FW_VERSION_BYTE2_SHIFT 16 367#define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 368#define HNAE3_FW_VERSION_BYTE1_SHIFT 8 369#define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 370#define HNAE3_FW_VERSION_BYTE0_SHIFT 0 371#define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 372 373#define HNAE3_SCC_VERSION_BYTE3_SHIFT 24 374#define HNAE3_SCC_VERSION_BYTE3_MASK GENMASK(31, 24) 375#define HNAE3_SCC_VERSION_BYTE2_SHIFT 16 376#define HNAE3_SCC_VERSION_BYTE2_MASK GENMASK(23, 16) 377#define HNAE3_SCC_VERSION_BYTE1_SHIFT 8 378#define HNAE3_SCC_VERSION_BYTE1_MASK GENMASK(15, 8) 379#define HNAE3_SCC_VERSION_BYTE0_SHIFT 0 380#define HNAE3_SCC_VERSION_BYTE0_MASK GENMASK(7, 0) 381 382struct hnae3_ring_chain_node { 383 struct hnae3_ring_chain_node *next; 384 u32 tqp_index; 385 u32 flag; 386 u32 int_gl_idx; 387}; 388 389#define HNAE3_IS_TX_RING(node) \ 390 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX) 391 392/* device specification info from firmware */ 393struct hnae3_dev_specs { 394 u32 mac_entry_num; /* number of mac-vlan table entry */ 395 u32 mng_entry_num; /* number of manager table entry */ 396 u32 max_tm_rate; 397 u16 rss_ind_tbl_size; 398 u16 rss_key_size; 399 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 400 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */ 401 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 402 u16 max_frm_size; 403 u16 max_qset_num; 404 u16 umv_size; 405 u16 mc_mac_size; 406 u32 mac_stats_num; 407 u8 tnl_num; 408 u8 hilink_version; 409}; 410 411struct hnae3_client_ops { 412 int (*init_instance)(struct hnae3_handle *handle); 413 void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 414 void (*link_status_change)(struct hnae3_handle *handle, bool state); 415 int (*reset_notify)(struct hnae3_handle *handle, 416 enum hnae3_reset_notify_type type); 417 void (*process_hw_error)(struct hnae3_handle *handle, 418 enum hnae3_hw_error_type); 419}; 420 421#define HNAE3_CLIENT_NAME_LENGTH 16 422struct hnae3_client { 423 char name[HNAE3_CLIENT_NAME_LENGTH]; 424 unsigned long state; 425 enum hnae3_client_type type; 426 const struct hnae3_client_ops *ops; 427 struct list_head node; 428}; 429 430#define HNAE3_DEV_CAPS_MAX_NUM 96 431struct hnae3_ae_dev { 432 struct pci_dev *pdev; 433 const struct hnae3_ae_ops *ops; 434 struct list_head node; 435 u32 flag; 436 unsigned long hw_err_reset_req; 437 struct hnae3_dev_specs dev_specs; 438 u32 dev_version; 439 DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM); 440 void *priv; 441 struct hnae3_handle *handle; 442}; 443 444typedef int (*read_func)(struct seq_file *s, void *data); 445 446/* This struct defines the operation on the handle. 447 * 448 * init_ae_dev(): (mandatory) 449 * Get PF configure from pci_dev and initialize PF hardware 450 * uninit_ae_dev() 451 * Disable PF device and release PF resource 452 * register_client 453 * Register client to ae_dev 454 * unregister_client() 455 * Unregister client from ae_dev 456 * start() 457 * Enable the hardware 458 * stop() 459 * Disable the hardware 460 * start_client() 461 * Inform the hclge that client has been started 462 * stop_client() 463 * Inform the hclge that client has been stopped 464 * get_status() 465 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 466 * non-ok 467 * get_ksettings_an_result() 468 * Get negotiation status,speed and duplex 469 * get_media_type() 470 * Get media type of MAC 471 * check_port_speed() 472 * Check target speed whether is supported 473 * adjust_link() 474 * Adjust link status 475 * set_loopback() 476 * Set loopback 477 * set_promisc_mode 478 * Set promisc mode 479 * request_update_promisc_mode 480 * request to hclge(vf) to update promisc mode 481 * set_mtu() 482 * set mtu 483 * get_pauseparam() 484 * get tx and rx of pause frame use 485 * set_pauseparam() 486 * set tx and rx of pause frame use 487 * set_autoneg() 488 * set auto autonegotiation of pause frame use 489 * get_autoneg() 490 * get auto autonegotiation of pause frame use 491 * restart_autoneg() 492 * restart autonegotiation 493 * halt_autoneg() 494 * halt/resume autonegotiation when autonegotiation on 495 * get_coalesce_usecs() 496 * get usecs to delay a TX interrupt after a packet is sent 497 * get_rx_max_coalesced_frames() 498 * get Maximum number of packets to be sent before a TX interrupt. 499 * set_coalesce_usecs() 500 * set usecs to delay a TX interrupt after a packet is sent 501 * set_coalesce_frames() 502 * set Maximum number of packets to be sent before a TX interrupt. 503 * get_mac_addr() 504 * get mac address 505 * set_mac_addr() 506 * set mac address 507 * add_uc_addr 508 * Add unicast addr to mac table 509 * rm_uc_addr 510 * Remove unicast addr from mac table 511 * set_mc_addr() 512 * Set multicast address 513 * add_mc_addr 514 * Add multicast address to mac table 515 * rm_mc_addr 516 * Remove multicast address from mac table 517 * update_stats() 518 * Update Old network device statistics 519 * get_mac_stats() 520 * get mac pause statistics including tx_cnt and rx_cnt 521 * get_ethtool_stats() 522 * Get ethtool network device statistics 523 * get_strings() 524 * Get a set of strings that describe the requested objects 525 * get_sset_count() 526 * Get number of strings that @get_strings will write 527 * update_led_status() 528 * Update the led status 529 * set_led_id() 530 * Set led id 531 * get_regs() 532 * Get regs dump 533 * get_regs_len() 534 * Get the len of the regs dump 535 * get_rss_key_size() 536 * Get rss key size 537 * get_rss() 538 * Get rss table 539 * set_rss() 540 * Set rss table 541 * get_tc_size() 542 * Get tc size of handle 543 * get_vector() 544 * Get vector number and vector information 545 * put_vector() 546 * Put the vector in hdev 547 * map_ring_to_vector() 548 * Map rings to vector 549 * unmap_ring_from_vector() 550 * Unmap rings from vector 551 * reset_queue() 552 * Reset queue 553 * get_fw_version() 554 * Get firmware version 555 * get_mdix_mode() 556 * Get media typr of phy 557 * enable_vlan_filter() 558 * Enable vlan filter 559 * set_vlan_filter() 560 * Set vlan filter config of Ports 561 * set_vf_vlan_filter() 562 * Set vlan filter config of vf 563 * enable_hw_strip_rxvtag() 564 * Enable/disable hardware strip vlan tag of packets received 565 * set_gro_en 566 * Enable/disable HW GRO 567 * add_arfs_entry 568 * Check the 5-tuples of flow, and create flow director rule 569 * get_vf_config 570 * Get the VF configuration setting by the host 571 * set_vf_link_state 572 * Set VF link status 573 * set_vf_spoofchk 574 * Enable/disable spoof check for specified vf 575 * set_vf_trust 576 * Enable/disable trust for specified vf, if the vf being trusted, then 577 * it can enable promisc mode 578 * set_vf_rate 579 * Set the max tx rate of specified vf. 580 * set_vf_mac 581 * Configure the default MAC for specified VF 582 * get_module_eeprom 583 * Get the optical module eeprom info. 584 * add_cls_flower 585 * Add clsflower rule 586 * del_cls_flower 587 * Delete clsflower rule 588 * cls_flower_active 589 * Check if any cls flower rule exist 590 * set_tx_hwts_info 591 * Save information for 1588 tx packet 592 * get_rx_hwts 593 * Get 1588 rx hwstamp 594 * get_ts_info 595 * Get phc info 596 * clean_vf_config 597 * Clean residual vf info after disable sriov 598 * get_wol 599 * Get wake on lan info 600 * set_wol 601 * Config wake on lan 602 * dbg_get_read_func 603 * Return the read func for debugfs seq file 604 */ 605struct hnae3_ae_ops { 606 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 607 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 608 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev, 609 enum hnae3_reset_type rst_type); 610 void (*reset_done)(struct hnae3_ae_dev *ae_dev); 611 int (*init_client_instance)(struct hnae3_client *client, 612 struct hnae3_ae_dev *ae_dev); 613 void (*uninit_client_instance)(struct hnae3_client *client, 614 struct hnae3_ae_dev *ae_dev); 615 int (*start)(struct hnae3_handle *handle); 616 void (*stop)(struct hnae3_handle *handle); 617 int (*client_start)(struct hnae3_handle *handle); 618 void (*client_stop)(struct hnae3_handle *handle); 619 int (*get_status)(struct hnae3_handle *handle); 620 void (*get_ksettings_an_result)(struct hnae3_handle *handle, 621 u8 *auto_neg, u32 *speed, u8 *duplex, 622 u32 *lane_num); 623 624 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 625 u8 duplex, u8 lane_num); 626 627 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 628 u8 *module_type); 629 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 630 void (*get_fec_stats)(struct hnae3_handle *handle, 631 struct ethtool_fec_stats *fec_stats); 632 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 633 u8 *fec_mode); 634 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 635 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 636 int (*set_loopback)(struct hnae3_handle *handle, 637 enum hnae3_loop loop_mode, bool en); 638 639 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 640 bool en_mc_pmc); 641 void (*request_update_promisc_mode)(struct hnae3_handle *handle); 642 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 643 644 void (*get_pauseparam)(struct hnae3_handle *handle, 645 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 646 int (*set_pauseparam)(struct hnae3_handle *handle, 647 u32 auto_neg, u32 rx_en, u32 tx_en); 648 649 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 650 int (*get_autoneg)(struct hnae3_handle *handle); 651 int (*restart_autoneg)(struct hnae3_handle *handle); 652 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 653 654 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 655 u32 *tx_usecs, u32 *rx_usecs); 656 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 657 u32 *tx_frames, u32 *rx_frames); 658 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 659 int (*set_coalesce_frames)(struct hnae3_handle *handle, 660 u32 coalesce_frames); 661 void (*get_coalesce_range)(struct hnae3_handle *handle, 662 u32 *tx_frames_low, u32 *rx_frames_low, 663 u32 *tx_frames_high, u32 *rx_frames_high, 664 u32 *tx_usecs_low, u32 *rx_usecs_low, 665 u32 *tx_usecs_high, u32 *rx_usecs_high); 666 667 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 668 int (*set_mac_addr)(struct hnae3_handle *handle, const void *p, 669 bool is_first); 670 int (*do_ioctl)(struct hnae3_handle *handle, 671 struct ifreq *ifr, int cmd); 672 int (*add_uc_addr)(struct hnae3_handle *handle, 673 const unsigned char *addr); 674 int (*rm_uc_addr)(struct hnae3_handle *handle, 675 const unsigned char *addr); 676 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 677 int (*add_mc_addr)(struct hnae3_handle *handle, 678 const unsigned char *addr); 679 int (*rm_mc_addr)(struct hnae3_handle *handle, 680 const unsigned char *addr); 681 void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 682 void (*update_stats)(struct hnae3_handle *handle); 683 void (*get_stats)(struct hnae3_handle *handle, u64 *data); 684 void (*get_mac_stats)(struct hnae3_handle *handle, 685 struct hns3_mac_stats *mac_stats); 686 void (*get_strings)(struct hnae3_handle *handle, 687 u32 stringset, u8 **data); 688 int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 689 690 void (*get_regs)(struct hnae3_handle *handle, u32 *version, 691 void *data); 692 int (*get_regs_len)(struct hnae3_handle *handle); 693 694 u32 (*get_rss_key_size)(struct hnae3_handle *handle); 695 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 696 u8 *hfunc); 697 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 698 const u8 *key, const u8 hfunc); 699 int (*set_rss_tuple)(struct hnae3_handle *handle, 700 const struct ethtool_rxfh_fields *cmd); 701 int (*get_rss_tuple)(struct hnae3_handle *handle, 702 struct ethtool_rxfh_fields *cmd); 703 704 int (*get_tc_size)(struct hnae3_handle *handle); 705 706 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 707 struct hnae3_vector_info *vector_info); 708 int (*put_vector)(struct hnae3_handle *handle, int vector_num); 709 int (*map_ring_to_vector)(struct hnae3_handle *handle, 710 int vector_num, 711 struct hnae3_ring_chain_node *vr_chain); 712 int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 713 int vector_num, 714 struct hnae3_ring_chain_node *vr_chain); 715 716 int (*reset_queue)(struct hnae3_handle *handle); 717 u32 (*get_fw_version)(struct hnae3_handle *handle); 718 void (*get_mdix_mode)(struct hnae3_handle *handle, 719 u8 *tp_mdix_ctrl, u8 *tp_mdix); 720 721 int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 722 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 723 u16 vlan_id, bool is_kill); 724 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 725 u16 vlan, u8 qos, __be16 proto); 726 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 727 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 728 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 729 unsigned long *addr); 730 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 731 enum hnae3_reset_type rst_type); 732 void (*get_channels)(struct hnae3_handle *handle, 733 struct ethtool_channels *ch); 734 void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 735 u16 *alloc_tqps, u16 *max_rss_size); 736 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 737 bool rxfh_configured); 738 void (*get_flowctrl_adv)(struct hnae3_handle *handle, 739 u32 *flowctrl_adv); 740 int (*set_led_id)(struct hnae3_handle *handle, 741 enum ethtool_phys_id_state status); 742 void (*get_link_mode)(struct hnae3_handle *handle, 743 unsigned long *supported, 744 unsigned long *advertising); 745 int (*add_fd_entry)(struct hnae3_handle *handle, 746 struct ethtool_rxnfc *cmd); 747 int (*del_fd_entry)(struct hnae3_handle *handle, 748 struct ethtool_rxnfc *cmd); 749 int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 750 struct ethtool_rxnfc *cmd); 751 int (*get_fd_rule_info)(struct hnae3_handle *handle, 752 struct ethtool_rxnfc *cmd); 753 int (*get_fd_all_rules)(struct hnae3_handle *handle, 754 struct ethtool_rxnfc *cmd, u32 *rule_locs); 755 void (*enable_fd)(struct hnae3_handle *handle, bool enable); 756 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 757 u16 flow_id, struct flow_keys *fkeys); 758 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 759 bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 760 bool (*ae_dev_resetting)(struct hnae3_handle *handle); 761 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 762 int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 763 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 764 void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 765 int (*mac_connect_phy)(struct hnae3_handle *handle); 766 void (*mac_disconnect_phy)(struct hnae3_handle *handle); 767 int (*get_vf_config)(struct hnae3_handle *handle, int vf, 768 struct ifla_vf_info *ivf); 769 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 770 int link_state); 771 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 772 bool enable); 773 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 774 int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 775 int min_tx_rate, int max_tx_rate, bool force); 776 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 777 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 778 u32 len, u8 *data); 779 bool (*get_cmdq_stat)(struct hnae3_handle *handle); 780 int (*add_cls_flower)(struct hnae3_handle *handle, 781 struct flow_cls_offload *cls_flower, int tc); 782 int (*del_cls_flower)(struct hnae3_handle *handle, 783 struct flow_cls_offload *cls_flower); 784 bool (*cls_flower_active)(struct hnae3_handle *handle); 785 int (*get_phy_link_ksettings)(struct hnae3_handle *handle, 786 struct ethtool_link_ksettings *cmd); 787 int (*set_phy_link_ksettings)(struct hnae3_handle *handle, 788 const struct ethtool_link_ksettings *cmd); 789 bool (*set_tx_hwts_info)(struct hnae3_handle *handle, 790 struct sk_buff *skb); 791 void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb, 792 u32 nsec, u32 sec); 793 int (*get_ts_info)(struct hnae3_handle *handle, 794 struct kernel_ethtool_ts_info *info); 795 int (*get_link_diagnosis_info)(struct hnae3_handle *handle, 796 u32 *status_code); 797 void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs); 798 int (*get_dscp_prio)(struct hnae3_handle *handle, u8 dscp, 799 u8 *tc_map_mode, u8 *priority); 800 void (*get_wol)(struct hnae3_handle *handle, 801 struct ethtool_wolinfo *wol); 802 int (*set_wol)(struct hnae3_handle *handle, 803 struct ethtool_wolinfo *wol); 804 int (*dbg_get_read_func)(struct hnae3_handle *handle, 805 enum hnae3_dbg_cmd cmd, 806 read_func *func); 807 int (*hwtstamp_get)(struct hnae3_handle *handle, 808 struct kernel_hwtstamp_config *config); 809 int (*hwtstamp_set)(struct hnae3_handle *handle, 810 struct kernel_hwtstamp_config *config, 811 struct netlink_ext_ack *extack); 812}; 813 814struct hnae3_dcb_ops { 815 /* IEEE 802.1Qaz std */ 816 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 817 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 818 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 819 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 820 int (*ieee_setapp)(struct hnae3_handle *h, struct dcb_app *app); 821 int (*ieee_delapp)(struct hnae3_handle *h, struct dcb_app *app); 822 823 /* DCBX configuration */ 824 u8 (*getdcbx)(struct hnae3_handle *); 825 u8 (*setdcbx)(struct hnae3_handle *, u8); 826 827 int (*setup_tc)(struct hnae3_handle *handle, 828 struct tc_mqprio_qopt_offload *mqprio_qopt); 829}; 830 831struct hnae3_ae_algo { 832 const struct hnae3_ae_ops *ops; 833 struct list_head node; 834 const struct pci_device_id *pdev_id_table; 835}; 836 837#define HNAE3_INT_NAME_LEN 32 838#define HNAE3_ITR_COUNTDOWN_START 100 839 840#define HNAE3_MAX_TC 8 841#define HNAE3_MAX_USER_PRIO 8 842struct hnae3_tc_info { 843 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 844 u16 tqp_count[HNAE3_MAX_TC]; 845 u16 tqp_offset[HNAE3_MAX_TC]; 846 u8 max_tc; /* Total number of TCs */ 847 u8 num_tc; /* Total number of enabled TCs */ 848 bool mqprio_active; 849 bool mqprio_destroy; 850 bool dcb_ets_active; 851}; 852 853#define HNAE3_MAX_DSCP 64 854#define HNAE3_PRIO_ID_INVALID 0xff 855struct hnae3_knic_private_info { 856 struct net_device *netdev; /* Set by KNIC client when init instance */ 857 u16 rss_size; /* Allocated RSS queues */ 858 u16 req_rss_size; 859 u16 rx_buf_len; 860 u16 num_tx_desc; 861 u16 num_rx_desc; 862 u32 tx_spare_buf_size; 863 864 struct hnae3_tc_info tc_info; 865 u8 tc_map_mode; 866 u8 dscp_app_cnt; 867 u8 dscp_prio[HNAE3_MAX_DSCP]; 868 869 u16 num_tqps; /* total number of TQPs in this handle */ 870 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 871 const struct hnae3_dcb_ops *dcb_ops; 872 873 u16 int_rl_setting; 874 void __iomem *io_base; 875}; 876 877struct hnae3_roce_private_info { 878 struct net_device *netdev; 879 void __iomem *roce_io_base; 880 void __iomem *roce_mem_base; 881 int base_vector; 882 int num_vectors; 883 884 /* The below attributes defined for RoCE client, hnae3 gives 885 * initial values to them, and RoCE client can modify and use 886 * them. 887 */ 888 unsigned long reset_state; 889 unsigned long instance_state; 890 unsigned long state; 891}; 892 893#define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 894#define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 895#define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 896#define HNAE3_SUPPORT_VF BIT(3) 897#define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 898#define HNAE3_SUPPORT_EXTERNAL_LOOPBACK BIT(5) 899 900#define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 901#define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 902#define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 903#define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 904#define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 905#define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 906#define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 907 908enum hnae3_pflag { 909 HNAE3_PFLAG_LIMIT_PROMISC, 910 HNAE3_PFLAG_MAX 911}; 912 913struct hnae3_handle { 914 struct hnae3_client *client; 915 struct pci_dev *pdev; 916 void *priv; 917 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 918 u64 flags; /* Indicate the capabilities for this handle */ 919 920 union { 921 struct net_device *netdev; /* first member */ 922 struct hnae3_knic_private_info kinfo; 923 struct hnae3_roce_private_info rinfo; 924 }; 925 926 nodemask_t numa_node_mask; /* for multi-chip support */ 927 928 enum hnae3_port_base_vlan_state port_base_vlan_state; 929 930 u8 netdev_flags; 931 struct dentry *hnae3_dbgfs; 932 933 /* Network interface message level enabled bits */ 934 u32 msg_enable; 935 936 unsigned long supported_pflags; 937 unsigned long priv_flags; 938}; 939 940#define hnae3_set_field(origin, mask, shift, val) \ 941 do { \ 942 (origin) &= (~(mask)); \ 943 (origin) |= ((val) << (shift)) & (mask); \ 944 } while (0) 945#define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 946 947#define hnae3_set_bit(origin, shift, val) \ 948 hnae3_set_field(origin, 0x1 << (shift), shift, val) 949#define hnae3_get_bit(origin, shift) \ 950 hnae3_get_field(origin, 0x1 << (shift), shift) 951 952#define HNAE3_FORMAT_MAC_ADDR_LEN 18 953#define HNAE3_FORMAT_MAC_ADDR_OFFSET_0 0 954#define HNAE3_FORMAT_MAC_ADDR_OFFSET_4 4 955#define HNAE3_FORMAT_MAC_ADDR_OFFSET_5 5 956 957static inline void hnae3_format_mac_addr(char *format_mac_addr, 958 const u8 *mac_addr) 959{ 960 snprintf(format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, "%02x:**:**:**:%02x:%02x", 961 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0], 962 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4], 963 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]); 964} 965 966int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 967void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 968 969void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo); 970void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 971void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 972 973void hnae3_unregister_client(struct hnae3_client *client); 974int hnae3_register_client(struct hnae3_client *client); 975 976void hnae3_set_client_init_flag(struct hnae3_client *client, 977 struct hnae3_ae_dev *ae_dev, 978 unsigned int inited); 979void hnae3_acquire_unload_lock(void); 980void hnae3_release_unload_lock(void); 981#endif
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