hbg_common.h

  1/* SPDX-License-Identifier: GPL-2.0+ */
  2/* Copyright (c) 2024 Hisilicon Limited. */
  3
  4#ifndef __HBG_COMMON_H
  5#define __HBG_COMMON_H
  6
  7#include <linux/ethtool.h>
  8#include <linux/netdevice.h>
  9#include <linux/pci.h>
 10#include <net/page_pool/helpers.h>
 11#include "hbg_reg.h"
 12
 13#define HBG_STATUS_DISABLE		0x0
 14#define HBG_STATUS_ENABLE		0x1
 15#define HBG_RX_SKIP1			0x00
 16#define HBG_RX_SKIP2			0x01
 17#define HBG_VECTOR_NUM			4
 18#define HBG_PCU_CACHE_LINE_SIZE		32
 19#define HBG_TX_TIMEOUT_BUF_LEN		1024
 20#define HBG_RX_DESCR			0x01
 21#define HBG_NO_PHY			0xFF
 22
 23#define HBG_PACKET_HEAD_SIZE	((HBG_RX_SKIP1 + HBG_RX_SKIP2 + \
 24				  HBG_RX_DESCR) * HBG_PCU_CACHE_LINE_SIZE)
 25
 26enum hbg_dir {
 27	HBG_DIR_TX = 1 << 0,
 28	HBG_DIR_RX = 1 << 1,
 29	HBG_DIR_TX_RX = HBG_DIR_TX | HBG_DIR_RX,
 30};
 31
 32enum hbg_tx_state {
 33	HBG_TX_STATE_COMPLETE = 0, /* clear state, must fix to 0 */
 34	HBG_TX_STATE_START,
 35};
 36
 37enum hbg_nic_state {
 38	HBG_NIC_STATE_EVENT_HANDLING = 0,
 39	HBG_NIC_STATE_RESETTING,
 40	HBG_NIC_STATE_RESET_FAIL,
 41	HBG_NIC_STATE_NEED_RESET, /* trigger a reset in scheduled task */
 42	HBG_NIC_STATE_NP_LINK_FAIL,
 43};
 44
 45enum hbg_reset_type {
 46	HBG_RESET_TYPE_NONE = 0,
 47	HBG_RESET_TYPE_FLR,
 48	HBG_RESET_TYPE_FUNCTION,
 49};
 50
 51struct hbg_buffer {
 52	u32 state;
 53	dma_addr_t state_dma;
 54
 55	struct sk_buff *skb;
 56	dma_addr_t skb_dma;
 57	u32 skb_len;
 58
 59	struct page *page;
 60	void *page_addr;
 61	dma_addr_t page_dma;
 62	u32 page_size;
 63	u32 page_offset;
 64
 65	enum hbg_dir dir;
 66	struct hbg_ring *ring;
 67	struct hbg_priv *priv;
 68};
 69
 70struct hbg_ring {
 71	struct hbg_buffer *queue;
 72	dma_addr_t queue_dma;
 73
 74	union {
 75		u32 head;
 76		u32 ntc;
 77	};
 78	union {
 79		u32 tail;
 80		u32 ntu;
 81	};
 82	u32 len;
 83
 84	enum hbg_dir dir;
 85	struct hbg_priv *priv;
 86	struct napi_struct napi;
 87	char *tout_log_buf; /* tx timeout log buffer */
 88	struct page_pool *page_pool; /* only for rx */
 89};
 90
 91enum hbg_hw_event_type {
 92	HBG_HW_EVENT_NONE = 0,
 93	HBG_HW_EVENT_INIT, /* driver is loading */
 94	HBG_HW_EVENT_RESET,
 95	HBG_HW_EVENT_CORE_RESET,
 96};
 97
 98struct hbg_dev_specs {
 99	u32 mac_id;
100	struct sockaddr mac_addr;
101	u32 phy_addr;
102	u32 mdio_frequency;
103	u32 rx_fifo_num;
104	u32 tx_fifo_num;
105	u32 vlan_layers;
106	u32 max_mtu;
107	u32 min_mtu;
108	u32 uc_mac_num;
109
110	u32 max_frame_len;
111	u32 rx_buf_size;
112};
113
114struct hbg_irq_info {
115	const char *name;
116	u32 mask;
117	bool re_enable;
118	bool need_print;
119	bool need_reset;
120
121	void (*irq_handle)(struct hbg_priv *priv,
122			   const struct hbg_irq_info *info);
123};
124
125struct hbg_vector {
126	char name[HBG_VECTOR_NUM][32];
127
128	u64 *stats_array;
129	const struct hbg_irq_info *info_array;
130	u32 info_array_len;
131};
132
133struct hbg_mac {
134	struct mii_bus *mdio_bus;
135	struct phy_device *phydev;
136	u8 phy_addr;
137
138	u32 speed;
139	u32 duplex;
140	u32 autoneg;
141	u32 link_status;
142	u32 pause_autoneg;
143};
144
145struct hbg_mac_table_entry {
146	u8 addr[ETH_ALEN];
147};
148
149struct hbg_mac_filter {
150	struct hbg_mac_table_entry *mac_table;
151	u32 table_max_len;
152	bool enabled;
153};
154
155/* saved for restore after rest */
156struct hbg_user_def {
157	struct ethtool_pauseparam pause_param;
158};
159
160struct hbg_stats {
161	u64 rx_desc_drop;
162	u64 rx_desc_l2_err_cnt;
163	u64 rx_desc_pkt_len_err_cnt;
164	u64 rx_desc_l3l4_err_cnt;
165	u64 rx_desc_l3_wrong_head_cnt;
166	u64 rx_desc_l3_csum_err_cnt;
167	u64 rx_desc_l3_len_err_cnt;
168	u64 rx_desc_l3_zero_ttl_cnt;
169	u64 rx_desc_l3_other_cnt;
170	u64 rx_desc_l4_err_cnt;
171	u64 rx_desc_l4_wrong_head_cnt;
172	u64 rx_desc_l4_len_err_cnt;
173	u64 rx_desc_l4_csum_err_cnt;
174	u64 rx_desc_l4_zero_port_num_cnt;
175	u64 rx_desc_l4_other_cnt;
176	u64 rx_desc_frag_cnt;
177	u64 rx_desc_ip_ver_err_cnt;
178	u64 rx_desc_ipv4_pkt_cnt;
179	u64 rx_desc_ipv6_pkt_cnt;
180	u64 rx_desc_no_ip_pkt_cnt;
181	u64 rx_desc_ip_pkt_cnt;
182	u64 rx_desc_tcp_pkt_cnt;
183	u64 rx_desc_udp_pkt_cnt;
184	u64 rx_desc_vlan_pkt_cnt;
185	u64 rx_desc_icmp_pkt_cnt;
186	u64 rx_desc_arp_pkt_cnt;
187	u64 rx_desc_rarp_pkt_cnt;
188	u64 rx_desc_multicast_pkt_cnt;
189	u64 rx_desc_broadcast_pkt_cnt;
190	u64 rx_desc_ipsec_pkt_cnt;
191	u64 rx_desc_ip_opt_pkt_cnt;
192	u64 rx_desc_key_not_match_cnt;
193
194	u64 rx_octets_total_ok_cnt;
195	u64 rx_uc_pkt_cnt;
196	u64 rx_mc_pkt_cnt;
197	u64 rx_bc_pkt_cnt;
198	u64 rx_vlan_pkt_cnt;
199	u64 rx_octets_bad_cnt;
200	u64 rx_octets_total_filt_cnt;
201	u64 rx_filt_pkt_cnt;
202	u64 rx_trans_pkt_cnt;
203	u64 rx_framesize_64;
204	u64 rx_framesize_65_127;
205	u64 rx_framesize_128_255;
206	u64 rx_framesize_256_511;
207	u64 rx_framesize_512_1023;
208	u64 rx_framesize_1024_1518;
209	u64 rx_framesize_bt_1518;
210	u64 rx_fcs_error_cnt;
211	u64 rx_data_error_cnt;
212	u64 rx_align_error_cnt;
213	u64 rx_pause_macctl_frame_cnt;
214	u64 rx_unknown_macctl_frame_cnt;
215	/* crc ok, > max_frm_size, < 2max_frm_size */
216	u64 rx_frame_long_err_cnt;
217	/* crc fail, > max_frm_size, < 2max_frm_size */
218	u64 rx_jabber_err_cnt;
219	/* > 2max_frm_size */
220	u64 rx_frame_very_long_err_cnt;
221	/* < 64byte, >= short_runts_thr */
222	u64 rx_frame_runt_err_cnt;
223	/* < short_runts_thr */
224	u64 rx_frame_short_err_cnt;
225	/* PCU: dropped when the RX FIFO is full.*/
226	u64 rx_overflow_cnt;
227	/* GMAC: the count of overflows of the RX FIFO */
228	u64 rx_overrun_cnt;
229	/* PCU: the count of buffer alloc errors in RX */
230	u64 rx_bufrq_err_cnt;
231	/* PCU: the count of write descriptor errors in RX */
232	u64 rx_we_err_cnt;
233	/* GMAC: the count of pkts that contain PAD but length is not 64 */
234	u64 rx_lengthfield_err_cnt;
235	u64 rx_fail_comma_cnt;
236
237	u64 rx_dma_err_cnt;
238	u64 rx_fifo_less_empty_thrsld_cnt;
239
240	u64 tx_octets_total_ok_cnt;
241	u64 tx_uc_pkt_cnt;
242	u64 tx_mc_pkt_cnt;
243	u64 tx_bc_pkt_cnt;
244	u64 tx_vlan_pkt_cnt;
245	u64 tx_octets_bad_cnt;
246	u64 tx_trans_pkt_cnt;
247	u64 tx_pause_frame_cnt;
248	u64 tx_framesize_64;
249	u64 tx_framesize_65_127;
250	u64 tx_framesize_128_255;
251	u64 tx_framesize_256_511;
252	u64 tx_framesize_512_1023;
253	u64 tx_framesize_1024_1518;
254	u64 tx_framesize_bt_1518;
255	/* GMAC: the count of times that frames fail to be transmitted
256	 *       due to internal errors.
257	 */
258	u64 tx_underrun_err_cnt;
259	u64 tx_add_cs_fail_cnt;
260	/* PCU: the count of buffer free errors in TX */
261	u64 tx_bufrl_err_cnt;
262	u64 tx_crc_err_cnt;
263	u64 tx_drop_cnt;
264	u64 tx_excessive_length_drop_cnt;
265
266	u64 tx_timeout_cnt;
267	u64 tx_dma_err_cnt;
268
269	u64 np_link_fail_cnt;
270	u64 reset_fail_cnt;
271};
272
273struct hbg_priv {
274	struct net_device *netdev;
275	struct pci_dev *pdev;
276	u8 __iomem *io_base;
277	struct hbg_dev_specs dev_specs;
278	unsigned long state;
279	struct hbg_mac mac;
280	struct hbg_vector vectors;
281	struct hbg_ring tx_ring;
282	struct hbg_ring rx_ring;
283	struct hbg_mac_filter filter;
284	enum hbg_reset_type reset_type;
285	struct hbg_user_def user_def;
286	struct hbg_stats stats;
287	unsigned long last_update_stats_time;
288	struct delayed_work service_task;
289};
290
291void hbg_err_reset_task_schedule(struct hbg_priv *priv);
292void hbg_np_link_fail_task_schedule(struct hbg_priv *priv);
293
294#endif