ucc_geth.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
   4 *
   5 * Author: Shlomi Gridish <gridish@freescale.com>
   6 *
   7 * Description:
   8 * Internal header file for UCC Gigabit Ethernet unit routines.
   9 *
  10 * Changelog:
  11 * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  12 * - Rearrange code and style fixes
  13 */
  14#ifndef __UCC_GETH_H__
  15#define __UCC_GETH_H__
  16
  17#include <linux/kernel.h>
  18#include <linux/list.h>
  19#include <linux/phylink.h>
  20#include <linux/if_ether.h>
  21
  22#include <soc/fsl/qe/immap_qe.h>
  23#include <soc/fsl/qe/qe.h>
  24
  25#include <soc/fsl/qe/ucc.h>
  26#include <soc/fsl/qe/ucc_fast.h>
  27
  28#define DRV_DESC "QE UCC Gigabit Ethernet Controller"
  29#define DRV_NAME "ucc_geth"
  30
  31#define NUM_TX_QUEUES                   8
  32#define NUM_RX_QUEUES                   8
  33#define NUM_BDS_IN_PREFETCHED_BDS       4
  34#define TX_IP_OFFSET_ENTRY_MAX          8
  35#define NUM_OF_PADDRS                   4
  36#define ENET_INIT_PARAM_MAX_ENTRIES_RX  9
  37#define ENET_INIT_PARAM_MAX_ENTRIES_TX  8
  38
  39struct ucc_geth {
  40	struct ucc_fast uccf;
  41	u8 res0[0x100 - sizeof(struct ucc_fast)];
  42
  43	u32 maccfg1;		/* mac configuration reg. 1 */
  44	u32 maccfg2;		/* mac configuration reg. 2 */
  45	u32 ipgifg;		/* interframe gap reg.  */
  46	u32 hafdup;		/* half-duplex reg.  */
  47	u8 res1[0x10];
  48	u8 miimng[0x18];	/* MII management structure moved to _mii.h */
  49	u32 ifctl;		/* interface control reg */
  50	u32 ifstat;		/* interface statux reg */
  51	u32 macstnaddr1;	/* mac station address part 1 reg */
  52	u32 macstnaddr2;	/* mac station address part 2 reg */
  53	u8 res2[0x8];
  54	u32 uempr;		/* UCC Ethernet Mac parameter reg */
  55	u32 utbipar;		/* UCC tbi address reg */
  56	u16 uescr;		/* UCC Ethernet statistics control reg */
  57	u8 res3[0x180 - 0x15A];
  58	u32 tx64;		/* Total number of frames (including bad
  59				   frames) transmitted that were exactly of the
  60				   minimal length (64 for un tagged, 68 for
  61				   tagged, or with length exactly equal to the
  62				   parameter MINLength */
  63	u32 tx127;		/* Total number of frames (including bad
  64				   frames) transmitted that were between
  65				   MINLength (Including FCS length==4) and 127
  66				   octets */
  67	u32 tx255;		/* Total number of frames (including bad
  68				   frames) transmitted that were between 128
  69				   (Including FCS length==4) and 255 octets */
  70	u32 rx64;		/* Total number of frames received including
  71				   bad frames that were exactly of the mninimal
  72				   length (64 bytes) */
  73	u32 rx127;		/* Total number of frames (including bad
  74				   frames) received that were between MINLength
  75				   (Including FCS length==4) and 127 octets */
  76	u32 rx255;		/* Total number of frames (including bad
  77				   frames) received that were between 128
  78				   (Including FCS length==4) and 255 octets */
  79	u32 txok;		/* Total number of octets residing in frames
  80				   that where involved in successful
  81				   transmission */
  82	u16 txcf;		/* Total number of PAUSE control frames
  83				   transmitted by this MAC */
  84	u8 res4[0x2];
  85	u32 tmca;		/* Total number of frames that were transmitted
  86				   successfully with the group address bit set
  87				   that are not broadcast frames */
  88	u32 tbca;		/* Total number of frames transmitted
  89				   successfully that had destination address
  90				   field equal to the broadcast address */
  91	u32 rxfok;		/* Total number of frames received OK */
  92	u32 rxbok;		/* Total number of octets received OK */
  93	u32 rbyt;		/* Total number of octets received including
  94				   octets in bad frames. Must be implemented in
  95				   HW because it includes octets in frames that
  96				   never even reach the UCC */
  97	u32 rmca;		/* Total number of frames that were received
  98				   successfully with the group address bit set
  99				   that are not broadcast frames */
 100	u32 rbca;		/* Total number of frames received successfully
 101				   that had destination address equal to the
 102				   broadcast address */
 103	u32 scar;		/* Statistics carry register */
 104	u32 scam;		/* Statistics caryy mask register */
 105	u8 res5[0x200 - 0x1c4];
 106} __packed;
 107
 108/* UCC GETH TEMODR Register */
 109#define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100	/* enable Tx statistics
 110							 */
 111#define TEMODER_SCHEDULER_ENABLE                0x2000	/* enable scheduler */
 112#define TEMODER_IP_CHECKSUM_GENERATE            0x0400	/* generate IPv4
 113							   checksums */
 114#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200	/* enable performance
 115							   optimization
 116							   enhancement (mode1) */
 117#define TEMODER_RMON_STATISTICS                 0x0100	/* enable tx statistics
 118							 */
 119#define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15)	/* Number of queues <<
 120							   shift */
 121
 122/* UCC GETH TEMODR Register */
 123#define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000	/* enable Rx
 124								   statistics */
 125#define REMODER_RX_EXTENDED_FEATURES            0x80000000	/* enable
 126								   extended
 127								   features */
 128#define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 )	/* vlan operation
 129							   tagged << shift */
 130#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)	/* vlan operation non
 131							   tagged << shift */
 132#define REMODER_RX_QOS_MODE_SHIFT               (31-15)	/* rx QoS mode << shift
 133							 */
 134#define REMODER_RMON_STATISTICS                 0x00001000	/* enable rx
 135								   statistics */
 136#define REMODER_RX_EXTENDED_FILTERING           0x00000800	/* extended
 137								   filtering
 138								   vs.
 139								   mpc82xx-like
 140								   filtering */
 141#define REMODER_NUM_OF_QUEUES_SHIFT             (31-23)	/* Number of queues <<
 142							   shift */
 143#define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008	/* enable
 144								   dynamic max
 145								   frame length
 146								 */
 147#define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004	/* enable
 148								   dynamic min
 149								   frame length
 150								 */
 151#define REMODER_IP_CHECKSUM_CHECK               0x00000002	/* check IPv4
 152								   checksums */
 153#define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001	/* align ip
 154								   address to
 155								   4-byte
 156								   boundary */
 157
 158/* UCC GETH Event Register */
 159#define UCCE_TXB   (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
 160		    UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
 161		    UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
 162		    UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
 163
 164#define UCCE_RXB   (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
 165		    UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
 166		    UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
 167		    UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
 168
 169#define UCCE_RXF   (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
 170		    UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
 171		    UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
 172		    UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
 173
 174#define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
 175		    UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
 176		    UCC_GETH_UCCE_RXC  | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
 177
 178#define UCCE_RX_EVENTS  (UCCE_RXF | UCC_GETH_UCCE_BSY)
 179#define UCCE_TX_EVENTS	(UCCE_TXB | UCC_GETH_UCCE_TXE)
 180
 181/* TBI defines */
 182#define	ENET_TBI_MII_CR		0x00	/* Control */
 183#define	ENET_TBI_MII_SR		0x01	/* Status */
 184#define	ENET_TBI_MII_ANA	0x04	/* AN advertisement */
 185#define	ENET_TBI_MII_ANLPBPA	0x05	/* AN link partner base page ability */
 186#define	ENET_TBI_MII_ANEX	0x06	/* AN expansion */
 187#define	ENET_TBI_MII_ANNPT	0x07	/* AN next page transmit */
 188#define	ENET_TBI_MII_ANLPANP	0x08	/* AN link partner ability next page */
 189#define	ENET_TBI_MII_EXST	0x0F	/* Extended status */
 190#define	ENET_TBI_MII_JD		0x10	/* Jitter diagnostics */
 191#define	ENET_TBI_MII_TBICON	0x11	/* TBI control */
 192
 193/* TBI MDIO register bit fields*/
 194#define TBISR_LSTATUS          0x0004
 195#define TBICON_CLK_SELECT       0x0020
 196#define TBIANA_ASYMMETRIC_PAUSE 0x0100
 197#define TBIANA_SYMMETRIC_PAUSE  0x0080
 198#define TBIANA_HALF_DUPLEX      0x0040
 199#define TBIANA_FULL_DUPLEX      0x0020
 200#define TBICR_PHY_RESET         0x8000
 201#define TBICR_ANEG_ENABLE       0x1000
 202#define TBICR_RESTART_ANEG      0x0200
 203#define TBICR_FULL_DUPLEX       0x0100
 204#define TBICR_SPEED1_SET        0x0040
 205
 206#define TBIANA_SETTINGS ( \
 207		TBIANA_ASYMMETRIC_PAUSE \
 208		| TBIANA_SYMMETRIC_PAUSE \
 209		| TBIANA_FULL_DUPLEX \
 210		)
 211#define TBICR_SETTINGS ( \
 212		TBICR_PHY_RESET \
 213		| TBICR_ANEG_ENABLE \
 214		| TBICR_FULL_DUPLEX \
 215		| TBICR_SPEED1_SET \
 216		)
 217
 218/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
 219#define MACCFG1_FLOW_RX                         0x00000020	/* Flow Control
 220								   Rx */
 221#define MACCFG1_FLOW_TX                         0x00000010	/* Flow Control
 222								   Tx */
 223#define MACCFG1_ENABLE_SYNCHED_RX               0x00000008	/* Rx Enable
 224								   synchronized
 225								   to Rx stream
 226								 */
 227#define MACCFG1_ENABLE_RX                       0x00000004	/* Enable Rx */
 228#define MACCFG1_ENABLE_SYNCHED_TX               0x00000002	/* Tx Enable
 229								   synchronized
 230								   to Tx stream
 231								 */
 232#define MACCFG1_ENABLE_TX                       0x00000001	/* Enable Tx */
 233
 234/* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
 235#define MACCFG2_PREL_SHIFT                      (31 - 19)	/* Preamble
 236								   Length <<
 237								   shift */
 238#define MACCFG2_PREL_MASK                       0x0000f000	/* Preamble
 239								   Length mask */
 240#define MACCFG2_SRP                             0x00000080	/* Soft Receive
 241								   Preamble */
 242#define MACCFG2_STP                             0x00000040	/* Soft
 243								   Transmit
 244								   Preamble */
 245#define MACCFG2_RESERVED_1                      0x00000020	/* Reserved -
 246								   must be set
 247								   to 1 */
 248#define MACCFG2_LC                              0x00000010	/* Length Check
 249								 */
 250#define MACCFG2_MPE                             0x00000008	/* Magic packet
 251								   detect */
 252#define MACCFG2_FDX                             0x00000001	/* Full Duplex */
 253#define MACCFG2_FDX_MASK                        0x00000001	/* Full Duplex
 254								   mask */
 255#define MACCFG2_PAD_CRC                         0x00000004
 256#define MACCFG2_CRC_EN                          0x00000002
 257#define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000	/* Neither
 258								   Padding
 259								   short frames
 260								   nor CRC */
 261#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002	/* Append CRC
 262								   only */
 263#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
 264#define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100	/* nibble mode
 265								   (MII/RMII/RGMII
 266								   10/100bps) */
 267#define MACCFG2_INTERFACE_MODE_BYTE             0x00000200	/* byte mode
 268								   (GMII/TBI/RTB/RGMII
 269								   1000bps ) */
 270#define MACCFG2_INTERFACE_MODE_MASK             0x00000300	/* mask
 271								   covering all
 272								   relevant
 273								   bits */
 274
 275/* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
 276#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 -  7)	/* Non
 277								   back-to-back
 278								   inter frame
 279								   gap part 1.
 280								   << shift */
 281#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)	/* Non
 282								   back-to-back
 283								   inter frame
 284								   gap part 2.
 285								   << shift */
 286#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT    (31 - 23)	/* Mimimum IFG
 287								   Enforcement
 288								   << shift */
 289#define IPGIFG_BACK_TO_BACK_IFG_SHIFT           (31 - 31)	/* back-to-back
 290								   inter frame
 291								   gap << shift
 292								 */
 293#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX   127	/* Non back-to-back
 294							   inter frame gap part
 295							   1. max val */
 296#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX   127	/* Non back-to-back
 297							   inter frame gap part
 298							   2. max val */
 299#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX      255	/* Mimimum IFG
 300							   Enforcement max val */
 301#define IPGIFG_BACK_TO_BACK_IFG_MAX             127	/* back-to-back inter
 302							   frame gap max val */
 303#define IPGIFG_NBTB_CS_IPG_MASK                 0x7F000000
 304#define IPGIFG_NBTB_IPG_MASK                    0x007F0000
 305#define IPGIFG_MIN_IFG_MASK                     0x0000FF00
 306#define IPGIFG_BTB_IPG_MASK                     0x0000007F
 307
 308/* UCC GETH HAFDUP (Half Duplex Register) */
 309#define HALFDUP_ALT_BEB_TRUNCATION_SHIFT        (31 - 11)	/* Alternate
 310								   Binary
 311								   Exponential
 312								   Backoff
 313								   Truncation
 314								   << shift */
 315#define HALFDUP_ALT_BEB_TRUNCATION_MAX          0xf	/* Alternate Binary
 316							   Exponential Backoff
 317							   Truncation max val */
 318#define HALFDUP_ALT_BEB                         0x00080000	/* Alternate
 319								   Binary
 320								   Exponential
 321								   Backoff */
 322#define HALFDUP_BACK_PRESSURE_NO_BACKOFF        0x00040000	/* Back
 323								   pressure no
 324								   backoff */
 325#define HALFDUP_NO_BACKOFF                      0x00020000	/* No Backoff */
 326#define HALFDUP_EXCESSIVE_DEFER                 0x00010000	/* Excessive
 327								   Defer */
 328#define HALFDUP_MAX_RETRANSMISSION_SHIFT        (31 - 19)	/* Maximum
 329								   Retransmission
 330								   << shift */
 331#define HALFDUP_MAX_RETRANSMISSION_MAX          0xf	/* Maximum
 332							   Retransmission max
 333							   val */
 334#define HALFDUP_COLLISION_WINDOW_SHIFT          (31 - 31)	/* Collision
 335								   Window <<
 336								   shift */
 337#define HALFDUP_COLLISION_WINDOW_MAX            0x3f	/* Collision Window max
 338							   val */
 339#define HALFDUP_ALT_BEB_TR_MASK                 0x00F00000
 340#define HALFDUP_RETRANS_MASK                    0x0000F000
 341#define HALFDUP_COL_WINDOW_MASK                 0x0000003F
 342
 343/* UCC GETH UCCS (Ethernet Status Register) */
 344#define UCCS_BPR                                0x02	/* Back pressure (in
 345							   half duplex mode) */
 346#define UCCS_PAU                                0x02	/* Pause state (in full
 347							   duplex mode) */
 348#define UCCS_MPD                                0x01	/* Magic Packet
 349							   Detected */
 350
 351/* UCC GETH IFSTAT (Interface Status Register) */
 352#define IFSTAT_EXCESS_DEFER                     0x00000200	/* Excessive
 353								   transmission
 354								   defer */
 355
 356/* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
 357#define MACSTNADDR1_OCTET_6_SHIFT               (31 -  7)	/* Station
 358								   address 6th
 359								   octet <<
 360								   shift */
 361#define MACSTNADDR1_OCTET_5_SHIFT               (31 - 15)	/* Station
 362								   address 5th
 363								   octet <<
 364								   shift */
 365#define MACSTNADDR1_OCTET_4_SHIFT               (31 - 23)	/* Station
 366								   address 4th
 367								   octet <<
 368								   shift */
 369#define MACSTNADDR1_OCTET_3_SHIFT               (31 - 31)	/* Station
 370								   address 3rd
 371								   octet <<
 372								   shift */
 373
 374/* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
 375#define MACSTNADDR2_OCTET_2_SHIFT               (31 -  7)	/* Station
 376								   address 2nd
 377								   octet <<
 378								   shift */
 379#define MACSTNADDR2_OCTET_1_SHIFT               (31 - 15)	/* Station
 380								   address 1st
 381								   octet <<
 382								   shift */
 383
 384/* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
 385#define UEMPR_PAUSE_TIME_VALUE_SHIFT            (31 - 15)	/* Pause time
 386								   value <<
 387								   shift */
 388#define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT   (31 - 31)	/* Extended
 389								   pause time
 390								   value <<
 391								   shift */
 392
 393/* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
 394#define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)	/* Phy address
 395								   << shift */
 396#define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f	/* Phy address
 397								   mask */
 398
 399/* UCC GETH UESCR (Ethernet Statistics Control Register) */
 400#define UESCR_AUTOZ                             0x8000	/* Automatically zero
 401							   addressed
 402							   statistical counter
 403							   values */
 404#define UESCR_CLRCNT                            0x4000	/* Clear all statistics
 405							   counters */
 406#define UESCR_MAXCOV_SHIFT                      (15 -  7)	/* Max
 407								   Coalescing
 408								   Value <<
 409								   shift */
 410#define UESCR_SCOV_SHIFT                        (15 - 15)	/* Status
 411								   Coalescing
 412								   Value <<
 413								   shift */
 414
 415/* UCC GETH UDSR (Data Synchronization Register) */
 416#define UDSR_MAGIC                              0x067E
 417
 418struct ucc_geth_thread_data_tx {
 419	u8 res0[104];
 420} __packed;
 421
 422struct ucc_geth_thread_data_rx {
 423	u8 res0[40];
 424} __packed;
 425
 426/* Send Queue Queue-Descriptor */
 427struct ucc_geth_send_queue_qd {
 428	u32 bd_ring_base;	/* pointer to BD ring base address */
 429	u8 res0[0x8];
 430	u32 last_bd_completed_address;/* initialize to last entry in BD ring */
 431	u8 res1[0x30];
 432} __packed;
 433
 434struct ucc_geth_send_queue_mem_region {
 435	struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
 436} __packed;
 437
 438struct ucc_geth_thread_tx_pram {
 439	u8 res0[64];
 440} __packed;
 441
 442struct ucc_geth_thread_rx_pram {
 443	u8 res0[128];
 444} __packed;
 445
 446#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64
 447#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64
 448#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96
 449
 450struct ucc_geth_scheduler {
 451	u16 cpucount0;		/* CPU packet counter */
 452	u16 cpucount1;		/* CPU packet counter */
 453	u16 cecount0;		/* QE packet counter */
 454	u16 cecount1;		/* QE packet counter */
 455	u16 cpucount2;		/* CPU packet counter */
 456	u16 cpucount3;		/* CPU packet counter */
 457	u16 cecount2;		/* QE packet counter */
 458	u16 cecount3;		/* QE packet counter */
 459	u16 cpucount4;		/* CPU packet counter */
 460	u16 cpucount5;		/* CPU packet counter */
 461	u16 cecount4;		/* QE packet counter */
 462	u16 cecount5;		/* QE packet counter */
 463	u16 cpucount6;		/* CPU packet counter */
 464	u16 cpucount7;		/* CPU packet counter */
 465	u16 cecount6;		/* QE packet counter */
 466	u16 cecount7;		/* QE packet counter */
 467	u32 weightstatus[NUM_TX_QUEUES];	/* accumulated weight factor */
 468	u32 rtsrshadow;		/* temporary variable handled by QE */
 469	u32 time;		/* temporary variable handled by QE */
 470	u32 ttl;		/* temporary variable handled by QE */
 471	u32 mblinterval;	/* max burst length interval */
 472	u16 nortsrbytetime;	/* normalized value of byte time in tsr units */
 473	u8 fracsiz;		/* radix 2 log value of denom. of
 474				   NorTSRByteTime */
 475	u8 res0[1];
 476	u8 strictpriorityq;	/* Strict Priority Mask register */
 477	u8 txasap;		/* Transmit ASAP register */
 478	u8 extrabw;		/* Extra BandWidth register */
 479	u8 oldwfqmask;		/* temporary variable handled by QE */
 480	u8 weightfactor[NUM_TX_QUEUES];
 481				      /**< weight factor for queues   */
 482	u32 minw;		/* temporary variable handled by QE */
 483	u8 res1[0x70 - 0x64];
 484} __packed;
 485
 486struct ucc_geth_tx_firmware_statistics_pram {
 487	u32 sicoltx;		/* single collision */
 488	u32 mulcoltx;		/* multiple collision */
 489	u32 latecoltxfr;	/* late collision */
 490	u32 frabortduecol;	/* frames aborted due to transmit collision */
 491	u32 frlostinmactxer;	/* frames lost due to internal MAC error
 492				   transmission that are not counted on any
 493				   other counter */
 494	u32 carriersenseertx;	/* carrier sense error */
 495	u32 frtxok;		/* frames transmitted OK */
 496	u32 txfrexcessivedefer;	/* frames with defferal time greater than
 497				   specified threshold */
 498	u32 txpkts256;		/* total packets (including bad) between 256
 499				   and 511 octets */
 500	u32 txpkts512;		/* total packets (including bad) between 512
 501				   and 1023 octets */
 502	u32 txpkts1024;		/* total packets (including bad) between 1024
 503				   and 1518 octets */
 504	u32 txpktsjumbo;	/* total packets (including bad) between 1024
 505				   and MAXLength octets */
 506} __packed;
 507
 508struct ucc_geth_rx_firmware_statistics_pram {
 509	u32 frrxfcser;		/* frames with crc error */
 510	u32 fraligner;		/* frames with alignment error */
 511	u32 inrangelenrxer;	/* in range length error */
 512	u32 outrangelenrxer;	/* out of range length error */
 513	u32 frtoolong;		/* frame too long */
 514	u32 runt;		/* runt */
 515	u32 verylongevent;	/* very long event */
 516	u32 symbolerror;	/* symbol error */
 517	u32 dropbsy;		/* drop because of BD not ready */
 518	u8 res0[0x8];
 519	u32 mismatchdrop;	/* drop because of MAC filtering (e.g. address
 520				   or type mismatch) */
 521	u32 underpkts;		/* total frames less than 64 octets */
 522	u32 pkts256;		/* total frames (including bad) between 256 and
 523				   511 octets */
 524	u32 pkts512;		/* total frames (including bad) between 512 and
 525				   1023 octets */
 526	u32 pkts1024;		/* total frames (including bad) between 1024
 527				   and 1518 octets */
 528	u32 pktsjumbo;		/* total frames (including bad) between 1024
 529				   and MAXLength octets */
 530	u32 frlossinmacer;	/* frames lost because of internal MAC error
 531				   that is not counted in any other counter */
 532	u32 pausefr;		/* pause frames */
 533	u8 res1[0x4];
 534	u32 removevlan;		/* total frames that had their VLAN tag removed
 535				 */
 536	u32 replacevlan;	/* total frames that had their VLAN tag
 537				   replaced */
 538	u32 insertvlan;		/* total frames that had their VLAN tag
 539				   inserted */
 540} __packed;
 541
 542struct ucc_geth_rx_interrupt_coalescing_entry {
 543	u32 interruptcoalescingmaxvalue;	/* interrupt coalescing max
 544						   value */
 545	u32 interruptcoalescingcounter;	/* interrupt coalescing counter,
 546					   initialize to
 547					   interruptcoalescingmaxvalue */
 548} __packed;
 549
 550struct ucc_geth_rx_interrupt_coalescing_table {
 551	struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
 552				       /**< interrupt coalescing entry */
 553} __packed;
 554
 555struct ucc_geth_rx_prefetched_bds {
 556	struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS];	/* prefetched bd */
 557} __packed;
 558
 559struct ucc_geth_rx_bd_queues_entry {
 560	u32 bdbaseptr;		/* BD base pointer */
 561	u32 bdptr;		/* BD pointer */
 562	u32 externalbdbaseptr;	/* external BD base pointer */
 563	u32 externalbdptr;	/* external BD pointer */
 564} __packed;
 565
 566struct ucc_geth_tx_global_pram {
 567	u16 temoder;
 568	u8 res0[0x38 - 0x02];
 569	u32 sqptr;		/* a base pointer to send queue memory region */
 570	u32 schedulerbasepointer;	/* a base pointer to scheduler memory
 571					   region */
 572	u32 txrmonbaseptr;	/* base pointer to Tx RMON statistics counter */
 573	u32 tstate;		/* tx internal state. High byte contains
 574				   function code */
 575	u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
 576	u32 vtagtable[0x8];	/* 8 4-byte VLAN tags */
 577	u32 tqptr;		/* a base pointer to the Tx Queues Memory
 578				   Region */
 579	u8 res2[0x78 - 0x74];
 580	u64 snums_en;
 581	u32 l2l3baseptr;	/* top byte consists of a few other bit fields */
 582
 583	u16 mtu[8];
 584	u8 res3[0xa8 - 0x94];
 585	u32 wrrtablebase;	/* top byte is reserved */
 586	u8 res4[0xc0 - 0xac];
 587} __packed;
 588
 589/* structure representing Extended Filtering Global Parameters in PRAM */
 590struct ucc_geth_exf_global_pram {
 591	u32 l2pcdptr;		/* individual address filter, high */
 592	u8 res0[0x10 - 0x04];
 593} __packed;
 594
 595struct ucc_geth_rx_global_pram {
 596	u32 remoder;		/* ethernet mode reg. */
 597	u32 rqptr;		/* base pointer to the Rx Queues Memory Region*/
 598	u32 res0[0x1];
 599	u8 res1[0x20 - 0xC];
 600	u16 typeorlen;		/* cutoff point less than which, type/len field
 601				   is considered length */
 602	u8 res2[0x1];
 603	u8 rxgstpack;		/* acknowledgement on GRACEFUL STOP RX command*/
 604	u32 rxrmonbaseptr;	/* base pointer to Rx RMON statistics counter */
 605	u8 res3[0x30 - 0x28];
 606	u32 intcoalescingptr;	/* Interrupt coalescing table pointer */
 607	u8 res4[0x36 - 0x34];
 608	u8 rstate;		/* rx internal state. High byte contains
 609				   function code */
 610	u8 res5[0x46 - 0x37];
 611	u16 mrblr;		/* max receive buffer length reg. */
 612	u32 rbdqptr;		/* base pointer to RxBD parameter table
 613				   description */
 614	u16 mflr;		/* max frame length reg. */
 615	u16 minflr;		/* min frame length reg. */
 616	u16 maxd1;		/* max dma1 length reg. */
 617	u16 maxd2;		/* max dma2 length reg. */
 618	u32 ecamptr;		/* external CAM address */
 619	u32 l2qt;		/* VLAN priority mapping table. */
 620	u32 l3qt[0x8];		/* IP priority mapping table. */
 621	u16 vlantype;		/* vlan type */
 622	u16 vlantci;		/* default vlan tci */
 623	u8 addressfiltering[64];	/* address filtering data structure */
 624	u32 exfGlobalParam;	/* base address for extended filtering global
 625				   parameters */
 626	u8 res6[0x100 - 0xC4];	/* Initialize to zero */
 627} __packed;
 628
 629#define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 630
 631/* structure representing InitEnet command */
 632struct ucc_geth_init_pram {
 633	u8 resinit1;
 634	u8 resinit2;
 635	u8 resinit3;
 636	u8 resinit4;
 637	u16 resinit5;
 638	u8 res1[0x1];
 639	u8 largestexternallookupkeysize;
 640	u32 rgftgfrxglobal;
 641	u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX];	/* rx threads */
 642	u8 res2[0x38 - 0x30];
 643	u32 txglobal;		/* tx global */
 644	u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];	/* tx threads */
 645	u8 res3[0x1];
 646} __packed;
 647
 648#define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
 649#define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
 650
 651#define ENET_INIT_PARAM_RISC_MASK               0x0000003f
 652#define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
 653#define ENET_INIT_PARAM_SNUM_MASK               0xff000000
 654#define ENET_INIT_PARAM_SNUM_SHIFT              24
 655
 656#define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x06
 657#define ENET_INIT_PARAM_MAGIC_RES_INIT2         0x30
 658#define ENET_INIT_PARAM_MAGIC_RES_INIT3         0xff
 659#define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x00
 660#define ENET_INIT_PARAM_MAGIC_RES_INIT5         0x0400
 661
 662/* structure representing 82xx Address Filtering Enet Address in PRAM */
 663struct ucc_geth_82xx_enet_address {
 664	u8 res1[0x2];
 665	u16 h;			/* address (MSB) */
 666	u16 m;			/* address */
 667	u16 l;			/* address (LSB) */
 668} __packed;
 669
 670/* structure representing 82xx Address Filtering PRAM */
 671struct ucc_geth_82xx_address_filtering_pram {
 672	u32 iaddr_h;		/* individual address filter, high */
 673	u32 iaddr_l;		/* individual address filter, low */
 674	u32 gaddr_h;		/* group address filter, high */
 675	u32 gaddr_l;		/* group address filter, low */
 676	struct ucc_geth_82xx_enet_address __iomem taddr;
 677	struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
 678	u8 res0[0x40 - 0x38];
 679} __packed;
 680
 681/* GETH Tx firmware statistics structure, used when calling
 682   UCC_GETH_GetStatistics. */
 683struct ucc_geth_tx_firmware_statistics {
 684	u32 sicoltx;		/* single collision */
 685	u32 mulcoltx;		/* multiple collision */
 686	u32 latecoltxfr;	/* late collision */
 687	u32 frabortduecol;	/* frames aborted due to transmit collision */
 688	u32 frlostinmactxer;	/* frames lost due to internal MAC error
 689				   transmission that are not counted on any
 690				   other counter */
 691	u32 carriersenseertx;	/* carrier sense error */
 692	u32 frtxok;		/* frames transmitted OK */
 693	u32 txfrexcessivedefer;	/* frames with defferal time greater than
 694				   specified threshold */
 695	u32 txpkts256;		/* total packets (including bad) between 256
 696				   and 511 octets */
 697	u32 txpkts512;		/* total packets (including bad) between 512
 698				   and 1023 octets */
 699	u32 txpkts1024;		/* total packets (including bad) between 1024
 700				   and 1518 octets */
 701	u32 txpktsjumbo;	/* total packets (including bad) between 1024
 702				   and MAXLength octets */
 703} __packed;
 704
 705/* GETH Rx firmware statistics structure, used when calling
 706   UCC_GETH_GetStatistics. */
 707struct ucc_geth_rx_firmware_statistics {
 708	u32 frrxfcser;		/* frames with crc error */
 709	u32 fraligner;		/* frames with alignment error */
 710	u32 inrangelenrxer;	/* in range length error */
 711	u32 outrangelenrxer;	/* out of range length error */
 712	u32 frtoolong;		/* frame too long */
 713	u32 runt;		/* runt */
 714	u32 verylongevent;	/* very long event */
 715	u32 symbolerror;	/* symbol error */
 716	u32 dropbsy;		/* drop because of BD not ready */
 717	u8 res0[0x8];
 718	u32 mismatchdrop;	/* drop because of MAC filtering (e.g. address
 719				   or type mismatch) */
 720	u32 underpkts;		/* total frames less than 64 octets */
 721	u32 pkts256;		/* total frames (including bad) between 256 and
 722				   511 octets */
 723	u32 pkts512;		/* total frames (including bad) between 512 and
 724				   1023 octets */
 725	u32 pkts1024;		/* total frames (including bad) between 1024
 726				   and 1518 octets */
 727	u32 pktsjumbo;		/* total frames (including bad) between 1024
 728				   and MAXLength octets */
 729	u32 frlossinmacer;	/* frames lost because of internal MAC error
 730				   that is not counted in any other counter */
 731	u32 pausefr;		/* pause frames */
 732	u8 res1[0x4];
 733	u32 removevlan;		/* total frames that had their VLAN tag removed
 734				 */
 735	u32 replacevlan;	/* total frames that had their VLAN tag
 736				   replaced */
 737	u32 insertvlan;		/* total frames that had their VLAN tag
 738				   inserted */
 739} __packed;
 740
 741/* GETH hardware statistics structure, used when calling
 742   UCC_GETH_GetStatistics. */
 743struct ucc_geth_hardware_statistics {
 744	u32 tx64;		/* Total number of frames (including bad
 745				   frames) transmitted that were exactly of the
 746				   minimal length (64 for un tagged, 68 for
 747				   tagged, or with length exactly equal to the
 748				   parameter MINLength */
 749	u32 tx127;		/* Total number of frames (including bad
 750				   frames) transmitted that were between
 751				   MINLength (Including FCS length==4) and 127
 752				   octets */
 753	u32 tx255;		/* Total number of frames (including bad
 754				   frames) transmitted that were between 128
 755				   (Including FCS length==4) and 255 octets */
 756	u32 rx64;		/* Total number of frames received including
 757				   bad frames that were exactly of the mninimal
 758				   length (64 bytes) */
 759	u32 rx127;		/* Total number of frames (including bad
 760				   frames) received that were between MINLength
 761				   (Including FCS length==4) and 127 octets */
 762	u32 rx255;		/* Total number of frames (including bad
 763				   frames) received that were between 128
 764				   (Including FCS length==4) and 255 octets */
 765	u32 txok;		/* Total number of octets residing in frames
 766				   that where involved in successful
 767				   transmission */
 768	u16 txcf;		/* Total number of PAUSE control frames
 769				   transmitted by this MAC */
 770	u32 tmca;		/* Total number of frames that were transmitted
 771				   successfully with the group address bit set
 772				   that are not broadcast frames */
 773	u32 tbca;		/* Total number of frames transmitted
 774				   successfully that had destination address
 775				   field equal to the broadcast address */
 776	u32 rxfok;		/* Total number of frames received OK */
 777	u32 rxbok;		/* Total number of octets received OK */
 778	u32 rbyt;		/* Total number of octets received including
 779				   octets in bad frames. Must be implemented in
 780				   HW because it includes octets in frames that
 781				   never even reach the UCC */
 782	u32 rmca;		/* Total number of frames that were received
 783				   successfully with the group address bit set
 784				   that are not broadcast frames */
 785	u32 rbca;		/* Total number of frames received successfully
 786				   that had destination address equal to the
 787				   broadcast address */
 788} __packed;
 789
 790/* UCC GETH Tx errors returned via TxConf callback */
 791#define TX_ERRORS_DEF      0x0200
 792#define TX_ERRORS_EXDEF    0x0100
 793#define TX_ERRORS_LC       0x0080
 794#define TX_ERRORS_RL       0x0040
 795#define TX_ERRORS_RC_MASK  0x003C
 796#define TX_ERRORS_RC_SHIFT 2
 797#define TX_ERRORS_UN       0x0002
 798#define TX_ERRORS_CSL      0x0001
 799
 800/* UCC GETH Rx errors returned via RxStore callback */
 801#define RX_ERRORS_CMR      0x0200
 802#define RX_ERRORS_M        0x0100
 803#define RX_ERRORS_BC       0x0080
 804#define RX_ERRORS_MC       0x0040
 805
 806/* Transmit BD. These are in addition to values defined in uccf. */
 807#define T_VID      0x003c0000	/* insert VLAN id index mask. */
 808#define T_DEF      (((u32) TX_ERRORS_DEF     ) << 16)
 809#define T_EXDEF    (((u32) TX_ERRORS_EXDEF   ) << 16)
 810#define T_LC       (((u32) TX_ERRORS_LC      ) << 16)
 811#define T_RL       (((u32) TX_ERRORS_RL      ) << 16)
 812#define T_RC_MASK  (((u32) TX_ERRORS_RC_MASK ) << 16)
 813#define T_UN       (((u32) TX_ERRORS_UN      ) << 16)
 814#define T_CSL      (((u32) TX_ERRORS_CSL     ) << 16)
 815#define T_ERRORS_REPORT  (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
 816		| T_UN | T_CSL)	/* transmit errors to report */
 817
 818/* Receive BD. These are in addition to values defined in uccf. */
 819#define R_LG    0x00200000	/* Frame length violation.  */
 820#define R_NO    0x00100000	/* Non-octet aligned frame.  */
 821#define R_SH    0x00080000	/* Short frame.  */
 822#define R_CR    0x00040000	/* CRC error.  */
 823#define R_OV    0x00020000	/* Overrun.  */
 824#define R_IPCH  0x00010000	/* IP checksum check failed. */
 825#define R_CMR   (((u32) RX_ERRORS_CMR  ) << 16)
 826#define R_M     (((u32) RX_ERRORS_M    ) << 16)
 827#define R_BC    (((u32) RX_ERRORS_BC   ) << 16)
 828#define R_MC    (((u32) RX_ERRORS_MC   ) << 16)
 829#define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC)	/* receive errors to
 830							   report */
 831#define R_ERRORS_FATAL  (R_LG  | R_NO | R_SH | R_CR | \
 832		R_OV | R_IPCH)	/* receive errors to discard */
 833
 834/* Alignments */
 835#define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT	256
 836#define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT       128
 837#define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT       128
 838#define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT       64
 839#define UCC_GETH_THREAD_DATA_ALIGNMENT          256	/* spec gives values
 840							   based on num of
 841							   threads, but always
 842							   using the maximum is
 843							   easier */
 844#define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT	32
 845#define UCC_GETH_SCHEDULER_ALIGNMENT		8	/* This is a guess */
 846#define UCC_GETH_TX_STATISTICS_ALIGNMENT	4	/* This is a guess */
 847#define UCC_GETH_RX_STATISTICS_ALIGNMENT	4	/* This is a guess */
 848#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT	64
 849#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT		8	/* This is a guess */
 850#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT	128	/* This is a guess */
 851#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 8	/* This
 852									   is a
 853									   guess
 854									 */
 855#define UCC_GETH_RX_BD_RING_ALIGNMENT		32
 856#define UCC_GETH_TX_BD_RING_ALIGNMENT		32
 857#define UCC_GETH_MRBLR_ALIGNMENT		128
 858#define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT	4
 859#define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT	32
 860#define UCC_GETH_RX_DATA_BUF_ALIGNMENT		64
 861
 862#define UCC_GETH_TAD_EF                         0x80
 863#define UCC_GETH_TAD_V                          0x40
 864#define UCC_GETH_TAD_REJ                        0x20
 865#define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT        2
 866#define UCC_GETH_TAD_VTAG_OP_SHIFT              6
 867#define UCC_GETH_TAD_V_NON_VTAG_OP              0x20
 868#define UCC_GETH_TAD_RQOS_SHIFT                 0
 869#define UCC_GETH_TAD_V_PRIORITY_SHIFT           5
 870#define UCC_GETH_TAD_CFI                        0x10
 871
 872#define UCC_GETH_VLAN_PRIORITY_MAX              8
 873#define UCC_GETH_IP_PRIORITY_MAX                64
 874#define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX        8
 875#define UCC_GETH_RX_BD_RING_SIZE_MIN            8
 876#define UCC_GETH_TX_BD_RING_SIZE_MIN            2
 877#define UCC_GETH_BD_RING_SIZE_MAX		0xffff
 878
 879#define UCC_GETH_SIZE_OF_BD                     QE_SIZEOF_BD
 880
 881/* Driver definitions */
 882#define TX_BD_RING_LEN                          0x10
 883#define RX_BD_RING_LEN                          0x20
 884
 885#define TX_RING_MOD_MASK(size)                  (size-1)
 886#define RX_RING_MOD_MASK(size)                  (size-1)
 887
 888#define ENET_GROUP_ADDR                         0x01	/* Group address mask
 889							   for ethernet
 890							   addresses */
 891
 892#define TX_TIMEOUT                              (1*HZ)
 893
 894/* Fast Ethernet (10/100 Mbps) */
 895#define UCC_GETH_URFS_INIT                      512	/* Rx virtual FIFO size
 896							 */
 897#define UCC_GETH_URFET_INIT                     256	/* 1/2 urfs */
 898#define UCC_GETH_URFSET_INIT                    384	/* 3/4 urfs */
 899#define UCC_GETH_UTFS_INIT                      512	/* Tx virtual FIFO size
 900							 */
 901#define UCC_GETH_UTFET_INIT                     256	/* 1/2 utfs */
 902#define UCC_GETH_UTFTT_INIT                     256	/* 1/2 utfs
 903							   due to errata */
 904/* Gigabit Ethernet (1000 Mbps) */
 905#define UCC_GETH_URFS_GIGA_INIT                 4096/*2048*/	/* Rx virtual
 906								   FIFO size */
 907#define UCC_GETH_URFET_GIGA_INIT                2048/*1024*/	/* 1/2 urfs */
 908#define UCC_GETH_URFSET_GIGA_INIT               3072/*1536*/	/* 3/4 urfs */
 909#define UCC_GETH_UTFS_GIGA_INIT                 4096/*2048*/	/* Tx virtual
 910								   FIFO size */
 911#define UCC_GETH_UTFET_GIGA_INIT                2048/*1024*/	/* 1/2 utfs */
 912#define UCC_GETH_UTFTT_GIGA_INIT                4096/*0x40*/	/* Tx virtual
 913								   FIFO size */
 914
 915#define UCC_GETH_REMODER_INIT                   0	/* bits that must be
 916							   set */
 917#define UCC_GETH_TEMODER_INIT                   0xC000	/* bits that must */
 918
 919/* Initial value for UPSMR */
 920#define UCC_GETH_UPSMR_INIT                     UCC_GETH_UPSMR_RES1
 921
 922#define UCC_GETH_MACCFG1_INIT                   0
 923#define UCC_GETH_MACCFG2_INIT                   (MACCFG2_RESERVED_1 | \
 924						 (7 << MACCFG2_PREL_SHIFT))
 925
 926/* Ethernet Address Type. */
 927enum enet_addr_type {
 928	ENET_ADDR_TYPE_INDIVIDUAL,
 929	ENET_ADDR_TYPE_GROUP,
 930	ENET_ADDR_TYPE_BROADCAST
 931};
 932
 933/* UCC GETH 82xx Ethernet Address Recognition Location */
 934enum ucc_geth_enet_address_recognition_location {
 935	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
 936								      address */
 937	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST,	/* additional
 938								   station
 939								   address
 940								   paddr1 */
 941	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2,	/* additional
 942								   station
 943								   address
 944								   paddr2 */
 945	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3,	/* additional
 946								   station
 947								   address
 948								   paddr3 */
 949	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST,	/* additional
 950								   station
 951								   address
 952								   paddr4 */
 953	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,	/* group hash */
 954	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
 955								      hash */
 956};
 957
 958/* UCC GETH vlan operation tagged */
 959enum ucc_geth_vlan_operation_tagged {
 960	UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,	/* Tagged - nop */
 961	UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
 962		= 0x1,	/* Tagged - replace vid portion of q tag */
 963	UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
 964		= 0x2,	/* Tagged - if vid0 replace vid with default value  */
 965	UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
 966		= 0x3	/* Tagged - extract q tag from frame */
 967};
 968
 969/* UCC GETH vlan operation non-tagged */
 970enum ucc_geth_vlan_operation_non_tagged {
 971	UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,	/* Non tagged - nop */
 972	UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1	/* Non tagged -
 973								   q tag insert
 974								 */
 975};
 976
 977/* UCC GETH Rx Quality of Service Mode */
 978enum ucc_geth_qos_mode {
 979	UCC_GETH_QOS_MODE_DEFAULT = 0x0,	/* default queue */
 980	UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1,	/* queue
 981								   determined
 982								   by L2
 983								   criteria */
 984	UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2	/* queue
 985								   determined
 986								   by L3
 987								   criteria */
 988};
 989
 990/* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
 991   for combined functionality */
 992enum ucc_geth_statistics_gathering_mode {
 993	UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,	/* No
 994								   statistics
 995								   gathering */
 996	UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
 997								    hardware
 998								    statistics
 999								    gathering
1000								  */
1001	UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
1002								      firmware
1003								      tx
1004								      statistics
1005								      gathering
1006								     */
1007	UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
1008								      firmware
1009								      rx
1010								      statistics
1011								      gathering
1012								    */
1013};
1014
1015/* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
1016enum ucc_geth_maccfg2_pad_and_crc_mode {
1017	UCC_GETH_PAD_AND_CRC_MODE_NONE
1018		= MACCFG2_PAD_AND_CRC_MODE_NONE,	/* Neither Padding
1019							   short frames
1020							   nor CRC */
1021	UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
1022		= MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY,	/* Append
1023							   CRC only */
1024	UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
1025	    MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1026};
1027
1028/* UCC GETH upsmr Flow Control Mode */
1029enum ucc_geth_flow_control_mode {
1030	UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,	/* No automatic
1031								   flow control
1032								 */
1033	UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1034		= 0x00004000	/* Send pause frame when RxFIFO reaches its
1035				   emergency threshold */
1036};
1037
1038/* UCC GETH number of threads */
1039enum ucc_geth_num_of_threads {
1040	UCC_GETH_NUM_OF_THREADS_1 = 0x1,	/* 1 */
1041	UCC_GETH_NUM_OF_THREADS_2 = 0x2,	/* 2 */
1042	UCC_GETH_NUM_OF_THREADS_4 = 0x0,	/* 4 */
1043	UCC_GETH_NUM_OF_THREADS_6 = 0x3,	/* 6 */
1044	UCC_GETH_NUM_OF_THREADS_8 = 0x4	/* 8 */
1045};
1046
1047/* UCC GETH number of station addresses */
1048enum ucc_geth_num_of_station_addresses {
1049	UCC_GETH_NUM_OF_STATION_ADDRESSES_1,	/* 1 */
1050	UCC_GETH_NUM_OF_STATION_ADDRESSES_5	/* 5 */
1051};
1052
1053/* UCC GETH 82xx Ethernet Address Container */
1054struct enet_addr_container {
1055	u8 address[ETH_ALEN];	/* ethernet address */
1056	enum ucc_geth_enet_address_recognition_location location;	/* location in
1057								   82xx address
1058								   recognition
1059								   hardware */
1060	struct list_head node;
1061};
1062
1063#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1064
1065/* UCC GETH Termination Action Descriptor (TAD) structure. */
1066struct ucc_geth_tad_params {
1067	int rx_non_dynamic_extended_features_mode;
1068	int reject_frame;
1069	enum ucc_geth_vlan_operation_tagged vtag_op;
1070	enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1071	enum ucc_geth_qos_mode rqos;
1072	u8 vpri;
1073	u16 vid;
1074};
1075
1076struct phylink;
1077struct phylink_config;
1078
1079/* GETH protocol initialization structure */
1080struct ucc_geth_info {
1081	struct ucc_fast_info uf_info;
1082	int ipCheckSumCheck;
1083	int ipCheckSumGenerate;
1084	int rxExtendedFiltering;
1085	u32 extendedFilteringChainPointer;
1086	u16 typeorlen;
1087	int dynamicMaxFrameLength;
1088	int dynamicMinFrameLength;
1089	u8 nonBackToBackIfgPart1;
1090	u8 nonBackToBackIfgPart2;
1091	u8 miminumInterFrameGapEnforcement;
1092	u8 backToBackInterFrameGap;
1093	int ipAddressAlignment;
1094	u32 mblinterval;
1095	u16 nortsrbytetime;
1096	u8 fracsiz;
1097	u8 strictpriorityq;
1098	u8 txasap;
1099	u8 extrabw;
1100	int miiPreambleSupress;
1101	u8 altBebTruncation;
1102	int altBeb;
1103	int backPressureNoBackoff;
1104	int noBackoff;
1105	int excessDefer;
1106	u8 maxRetransmission;
1107	u8 collisionWindow;
1108	int pro;
1109	int cap;
1110	int rsh;
1111	int rlpb;
1112	int cam;
1113	int bro;
1114	int ecm;
1115	int receiveFlowControl;
1116	int transmitFlowControl;
1117	u8 maxGroupAddrInHash;
1118	u8 maxIndAddrInHash;
1119	u16 maxFrameLength;
1120	u16 minFrameLength;
1121	u16 maxD1Length;
1122	u16 maxD2Length;
1123	u16 vlantype;
1124	u16 vlantci;
1125	u32 ecamptr;
1126	u32 eventRegMask;
1127	u16 pausePeriod;
1128	u16 extensionField;
1129	struct device_node *tbi_node;
1130	u8 weightfactor[NUM_TX_QUEUES];
1131	u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1132	u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1133	u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1134	u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1135	u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1136	u16 bdRingLenTx[NUM_TX_QUEUES];
1137	u16 bdRingLenRx[NUM_RX_QUEUES];
1138	enum ucc_geth_num_of_station_addresses numStationAddresses;
1139	enum qe_fltr_largest_external_tbl_lookup_key_size
1140	    largestexternallookupkeysize;
1141	enum ucc_geth_statistics_gathering_mode statisticsMode;
1142	enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1143	enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1144	enum ucc_geth_qos_mode rxQoSMode;
1145	enum ucc_geth_flow_control_mode aufc;
1146	enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1147	enum ucc_geth_num_of_threads numThreadsTx;
1148	enum ucc_geth_num_of_threads numThreadsRx;
1149	unsigned int riscTx;
1150	unsigned int riscRx;
1151};
1152
1153/* structure representing UCC GETH */
1154struct ucc_geth_private {
1155	struct ucc_geth_info *ug_info;
1156	struct ucc_fast_private *uccf;
1157	struct device *dev;
1158	struct net_device *ndev;
1159	struct napi_struct napi;
1160	struct work_struct timeout_work;
1161	struct ucc_geth __iomem *ug_regs;
1162	struct ucc_geth_init_pram *p_init_enet_param_shadow;
1163	struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1164	u32 exf_glbl_param_offset;
1165	struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1166	struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1167	struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1168	u32 send_q_mem_reg_offset;
1169	struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1170	u32 thread_dat_tx_offset;
1171	struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1172	u32 thread_dat_rx_offset;
1173	struct ucc_geth_scheduler __iomem *p_scheduler;
1174	u32 scheduler_offset;
1175	struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1176	u32 tx_fw_statistics_pram_offset;
1177	struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1178	u32 rx_fw_statistics_pram_offset;
1179	struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1180	u32 rx_irq_coalescing_tbl_offset;
1181	struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1182	u32 rx_bd_qs_tbl_offset;
1183	u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1184	u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1185	u8 __iomem *confBd[NUM_TX_QUEUES];
1186	u8 __iomem *txBd[NUM_TX_QUEUES];
1187	u8 __iomem *rxBd[NUM_RX_QUEUES];
1188	int badFrame[NUM_RX_QUEUES];
1189	u16 cpucount[NUM_TX_QUEUES];
1190	u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1191	int indAddrRegUsed[NUM_OF_PADDRS];
1192	u8 paddr[NUM_OF_PADDRS][ETH_ALEN];	/* ethernet address */
1193	u8 numGroupAddrInHash;
1194	u8 numIndAddrInHash;
1195	u8 numIndAddrInReg;
1196	int rx_extended_features;
1197	int rx_non_dynamic_extended_features;
1198	struct list_head conf_skbs;
1199	struct list_head group_hash_q;
1200	struct list_head ind_hash_q;
1201	u32 saved_uccm;
1202	spinlock_t lock;
1203	/* pointers to arrays of skbuffs for tx and rx */
1204	struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1205	struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1206	/* indices pointing to the next free sbk in skb arrays */
1207	u16 skb_curtx[NUM_TX_QUEUES];
1208	u16 skb_currx[NUM_RX_QUEUES];
1209	/* index of the first skb which hasn't been transmitted yet. */
1210	u16 skb_dirtytx[NUM_TX_QUEUES];
1211
1212	struct ugeth_mii_info *mii_info;
1213	uint32_t msg_enable;
1214	u32 wol_en;
1215	u32 phy_wol_en;
1216
1217	struct phylink *phylink;
1218	struct phylink_config phylink_config;
1219
1220	struct device_node *node;
1221};
1222
1223void uec_set_ethtool_ops(struct net_device *netdev);
1224int init_flow_control_params(u32 automatic_flow_control_mode,
1225		int rx_flow_control_enable, int tx_flow_control_enable,
1226		u16 pause_period, u16 extension_field,
1227		u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1228		u32 __iomem *maccfg1_register);
1229
1230
1231#endif				/* __UCC_GETH_H__ */