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ucc_geth.c
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linux-6.19.14/drivers/net/ethernet/freescale/ucc_geth.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved. 4 * 5 * Author: Shlomi Gridish <gridish@freescale.com> 6 * Li Yang <leoli@freescale.com> 7 * 8 * Description: 9 * QE UCC Gigabit Ethernet Driver 10 */ 11 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13 14#include <linux/kernel.h> 15#include <linux/init.h> 16#include <linux/errno.h> 17#include <linux/slab.h> 18#include <linux/stddef.h> 19#include <linux/module.h> 20#include <linux/interrupt.h> 21#include <linux/netdevice.h> 22#include <linux/etherdevice.h> 23#include <linux/skbuff.h> 24#include <linux/spinlock.h> 25#include <linux/mm.h> 26#include <linux/dma-mapping.h> 27#include <linux/mii.h> 28#include <linux/phy.h> 29#include <linux/phylink.h> 30#include <linux/workqueue.h> 31#include <linux/of.h> 32#include <linux/of_address.h> 33#include <linux/of_irq.h> 34#include <linux/of_mdio.h> 35#include <linux/of_net.h> 36#include <linux/platform_device.h> 37#include <linux/rtnetlink.h> 38 39#include <linux/uaccess.h> 40#include <asm/irq.h> 41#include <asm/io.h> 42#include <soc/fsl/qe/immap_qe.h> 43#include <soc/fsl/qe/qe.h> 44#include <soc/fsl/qe/ucc.h> 45#include <soc/fsl/qe/ucc_fast.h> 46#include <asm/machdep.h> 47 48#include "ucc_geth.h" 49 50#undef DEBUG 51 52#define ugeth_printk(level, format, arg...) \ 53 printk(level format "\n", ## arg) 54 55#define ugeth_dbg(format, arg...) \ 56 ugeth_printk(KERN_DEBUG , format , ## arg) 57 58#ifdef UGETH_VERBOSE_DEBUG 59#define ugeth_vdbg ugeth_dbg 60#else 61#define ugeth_vdbg(fmt, args...) do { } while (0) 62#endif /* UGETH_VERBOSE_DEBUG */ 63#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1 64 65 66static DEFINE_SPINLOCK(ugeth_lock); 67 68static struct { 69 u32 msg_enable; 70} debug = { -1 }; 71 72module_param_named(debug, debug.msg_enable, int, 0); 73MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)"); 74 75static int ucc_geth_thread_count(enum ucc_geth_num_of_threads idx) 76{ 77 static const u8 count[] = { 78 [UCC_GETH_NUM_OF_THREADS_1] = 1, 79 [UCC_GETH_NUM_OF_THREADS_2] = 2, 80 [UCC_GETH_NUM_OF_THREADS_4] = 4, 81 [UCC_GETH_NUM_OF_THREADS_6] = 6, 82 [UCC_GETH_NUM_OF_THREADS_8] = 8, 83 }; 84 if (idx >= ARRAY_SIZE(count)) 85 return 0; 86 return count[idx]; 87} 88 89static inline int ucc_geth_tx_queues(const struct ucc_geth_info *info) 90{ 91 return 1; 92} 93 94static inline int ucc_geth_rx_queues(const struct ucc_geth_info *info) 95{ 96 return 1; 97} 98 99static const struct ucc_geth_info ugeth_primary_info = { 100 .uf_info = { 101 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES, 102 .max_rx_buf_length = 1536, 103 /* adjusted at startup if max-speed 1000 */ 104 .urfs = UCC_GETH_URFS_INIT, 105 .urfet = UCC_GETH_URFET_INIT, 106 .urfset = UCC_GETH_URFSET_INIT, 107 .utfs = UCC_GETH_UTFS_INIT, 108 .utfet = UCC_GETH_UTFET_INIT, 109 .utftt = UCC_GETH_UTFTT_INIT, 110 .ufpt = 256, 111 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET, 112 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, 113 .tenc = UCC_FAST_TX_ENCODING_NRZ, 114 .renc = UCC_FAST_RX_ENCODING_NRZ, 115 .tcrc = UCC_FAST_16_BIT_CRC, 116 .synl = UCC_FAST_SYNC_LEN_NOT_USED, 117 }, 118 .extendedFilteringChainPointer = ((uint32_t) NULL), 119 .typeorlen = 3072 /*1536 */ , 120 .nonBackToBackIfgPart1 = 0x40, 121 .nonBackToBackIfgPart2 = 0x60, 122 .miminumInterFrameGapEnforcement = 0x50, 123 .backToBackInterFrameGap = 0x60, 124 .mblinterval = 128, 125 .nortsrbytetime = 5, 126 .fracsiz = 1, 127 .strictpriorityq = 0xff, 128 .altBebTruncation = 0xa, 129 .excessDefer = 1, 130 .maxRetransmission = 0xf, 131 .collisionWindow = 0x37, 132 .receiveFlowControl = 1, 133 .transmitFlowControl = 1, 134 .maxGroupAddrInHash = 4, 135 .maxIndAddrInHash = 4, 136 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */ 137 .minFrameLength = 64, 138 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */ 139 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */ 140 .vlantype = 0x8100, 141 .ecamptr = ((uint32_t) NULL), 142 .eventRegMask = UCCE_OTHER, 143 .pausePeriod = 0xf000, 144 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1}, 145 .bdRingLenTx = { 146 TX_BD_RING_LEN, 147 TX_BD_RING_LEN, 148 TX_BD_RING_LEN, 149 TX_BD_RING_LEN, 150 TX_BD_RING_LEN, 151 TX_BD_RING_LEN, 152 TX_BD_RING_LEN, 153 TX_BD_RING_LEN}, 154 155 .bdRingLenRx = { 156 RX_BD_RING_LEN, 157 RX_BD_RING_LEN, 158 RX_BD_RING_LEN, 159 RX_BD_RING_LEN, 160 RX_BD_RING_LEN, 161 RX_BD_RING_LEN, 162 RX_BD_RING_LEN, 163 RX_BD_RING_LEN}, 164 165 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1, 166 .largestexternallookupkeysize = 167 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE, 168 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE | 169 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX | 170 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX, 171 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP, 172 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP, 173 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT, 174 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE, 175 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC, 176 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1, 177 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1, 178 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 179 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 180}; 181 182#ifdef DEBUG 183static void mem_disp(u8 *addr, int size) 184{ 185 u8 *i; 186 int size16Aling = (size >> 4) << 4; 187 int size4Aling = (size >> 2) << 2; 188 int notAlign = 0; 189 if (size % 16) 190 notAlign = 1; 191 192 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16) 193 printk("0x%08x: %08x %08x %08x %08x\r\n", 194 (u32) i, 195 *((u32 *) (i)), 196 *((u32 *) (i + 4)), 197 *((u32 *) (i + 8)), *((u32 *) (i + 12))); 198 if (notAlign == 1) 199 printk("0x%08x: ", (u32) i); 200 for (; (u32) i < (u32) addr + size4Aling; i += 4) 201 printk("%08x ", *((u32 *) (i))); 202 for (; (u32) i < (u32) addr + size; i++) 203 printk("%02x", *((i))); 204 if (notAlign == 1) 205 printk("\r\n"); 206} 207#endif /* DEBUG */ 208 209static struct list_head *dequeue(struct list_head *lh) 210{ 211 unsigned long flags; 212 213 spin_lock_irqsave(&ugeth_lock, flags); 214 if (!list_empty(lh)) { 215 struct list_head *node = lh->next; 216 list_del(node); 217 spin_unlock_irqrestore(&ugeth_lock, flags); 218 return node; 219 } else { 220 spin_unlock_irqrestore(&ugeth_lock, flags); 221 return NULL; 222 } 223} 224 225static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, 226 u8 __iomem *bd) 227{ 228 struct sk_buff *skb; 229 230 skb = netdev_alloc_skb(ugeth->ndev, 231 ugeth->ug_info->uf_info.max_rx_buf_length + 232 UCC_GETH_RX_DATA_BUF_ALIGNMENT); 233 if (!skb) 234 return NULL; 235 236 /* We need the data buffer to be aligned properly. We will reserve 237 * as many bytes as needed to align the data properly 238 */ 239 skb_reserve(skb, 240 UCC_GETH_RX_DATA_BUF_ALIGNMENT - 241 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT - 242 1))); 243 244 out_be32(&((struct qe_bd __iomem *)bd)->buf, 245 dma_map_single(ugeth->dev, 246 skb->data, 247 ugeth->ug_info->uf_info.max_rx_buf_length + 248 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 249 DMA_FROM_DEVICE)); 250 251 out_be32((u32 __iomem *)bd, 252 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W))); 253 254 return skb; 255} 256 257static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ) 258{ 259 u8 __iomem *bd; 260 u32 bd_status; 261 struct sk_buff *skb; 262 int i; 263 264 bd = ugeth->p_rx_bd_ring[rxQ]; 265 i = 0; 266 267 do { 268 bd_status = in_be32((u32 __iomem *)bd); 269 skb = get_new_skb(ugeth, bd); 270 271 if (!skb) /* If can not allocate data buffer, 272 abort. Cleanup will be elsewhere */ 273 return -ENOMEM; 274 275 ugeth->rx_skbuff[rxQ][i] = skb; 276 277 /* advance the BD pointer */ 278 bd += sizeof(struct qe_bd); 279 i++; 280 } while (!(bd_status & R_W)); 281 282 return 0; 283} 284 285static int fill_init_enet_entries(struct ucc_geth_private *ugeth, 286 u32 *p_start, 287 u8 num_entries, 288 u32 thread_size, 289 u32 thread_alignment, 290 unsigned int risc, 291 int skip_page_for_first_entry) 292{ 293 u32 init_enet_offset; 294 u8 i; 295 int snum; 296 297 for (i = 0; i < num_entries; i++) { 298 if ((snum = qe_get_snum()) < 0) { 299 if (netif_msg_ifup(ugeth)) 300 pr_err("Can not get SNUM\n"); 301 return snum; 302 } 303 if ((i == 0) && skip_page_for_first_entry) 304 /* First entry of Rx does not have page */ 305 init_enet_offset = 0; 306 else { 307 init_enet_offset = 308 qe_muram_alloc(thread_size, thread_alignment); 309 if (IS_ERR_VALUE(init_enet_offset)) { 310 if (netif_msg_ifup(ugeth)) 311 pr_err("Can not allocate DPRAM memory\n"); 312 qe_put_snum((u8) snum); 313 return -ENOMEM; 314 } 315 } 316 *(p_start++) = 317 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset 318 | risc; 319 } 320 321 return 0; 322} 323 324static int return_init_enet_entries(struct ucc_geth_private *ugeth, 325 u32 *p_start, 326 u8 num_entries, 327 unsigned int risc, 328 int skip_page_for_first_entry) 329{ 330 u32 init_enet_offset; 331 u8 i; 332 int snum; 333 334 for (i = 0; i < num_entries; i++) { 335 u32 val = *p_start; 336 337 /* Check that this entry was actually valid -- 338 needed in case failed in allocations */ 339 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 340 snum = 341 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 342 ENET_INIT_PARAM_SNUM_SHIFT; 343 qe_put_snum((u8) snum); 344 if (!((i == 0) && skip_page_for_first_entry)) { 345 /* First entry of Rx does not have page */ 346 init_enet_offset = 347 (val & ENET_INIT_PARAM_PTR_MASK); 348 qe_muram_free(init_enet_offset); 349 } 350 *p_start++ = 0; 351 } 352 } 353 354 return 0; 355} 356 357#ifdef DEBUG 358static int dump_init_enet_entries(struct ucc_geth_private *ugeth, 359 u32 __iomem *p_start, 360 u8 num_entries, 361 u32 thread_size, 362 unsigned int risc, 363 int skip_page_for_first_entry) 364{ 365 u32 init_enet_offset; 366 u8 i; 367 int snum; 368 369 for (i = 0; i < num_entries; i++) { 370 u32 val = in_be32(p_start); 371 372 /* Check that this entry was actually valid -- 373 needed in case failed in allocations */ 374 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 375 snum = 376 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 377 ENET_INIT_PARAM_SNUM_SHIFT; 378 qe_put_snum((u8) snum); 379 if (!((i == 0) && skip_page_for_first_entry)) { 380 /* First entry of Rx does not have page */ 381 init_enet_offset = 382 (in_be32(p_start) & 383 ENET_INIT_PARAM_PTR_MASK); 384 pr_info("Init enet entry %d:\n", i); 385 pr_info("Base address: 0x%08x\n", 386 (u32)qe_muram_addr(init_enet_offset)); 387 mem_disp(qe_muram_addr(init_enet_offset), 388 thread_size); 389 } 390 p_start++; 391 } 392 } 393 394 return 0; 395} 396#endif 397 398static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont) 399{ 400 kfree(enet_addr_cont); 401} 402 403static void set_mac_addr(__be16 __iomem *reg, u8 *mac) 404{ 405 out_be16(®[0], ((u16)mac[5] << 8) | mac[4]); 406 out_be16(®[1], ((u16)mac[3] << 8) | mac[2]); 407 out_be16(®[2], ((u16)mac[1] << 8) | mac[0]); 408} 409 410static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num) 411{ 412 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 413 414 if (paddr_num >= NUM_OF_PADDRS) { 415 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num); 416 return -EINVAL; 417 } 418 419 p_82xx_addr_filt = 420 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 421 addressfiltering; 422 423 /* Writing address ff.ff.ff.ff.ff.ff disables address 424 recognition for this register */ 425 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff); 426 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff); 427 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff); 428 429 return 0; 430} 431 432static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth, 433 u8 *p_enet_addr) 434{ 435 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 436 u32 cecr_subblock; 437 438 p_82xx_addr_filt = 439 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 440 addressfiltering; 441 442 cecr_subblock = 443 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 444 445 /* Ethernet frames are defined in Little Endian mode, 446 therefore to insert */ 447 /* the address to the hash (Big Endian mode), we reverse the bytes.*/ 448 449 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr); 450 451 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock, 452 QE_CR_PROTOCOL_ETHERNET, 0); 453} 454 455#ifdef DEBUG 456static void get_statistics(struct ucc_geth_private *ugeth, 457 struct ucc_geth_tx_firmware_statistics * 458 tx_firmware_statistics, 459 struct ucc_geth_rx_firmware_statistics * 460 rx_firmware_statistics, 461 struct ucc_geth_hardware_statistics *hardware_statistics) 462{ 463 struct ucc_fast __iomem *uf_regs; 464 struct ucc_geth __iomem *ug_regs; 465 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; 466 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; 467 468 ug_regs = ugeth->ug_regs; 469 uf_regs = (struct ucc_fast __iomem *) ug_regs; 470 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram; 471 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram; 472 473 /* Tx firmware only if user handed pointer and driver actually 474 gathers Tx firmware statistics */ 475 if (tx_firmware_statistics && p_tx_fw_statistics_pram) { 476 tx_firmware_statistics->sicoltx = 477 in_be32(&p_tx_fw_statistics_pram->sicoltx); 478 tx_firmware_statistics->mulcoltx = 479 in_be32(&p_tx_fw_statistics_pram->mulcoltx); 480 tx_firmware_statistics->latecoltxfr = 481 in_be32(&p_tx_fw_statistics_pram->latecoltxfr); 482 tx_firmware_statistics->frabortduecol = 483 in_be32(&p_tx_fw_statistics_pram->frabortduecol); 484 tx_firmware_statistics->frlostinmactxer = 485 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer); 486 tx_firmware_statistics->carriersenseertx = 487 in_be32(&p_tx_fw_statistics_pram->carriersenseertx); 488 tx_firmware_statistics->frtxok = 489 in_be32(&p_tx_fw_statistics_pram->frtxok); 490 tx_firmware_statistics->txfrexcessivedefer = 491 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer); 492 tx_firmware_statistics->txpkts256 = 493 in_be32(&p_tx_fw_statistics_pram->txpkts256); 494 tx_firmware_statistics->txpkts512 = 495 in_be32(&p_tx_fw_statistics_pram->txpkts512); 496 tx_firmware_statistics->txpkts1024 = 497 in_be32(&p_tx_fw_statistics_pram->txpkts1024); 498 tx_firmware_statistics->txpktsjumbo = 499 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo); 500 } 501 502 /* Rx firmware only if user handed pointer and driver actually 503 * gathers Rx firmware statistics */ 504 if (rx_firmware_statistics && p_rx_fw_statistics_pram) { 505 int i; 506 rx_firmware_statistics->frrxfcser = 507 in_be32(&p_rx_fw_statistics_pram->frrxfcser); 508 rx_firmware_statistics->fraligner = 509 in_be32(&p_rx_fw_statistics_pram->fraligner); 510 rx_firmware_statistics->inrangelenrxer = 511 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer); 512 rx_firmware_statistics->outrangelenrxer = 513 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer); 514 rx_firmware_statistics->frtoolong = 515 in_be32(&p_rx_fw_statistics_pram->frtoolong); 516 rx_firmware_statistics->runt = 517 in_be32(&p_rx_fw_statistics_pram->runt); 518 rx_firmware_statistics->verylongevent = 519 in_be32(&p_rx_fw_statistics_pram->verylongevent); 520 rx_firmware_statistics->symbolerror = 521 in_be32(&p_rx_fw_statistics_pram->symbolerror); 522 rx_firmware_statistics->dropbsy = 523 in_be32(&p_rx_fw_statistics_pram->dropbsy); 524 for (i = 0; i < 0x8; i++) 525 rx_firmware_statistics->res0[i] = 526 p_rx_fw_statistics_pram->res0[i]; 527 rx_firmware_statistics->mismatchdrop = 528 in_be32(&p_rx_fw_statistics_pram->mismatchdrop); 529 rx_firmware_statistics->underpkts = 530 in_be32(&p_rx_fw_statistics_pram->underpkts); 531 rx_firmware_statistics->pkts256 = 532 in_be32(&p_rx_fw_statistics_pram->pkts256); 533 rx_firmware_statistics->pkts512 = 534 in_be32(&p_rx_fw_statistics_pram->pkts512); 535 rx_firmware_statistics->pkts1024 = 536 in_be32(&p_rx_fw_statistics_pram->pkts1024); 537 rx_firmware_statistics->pktsjumbo = 538 in_be32(&p_rx_fw_statistics_pram->pktsjumbo); 539 rx_firmware_statistics->frlossinmacer = 540 in_be32(&p_rx_fw_statistics_pram->frlossinmacer); 541 rx_firmware_statistics->pausefr = 542 in_be32(&p_rx_fw_statistics_pram->pausefr); 543 for (i = 0; i < 0x4; i++) 544 rx_firmware_statistics->res1[i] = 545 p_rx_fw_statistics_pram->res1[i]; 546 rx_firmware_statistics->removevlan = 547 in_be32(&p_rx_fw_statistics_pram->removevlan); 548 rx_firmware_statistics->replacevlan = 549 in_be32(&p_rx_fw_statistics_pram->replacevlan); 550 rx_firmware_statistics->insertvlan = 551 in_be32(&p_rx_fw_statistics_pram->insertvlan); 552 } 553 554 /* Hardware only if user handed pointer and driver actually 555 gathers hardware statistics */ 556 if (hardware_statistics && 557 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { 558 hardware_statistics->tx64 = in_be32(&ug_regs->tx64); 559 hardware_statistics->tx127 = in_be32(&ug_regs->tx127); 560 hardware_statistics->tx255 = in_be32(&ug_regs->tx255); 561 hardware_statistics->rx64 = in_be32(&ug_regs->rx64); 562 hardware_statistics->rx127 = in_be32(&ug_regs->rx127); 563 hardware_statistics->rx255 = in_be32(&ug_regs->rx255); 564 hardware_statistics->txok = in_be32(&ug_regs->txok); 565 hardware_statistics->txcf = in_be16(&ug_regs->txcf); 566 hardware_statistics->tmca = in_be32(&ug_regs->tmca); 567 hardware_statistics->tbca = in_be32(&ug_regs->tbca); 568 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok); 569 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok); 570 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt); 571 hardware_statistics->rmca = in_be32(&ug_regs->rmca); 572 hardware_statistics->rbca = in_be32(&ug_regs->rbca); 573 } 574} 575 576static void dump_bds(struct ucc_geth_private *ugeth) 577{ 578 int i; 579 int length; 580 581 for (i = 0; i < ucc_geth_tx_queues(ugeth->ug_info); i++) { 582 if (ugeth->p_tx_bd_ring[i]) { 583 length = 584 (ugeth->ug_info->bdRingLenTx[i] * 585 sizeof(struct qe_bd)); 586 pr_info("TX BDs[%d]\n", i); 587 mem_disp(ugeth->p_tx_bd_ring[i], length); 588 } 589 } 590 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) { 591 if (ugeth->p_rx_bd_ring[i]) { 592 length = 593 (ugeth->ug_info->bdRingLenRx[i] * 594 sizeof(struct qe_bd)); 595 pr_info("RX BDs[%d]\n", i); 596 mem_disp(ugeth->p_rx_bd_ring[i], length); 597 } 598 } 599} 600 601static void dump_regs(struct ucc_geth_private *ugeth) 602{ 603 int i; 604 605 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1); 606 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs); 607 608 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n", 609 (u32)&ugeth->ug_regs->maccfg1, 610 in_be32(&ugeth->ug_regs->maccfg1)); 611 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n", 612 (u32)&ugeth->ug_regs->maccfg2, 613 in_be32(&ugeth->ug_regs->maccfg2)); 614 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n", 615 (u32)&ugeth->ug_regs->ipgifg, 616 in_be32(&ugeth->ug_regs->ipgifg)); 617 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n", 618 (u32)&ugeth->ug_regs->hafdup, 619 in_be32(&ugeth->ug_regs->hafdup)); 620 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n", 621 (u32)&ugeth->ug_regs->ifctl, 622 in_be32(&ugeth->ug_regs->ifctl)); 623 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n", 624 (u32)&ugeth->ug_regs->ifstat, 625 in_be32(&ugeth->ug_regs->ifstat)); 626 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n", 627 (u32)&ugeth->ug_regs->macstnaddr1, 628 in_be32(&ugeth->ug_regs->macstnaddr1)); 629 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n", 630 (u32)&ugeth->ug_regs->macstnaddr2, 631 in_be32(&ugeth->ug_regs->macstnaddr2)); 632 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n", 633 (u32)&ugeth->ug_regs->uempr, 634 in_be32(&ugeth->ug_regs->uempr)); 635 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n", 636 (u32)&ugeth->ug_regs->utbipar, 637 in_be32(&ugeth->ug_regs->utbipar)); 638 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n", 639 (u32)&ugeth->ug_regs->uescr, 640 in_be16(&ugeth->ug_regs->uescr)); 641 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n", 642 (u32)&ugeth->ug_regs->tx64, 643 in_be32(&ugeth->ug_regs->tx64)); 644 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n", 645 (u32)&ugeth->ug_regs->tx127, 646 in_be32(&ugeth->ug_regs->tx127)); 647 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n", 648 (u32)&ugeth->ug_regs->tx255, 649 in_be32(&ugeth->ug_regs->tx255)); 650 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n", 651 (u32)&ugeth->ug_regs->rx64, 652 in_be32(&ugeth->ug_regs->rx64)); 653 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n", 654 (u32)&ugeth->ug_regs->rx127, 655 in_be32(&ugeth->ug_regs->rx127)); 656 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n", 657 (u32)&ugeth->ug_regs->rx255, 658 in_be32(&ugeth->ug_regs->rx255)); 659 pr_info("txok : addr - 0x%08x, val - 0x%08x\n", 660 (u32)&ugeth->ug_regs->txok, 661 in_be32(&ugeth->ug_regs->txok)); 662 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n", 663 (u32)&ugeth->ug_regs->txcf, 664 in_be16(&ugeth->ug_regs->txcf)); 665 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n", 666 (u32)&ugeth->ug_regs->tmca, 667 in_be32(&ugeth->ug_regs->tmca)); 668 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n", 669 (u32)&ugeth->ug_regs->tbca, 670 in_be32(&ugeth->ug_regs->tbca)); 671 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n", 672 (u32)&ugeth->ug_regs->rxfok, 673 in_be32(&ugeth->ug_regs->rxfok)); 674 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n", 675 (u32)&ugeth->ug_regs->rxbok, 676 in_be32(&ugeth->ug_regs->rxbok)); 677 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n", 678 (u32)&ugeth->ug_regs->rbyt, 679 in_be32(&ugeth->ug_regs->rbyt)); 680 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n", 681 (u32)&ugeth->ug_regs->rmca, 682 in_be32(&ugeth->ug_regs->rmca)); 683 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n", 684 (u32)&ugeth->ug_regs->rbca, 685 in_be32(&ugeth->ug_regs->rbca)); 686 pr_info("scar : addr - 0x%08x, val - 0x%08x\n", 687 (u32)&ugeth->ug_regs->scar, 688 in_be32(&ugeth->ug_regs->scar)); 689 pr_info("scam : addr - 0x%08x, val - 0x%08x\n", 690 (u32)&ugeth->ug_regs->scam, 691 in_be32(&ugeth->ug_regs->scam)); 692 693 if (ugeth->p_thread_data_tx) { 694 int count = ucc_geth_thread_count(ugeth->ug_info->numThreadsTx); 695 696 pr_info("Thread data TXs:\n"); 697 pr_info("Base address: 0x%08x\n", 698 (u32)ugeth->p_thread_data_tx); 699 for (i = 0; i < count; i++) { 700 pr_info("Thread data TX[%d]:\n", i); 701 pr_info("Base address: 0x%08x\n", 702 (u32)&ugeth->p_thread_data_tx[i]); 703 mem_disp((u8 *) & ugeth->p_thread_data_tx[i], 704 sizeof(struct ucc_geth_thread_data_tx)); 705 } 706 } 707 if (ugeth->p_thread_data_rx) { 708 int count = ucc_geth_thread_count(ugeth->ug_info->numThreadsRx); 709 710 pr_info("Thread data RX:\n"); 711 pr_info("Base address: 0x%08x\n", 712 (u32)ugeth->p_thread_data_rx); 713 for (i = 0; i < count; i++) { 714 pr_info("Thread data RX[%d]:\n", i); 715 pr_info("Base address: 0x%08x\n", 716 (u32)&ugeth->p_thread_data_rx[i]); 717 mem_disp((u8 *) & ugeth->p_thread_data_rx[i], 718 sizeof(struct ucc_geth_thread_data_rx)); 719 } 720 } 721 if (ugeth->p_exf_glbl_param) { 722 pr_info("EXF global param:\n"); 723 pr_info("Base address: 0x%08x\n", 724 (u32)ugeth->p_exf_glbl_param); 725 mem_disp((u8 *) ugeth->p_exf_glbl_param, 726 sizeof(*ugeth->p_exf_glbl_param)); 727 } 728 if (ugeth->p_tx_glbl_pram) { 729 pr_info("TX global param:\n"); 730 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram); 731 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n", 732 (u32)&ugeth->p_tx_glbl_pram->temoder, 733 in_be16(&ugeth->p_tx_glbl_pram->temoder)); 734 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n", 735 (u32)&ugeth->p_tx_glbl_pram->sqptr, 736 in_be32(&ugeth->p_tx_glbl_pram->sqptr)); 737 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n", 738 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer, 739 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer)); 740 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n", 741 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr, 742 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr)); 743 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n", 744 (u32)&ugeth->p_tx_glbl_pram->tstate, 745 in_be32(&ugeth->p_tx_glbl_pram->tstate)); 746 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n", 747 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0], 748 ugeth->p_tx_glbl_pram->iphoffset[0]); 749 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n", 750 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1], 751 ugeth->p_tx_glbl_pram->iphoffset[1]); 752 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n", 753 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2], 754 ugeth->p_tx_glbl_pram->iphoffset[2]); 755 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n", 756 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3], 757 ugeth->p_tx_glbl_pram->iphoffset[3]); 758 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n", 759 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4], 760 ugeth->p_tx_glbl_pram->iphoffset[4]); 761 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n", 762 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5], 763 ugeth->p_tx_glbl_pram->iphoffset[5]); 764 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n", 765 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6], 766 ugeth->p_tx_glbl_pram->iphoffset[6]); 767 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n", 768 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7], 769 ugeth->p_tx_glbl_pram->iphoffset[7]); 770 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n", 771 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0], 772 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0])); 773 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n", 774 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1], 775 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1])); 776 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n", 777 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2], 778 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2])); 779 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n", 780 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3], 781 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3])); 782 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n", 783 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4], 784 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4])); 785 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n", 786 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5], 787 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5])); 788 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n", 789 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6], 790 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6])); 791 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n", 792 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7], 793 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7])); 794 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n", 795 (u32)&ugeth->p_tx_glbl_pram->tqptr, 796 in_be32(&ugeth->p_tx_glbl_pram->tqptr)); 797 } 798 if (ugeth->p_rx_glbl_pram) { 799 pr_info("RX global param:\n"); 800 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram); 801 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n", 802 (u32)&ugeth->p_rx_glbl_pram->remoder, 803 in_be32(&ugeth->p_rx_glbl_pram->remoder)); 804 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n", 805 (u32)&ugeth->p_rx_glbl_pram->rqptr, 806 in_be32(&ugeth->p_rx_glbl_pram->rqptr)); 807 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n", 808 (u32)&ugeth->p_rx_glbl_pram->typeorlen, 809 in_be16(&ugeth->p_rx_glbl_pram->typeorlen)); 810 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n", 811 (u32)&ugeth->p_rx_glbl_pram->rxgstpack, 812 ugeth->p_rx_glbl_pram->rxgstpack); 813 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n", 814 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr, 815 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr)); 816 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n", 817 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr, 818 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr)); 819 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n", 820 (u32)&ugeth->p_rx_glbl_pram->rstate, 821 ugeth->p_rx_glbl_pram->rstate); 822 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n", 823 (u32)&ugeth->p_rx_glbl_pram->mrblr, 824 in_be16(&ugeth->p_rx_glbl_pram->mrblr)); 825 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n", 826 (u32)&ugeth->p_rx_glbl_pram->rbdqptr, 827 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr)); 828 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n", 829 (u32)&ugeth->p_rx_glbl_pram->mflr, 830 in_be16(&ugeth->p_rx_glbl_pram->mflr)); 831 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n", 832 (u32)&ugeth->p_rx_glbl_pram->minflr, 833 in_be16(&ugeth->p_rx_glbl_pram->minflr)); 834 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n", 835 (u32)&ugeth->p_rx_glbl_pram->maxd1, 836 in_be16(&ugeth->p_rx_glbl_pram->maxd1)); 837 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n", 838 (u32)&ugeth->p_rx_glbl_pram->maxd2, 839 in_be16(&ugeth->p_rx_glbl_pram->maxd2)); 840 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n", 841 (u32)&ugeth->p_rx_glbl_pram->ecamptr, 842 in_be32(&ugeth->p_rx_glbl_pram->ecamptr)); 843 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n", 844 (u32)&ugeth->p_rx_glbl_pram->l2qt, 845 in_be32(&ugeth->p_rx_glbl_pram->l2qt)); 846 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n", 847 (u32)&ugeth->p_rx_glbl_pram->l3qt[0], 848 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0])); 849 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n", 850 (u32)&ugeth->p_rx_glbl_pram->l3qt[1], 851 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1])); 852 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n", 853 (u32)&ugeth->p_rx_glbl_pram->l3qt[2], 854 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2])); 855 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n", 856 (u32)&ugeth->p_rx_glbl_pram->l3qt[3], 857 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3])); 858 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n", 859 (u32)&ugeth->p_rx_glbl_pram->l3qt[4], 860 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4])); 861 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n", 862 (u32)&ugeth->p_rx_glbl_pram->l3qt[5], 863 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5])); 864 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n", 865 (u32)&ugeth->p_rx_glbl_pram->l3qt[6], 866 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6])); 867 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n", 868 (u32)&ugeth->p_rx_glbl_pram->l3qt[7], 869 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7])); 870 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n", 871 (u32)&ugeth->p_rx_glbl_pram->vlantype, 872 in_be16(&ugeth->p_rx_glbl_pram->vlantype)); 873 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n", 874 (u32)&ugeth->p_rx_glbl_pram->vlantci, 875 in_be16(&ugeth->p_rx_glbl_pram->vlantci)); 876 for (i = 0; i < 64; i++) 877 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n", 878 i, 879 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i], 880 ugeth->p_rx_glbl_pram->addressfiltering[i]); 881 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n", 882 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam, 883 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam)); 884 } 885 if (ugeth->p_send_q_mem_reg) { 886 pr_info("Send Q memory registers:\n"); 887 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg); 888 for (i = 0; i < ucc_geth_tx_queues(ugeth->ug_info); i++) { 889 pr_info("SQQD[%d]:\n", i); 890 pr_info("Base address: 0x%08x\n", 891 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]); 892 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i], 893 sizeof(struct ucc_geth_send_queue_qd)); 894 } 895 } 896 if (ugeth->p_scheduler) { 897 pr_info("Scheduler:\n"); 898 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler); 899 mem_disp((u8 *) ugeth->p_scheduler, 900 sizeof(*ugeth->p_scheduler)); 901 } 902 if (ugeth->p_tx_fw_statistics_pram) { 903 pr_info("TX FW statistics pram:\n"); 904 pr_info("Base address: 0x%08x\n", 905 (u32)ugeth->p_tx_fw_statistics_pram); 906 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram, 907 sizeof(*ugeth->p_tx_fw_statistics_pram)); 908 } 909 if (ugeth->p_rx_fw_statistics_pram) { 910 pr_info("RX FW statistics pram:\n"); 911 pr_info("Base address: 0x%08x\n", 912 (u32)ugeth->p_rx_fw_statistics_pram); 913 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram, 914 sizeof(*ugeth->p_rx_fw_statistics_pram)); 915 } 916 if (ugeth->p_rx_irq_coalescing_tbl) { 917 pr_info("RX IRQ coalescing tables:\n"); 918 pr_info("Base address: 0x%08x\n", 919 (u32)ugeth->p_rx_irq_coalescing_tbl); 920 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) { 921 pr_info("RX IRQ coalescing table entry[%d]:\n", i); 922 pr_info("Base address: 0x%08x\n", 923 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 924 coalescingentry[i]); 925 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n", 926 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 927 coalescingentry[i].interruptcoalescingmaxvalue, 928 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 929 coalescingentry[i]. 930 interruptcoalescingmaxvalue)); 931 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n", 932 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 933 coalescingentry[i].interruptcoalescingcounter, 934 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 935 coalescingentry[i]. 936 interruptcoalescingcounter)); 937 } 938 } 939 if (ugeth->p_rx_bd_qs_tbl) { 940 pr_info("RX BD QS tables:\n"); 941 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl); 942 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) { 943 pr_info("RX BD QS table[%d]:\n", i); 944 pr_info("Base address: 0x%08x\n", 945 (u32)&ugeth->p_rx_bd_qs_tbl[i]); 946 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n", 947 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr, 948 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr)); 949 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n", 950 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr, 951 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr)); 952 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n", 953 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 954 in_be32(&ugeth->p_rx_bd_qs_tbl[i]. 955 externalbdbaseptr)); 956 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n", 957 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr, 958 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr)); 959 pr_info("ucode RX Prefetched BDs:\n"); 960 pr_info("Base address: 0x%08x\n", 961 (u32)qe_muram_addr(in_be32 962 (&ugeth->p_rx_bd_qs_tbl[i]. 963 bdbaseptr))); 964 mem_disp((u8 *) 965 qe_muram_addr(in_be32 966 (&ugeth->p_rx_bd_qs_tbl[i]. 967 bdbaseptr)), 968 sizeof(struct ucc_geth_rx_prefetched_bds)); 969 } 970 } 971 if (ugeth->p_init_enet_param_shadow) { 972 int size; 973 pr_info("Init enet param shadow:\n"); 974 pr_info("Base address: 0x%08x\n", 975 (u32) ugeth->p_init_enet_param_shadow); 976 mem_disp((u8 *) ugeth->p_init_enet_param_shadow, 977 sizeof(*ugeth->p_init_enet_param_shadow)); 978 979 size = sizeof(struct ucc_geth_thread_rx_pram); 980 if (ugeth->ug_info->rxExtendedFiltering) { 981 size += 982 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 983 if (ugeth->ug_info->largestexternallookupkeysize == 984 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 985 size += 986 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 987 if (ugeth->ug_info->largestexternallookupkeysize == 988 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 989 size += 990 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 991 } 992 993 dump_init_enet_entries(ugeth, 994 &(ugeth->p_init_enet_param_shadow-> 995 txthread[0]), 996 ENET_INIT_PARAM_MAX_ENTRIES_TX, 997 sizeof(struct ucc_geth_thread_tx_pram), 998 ugeth->ug_info->riscTx, 0); 999 dump_init_enet_entries(ugeth, 1000 &(ugeth->p_init_enet_param_shadow-> 1001 rxthread[0]), 1002 ENET_INIT_PARAM_MAX_ENTRIES_RX, size, 1003 ugeth->ug_info->riscRx, 1); 1004 } 1005} 1006#endif /* DEBUG */ 1007 1008static void init_default_reg_vals(u32 __iomem *upsmr_register, 1009 u32 __iomem *maccfg1_register, 1010 u32 __iomem *maccfg2_register) 1011{ 1012 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT); 1013 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT); 1014 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT); 1015} 1016 1017static int init_half_duplex_params(int alt_beb, 1018 int back_pressure_no_backoff, 1019 int no_backoff, 1020 int excess_defer, 1021 u8 alt_beb_truncation, 1022 u8 max_retransmissions, 1023 u8 collision_window, 1024 u32 __iomem *hafdup_register) 1025{ 1026 u32 value = 0; 1027 1028 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) || 1029 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) || 1030 (collision_window > HALFDUP_COLLISION_WINDOW_MAX)) 1031 return -EINVAL; 1032 1033 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT); 1034 1035 if (alt_beb) 1036 value |= HALFDUP_ALT_BEB; 1037 if (back_pressure_no_backoff) 1038 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF; 1039 if (no_backoff) 1040 value |= HALFDUP_NO_BACKOFF; 1041 if (excess_defer) 1042 value |= HALFDUP_EXCESSIVE_DEFER; 1043 1044 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT); 1045 1046 value |= collision_window; 1047 1048 out_be32(hafdup_register, value); 1049 return 0; 1050} 1051 1052static int init_inter_frame_gap_params(u8 non_btb_cs_ipg, 1053 u8 non_btb_ipg, 1054 u8 min_ifg, 1055 u8 btb_ipg, 1056 u32 __iomem *ipgifg_register) 1057{ 1058 u32 value = 0; 1059 1060 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back 1061 IPG part 2 */ 1062 if (non_btb_cs_ipg > non_btb_ipg) 1063 return -EINVAL; 1064 1065 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) || 1066 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) || 1067 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */ 1068 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX)) 1069 return -EINVAL; 1070 1071 value |= 1072 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) & 1073 IPGIFG_NBTB_CS_IPG_MASK); 1074 value |= 1075 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) & 1076 IPGIFG_NBTB_IPG_MASK); 1077 value |= 1078 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) & 1079 IPGIFG_MIN_IFG_MASK); 1080 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK); 1081 1082 out_be32(ipgifg_register, value); 1083 return 0; 1084} 1085 1086int init_flow_control_params(u32 automatic_flow_control_mode, 1087 int rx_flow_control_enable, 1088 int tx_flow_control_enable, 1089 u16 pause_period, 1090 u16 extension_field, 1091 u32 __iomem *upsmr_register, 1092 u32 __iomem *uempr_register, 1093 u32 __iomem *maccfg1_register) 1094{ 1095 u32 value = 0; 1096 1097 /* Set UEMPR register */ 1098 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT; 1099 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT; 1100 out_be32(uempr_register, value); 1101 1102 /* Set UPSMR register */ 1103 setbits32(upsmr_register, automatic_flow_control_mode); 1104 1105 value = in_be32(maccfg1_register); 1106 if (rx_flow_control_enable) 1107 value |= MACCFG1_FLOW_RX; 1108 if (tx_flow_control_enable) 1109 value |= MACCFG1_FLOW_TX; 1110 out_be32(maccfg1_register, value); 1111 1112 return 0; 1113} 1114 1115static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, 1116 int auto_zero_hardware_statistics, 1117 u32 __iomem *upsmr_register, 1118 u16 __iomem *uescr_register) 1119{ 1120 u16 uescr_value = 0; 1121 1122 /* Enable hardware statistics gathering if requested */ 1123 if (enable_hardware_statistics) 1124 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); 1125 1126 /* Clear hardware statistics counters */ 1127 uescr_value = in_be16(uescr_register); 1128 uescr_value |= UESCR_CLRCNT; 1129 /* Automatically zero hardware statistics counters on read, 1130 if requested */ 1131 if (auto_zero_hardware_statistics) 1132 uescr_value |= UESCR_AUTOZ; 1133 out_be16(uescr_register, uescr_value); 1134 1135 return 0; 1136} 1137 1138static int init_firmware_statistics_gathering_mode(int 1139 enable_tx_firmware_statistics, 1140 int enable_rx_firmware_statistics, 1141 u32 __iomem *tx_rmon_base_ptr, 1142 u32 tx_firmware_statistics_structure_address, 1143 u32 __iomem *rx_rmon_base_ptr, 1144 u32 rx_firmware_statistics_structure_address, 1145 u16 __iomem *temoder_register, 1146 u32 __iomem *remoder_register) 1147{ 1148 /* Note: this function does not check if */ 1149 /* the parameters it receives are NULL */ 1150 1151 if (enable_tx_firmware_statistics) { 1152 out_be32(tx_rmon_base_ptr, 1153 tx_firmware_statistics_structure_address); 1154 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); 1155 } 1156 1157 if (enable_rx_firmware_statistics) { 1158 out_be32(rx_rmon_base_ptr, 1159 rx_firmware_statistics_structure_address); 1160 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); 1161 } 1162 1163 return 0; 1164} 1165 1166static int init_mac_station_addr_regs(u8 address_byte_0, 1167 u8 address_byte_1, 1168 u8 address_byte_2, 1169 u8 address_byte_3, 1170 u8 address_byte_4, 1171 u8 address_byte_5, 1172 u32 __iomem *macstnaddr1_register, 1173 u32 __iomem *macstnaddr2_register) 1174{ 1175 u32 value = 0; 1176 1177 /* Example: for a station address of 0x12345678ABCD, */ 1178 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */ 1179 1180 /* MACSTNADDR1 Register: */ 1181 1182 /* 0 7 8 15 */ 1183 /* station address byte 5 station address byte 4 */ 1184 /* 16 23 24 31 */ 1185 /* station address byte 3 station address byte 2 */ 1186 value |= (u32) ((address_byte_2 << 0) & 0x000000FF); 1187 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00); 1188 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000); 1189 value |= (u32) ((address_byte_5 << 24) & 0xFF000000); 1190 1191 out_be32(macstnaddr1_register, value); 1192 1193 /* MACSTNADDR2 Register: */ 1194 1195 /* 0 7 8 15 */ 1196 /* station address byte 1 station address byte 0 */ 1197 /* 16 23 24 31 */ 1198 /* reserved reserved */ 1199 value = 0; 1200 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000); 1201 value |= (u32) ((address_byte_1 << 24) & 0xFF000000); 1202 1203 out_be32(macstnaddr2_register, value); 1204 1205 return 0; 1206} 1207 1208static int init_rx_parameters(int reject_broadcast, 1209 int receive_short_frames, 1210 int promiscuous, u32 __iomem *upsmr_register) 1211{ 1212 u32 value = 0; 1213 1214 value = in_be32(upsmr_register); 1215 1216 if (reject_broadcast) 1217 value |= UCC_GETH_UPSMR_BRO; 1218 else 1219 value &= ~UCC_GETH_UPSMR_BRO; 1220 1221 if (receive_short_frames) 1222 value |= UCC_GETH_UPSMR_RSH; 1223 else 1224 value &= ~UCC_GETH_UPSMR_RSH; 1225 1226 if (promiscuous) 1227 value |= UCC_GETH_UPSMR_PRO; 1228 else 1229 value &= ~UCC_GETH_UPSMR_PRO; 1230 1231 out_be32(upsmr_register, value); 1232 1233 return 0; 1234} 1235 1236static int init_max_rx_buff_len(u16 max_rx_buf_len, 1237 u16 __iomem *mrblr_register) 1238{ 1239 /* max_rx_buf_len value must be a multiple of 128 */ 1240 if ((max_rx_buf_len == 0) || 1241 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT)) 1242 return -EINVAL; 1243 1244 out_be16(mrblr_register, max_rx_buf_len); 1245 return 0; 1246} 1247 1248static int init_min_frame_len(u16 min_frame_length, 1249 u16 __iomem *minflr_register, 1250 u16 __iomem *mrblr_register) 1251{ 1252 u16 mrblr_value = 0; 1253 1254 mrblr_value = in_be16(mrblr_register); 1255 if (min_frame_length >= (mrblr_value - 4)) 1256 return -EINVAL; 1257 1258 out_be16(minflr_register, min_frame_length); 1259 return 0; 1260} 1261 1262static bool phy_interface_mode_is_reduced(phy_interface_t interface) 1263{ 1264 return phy_interface_mode_is_rgmii(interface) || 1265 interface == PHY_INTERFACE_MODE_RMII || 1266 interface == PHY_INTERFACE_MODE_RTBI; 1267} 1268 1269static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) 1270{ 1271 struct ucc_fast_private *uccf; 1272 u32 cecr_subblock; 1273 u32 temp; 1274 int i = 10; 1275 1276 uccf = ugeth->uccf; 1277 1278 /* Mask GRACEFUL STOP TX interrupt bit and clear it */ 1279 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); 1280 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ 1281 1282 /* Issue host command */ 1283 cecr_subblock = 1284 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1285 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 1286 QE_CR_PROTOCOL_ETHERNET, 0); 1287 1288 /* Wait for command to complete */ 1289 do { 1290 msleep(10); 1291 temp = in_be32(uccf->p_ucce); 1292 } while (!(temp & UCC_GETH_UCCE_GRA) && --i); 1293 1294 uccf->stopped_tx = 1; 1295 1296 return 0; 1297} 1298 1299static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth) 1300{ 1301 struct ucc_fast_private *uccf; 1302 u32 cecr_subblock; 1303 u8 temp; 1304 int i = 10; 1305 1306 uccf = ugeth->uccf; 1307 1308 /* Clear acknowledge bit */ 1309 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1310 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; 1311 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp); 1312 1313 /* Keep issuing command and checking acknowledge bit until 1314 it is asserted, according to spec */ 1315 do { 1316 /* Issue host command */ 1317 cecr_subblock = 1318 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info. 1319 ucc_num); 1320 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, 1321 QE_CR_PROTOCOL_ETHERNET, 0); 1322 msleep(10); 1323 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1324 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i); 1325 1326 uccf->stopped_rx = 1; 1327 1328 return 0; 1329} 1330 1331static int ugeth_restart_tx(struct ucc_geth_private *ugeth) 1332{ 1333 struct ucc_fast_private *uccf; 1334 u32 cecr_subblock; 1335 1336 uccf = ugeth->uccf; 1337 1338 cecr_subblock = 1339 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1340 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0); 1341 uccf->stopped_tx = 0; 1342 1343 return 0; 1344} 1345 1346static int ugeth_restart_rx(struct ucc_geth_private *ugeth) 1347{ 1348 struct ucc_fast_private *uccf; 1349 u32 cecr_subblock; 1350 1351 uccf = ugeth->uccf; 1352 1353 cecr_subblock = 1354 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1355 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 1356 0); 1357 uccf->stopped_rx = 0; 1358 1359 return 0; 1360} 1361 1362static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1363{ 1364 struct ucc_fast_private *uccf; 1365 int enabled_tx, enabled_rx; 1366 1367 uccf = ugeth->uccf; 1368 1369 /* check if the UCC number is in range. */ 1370 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1371 if (netif_msg_probe(ugeth)) 1372 pr_err("ucc_num out of range\n"); 1373 return -EINVAL; 1374 } 1375 1376 enabled_tx = uccf->enabled_tx; 1377 enabled_rx = uccf->enabled_rx; 1378 1379 /* Get Tx and Rx going again, in case this channel was actively 1380 disabled. */ 1381 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx) 1382 ugeth_restart_tx(ugeth); 1383 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx) 1384 ugeth_restart_rx(ugeth); 1385 1386 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */ 1387 1388 return 0; 1389 1390} 1391 1392static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1393{ 1394 struct ucc_fast_private *uccf; 1395 1396 uccf = ugeth->uccf; 1397 1398 /* check if the UCC number is in range. */ 1399 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1400 if (netif_msg_probe(ugeth)) 1401 pr_err("ucc_num out of range\n"); 1402 return -EINVAL; 1403 } 1404 1405 /* Stop any transmissions */ 1406 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx) 1407 ugeth_graceful_stop_tx(ugeth); 1408 1409 /* Stop any receptions */ 1410 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx) 1411 ugeth_graceful_stop_rx(ugeth); 1412 1413 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */ 1414 1415 return 0; 1416} 1417 1418static void ugeth_quiesce(struct ucc_geth_private *ugeth) 1419{ 1420 /* Prevent any further xmits */ 1421 netif_tx_stop_all_queues(ugeth->ndev); 1422 1423 /* Disable the interrupt to avoid NAPI rescheduling. */ 1424 disable_irq(ugeth->ug_info->uf_info.irq); 1425 1426 /* Stop NAPI, and possibly wait for its completion. */ 1427 napi_disable(&ugeth->napi); 1428} 1429 1430static void ugeth_activate(struct ucc_geth_private *ugeth) 1431{ 1432 napi_enable(&ugeth->napi); 1433 enable_irq(ugeth->ug_info->uf_info.irq); 1434 1435 /* allow to xmit again */ 1436 netif_tx_wake_all_queues(ugeth->ndev); 1437 netdev_watchdog_up(ugeth->ndev); 1438} 1439 1440/* Initialize TBI PHY interface for communicating with the 1441 * SERDES lynx PHY on the chip. We communicate with this PHY 1442 * through the MDIO bus on each controller, treating it as a 1443 * "normal" PHY at the address found in the UTBIPA register. We assume 1444 * that the UTBIPA register is valid. Either the MDIO bus code will set 1445 * it to a value that doesn't conflict with other PHYs on the bus, or the 1446 * value doesn't matter, as there are no other PHYs on the bus. 1447 */ 1448static void uec_configure_serdes(struct net_device *dev) 1449{ 1450 struct ucc_geth_private *ugeth = netdev_priv(dev); 1451 struct ucc_geth_info *ug_info = ugeth->ug_info; 1452 struct phy_device *tbiphy; 1453 1454 if (!ug_info->tbi_node) { 1455 dev_warn(&dev->dev, "SGMII mode requires that the device tree specify a tbi-handle\n"); 1456 return; 1457 } 1458 1459 tbiphy = of_phy_find_device(ug_info->tbi_node); 1460 if (!tbiphy) { 1461 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1462 return; 1463 } 1464 1465 /* 1466 * If the link is already up, we must already be ok, and don't need to 1467 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1468 * everything for us? Resetting it takes the link down and requires 1469 * several seconds for it to come back. 1470 */ 1471 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) { 1472 put_device(&tbiphy->mdio.dev); 1473 return; 1474 } 1475 1476 /* Single clk mode, mii mode off(for serdes communication) */ 1477 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS); 1478 1479 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); 1480 1481 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS); 1482 1483 put_device(&tbiphy->mdio.dev); 1484} 1485 1486static void ugeth_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1487 unsigned int mode, phy_interface_t interface, 1488 int speed, int duplex, bool tx_pause, bool rx_pause) 1489{ 1490 struct net_device *ndev = to_net_dev(config->dev); 1491 struct ucc_geth_private *ugeth = netdev_priv(ndev); 1492 struct ucc_geth_info *ug_info = ugeth->ug_info; 1493 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 1494 struct ucc_fast __iomem *uf_regs = ugeth->uccf->uf_regs; 1495 u32 old_maccfg2, maccfg2 = in_be32(&ug_regs->maccfg2); 1496 u32 old_upsmr, upsmr = in_be32(&uf_regs->upsmr); 1497 1498 old_maccfg2 = maccfg2; 1499 old_upsmr = upsmr; 1500 1501 /* No length check */ 1502 maccfg2 &= ~MACCFG2_LC; 1503 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; 1504 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | 1505 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); 1506 1507 if (speed == SPEED_10 || speed == SPEED_100) 1508 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 1509 else if (speed == SPEED_1000) 1510 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; 1511 1512 maccfg2 |= ug_info->padAndCrc; 1513 1514 if (phy_interface_mode_is_reduced(interface)) { 1515 1516 if (interface != PHY_INTERFACE_MODE_RMII) 1517 upsmr |= UCC_GETH_UPSMR_RPM; 1518 1519 switch (speed) { 1520 case SPEED_10: 1521 upsmr |= UCC_GETH_UPSMR_R10M; 1522 fallthrough; 1523 case SPEED_100: 1524 if (interface != PHY_INTERFACE_MODE_RTBI) 1525 upsmr |= UCC_GETH_UPSMR_RMM; 1526 } 1527 } 1528 1529 if (interface == PHY_INTERFACE_MODE_TBI || 1530 interface == PHY_INTERFACE_MODE_RTBI) 1531 upsmr |= UCC_GETH_UPSMR_TBIM; 1532 1533 if (interface == PHY_INTERFACE_MODE_SGMII) 1534 upsmr |= UCC_GETH_UPSMR_SGMM; 1535 1536 if (duplex == DUPLEX_HALF) 1537 maccfg2 &= ~(MACCFG2_FDX); 1538 else 1539 maccfg2 |= MACCFG2_FDX; 1540 1541 if (maccfg2 != old_maccfg2 || upsmr != old_upsmr) { 1542 /* 1543 * To change the MAC configuration we need to disable 1544 * the controller. To do so, we have to either grab 1545 * ugeth->lock, which is a bad idea since 'graceful 1546 * stop' commands might take quite a while, or we can 1547 * quiesce driver's activity. 1548 */ 1549 ugeth_quiesce(ugeth); 1550 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 1551 1552 out_be32(&ug_regs->maccfg2, maccfg2); 1553 out_be32(&uf_regs->upsmr, upsmr); 1554 1555 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 1556 ugeth_activate(ugeth); 1557 } 1558 1559 if (interface == PHY_INTERFACE_MODE_SGMII) 1560 uec_configure_serdes(ndev); 1561 1562 if (!phylink_autoneg_inband(mode)) { 1563 ug_info->aufc = 0; 1564 ug_info->receiveFlowControl = rx_pause; 1565 ug_info->transmitFlowControl = tx_pause; 1566 1567 init_flow_control_params(ug_info->aufc, 1568 ug_info->receiveFlowControl, 1569 ug_info->transmitFlowControl, 1570 ug_info->pausePeriod, 1571 ug_info->extensionField, 1572 &ugeth->uccf->uf_regs->upsmr, 1573 &ugeth->ug_regs->uempr, 1574 &ugeth->ug_regs->maccfg1); 1575 } 1576 1577 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 1578} 1579 1580static void ugeth_mac_link_down(struct phylink_config *config, 1581 unsigned int mode, phy_interface_t interface) 1582{ 1583 struct net_device *ndev = to_net_dev(config->dev); 1584 struct ucc_geth_private *ugeth = netdev_priv(ndev); 1585 1586 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 1587} 1588 1589static void ugeth_mac_config(struct phylink_config *config, unsigned int mode, 1590 const struct phylink_link_state *state) 1591{ 1592 struct net_device *ndev = to_net_dev(config->dev); 1593 struct ucc_geth_private *ugeth = netdev_priv(ndev); 1594 struct ucc_geth_info *ug_info = ugeth->ug_info; 1595 u16 value; 1596 1597 if (state->interface == PHY_INTERFACE_MODE_TBI || 1598 state->interface == PHY_INTERFACE_MODE_RTBI) { 1599 struct phy_device *tbiphy; 1600 1601 if (!ug_info->tbi_node) 1602 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n"); 1603 1604 tbiphy = of_phy_find_device(ug_info->tbi_node); 1605 if (!tbiphy) { 1606 pr_warn("Could not get TBI device\n"); 1607 return; 1608 } 1609 1610 value = phy_read(tbiphy, ENET_TBI_MII_CR); 1611 value &= ~0x1000; /* Turn off autonegotiation */ 1612 phy_write(tbiphy, ENET_TBI_MII_CR, value); 1613 1614 put_device(&tbiphy->mdio.dev); 1615 } 1616 1617 if (phylink_autoneg_inband(mode)) { 1618 ug_info->aufc = 1; 1619 1620 init_flow_control_params(ug_info->aufc, 1, 1, 1621 ug_info->pausePeriod, 1622 ug_info->extensionField, 1623 &ugeth->uccf->uf_regs->upsmr, 1624 &ugeth->ug_regs->uempr, 1625 &ugeth->ug_regs->maccfg1); 1626 } 1627} 1628 1629static void ugeth_dump_regs(struct ucc_geth_private *ugeth) 1630{ 1631#ifdef DEBUG 1632 ucc_fast_dump_regs(ugeth->uccf); 1633 dump_regs(ugeth); 1634 dump_bds(ugeth); 1635#endif 1636} 1637 1638static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private * 1639 ugeth, 1640 enum enet_addr_type 1641 enet_addr_type) 1642{ 1643 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 1644 struct ucc_fast_private *uccf; 1645 enum comm_dir comm_dir; 1646 struct list_head *p_lh; 1647 u16 i, num; 1648 u32 __iomem *addr_h; 1649 u32 __iomem *addr_l; 1650 u8 *p_counter; 1651 1652 uccf = ugeth->uccf; 1653 1654 p_82xx_addr_filt = 1655 (struct ucc_geth_82xx_address_filtering_pram __iomem *) 1656 ugeth->p_rx_glbl_pram->addressfiltering; 1657 1658 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) { 1659 addr_h = &(p_82xx_addr_filt->gaddr_h); 1660 addr_l = &(p_82xx_addr_filt->gaddr_l); 1661 p_lh = &ugeth->group_hash_q; 1662 p_counter = &(ugeth->numGroupAddrInHash); 1663 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) { 1664 addr_h = &(p_82xx_addr_filt->iaddr_h); 1665 addr_l = &(p_82xx_addr_filt->iaddr_l); 1666 p_lh = &ugeth->ind_hash_q; 1667 p_counter = &(ugeth->numIndAddrInHash); 1668 } else 1669 return -EINVAL; 1670 1671 comm_dir = 0; 1672 if (uccf->enabled_tx) 1673 comm_dir |= COMM_DIR_TX; 1674 if (uccf->enabled_rx) 1675 comm_dir |= COMM_DIR_RX; 1676 if (comm_dir) 1677 ugeth_disable(ugeth, comm_dir); 1678 1679 /* Clear the hash table. */ 1680 out_be32(addr_h, 0x00000000); 1681 out_be32(addr_l, 0x00000000); 1682 1683 if (!p_lh) 1684 return 0; 1685 1686 num = *p_counter; 1687 1688 /* Delete all remaining CQ elements */ 1689 for (i = 0; i < num; i++) 1690 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh))); 1691 1692 *p_counter = 0; 1693 1694 if (comm_dir) 1695 ugeth_enable(ugeth, comm_dir); 1696 1697 return 0; 1698} 1699 1700static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth, 1701 u8 paddr_num) 1702{ 1703 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */ 1704 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */ 1705} 1706 1707static void ucc_geth_free_rx(struct ucc_geth_private *ugeth) 1708{ 1709 struct ucc_geth_info *ug_info; 1710 struct ucc_fast_info *uf_info; 1711 u16 i, j; 1712 u8 __iomem *bd; 1713 1714 1715 ug_info = ugeth->ug_info; 1716 uf_info = &ug_info->uf_info; 1717 1718 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) { 1719 if (ugeth->p_rx_bd_ring[i]) { 1720 /* Return existing data buffers in ring */ 1721 bd = ugeth->p_rx_bd_ring[i]; 1722 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) { 1723 if (ugeth->rx_skbuff[i][j]) { 1724 dma_unmap_single(ugeth->dev, 1725 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1726 ugeth->ug_info-> 1727 uf_info.max_rx_buf_length + 1728 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 1729 DMA_FROM_DEVICE); 1730 dev_kfree_skb_any( 1731 ugeth->rx_skbuff[i][j]); 1732 ugeth->rx_skbuff[i][j] = NULL; 1733 } 1734 bd += sizeof(struct qe_bd); 1735 } 1736 1737 kfree(ugeth->rx_skbuff[i]); 1738 1739 kfree(ugeth->p_rx_bd_ring[i]); 1740 ugeth->p_rx_bd_ring[i] = NULL; 1741 } 1742 } 1743 1744} 1745 1746static void ucc_geth_free_tx(struct ucc_geth_private *ugeth) 1747{ 1748 struct ucc_geth_info *ug_info; 1749 struct ucc_fast_info *uf_info; 1750 u16 i, j; 1751 u8 __iomem *bd; 1752 1753 netdev_reset_queue(ugeth->ndev); 1754 1755 ug_info = ugeth->ug_info; 1756 uf_info = &ug_info->uf_info; 1757 1758 for (i = 0; i < ucc_geth_tx_queues(ugeth->ug_info); i++) { 1759 bd = ugeth->p_tx_bd_ring[i]; 1760 if (!bd) 1761 continue; 1762 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) { 1763 if (ugeth->tx_skbuff[i][j]) { 1764 dma_unmap_single(ugeth->dev, 1765 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1766 (in_be32((u32 __iomem *)bd) & 1767 BD_LENGTH_MASK), 1768 DMA_TO_DEVICE); 1769 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]); 1770 ugeth->tx_skbuff[i][j] = NULL; 1771 } 1772 } 1773 1774 kfree(ugeth->tx_skbuff[i]); 1775 1776 kfree(ugeth->p_tx_bd_ring[i]); 1777 ugeth->p_tx_bd_ring[i] = NULL; 1778 } 1779 1780} 1781 1782static void ucc_geth_memclean(struct ucc_geth_private *ugeth) 1783{ 1784 if (!ugeth) 1785 return; 1786 1787 if (ugeth->uccf) { 1788 ucc_fast_free(ugeth->uccf); 1789 ugeth->uccf = NULL; 1790 } 1791 1792 qe_muram_free_addr(ugeth->p_thread_data_tx); 1793 ugeth->p_thread_data_tx = NULL; 1794 1795 qe_muram_free_addr(ugeth->p_thread_data_rx); 1796 ugeth->p_thread_data_rx = NULL; 1797 1798 qe_muram_free_addr(ugeth->p_exf_glbl_param); 1799 ugeth->p_exf_glbl_param = NULL; 1800 1801 qe_muram_free_addr(ugeth->p_rx_glbl_pram); 1802 ugeth->p_rx_glbl_pram = NULL; 1803 1804 qe_muram_free_addr(ugeth->p_tx_glbl_pram); 1805 ugeth->p_tx_glbl_pram = NULL; 1806 1807 qe_muram_free_addr(ugeth->p_send_q_mem_reg); 1808 ugeth->p_send_q_mem_reg = NULL; 1809 1810 qe_muram_free_addr(ugeth->p_scheduler); 1811 ugeth->p_scheduler = NULL; 1812 1813 qe_muram_free_addr(ugeth->p_tx_fw_statistics_pram); 1814 ugeth->p_tx_fw_statistics_pram = NULL; 1815 1816 qe_muram_free_addr(ugeth->p_rx_fw_statistics_pram); 1817 ugeth->p_rx_fw_statistics_pram = NULL; 1818 1819 qe_muram_free_addr(ugeth->p_rx_irq_coalescing_tbl); 1820 ugeth->p_rx_irq_coalescing_tbl = NULL; 1821 1822 qe_muram_free_addr(ugeth->p_rx_bd_qs_tbl); 1823 ugeth->p_rx_bd_qs_tbl = NULL; 1824 1825 if (ugeth->p_init_enet_param_shadow) { 1826 return_init_enet_entries(ugeth, 1827 &(ugeth->p_init_enet_param_shadow-> 1828 rxthread[0]), 1829 ENET_INIT_PARAM_MAX_ENTRIES_RX, 1830 ugeth->ug_info->riscRx, 1); 1831 return_init_enet_entries(ugeth, 1832 &(ugeth->p_init_enet_param_shadow-> 1833 txthread[0]), 1834 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1835 ugeth->ug_info->riscTx, 0); 1836 kfree(ugeth->p_init_enet_param_shadow); 1837 ugeth->p_init_enet_param_shadow = NULL; 1838 } 1839 ucc_geth_free_tx(ugeth); 1840 ucc_geth_free_rx(ugeth); 1841 while (!list_empty(&ugeth->group_hash_q)) 1842 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1843 (dequeue(&ugeth->group_hash_q))); 1844 while (!list_empty(&ugeth->ind_hash_q)) 1845 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1846 (dequeue(&ugeth->ind_hash_q))); 1847 if (ugeth->ug_regs) { 1848 iounmap(ugeth->ug_regs); 1849 ugeth->ug_regs = NULL; 1850 } 1851} 1852 1853static void ucc_geth_set_multi(struct net_device *dev) 1854{ 1855 struct ucc_geth_private *ugeth; 1856 struct netdev_hw_addr *ha; 1857 struct ucc_fast __iomem *uf_regs; 1858 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 1859 1860 ugeth = netdev_priv(dev); 1861 1862 uf_regs = ugeth->uccf->uf_regs; 1863 1864 if (dev->flags & IFF_PROMISC) { 1865 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 1866 } else { 1867 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 1868 1869 p_82xx_addr_filt = 1870 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 1871 p_rx_glbl_pram->addressfiltering; 1872 1873 if (dev->flags & IFF_ALLMULTI) { 1874 /* Catch all multicast addresses, so set the 1875 * filter to all 1's. 1876 */ 1877 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff); 1878 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff); 1879 } else { 1880 /* Clear filter and add the addresses in the list. 1881 */ 1882 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0); 1883 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0); 1884 1885 netdev_for_each_mc_addr(ha, dev) { 1886 /* Ask CPM to run CRC and set bit in 1887 * filter mask. 1888 */ 1889 hw_add_addr_in_hash(ugeth, ha->addr); 1890 } 1891 } 1892 } 1893} 1894 1895static void ucc_geth_stop(struct ucc_geth_private *ugeth) 1896{ 1897 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 1898 1899 ugeth_vdbg("%s: IN", __func__); 1900 1901 /* 1902 * Tell the kernel the link is down. 1903 * Must be done before disabling the controller 1904 * or deadlock may happen. 1905 */ 1906 phylink_stop(ugeth->phylink); 1907 1908 /* Disable the controller */ 1909 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 1910 1911 /* Mask all interrupts */ 1912 out_be32(ugeth->uccf->p_uccm, 0x00000000); 1913 1914 /* Clear all interrupts */ 1915 out_be32(ugeth->uccf->p_ucce, 0xffffffff); 1916 1917 /* Disable Rx and Tx */ 1918 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 1919 1920 ucc_geth_memclean(ugeth); 1921} 1922 1923static int ucc_struct_init(struct ucc_geth_private *ugeth) 1924{ 1925 struct ucc_geth_info *ug_info; 1926 struct ucc_fast_info *uf_info; 1927 int i; 1928 1929 ug_info = ugeth->ug_info; 1930 uf_info = &ug_info->uf_info; 1931 1932 /* Rx BD lengths */ 1933 for (i = 0; i < ucc_geth_rx_queues(ug_info); i++) { 1934 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) || 1935 (ug_info->bdRingLenRx[i] % 1936 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) { 1937 if (netif_msg_probe(ugeth)) 1938 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n"); 1939 return -EINVAL; 1940 } 1941 } 1942 1943 /* Tx BD lengths */ 1944 for (i = 0; i < ucc_geth_tx_queues(ug_info); i++) { 1945 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) { 1946 if (netif_msg_probe(ugeth)) 1947 pr_err("Tx BD ring length must be no smaller than 2\n"); 1948 return -EINVAL; 1949 } 1950 } 1951 1952 /* mrblr */ 1953 if ((uf_info->max_rx_buf_length == 0) || 1954 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) { 1955 if (netif_msg_probe(ugeth)) 1956 pr_err("max_rx_buf_length must be non-zero multiple of 128\n"); 1957 return -EINVAL; 1958 } 1959 1960 /* num Tx queues */ 1961 if (ucc_geth_tx_queues(ug_info) > NUM_TX_QUEUES) { 1962 if (netif_msg_probe(ugeth)) 1963 pr_err("number of tx queues too large\n"); 1964 return -EINVAL; 1965 } 1966 1967 /* num Rx queues */ 1968 if (ucc_geth_rx_queues(ug_info) > NUM_RX_QUEUES) { 1969 if (netif_msg_probe(ugeth)) 1970 pr_err("number of rx queues too large\n"); 1971 return -EINVAL; 1972 } 1973 1974 /* l2qt */ 1975 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) { 1976 if (ug_info->l2qt[i] >= ucc_geth_rx_queues(ug_info)) { 1977 if (netif_msg_probe(ugeth)) 1978 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n"); 1979 return -EINVAL; 1980 } 1981 } 1982 1983 /* l3qt */ 1984 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) { 1985 if (ug_info->l3qt[i] >= ucc_geth_rx_queues(ug_info)) { 1986 if (netif_msg_probe(ugeth)) 1987 pr_err("IP priority table entry must not be larger than number of Rx queues\n"); 1988 return -EINVAL; 1989 } 1990 } 1991 1992 if (ug_info->cam && !ug_info->ecamptr) { 1993 if (netif_msg_probe(ugeth)) 1994 pr_err("If cam mode is chosen, must supply cam ptr\n"); 1995 return -EINVAL; 1996 } 1997 1998 if ((ug_info->numStationAddresses != 1999 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) && 2000 ug_info->rxExtendedFiltering) { 2001 if (netif_msg_probe(ugeth)) 2002 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n"); 2003 return -EINVAL; 2004 } 2005 2006 /* Generate uccm_mask for receive */ 2007 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ 2008 for (i = 0; i < ucc_geth_rx_queues(ug_info); i++) 2009 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); 2010 2011 for (i = 0; i < ucc_geth_tx_queues(ug_info); i++) 2012 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); 2013 /* Initialize the general fast UCC block. */ 2014 if (ucc_fast_init(uf_info, &ugeth->uccf)) { 2015 if (netif_msg_probe(ugeth)) 2016 pr_err("Failed to init uccf\n"); 2017 return -ENOMEM; 2018 } 2019 2020 /* read the number of risc engines, update the riscTx and riscRx 2021 * if there are 4 riscs in QE 2022 */ 2023 if (qe_get_num_of_risc() == 4) { 2024 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; 2025 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; 2026 } 2027 2028 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); 2029 if (!ugeth->ug_regs) { 2030 if (netif_msg_probe(ugeth)) 2031 pr_err("Failed to ioremap regs\n"); 2032 return -ENOMEM; 2033 } 2034 2035 return 0; 2036} 2037 2038static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth) 2039{ 2040 struct ucc_geth_info *ug_info; 2041 struct ucc_fast_info *uf_info; 2042 int length; 2043 u16 i, j; 2044 u8 __iomem *bd; 2045 2046 ug_info = ugeth->ug_info; 2047 uf_info = &ug_info->uf_info; 2048 2049 /* Allocate Tx bds */ 2050 for (j = 0; j < ucc_geth_tx_queues(ug_info); j++) { 2051 u32 align = max(UCC_GETH_TX_BD_RING_ALIGNMENT, 2052 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT); 2053 u32 alloc; 2054 2055 length = ug_info->bdRingLenTx[j] * sizeof(struct qe_bd); 2056 alloc = round_up(length, align); 2057 alloc = roundup_pow_of_two(alloc); 2058 2059 ugeth->p_tx_bd_ring[j] = kmalloc(alloc, GFP_KERNEL); 2060 2061 if (!ugeth->p_tx_bd_ring[j]) { 2062 if (netif_msg_ifup(ugeth)) 2063 pr_err("Can not allocate memory for Tx bd rings\n"); 2064 return -ENOMEM; 2065 } 2066 /* Zero unused end of bd ring, according to spec */ 2067 memset(ugeth->p_tx_bd_ring[j] + length, 0, alloc - length); 2068 } 2069 2070 /* Init Tx bds */ 2071 for (j = 0; j < ucc_geth_tx_queues(ug_info); j++) { 2072 /* Setup the skbuff rings */ 2073 ugeth->tx_skbuff[j] = 2074 kcalloc(ugeth->ug_info->bdRingLenTx[j], 2075 sizeof(struct sk_buff *), GFP_KERNEL); 2076 2077 if (ugeth->tx_skbuff[j] == NULL) { 2078 if (netif_msg_ifup(ugeth)) 2079 pr_err("Could not allocate tx_skbuff\n"); 2080 return -ENOMEM; 2081 } 2082 2083 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0; 2084 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j]; 2085 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) { 2086 /* clear bd buffer */ 2087 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2088 /* set bd status and length */ 2089 out_be32((u32 __iomem *)bd, 0); 2090 bd += sizeof(struct qe_bd); 2091 } 2092 bd -= sizeof(struct qe_bd); 2093 /* set bd status and length */ 2094 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */ 2095 } 2096 2097 return 0; 2098} 2099 2100static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth) 2101{ 2102 struct ucc_geth_info *ug_info; 2103 struct ucc_fast_info *uf_info; 2104 int length; 2105 u16 i, j; 2106 u8 __iomem *bd; 2107 2108 ug_info = ugeth->ug_info; 2109 uf_info = &ug_info->uf_info; 2110 2111 /* Allocate Rx bds */ 2112 for (j = 0; j < ucc_geth_rx_queues(ug_info); j++) { 2113 u32 align = UCC_GETH_RX_BD_RING_ALIGNMENT; 2114 u32 alloc; 2115 2116 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd); 2117 alloc = round_up(length, align); 2118 alloc = roundup_pow_of_two(alloc); 2119 2120 ugeth->p_rx_bd_ring[j] = kmalloc(alloc, GFP_KERNEL); 2121 if (!ugeth->p_rx_bd_ring[j]) { 2122 if (netif_msg_ifup(ugeth)) 2123 pr_err("Can not allocate memory for Rx bd rings\n"); 2124 return -ENOMEM; 2125 } 2126 } 2127 2128 /* Init Rx bds */ 2129 for (j = 0; j < ucc_geth_rx_queues(ug_info); j++) { 2130 /* Setup the skbuff rings */ 2131 ugeth->rx_skbuff[j] = 2132 kcalloc(ugeth->ug_info->bdRingLenRx[j], 2133 sizeof(struct sk_buff *), GFP_KERNEL); 2134 2135 if (ugeth->rx_skbuff[j] == NULL) { 2136 if (netif_msg_ifup(ugeth)) 2137 pr_err("Could not allocate rx_skbuff\n"); 2138 return -ENOMEM; 2139 } 2140 2141 ugeth->skb_currx[j] = 0; 2142 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j]; 2143 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) { 2144 /* set bd status and length */ 2145 out_be32((u32 __iomem *)bd, R_I); 2146 /* clear bd buffer */ 2147 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2148 bd += sizeof(struct qe_bd); 2149 } 2150 bd -= sizeof(struct qe_bd); 2151 /* set bd status and length */ 2152 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */ 2153 } 2154 2155 return 0; 2156} 2157 2158static int ucc_geth_startup(struct ucc_geth_private *ugeth) 2159{ 2160 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2161 struct ucc_geth_init_pram __iomem *p_init_enet_pram; 2162 struct ucc_fast_private *uccf; 2163 struct ucc_geth_info *ug_info; 2164 struct ucc_fast_info *uf_info; 2165 struct ucc_fast __iomem *uf_regs; 2166 struct ucc_geth __iomem *ug_regs; 2167 int ret_val = -EINVAL; 2168 u32 remoder = UCC_GETH_REMODER_INIT; 2169 u32 init_enet_pram_offset, cecr_subblock, command; 2170 u32 ifstat, i, j, size, l2qt, l3qt; 2171 u16 temoder = UCC_GETH_TEMODER_INIT; 2172 u8 function_code = 0; 2173 u8 __iomem *endOfRing; 2174 u8 numThreadsRxNumerical, numThreadsTxNumerical; 2175 s32 rx_glbl_pram_offset, tx_glbl_pram_offset; 2176 2177 ugeth_vdbg("%s: IN", __func__); 2178 uccf = ugeth->uccf; 2179 ug_info = ugeth->ug_info; 2180 uf_info = &ug_info->uf_info; 2181 uf_regs = uccf->uf_regs; 2182 ug_regs = ugeth->ug_regs; 2183 2184 numThreadsRxNumerical = ucc_geth_thread_count(ug_info->numThreadsRx); 2185 if (!numThreadsRxNumerical) { 2186 if (netif_msg_ifup(ugeth)) 2187 pr_err("Bad number of Rx threads value\n"); 2188 return -EINVAL; 2189 } 2190 2191 numThreadsTxNumerical = ucc_geth_thread_count(ug_info->numThreadsTx); 2192 if (!numThreadsTxNumerical) { 2193 if (netif_msg_ifup(ugeth)) 2194 pr_err("Bad number of Tx threads value\n"); 2195 return -EINVAL; 2196 } 2197 2198 /* Calculate rx_extended_features */ 2199 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck || 2200 ug_info->ipAddressAlignment || 2201 (ug_info->numStationAddresses != 2202 UCC_GETH_NUM_OF_STATION_ADDRESSES_1); 2203 2204 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features || 2205 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) || 2206 (ug_info->vlanOperationNonTagged != 2207 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP); 2208 2209 init_default_reg_vals(&uf_regs->upsmr, 2210 &ug_regs->maccfg1, &ug_regs->maccfg2); 2211 2212 /* Set UPSMR */ 2213 /* For more details see the hardware spec. */ 2214 init_rx_parameters(ug_info->bro, 2215 ug_info->rsh, ug_info->pro, &uf_regs->upsmr); 2216 2217 /* We're going to ignore other registers for now, */ 2218 /* except as needed to get up and running */ 2219 2220 /* Set MACCFG1 */ 2221 /* For more details see the hardware spec. */ 2222 init_flow_control_params(ug_info->aufc, 2223 ug_info->receiveFlowControl, 2224 ug_info->transmitFlowControl, 2225 ug_info->pausePeriod, 2226 ug_info->extensionField, 2227 &uf_regs->upsmr, 2228 &ug_regs->uempr, &ug_regs->maccfg1); 2229 2230 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2231 2232 /* Set IPGIFG */ 2233 /* For more details see the hardware spec. */ 2234 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1, 2235 ug_info->nonBackToBackIfgPart2, 2236 ug_info-> 2237 miminumInterFrameGapEnforcement, 2238 ug_info->backToBackInterFrameGap, 2239 &ug_regs->ipgifg); 2240 if (ret_val != 0) { 2241 if (netif_msg_ifup(ugeth)) 2242 pr_err("IPGIFG initialization parameter too large\n"); 2243 return ret_val; 2244 } 2245 2246 /* Set HAFDUP */ 2247 /* For more details see the hardware spec. */ 2248 ret_val = init_half_duplex_params(ug_info->altBeb, 2249 ug_info->backPressureNoBackoff, 2250 ug_info->noBackoff, 2251 ug_info->excessDefer, 2252 ug_info->altBebTruncation, 2253 ug_info->maxRetransmission, 2254 ug_info->collisionWindow, 2255 &ug_regs->hafdup); 2256 if (ret_val != 0) { 2257 if (netif_msg_ifup(ugeth)) 2258 pr_err("Half Duplex initialization parameter too large\n"); 2259 return ret_val; 2260 } 2261 2262 /* Set IFSTAT */ 2263 /* For more details see the hardware spec. */ 2264 /* Read only - resets upon read */ 2265 ifstat = in_be32(&ug_regs->ifstat); 2266 2267 /* Clear UEMPR */ 2268 /* For more details see the hardware spec. */ 2269 out_be32(&ug_regs->uempr, 0); 2270 2271 /* Set UESCR */ 2272 /* For more details see the hardware spec. */ 2273 init_hw_statistics_gathering_mode((ug_info->statisticsMode & 2274 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE), 2275 0, &uf_regs->upsmr, &ug_regs->uescr); 2276 2277 ret_val = ucc_geth_alloc_tx(ugeth); 2278 if (ret_val != 0) 2279 return ret_val; 2280 2281 ret_val = ucc_geth_alloc_rx(ugeth); 2282 if (ret_val != 0) 2283 return ret_val; 2284 2285 /* 2286 * Global PRAM 2287 */ 2288 /* Tx global PRAM */ 2289 /* Allocate global tx parameter RAM page */ 2290 tx_glbl_pram_offset = 2291 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram), 2292 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT); 2293 if (tx_glbl_pram_offset < 0) { 2294 if (netif_msg_ifup(ugeth)) 2295 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n"); 2296 return -ENOMEM; 2297 } 2298 ugeth->p_tx_glbl_pram = qe_muram_addr(tx_glbl_pram_offset); 2299 /* Fill global PRAM */ 2300 2301 /* TQPTR */ 2302 /* Size varies with number of Tx threads */ 2303 ugeth->thread_dat_tx_offset = 2304 qe_muram_alloc(numThreadsTxNumerical * 2305 sizeof(struct ucc_geth_thread_data_tx) + 2306 32 * (numThreadsTxNumerical == 1), 2307 UCC_GETH_THREAD_DATA_ALIGNMENT); 2308 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) { 2309 if (netif_msg_ifup(ugeth)) 2310 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n"); 2311 return -ENOMEM; 2312 } 2313 2314 ugeth->p_thread_data_tx = 2315 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth-> 2316 thread_dat_tx_offset); 2317 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset); 2318 2319 /* vtagtable */ 2320 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++) 2321 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i], 2322 ug_info->vtagtable[i]); 2323 2324 /* iphoffset */ 2325 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++) 2326 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i], 2327 ug_info->iphoffset[i]); 2328 2329 /* SQPTR */ 2330 /* Size varies with number of Tx queues */ 2331 ugeth->send_q_mem_reg_offset = 2332 qe_muram_alloc(ucc_geth_tx_queues(ug_info) * 2333 sizeof(struct ucc_geth_send_queue_qd), 2334 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); 2335 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) { 2336 if (netif_msg_ifup(ugeth)) 2337 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n"); 2338 return -ENOMEM; 2339 } 2340 2341 ugeth->p_send_q_mem_reg = 2342 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth-> 2343 send_q_mem_reg_offset); 2344 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset); 2345 2346 /* Setup the table */ 2347 /* Assume BD rings are already established */ 2348 for (i = 0; i < ucc_geth_tx_queues(ug_info); i++) { 2349 endOfRing = 2350 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] - 2351 1) * sizeof(struct qe_bd); 2352 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2353 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i])); 2354 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2355 last_bd_completed_address, 2356 (u32) virt_to_phys(endOfRing)); 2357 } 2358 2359 /* schedulerbasepointer */ 2360 2361 if (ucc_geth_tx_queues(ug_info) > 1) { 2362 /* scheduler exists only if more than 1 tx queue */ 2363 ugeth->scheduler_offset = 2364 qe_muram_alloc(sizeof(struct ucc_geth_scheduler), 2365 UCC_GETH_SCHEDULER_ALIGNMENT); 2366 if (IS_ERR_VALUE(ugeth->scheduler_offset)) { 2367 if (netif_msg_ifup(ugeth)) 2368 pr_err("Can not allocate DPRAM memory for p_scheduler\n"); 2369 return -ENOMEM; 2370 } 2371 2372 ugeth->p_scheduler = 2373 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth-> 2374 scheduler_offset); 2375 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer, 2376 ugeth->scheduler_offset); 2377 2378 /* Set values in scheduler */ 2379 out_be32(&ugeth->p_scheduler->mblinterval, 2380 ug_info->mblinterval); 2381 out_be16(&ugeth->p_scheduler->nortsrbytetime, 2382 ug_info->nortsrbytetime); 2383 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz); 2384 out_8(&ugeth->p_scheduler->strictpriorityq, 2385 ug_info->strictpriorityq); 2386 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap); 2387 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw); 2388 for (i = 0; i < NUM_TX_QUEUES; i++) 2389 out_8(&ugeth->p_scheduler->weightfactor[i], 2390 ug_info->weightfactor[i]); 2391 2392 /* Set pointers to cpucount registers in scheduler */ 2393 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0); 2394 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1); 2395 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2); 2396 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3); 2397 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4); 2398 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5); 2399 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6); 2400 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7); 2401 } 2402 2403 /* schedulerbasepointer */ 2404 /* TxRMON_PTR (statistics) */ 2405 if (ug_info-> 2406 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) { 2407 ugeth->tx_fw_statistics_pram_offset = 2408 qe_muram_alloc(sizeof 2409 (struct ucc_geth_tx_firmware_statistics_pram), 2410 UCC_GETH_TX_STATISTICS_ALIGNMENT); 2411 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) { 2412 if (netif_msg_ifup(ugeth)) 2413 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n"); 2414 return -ENOMEM; 2415 } 2416 ugeth->p_tx_fw_statistics_pram = 2417 (struct ucc_geth_tx_firmware_statistics_pram __iomem *) 2418 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset); 2419 } 2420 2421 /* temoder */ 2422 /* Already has speed set */ 2423 2424 if (ucc_geth_tx_queues(ug_info) > 1) 2425 temoder |= TEMODER_SCHEDULER_ENABLE; 2426 if (ug_info->ipCheckSumGenerate) 2427 temoder |= TEMODER_IP_CHECKSUM_GENERATE; 2428 temoder |= ((ucc_geth_tx_queues(ug_info) - 1) << TEMODER_NUM_OF_QUEUES_SHIFT); 2429 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder); 2430 2431 /* Function code register value to be used later */ 2432 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL; 2433 /* Required for QE */ 2434 2435 /* function code register */ 2436 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24); 2437 2438 /* Rx global PRAM */ 2439 /* Allocate global rx parameter RAM page */ 2440 rx_glbl_pram_offset = 2441 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram), 2442 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT); 2443 if (rx_glbl_pram_offset < 0) { 2444 if (netif_msg_ifup(ugeth)) 2445 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n"); 2446 return -ENOMEM; 2447 } 2448 ugeth->p_rx_glbl_pram = qe_muram_addr(rx_glbl_pram_offset); 2449 /* Fill global PRAM */ 2450 2451 /* RQPTR */ 2452 /* Size varies with number of Rx threads */ 2453 ugeth->thread_dat_rx_offset = 2454 qe_muram_alloc(numThreadsRxNumerical * 2455 sizeof(struct ucc_geth_thread_data_rx), 2456 UCC_GETH_THREAD_DATA_ALIGNMENT); 2457 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) { 2458 if (netif_msg_ifup(ugeth)) 2459 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n"); 2460 return -ENOMEM; 2461 } 2462 2463 ugeth->p_thread_data_rx = 2464 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth-> 2465 thread_dat_rx_offset); 2466 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset); 2467 2468 /* typeorlen */ 2469 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen); 2470 2471 /* rxrmonbaseptr (statistics) */ 2472 if (ug_info-> 2473 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) { 2474 ugeth->rx_fw_statistics_pram_offset = 2475 qe_muram_alloc(sizeof 2476 (struct ucc_geth_rx_firmware_statistics_pram), 2477 UCC_GETH_RX_STATISTICS_ALIGNMENT); 2478 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) { 2479 if (netif_msg_ifup(ugeth)) 2480 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n"); 2481 return -ENOMEM; 2482 } 2483 ugeth->p_rx_fw_statistics_pram = 2484 (struct ucc_geth_rx_firmware_statistics_pram __iomem *) 2485 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset); 2486 } 2487 2488 /* intCoalescingPtr */ 2489 2490 /* Size varies with number of Rx queues */ 2491 ugeth->rx_irq_coalescing_tbl_offset = 2492 qe_muram_alloc(ucc_geth_rx_queues(ug_info) * 2493 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry) 2494 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT); 2495 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) { 2496 if (netif_msg_ifup(ugeth)) 2497 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n"); 2498 return -ENOMEM; 2499 } 2500 2501 ugeth->p_rx_irq_coalescing_tbl = 2502 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *) 2503 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset); 2504 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr, 2505 ugeth->rx_irq_coalescing_tbl_offset); 2506 2507 /* Fill interrupt coalescing table */ 2508 for (i = 0; i < ucc_geth_rx_queues(ug_info); i++) { 2509 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2510 interruptcoalescingmaxvalue, 2511 ug_info->interruptcoalescingmaxvalue[i]); 2512 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2513 interruptcoalescingcounter, 2514 ug_info->interruptcoalescingmaxvalue[i]); 2515 } 2516 2517 /* MRBLR */ 2518 init_max_rx_buff_len(uf_info->max_rx_buf_length, 2519 &ugeth->p_rx_glbl_pram->mrblr); 2520 /* MFLR */ 2521 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength); 2522 /* MINFLR */ 2523 init_min_frame_len(ug_info->minFrameLength, 2524 &ugeth->p_rx_glbl_pram->minflr, 2525 &ugeth->p_rx_glbl_pram->mrblr); 2526 /* MAXD1 */ 2527 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length); 2528 /* MAXD2 */ 2529 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length); 2530 2531 /* l2qt */ 2532 l2qt = 0; 2533 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) 2534 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i)); 2535 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt); 2536 2537 /* l3qt */ 2538 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) { 2539 l3qt = 0; 2540 for (i = 0; i < 8; i++) 2541 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i)); 2542 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt); 2543 } 2544 2545 /* vlantype */ 2546 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype); 2547 2548 /* vlantci */ 2549 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci); 2550 2551 /* ecamptr */ 2552 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr); 2553 2554 /* RBDQPTR */ 2555 /* Size varies with number of Rx queues */ 2556 ugeth->rx_bd_qs_tbl_offset = 2557 qe_muram_alloc(ucc_geth_rx_queues(ug_info) * 2558 (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2559 sizeof(struct ucc_geth_rx_prefetched_bds)), 2560 UCC_GETH_RX_BD_QUEUES_ALIGNMENT); 2561 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) { 2562 if (netif_msg_ifup(ugeth)) 2563 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n"); 2564 return -ENOMEM; 2565 } 2566 2567 ugeth->p_rx_bd_qs_tbl = 2568 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth-> 2569 rx_bd_qs_tbl_offset); 2570 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset); 2571 2572 /* Setup the table */ 2573 /* Assume BD rings are already established */ 2574 for (i = 0; i < ucc_geth_rx_queues(ug_info); i++) { 2575 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2576 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i])); 2577 /* rest of fields handled by QE */ 2578 } 2579 2580 /* remoder */ 2581 /* Already has speed set */ 2582 2583 if (ugeth->rx_extended_features) 2584 remoder |= REMODER_RX_EXTENDED_FEATURES; 2585 if (ug_info->rxExtendedFiltering) 2586 remoder |= REMODER_RX_EXTENDED_FILTERING; 2587 if (ug_info->dynamicMaxFrameLength) 2588 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH; 2589 if (ug_info->dynamicMinFrameLength) 2590 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH; 2591 remoder |= 2592 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT; 2593 remoder |= 2594 ug_info-> 2595 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT; 2596 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT; 2597 remoder |= ((ucc_geth_rx_queues(ug_info) - 1) << REMODER_NUM_OF_QUEUES_SHIFT); 2598 if (ug_info->ipCheckSumCheck) 2599 remoder |= REMODER_IP_CHECKSUM_CHECK; 2600 if (ug_info->ipAddressAlignment) 2601 remoder |= REMODER_IP_ADDRESS_ALIGNMENT; 2602 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder); 2603 2604 /* Note that this function must be called */ 2605 /* ONLY AFTER p_tx_fw_statistics_pram */ 2606 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */ 2607 init_firmware_statistics_gathering_mode((ug_info-> 2608 statisticsMode & 2609 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX), 2610 (ug_info->statisticsMode & 2611 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX), 2612 &ugeth->p_tx_glbl_pram->txrmonbaseptr, 2613 ugeth->tx_fw_statistics_pram_offset, 2614 &ugeth->p_rx_glbl_pram->rxrmonbaseptr, 2615 ugeth->rx_fw_statistics_pram_offset, 2616 &ugeth->p_tx_glbl_pram->temoder, 2617 &ugeth->p_rx_glbl_pram->remoder); 2618 2619 /* function code register */ 2620 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code); 2621 2622 /* initialize extended filtering */ 2623 if (ug_info->rxExtendedFiltering) { 2624 if (!ug_info->extendedFilteringChainPointer) { 2625 if (netif_msg_ifup(ugeth)) 2626 pr_err("Null Extended Filtering Chain Pointer\n"); 2627 return -EINVAL; 2628 } 2629 2630 /* Allocate memory for extended filtering Mode Global 2631 Parameters */ 2632 ugeth->exf_glbl_param_offset = 2633 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram), 2634 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT); 2635 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) { 2636 if (netif_msg_ifup(ugeth)) 2637 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n"); 2638 return -ENOMEM; 2639 } 2640 2641 ugeth->p_exf_glbl_param = 2642 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth-> 2643 exf_glbl_param_offset); 2644 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam, 2645 ugeth->exf_glbl_param_offset); 2646 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr, 2647 (u32) ug_info->extendedFilteringChainPointer); 2648 2649 } else { /* initialize 82xx style address filtering */ 2650 2651 /* Init individual address recognition registers to disabled */ 2652 2653 for (j = 0; j < NUM_OF_PADDRS; j++) 2654 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j); 2655 2656 p_82xx_addr_filt = 2657 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2658 p_rx_glbl_pram->addressfiltering; 2659 2660 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2661 ENET_ADDR_TYPE_GROUP); 2662 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2663 ENET_ADDR_TYPE_INDIVIDUAL); 2664 } 2665 2666 /* 2667 * Initialize UCC at QE level 2668 */ 2669 2670 command = QE_INIT_TX_RX; 2671 2672 /* Allocate shadow InitEnet command parameter structure. 2673 * This is needed because after the InitEnet command is executed, 2674 * the structure in DPRAM is released, because DPRAM is a premium 2675 * resource. 2676 * This shadow structure keeps a copy of what was done so that the 2677 * allocated resources can be released when the channel is freed. 2678 */ 2679 if (!(ugeth->p_init_enet_param_shadow = 2680 kzalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) { 2681 if (netif_msg_ifup(ugeth)) 2682 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n"); 2683 return -ENOMEM; 2684 } 2685 2686 /* Fill shadow InitEnet command parameter structure */ 2687 2688 ugeth->p_init_enet_param_shadow->resinit1 = 2689 ENET_INIT_PARAM_MAGIC_RES_INIT1; 2690 ugeth->p_init_enet_param_shadow->resinit2 = 2691 ENET_INIT_PARAM_MAGIC_RES_INIT2; 2692 ugeth->p_init_enet_param_shadow->resinit3 = 2693 ENET_INIT_PARAM_MAGIC_RES_INIT3; 2694 ugeth->p_init_enet_param_shadow->resinit4 = 2695 ENET_INIT_PARAM_MAGIC_RES_INIT4; 2696 ugeth->p_init_enet_param_shadow->resinit5 = 2697 ENET_INIT_PARAM_MAGIC_RES_INIT5; 2698 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2699 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT; 2700 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2701 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT; 2702 2703 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2704 rx_glbl_pram_offset | ug_info->riscRx; 2705 if ((ug_info->largestexternallookupkeysize != 2706 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) && 2707 (ug_info->largestexternallookupkeysize != 2708 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) && 2709 (ug_info->largestexternallookupkeysize != 2710 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) { 2711 if (netif_msg_ifup(ugeth)) 2712 pr_err("Invalid largest External Lookup Key Size\n"); 2713 return -EINVAL; 2714 } 2715 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize = 2716 ug_info->largestexternallookupkeysize; 2717 size = sizeof(struct ucc_geth_thread_rx_pram); 2718 if (ug_info->rxExtendedFiltering) { 2719 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 2720 if (ug_info->largestexternallookupkeysize == 2721 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 2722 size += 2723 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 2724 if (ug_info->largestexternallookupkeysize == 2725 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 2726 size += 2727 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 2728 } 2729 2730 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth-> 2731 p_init_enet_param_shadow->rxthread[0]), 2732 (u8) (numThreadsRxNumerical + 1) 2733 /* Rx needs one extra for terminator */ 2734 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT, 2735 ug_info->riscRx, 1)) != 0) { 2736 if (netif_msg_ifup(ugeth)) 2737 pr_err("Can not fill p_init_enet_param_shadow\n"); 2738 return ret_val; 2739 } 2740 2741 ugeth->p_init_enet_param_shadow->txglobal = 2742 tx_glbl_pram_offset | ug_info->riscTx; 2743 if ((ret_val = 2744 fill_init_enet_entries(ugeth, 2745 &(ugeth->p_init_enet_param_shadow-> 2746 txthread[0]), numThreadsTxNumerical, 2747 sizeof(struct ucc_geth_thread_tx_pram), 2748 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT, 2749 ug_info->riscTx, 0)) != 0) { 2750 if (netif_msg_ifup(ugeth)) 2751 pr_err("Can not fill p_init_enet_param_shadow\n"); 2752 return ret_val; 2753 } 2754 2755 /* Load Rx bds with buffers */ 2756 for (i = 0; i < ucc_geth_rx_queues(ug_info); i++) { 2757 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) { 2758 if (netif_msg_ifup(ugeth)) 2759 pr_err("Can not fill Rx bds with buffers\n"); 2760 return ret_val; 2761 } 2762 } 2763 2764 /* Allocate InitEnet command parameter structure */ 2765 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4); 2766 if (IS_ERR_VALUE(init_enet_pram_offset)) { 2767 if (netif_msg_ifup(ugeth)) 2768 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n"); 2769 return -ENOMEM; 2770 } 2771 p_init_enet_pram = 2772 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset); 2773 2774 /* Copy shadow InitEnet command parameter structure into PRAM */ 2775 out_8(&p_init_enet_pram->resinit1, 2776 ugeth->p_init_enet_param_shadow->resinit1); 2777 out_8(&p_init_enet_pram->resinit2, 2778 ugeth->p_init_enet_param_shadow->resinit2); 2779 out_8(&p_init_enet_pram->resinit3, 2780 ugeth->p_init_enet_param_shadow->resinit3); 2781 out_8(&p_init_enet_pram->resinit4, 2782 ugeth->p_init_enet_param_shadow->resinit4); 2783 out_be16(&p_init_enet_pram->resinit5, 2784 ugeth->p_init_enet_param_shadow->resinit5); 2785 out_8(&p_init_enet_pram->largestexternallookupkeysize, 2786 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize); 2787 out_be32(&p_init_enet_pram->rgftgfrxglobal, 2788 ugeth->p_init_enet_param_shadow->rgftgfrxglobal); 2789 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++) 2790 out_be32(&p_init_enet_pram->rxthread[i], 2791 ugeth->p_init_enet_param_shadow->rxthread[i]); 2792 out_be32(&p_init_enet_pram->txglobal, 2793 ugeth->p_init_enet_param_shadow->txglobal); 2794 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++) 2795 out_be32(&p_init_enet_pram->txthread[i], 2796 ugeth->p_init_enet_param_shadow->txthread[i]); 2797 2798 /* Issue QE command */ 2799 cecr_subblock = 2800 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 2801 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 2802 init_enet_pram_offset); 2803 2804 /* Free InitEnet command parameter */ 2805 qe_muram_free(init_enet_pram_offset); 2806 2807 return 0; 2808} 2809 2810/* This is called by the kernel when a frame is ready for transmission. */ 2811/* It is pointed to by the dev->hard_start_xmit function pointer */ 2812static netdev_tx_t 2813ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev) 2814{ 2815 struct ucc_geth_private *ugeth = netdev_priv(dev); 2816#ifdef CONFIG_UGETH_TX_ON_DEMAND 2817 struct ucc_fast_private *uccf; 2818#endif 2819 u8 __iomem *bd; /* BD pointer */ 2820 u32 bd_status; 2821 u8 txQ = 0; 2822 unsigned long flags; 2823 2824 ugeth_vdbg("%s: IN", __func__); 2825 2826 netdev_sent_queue(dev, skb->len); 2827 spin_lock_irqsave(&ugeth->lock, flags); 2828 2829 dev->stats.tx_bytes += skb->len; 2830 2831 /* Start from the next BD that should be filled */ 2832 bd = ugeth->txBd[txQ]; 2833 bd_status = in_be32((u32 __iomem *)bd); 2834 /* Save the skb pointer so we can free it later */ 2835 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb; 2836 2837 /* Update the current skb pointer (wrapping if this was the last) */ 2838 ugeth->skb_curtx[txQ] = 2839 (ugeth->skb_curtx[txQ] + 2840 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 2841 2842 /* set up the buffer descriptor */ 2843 out_be32(&((struct qe_bd __iomem *)bd)->buf, 2844 dma_map_single(ugeth->dev, skb->data, 2845 skb->len, DMA_TO_DEVICE)); 2846 2847 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */ 2848 2849 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len; 2850 2851 /* set bd status and length */ 2852 out_be32((u32 __iomem *)bd, bd_status); 2853 2854 /* Move to next BD in the ring */ 2855 if (!(bd_status & T_W)) 2856 bd += sizeof(struct qe_bd); 2857 else 2858 bd = ugeth->p_tx_bd_ring[txQ]; 2859 2860 /* If the next BD still needs to be cleaned up, then the bds 2861 are full. We need to tell the kernel to stop sending us stuff. */ 2862 if (bd == ugeth->confBd[txQ]) { 2863 if (!netif_queue_stopped(dev)) 2864 netif_stop_queue(dev); 2865 } 2866 2867 ugeth->txBd[txQ] = bd; 2868 2869 skb_tx_timestamp(skb); 2870 2871 if (ugeth->p_scheduler) { 2872 ugeth->cpucount[txQ]++; 2873 /* Indicate to QE that there are more Tx bds ready for 2874 transmission */ 2875 /* This is done by writing a running counter of the bd 2876 count to the scheduler PRAM. */ 2877 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]); 2878 } 2879 2880#ifdef CONFIG_UGETH_TX_ON_DEMAND 2881 uccf = ugeth->uccf; 2882 out_be16(uccf->p_utodr, UCC_FAST_TOD); 2883#endif 2884 spin_unlock_irqrestore(&ugeth->lock, flags); 2885 2886 return NETDEV_TX_OK; 2887} 2888 2889static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit) 2890{ 2891 struct sk_buff *skb; 2892 u8 __iomem *bd; 2893 u16 length, howmany = 0; 2894 u32 bd_status; 2895 u8 *bdBuffer; 2896 struct net_device *dev; 2897 2898 ugeth_vdbg("%s: IN", __func__); 2899 2900 dev = ugeth->ndev; 2901 2902 /* collect received buffers */ 2903 bd = ugeth->rxBd[rxQ]; 2904 2905 bd_status = in_be32((u32 __iomem *)bd); 2906 2907 /* while there are received buffers and BD is full (~R_E) */ 2908 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) { 2909 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf); 2910 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4); 2911 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]]; 2912 2913 /* determine whether buffer is first, last, first and last 2914 (single buffer frame) or middle (not first and not last) */ 2915 if (!skb || 2916 (!(bd_status & (R_F | R_L))) || 2917 (bd_status & R_ERRORS_FATAL)) { 2918 if (netif_msg_rx_err(ugeth)) 2919 pr_err("%d: ERROR!!! skb - 0x%08x\n", 2920 __LINE__, (u32)skb); 2921 dev_kfree_skb(skb); 2922 2923 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL; 2924 dev->stats.rx_dropped++; 2925 } else { 2926 dev->stats.rx_packets++; 2927 howmany++; 2928 2929 /* Prep the skb for the packet */ 2930 skb_put(skb, length); 2931 2932 /* Tell the skb what kind of packet this is */ 2933 skb->protocol = eth_type_trans(skb, ugeth->ndev); 2934 2935 dev->stats.rx_bytes += length; 2936 /* Send the packet up the stack */ 2937 netif_receive_skb(skb); 2938 } 2939 2940 skb = get_new_skb(ugeth, bd); 2941 if (!skb) { 2942 if (netif_msg_rx_err(ugeth)) 2943 pr_warn("No Rx Data Buffer\n"); 2944 dev->stats.rx_dropped++; 2945 break; 2946 } 2947 2948 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb; 2949 2950 /* update to point at the next skb */ 2951 ugeth->skb_currx[rxQ] = 2952 (ugeth->skb_currx[rxQ] + 2953 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]); 2954 2955 if (bd_status & R_W) 2956 bd = ugeth->p_rx_bd_ring[rxQ]; 2957 else 2958 bd += sizeof(struct qe_bd); 2959 2960 bd_status = in_be32((u32 __iomem *)bd); 2961 } 2962 2963 ugeth->rxBd[rxQ] = bd; 2964 return howmany; 2965} 2966 2967static int ucc_geth_tx(struct net_device *dev, u8 txQ) 2968{ 2969 /* Start from the next BD that should be filled */ 2970 struct ucc_geth_private *ugeth = netdev_priv(dev); 2971 unsigned int bytes_sent = 0; 2972 int howmany = 0; 2973 u8 __iomem *bd; /* BD pointer */ 2974 u32 bd_status; 2975 2976 bd = ugeth->confBd[txQ]; 2977 bd_status = in_be32((u32 __iomem *)bd); 2978 2979 /* Normal processing. */ 2980 while ((bd_status & T_R) == 0) { 2981 struct sk_buff *skb; 2982 2983 /* BD contains already transmitted buffer. */ 2984 /* Handle the transmitted buffer and release */ 2985 /* the BD to be used with the current frame */ 2986 2987 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]; 2988 if (!skb) 2989 break; 2990 howmany++; 2991 bytes_sent += skb->len; 2992 dev->stats.tx_packets++; 2993 2994 dev_consume_skb_any(skb); 2995 2996 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL; 2997 ugeth->skb_dirtytx[txQ] = 2998 (ugeth->skb_dirtytx[txQ] + 2999 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3000 3001 /* We freed a buffer, so now we can restart transmission */ 3002 if (netif_queue_stopped(dev)) 3003 netif_wake_queue(dev); 3004 3005 /* Advance the confirmation BD pointer */ 3006 if (!(bd_status & T_W)) 3007 bd += sizeof(struct qe_bd); 3008 else 3009 bd = ugeth->p_tx_bd_ring[txQ]; 3010 bd_status = in_be32((u32 __iomem *)bd); 3011 } 3012 ugeth->confBd[txQ] = bd; 3013 netdev_completed_queue(dev, howmany, bytes_sent); 3014 return 0; 3015} 3016 3017static int ucc_geth_poll(struct napi_struct *napi, int budget) 3018{ 3019 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3020 struct ucc_geth_info *ug_info; 3021 int howmany, i; 3022 3023 ug_info = ugeth->ug_info; 3024 3025 /* Tx event processing */ 3026 spin_lock(&ugeth->lock); 3027 for (i = 0; i < ucc_geth_tx_queues(ug_info); i++) 3028 ucc_geth_tx(ugeth->ndev, i); 3029 spin_unlock(&ugeth->lock); 3030 3031 howmany = 0; 3032 for (i = 0; i < ucc_geth_rx_queues(ug_info); i++) 3033 howmany += ucc_geth_rx(ugeth, i, budget - howmany); 3034 3035 if (howmany < budget) { 3036 napi_complete_done(napi, howmany); 3037 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3038 } 3039 3040 return howmany; 3041} 3042 3043static irqreturn_t ucc_geth_irq_handler(int irq, void *info) 3044{ 3045 struct net_device *dev = info; 3046 struct ucc_geth_private *ugeth = netdev_priv(dev); 3047 struct ucc_fast_private *uccf; 3048 struct ucc_geth_info *ug_info; 3049 register u32 ucce; 3050 register u32 uccm; 3051 3052 ugeth_vdbg("%s: IN", __func__); 3053 3054 uccf = ugeth->uccf; 3055 ug_info = ugeth->ug_info; 3056 3057 /* read and clear events */ 3058 ucce = (u32) in_be32(uccf->p_ucce); 3059 uccm = (u32) in_be32(uccf->p_uccm); 3060 ucce &= uccm; 3061 out_be32(uccf->p_ucce, ucce); 3062 3063 /* check for receive events that require processing */ 3064 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) { 3065 if (napi_schedule_prep(&ugeth->napi)) { 3066 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3067 out_be32(uccf->p_uccm, uccm); 3068 __napi_schedule(&ugeth->napi); 3069 } 3070 } 3071 3072 /* Errors and other events */ 3073 if (ucce & UCCE_OTHER) { 3074 if (ucce & UCC_GETH_UCCE_BSY) 3075 dev->stats.rx_errors++; 3076 if (ucce & UCC_GETH_UCCE_TXE) 3077 dev->stats.tx_errors++; 3078 } 3079 3080 return IRQ_HANDLED; 3081} 3082 3083#ifdef CONFIG_NET_POLL_CONTROLLER 3084/* 3085 * Polling 'interrupt' - used by things like netconsole to send skbs 3086 * without having to re-enable interrupts. It's not called while 3087 * the interrupt routine is executing. 3088 */ 3089static void ucc_netpoll(struct net_device *dev) 3090{ 3091 struct ucc_geth_private *ugeth = netdev_priv(dev); 3092 int irq = ugeth->ug_info->uf_info.irq; 3093 3094 disable_irq(irq); 3095 ucc_geth_irq_handler(irq, dev); 3096 enable_irq(irq); 3097} 3098#endif /* CONFIG_NET_POLL_CONTROLLER */ 3099 3100static int ucc_geth_set_mac_addr(struct net_device *dev, void *p) 3101{ 3102 struct ucc_geth_private *ugeth = netdev_priv(dev); 3103 struct sockaddr *addr = p; 3104 3105 if (!is_valid_ether_addr(addr->sa_data)) 3106 return -EADDRNOTAVAIL; 3107 3108 eth_hw_addr_set(dev, addr->sa_data); 3109 3110 /* 3111 * If device is not running, we will set mac addr register 3112 * when opening the device. 3113 */ 3114 if (!netif_running(dev)) 3115 return 0; 3116 3117 spin_lock_irq(&ugeth->lock); 3118 init_mac_station_addr_regs(dev->dev_addr[0], 3119 dev->dev_addr[1], 3120 dev->dev_addr[2], 3121 dev->dev_addr[3], 3122 dev->dev_addr[4], 3123 dev->dev_addr[5], 3124 &ugeth->ug_regs->macstnaddr1, 3125 &ugeth->ug_regs->macstnaddr2); 3126 spin_unlock_irq(&ugeth->lock); 3127 3128 return 0; 3129} 3130 3131static int ucc_geth_init_mac(struct ucc_geth_private *ugeth) 3132{ 3133 struct net_device *dev = ugeth->ndev; 3134 int err; 3135 3136 err = ucc_struct_init(ugeth); 3137 if (err) { 3138 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n"); 3139 goto err; 3140 } 3141 3142 err = ucc_geth_startup(ugeth); 3143 if (err) { 3144 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3145 goto err; 3146 } 3147 3148 /* Set MACSTNADDR1, MACSTNADDR2 */ 3149 /* For more details see the hardware spec. */ 3150 init_mac_station_addr_regs(dev->dev_addr[0], 3151 dev->dev_addr[1], 3152 dev->dev_addr[2], 3153 dev->dev_addr[3], 3154 dev->dev_addr[4], 3155 dev->dev_addr[5], 3156 &ugeth->ug_regs->macstnaddr1, 3157 &ugeth->ug_regs->macstnaddr2); 3158 3159 return 0; 3160err: 3161 ucc_geth_stop(ugeth); 3162 return err; 3163} 3164 3165/* Called when something needs to use the ethernet device */ 3166/* Returns 0 for success. */ 3167static int ucc_geth_open(struct net_device *dev) 3168{ 3169 struct ucc_geth_private *ugeth = netdev_priv(dev); 3170 int err; 3171 3172 ugeth_vdbg("%s: IN", __func__); 3173 3174 /* Test station address */ 3175 if (dev->dev_addr[0] & ENET_GROUP_ADDR) { 3176 netif_err(ugeth, ifup, dev, 3177 "Multicast address used for station address - is this what you wanted?\n"); 3178 return -EINVAL; 3179 } 3180 3181 err = phylink_of_phy_connect(ugeth->phylink, ugeth->dev->of_node, 0); 3182 if (err) { 3183 dev_err(&dev->dev, "Could not attach to PHY\n"); 3184 return -ENODEV; 3185 } 3186 3187 err = ucc_geth_init_mac(ugeth); 3188 if (err) { 3189 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n"); 3190 goto err; 3191 } 3192 3193 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 3194 0, "UCC Geth", dev); 3195 if (err) { 3196 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n"); 3197 goto err; 3198 } 3199 3200 phylink_start(ugeth->phylink); 3201 napi_enable(&ugeth->napi); 3202 netdev_reset_queue(dev); 3203 netif_start_queue(dev); 3204 3205 device_set_wakeup_capable(&dev->dev, 3206 qe_alive_during_sleep() || dev->phydev->irq); 3207 device_set_wakeup_enable(&dev->dev, ugeth->wol_en); 3208 3209 return err; 3210 3211err: 3212 ucc_geth_stop(ugeth); 3213 return err; 3214} 3215 3216/* Stops the kernel queue, and halts the controller */ 3217static int ucc_geth_close(struct net_device *dev) 3218{ 3219 struct ucc_geth_private *ugeth = netdev_priv(dev); 3220 3221 ugeth_vdbg("%s: IN", __func__); 3222 3223 napi_disable(&ugeth->napi); 3224 3225 cancel_work_sync(&ugeth->timeout_work); 3226 ucc_geth_stop(ugeth); 3227 phylink_disconnect_phy(ugeth->phylink); 3228 3229 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev); 3230 3231 netif_stop_queue(dev); 3232 netdev_reset_queue(dev); 3233 3234 return 0; 3235} 3236 3237/* Reopen device. This will reset the MAC and PHY. */ 3238static void ucc_geth_timeout_work(struct work_struct *work) 3239{ 3240 struct ucc_geth_private *ugeth; 3241 struct net_device *dev; 3242 3243 ugeth = container_of(work, struct ucc_geth_private, timeout_work); 3244 dev = ugeth->ndev; 3245 3246 ugeth_vdbg("%s: IN", __func__); 3247 3248 dev->stats.tx_errors++; 3249 3250 ugeth_dump_regs(ugeth); 3251 3252 if (dev->flags & IFF_UP) { 3253 /* 3254 * Must reset MAC *and* PHY. This is done by reopening 3255 * the device. 3256 */ 3257 netif_tx_stop_all_queues(dev); 3258 ucc_geth_stop(ugeth); 3259 ucc_geth_init_mac(ugeth); 3260 /* Must start PHY here */ 3261 phylink_start(ugeth->phylink); 3262 netif_tx_start_all_queues(dev); 3263 } 3264 3265 netif_tx_schedule_all(dev); 3266} 3267 3268/* 3269 * ucc_geth_timeout gets called when a packet has not been 3270 * transmitted after a set amount of time. 3271 */ 3272static void ucc_geth_timeout(struct net_device *dev, unsigned int txqueue) 3273{ 3274 struct ucc_geth_private *ugeth = netdev_priv(dev); 3275 3276 schedule_work(&ugeth->timeout_work); 3277} 3278 3279 3280#ifdef CONFIG_PM 3281 3282static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state) 3283{ 3284 struct net_device *ndev = platform_get_drvdata(ofdev); 3285 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3286 bool mac_wol = false; 3287 3288 if (!netif_running(ndev)) 3289 return 0; 3290 3291 netif_device_detach(ndev); 3292 napi_disable(&ugeth->napi); 3293 3294 /* 3295 * Disable the controller, otherwise we'll wakeup on any network 3296 * activity. 3297 */ 3298 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 3299 3300 if (ugeth->wol_en & WAKE_MAGIC && !ugeth->phy_wol_en) { 3301 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3302 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3303 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3304 mac_wol = true; 3305 } 3306 3307 rtnl_lock(); 3308 phylink_suspend(ugeth->phylink, mac_wol); 3309 rtnl_unlock(); 3310 3311 return 0; 3312} 3313 3314static int ucc_geth_resume(struct platform_device *ofdev) 3315{ 3316 struct net_device *ndev = platform_get_drvdata(ofdev); 3317 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3318 int err; 3319 3320 if (!netif_running(ndev)) 3321 return 0; 3322 3323 if (qe_alive_during_sleep()) { 3324 if (ugeth->wol_en & WAKE_MAGIC) { 3325 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3326 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3327 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3328 } 3329 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3330 } else { 3331 /* 3332 * Full reinitialization is required if QE shuts down 3333 * during sleep. 3334 */ 3335 ucc_geth_memclean(ugeth); 3336 3337 err = ucc_geth_init_mac(ugeth); 3338 if (err) { 3339 netdev_err(ndev, "Cannot initialize MAC, aborting\n"); 3340 return err; 3341 } 3342 } 3343 3344 rtnl_lock(); 3345 phylink_resume(ugeth->phylink); 3346 rtnl_unlock(); 3347 3348 napi_enable(&ugeth->napi); 3349 netif_device_attach(ndev); 3350 3351 return 0; 3352} 3353 3354#else 3355#define ucc_geth_suspend NULL 3356#define ucc_geth_resume NULL 3357#endif 3358 3359static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3360{ 3361 struct ucc_geth_private *ugeth = netdev_priv(dev); 3362 3363 if (!netif_running(dev)) 3364 return -EINVAL; 3365 3366 return phylink_mii_ioctl(ugeth->phylink, rq, cmd); 3367} 3368 3369static const struct net_device_ops ucc_geth_netdev_ops = { 3370 .ndo_open = ucc_geth_open, 3371 .ndo_stop = ucc_geth_close, 3372 .ndo_start_xmit = ucc_geth_start_xmit, 3373 .ndo_validate_addr = eth_validate_addr, 3374 .ndo_set_mac_address = ucc_geth_set_mac_addr, 3375 .ndo_set_rx_mode = ucc_geth_set_multi, 3376 .ndo_tx_timeout = ucc_geth_timeout, 3377 .ndo_eth_ioctl = ucc_geth_ioctl, 3378#ifdef CONFIG_NET_POLL_CONTROLLER 3379 .ndo_poll_controller = ucc_netpoll, 3380#endif 3381}; 3382 3383static int ucc_geth_parse_clock(struct device_node *np, const char *which, 3384 enum qe_clock *out) 3385{ 3386 const char *sprop; 3387 char buf[24]; 3388 3389 snprintf(buf, sizeof(buf), "%s-clock-name", which); 3390 sprop = of_get_property(np, buf, NULL); 3391 if (sprop) { 3392 *out = qe_clock_source(sprop); 3393 } else { 3394 u32 val; 3395 3396 snprintf(buf, sizeof(buf), "%s-clock", which); 3397 if (of_property_read_u32(np, buf, &val)) { 3398 /* If both *-clock-name and *-clock are missing, 3399 * we want to tell people to use *-clock-name. 3400 */ 3401 pr_err("missing %s-clock-name property\n", buf); 3402 return -EINVAL; 3403 } 3404 *out = val; 3405 } 3406 if (*out < QE_CLK_NONE || *out > QE_CLK24) { 3407 pr_err("invalid %s property\n", buf); 3408 return -EINVAL; 3409 } 3410 return 0; 3411} 3412 3413static const struct phylink_mac_ops ugeth_mac_ops = { 3414 .mac_link_up = ugeth_mac_link_up, 3415 .mac_link_down = ugeth_mac_link_down, 3416 .mac_config = ugeth_mac_config, 3417}; 3418 3419static int ucc_geth_probe(struct platform_device* ofdev) 3420{ 3421 struct device *device = &ofdev->dev; 3422 struct device_node *np = ofdev->dev.of_node; 3423 struct net_device *dev = NULL; 3424 struct ucc_geth_private *ugeth = NULL; 3425 struct ucc_geth_info *ug_info; 3426 struct device_node *phy_node; 3427 struct phylink *phylink; 3428 struct resource res; 3429 int err, ucc_num; 3430 const unsigned int *prop; 3431 phy_interface_t phy_interface; 3432 3433 ugeth_vdbg("%s: IN", __func__); 3434 3435 prop = of_get_property(np, "cell-index", NULL); 3436 if (!prop) { 3437 prop = of_get_property(np, "device-id", NULL); 3438 if (!prop) 3439 return -ENODEV; 3440 } 3441 3442 ucc_num = *prop - 1; 3443 if ((ucc_num < 0) || (ucc_num > 7)) 3444 return -ENODEV; 3445 3446 ug_info = devm_kmemdup(&ofdev->dev, &ugeth_primary_info, 3447 sizeof(*ug_info), GFP_KERNEL); 3448 if (!ug_info) 3449 return -ENOMEM; 3450 3451 ug_info->uf_info.ucc_num = ucc_num; 3452 3453 err = ucc_geth_parse_clock(np, "rx", &ug_info->uf_info.rx_clock); 3454 if (err) 3455 return err; 3456 err = ucc_geth_parse_clock(np, "tx", &ug_info->uf_info.tx_clock); 3457 if (err) 3458 return err; 3459 3460 err = of_address_to_resource(np, 0, &res); 3461 if (err) 3462 return err; 3463 3464 ug_info->uf_info.regs = res.start; 3465 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); 3466 3467 /* Find the TBI PHY node. If it's not there, we don't support SGMII */ 3468 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 3469 3470 phy_node = of_parse_phandle(np, "phy-handle", 0); 3471 if (phy_node) { 3472 prop = of_get_property(phy_node, "interface", NULL); 3473 if (prop) { 3474 dev_err(&ofdev->dev, 3475 "Device-tree property 'interface' is no longer supported. Please use 'phy-connection-type' instead."); 3476 of_node_put(phy_node); 3477 err = -EINVAL; 3478 goto err_put_tbi; 3479 } 3480 of_node_put(phy_node); 3481 } 3482 3483 err = of_get_phy_mode(np, &phy_interface); 3484 if (err) { 3485 dev_err(&ofdev->dev, "Invalid phy-connection-type"); 3486 goto err_put_tbi; 3487 } 3488 3489 if (phy_interface == PHY_INTERFACE_MODE_GMII || 3490 phy_interface_mode_is_rgmii(phy_interface) || 3491 phy_interface == PHY_INTERFACE_MODE_TBI || 3492 phy_interface == PHY_INTERFACE_MODE_RTBI || 3493 phy_interface == PHY_INTERFACE_MODE_SGMII) { 3494 unsigned int snums = qe_get_num_of_snums(); 3495 3496 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT; 3497 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT; 3498 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT; 3499 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT; 3500 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT; 3501 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; 3502 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; 3503 3504 /* If QE's snum number is 46/76 which means we need to support 3505 * 4 UECs at 1000Base-T simultaneously, we need to allocate 3506 * more Threads to Rx. 3507 */ 3508 if ((snums == 76) || (snums == 46)) 3509 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; 3510 else 3511 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; 3512 } 3513 3514 if (netif_msg_probe(&debug)) 3515 pr_info("UCC%1d at 0x%8llx (irq = %d)\n", 3516 ug_info->uf_info.ucc_num + 1, 3517 (u64)ug_info->uf_info.regs, 3518 ug_info->uf_info.irq); 3519 3520 /* Create an ethernet device instance */ 3521 dev = devm_alloc_etherdev(&ofdev->dev, sizeof(*ugeth)); 3522 if (!dev) { 3523 err = -ENOMEM; 3524 goto err_put_tbi; 3525 } 3526 3527 ugeth = netdev_priv(dev); 3528 spin_lock_init(&ugeth->lock); 3529 3530 /* Create CQs for hash tables */ 3531 INIT_LIST_HEAD(&ugeth->group_hash_q); 3532 INIT_LIST_HEAD(&ugeth->ind_hash_q); 3533 3534 dev_set_drvdata(device, dev); 3535 3536 /* Set the dev->base_addr to the gfar reg region */ 3537 dev->base_addr = (unsigned long)(ug_info->uf_info.regs); 3538 3539 SET_NETDEV_DEV(dev, device); 3540 3541 /* Fill in the dev structure */ 3542 uec_set_ethtool_ops(dev); 3543 dev->netdev_ops = &ucc_geth_netdev_ops; 3544 dev->watchdog_timeo = TX_TIMEOUT; 3545 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work); 3546 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll); 3547 dev->mtu = 1500; 3548 dev->max_mtu = 1518; 3549 3550 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT); 3551 3552 ugeth->phylink_config.dev = &dev->dev; 3553 ugeth->phylink_config.type = PHYLINK_NETDEV; 3554 3555 ugeth->phylink_config.mac_capabilities = 3556 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 3557 3558 __set_bit(PHY_INTERFACE_MODE_MII, 3559 ugeth->phylink_config.supported_interfaces); 3560 __set_bit(PHY_INTERFACE_MODE_RMII, 3561 ugeth->phylink_config.supported_interfaces); 3562 __set_bit(PHY_INTERFACE_MODE_GMII, 3563 ugeth->phylink_config.supported_interfaces); 3564 phy_interface_set_rgmii(ugeth->phylink_config.supported_interfaces); 3565 3566 if (ug_info->tbi_node) { 3567 __set_bit(PHY_INTERFACE_MODE_SGMII, 3568 ugeth->phylink_config.supported_interfaces); 3569 __set_bit(PHY_INTERFACE_MODE_TBI, 3570 ugeth->phylink_config.supported_interfaces); 3571 __set_bit(PHY_INTERFACE_MODE_RTBI, 3572 ugeth->phylink_config.supported_interfaces); 3573 } 3574 3575 phylink = phylink_create(&ugeth->phylink_config, dev_fwnode(&dev->dev), 3576 phy_interface, &ugeth_mac_ops); 3577 if (IS_ERR(phylink)) { 3578 err = PTR_ERR(phylink); 3579 goto err_put_tbi; 3580 } 3581 3582 ugeth->phylink = phylink; 3583 3584 err = devm_register_netdev(&ofdev->dev, dev); 3585 if (err) { 3586 if (netif_msg_probe(ugeth)) 3587 pr_err("%s: Cannot register net device, aborting\n", 3588 dev->name); 3589 goto err_destroy_phylink; 3590 } 3591 3592 err = of_get_ethdev_address(np, dev); 3593 if (err == -EPROBE_DEFER) 3594 goto err_destroy_phylink; 3595 3596 ugeth->ug_info = ug_info; 3597 ugeth->dev = device; 3598 ugeth->ndev = dev; 3599 ugeth->node = np; 3600 3601 return 0; 3602 3603err_destroy_phylink: 3604 phylink_destroy(phylink); 3605err_put_tbi: 3606 of_node_put(ug_info->tbi_node); 3607 3608 return err; 3609} 3610 3611static void ucc_geth_remove(struct platform_device* ofdev) 3612{ 3613 struct net_device *dev = platform_get_drvdata(ofdev); 3614 struct ucc_geth_private *ugeth = netdev_priv(dev); 3615 3616 ucc_geth_memclean(ugeth); 3617 phylink_destroy(ugeth->phylink); 3618 of_node_put(ugeth->ug_info->tbi_node); 3619} 3620 3621static const struct of_device_id ucc_geth_match[] = { 3622 { 3623 .type = "network", 3624 .compatible = "ucc_geth", 3625 }, 3626 {}, 3627}; 3628 3629MODULE_DEVICE_TABLE(of, ucc_geth_match); 3630 3631static struct platform_driver ucc_geth_driver = { 3632 .driver = { 3633 .name = DRV_NAME, 3634 .of_match_table = ucc_geth_match, 3635 }, 3636 .probe = ucc_geth_probe, 3637 .remove = ucc_geth_remove, 3638 .suspend = ucc_geth_suspend, 3639 .resume = ucc_geth_resume, 3640}; 3641 3642static int __init ucc_geth_init(void) 3643{ 3644 if (netif_msg_drv(&debug)) 3645 pr_info(DRV_DESC "\n"); 3646 3647 return platform_driver_register(&ucc_geth_driver); 3648} 3649 3650static void __exit ucc_geth_exit(void) 3651{ 3652 platform_driver_unregister(&ucc_geth_driver); 3653} 3654 3655module_init(ucc_geth_init); 3656module_exit(ucc_geth_exit); 3657 3658MODULE_AUTHOR("Freescale Semiconductor, Inc"); 3659MODULE_DESCRIPTION(DRV_DESC); 3660MODULE_LICENSE("GPL");
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