fman_memac.c

   1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
   2/*
   3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
   4 */
   5
   6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8#include "fman_memac.h"
   9#include "fman.h"
  10#include "mac.h"
  11
  12#include <linux/slab.h>
  13#include <linux/io.h>
  14#include <linux/pcs-lynx.h>
  15#include <linux/phy.h>
  16#include <linux/phy_fixed.h>
  17#include <linux/phy/phy.h>
  18#include <linux/of_mdio.h>
  19
  20/* Num of additional exact match MAC adr regs */
  21#define MEMAC_NUM_OF_PADDRS 7
  22
  23/* Control and Configuration Register (COMMAND_CONFIG) */
  24#define CMD_CFG_REG_LOWP_RXETY	0x01000000 /* 07 Rx low power indication */
  25#define CMD_CFG_TX_LOWP_ENA	0x00800000 /* 08 Tx Low Power Idle Enable */
  26#define CMD_CFG_PFC_MODE	0x00080000 /* 12 Enable PFC */
  27#define CMD_CFG_NO_LEN_CHK	0x00020000 /* 14 Payload length check disable */
  28#define CMD_CFG_SW_RESET	0x00001000 /* 19 S/W Reset, self clearing bit */
  29#define CMD_CFG_TX_PAD_EN	0x00000800 /* 20 Enable Tx padding of frames */
  30#define CMD_CFG_PAUSE_IGNORE	0x00000100 /* 23 Ignore Pause frame quanta */
  31#define CMD_CFG_CRC_FWD		0x00000040 /* 25 Terminate/frwd CRC of frames */
  32#define CMD_CFG_PAD_EN		0x00000020 /* 26 Frame padding removal */
  33#define CMD_CFG_PROMIS_EN	0x00000010 /* 27 Promiscuous operation enable */
  34#define CMD_CFG_RX_EN		0x00000002 /* 30 MAC receive path enable */
  35#define CMD_CFG_TX_EN		0x00000001 /* 31 MAC transmit path enable */
  36
  37/* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */
  38#define TX_FIFO_SECTIONS_TX_EMPTY_MASK			0xFFFF0000
  39#define TX_FIFO_SECTIONS_TX_AVAIL_MASK			0x0000FFFF
  40#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G		0x00400000
  41#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G		0x00100000
  42#define TX_FIFO_SECTIONS_TX_AVAIL_10G			0x00000019
  43#define TX_FIFO_SECTIONS_TX_AVAIL_1G			0x00000020
  44#define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G		0x00000060
  45
  46#define GET_TX_EMPTY_DEFAULT_VALUE(_val)				\
  47do {									\
  48	_val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK;			\
  49	((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ?			\
  50			(_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\
  51			(_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\
  52} while (0)
  53
  54/* Interface Mode Register (IF_MODE) */
  55
  56#define IF_MODE_MASK		0x00000003 /* 30-31 Mask on i/f mode bits */
  57#define IF_MODE_10G		0x00000000 /* 30-31 10G interface */
  58#define IF_MODE_MII		0x00000001 /* 30-31 MII interface */
  59#define IF_MODE_GMII		0x00000002 /* 30-31 GMII (1G) interface */
  60#define IF_MODE_RGMII		0x00000004
  61#define IF_MODE_RGMII_AUTO	0x00008000
  62#define IF_MODE_RGMII_1000	0x00004000 /* 10 - 1000Mbps RGMII */
  63#define IF_MODE_RGMII_100	0x00000000 /* 00 - 100Mbps RGMII */
  64#define IF_MODE_RGMII_10	0x00002000 /* 01 - 10Mbps RGMII */
  65#define IF_MODE_RGMII_SP_MASK	0x00006000 /* Setsp mask bits */
  66#define IF_MODE_RGMII_FD	0x00001000 /* Full duplex RGMII */
  67#define IF_MODE_HD		0x00000040 /* Half duplex operation */
  68
  69/* Hash table Control Register (HASHTABLE_CTRL) */
  70#define HASH_CTRL_MCAST_EN	0x00000100
  71/* 26-31 Hash table address code */
  72#define HASH_CTRL_ADDR_MASK	0x0000003F
  73/* MAC mcast indication */
  74#define GROUP_ADDRESS		0x0000010000000000LL
  75#define HASH_TABLE_SIZE		64	/* Hash tbl size */
  76
  77/* Interrupt Mask Register (IMASK) */
  78#define MEMAC_IMASK_MGI		0x40000000 /* 1 Magic pkt detect indication */
  79#define MEMAC_IMASK_TSECC_ER	0x20000000 /* 2 Timestamp FIFO ECC error evnt */
  80#define MEMAC_IMASK_TECC_ER	0x02000000 /* 6 Transmit frame ECC error evnt */
  81#define MEMAC_IMASK_RECC_ER	0x01000000 /* 7 Receive frame ECC error evnt */
  82
  83#define MEMAC_ALL_ERRS_IMASK					\
  84		((u32)(MEMAC_IMASK_TSECC_ER	|	\
  85		       MEMAC_IMASK_TECC_ER		|	\
  86		       MEMAC_IMASK_RECC_ER		|	\
  87		       MEMAC_IMASK_MGI))
  88
  89#define MEMAC_IEVNT_PCS			0x80000000 /* PCS (XG). Link sync (G) */
  90#define MEMAC_IEVNT_AN			0x40000000 /* Auto-negotiation */
  91#define MEMAC_IEVNT_LT			0x20000000 /* Link Training/New page */
  92#define MEMAC_IEVNT_MGI			0x00004000 /* Magic pkt detection */
  93#define MEMAC_IEVNT_TS_ECC_ER		0x00002000 /* Timestamp FIFO ECC error*/
  94#define MEMAC_IEVNT_RX_FIFO_OVFL	0x00001000 /* Rx FIFO overflow */
  95#define MEMAC_IEVNT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
  96#define MEMAC_IEVNT_TX_FIFO_OVFL	0x00000400 /* Tx FIFO overflow */
  97#define MEMAC_IEVNT_TX_ECC_ER		0x00000200 /* Tx frame ECC error */
  98#define MEMAC_IEVNT_RX_ECC_ER		0x00000100 /* Rx frame ECC error */
  99#define MEMAC_IEVNT_LI_FAULT		0x00000080 /* Link Interruption flt */
 100#define MEMAC_IEVNT_RX_EMPTY		0x00000040 /* Rx FIFO empty */
 101#define MEMAC_IEVNT_TX_EMPTY		0x00000020 /* Tx FIFO empty */
 102#define MEMAC_IEVNT_RX_LOWP		0x00000010 /* Low Power Idle */
 103#define MEMAC_IEVNT_PHY_LOS		0x00000004 /* Phy loss of signal */
 104#define MEMAC_IEVNT_REM_FAULT		0x00000002 /* Remote fault (XGMII) */
 105#define MEMAC_IEVNT_LOC_FAULT		0x00000001 /* Local fault (XGMII) */
 106
 107#define DEFAULT_PAUSE_QUANTA	0xf000
 108#define DEFAULT_FRAME_LENGTH	0x600
 109#define DEFAULT_TX_IPG_LENGTH	12
 110
 111#define CLXY_PAUSE_QUANTA_CLX_PQNT	0x0000FFFF
 112#define CLXY_PAUSE_QUANTA_CLY_PQNT	0xFFFF0000
 113#define CLXY_PAUSE_THRESH_CLX_QTH	0x0000FFFF
 114#define CLXY_PAUSE_THRESH_CLY_QTH	0xFFFF0000
 115
 116struct mac_addr {
 117	/* Lower 32 bits of 48-bit MAC address */
 118	u32 mac_addr_l;
 119	/* Upper 16 bits of 48-bit MAC address */
 120	u32 mac_addr_u;
 121};
 122
 123/* memory map */
 124struct memac_regs {
 125	u32 res0000[2];			/* General Control and Status */
 126	u32 command_config;		/* 0x008 Ctrl and cfg */
 127	struct mac_addr mac_addr0;	/* 0x00C-0x010 MAC_ADDR_0...1 */
 128	u32 maxfrm;			/* 0x014 Max frame length */
 129	u32 res0018[1];
 130	u32 rx_fifo_sections;		/* Receive FIFO configuration reg */
 131	u32 tx_fifo_sections;		/* Transmit FIFO configuration reg */
 132	u32 res0024[2];
 133	u32 hashtable_ctrl;		/* 0x02C Hash table control */
 134	u32 res0030[4];
 135	u32 ievent;			/* 0x040 Interrupt event */
 136	u32 tx_ipg_length;		/* 0x044 Transmitter inter-packet-gap */
 137	u32 res0048;
 138	u32 imask;			/* 0x04C Interrupt mask */
 139	u32 res0050;
 140	u32 pause_quanta[4];		/* 0x054 Pause quanta */
 141	u32 pause_thresh[4];		/* 0x064 Pause quanta threshold */
 142	u32 rx_pause_status;		/* 0x074 Receive pause status */
 143	u32 res0078[2];
 144	struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */
 145	u32 lpwake_timer;		/* 0x0B8 Low Power Wakeup Timer */
 146	u32 sleep_timer;		/* 0x0BC Transmit EEE Low Power Timer */
 147	u32 res00c0[8];
 148	u32 statn_config;		/* 0x0E0 Statistics configuration */
 149	u32 res00e4[7];
 150	/* Rx Statistics Counter */
 151	u32 reoct_l;
 152	u32 reoct_u;
 153	u32 roct_l;
 154	u32 roct_u;
 155	u32 raln_l;
 156	u32 raln_u;
 157	u32 rxpf_l;
 158	u32 rxpf_u;
 159	u32 rfrm_l;
 160	u32 rfrm_u;
 161	u32 rfcs_l;
 162	u32 rfcs_u;
 163	u32 rvlan_l;
 164	u32 rvlan_u;
 165	u32 rerr_l;
 166	u32 rerr_u;
 167	u32 ruca_l;
 168	u32 ruca_u;
 169	u32 rmca_l;
 170	u32 rmca_u;
 171	u32 rbca_l;
 172	u32 rbca_u;
 173	u32 rdrp_l;
 174	u32 rdrp_u;
 175	u32 rpkt_l;
 176	u32 rpkt_u;
 177	u32 rund_l;
 178	u32 rund_u;
 179	u32 r64_l;
 180	u32 r64_u;
 181	u32 r127_l;
 182	u32 r127_u;
 183	u32 r255_l;
 184	u32 r255_u;
 185	u32 r511_l;
 186	u32 r511_u;
 187	u32 r1023_l;
 188	u32 r1023_u;
 189	u32 r1518_l;
 190	u32 r1518_u;
 191	u32 r1519x_l;
 192	u32 r1519x_u;
 193	u32 rovr_l;
 194	u32 rovr_u;
 195	u32 rjbr_l;
 196	u32 rjbr_u;
 197	u32 rfrg_l;
 198	u32 rfrg_u;
 199	u32 rcnp_l;
 200	u32 rcnp_u;
 201	u32 rdrntp_l;
 202	u32 rdrntp_u;
 203	u32 res01d0[12];
 204	/* Tx Statistics Counter */
 205	u32 teoct_l;
 206	u32 teoct_u;
 207	u32 toct_l;
 208	u32 toct_u;
 209	u32 res0210[2];
 210	u32 txpf_l;
 211	u32 txpf_u;
 212	u32 tfrm_l;
 213	u32 tfrm_u;
 214	u32 tfcs_l;
 215	u32 tfcs_u;
 216	u32 tvlan_l;
 217	u32 tvlan_u;
 218	u32 terr_l;
 219	u32 terr_u;
 220	u32 tuca_l;
 221	u32 tuca_u;
 222	u32 tmca_l;
 223	u32 tmca_u;
 224	u32 tbca_l;
 225	u32 tbca_u;
 226	u32 res0258[2];
 227	u32 tpkt_l;
 228	u32 tpkt_u;
 229	u32 tund_l;
 230	u32 tund_u;
 231	u32 t64_l;
 232	u32 t64_u;
 233	u32 t127_l;
 234	u32 t127_u;
 235	u32 t255_l;
 236	u32 t255_u;
 237	u32 t511_l;
 238	u32 t511_u;
 239	u32 t1023_l;
 240	u32 t1023_u;
 241	u32 t1518_l;
 242	u32 t1518_u;
 243	u32 t1519x_l;
 244	u32 t1519x_u;
 245	u32 res02a8[6];
 246	u32 tcnp_l;
 247	u32 tcnp_u;
 248	u32 res02c8[14];
 249	/* Line Interface Control */
 250	u32 if_mode;		/* 0x300 Interface Mode Control */
 251	u32 if_status;		/* 0x304 Interface Status */
 252	u32 res0308[14];
 253	/* HiGig/2 */
 254	u32 hg_config;		/* 0x340 Control and cfg */
 255	u32 res0344[3];
 256	u32 hg_pause_quanta;	/* 0x350 Pause quanta */
 257	u32 res0354[3];
 258	u32 hg_pause_thresh;	/* 0x360 Pause quanta threshold */
 259	u32 res0364[3];
 260	u32 hgrx_pause_status;	/* 0x370 Receive pause status */
 261	u32 hg_fifos_status;	/* 0x374 fifos status */
 262	u32 rhm;		/* 0x378 rx messages counter */
 263	u32 thm;		/* 0x37C tx messages counter */
 264};
 265
 266struct memac_cfg {
 267	bool reset_on_init;
 268	bool pause_ignore;
 269	bool promiscuous_mode_enable;
 270	u16 max_frame_length;
 271	u16 pause_quanta;
 272	u32 tx_ipg_length;
 273};
 274
 275struct fman_mac {
 276	/* Pointer to MAC memory mapped registers */
 277	struct memac_regs __iomem *regs;
 278	/* MAC address of device */
 279	u64 addr;
 280	struct mac_device *dev_id; /* device cookie used by the exception cbs */
 281	fman_mac_exception_cb *exception_cb;
 282	fman_mac_exception_cb *event_cb;
 283	/* Pointer to driver's global address hash table  */
 284	struct eth_hash_t *multicast_addr_hash;
 285	/* Pointer to driver's individual address hash table  */
 286	struct eth_hash_t *unicast_addr_hash;
 287	u8 mac_id;
 288	u32 exceptions;
 289	struct memac_cfg *memac_drv_param;
 290	void *fm;
 291	struct fman_rev_info fm_rev_info;
 292	struct phy *serdes;
 293	struct phylink_pcs *sgmii_pcs;
 294	struct phylink_pcs *qsgmii_pcs;
 295	struct phylink_pcs *xfi_pcs;
 296	bool allmulti_enabled;
 297	bool rgmii_no_half_duplex;
 298};
 299
 300static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr,
 301			      u8 paddr_num)
 302{
 303	u32 tmp0, tmp1;
 304
 305	tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
 306	tmp1 = (u32)(adr[4] | adr[5] << 8);
 307
 308	if (paddr_num == 0) {
 309		iowrite32be(tmp0, &regs->mac_addr0.mac_addr_l);
 310		iowrite32be(tmp1, &regs->mac_addr0.mac_addr_u);
 311	} else {
 312		iowrite32be(tmp0, &regs->mac_addr[paddr_num - 1].mac_addr_l);
 313		iowrite32be(tmp1, &regs->mac_addr[paddr_num - 1].mac_addr_u);
 314	}
 315}
 316
 317static int reset(struct memac_regs __iomem *regs)
 318{
 319	u32 tmp;
 320	int count;
 321
 322	tmp = ioread32be(&regs->command_config);
 323
 324	tmp |= CMD_CFG_SW_RESET;
 325
 326	iowrite32be(tmp, &regs->command_config);
 327
 328	count = 100;
 329	do {
 330		udelay(1);
 331	} while ((ioread32be(&regs->command_config) & CMD_CFG_SW_RESET) &&
 332		 --count);
 333
 334	if (count == 0)
 335		return -EBUSY;
 336
 337	return 0;
 338}
 339
 340static void set_exception(struct memac_regs __iomem *regs, u32 val,
 341			  bool enable)
 342{
 343	u32 tmp;
 344
 345	tmp = ioread32be(&regs->imask);
 346	if (enable)
 347		tmp |= val;
 348	else
 349		tmp &= ~val;
 350
 351	iowrite32be(tmp, &regs->imask);
 352}
 353
 354static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
 355		u32 exceptions)
 356{
 357	u32 tmp;
 358
 359	/* Config */
 360	tmp = 0;
 361	if (cfg->promiscuous_mode_enable)
 362		tmp |= CMD_CFG_PROMIS_EN;
 363	if (cfg->pause_ignore)
 364		tmp |= CMD_CFG_PAUSE_IGNORE;
 365
 366	/* Payload length check disable */
 367	tmp |= CMD_CFG_NO_LEN_CHK;
 368	/* Enable padding of frames in transmit direction */
 369	tmp |= CMD_CFG_TX_PAD_EN;
 370
 371	tmp |= CMD_CFG_CRC_FWD;
 372
 373	iowrite32be(tmp, &regs->command_config);
 374
 375	/* Max Frame Length */
 376	iowrite32be((u32)cfg->max_frame_length, &regs->maxfrm);
 377
 378	/* Pause Time */
 379	iowrite32be((u32)cfg->pause_quanta, &regs->pause_quanta[0]);
 380	iowrite32be((u32)0, &regs->pause_thresh[0]);
 381
 382	/* clear all pending events and set-up interrupts */
 383	iowrite32be(0xffffffff, &regs->ievent);
 384	set_exception(regs, exceptions, true);
 385
 386	return 0;
 387}
 388
 389static void set_dflts(struct memac_cfg *cfg)
 390{
 391	cfg->reset_on_init = false;
 392	cfg->promiscuous_mode_enable = false;
 393	cfg->pause_ignore = false;
 394	cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
 395	cfg->max_frame_length = DEFAULT_FRAME_LENGTH;
 396	cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;
 397}
 398
 399static u32 get_mac_addr_hash_code(u64 eth_addr)
 400{
 401	u64 mask1, mask2;
 402	u32 xor_val = 0;
 403	u8 i, j;
 404
 405	for (i = 0; i < 6; i++) {
 406		mask1 = eth_addr & (u64)0x01;
 407		eth_addr >>= 1;
 408
 409		for (j = 0; j < 7; j++) {
 410			mask2 = eth_addr & (u64)0x01;
 411			mask1 ^= mask2;
 412			eth_addr >>= 1;
 413		}
 414
 415		xor_val |= (mask1 << (5 - i));
 416	}
 417
 418	return xor_val;
 419}
 420
 421static int check_init_parameters(struct fman_mac *memac)
 422{
 423	if (!memac->exception_cb) {
 424		pr_err("Uninitialized exception handler\n");
 425		return -EINVAL;
 426	}
 427	if (!memac->event_cb) {
 428		pr_warn("Uninitialize event handler\n");
 429		return -EINVAL;
 430	}
 431
 432	return 0;
 433}
 434
 435static int get_exception_flag(enum fman_mac_exceptions exception)
 436{
 437	u32 bit_mask;
 438
 439	switch (exception) {
 440	case FM_MAC_EX_10G_TX_ECC_ER:
 441		bit_mask = MEMAC_IMASK_TECC_ER;
 442		break;
 443	case FM_MAC_EX_10G_RX_ECC_ER:
 444		bit_mask = MEMAC_IMASK_RECC_ER;
 445		break;
 446	case FM_MAC_EX_TS_FIFO_ECC_ERR:
 447		bit_mask = MEMAC_IMASK_TSECC_ER;
 448		break;
 449	case FM_MAC_EX_MAGIC_PACKET_INDICATION:
 450		bit_mask = MEMAC_IMASK_MGI;
 451		break;
 452	default:
 453		bit_mask = 0;
 454		break;
 455	}
 456
 457	return bit_mask;
 458}
 459
 460static void memac_err_exception(void *handle)
 461{
 462	struct fman_mac *memac = (struct fman_mac *)handle;
 463	struct memac_regs __iomem *regs = memac->regs;
 464	u32 event, imask;
 465
 466	event = ioread32be(&regs->ievent);
 467	imask = ioread32be(&regs->imask);
 468
 469	/* Imask include both error and notification/event bits.
 470	 * Leaving only error bits enabled by imask.
 471	 * The imask error bits are shifted by 16 bits offset from
 472	 * their corresponding location in the ievent - hence the >> 16
 473	 */
 474	event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
 475
 476	iowrite32be(event, &regs->ievent);
 477
 478	if (event & MEMAC_IEVNT_TS_ECC_ER)
 479		memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR);
 480	if (event & MEMAC_IEVNT_TX_ECC_ER)
 481		memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER);
 482	if (event & MEMAC_IEVNT_RX_ECC_ER)
 483		memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER);
 484}
 485
 486static void memac_exception(void *handle)
 487{
 488	struct fman_mac *memac = (struct fman_mac *)handle;
 489	struct memac_regs __iomem *regs = memac->regs;
 490	u32 event, imask;
 491
 492	event = ioread32be(&regs->ievent);
 493	imask = ioread32be(&regs->imask);
 494
 495	/* Imask include both error and notification/event bits.
 496	 * Leaving only error bits enabled by imask.
 497	 * The imask error bits are shifted by 16 bits offset from
 498	 * their corresponding location in the ievent - hence the >> 16
 499	 */
 500	event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
 501
 502	iowrite32be(event, &regs->ievent);
 503
 504	if (event & MEMAC_IEVNT_MGI)
 505		memac->exception_cb(memac->dev_id,
 506				    FM_MAC_EX_MAGIC_PACKET_INDICATION);
 507}
 508
 509static void free_init_resources(struct fman_mac *memac)
 510{
 511	fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
 512			     FMAN_INTR_TYPE_ERR);
 513
 514	fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
 515			     FMAN_INTR_TYPE_NORMAL);
 516
 517	/* release the driver's group hash table */
 518	free_hash_table(memac->multicast_addr_hash);
 519	memac->multicast_addr_hash = NULL;
 520
 521	/* release the driver's individual hash table */
 522	free_hash_table(memac->unicast_addr_hash);
 523	memac->unicast_addr_hash = NULL;
 524}
 525
 526static int memac_enable(struct fman_mac *memac)
 527{
 528	int ret;
 529
 530	ret = phy_init(memac->serdes);
 531	if (ret) {
 532		dev_err(memac->dev_id->dev,
 533			"could not initialize serdes: %pe\n", ERR_PTR(ret));
 534		return ret;
 535	}
 536
 537	ret = phy_power_on(memac->serdes);
 538	if (ret) {
 539		dev_err(memac->dev_id->dev,
 540			"could not power on serdes: %pe\n", ERR_PTR(ret));
 541		phy_exit(memac->serdes);
 542	}
 543
 544	return ret;
 545}
 546
 547static void memac_disable(struct fman_mac *memac)
 548{
 549	phy_power_off(memac->serdes);
 550	phy_exit(memac->serdes);
 551}
 552
 553static int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
 554{
 555	struct memac_regs __iomem *regs = memac->regs;
 556	u32 tmp;
 557
 558	tmp = ioread32be(&regs->command_config);
 559	if (new_val)
 560		tmp |= CMD_CFG_PROMIS_EN;
 561	else
 562		tmp &= ~CMD_CFG_PROMIS_EN;
 563
 564	iowrite32be(tmp, &regs->command_config);
 565
 566	return 0;
 567}
 568
 569static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
 570				     u16 pause_time, u16 thresh_time)
 571{
 572	struct memac_regs __iomem *regs = memac->regs;
 573	u32 tmp;
 574
 575	tmp = ioread32be(&regs->tx_fifo_sections);
 576
 577	GET_TX_EMPTY_DEFAULT_VALUE(tmp);
 578	iowrite32be(tmp, &regs->tx_fifo_sections);
 579
 580	tmp = ioread32be(&regs->command_config);
 581	tmp &= ~CMD_CFG_PFC_MODE;
 582
 583	iowrite32be(tmp, &regs->command_config);
 584
 585	tmp = ioread32be(&regs->pause_quanta[priority / 2]);
 586	if (priority % 2)
 587		tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT;
 588	else
 589		tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT;
 590	tmp |= ((u32)pause_time << (16 * (priority % 2)));
 591	iowrite32be(tmp, &regs->pause_quanta[priority / 2]);
 592
 593	tmp = ioread32be(&regs->pause_thresh[priority / 2]);
 594	if (priority % 2)
 595		tmp &= CLXY_PAUSE_THRESH_CLX_QTH;
 596	else
 597		tmp &= CLXY_PAUSE_THRESH_CLY_QTH;
 598	tmp |= ((u32)thresh_time << (16 * (priority % 2)));
 599	iowrite32be(tmp, &regs->pause_thresh[priority / 2]);
 600
 601	return 0;
 602}
 603
 604static int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en)
 605{
 606	struct memac_regs __iomem *regs = memac->regs;
 607	u32 tmp;
 608
 609	tmp = ioread32be(&regs->command_config);
 610	if (en)
 611		tmp &= ~CMD_CFG_PAUSE_IGNORE;
 612	else
 613		tmp |= CMD_CFG_PAUSE_IGNORE;
 614
 615	iowrite32be(tmp, &regs->command_config);
 616
 617	return 0;
 618}
 619
 620static unsigned long memac_get_caps(struct phylink_config *config,
 621				    phy_interface_t interface)
 622{
 623	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
 624	unsigned long caps = config->mac_capabilities;
 625
 626	if (phy_interface_mode_is_rgmii(interface) &&
 627	    memac->rgmii_no_half_duplex)
 628		caps &= ~(MAC_10HD | MAC_100HD);
 629
 630	return caps;
 631}
 632
 633/**
 634 * memac_if_mode() - Convert an interface mode into an IF_MODE config
 635 * @interface: A phy interface mode
 636 *
 637 * Return: A configuration word, suitable for programming into the lower bits
 638 *         of %IF_MODE.
 639 */
 640static u32 memac_if_mode(phy_interface_t interface)
 641{
 642	switch (interface) {
 643	case PHY_INTERFACE_MODE_MII:
 644		return IF_MODE_MII;
 645	case PHY_INTERFACE_MODE_RGMII:
 646	case PHY_INTERFACE_MODE_RGMII_ID:
 647	case PHY_INTERFACE_MODE_RGMII_RXID:
 648	case PHY_INTERFACE_MODE_RGMII_TXID:
 649		return IF_MODE_GMII | IF_MODE_RGMII;
 650	case PHY_INTERFACE_MODE_SGMII:
 651	case PHY_INTERFACE_MODE_1000BASEX:
 652	case PHY_INTERFACE_MODE_2500BASEX:
 653	case PHY_INTERFACE_MODE_QSGMII:
 654		return IF_MODE_GMII;
 655	case PHY_INTERFACE_MODE_10GBASER:
 656		return IF_MODE_10G;
 657	default:
 658		WARN_ON_ONCE(1);
 659		return 0;
 660	}
 661}
 662
 663static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,
 664					    phy_interface_t iface)
 665{
 666	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
 667
 668	switch (iface) {
 669	case PHY_INTERFACE_MODE_SGMII:
 670	case PHY_INTERFACE_MODE_1000BASEX:
 671	case PHY_INTERFACE_MODE_2500BASEX:
 672		return memac->sgmii_pcs;
 673	case PHY_INTERFACE_MODE_QSGMII:
 674		return memac->qsgmii_pcs;
 675	case PHY_INTERFACE_MODE_10GBASER:
 676		return memac->xfi_pcs;
 677	default:
 678		return NULL;
 679	}
 680}
 681
 682static int memac_prepare(struct phylink_config *config, unsigned int mode,
 683			 phy_interface_t iface)
 684{
 685	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
 686
 687	switch (iface) {
 688	case PHY_INTERFACE_MODE_SGMII:
 689	case PHY_INTERFACE_MODE_1000BASEX:
 690	case PHY_INTERFACE_MODE_2500BASEX:
 691	case PHY_INTERFACE_MODE_QSGMII:
 692	case PHY_INTERFACE_MODE_10GBASER:
 693		return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
 694					iface);
 695	default:
 696		return 0;
 697	}
 698}
 699
 700static void memac_mac_config(struct phylink_config *config, unsigned int mode,
 701			     const struct phylink_link_state *state)
 702{
 703	struct mac_device *mac_dev = fman_config_to_mac(config);
 704	struct memac_regs __iomem *regs = mac_dev->fman_mac->regs;
 705	u32 tmp = ioread32be(&regs->if_mode);
 706
 707	tmp &= ~(IF_MODE_MASK | IF_MODE_RGMII);
 708	tmp |= memac_if_mode(state->interface);
 709	if (phylink_autoneg_inband(mode))
 710		tmp |= IF_MODE_RGMII_AUTO;
 711	iowrite32be(tmp, &regs->if_mode);
 712}
 713
 714static void memac_link_up(struct phylink_config *config, struct phy_device *phy,
 715			  unsigned int mode, phy_interface_t interface,
 716			  int speed, int duplex, bool tx_pause, bool rx_pause)
 717{
 718	struct mac_device *mac_dev = fman_config_to_mac(config);
 719	struct fman_mac *memac = mac_dev->fman_mac;
 720	struct memac_regs __iomem *regs = memac->regs;
 721	u32 tmp = memac_if_mode(interface);
 722	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
 723			 FSL_FM_PAUSE_TIME_DISABLE;
 724
 725	memac_set_tx_pause_frames(memac, 0, pause_time, 0);
 726	memac_accept_rx_pause_frames(memac, rx_pause);
 727
 728	if (duplex == DUPLEX_HALF)
 729		tmp |= IF_MODE_HD;
 730
 731	switch (speed) {
 732	case SPEED_1000:
 733		tmp |= IF_MODE_RGMII_1000;
 734		break;
 735	case SPEED_100:
 736		tmp |= IF_MODE_RGMII_100;
 737		break;
 738	case SPEED_10:
 739		tmp |= IF_MODE_RGMII_10;
 740		break;
 741	}
 742	iowrite32be(tmp, &regs->if_mode);
 743
 744	/* TODO: EEE? */
 745
 746	if (speed == SPEED_10000) {
 747		if (memac->fm_rev_info.major == 6 &&
 748		    memac->fm_rev_info.minor == 4)
 749			tmp = TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G;
 750		else
 751			tmp = TX_FIFO_SECTIONS_TX_AVAIL_10G;
 752		tmp |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G;
 753	} else {
 754		tmp = TX_FIFO_SECTIONS_TX_AVAIL_1G |
 755		      TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G;
 756	}
 757	iowrite32be(tmp, &regs->tx_fifo_sections);
 758
 759	mac_dev->update_speed(mac_dev, speed);
 760
 761	tmp = ioread32be(&regs->command_config);
 762	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
 763	iowrite32be(tmp, &regs->command_config);
 764}
 765
 766static void memac_link_down(struct phylink_config *config, unsigned int mode,
 767			    phy_interface_t interface)
 768{
 769	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
 770	struct memac_regs __iomem *regs = memac->regs;
 771	u32 tmp;
 772
 773	/* TODO: graceful */
 774	tmp = ioread32be(&regs->command_config);
 775	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
 776	iowrite32be(tmp, &regs->command_config);
 777}
 778
 779static const struct phylink_mac_ops memac_mac_ops = {
 780	.mac_get_caps = memac_get_caps,
 781	.mac_select_pcs = memac_select_pcs,
 782	.mac_prepare = memac_prepare,
 783	.mac_config = memac_mac_config,
 784	.mac_link_up = memac_link_up,
 785	.mac_link_down = memac_link_down,
 786};
 787
 788static int memac_modify_mac_address(struct fman_mac *memac,
 789				    const enet_addr_t *enet_addr)
 790{
 791	add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0);
 792
 793	return 0;
 794}
 795
 796static int memac_add_hash_mac_address(struct fman_mac *memac,
 797				      enet_addr_t *eth_addr)
 798{
 799	struct memac_regs __iomem *regs = memac->regs;
 800	struct eth_hash_entry *hash_entry;
 801	u32 hash;
 802	u64 addr;
 803
 804	addr = ENET_ADDR_TO_UINT64(*eth_addr);
 805
 806	if (!(addr & GROUP_ADDRESS)) {
 807		/* Unicast addresses not supported in hash */
 808		pr_err("Unicast Address\n");
 809		return -EINVAL;
 810	}
 811	hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
 812
 813	/* Create element to be added to the driver hash table */
 814	hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC);
 815	if (!hash_entry)
 816		return -ENOMEM;
 817	hash_entry->addr = addr;
 818	INIT_LIST_HEAD(&hash_entry->node);
 819
 820	list_add_tail(&hash_entry->node,
 821		      &memac->multicast_addr_hash->lsts[hash]);
 822	iowrite32be(hash | HASH_CTRL_MCAST_EN, &regs->hashtable_ctrl);
 823
 824	return 0;
 825}
 826
 827static int memac_set_allmulti(struct fman_mac *memac, bool enable)
 828{
 829	u32 entry;
 830	struct memac_regs __iomem *regs = memac->regs;
 831
 832	if (enable) {
 833		for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
 834			iowrite32be(entry | HASH_CTRL_MCAST_EN,
 835				    &regs->hashtable_ctrl);
 836	} else {
 837		for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
 838			iowrite32be(entry & ~HASH_CTRL_MCAST_EN,
 839				    &regs->hashtable_ctrl);
 840	}
 841
 842	memac->allmulti_enabled = enable;
 843
 844	return 0;
 845}
 846
 847static int memac_set_tstamp(struct fman_mac *memac, bool enable)
 848{
 849	return 0; /* Always enabled. */
 850}
 851
 852static int memac_del_hash_mac_address(struct fman_mac *memac,
 853				      enet_addr_t *eth_addr)
 854{
 855	struct memac_regs __iomem *regs = memac->regs;
 856	struct eth_hash_entry *hash_entry = NULL;
 857	struct list_head *pos;
 858	u32 hash;
 859	u64 addr;
 860
 861	addr = ENET_ADDR_TO_UINT64(*eth_addr);
 862
 863	hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
 864
 865	list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) {
 866		hash_entry = ETH_HASH_ENTRY_OBJ(pos);
 867		if (hash_entry && hash_entry->addr == addr) {
 868			list_del_init(&hash_entry->node);
 869			kfree(hash_entry);
 870			break;
 871		}
 872	}
 873
 874	if (!memac->allmulti_enabled) {
 875		if (list_empty(&memac->multicast_addr_hash->lsts[hash]))
 876			iowrite32be(hash & ~HASH_CTRL_MCAST_EN,
 877				    &regs->hashtable_ctrl);
 878	}
 879
 880	return 0;
 881}
 882
 883static int memac_set_exception(struct fman_mac *memac,
 884			       enum fman_mac_exceptions exception, bool enable)
 885{
 886	u32 bit_mask = 0;
 887
 888	bit_mask = get_exception_flag(exception);
 889	if (bit_mask) {
 890		if (enable)
 891			memac->exceptions |= bit_mask;
 892		else
 893			memac->exceptions &= ~bit_mask;
 894	} else {
 895		pr_err("Undefined exception\n");
 896		return -EINVAL;
 897	}
 898	set_exception(memac->regs, bit_mask, enable);
 899
 900	return 0;
 901}
 902
 903static u64 memac_read64(void __iomem *reg)
 904{
 905	u32 low, high, tmp;
 906
 907	do {
 908		high = ioread32be(reg + 4);
 909		low = ioread32be(reg);
 910		tmp = ioread32be(reg + 4);
 911	} while (high != tmp);
 912
 913	return ((u64)high << 32) | low;
 914}
 915
 916static void memac_get_pause_stats(struct fman_mac *memac,
 917				  struct ethtool_pause_stats *s)
 918{
 919	s->tx_pause_frames = memac_read64(&memac->regs->txpf_l);
 920	s->rx_pause_frames = memac_read64(&memac->regs->rxpf_l);
 921}
 922
 923static const struct ethtool_rmon_hist_range memac_rmon_ranges[] = {
 924	{   64,   64 },
 925	{   65,  127 },
 926	{  128,  255 },
 927	{  256,  511 },
 928	{  512, 1023 },
 929	{ 1024, 1518 },
 930	{ 1519, 9600 },
 931	{},
 932};
 933
 934static void memac_get_rmon_stats(struct fman_mac *memac,
 935				 struct ethtool_rmon_stats *s,
 936				 const struct ethtool_rmon_hist_range **ranges)
 937{
 938	s->undersize_pkts = memac_read64(&memac->regs->rund_l);
 939	s->oversize_pkts = memac_read64(&memac->regs->rovr_l);
 940	s->fragments = memac_read64(&memac->regs->rfrg_l);
 941	s->jabbers = memac_read64(&memac->regs->rjbr_l);
 942
 943	s->hist[0] = memac_read64(&memac->regs->r64_l);
 944	s->hist[1] = memac_read64(&memac->regs->r127_l);
 945	s->hist[2] = memac_read64(&memac->regs->r255_l);
 946	s->hist[3] = memac_read64(&memac->regs->r511_l);
 947	s->hist[4] = memac_read64(&memac->regs->r1023_l);
 948	s->hist[5] = memac_read64(&memac->regs->r1518_l);
 949	s->hist[6] = memac_read64(&memac->regs->r1519x_l);
 950
 951	s->hist_tx[0] = memac_read64(&memac->regs->t64_l);
 952	s->hist_tx[1] = memac_read64(&memac->regs->t127_l);
 953	s->hist_tx[2] = memac_read64(&memac->regs->t255_l);
 954	s->hist_tx[3] = memac_read64(&memac->regs->t511_l);
 955	s->hist_tx[4] = memac_read64(&memac->regs->t1023_l);
 956	s->hist_tx[5] = memac_read64(&memac->regs->t1518_l);
 957	s->hist_tx[6] = memac_read64(&memac->regs->t1519x_l);
 958
 959	*ranges = memac_rmon_ranges;
 960}
 961
 962static void memac_get_eth_ctrl_stats(struct fman_mac *memac,
 963				     struct ethtool_eth_ctrl_stats *s)
 964{
 965	s->MACControlFramesTransmitted = memac_read64(&memac->regs->tcnp_l);
 966	s->MACControlFramesReceived = memac_read64(&memac->regs->rcnp_l);
 967}
 968
 969static void memac_get_eth_mac_stats(struct fman_mac *memac,
 970				    struct ethtool_eth_mac_stats *s)
 971{
 972	s->FramesTransmittedOK = memac_read64(&memac->regs->tfrm_l);
 973	s->FramesReceivedOK = memac_read64(&memac->regs->rfrm_l);
 974	s->FrameCheckSequenceErrors = memac_read64(&memac->regs->rfcs_l);
 975	s->AlignmentErrors = memac_read64(&memac->regs->raln_l);
 976	s->OctetsTransmittedOK = memac_read64(&memac->regs->teoct_l);
 977	s->FramesLostDueToIntMACXmitError = memac_read64(&memac->regs->terr_l);
 978	s->OctetsReceivedOK = memac_read64(&memac->regs->reoct_l);
 979	s->FramesLostDueToIntMACRcvError = memac_read64(&memac->regs->rdrntp_l);
 980	s->MulticastFramesXmittedOK = memac_read64(&memac->regs->tmca_l);
 981	s->BroadcastFramesXmittedOK = memac_read64(&memac->regs->tbca_l);
 982	s->MulticastFramesReceivedOK = memac_read64(&memac->regs->rmca_l);
 983	s->BroadcastFramesReceivedOK = memac_read64(&memac->regs->rbca_l);
 984}
 985
 986static int memac_init(struct fman_mac *memac)
 987{
 988	struct memac_cfg *memac_drv_param;
 989	enet_addr_t eth_addr;
 990	int err;
 991	u32 reg32 = 0;
 992
 993	err = check_init_parameters(memac);
 994	if (err)
 995		return err;
 996
 997	memac_drv_param = memac->memac_drv_param;
 998
 999	/* First, reset the MAC if desired. */
1000	if (memac_drv_param->reset_on_init) {
1001		err = reset(memac->regs);
1002		if (err) {
1003			pr_err("mEMAC reset failed\n");
1004			return err;
1005		}
1006	}
1007
1008	/* MAC Address */
1009	if (memac->addr != 0) {
1010		MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr);
1011		add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0);
1012	}
1013
1014	init(memac->regs, memac->memac_drv_param, memac->exceptions);
1015
1016	/* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
1017	 * Exists only in FMan 6.0 and 6.3.
1018	 */
1019	if ((memac->fm_rev_info.major == 6) &&
1020	    ((memac->fm_rev_info.minor == 0) ||
1021	    (memac->fm_rev_info.minor == 3))) {
1022		/* MAC strips CRC from received frames - this workaround
1023		 * should decrease the likelihood of bug appearance
1024		 */
1025		reg32 = ioread32be(&memac->regs->command_config);
1026		reg32 &= ~CMD_CFG_CRC_FWD;
1027		iowrite32be(reg32, &memac->regs->command_config);
1028	}
1029
1030	/* Max Frame Length */
1031	err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
1032				     memac_drv_param->max_frame_length);
1033	if (err) {
1034		pr_err("settings Mac max frame length is FAILED\n");
1035		return err;
1036	}
1037
1038	memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
1039	if (!memac->multicast_addr_hash) {
1040		free_init_resources(memac);
1041		pr_err("allocation hash table is FAILED\n");
1042		return -ENOMEM;
1043	}
1044
1045	memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
1046	if (!memac->unicast_addr_hash) {
1047		free_init_resources(memac);
1048		pr_err("allocation hash table is FAILED\n");
1049		return -ENOMEM;
1050	}
1051
1052	fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
1053			   FMAN_INTR_TYPE_ERR, memac_err_exception, memac);
1054
1055	fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
1056			   FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
1057
1058	return 0;
1059}
1060
1061static void pcs_put(struct phylink_pcs *pcs)
1062{
1063	if (IS_ERR_OR_NULL(pcs))
1064		return;
1065
1066	lynx_pcs_destroy(pcs);
1067}
1068
1069static int memac_free(struct fman_mac *memac)
1070{
1071	free_init_resources(memac);
1072
1073	pcs_put(memac->sgmii_pcs);
1074	pcs_put(memac->qsgmii_pcs);
1075	pcs_put(memac->xfi_pcs);
1076	kfree(memac->memac_drv_param);
1077	kfree(memac);
1078
1079	return 0;
1080}
1081
1082static struct fman_mac *memac_config(struct mac_device *mac_dev,
1083				     struct fman_mac_params *params)
1084{
1085	struct fman_mac *memac;
1086	struct memac_cfg *memac_drv_param;
1087
1088	/* allocate memory for the m_emac data structure */
1089	memac = kzalloc(sizeof(*memac), GFP_KERNEL);
1090	if (!memac)
1091		return NULL;
1092
1093	/* allocate memory for the m_emac driver parameters data structure */
1094	memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL);
1095	if (!memac_drv_param) {
1096		memac_free(memac);
1097		return NULL;
1098	}
1099
1100	/* Plant parameter structure pointer */
1101	memac->memac_drv_param = memac_drv_param;
1102
1103	set_dflts(memac_drv_param);
1104
1105	memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
1106
1107	memac->regs = mac_dev->vaddr;
1108	memac->mac_id = params->mac_id;
1109	memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
1110			     MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
1111	memac->exception_cb = params->exception_cb;
1112	memac->event_cb = params->event_cb;
1113	memac->dev_id = mac_dev;
1114	memac->fm = params->fm;
1115
1116	/* Save FMan revision */
1117	fman_get_revision(memac->fm, &memac->fm_rev_info);
1118
1119	return memac;
1120}
1121
1122static struct phylink_pcs *memac_pcs_create(struct device_node *mac_node,
1123					    int index)
1124{
1125	struct device_node *node;
1126	struct phylink_pcs *pcs;
1127
1128	node = of_parse_phandle(mac_node, "pcsphy-handle", index);
1129	if (!node)
1130		return ERR_PTR(-ENODEV);
1131
1132	pcs = lynx_pcs_create_fwnode(of_fwnode_handle(node));
1133	of_node_put(node);
1134
1135	return pcs;
1136}
1137
1138static bool memac_supports(struct mac_device *mac_dev, phy_interface_t iface)
1139{
1140	/* If there's no serdes device, assume that it's been configured for
1141	 * whatever the default interface mode is.
1142	 */
1143	if (!mac_dev->fman_mac->serdes)
1144		return mac_dev->phy_if == iface;
1145	/* Otherwise, ask the serdes */
1146	return !phy_validate(mac_dev->fman_mac->serdes, PHY_MODE_ETHERNET,
1147			     iface, NULL);
1148}
1149
1150int memac_initialization(struct mac_device *mac_dev,
1151			 struct device_node *mac_node,
1152			 struct fman_mac_params *params)
1153{
1154	int			 err;
1155	struct phylink_pcs	*pcs;
1156	struct fman_mac		*memac;
1157	unsigned long		 capabilities;
1158	unsigned long		*supported;
1159
1160	/* The internal connection to the serdes is XGMII, but this isn't
1161	 * really correct for the phy mode (which is the external connection).
1162	 * However, this is how all older device trees say that they want
1163	 * 10GBASE-R (aka XFI), so just convert it for them.
1164	 */
1165	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
1166		mac_dev->phy_if = PHY_INTERFACE_MODE_10GBASER;
1167
1168	mac_dev->phylink_ops		= &memac_mac_ops;
1169	mac_dev->set_promisc		= memac_set_promiscuous;
1170	mac_dev->change_addr		= memac_modify_mac_address;
1171	mac_dev->add_hash_mac_addr	= memac_add_hash_mac_address;
1172	mac_dev->remove_hash_mac_addr	= memac_del_hash_mac_address;
1173	mac_dev->set_exception		= memac_set_exception;
1174	mac_dev->set_allmulti		= memac_set_allmulti;
1175	mac_dev->set_tstamp		= memac_set_tstamp;
1176	mac_dev->enable			= memac_enable;
1177	mac_dev->disable		= memac_disable;
1178	mac_dev->get_pause_stats	= memac_get_pause_stats;
1179	mac_dev->get_rmon_stats		= memac_get_rmon_stats;
1180	mac_dev->get_eth_ctrl_stats	= memac_get_eth_ctrl_stats;
1181	mac_dev->get_eth_mac_stats	= memac_get_eth_mac_stats;
1182
1183	mac_dev->fman_mac = memac_config(mac_dev, params);
1184	if (!mac_dev->fman_mac)
1185		return -EINVAL;
1186
1187	memac = mac_dev->fman_mac;
1188	memac->memac_drv_param->max_frame_length = fman_get_max_frm();
1189	memac->memac_drv_param->reset_on_init = true;
1190
1191	err = of_property_match_string(mac_node, "pcs-handle-names", "xfi");
1192	if (err >= 0) {
1193		memac->xfi_pcs = memac_pcs_create(mac_node, err);
1194		if (IS_ERR(memac->xfi_pcs)) {
1195			err = PTR_ERR(memac->xfi_pcs);
1196			dev_err_probe(mac_dev->dev, err, "missing xfi pcs\n");
1197			goto _return_fm_mac_free;
1198		}
1199	} else if (err != -EINVAL && err != -ENODATA) {
1200		goto _return_fm_mac_free;
1201	}
1202
1203	err = of_property_match_string(mac_node, "pcs-handle-names", "qsgmii");
1204	if (err >= 0) {
1205		memac->qsgmii_pcs = memac_pcs_create(mac_node, err);
1206		if (IS_ERR(memac->qsgmii_pcs)) {
1207			err = PTR_ERR(memac->qsgmii_pcs);
1208			dev_err_probe(mac_dev->dev, err,
1209				      "missing qsgmii pcs\n");
1210			goto _return_fm_mac_free;
1211		}
1212	} else if (err != -EINVAL && err != -ENODATA) {
1213		goto _return_fm_mac_free;
1214	}
1215
1216	/* For compatibility, if pcs-handle-names is missing, we assume this
1217	 * phy is the first one in pcsphy-handle
1218	 */
1219	err = of_property_match_string(mac_node, "pcs-handle-names", "sgmii");
1220	if (err == -EINVAL || err == -ENODATA)
1221		pcs = memac_pcs_create(mac_node, 0);
1222	else if (err < 0)
1223		goto _return_fm_mac_free;
1224	else
1225		pcs = memac_pcs_create(mac_node, err);
1226
1227	if (IS_ERR(pcs)) {
1228		err = PTR_ERR(pcs);
1229		dev_err_probe(mac_dev->dev, err, "missing pcs\n");
1230		goto _return_fm_mac_free;
1231	}
1232
1233	/* If err is set here, it means that pcs-handle-names was missing above
1234	 * (and therefore that xfi_pcs cannot be set). If we are defaulting to
1235	 * XGMII, assume this is for XFI. Otherwise, assume it is for SGMII.
1236	 */
1237	if (err && mac_dev->phy_if == PHY_INTERFACE_MODE_10GBASER)
1238		memac->xfi_pcs = pcs;
1239	else
1240		memac->sgmii_pcs = pcs;
1241
1242	memac->serdes = devm_of_phy_optional_get(mac_dev->dev, mac_node,
1243						 "serdes");
1244	if (!memac->serdes) {
1245		dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
1246	} else if (IS_ERR(memac->serdes)) {
1247		err = PTR_ERR(memac->serdes);
1248		goto _return_fm_mac_free;
1249	}
1250
1251	/* TODO: The following interface modes are supported by (some) hardware
1252	 * but not by this driver:
1253	 * - 1000BASE-KX
1254	 * - 10GBASE-KR
1255	 * - XAUI/HiGig
1256	 */
1257	supported = mac_dev->phylink_config.supported_interfaces;
1258
1259	/* Note that half duplex is only supported on 10/100M interfaces. */
1260
1261	if (memac->sgmii_pcs &&
1262	    (memac_supports(mac_dev, PHY_INTERFACE_MODE_SGMII) ||
1263	     memac_supports(mac_dev, PHY_INTERFACE_MODE_1000BASEX))) {
1264		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
1265		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
1266	}
1267
1268	if (memac->sgmii_pcs &&
1269	    memac_supports(mac_dev, PHY_INTERFACE_MODE_2500BASEX))
1270		__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
1271
1272	if (memac->qsgmii_pcs &&
1273	    memac_supports(mac_dev, PHY_INTERFACE_MODE_QSGMII))
1274		__set_bit(PHY_INTERFACE_MODE_QSGMII, supported);
1275	else if (mac_dev->phy_if == PHY_INTERFACE_MODE_QSGMII)
1276		dev_warn(mac_dev->dev, "no QSGMII pcs specified\n");
1277
1278	if (memac->xfi_pcs &&
1279	    memac_supports(mac_dev, PHY_INTERFACE_MODE_10GBASER)) {
1280		__set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
1281	} else {
1282		/* From what I can tell, no 10g macs support RGMII. */
1283		phy_interface_set_rgmii(supported);
1284		__set_bit(PHY_INTERFACE_MODE_MII, supported);
1285	}
1286
1287	capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100;
1288	capabilities |= MAC_1000FD | MAC_2500FD | MAC_10000FD;
1289
1290	/* These SoCs don't support half duplex at all; there's no different
1291	 * FMan version or compatible, so we just have to check the machine
1292	 * compatible instead
1293	 */
1294	if (of_machine_is_compatible("fsl,ls1043a") ||
1295	    of_machine_is_compatible("fsl,ls1046a") ||
1296	    of_machine_is_compatible("fsl,B4QDS"))
1297		capabilities &= ~(MAC_10HD | MAC_100HD);
1298
1299	mac_dev->phylink_config.mac_capabilities = capabilities;
1300
1301	/* The T2080 and T4240 don't support half duplex RGMII. There is no
1302	 * other way to identify these SoCs, so just use the machine
1303	 * compatible.
1304	 */
1305	if (of_machine_is_compatible("fsl,T2080QDS") ||
1306	    of_machine_is_compatible("fsl,T2080RDB") ||
1307	    of_machine_is_compatible("fsl,T2081QDS") ||
1308	    of_machine_is_compatible("fsl,T4240QDS") ||
1309	    of_machine_is_compatible("fsl,T4240RDB"))
1310		memac->rgmii_no_half_duplex = true;
1311
1312	/* Most boards should use MLO_AN_INBAND, but existing boards don't have
1313	 * a managed property. Default to MLO_AN_INBAND rather than MLO_AN_PHY.
1314	 * Phylink will allow this to be overriden by a fixed link. We need to
1315	 * be careful and not enable this if we are using MII or RGMII, since
1316	 * those configurations modes don't use in-band autonegotiation.
1317	 */
1318	if (!of_property_present(mac_node, "managed") &&
1319	    mac_dev->phy_if != PHY_INTERFACE_MODE_2500BASEX &&
1320	    mac_dev->phy_if != PHY_INTERFACE_MODE_MII &&
1321	    !phy_interface_mode_is_rgmii(mac_dev->phy_if))
1322		mac_dev->phylink_config.default_an_inband = true;
1323
1324	err = memac_init(mac_dev->fman_mac);
1325	if (err < 0)
1326		goto _return_fm_mac_free;
1327
1328	dev_info(mac_dev->dev, "FMan MEMAC\n");
1329
1330	return 0;
1331
1332_return_fm_mac_free:
1333	memac_free(mac_dev->fman_mac);
1334	return err;
1335}