fec_ptp.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Fast Ethernet Controller (ENET) PTP driver for MX6x.
  4 *
  5 * Copyright (C) 2012 Freescale Semiconductor, Inc.
  6 */
  7
  8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  9
 10#include <linux/bitops.h>
 11#include <linux/clk.h>
 12#include <linux/delay.h>
 13#include <linux/errno.h>
 14#include <linux/etherdevice.h>
 15#include <linux/fec.h>
 16#include <linux/interrupt.h>
 17#include <linux/io.h>
 18#include <linux/ioport.h>
 19#include <linux/irq.h>
 20#include <linux/kernel.h>
 21#include <linux/module.h>
 22#include <linux/netdevice.h>
 23#include <linux/of.h>
 24#include <linux/of_net.h>
 25#include <linux/pci.h>
 26#include <linux/phy.h>
 27#include <linux/platform_device.h>
 28#include <linux/ptrace.h>
 29#include <linux/skbuff.h>
 30#include <linux/slab.h>
 31#include <linux/spinlock.h>
 32#include <linux/string.h>
 33#include <linux/workqueue.h>
 34
 35#include "fec.h"
 36
 37/* FEC 1588 register bits */
 38#define FEC_T_CTRL_SLAVE                0x00002000
 39#define FEC_T_CTRL_CAPTURE              0x00000800
 40#define FEC_T_CTRL_RESTART              0x00000200
 41#define FEC_T_CTRL_PERIOD_RST           0x00000030
 42#define FEC_T_CTRL_PERIOD_EN		0x00000010
 43#define FEC_T_CTRL_ENABLE               0x00000001
 44
 45#define FEC_T_INC_MASK                  0x0000007f
 46#define FEC_T_INC_OFFSET                0
 47#define FEC_T_INC_CORR_MASK             0x00007f00
 48#define FEC_T_INC_CORR_OFFSET           8
 49
 50#define FEC_T_CTRL_PINPER		0x00000080
 51#define FEC_T_TF0_MASK			0x00000001
 52#define FEC_T_TF0_OFFSET		0
 53#define FEC_T_TF1_MASK			0x00000002
 54#define FEC_T_TF1_OFFSET		1
 55#define FEC_T_TF2_MASK			0x00000004
 56#define FEC_T_TF2_OFFSET		2
 57#define FEC_T_TF3_MASK			0x00000008
 58#define FEC_T_TF3_OFFSET		3
 59#define FEC_T_TDRE_MASK			0x00000001
 60#define FEC_T_TDRE_OFFSET		0
 61#define FEC_T_TMODE_MASK		0x0000003C
 62#define FEC_T_TMODE_OFFSET		2
 63#define FEC_T_TIE_MASK			0x00000040
 64#define FEC_T_TIE_OFFSET		6
 65#define FEC_T_TF_MASK			0x00000080
 66#define FEC_T_TF_OFFSET			7
 67
 68#define FEC_ATIME_CTRL		0x400
 69#define FEC_ATIME		0x404
 70#define FEC_ATIME_EVT_OFFSET	0x408
 71#define FEC_ATIME_EVT_PERIOD	0x40c
 72#define FEC_ATIME_CORR		0x410
 73#define FEC_ATIME_INC		0x414
 74#define FEC_TS_TIMESTAMP	0x418
 75
 76#define FEC_TGSR		0x604
 77#define FEC_TCSR(n)		(0x608 + n * 0x08)
 78#define FEC_TCCR(n)		(0x60C + n * 0x08)
 79#define MAX_TIMER_CHANNEL	3
 80#define FEC_TMODE_TOGGLE	0x05
 81#define FEC_HIGH_PULSE		0x0F
 82
 83#define FEC_CC_MULT	(1 << 31)
 84#define FEC_COUNTER_PERIOD	(1 << 31)
 85#define PPS_OUPUT_RELOAD_PERIOD	NSEC_PER_SEC
 86#define DEFAULT_PPS_CHANNEL	0
 87
 88#define FEC_PTP_MAX_NSEC_PERIOD		4000000000ULL
 89#define FEC_PTP_MAX_NSEC_COUNTER	0x80000000ULL
 90
 91/**
 92 * fec_ptp_read - read raw cycle counter (to be used by time counter)
 93 * @cc: the cyclecounter structure
 94 *
 95 * this function reads the cyclecounter registers and is called by the
 96 * cyclecounter structure used to construct a ns counter from the
 97 * arbitrary fixed point registers
 98 */
 99static u64 fec_ptp_read(struct cyclecounter *cc)
100{
101	struct fec_enet_private *fep =
102		container_of(cc, struct fec_enet_private, cc);
103	u32 tempval;
104
105	tempval = readl(fep->hwp + FEC_ATIME_CTRL);
106	tempval |= FEC_T_CTRL_CAPTURE;
107	writel(tempval, fep->hwp + FEC_ATIME_CTRL);
108
109	if (fep->quirks & FEC_QUIRK_BUG_CAPTURE)
110		udelay(1);
111
112	return readl(fep->hwp + FEC_ATIME);
113}
114
115/**
116 * fec_ptp_enable_pps
117 * @fep: the fec_enet_private structure handle
118 * @enable: enable the channel pps output
119 *
120 * This function enables the PPS output on the timer channel.
121 */
122static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
123{
124	unsigned long flags;
125	u32 val, tempval;
126	struct timespec64 ts;
127	u64 ns;
128
129	spin_lock_irqsave(&fep->tmreg_lock, flags);
130
131	if (fep->perout_enable) {
132		spin_unlock_irqrestore(&fep->tmreg_lock, flags);
133		dev_err(&fep->pdev->dev, "PEROUT is running");
134		return -EBUSY;
135	}
136
137	if (fep->pps_enable == enable) {
138		spin_unlock_irqrestore(&fep->tmreg_lock, flags);
139		return 0;
140	}
141
142	if (enable) {
143		/* clear capture or output compare interrupt status if have.
144		 */
145		writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
146
147		/* It is recommended to double check the TMODE field in the
148		 * TCSR register to be cleared before the first compare counter
149		 * is written into TCCR register. Just add a double check.
150		 */
151		val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
152		do {
153			val &= ~(FEC_T_TMODE_MASK);
154			writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
155			val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
156		} while (val & FEC_T_TMODE_MASK);
157
158		/* Dummy read counter to update the counter */
159		timecounter_read(&fep->tc);
160		/* We want to find the first compare event in the next
161		 * second point. So we need to know what the ptp time
162		 * is now and how many nanoseconds is ahead to get next second.
163		 * The remaining nanosecond ahead before the next second would be
164		 * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds
165		 * to current timer would be next second.
166		 */
167		tempval = fec_ptp_read(&fep->cc);
168		/* Convert the ptp local counter to 1588 timestamp */
169		ns = timecounter_cyc2time(&fep->tc, tempval);
170		ts = ns_to_timespec64(ns);
171
172		/* The tempval is  less than 3 seconds, and  so val is less than
173		 * 4 seconds. No overflow for 32bit calculation.
174		 */
175		val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval;
176
177		/* Need to consider the situation that the current time is
178		 * very close to the second point, which means NSEC_PER_SEC
179		 * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer
180		 * is still running when we calculate the first compare event, it is
181		 * possible that the remaining nanoseconds run out before the compare
182		 * counter is calculated and written into TCCR register. To avoid
183		 * this possibility, we will set the compare event to be the next
184		 * of next second. The current setting is 31-bit timer and wrap
185		 * around over 2 seconds. So it is okay to set the next of next
186		 * seond for the timer.
187		 */
188		val += NSEC_PER_SEC;
189
190		/* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current
191		 * ptp counter, which maybe cause 32-bit wrap. Since the
192		 * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second.
193		 * We can ensure the wrap will not cause issue. If the offset
194		 * is bigger than fep->cc.mask would be a error.
195		 */
196		val &= fep->cc.mask;
197		writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));
198
199		/* Calculate the second the compare event timestamp */
200		fep->next_counter = (val + fep->reload_period) & fep->cc.mask;
201
202		/* * Enable compare event when overflow */
203		val = readl(fep->hwp + FEC_ATIME_CTRL);
204		val |= FEC_T_CTRL_PINPER;
205		writel(val, fep->hwp + FEC_ATIME_CTRL);
206
207		/* Compare channel setting. */
208		val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
209		val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET);
210		val &= ~(1 << FEC_T_TDRE_OFFSET);
211		val &= ~(FEC_T_TMODE_MASK);
212		val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET);
213		writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
214
215		/* Write the second compare event timestamp and calculate
216		 * the third timestamp. Refer the TCCR register detail in the spec.
217		 */
218		writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
219		fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
220	} else {
221		writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
222	}
223
224	fep->pps_enable = enable;
225	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
226
227	return 0;
228}
229
230static int fec_ptp_pps_perout(struct fec_enet_private *fep)
231{
232	u32 compare_val, ptp_hc, temp_val;
233	u64 curr_time;
234	unsigned long flags;
235
236	spin_lock_irqsave(&fep->tmreg_lock, flags);
237
238	/* Update time counter */
239	timecounter_read(&fep->tc);
240
241	/* Get the current ptp hardware time counter */
242	ptp_hc = fec_ptp_read(&fep->cc);
243
244	/* Convert the ptp local counter to 1588 timestamp */
245	curr_time = timecounter_cyc2time(&fep->tc, ptp_hc);
246
247	/* If the pps start time less than current time add 100ms, just return.
248	 * Because the software might not able to set the comparison time into
249	 * the FEC_TCCR register in time and missed the start time.
250	 */
251	if (fep->perout_stime < curr_time + 100 * NSEC_PER_MSEC) {
252		fep->perout_enable = false;
253		dev_err(&fep->pdev->dev, "Current time is too close to the start time!\n");
254		spin_unlock_irqrestore(&fep->tmreg_lock, flags);
255		return -1;
256	}
257
258	compare_val = fep->perout_stime - curr_time + ptp_hc;
259	compare_val &= fep->cc.mask;
260
261	writel(compare_val, fep->hwp + FEC_TCCR(fep->pps_channel));
262	fep->next_counter = (compare_val + fep->reload_period) & fep->cc.mask;
263
264	/* Enable compare event when overflow */
265	temp_val = readl(fep->hwp + FEC_ATIME_CTRL);
266	temp_val |= FEC_T_CTRL_PINPER;
267	writel(temp_val, fep->hwp + FEC_ATIME_CTRL);
268
269	/* Compare channel setting. */
270	temp_val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
271	temp_val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET);
272	temp_val &= ~(1 << FEC_T_TDRE_OFFSET);
273	temp_val &= ~(FEC_T_TMODE_MASK);
274	temp_val |= (FEC_TMODE_TOGGLE << FEC_T_TMODE_OFFSET);
275	writel(temp_val, fep->hwp + FEC_TCSR(fep->pps_channel));
276
277	/* Write the second compare event timestamp and calculate
278	 * the third timestamp. Refer the TCCR register detail in the spec.
279	 */
280	writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
281	fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
282	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
283
284	return 0;
285}
286
287static enum hrtimer_restart fec_ptp_pps_perout_handler(struct hrtimer *timer)
288{
289	struct fec_enet_private *fep = container_of(timer,
290					struct fec_enet_private, perout_timer);
291
292	fec_ptp_pps_perout(fep);
293
294	return HRTIMER_NORESTART;
295}
296
297/**
298 * fec_ptp_start_cyclecounter - create the cycle counter from hw
299 * @ndev: network device
300 *
301 * this function initializes the timecounter and cyclecounter
302 * structures for use in generated a ns counter from the arbitrary
303 * fixed point cycles registers in the hardware.
304 */
305void fec_ptp_start_cyclecounter(struct net_device *ndev)
306{
307	struct fec_enet_private *fep = netdev_priv(ndev);
308	unsigned long flags;
309	int inc;
310
311	inc = 1000000000 / fep->cycle_speed;
312
313	/* grab the ptp lock */
314	spin_lock_irqsave(&fep->tmreg_lock, flags);
315
316	/* 1ns counter */
317	writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
318
319	/* use 31-bit timer counter */
320	writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
321
322	writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST,
323		fep->hwp + FEC_ATIME_CTRL);
324
325	memset(&fep->cc, 0, sizeof(fep->cc));
326	fep->cc.read = fec_ptp_read;
327	fep->cc.mask = CLOCKSOURCE_MASK(31);
328	fep->cc.shift = 31;
329	fep->cc.mult = FEC_CC_MULT;
330
331	/* reset the ns time counter */
332	timecounter_init(&fep->tc, &fep->cc, 0);
333
334	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
335}
336
337/**
338 * fec_ptp_adjfine - adjust ptp cycle frequency
339 * @ptp: the ptp clock structure
340 * @scaled_ppm: scaled parts per million adjustment from base
341 *
342 * Adjust the frequency of the ptp cycle counter by the
343 * indicated amount from the base frequency.
344 *
345 * Scaled parts per million is ppm with a 16-bit binary fractional field.
346 *
347 * Because ENET hardware frequency adjust is complex,
348 * using software method to do that.
349 */
350static int fec_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
351{
352	s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
353	unsigned long flags;
354	int neg_adj = 0;
355	u32 i, tmp;
356	u32 corr_inc, corr_period;
357	u32 corr_ns;
358	u64 lhs, rhs;
359
360	struct fec_enet_private *fep =
361	    container_of(ptp, struct fec_enet_private, ptp_caps);
362
363	if (ppb == 0)
364		return 0;
365
366	if (ppb < 0) {
367		ppb = -ppb;
368		neg_adj = 1;
369	}
370
371	/* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC;
372	 * Try to find the corr_inc  between 1 to fep->ptp_inc to
373	 * meet adjustment requirement.
374	 */
375	lhs = NSEC_PER_SEC;
376	rhs = (u64)ppb * (u64)fep->ptp_inc;
377	for (i = 1; i <= fep->ptp_inc; i++) {
378		if (lhs >= rhs) {
379			corr_inc = i;
380			corr_period = div_u64(lhs, rhs);
381			break;
382		}
383		lhs += NSEC_PER_SEC;
384	}
385	/* Not found? Set it to high value - double speed
386	 * correct in every clock step.
387	 */
388	if (i > fep->ptp_inc) {
389		corr_inc = fep->ptp_inc;
390		corr_period = 1;
391	}
392
393	if (neg_adj)
394		corr_ns = fep->ptp_inc - corr_inc;
395	else
396		corr_ns = fep->ptp_inc + corr_inc;
397
398	spin_lock_irqsave(&fep->tmreg_lock, flags);
399
400	tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
401	tmp |= corr_ns << FEC_T_INC_CORR_OFFSET;
402	writel(tmp, fep->hwp + FEC_ATIME_INC);
403	corr_period = corr_period > 1 ? corr_period - 1 : corr_period;
404	writel(corr_period, fep->hwp + FEC_ATIME_CORR);
405	/* dummy read to update the timer. */
406	timecounter_read(&fep->tc);
407
408	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
409
410	return 0;
411}
412
413/**
414 * fec_ptp_adjtime
415 * @ptp: the ptp clock structure
416 * @delta: offset to adjust the cycle counter by
417 *
418 * adjust the timer by resetting the timecounter structure.
419 */
420static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
421{
422	struct fec_enet_private *fep =
423	    container_of(ptp, struct fec_enet_private, ptp_caps);
424	unsigned long flags;
425
426	spin_lock_irqsave(&fep->tmreg_lock, flags);
427	timecounter_adjtime(&fep->tc, delta);
428	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
429
430	return 0;
431}
432
433/**
434 * fec_ptp_gettime
435 * @ptp: the ptp clock structure
436 * @ts: timespec structure to hold the current time value
437 *
438 * read the timecounter and return the correct value on ns,
439 * after converting it into a struct timespec.
440 */
441static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
442{
443	struct fec_enet_private *fep =
444	    container_of(ptp, struct fec_enet_private, ptp_caps);
445	u64 ns;
446	unsigned long flags;
447
448	mutex_lock(&fep->ptp_clk_mutex);
449	/* Check the ptp clock */
450	if (!fep->ptp_clk_on) {
451		mutex_unlock(&fep->ptp_clk_mutex);
452		return -EINVAL;
453	}
454	spin_lock_irqsave(&fep->tmreg_lock, flags);
455	ns = timecounter_read(&fep->tc);
456	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
457	mutex_unlock(&fep->ptp_clk_mutex);
458
459	*ts = ns_to_timespec64(ns);
460
461	return 0;
462}
463
464/**
465 * fec_ptp_settime
466 * @ptp: the ptp clock structure
467 * @ts: the timespec containing the new time for the cycle counter
468 *
469 * reset the timecounter to use a new base value instead of the kernel
470 * wall timer value.
471 */
472static int fec_ptp_settime(struct ptp_clock_info *ptp,
473			   const struct timespec64 *ts)
474{
475	struct fec_enet_private *fep =
476	    container_of(ptp, struct fec_enet_private, ptp_caps);
477
478	u64 ns;
479	unsigned long flags;
480	u32 counter;
481
482	mutex_lock(&fep->ptp_clk_mutex);
483	/* Check the ptp clock */
484	if (!fep->ptp_clk_on) {
485		mutex_unlock(&fep->ptp_clk_mutex);
486		return -EINVAL;
487	}
488
489	ns = timespec64_to_ns(ts);
490	/* Get the timer value based on timestamp.
491	 * Update the counter with the masked value.
492	 */
493	counter = ns & fep->cc.mask;
494
495	spin_lock_irqsave(&fep->tmreg_lock, flags);
496	writel(counter, fep->hwp + FEC_ATIME);
497	timecounter_init(&fep->tc, &fep->cc, ns);
498	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
499	mutex_unlock(&fep->ptp_clk_mutex);
500	return 0;
501}
502
503static int fec_ptp_pps_disable(struct fec_enet_private *fep, uint channel)
504{
505	unsigned long flags;
506
507	hrtimer_cancel(&fep->perout_timer);
508
509	spin_lock_irqsave(&fep->tmreg_lock, flags);
510	fep->perout_enable = false;
511	writel(0, fep->hwp + FEC_TCSR(channel));
512	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
513
514	return 0;
515}
516
517/**
518 * fec_ptp_enable
519 * @ptp: the ptp clock structure
520 * @rq: the requested feature to change
521 * @on: whether to enable or disable the feature
522 *
523 */
524static int fec_ptp_enable(struct ptp_clock_info *ptp,
525			  struct ptp_clock_request *rq, int on)
526{
527	struct fec_enet_private *fep =
528	    container_of(ptp, struct fec_enet_private, ptp_caps);
529	ktime_t timeout;
530	struct timespec64 start_time, period;
531	u64 curr_time, delta, period_ns;
532	unsigned long flags;
533	int ret = 0;
534
535	if (rq->type == PTP_CLK_REQ_PPS) {
536		fep->reload_period = PPS_OUPUT_RELOAD_PERIOD;
537
538		ret = fec_ptp_enable_pps(fep, on);
539
540		return ret;
541	} else if (rq->type == PTP_CLK_REQ_PEROUT) {
542		u32 reload_period;
543
544		/* Reject requests with unsupported flags */
545		if (rq->perout.flags)
546			return -EOPNOTSUPP;
547
548		period.tv_sec = rq->perout.period.sec;
549		period.tv_nsec = rq->perout.period.nsec;
550		period_ns = timespec64_to_ns(&period);
551
552		/* FEC PTP timer only has 31 bits, so if the period exceed
553		 * 4s is not supported.
554		 */
555		if (period_ns > FEC_PTP_MAX_NSEC_PERIOD) {
556			dev_err(&fep->pdev->dev, "The period must equal to or less than 4s!\n");
557			return -EOPNOTSUPP;
558		}
559
560		reload_period = div_u64(period_ns, 2);
561		if (on && reload_period) {
562			u64 perout_stime;
563
564			/* Convert 1588 timestamp to ns*/
565			start_time.tv_sec = rq->perout.start.sec;
566			start_time.tv_nsec = rq->perout.start.nsec;
567			perout_stime = timespec64_to_ns(&start_time);
568
569			mutex_lock(&fep->ptp_clk_mutex);
570			if (!fep->ptp_clk_on) {
571				dev_err(&fep->pdev->dev, "Error: PTP clock is closed!\n");
572				mutex_unlock(&fep->ptp_clk_mutex);
573				return -EOPNOTSUPP;
574			}
575			spin_lock_irqsave(&fep->tmreg_lock, flags);
576
577			if (fep->pps_enable) {
578				dev_err(&fep->pdev->dev, "PPS is running");
579				ret = -EBUSY;
580				goto unlock;
581			}
582
583			if (fep->perout_enable) {
584				dev_err(&fep->pdev->dev,
585					"PEROUT has been enabled\n");
586				ret = -EBUSY;
587				goto unlock;
588			}
589
590			/* Read current timestamp */
591			curr_time = timecounter_read(&fep->tc);
592			if (perout_stime <= curr_time) {
593				dev_err(&fep->pdev->dev,
594					"Start time must be greater than current time\n");
595				ret = -EINVAL;
596				goto unlock;
597			}
598
599			/* Calculate time difference */
600			delta = perout_stime - curr_time;
601			fep->reload_period = reload_period;
602			fep->perout_stime = perout_stime;
603			fep->perout_enable = true;
604
605unlock:
606			spin_unlock_irqrestore(&fep->tmreg_lock, flags);
607			mutex_unlock(&fep->ptp_clk_mutex);
608
609			if (ret)
610				return ret;
611
612			/* Because the timer counter of FEC only has 31-bits, correspondingly,
613			 * the time comparison register FEC_TCCR also only low 31 bits can be
614			 * set. If the start time of pps signal exceeds current time more than
615			 * 0x80000000 ns, a software timer is used and the timer expires about
616			 * 1 second before the start time to be able to set FEC_TCCR.
617			 */
618			if (delta > FEC_PTP_MAX_NSEC_COUNTER) {
619				timeout = ns_to_ktime(delta - NSEC_PER_SEC);
620				hrtimer_start(&fep->perout_timer, timeout, HRTIMER_MODE_REL);
621			} else {
622				return fec_ptp_pps_perout(fep);
623			}
624		} else {
625			fec_ptp_pps_disable(fep, fep->pps_channel);
626		}
627
628		return 0;
629	} else {
630		return -EOPNOTSUPP;
631	}
632}
633
634int fec_ptp_set(struct net_device *ndev, struct kernel_hwtstamp_config *config,
635		struct netlink_ext_ack *extack)
636{
637	struct fec_enet_private *fep = netdev_priv(ndev);
638
639	switch (config->tx_type) {
640	case HWTSTAMP_TX_OFF:
641		fep->hwts_tx_en = 0;
642		break;
643	case HWTSTAMP_TX_ON:
644		fep->hwts_tx_en = 1;
645		break;
646	default:
647		return -ERANGE;
648	}
649
650	switch (config->rx_filter) {
651	case HWTSTAMP_FILTER_NONE:
652		fep->hwts_rx_en = 0;
653		break;
654
655	default:
656		fep->hwts_rx_en = 1;
657		config->rx_filter = HWTSTAMP_FILTER_ALL;
658		break;
659	}
660
661	return 0;
662}
663
664void fec_ptp_get(struct net_device *ndev, struct kernel_hwtstamp_config *config)
665{
666	struct fec_enet_private *fep = netdev_priv(ndev);
667
668	config->flags = 0;
669	config->tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
670	config->rx_filter = (fep->hwts_rx_en ?
671			     HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
672}
673
674/*
675 * fec_time_keep - call timecounter_read every second to avoid timer overrun
676 *                 because ENET just support 32bit counter, will timeout in 4s
677 */
678static void fec_time_keep(struct work_struct *work)
679{
680	struct delayed_work *dwork = to_delayed_work(work);
681	struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep);
682	unsigned long flags;
683
684	mutex_lock(&fep->ptp_clk_mutex);
685	if (fep->ptp_clk_on) {
686		spin_lock_irqsave(&fep->tmreg_lock, flags);
687		timecounter_read(&fep->tc);
688		spin_unlock_irqrestore(&fep->tmreg_lock, flags);
689	}
690	mutex_unlock(&fep->ptp_clk_mutex);
691
692	schedule_delayed_work(&fep->time_keep, HZ);
693}
694
695/* This function checks the pps event and reloads the timer compare counter. */
696static irqreturn_t fec_pps_interrupt(int irq, void *dev_id)
697{
698	struct net_device *ndev = dev_id;
699	struct fec_enet_private *fep = netdev_priv(ndev);
700	u32 val;
701	u8 channel = fep->pps_channel;
702	struct ptp_clock_event event;
703
704	val = readl(fep->hwp + FEC_TCSR(channel));
705	if (val & FEC_T_TF_MASK) {
706		/* Write the next next compare(not the next according the spec)
707		 * value to the register
708		 */
709		writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
710		do {
711			writel(val, fep->hwp + FEC_TCSR(channel));
712		} while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK);
713
714		/* Update the counter; */
715		fep->next_counter = (fep->next_counter + fep->reload_period) &
716				fep->cc.mask;
717
718		if (fep->pps_enable) {
719			event.type = PTP_CLOCK_PPS;
720			ptp_clock_event(fep->ptp_clock, &event);
721		}
722
723		return IRQ_HANDLED;
724	}
725
726	return IRQ_NONE;
727}
728
729/**
730 * fec_ptp_init
731 * @pdev: The FEC network adapter
732 * @irq_idx: the interrupt index
733 *
734 * This function performs the required steps for enabling ptp
735 * support. If ptp support has already been loaded it simply calls the
736 * cyclecounter init routine and exits.
737 */
738
739void fec_ptp_init(struct platform_device *pdev, int irq_idx)
740{
741	struct net_device *ndev = platform_get_drvdata(pdev);
742	struct fec_enet_private *fep = netdev_priv(ndev);
743	struct device_node *np = fep->pdev->dev.of_node;
744	int irq;
745	int ret;
746
747	fep->ptp_caps.owner = THIS_MODULE;
748	strscpy(fep->ptp_caps.name, "fec ptp", sizeof(fep->ptp_caps.name));
749
750	fep->pps_channel = DEFAULT_PPS_CHANNEL;
751	of_property_read_u32(np, "fsl,pps-channel", &fep->pps_channel);
752
753	fep->ptp_caps.max_adj = 250000000;
754	fep->ptp_caps.n_alarm = 0;
755	fep->ptp_caps.n_ext_ts = 0;
756	fep->ptp_caps.n_per_out = 1;
757	fep->ptp_caps.n_pins = 0;
758	fep->ptp_caps.pps = 1;
759	fep->ptp_caps.adjfine = fec_ptp_adjfine;
760	fep->ptp_caps.adjtime = fec_ptp_adjtime;
761	fep->ptp_caps.gettime64 = fec_ptp_gettime;
762	fep->ptp_caps.settime64 = fec_ptp_settime;
763	fep->ptp_caps.enable = fec_ptp_enable;
764
765	fep->cycle_speed = clk_get_rate(fep->clk_ptp);
766	if (!fep->cycle_speed) {
767		fep->cycle_speed = NSEC_PER_SEC;
768		dev_err(&fep->pdev->dev, "clk_ptp clock rate is zero\n");
769	}
770	fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed;
771
772	spin_lock_init(&fep->tmreg_lock);
773
774	fec_ptp_start_cyclecounter(ndev);
775
776	INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep);
777
778	hrtimer_setup(&fep->perout_timer, fec_ptp_pps_perout_handler, CLOCK_REALTIME,
779		      HRTIMER_MODE_REL);
780
781	irq = platform_get_irq_byname_optional(pdev, "pps");
782	if (irq < 0)
783		irq = platform_get_irq_optional(pdev, irq_idx);
784	/* Failure to get an irq is not fatal,
785	 * only the PTP_CLOCK_PPS clock events should stop
786	 */
787	if (irq >= 0) {
788		ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt,
789				       0, pdev->name, ndev);
790		if (ret < 0)
791			dev_warn(&pdev->dev, "request for pps irq failed(%d)\n",
792				 ret);
793	}
794
795	fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev);
796	if (IS_ERR(fep->ptp_clock)) {
797		fep->ptp_clock = NULL;
798		dev_err(&pdev->dev, "ptp_clock_register failed\n");
799	}
800
801	schedule_delayed_work(&fep->time_keep, HZ);
802}
803
804void fec_ptp_save_state(struct fec_enet_private *fep)
805{
806	unsigned long flags;
807	u32 atime_inc_corr;
808
809	spin_lock_irqsave(&fep->tmreg_lock, flags);
810
811	fep->ptp_saved_state.pps_enable = fep->pps_enable;
812
813	fep->ptp_saved_state.ns_phc = timecounter_read(&fep->tc);
814	fep->ptp_saved_state.ns_sys = ktime_get_ns();
815
816	fep->ptp_saved_state.at_corr = readl(fep->hwp + FEC_ATIME_CORR);
817	atime_inc_corr = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_CORR_MASK;
818	fep->ptp_saved_state.at_inc_corr = (u8)(atime_inc_corr >> FEC_T_INC_CORR_OFFSET);
819
820	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
821}
822
823/* Restore PTP functionality after a reset */
824void fec_ptp_restore_state(struct fec_enet_private *fep)
825{
826	u32 atime_inc = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
827	unsigned long flags;
828	u32 counter;
829	u64 ns;
830
831	spin_lock_irqsave(&fep->tmreg_lock, flags);
832
833	/* Reset turned it off, so adjust our status flag */
834	fep->pps_enable = 0;
835
836	writel(fep->ptp_saved_state.at_corr, fep->hwp + FEC_ATIME_CORR);
837	atime_inc |= ((u32)fep->ptp_saved_state.at_inc_corr) << FEC_T_INC_CORR_OFFSET;
838	writel(atime_inc, fep->hwp + FEC_ATIME_INC);
839
840	ns = ktime_get_ns() - fep->ptp_saved_state.ns_sys + fep->ptp_saved_state.ns_phc;
841	counter = ns & fep->cc.mask;
842	writel(counter, fep->hwp + FEC_ATIME);
843	timecounter_init(&fep->tc, &fep->cc, ns);
844
845	spin_unlock_irqrestore(&fep->tmreg_lock, flags);
846
847	/* Restart PPS if needed */
848	if (fep->ptp_saved_state.pps_enable) {
849		/* Re-enable PPS */
850		fec_ptp_enable_pps(fep, 1);
851	}
852}
853
854void fec_ptp_stop(struct platform_device *pdev)
855{
856	struct net_device *ndev = platform_get_drvdata(pdev);
857	struct fec_enet_private *fep = netdev_priv(ndev);
858
859	if (fep->pps_enable)
860		fec_ptp_enable_pps(fep, 0);
861
862	cancel_delayed_work_sync(&fep->time_keep);
863	hrtimer_cancel(&fep->perout_timer);
864	if (fep->ptp_clock)
865		ptp_clock_unregister(fep->ptp_clock);
866}