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fec_main.c
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linux-6.19.14/drivers/net/ethernet/freescale/fec_main.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25#include <linux/bitops.h> 26#include <linux/bpf.h> 27#include <linux/bpf_trace.h> 28#include <linux/cacheflush.h> 29#include <linux/clk.h> 30#include <linux/crc32.h> 31#include <linux/delay.h> 32#include <linux/errno.h> 33#include <linux/etherdevice.h> 34#include <linux/fec.h> 35#include <linux/filter.h> 36#include <linux/gpio/consumer.h> 37#include <linux/icmp.h> 38#include <linux/if_vlan.h> 39#include <linux/in.h> 40#include <linux/interrupt.h> 41#include <linux/io.h> 42#include <linux/ioport.h> 43#include <linux/ip.h> 44#include <linux/irq.h> 45#include <linux/kernel.h> 46#include <linux/mdio.h> 47#include <linux/mfd/syscon.h> 48#include <linux/module.h> 49#include <linux/netdevice.h> 50#include <linux/of.h> 51#include <linux/of_mdio.h> 52#include <linux/of_net.h> 53#include <linux/phy.h> 54#include <linux/pinctrl/consumer.h> 55#include <linux/phy_fixed.h> 56#include <linux/platform_device.h> 57#include <linux/pm_runtime.h> 58#include <linux/prefetch.h> 59#include <linux/property.h> 60#include <linux/ptrace.h> 61#include <linux/regmap.h> 62#include <linux/regulator/consumer.h> 63#include <linux/skbuff.h> 64#include <linux/slab.h> 65#include <linux/spinlock.h> 66#include <linux/string.h> 67#include <linux/tcp.h> 68#include <linux/udp.h> 69#include <linux/workqueue.h> 70#include <net/ip.h> 71#include <net/page_pool/helpers.h> 72#include <net/selftests.h> 73#include <net/tso.h> 74#include <soc/imx/cpuidle.h> 75 76#include "fec.h" 77 78static void set_multicast_list(struct net_device *ndev); 79static void fec_enet_itr_coal_set(struct net_device *ndev); 80static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 81 int cpu, struct xdp_buff *xdp, 82 u32 dma_sync_len); 83 84#define DRIVER_NAME "fec" 85 86static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 87 88#define FEC_ENET_RSEM_V 0x84 89#define FEC_ENET_RSFL_V 16 90#define FEC_ENET_RAEM_V 0x8 91#define FEC_ENET_RAFL_V 0x8 92#define FEC_ENET_OPD_V 0xFFF0 93#define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 94 95#define FEC_ENET_XDP_PASS 0 96#define FEC_ENET_XDP_CONSUMED BIT(0) 97#define FEC_ENET_XDP_TX BIT(1) 98#define FEC_ENET_XDP_REDIR BIT(2) 99 100struct fec_devinfo { 101 u32 quirks; 102}; 103 104static const struct fec_devinfo fec_imx25_info = { 105 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45, 107}; 108 109static const struct fec_devinfo fec_imx27_info = { 110 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG | 111 FEC_QUIRK_HAS_MDIO_C45, 112}; 113 114static const struct fec_devinfo fec_imx28_info = { 115 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 116 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 117 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII | 118 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45, 119}; 120 121static const struct fec_devinfo fec_imx6q_info = { 122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 125 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII | 126 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45, 127}; 128 129static const struct fec_devinfo fec_mvf600_info = { 130 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC | 131 FEC_QUIRK_HAS_MDIO_C45, 132}; 133 134static const struct fec_devinfo fec_imx6sx_info = { 135 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 136 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 137 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 138 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 139 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 140 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 141 FEC_QUIRK_HAS_MDIO_C45, 142}; 143 144static const struct fec_devinfo fec_imx6ul_info = { 145 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 146 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 147 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 148 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 149 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII | 150 FEC_QUIRK_HAS_MDIO_C45, 151}; 152 153static const struct fec_devinfo fec_imx8mq_info = { 154 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 155 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 156 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 157 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 158 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 159 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 160 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 | 161 FEC_QUIRK_HAS_MDIO_C45, 162}; 163 164static const struct fec_devinfo fec_imx8qm_info = { 165 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 166 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 167 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 168 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 169 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 170 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | 171 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45 | 172 FEC_QUIRK_JUMBO_FRAME, 173}; 174 175static const struct fec_devinfo fec_s32v234_info = { 176 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 177 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 178 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 179 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 180 FEC_QUIRK_HAS_MDIO_C45, 181}; 182 183static struct platform_device_id fec_devtype[] = { 184 { 185 /* keep it for coldfire */ 186 .name = DRIVER_NAME, 187 .driver_data = 0, 188 }, { 189 /* sentinel */ 190 } 191}; 192MODULE_DEVICE_TABLE(platform, fec_devtype); 193 194static const struct of_device_id fec_dt_ids[] = { 195 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, }, 196 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, }, 197 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, }, 198 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, }, 199 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, }, 200 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6sx_info, }, 201 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, }, 202 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, }, 203 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, }, 204 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, }, 205 { /* sentinel */ } 206}; 207MODULE_DEVICE_TABLE(of, fec_dt_ids); 208 209static unsigned char macaddr[ETH_ALEN]; 210module_param_array(macaddr, byte, NULL, 0); 211MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 212 213#if defined(CONFIG_M5272) 214/* 215 * Some hardware gets it MAC address out of local flash memory. 216 * if this is non-zero then assume it is the address to get MAC from. 217 */ 218#if defined(CONFIG_NETtel) 219#define FEC_FLASHMAC 0xf0006006 220#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 221#define FEC_FLASHMAC 0xf0006000 222#elif defined(CONFIG_CANCam) 223#define FEC_FLASHMAC 0xf0020000 224#elif defined (CONFIG_M5272C3) 225#define FEC_FLASHMAC (0xffe04000 + 4) 226#elif defined(CONFIG_MOD5272) 227#define FEC_FLASHMAC 0xffc0406b 228#else 229#define FEC_FLASHMAC 0 230#endif 231#endif /* CONFIG_M5272 */ 232 233/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 234 * 235 * 2048 byte skbufs are allocated. However, alignment requirements 236 * varies between FEC variants. Worst case is 64, so round down by 64. 237 */ 238#define MAX_JUMBO_BUF_SIZE (round_down(16384 - FEC_DRV_RESERVE_SPACE - 64, 64)) 239#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 240#define PKT_MINBUF_SIZE 64 241 242/* FEC receive acceleration */ 243#define FEC_RACC_IPDIS BIT(1) 244#define FEC_RACC_PRODIS BIT(2) 245#define FEC_RACC_SHIFT16 BIT(7) 246#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 247 248/* MIB Control Register */ 249#define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 250 251/* 252 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 253 * size bits. Other FEC hardware does not, so we need to take that into 254 * account when setting it. 255 */ 256#ifndef CONFIG_M5272 257#define OPT_ARCH_HAS_MAX_FL 1 258#else 259#define OPT_ARCH_HAS_MAX_FL 0 260#endif 261 262/* FEC MII MMFR bits definition */ 263#define FEC_MMFR_ST (1 << 30) 264#define FEC_MMFR_ST_C45 (0) 265#define FEC_MMFR_OP_READ (2 << 28) 266#define FEC_MMFR_OP_READ_C45 (3 << 28) 267#define FEC_MMFR_OP_WRITE (1 << 28) 268#define FEC_MMFR_OP_ADDR_WRITE (0) 269#define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 270#define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 271#define FEC_MMFR_TA (2 << 16) 272#define FEC_MMFR_DATA(v) (v & 0xffff) 273/* FEC ECR bits definition */ 274#define FEC_ECR_RESET BIT(0) 275#define FEC_ECR_ETHEREN BIT(1) 276#define FEC_ECR_MAGICEN BIT(2) 277#define FEC_ECR_SLEEP BIT(3) 278#define FEC_ECR_EN1588 BIT(4) 279#define FEC_ECR_SPEED BIT(5) 280#define FEC_ECR_BYTESWP BIT(8) 281/* FEC RCR bits definition */ 282#define FEC_RCR_LOOP BIT(0) 283#define FEC_RCR_DRT BIT(1) 284#define FEC_RCR_MII BIT(2) 285#define FEC_RCR_PROMISC BIT(3) 286#define FEC_RCR_BC_REJ BIT(4) 287#define FEC_RCR_FLOWCTL BIT(5) 288#define FEC_RCR_RGMII BIT(6) 289#define FEC_RCR_RMII BIT(8) 290#define FEC_RCR_10BASET BIT(9) 291#define FEC_RCR_NLC BIT(30) 292/* TX WMARK bits */ 293#define FEC_TXWMRK_STRFWD BIT(8) 294 295#define FEC_MII_TIMEOUT 30000 /* us */ 296 297/* Transmitter timeout */ 298#define TX_TIMEOUT (2 * HZ) 299 300#define FEC_PAUSE_FLAG_AUTONEG 0x1 301#define FEC_PAUSE_FLAG_ENABLE 0x2 302#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 303#define FEC_WOL_FLAG_ENABLE (0x1 << 1) 304#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 305 306/* Max number of allowed TCP segments for software TSO */ 307#define FEC_MAX_TSO_SEGS 100 308#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 309 310#define IS_TSO_HEADER(txq, addr) \ 311 ((addr >= txq->tso_hdrs_dma) && \ 312 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 313 314static int mii_cnt; 315 316static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 317 struct bufdesc_prop *bd) 318{ 319 return (bdp >= bd->last) ? bd->base 320 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 321} 322 323static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 324 struct bufdesc_prop *bd) 325{ 326 return (bdp <= bd->base) ? bd->last 327 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 328} 329 330static int fec_enet_get_bd_index(struct bufdesc *bdp, 331 struct bufdesc_prop *bd) 332{ 333 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 334} 335 336static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 337{ 338 int entries; 339 340 entries = (((const char *)txq->dirty_tx - 341 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 342 343 return entries >= 0 ? entries : entries + txq->bd.ring_size; 344} 345 346static void swap_buffer(void *bufaddr, int len) 347{ 348 int i; 349 unsigned int *buf = bufaddr; 350 351 for (i = 0; i < len; i += 4, buf++) 352 swab32s(buf); 353} 354 355static void fec_dump(struct net_device *ndev) 356{ 357 struct fec_enet_private *fep = netdev_priv(ndev); 358 struct bufdesc *bdp; 359 struct fec_enet_priv_tx_q *txq; 360 int index = 0; 361 362 netdev_info(ndev, "TX ring dump\n"); 363 pr_info("Nr SC addr len SKB\n"); 364 365 txq = fep->tx_queue[0]; 366 bdp = txq->bd.base; 367 368 do { 369 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 370 index, 371 bdp == txq->bd.cur ? 'S' : ' ', 372 bdp == txq->dirty_tx ? 'H' : ' ', 373 fec16_to_cpu(bdp->cbd_sc), 374 fec32_to_cpu(bdp->cbd_bufaddr), 375 fec16_to_cpu(bdp->cbd_datlen), 376 txq->tx_buf[index].buf_p); 377 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 378 index++; 379 } while (bdp != txq->bd.base); 380} 381 382/* 383 * Coldfire does not support DMA coherent allocations, and has historically used 384 * a band-aid with a manual flush in fec_enet_rx_queue. 385 */ 386#if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 387static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 388 gfp_t gfp) 389{ 390 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp); 391} 392 393static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 394 dma_addr_t handle) 395{ 396 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL); 397} 398#else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 399static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, 400 gfp_t gfp) 401{ 402 return dma_alloc_coherent(dev, size, handle, gfp); 403} 404 405static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr, 406 dma_addr_t handle) 407{ 408 dma_free_coherent(dev, size, cpu_addr, handle); 409} 410#endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */ 411 412struct fec_dma_devres { 413 size_t size; 414 void *vaddr; 415 dma_addr_t dma_handle; 416}; 417 418static void fec_dmam_release(struct device *dev, void *res) 419{ 420 struct fec_dma_devres *this = res; 421 422 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle); 423} 424 425static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle, 426 gfp_t gfp) 427{ 428 struct fec_dma_devres *dr; 429 void *vaddr; 430 431 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp); 432 if (!dr) 433 return NULL; 434 vaddr = fec_dma_alloc(dev, size, handle, gfp); 435 if (!vaddr) { 436 devres_free(dr); 437 return NULL; 438 } 439 dr->vaddr = vaddr; 440 dr->dma_handle = *handle; 441 dr->size = size; 442 devres_add(dev, dr); 443 return vaddr; 444} 445 446static inline bool is_ipv4_pkt(struct sk_buff *skb) 447{ 448 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 449} 450 451static int 452fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 453{ 454 /* Only run for packets requiring a checksum. */ 455 if (skb->ip_summed != CHECKSUM_PARTIAL) 456 return 0; 457 458 if (unlikely(skb_cow_head(skb, 0))) 459 return -1; 460 461 if (is_ipv4_pkt(skb)) 462 ip_hdr(skb)->check = 0; 463 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 464 465 return 0; 466} 467 468static int 469fec_enet_create_page_pool(struct fec_enet_private *fep, 470 struct fec_enet_priv_rx_q *rxq, int size) 471{ 472 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 473 struct page_pool_params pp_params = { 474 .order = fep->pagepool_order, 475 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 476 .pool_size = size, 477 .nid = dev_to_node(&fep->pdev->dev), 478 .dev = &fep->pdev->dev, 479 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 480 .offset = FEC_ENET_XDP_HEADROOM, 481 .max_len = fep->rx_frame_size, 482 }; 483 int err; 484 485 rxq->page_pool = page_pool_create(&pp_params); 486 if (IS_ERR(rxq->page_pool)) { 487 err = PTR_ERR(rxq->page_pool); 488 rxq->page_pool = NULL; 489 return err; 490 } 491 492 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0); 493 if (err < 0) 494 goto err_free_pp; 495 496 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 497 rxq->page_pool); 498 if (err) 499 goto err_unregister_rxq; 500 501 return 0; 502 503err_unregister_rxq: 504 xdp_rxq_info_unreg(&rxq->xdp_rxq); 505err_free_pp: 506 page_pool_destroy(rxq->page_pool); 507 rxq->page_pool = NULL; 508 return err; 509} 510 511static struct bufdesc * 512fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 513 struct sk_buff *skb, 514 struct net_device *ndev) 515{ 516 struct fec_enet_private *fep = netdev_priv(ndev); 517 struct bufdesc *bdp = txq->bd.cur; 518 struct bufdesc_ex *ebdp; 519 int nr_frags = skb_shinfo(skb)->nr_frags; 520 int frag, frag_len; 521 unsigned short status; 522 unsigned int estatus = 0; 523 skb_frag_t *this_frag; 524 unsigned int index; 525 void *bufaddr; 526 dma_addr_t addr; 527 int i; 528 529 for (frag = 0; frag < nr_frags; frag++) { 530 this_frag = &skb_shinfo(skb)->frags[frag]; 531 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 532 ebdp = (struct bufdesc_ex *)bdp; 533 534 status = fec16_to_cpu(bdp->cbd_sc); 535 status &= ~BD_ENET_TX_STATS; 536 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 537 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 538 539 /* Handle the last BD specially */ 540 if (frag == nr_frags - 1) { 541 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 542 if (fep->bufdesc_ex) { 543 estatus |= BD_ENET_TX_INT; 544 if (unlikely(skb_shinfo(skb)->tx_flags & 545 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 546 estatus |= BD_ENET_TX_TS; 547 } 548 } 549 550 if (fep->bufdesc_ex) { 551 if (fep->quirks & FEC_QUIRK_HAS_AVB) 552 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 553 if (skb->ip_summed == CHECKSUM_PARTIAL) 554 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 555 556 ebdp->cbd_bdu = 0; 557 ebdp->cbd_esc = cpu_to_fec32(estatus); 558 } 559 560 bufaddr = skb_frag_address(this_frag); 561 562 index = fec_enet_get_bd_index(bdp, &txq->bd); 563 if (((unsigned long) bufaddr) & fep->tx_align || 564 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 565 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 566 bufaddr = txq->tx_bounce[index]; 567 568 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 569 swap_buffer(bufaddr, frag_len); 570 } 571 572 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 573 DMA_TO_DEVICE); 574 if (dma_mapping_error(&fep->pdev->dev, addr)) { 575 if (net_ratelimit()) 576 netdev_err(ndev, "Tx DMA memory map failed\n"); 577 goto dma_mapping_error; 578 } 579 580 bdp->cbd_bufaddr = cpu_to_fec32(addr); 581 bdp->cbd_datlen = cpu_to_fec16(frag_len); 582 /* Make sure the updates to rest of the descriptor are 583 * performed before transferring ownership. 584 */ 585 wmb(); 586 bdp->cbd_sc = cpu_to_fec16(status); 587 } 588 589 return bdp; 590dma_mapping_error: 591 bdp = txq->bd.cur; 592 for (i = 0; i < frag; i++) { 593 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 594 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 595 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 596 } 597 return ERR_PTR(-ENOMEM); 598} 599 600static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 601 struct sk_buff *skb, struct net_device *ndev) 602{ 603 struct fec_enet_private *fep = netdev_priv(ndev); 604 int nr_frags = skb_shinfo(skb)->nr_frags; 605 struct bufdesc *bdp, *last_bdp; 606 void *bufaddr; 607 dma_addr_t addr; 608 unsigned short status; 609 unsigned short buflen; 610 unsigned int estatus = 0; 611 unsigned int index; 612 int entries_free; 613 614 entries_free = fec_enet_get_free_txdesc_num(txq); 615 if (entries_free < MAX_SKB_FRAGS + 1) { 616 dev_kfree_skb_any(skb); 617 if (net_ratelimit()) 618 netdev_err(ndev, "NOT enough BD for SG!\n"); 619 return NETDEV_TX_OK; 620 } 621 622 /* Protocol checksum off-load for TCP and UDP. */ 623 if (fec_enet_clear_csum(skb, ndev)) { 624 dev_kfree_skb_any(skb); 625 return NETDEV_TX_OK; 626 } 627 628 /* Fill in a Tx ring entry */ 629 bdp = txq->bd.cur; 630 last_bdp = bdp; 631 status = fec16_to_cpu(bdp->cbd_sc); 632 status &= ~BD_ENET_TX_STATS; 633 634 /* Set buffer length and buffer pointer */ 635 bufaddr = skb->data; 636 buflen = skb_headlen(skb); 637 638 index = fec_enet_get_bd_index(bdp, &txq->bd); 639 if (((unsigned long) bufaddr) & fep->tx_align || 640 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 641 memcpy(txq->tx_bounce[index], skb->data, buflen); 642 bufaddr = txq->tx_bounce[index]; 643 644 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 645 swap_buffer(bufaddr, buflen); 646 } 647 648 /* Push the data cache so the CPM does not get stale memory data. */ 649 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 650 if (dma_mapping_error(&fep->pdev->dev, addr)) { 651 dev_kfree_skb_any(skb); 652 if (net_ratelimit()) 653 netdev_err(ndev, "Tx DMA memory map failed\n"); 654 return NETDEV_TX_OK; 655 } 656 657 if (nr_frags) { 658 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 659 if (IS_ERR(last_bdp)) { 660 dma_unmap_single(&fep->pdev->dev, addr, 661 buflen, DMA_TO_DEVICE); 662 dev_kfree_skb_any(skb); 663 return NETDEV_TX_OK; 664 } 665 } else { 666 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 667 if (fep->bufdesc_ex) { 668 estatus = BD_ENET_TX_INT; 669 if (unlikely(skb_shinfo(skb)->tx_flags & 670 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 671 estatus |= BD_ENET_TX_TS; 672 } 673 } 674 bdp->cbd_bufaddr = cpu_to_fec32(addr); 675 bdp->cbd_datlen = cpu_to_fec16(buflen); 676 677 if (fep->bufdesc_ex) { 678 679 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 680 681 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 682 fep->hwts_tx_en)) 683 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 684 685 if (fep->quirks & FEC_QUIRK_HAS_AVB) 686 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 687 688 if (skb->ip_summed == CHECKSUM_PARTIAL) 689 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 690 691 ebdp->cbd_bdu = 0; 692 ebdp->cbd_esc = cpu_to_fec32(estatus); 693 } 694 695 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 696 /* Save skb pointer */ 697 txq->tx_buf[index].buf_p = skb; 698 699 /* Make sure the updates to rest of the descriptor are performed before 700 * transferring ownership. 701 */ 702 wmb(); 703 704 /* Send it on its way. Tell FEC it's ready, interrupt when done, 705 * it's the last BD of the frame, and to put the CRC on the end. 706 */ 707 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 708 bdp->cbd_sc = cpu_to_fec16(status); 709 710 /* If this was the last BD in the ring, start at the beginning again. */ 711 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 712 713 skb_tx_timestamp(skb); 714 715 /* Make sure the update to bdp is performed before txq->bd.cur. */ 716 wmb(); 717 txq->bd.cur = bdp; 718 719 /* Trigger transmission start */ 720 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 721 !readl(txq->bd.reg_desc_active) || 722 !readl(txq->bd.reg_desc_active) || 723 !readl(txq->bd.reg_desc_active) || 724 !readl(txq->bd.reg_desc_active)) 725 writel(0, txq->bd.reg_desc_active); 726 727 return 0; 728} 729 730static int 731fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 732 struct net_device *ndev, 733 struct bufdesc *bdp, int index, char *data, 734 int size, bool last_tcp, bool is_last) 735{ 736 struct fec_enet_private *fep = netdev_priv(ndev); 737 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 738 unsigned short status; 739 unsigned int estatus = 0; 740 dma_addr_t addr; 741 742 status = fec16_to_cpu(bdp->cbd_sc); 743 status &= ~BD_ENET_TX_STATS; 744 745 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 746 747 if (((unsigned long) data) & fep->tx_align || 748 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 749 memcpy(txq->tx_bounce[index], data, size); 750 data = txq->tx_bounce[index]; 751 752 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 753 swap_buffer(data, size); 754 } 755 756 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 757 if (dma_mapping_error(&fep->pdev->dev, addr)) { 758 dev_kfree_skb_any(skb); 759 if (net_ratelimit()) 760 netdev_err(ndev, "Tx DMA memory map failed\n"); 761 return NETDEV_TX_OK; 762 } 763 764 bdp->cbd_datlen = cpu_to_fec16(size); 765 bdp->cbd_bufaddr = cpu_to_fec32(addr); 766 767 if (fep->bufdesc_ex) { 768 if (fep->quirks & FEC_QUIRK_HAS_AVB) 769 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 770 if (skb->ip_summed == CHECKSUM_PARTIAL) 771 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 772 ebdp->cbd_bdu = 0; 773 ebdp->cbd_esc = cpu_to_fec32(estatus); 774 } 775 776 /* Handle the last BD specially */ 777 if (last_tcp) 778 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 779 if (is_last) { 780 status |= BD_ENET_TX_INTR; 781 if (fep->bufdesc_ex) 782 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 783 } 784 785 bdp->cbd_sc = cpu_to_fec16(status); 786 787 return 0; 788} 789 790static int 791fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 792 struct sk_buff *skb, struct net_device *ndev, 793 struct bufdesc *bdp, int index) 794{ 795 struct fec_enet_private *fep = netdev_priv(ndev); 796 int hdr_len = skb_tcp_all_headers(skb); 797 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 798 void *bufaddr; 799 unsigned long dmabuf; 800 unsigned short status; 801 unsigned int estatus = 0; 802 803 status = fec16_to_cpu(bdp->cbd_sc); 804 status &= ~BD_ENET_TX_STATS; 805 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 806 807 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 808 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 809 if (((unsigned long)bufaddr) & fep->tx_align || 810 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 811 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 812 bufaddr = txq->tx_bounce[index]; 813 814 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 815 swap_buffer(bufaddr, hdr_len); 816 817 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 818 hdr_len, DMA_TO_DEVICE); 819 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 820 dev_kfree_skb_any(skb); 821 if (net_ratelimit()) 822 netdev_err(ndev, "Tx DMA memory map failed\n"); 823 return NETDEV_TX_OK; 824 } 825 } 826 827 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 828 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 829 830 if (fep->bufdesc_ex) { 831 if (fep->quirks & FEC_QUIRK_HAS_AVB) 832 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 833 if (skb->ip_summed == CHECKSUM_PARTIAL) 834 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 835 ebdp->cbd_bdu = 0; 836 ebdp->cbd_esc = cpu_to_fec32(estatus); 837 } 838 839 bdp->cbd_sc = cpu_to_fec16(status); 840 841 return 0; 842} 843 844static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 845 struct sk_buff *skb, 846 struct net_device *ndev) 847{ 848 struct fec_enet_private *fep = netdev_priv(ndev); 849 int hdr_len, total_len, data_left; 850 struct bufdesc *bdp = txq->bd.cur; 851 struct bufdesc *tmp_bdp; 852 struct bufdesc_ex *ebdp; 853 struct tso_t tso; 854 unsigned int index = 0; 855 int ret; 856 857 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 858 dev_kfree_skb_any(skb); 859 if (net_ratelimit()) 860 netdev_err(ndev, "NOT enough BD for TSO!\n"); 861 return NETDEV_TX_OK; 862 } 863 864 /* Protocol checksum off-load for TCP and UDP. */ 865 if (fec_enet_clear_csum(skb, ndev)) { 866 dev_kfree_skb_any(skb); 867 return NETDEV_TX_OK; 868 } 869 870 /* Initialize the TSO handler, and prepare the first payload */ 871 hdr_len = tso_start(skb, &tso); 872 873 total_len = skb->len - hdr_len; 874 while (total_len > 0) { 875 char *hdr; 876 877 index = fec_enet_get_bd_index(bdp, &txq->bd); 878 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 879 total_len -= data_left; 880 881 /* prepare packet headers: MAC + IP + TCP */ 882 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 883 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 884 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 885 if (ret) 886 goto err_release; 887 888 while (data_left > 0) { 889 int size; 890 891 size = min_t(int, tso.size, data_left); 892 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 893 index = fec_enet_get_bd_index(bdp, &txq->bd); 894 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 895 bdp, index, 896 tso.data, size, 897 size == data_left, 898 total_len == 0); 899 if (ret) 900 goto err_release; 901 902 data_left -= size; 903 tso_build_data(skb, &tso, size); 904 } 905 906 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 907 } 908 909 /* Save skb pointer */ 910 txq->tx_buf[index].buf_p = skb; 911 912 skb_tx_timestamp(skb); 913 txq->bd.cur = bdp; 914 915 /* Trigger transmission start */ 916 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 917 !readl(txq->bd.reg_desc_active) || 918 !readl(txq->bd.reg_desc_active) || 919 !readl(txq->bd.reg_desc_active) || 920 !readl(txq->bd.reg_desc_active)) 921 writel(0, txq->bd.reg_desc_active); 922 923 return 0; 924 925err_release: 926 /* Release all used data descriptors for TSO */ 927 tmp_bdp = txq->bd.cur; 928 929 while (tmp_bdp != bdp) { 930 /* Unmap data buffers */ 931 if (tmp_bdp->cbd_bufaddr && 932 !IS_TSO_HEADER(txq, fec32_to_cpu(tmp_bdp->cbd_bufaddr))) 933 dma_unmap_single(&fep->pdev->dev, 934 fec32_to_cpu(tmp_bdp->cbd_bufaddr), 935 fec16_to_cpu(tmp_bdp->cbd_datlen), 936 DMA_TO_DEVICE); 937 938 /* Clear standard buffer descriptor fields */ 939 tmp_bdp->cbd_sc = 0; 940 tmp_bdp->cbd_datlen = 0; 941 tmp_bdp->cbd_bufaddr = 0; 942 943 /* Handle extended descriptor if enabled */ 944 if (fep->bufdesc_ex) { 945 ebdp = (struct bufdesc_ex *)tmp_bdp; 946 ebdp->cbd_esc = 0; 947 } 948 949 tmp_bdp = fec_enet_get_nextdesc(tmp_bdp, &txq->bd); 950 } 951 952 dev_kfree_skb_any(skb); 953 954 return ret; 955} 956 957static netdev_tx_t 958fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 959{ 960 struct fec_enet_private *fep = netdev_priv(ndev); 961 int entries_free; 962 unsigned short queue; 963 struct fec_enet_priv_tx_q *txq; 964 struct netdev_queue *nq; 965 int ret; 966 967 queue = skb_get_queue_mapping(skb); 968 txq = fep->tx_queue[queue]; 969 nq = netdev_get_tx_queue(ndev, queue); 970 971 if (skb_is_gso(skb)) 972 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 973 else 974 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 975 if (ret) 976 return ret; 977 978 entries_free = fec_enet_get_free_txdesc_num(txq); 979 if (entries_free <= txq->tx_stop_threshold) 980 netif_tx_stop_queue(nq); 981 982 return NETDEV_TX_OK; 983} 984 985/* Init RX & TX buffer descriptors 986 */ 987static void fec_enet_bd_init(struct net_device *dev) 988{ 989 struct fec_enet_private *fep = netdev_priv(dev); 990 struct fec_enet_priv_tx_q *txq; 991 struct fec_enet_priv_rx_q *rxq; 992 struct bufdesc *bdp; 993 unsigned int i; 994 unsigned int q; 995 996 for (q = 0; q < fep->num_rx_queues; q++) { 997 /* Initialize the receive buffer descriptors. */ 998 rxq = fep->rx_queue[q]; 999 bdp = rxq->bd.base; 1000 1001 for (i = 0; i < rxq->bd.ring_size; i++) { 1002 1003 /* Initialize the BD for every fragment in the page. */ 1004 if (bdp->cbd_bufaddr) 1005 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 1006 else 1007 bdp->cbd_sc = cpu_to_fec16(0); 1008 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1009 } 1010 1011 /* Set the last buffer to wrap */ 1012 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 1013 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_RX_WRAP); 1014 1015 rxq->bd.cur = rxq->bd.base; 1016 } 1017 1018 for (q = 0; q < fep->num_tx_queues; q++) { 1019 /* ...and the same for transmit */ 1020 txq = fep->tx_queue[q]; 1021 bdp = txq->bd.base; 1022 txq->bd.cur = bdp; 1023 1024 for (i = 0; i < txq->bd.ring_size; i++) { 1025 /* Initialize the BD for every fragment in the page. */ 1026 bdp->cbd_sc = cpu_to_fec16(0); 1027 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 1028 if (bdp->cbd_bufaddr && 1029 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1030 dma_unmap_single(&fep->pdev->dev, 1031 fec32_to_cpu(bdp->cbd_bufaddr), 1032 fec16_to_cpu(bdp->cbd_datlen), 1033 DMA_TO_DEVICE); 1034 if (txq->tx_buf[i].buf_p) 1035 dev_kfree_skb_any(txq->tx_buf[i].buf_p); 1036 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 1037 if (bdp->cbd_bufaddr) 1038 dma_unmap_single(&fep->pdev->dev, 1039 fec32_to_cpu(bdp->cbd_bufaddr), 1040 fec16_to_cpu(bdp->cbd_datlen), 1041 DMA_TO_DEVICE); 1042 1043 if (txq->tx_buf[i].buf_p) 1044 xdp_return_frame(txq->tx_buf[i].buf_p); 1045 } else { 1046 struct page *page = txq->tx_buf[i].buf_p; 1047 1048 if (page) 1049 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 1050 page, 0, 1051 false); 1052 } 1053 1054 txq->tx_buf[i].buf_p = NULL; 1055 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1056 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 1057 bdp->cbd_bufaddr = cpu_to_fec32(0); 1058 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1059 } 1060 1061 /* Set the last buffer to wrap */ 1062 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 1063 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_TX_WRAP); 1064 txq->dirty_tx = bdp; 1065 } 1066} 1067 1068static void fec_enet_active_rxring(struct net_device *ndev) 1069{ 1070 struct fec_enet_private *fep = netdev_priv(ndev); 1071 int i; 1072 1073 for (i = 0; i < fep->num_rx_queues; i++) 1074 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 1075} 1076 1077static void fec_enet_enable_ring(struct net_device *ndev) 1078{ 1079 struct fec_enet_private *fep = netdev_priv(ndev); 1080 struct fec_enet_priv_tx_q *txq; 1081 struct fec_enet_priv_rx_q *rxq; 1082 int i; 1083 1084 for (i = 0; i < fep->num_rx_queues; i++) { 1085 rxq = fep->rx_queue[i]; 1086 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 1087 writel(fep->max_buf_size, fep->hwp + FEC_R_BUFF_SIZE(i)); 1088 1089 /* enable DMA1/2 */ 1090 if (i) 1091 writel(RCMR_MATCHEN | RCMR_CMP(i), 1092 fep->hwp + FEC_RCMR(i)); 1093 } 1094 1095 for (i = 0; i < fep->num_tx_queues; i++) { 1096 txq = fep->tx_queue[i]; 1097 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 1098 1099 /* enable DMA1/2 */ 1100 if (i) 1101 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 1102 fep->hwp + FEC_DMA_CFG(i)); 1103 } 1104} 1105 1106/* Whack a reset. We should wait for this. 1107 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1108 * instead of reset MAC itself. 1109 */ 1110static void fec_ctrl_reset(struct fec_enet_private *fep, bool allow_wol) 1111{ 1112 u32 val; 1113 1114 if (!allow_wol || !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1115 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || 1116 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { 1117 writel(0, fep->hwp + FEC_ECNTRL); 1118 } else { 1119 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); 1120 udelay(10); 1121 } 1122 } else { 1123 val = readl(fep->hwp + FEC_ECNTRL); 1124 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1125 writel(val, fep->hwp + FEC_ECNTRL); 1126 } 1127} 1128 1129static void fec_set_hw_mac_addr(struct net_device *ndev) 1130{ 1131 struct fec_enet_private *fep = netdev_priv(ndev); 1132 1133 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1134 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1135 fep->hwp + FEC_ADDR_LOW); 1136 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1137 fep->hwp + FEC_ADDR_HIGH); 1138} 1139 1140/* 1141 * This function is called to start or restart the FEC during a link 1142 * change, transmit timeout, or to reconfigure the FEC. The network 1143 * packet processing for this device must be stopped before this call. 1144 */ 1145static void 1146fec_restart(struct net_device *ndev) 1147{ 1148 struct fec_enet_private *fep = netdev_priv(ndev); 1149 u32 ecntl = FEC_ECR_ETHEREN; 1150 u32 rcntl = FEC_RCR_MII; 1151 1152 if (OPT_ARCH_HAS_MAX_FL) 1153 rcntl |= (fep->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN) << 16; 1154 1155 if (fep->bufdesc_ex) 1156 fec_ptp_save_state(fep); 1157 1158 fec_ctrl_reset(fep, false); 1159 1160 /* 1161 * enet-mac reset will reset mac address registers too, 1162 * so need to reconfigure it. 1163 */ 1164 fec_set_hw_mac_addr(ndev); 1165 1166 /* Clear any outstanding interrupt, except MDIO. */ 1167 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 1168 1169 fec_enet_bd_init(ndev); 1170 1171 fec_enet_enable_ring(ndev); 1172 1173 /* Enable MII mode */ 1174 if (fep->full_duplex == DUPLEX_FULL) { 1175 /* FD enable */ 1176 writel(0x04, fep->hwp + FEC_X_CNTRL); 1177 } else { 1178 /* No Rcv on Xmit */ 1179 rcntl |= FEC_RCR_DRT; 1180 writel(0x0, fep->hwp + FEC_X_CNTRL); 1181 } 1182 1183 /* Set MII speed */ 1184 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1185 1186#if !defined(CONFIG_M5272) 1187 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1188 u32 val = readl(fep->hwp + FEC_RACC); 1189 1190 /* align IP header */ 1191 val |= FEC_RACC_SHIFT16; 1192 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1193 /* set RX checksum */ 1194 val |= FEC_RACC_OPTIONS; 1195 else 1196 val &= ~FEC_RACC_OPTIONS; 1197 writel(val, fep->hwp + FEC_RACC); 1198 writel(min(fep->rx_frame_size, fep->max_buf_size), fep->hwp + FEC_FTRL); 1199 } 1200#endif 1201 1202 /* 1203 * The phy interface and speed need to get configured 1204 * differently on enet-mac. 1205 */ 1206 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1207 /* Enable flow control and length check */ 1208 rcntl |= FEC_RCR_NLC | FEC_RCR_FLOWCTL; 1209 1210 /* RGMII, RMII or MII */ 1211 if (phy_interface_mode_is_rgmii(fep->phy_interface)) 1212 rcntl |= FEC_RCR_RGMII; 1213 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1214 rcntl |= FEC_RCR_RMII; 1215 else 1216 rcntl &= ~FEC_RCR_RMII; 1217 1218 /* 1G, 100M or 10M */ 1219 if (ndev->phydev) { 1220 if (ndev->phydev->speed == SPEED_1000) 1221 ecntl |= FEC_ECR_SPEED; 1222 else if (ndev->phydev->speed == SPEED_100) 1223 rcntl &= ~FEC_RCR_10BASET; 1224 else 1225 rcntl |= FEC_RCR_10BASET; 1226 } 1227 } else { 1228#ifdef FEC_MIIGSK_ENR 1229 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1230 u32 cfgr; 1231 /* disable the gasket and wait */ 1232 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1233 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1234 udelay(1); 1235 1236 /* 1237 * configure the gasket: 1238 * RMII, 50 MHz, no loopback, no echo 1239 * MII, 25 MHz, no loopback, no echo 1240 */ 1241 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1242 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1243 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1244 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1245 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1246 1247 /* re-enable the gasket */ 1248 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1249 } 1250#endif 1251 } 1252 1253#if !defined(CONFIG_M5272) 1254 /* enable pause frame*/ 1255 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1256 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1257 ndev->phydev && ndev->phydev->pause)) { 1258 rcntl |= FEC_RCR_FLOWCTL; 1259 1260 /* set FIFO threshold parameter to reduce overrun */ 1261 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1262 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1263 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1264 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1265 1266 /* OPD */ 1267 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1268 } else { 1269 rcntl &= ~FEC_RCR_FLOWCTL; 1270 } 1271#endif /* !defined(CONFIG_M5272) */ 1272 1273 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1274 1275 /* Setup multicast filter. */ 1276 set_multicast_list(ndev); 1277#ifndef CONFIG_M5272 1278 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1279 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1280#endif 1281 1282 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1283 /* enable ENET endian swap */ 1284 ecntl |= FEC_ECR_BYTESWP; 1285 1286 /* When Jumbo Frame is enabled, the FIFO may not be large enough 1287 * to hold an entire frame. In such cases, if the MTU exceeds 1288 * (PKT_MAXBUF_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN), configure 1289 * the interface to operate in cut-through mode, triggered by 1290 * the FIFO threshold. 1291 * Otherwise, enable the ENET store-and-forward mode. 1292 */ 1293 if ((fep->quirks & FEC_QUIRK_JUMBO_FRAME) && 1294 (ndev->mtu > (PKT_MAXBUF_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN))) 1295 writel(0xF, fep->hwp + FEC_X_WMRK); 1296 else 1297 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); 1298 } 1299 1300 if (fep->bufdesc_ex) 1301 ecntl |= FEC_ECR_EN1588; 1302 1303 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1304 fep->rgmii_txc_dly) 1305 ecntl |= FEC_ENET_TXC_DLY; 1306 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && 1307 fep->rgmii_rxc_dly) 1308 ecntl |= FEC_ENET_RXC_DLY; 1309 1310#ifndef CONFIG_M5272 1311 /* Enable the MIB statistic event counters */ 1312 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1313#endif 1314 1315 /* And last, enable the transmit and receive processing */ 1316 writel(ecntl, fep->hwp + FEC_ECNTRL); 1317 fec_enet_active_rxring(ndev); 1318 1319 if (fep->bufdesc_ex) { 1320 fec_ptp_start_cyclecounter(ndev); 1321 fec_ptp_restore_state(fep); 1322 } 1323 1324 /* Enable interrupts we wish to service */ 1325 if (fep->link) 1326 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1327 else 1328 writel(0, fep->hwp + FEC_IMASK); 1329 1330 /* Init the interrupt coalescing */ 1331 if (fep->quirks & FEC_QUIRK_HAS_COALESCE) 1332 fec_enet_itr_coal_set(ndev); 1333} 1334 1335static int fec_enet_ipc_handle_init(struct fec_enet_private *fep) 1336{ 1337 if (!(of_machine_is_compatible("fsl,imx8qm") || 1338 of_machine_is_compatible("fsl,imx8qxp") || 1339 of_machine_is_compatible("fsl,imx8dxl"))) 1340 return 0; 1341 1342 return imx_scu_get_handle(&fep->ipc_handle); 1343} 1344 1345static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled) 1346{ 1347 struct device_node *np = fep->pdev->dev.of_node; 1348 u32 rsrc_id, val; 1349 int idx; 1350 1351 if (!np || !fep->ipc_handle) 1352 return; 1353 1354 idx = of_alias_get_id(np, "ethernet"); 1355 if (idx < 0) 1356 idx = 0; 1357 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0; 1358 1359 val = enabled ? 1 : 0; 1360 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val); 1361} 1362 1363static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1364{ 1365 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1366 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1367 1368 if (stop_gpr->gpr) { 1369 if (enabled) 1370 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1371 BIT(stop_gpr->bit), 1372 BIT(stop_gpr->bit)); 1373 else 1374 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1375 BIT(stop_gpr->bit), 0); 1376 } else if (pdata && pdata->sleep_mode_enable) { 1377 pdata->sleep_mode_enable(enabled); 1378 } else { 1379 fec_enet_ipg_stop_set(fep, enabled); 1380 } 1381} 1382 1383static void fec_irqs_disable(struct net_device *ndev) 1384{ 1385 struct fec_enet_private *fep = netdev_priv(ndev); 1386 1387 writel(0, fep->hwp + FEC_IMASK); 1388} 1389 1390static void fec_irqs_disable_except_wakeup(struct net_device *ndev) 1391{ 1392 struct fec_enet_private *fep = netdev_priv(ndev); 1393 1394 writel(0, fep->hwp + FEC_IMASK); 1395 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1396} 1397 1398static void 1399fec_stop(struct net_device *ndev) 1400{ 1401 struct fec_enet_private *fep = netdev_priv(ndev); 1402 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; 1403 u32 val; 1404 1405 /* We cannot expect a graceful transmit stop without link !!! */ 1406 if (fep->link) { 1407 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1408 udelay(10); 1409 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1410 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1411 } 1412 1413 if (fep->bufdesc_ex) 1414 fec_ptp_save_state(fep); 1415 1416 fec_ctrl_reset(fep, true); 1417 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1418 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1419 1420 /* We have to keep ENET enabled to have MII interrupt stay working */ 1421 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1422 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1423 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); 1424 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1425 } 1426 1427 if (fep->bufdesc_ex) { 1428 val = readl(fep->hwp + FEC_ECNTRL); 1429 val |= FEC_ECR_EN1588; 1430 writel(val, fep->hwp + FEC_ECNTRL); 1431 1432 fec_ptp_start_cyclecounter(ndev); 1433 fec_ptp_restore_state(fep); 1434 } 1435} 1436 1437static void 1438fec_timeout(struct net_device *ndev, unsigned int txqueue) 1439{ 1440 struct fec_enet_private *fep = netdev_priv(ndev); 1441 1442 fec_dump(ndev); 1443 1444 ndev->stats.tx_errors++; 1445 1446 schedule_work(&fep->tx_timeout_work); 1447} 1448 1449static void fec_enet_timeout_work(struct work_struct *work) 1450{ 1451 struct fec_enet_private *fep = 1452 container_of(work, struct fec_enet_private, tx_timeout_work); 1453 struct net_device *ndev = fep->netdev; 1454 1455 rtnl_lock(); 1456 if (netif_device_present(ndev) || netif_running(ndev)) { 1457 napi_disable(&fep->napi); 1458 netif_tx_lock_bh(ndev); 1459 fec_restart(ndev); 1460 netif_tx_wake_all_queues(ndev); 1461 netif_tx_unlock_bh(ndev); 1462 napi_enable(&fep->napi); 1463 } 1464 rtnl_unlock(); 1465} 1466 1467static void 1468fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1469 struct skb_shared_hwtstamps *hwtstamps) 1470{ 1471 unsigned long flags; 1472 u64 ns; 1473 1474 spin_lock_irqsave(&fep->tmreg_lock, flags); 1475 ns = timecounter_cyc2time(&fep->tc, ts); 1476 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1477 1478 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1479 hwtstamps->hwtstamp = ns_to_ktime(ns); 1480} 1481 1482static void 1483fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget) 1484{ 1485 struct fec_enet_private *fep; 1486 struct xdp_frame *xdpf; 1487 struct bufdesc *bdp; 1488 unsigned short status; 1489 struct sk_buff *skb; 1490 struct fec_enet_priv_tx_q *txq; 1491 struct netdev_queue *nq; 1492 int index = 0; 1493 int entries_free; 1494 struct page *page; 1495 int frame_len; 1496 1497 fep = netdev_priv(ndev); 1498 1499 txq = fep->tx_queue[queue_id]; 1500 /* get next bdp of dirty_tx */ 1501 nq = netdev_get_tx_queue(ndev, queue_id); 1502 bdp = txq->dirty_tx; 1503 1504 /* get next bdp of dirty_tx */ 1505 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1506 1507 while (bdp != READ_ONCE(txq->bd.cur)) { 1508 /* Order the load of bd.cur and cbd_sc */ 1509 rmb(); 1510 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1511 if (status & BD_ENET_TX_READY) 1512 break; 1513 1514 index = fec_enet_get_bd_index(bdp, &txq->bd); 1515 1516 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1517 skb = txq->tx_buf[index].buf_p; 1518 if (bdp->cbd_bufaddr && 1519 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1520 dma_unmap_single(&fep->pdev->dev, 1521 fec32_to_cpu(bdp->cbd_bufaddr), 1522 fec16_to_cpu(bdp->cbd_datlen), 1523 DMA_TO_DEVICE); 1524 bdp->cbd_bufaddr = cpu_to_fec32(0); 1525 if (!skb) 1526 goto tx_buf_done; 1527 } else { 1528 /* Tx processing cannot call any XDP (or page pool) APIs if 1529 * the "budget" is 0. Because NAPI is called with budget of 1530 * 0 (such as netpoll) indicates we may be in an IRQ context, 1531 * however, we can't use the page pool from IRQ context. 1532 */ 1533 if (unlikely(!budget)) 1534 break; 1535 1536 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1537 xdpf = txq->tx_buf[index].buf_p; 1538 if (bdp->cbd_bufaddr) 1539 dma_unmap_single(&fep->pdev->dev, 1540 fec32_to_cpu(bdp->cbd_bufaddr), 1541 fec16_to_cpu(bdp->cbd_datlen), 1542 DMA_TO_DEVICE); 1543 } else { 1544 page = txq->tx_buf[index].buf_p; 1545 } 1546 1547 bdp->cbd_bufaddr = cpu_to_fec32(0); 1548 if (unlikely(!txq->tx_buf[index].buf_p)) { 1549 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1550 goto tx_buf_done; 1551 } 1552 1553 frame_len = fec16_to_cpu(bdp->cbd_datlen); 1554 } 1555 1556 /* Check for errors. */ 1557 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1558 BD_ENET_TX_RL | BD_ENET_TX_UN | 1559 BD_ENET_TX_CSL)) { 1560 ndev->stats.tx_errors++; 1561 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1562 ndev->stats.tx_heartbeat_errors++; 1563 if (status & BD_ENET_TX_LC) /* Late collision */ 1564 ndev->stats.tx_window_errors++; 1565 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1566 ndev->stats.tx_aborted_errors++; 1567 if (status & BD_ENET_TX_UN) /* Underrun */ 1568 ndev->stats.tx_fifo_errors++; 1569 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1570 ndev->stats.tx_carrier_errors++; 1571 } else { 1572 ndev->stats.tx_packets++; 1573 1574 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) 1575 ndev->stats.tx_bytes += skb->len; 1576 else 1577 ndev->stats.tx_bytes += frame_len; 1578 } 1579 1580 /* Deferred means some collisions occurred during transmit, 1581 * but we eventually sent the packet OK. 1582 */ 1583 if (status & BD_ENET_TX_DEF) 1584 ndev->stats.collisions++; 1585 1586 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) { 1587 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1588 * are to time stamp the packet, so we still need to check time 1589 * stamping enabled flag. 1590 */ 1591 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1592 fep->hwts_tx_en) && fep->bufdesc_ex) { 1593 struct skb_shared_hwtstamps shhwtstamps; 1594 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1595 1596 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1597 skb_tstamp_tx(skb, &shhwtstamps); 1598 } 1599 1600 /* Free the sk buffer associated with this last transmit */ 1601 napi_consume_skb(skb, budget); 1602 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) { 1603 xdp_return_frame_rx_napi(xdpf); 1604 } else { /* recycle pages of XDP_TX frames */ 1605 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */ 1606 page_pool_put_page(pp_page_to_nmdesc(page)->pp, page, 1607 0, true); 1608 } 1609 1610 txq->tx_buf[index].buf_p = NULL; 1611 /* restore default tx buffer type: FEC_TXBUF_T_SKB */ 1612 txq->tx_buf[index].type = FEC_TXBUF_T_SKB; 1613 1614tx_buf_done: 1615 /* Make sure the update to bdp and tx_buf are performed 1616 * before dirty_tx 1617 */ 1618 wmb(); 1619 txq->dirty_tx = bdp; 1620 1621 /* Update pointer to next buffer descriptor to be transmitted */ 1622 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1623 1624 /* Since we have freed up a buffer, the ring is no longer full 1625 */ 1626 if (netif_tx_queue_stopped(nq)) { 1627 entries_free = fec_enet_get_free_txdesc_num(txq); 1628 if (entries_free >= txq->tx_wake_threshold) 1629 netif_tx_wake_queue(nq); 1630 } 1631 } 1632 1633 /* ERR006358: Keep the transmitter going */ 1634 if (bdp != txq->bd.cur && 1635 readl(txq->bd.reg_desc_active) == 0) 1636 writel(0, txq->bd.reg_desc_active); 1637} 1638 1639static void fec_enet_tx(struct net_device *ndev, int budget) 1640{ 1641 struct fec_enet_private *fep = netdev_priv(ndev); 1642 int i; 1643 1644 /* Make sure that AVB queues are processed first. */ 1645 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1646 fec_enet_tx_queue(ndev, i, budget); 1647} 1648 1649static int fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq, 1650 struct bufdesc *bdp, int index) 1651{ 1652 struct page *new_page; 1653 dma_addr_t phys_addr; 1654 1655 new_page = page_pool_dev_alloc_pages(rxq->page_pool); 1656 if (unlikely(!new_page)) 1657 return -ENOMEM; 1658 1659 rxq->rx_buf[index] = new_page; 1660 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM; 1661 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 1662 1663 return 0; 1664} 1665 1666static u32 1667fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog, 1668 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu) 1669{ 1670 unsigned int sync, len = xdp->data_end - xdp->data; 1671 u32 ret = FEC_ENET_XDP_PASS; 1672 struct page *page; 1673 int err; 1674 u32 act; 1675 1676 act = bpf_prog_run_xdp(prog, xdp); 1677 1678 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover 1679 * max len CPU touch 1680 */ 1681 sync = xdp->data_end - xdp->data; 1682 sync = max(sync, len); 1683 1684 switch (act) { 1685 case XDP_PASS: 1686 rxq->stats[RX_XDP_PASS]++; 1687 ret = FEC_ENET_XDP_PASS; 1688 break; 1689 1690 case XDP_REDIRECT: 1691 rxq->stats[RX_XDP_REDIRECT]++; 1692 err = xdp_do_redirect(fep->netdev, xdp, prog); 1693 if (unlikely(err)) 1694 goto xdp_err; 1695 1696 ret = FEC_ENET_XDP_REDIR; 1697 break; 1698 1699 case XDP_TX: 1700 rxq->stats[RX_XDP_TX]++; 1701 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync); 1702 if (unlikely(err)) { 1703 rxq->stats[RX_XDP_TX_ERRORS]++; 1704 goto xdp_err; 1705 } 1706 1707 ret = FEC_ENET_XDP_TX; 1708 break; 1709 1710 default: 1711 bpf_warn_invalid_xdp_action(fep->netdev, prog, act); 1712 fallthrough; 1713 1714 case XDP_ABORTED: 1715 fallthrough; /* handle aborts by dropping packet */ 1716 1717 case XDP_DROP: 1718 rxq->stats[RX_XDP_DROP]++; 1719xdp_err: 1720 ret = FEC_ENET_XDP_CONSUMED; 1721 page = virt_to_head_page(xdp->data); 1722 page_pool_put_page(rxq->page_pool, page, sync, true); 1723 if (act != XDP_DROP) 1724 trace_xdp_exception(fep->netdev, prog, act); 1725 break; 1726 } 1727 1728 return ret; 1729} 1730 1731static void fec_enet_rx_vlan(const struct net_device *ndev, struct sk_buff *skb) 1732{ 1733 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { 1734 const struct vlan_ethhdr *vlan_header = skb_vlan_eth_hdr(skb); 1735 const u16 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1736 1737 /* Push and remove the vlan tag */ 1738 1739 memmove(skb->data + VLAN_HLEN, skb->data, ETH_ALEN * 2); 1740 skb_pull(skb, VLAN_HLEN); 1741 __vlan_hwaccel_put_tag(skb, 1742 htons(ETH_P_8021Q), 1743 vlan_tag); 1744 } 1745} 1746 1747/* During a receive, the bd_rx.cur points to the current incoming buffer. 1748 * When we update through the ring, if the next incoming buffer has 1749 * not been given to the system, we just set the empty indicator, 1750 * effectively tossing the packet. 1751 */ 1752static int 1753fec_enet_rx_queue(struct net_device *ndev, u16 queue_id, int budget) 1754{ 1755 struct fec_enet_private *fep = netdev_priv(ndev); 1756 struct fec_enet_priv_rx_q *rxq; 1757 struct bufdesc *bdp; 1758 unsigned short status; 1759 struct sk_buff *skb; 1760 ushort pkt_len; 1761 int pkt_received = 0; 1762 struct bufdesc_ex *ebdp = NULL; 1763 int index = 0; 1764 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1765 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog); 1766 u32 ret, xdp_result = FEC_ENET_XDP_PASS; 1767 u32 data_start = FEC_ENET_XDP_HEADROOM; 1768 int cpu = smp_processor_id(); 1769 struct xdp_buff xdp; 1770 struct page *page; 1771 __fec32 cbd_bufaddr; 1772 u32 sub_len = 4; 1773 1774 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of 1775 * FEC_RACC_SHIFT16 is set by default in the probe function. 1776 */ 1777 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1778 data_start += 2; 1779 sub_len += 2; 1780 } 1781 1782#if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA) 1783 /* 1784 * Hacky flush of all caches instead of using the DMA API for the TSO 1785 * headers. 1786 */ 1787 flush_cache_all(); 1788#endif 1789 rxq = fep->rx_queue[queue_id]; 1790 1791 /* First, grab all of the stats for the incoming packet. 1792 * These get messed up if we get called due to a busy condition. 1793 */ 1794 bdp = rxq->bd.cur; 1795 xdp_init_buff(&xdp, PAGE_SIZE << fep->pagepool_order, &rxq->xdp_rxq); 1796 1797 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1798 1799 if (pkt_received >= budget) 1800 break; 1801 pkt_received++; 1802 1803 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1804 1805 /* Check for errors. */ 1806 status ^= BD_ENET_RX_LAST; 1807 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1808 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1809 BD_ENET_RX_CL)) { 1810 ndev->stats.rx_errors++; 1811 if (status & BD_ENET_RX_OV) { 1812 /* FIFO overrun */ 1813 ndev->stats.rx_fifo_errors++; 1814 goto rx_processing_done; 1815 } 1816 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1817 | BD_ENET_RX_LAST)) { 1818 /* Frame too long or too short. */ 1819 ndev->stats.rx_length_errors++; 1820 if (status & BD_ENET_RX_LAST) 1821 netdev_err(ndev, "rcv is not +last\n"); 1822 } 1823 if (status & BD_ENET_RX_CR) /* CRC Error */ 1824 ndev->stats.rx_crc_errors++; 1825 /* Report late collisions as a frame error. */ 1826 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1827 ndev->stats.rx_frame_errors++; 1828 goto rx_processing_done; 1829 } 1830 1831 /* Process the incoming frame. */ 1832 ndev->stats.rx_packets++; 1833 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1834 ndev->stats.rx_bytes += pkt_len; 1835 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1836 ndev->stats.rx_bytes -= 2; 1837 1838 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1839 page = rxq->rx_buf[index]; 1840 cbd_bufaddr = bdp->cbd_bufaddr; 1841 if (fec_enet_update_cbd(rxq, bdp, index)) { 1842 ndev->stats.rx_dropped++; 1843 goto rx_processing_done; 1844 } 1845 1846 dma_sync_single_for_cpu(&fep->pdev->dev, 1847 fec32_to_cpu(cbd_bufaddr), 1848 pkt_len, 1849 DMA_FROM_DEVICE); 1850 prefetch(page_address(page)); 1851 1852 if (xdp_prog) { 1853 xdp_buff_clear_frags_flag(&xdp); 1854 /* subtract 16bit shift and FCS */ 1855 xdp_prepare_buff(&xdp, page_address(page), 1856 data_start, pkt_len - sub_len, false); 1857 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu); 1858 xdp_result |= ret; 1859 if (ret != FEC_ENET_XDP_PASS) 1860 goto rx_processing_done; 1861 } 1862 1863 /* The packet length includes FCS, but we don't want to 1864 * include that when passing upstream as it messes up 1865 * bridging applications. 1866 */ 1867 skb = build_skb(page_address(page), 1868 PAGE_SIZE << fep->pagepool_order); 1869 if (unlikely(!skb)) { 1870 page_pool_recycle_direct(rxq->page_pool, page); 1871 ndev->stats.rx_dropped++; 1872 1873 netdev_err_once(ndev, "build_skb failed!\n"); 1874 goto rx_processing_done; 1875 } 1876 1877 skb_reserve(skb, data_start); 1878 skb_put(skb, pkt_len - sub_len); 1879 skb_mark_for_recycle(skb); 1880 1881 if (unlikely(need_swap)) { 1882 u8 *data; 1883 1884 data = page_address(page) + FEC_ENET_XDP_HEADROOM; 1885 swap_buffer(data, pkt_len); 1886 } 1887 1888 /* Extract the enhanced buffer descriptor */ 1889 ebdp = NULL; 1890 if (fep->bufdesc_ex) 1891 ebdp = (struct bufdesc_ex *)bdp; 1892 1893 /* If this is a VLAN packet remove the VLAN Tag */ 1894 if (fep->bufdesc_ex && 1895 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) 1896 fec_enet_rx_vlan(ndev, skb); 1897 1898 skb->protocol = eth_type_trans(skb, ndev); 1899 1900 /* Get receive timestamp from the skb */ 1901 if (fep->hwts_rx_en && fep->bufdesc_ex) 1902 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1903 skb_hwtstamps(skb)); 1904 1905 if (fep->bufdesc_ex && 1906 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1907 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1908 /* don't check it */ 1909 skb->ip_summed = CHECKSUM_UNNECESSARY; 1910 } else { 1911 skb_checksum_none_assert(skb); 1912 } 1913 } 1914 1915 skb_record_rx_queue(skb, queue_id); 1916 napi_gro_receive(&fep->napi, skb); 1917 1918rx_processing_done: 1919 /* Clear the status flags for this buffer */ 1920 status &= ~BD_ENET_RX_STATS; 1921 1922 /* Mark the buffer empty */ 1923 status |= BD_ENET_RX_EMPTY; 1924 1925 if (fep->bufdesc_ex) { 1926 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1927 1928 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1929 ebdp->cbd_prot = 0; 1930 ebdp->cbd_bdu = 0; 1931 } 1932 /* Make sure the updates to rest of the descriptor are 1933 * performed before transferring ownership. 1934 */ 1935 wmb(); 1936 bdp->cbd_sc = cpu_to_fec16(status); 1937 1938 /* Update BD pointer to next entry */ 1939 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1940 1941 /* Doing this here will keep the FEC running while we process 1942 * incoming frames. On a heavily loaded network, we should be 1943 * able to keep up at the expense of system resources. 1944 */ 1945 writel(0, rxq->bd.reg_desc_active); 1946 } 1947 rxq->bd.cur = bdp; 1948 1949 if (xdp_result & FEC_ENET_XDP_REDIR) 1950 xdp_do_flush(); 1951 1952 return pkt_received; 1953} 1954 1955static int fec_enet_rx(struct net_device *ndev, int budget) 1956{ 1957 struct fec_enet_private *fep = netdev_priv(ndev); 1958 int i, done = 0; 1959 1960 /* Make sure that AVB queues are processed first. */ 1961 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1962 done += fec_enet_rx_queue(ndev, i, budget - done); 1963 1964 return done; 1965} 1966 1967static bool fec_enet_collect_events(struct fec_enet_private *fep) 1968{ 1969 uint int_events; 1970 1971 int_events = readl(fep->hwp + FEC_IEVENT); 1972 1973 /* Don't clear MDIO events, we poll for those */ 1974 int_events &= ~FEC_ENET_MII; 1975 1976 writel(int_events, fep->hwp + FEC_IEVENT); 1977 1978 return int_events != 0; 1979} 1980 1981static irqreturn_t 1982fec_enet_interrupt(int irq, void *dev_id) 1983{ 1984 struct net_device *ndev = dev_id; 1985 struct fec_enet_private *fep = netdev_priv(ndev); 1986 irqreturn_t ret = IRQ_NONE; 1987 1988 if (fec_enet_collect_events(fep) && fep->link) { 1989 ret = IRQ_HANDLED; 1990 1991 if (napi_schedule_prep(&fep->napi)) { 1992 /* Disable interrupts */ 1993 writel(0, fep->hwp + FEC_IMASK); 1994 __napi_schedule(&fep->napi); 1995 } 1996 } 1997 1998 return ret; 1999} 2000 2001static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 2002{ 2003 struct net_device *ndev = napi->dev; 2004 struct fec_enet_private *fep = netdev_priv(ndev); 2005 int done = 0; 2006 2007 do { 2008 done += fec_enet_rx(ndev, budget - done); 2009 fec_enet_tx(ndev, budget); 2010 } while ((done < budget) && fec_enet_collect_events(fep)); 2011 2012 if (done < budget) { 2013 napi_complete_done(napi, done); 2014 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 2015 } 2016 2017 return done; 2018} 2019 2020/* ------------------------------------------------------------------------- */ 2021static int fec_get_mac(struct net_device *ndev) 2022{ 2023 struct fec_enet_private *fep = netdev_priv(ndev); 2024 unsigned char *iap, tmpaddr[ETH_ALEN]; 2025 int ret; 2026 2027 /* 2028 * try to get mac address in following order: 2029 * 2030 * 1) module parameter via kernel command line in form 2031 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 2032 */ 2033 iap = macaddr; 2034 2035 /* 2036 * 2) from device tree data 2037 */ 2038 if (!is_valid_ether_addr(iap)) { 2039 struct device_node *np = fep->pdev->dev.of_node; 2040 if (np) { 2041 ret = of_get_mac_address(np, tmpaddr); 2042 if (!ret) 2043 iap = tmpaddr; 2044 else if (ret == -EPROBE_DEFER) 2045 return ret; 2046 } 2047 } 2048 2049 /* 2050 * 3) from flash or fuse (via platform data) 2051 */ 2052 if (!is_valid_ether_addr(iap)) { 2053#ifdef CONFIG_M5272 2054 if (FEC_FLASHMAC) 2055 iap = (unsigned char *)FEC_FLASHMAC; 2056#else 2057 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 2058 2059 if (pdata) 2060 iap = (unsigned char *)&pdata->mac; 2061#endif 2062 } 2063 2064 /* 2065 * 4) FEC mac registers set by bootloader 2066 */ 2067 if (!is_valid_ether_addr(iap)) { 2068 *((__be32 *) &tmpaddr[0]) = 2069 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 2070 *((__be16 *) &tmpaddr[4]) = 2071 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 2072 iap = &tmpaddr[0]; 2073 } 2074 2075 /* 2076 * 5) random mac address 2077 */ 2078 if (!is_valid_ether_addr(iap)) { 2079 /* Report it and use a random ethernet address instead */ 2080 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 2081 eth_hw_addr_random(ndev); 2082 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 2083 ndev->dev_addr); 2084 return 0; 2085 } 2086 2087 /* Adjust MAC if using macaddr */ 2088 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0); 2089 2090 return 0; 2091} 2092 2093/* ------------------------------------------------------------------------- */ 2094 2095/* 2096 * Phy section 2097 */ 2098 2099/* LPI Sleep Ts count base on tx clk (clk_ref). 2100 * The lpi sleep cnt value = X us / (cycle_ns). 2101 */ 2102static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) 2103{ 2104 struct fec_enet_private *fep = netdev_priv(ndev); 2105 2106 return us * (fep->clk_ref_rate / 1000) / 1000; 2107} 2108 2109static int fec_enet_eee_mode_set(struct net_device *ndev, u32 lpi_timer, 2110 bool enable) 2111{ 2112 struct fec_enet_private *fep = netdev_priv(ndev); 2113 unsigned int sleep_cycle, wake_cycle; 2114 2115 if (enable) { 2116 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, lpi_timer); 2117 wake_cycle = sleep_cycle; 2118 } else { 2119 sleep_cycle = 0; 2120 wake_cycle = 0; 2121 } 2122 2123 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); 2124 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); 2125 2126 return 0; 2127} 2128 2129static void fec_enet_adjust_link(struct net_device *ndev) 2130{ 2131 struct fec_enet_private *fep = netdev_priv(ndev); 2132 struct phy_device *phy_dev = ndev->phydev; 2133 int status_change = 0; 2134 2135 /* 2136 * If the netdev is down, or is going down, we're not interested 2137 * in link state events, so just mark our idea of the link as down 2138 * and ignore the event. 2139 */ 2140 if (!netif_running(ndev) || !netif_device_present(ndev)) { 2141 fep->link = 0; 2142 } else if (phy_dev->link) { 2143 if (!fep->link) { 2144 fep->link = phy_dev->link; 2145 status_change = 1; 2146 } 2147 2148 if (fep->full_duplex != phy_dev->duplex) { 2149 fep->full_duplex = phy_dev->duplex; 2150 status_change = 1; 2151 } 2152 2153 if (phy_dev->speed != fep->speed) { 2154 fep->speed = phy_dev->speed; 2155 status_change = 1; 2156 } 2157 2158 /* if any of the above changed restart the FEC */ 2159 if (status_change) { 2160 netif_stop_queue(ndev); 2161 napi_disable(&fep->napi); 2162 netif_tx_lock_bh(ndev); 2163 fec_restart(ndev); 2164 netif_tx_wake_all_queues(ndev); 2165 netif_tx_unlock_bh(ndev); 2166 napi_enable(&fep->napi); 2167 } 2168 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2169 fec_enet_eee_mode_set(ndev, 2170 phy_dev->eee_cfg.tx_lpi_timer, 2171 phy_dev->enable_tx_lpi); 2172 } else { 2173 if (fep->link) { 2174 netif_stop_queue(ndev); 2175 napi_disable(&fep->napi); 2176 netif_tx_lock_bh(ndev); 2177 fec_stop(ndev); 2178 netif_tx_unlock_bh(ndev); 2179 napi_enable(&fep->napi); 2180 fep->link = phy_dev->link; 2181 status_change = 1; 2182 } 2183 } 2184 2185 if (status_change) 2186 phy_print_status(phy_dev); 2187} 2188 2189static int fec_enet_mdio_wait(struct fec_enet_private *fep) 2190{ 2191 uint ievent; 2192 int ret; 2193 2194 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 2195 ievent & FEC_ENET_MII, 2, 30000); 2196 2197 if (!ret) 2198 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2199 2200 return ret; 2201} 2202 2203static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) 2204{ 2205 struct fec_enet_private *fep = bus->priv; 2206 struct device *dev = &fep->pdev->dev; 2207 int ret = 0, frame_start, frame_addr, frame_op; 2208 2209 ret = pm_runtime_resume_and_get(dev); 2210 if (ret < 0) 2211 return ret; 2212 2213 /* C22 read */ 2214 frame_op = FEC_MMFR_OP_READ; 2215 frame_start = FEC_MMFR_ST; 2216 frame_addr = regnum; 2217 2218 /* start a read op */ 2219 writel(frame_start | frame_op | 2220 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2221 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2222 2223 /* wait for end of transfer */ 2224 ret = fec_enet_mdio_wait(fep); 2225 if (ret) { 2226 netdev_err(fep->netdev, "MDIO read timeout\n"); 2227 goto out; 2228 } 2229 2230 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2231 2232out: 2233 pm_runtime_put_autosuspend(dev); 2234 2235 return ret; 2236} 2237 2238static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, 2239 int devad, int regnum) 2240{ 2241 struct fec_enet_private *fep = bus->priv; 2242 struct device *dev = &fep->pdev->dev; 2243 int ret = 0, frame_start, frame_op; 2244 2245 ret = pm_runtime_resume_and_get(dev); 2246 if (ret < 0) 2247 return ret; 2248 2249 frame_start = FEC_MMFR_ST_C45; 2250 2251 /* write address */ 2252 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2253 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2254 FEC_MMFR_TA | (regnum & 0xFFFF), 2255 fep->hwp + FEC_MII_DATA); 2256 2257 /* wait for end of transfer */ 2258 ret = fec_enet_mdio_wait(fep); 2259 if (ret) { 2260 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2261 goto out; 2262 } 2263 2264 frame_op = FEC_MMFR_OP_READ_C45; 2265 2266 /* start a read op */ 2267 writel(frame_start | frame_op | 2268 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2269 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 2270 2271 /* wait for end of transfer */ 2272 ret = fec_enet_mdio_wait(fep); 2273 if (ret) { 2274 netdev_err(fep->netdev, "MDIO read timeout\n"); 2275 goto out; 2276 } 2277 2278 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 2279 2280out: 2281 pm_runtime_put_autosuspend(dev); 2282 2283 return ret; 2284} 2285 2286static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, 2287 u16 value) 2288{ 2289 struct fec_enet_private *fep = bus->priv; 2290 struct device *dev = &fep->pdev->dev; 2291 int ret, frame_start, frame_addr; 2292 2293 ret = pm_runtime_resume_and_get(dev); 2294 if (ret < 0) 2295 return ret; 2296 2297 /* C22 write */ 2298 frame_start = FEC_MMFR_ST; 2299 frame_addr = regnum; 2300 2301 /* start a write op */ 2302 writel(frame_start | FEC_MMFR_OP_WRITE | 2303 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 2304 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2305 fep->hwp + FEC_MII_DATA); 2306 2307 /* wait for end of transfer */ 2308 ret = fec_enet_mdio_wait(fep); 2309 if (ret) 2310 netdev_err(fep->netdev, "MDIO write timeout\n"); 2311 2312 pm_runtime_put_autosuspend(dev); 2313 2314 return ret; 2315} 2316 2317static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, 2318 int devad, int regnum, u16 value) 2319{ 2320 struct fec_enet_private *fep = bus->priv; 2321 struct device *dev = &fep->pdev->dev; 2322 int ret, frame_start; 2323 2324 ret = pm_runtime_resume_and_get(dev); 2325 if (ret < 0) 2326 return ret; 2327 2328 frame_start = FEC_MMFR_ST_C45; 2329 2330 /* write address */ 2331 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 2332 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2333 FEC_MMFR_TA | (regnum & 0xFFFF), 2334 fep->hwp + FEC_MII_DATA); 2335 2336 /* wait for end of transfer */ 2337 ret = fec_enet_mdio_wait(fep); 2338 if (ret) { 2339 netdev_err(fep->netdev, "MDIO address write timeout\n"); 2340 goto out; 2341 } 2342 2343 /* start a write op */ 2344 writel(frame_start | FEC_MMFR_OP_WRITE | 2345 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | 2346 FEC_MMFR_TA | FEC_MMFR_DATA(value), 2347 fep->hwp + FEC_MII_DATA); 2348 2349 /* wait for end of transfer */ 2350 ret = fec_enet_mdio_wait(fep); 2351 if (ret) 2352 netdev_err(fep->netdev, "MDIO write timeout\n"); 2353 2354out: 2355 pm_runtime_put_autosuspend(dev); 2356 2357 return ret; 2358} 2359 2360static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 2361{ 2362 struct fec_enet_private *fep = netdev_priv(ndev); 2363 struct phy_device *phy_dev = ndev->phydev; 2364 2365 if (phy_dev) { 2366 phy_reset_after_clk_enable(phy_dev); 2367 } else if (fep->phy_node) { 2368 /* 2369 * If the PHY still is not bound to the MAC, but there is 2370 * OF PHY node and a matching PHY device instance already, 2371 * use the OF PHY node to obtain the PHY device instance, 2372 * and then use that PHY device instance when triggering 2373 * the PHY reset. 2374 */ 2375 phy_dev = of_phy_find_device(fep->phy_node); 2376 phy_reset_after_clk_enable(phy_dev); 2377 if (phy_dev) 2378 put_device(&phy_dev->mdio.dev); 2379 } 2380} 2381 2382static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 2383{ 2384 struct fec_enet_private *fep = netdev_priv(ndev); 2385 int ret; 2386 2387 if (enable) { 2388 ret = clk_prepare_enable(fep->clk_enet_out); 2389 if (ret) 2390 return ret; 2391 2392 if (fep->clk_ptp) { 2393 mutex_lock(&fep->ptp_clk_mutex); 2394 ret = clk_prepare_enable(fep->clk_ptp); 2395 if (ret) { 2396 mutex_unlock(&fep->ptp_clk_mutex); 2397 goto failed_clk_ptp; 2398 } else { 2399 fep->ptp_clk_on = true; 2400 } 2401 mutex_unlock(&fep->ptp_clk_mutex); 2402 } 2403 2404 ret = clk_prepare_enable(fep->clk_ref); 2405 if (ret) 2406 goto failed_clk_ref; 2407 2408 ret = clk_prepare_enable(fep->clk_2x_txclk); 2409 if (ret) 2410 goto failed_clk_2x_txclk; 2411 2412 fec_enet_phy_reset_after_clk_enable(ndev); 2413 } else { 2414 clk_disable_unprepare(fep->clk_enet_out); 2415 if (fep->clk_ptp) { 2416 mutex_lock(&fep->ptp_clk_mutex); 2417 clk_disable_unprepare(fep->clk_ptp); 2418 fep->ptp_clk_on = false; 2419 mutex_unlock(&fep->ptp_clk_mutex); 2420 } 2421 clk_disable_unprepare(fep->clk_ref); 2422 clk_disable_unprepare(fep->clk_2x_txclk); 2423 } 2424 2425 return 0; 2426 2427failed_clk_2x_txclk: 2428 if (fep->clk_ref) 2429 clk_disable_unprepare(fep->clk_ref); 2430failed_clk_ref: 2431 if (fep->clk_ptp) { 2432 mutex_lock(&fep->ptp_clk_mutex); 2433 clk_disable_unprepare(fep->clk_ptp); 2434 fep->ptp_clk_on = false; 2435 mutex_unlock(&fep->ptp_clk_mutex); 2436 } 2437failed_clk_ptp: 2438 clk_disable_unprepare(fep->clk_enet_out); 2439 2440 return ret; 2441} 2442 2443static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep, 2444 struct device_node *np) 2445{ 2446 u32 rgmii_tx_delay, rgmii_rx_delay; 2447 2448 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ 2449 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { 2450 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) { 2451 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); 2452 return -EINVAL; 2453 } else if (rgmii_tx_delay == 2000) { 2454 fep->rgmii_txc_dly = true; 2455 } 2456 } 2457 2458 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */ 2459 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { 2460 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) { 2461 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); 2462 return -EINVAL; 2463 } else if (rgmii_rx_delay == 2000) { 2464 fep->rgmii_rxc_dly = true; 2465 } 2466 } 2467 2468 return 0; 2469} 2470 2471static int fec_enet_mii_probe(struct net_device *ndev) 2472{ 2473 struct fec_enet_private *fep = netdev_priv(ndev); 2474 struct phy_device *phy_dev; 2475 int ret; 2476 2477 if (fep->phy_node) { 2478 phy_dev = of_phy_connect(ndev, fep->phy_node, 2479 &fec_enet_adjust_link, 0, 2480 fep->phy_interface); 2481 if (!phy_dev) { 2482 netdev_err(ndev, "Unable to connect to phy\n"); 2483 return -ENODEV; 2484 } 2485 } else { 2486 /* check for attached phy */ 2487 phy_dev = phy_find_first(fep->mii_bus); 2488 if (fep->dev_id && phy_dev) 2489 phy_dev = phy_find_next(fep->mii_bus, phy_dev); 2490 2491 if (!phy_dev) { 2492 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2493 phy_dev = fixed_phy_register_100fd(); 2494 if (IS_ERR(phy_dev)) { 2495 netdev_err(ndev, "could not register fixed PHY\n"); 2496 return PTR_ERR(phy_dev); 2497 } 2498 } 2499 2500 ret = phy_connect_direct(ndev, phy_dev, &fec_enet_adjust_link, 2501 fep->phy_interface); 2502 if (ret) { 2503 if (phy_is_pseudo_fixed_link(phy_dev)) 2504 fixed_phy_unregister(phy_dev); 2505 netdev_err(ndev, "could not attach to PHY\n"); 2506 return ret; 2507 } 2508 2509 } 2510 2511 /* mask with MAC supported features */ 2512 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2513 phy_set_max_speed(phy_dev, 1000); 2514 phy_remove_link_mode(phy_dev, 2515 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2516 phy_support_sym_pause(phy_dev); 2517 } 2518 else 2519 phy_set_max_speed(phy_dev, 100); 2520 2521 if (fep->quirks & FEC_QUIRK_HAS_EEE) 2522 phy_support_eee(phy_dev); 2523 2524 fep->link = 0; 2525 fep->full_duplex = 0; 2526 2527 phy_attached_info(phy_dev); 2528 2529 return 0; 2530} 2531 2532static int fec_enet_mii_init(struct platform_device *pdev) 2533{ 2534 static struct mii_bus *fec0_mii_bus; 2535 struct net_device *ndev = platform_get_drvdata(pdev); 2536 struct fec_enet_private *fep = netdev_priv(ndev); 2537 bool suppress_preamble = false; 2538 struct phy_device *phydev; 2539 struct device_node *node; 2540 int err = -ENXIO; 2541 u32 mii_speed, holdtime; 2542 u32 bus_freq; 2543 2544 /* 2545 * The i.MX28 dual fec interfaces are not equal. 2546 * Here are the differences: 2547 * 2548 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2549 * - fec0 acts as the 1588 time master while fec1 is slave 2550 * - external phys can only be configured by fec0 2551 * 2552 * That is to say fec1 can not work independently. It only works 2553 * when fec0 is working. The reason behind this design is that the 2554 * second interface is added primarily for Switch mode. 2555 * 2556 * Because of the last point above, both phys are attached on fec0 2557 * mdio interface in board design, and need to be configured by 2558 * fec0 mii_bus. 2559 */ 2560 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2561 /* fec1 uses fec0 mii_bus */ 2562 if (mii_cnt && fec0_mii_bus) { 2563 fep->mii_bus = fec0_mii_bus; 2564 mii_cnt++; 2565 return 0; 2566 } 2567 return -ENOENT; 2568 } 2569 2570 bus_freq = 2500000; /* 2.5MHz by default */ 2571 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2572 if (node) { 2573 of_property_read_u32(node, "clock-frequency", &bus_freq); 2574 suppress_preamble = of_property_read_bool(node, 2575 "suppress-preamble"); 2576 } 2577 2578 /* 2579 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2580 * 2581 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2582 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2583 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2584 * document. 2585 */ 2586 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2587 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2588 mii_speed--; 2589 if (mii_speed > 63) { 2590 dev_err(&pdev->dev, 2591 "fec clock (%lu) too fast to get right mii speed\n", 2592 clk_get_rate(fep->clk_ipg)); 2593 err = -EINVAL; 2594 goto err_out; 2595 } 2596 2597 /* 2598 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2599 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2600 * versions are RAZ there, so just ignore the difference and write the 2601 * register always. 2602 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2603 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2604 * output. 2605 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2606 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2607 * holdtime cannot result in a value greater than 3. 2608 */ 2609 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2610 2611 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2612 2613 if (suppress_preamble) 2614 fep->phy_speed |= BIT(7); 2615 2616 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2617 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2618 * MII event generation condition: 2619 * - writing MSCR: 2620 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2621 * mscr_reg_data_in[7:0] != 0 2622 * - writing MMFR: 2623 * - mscr[7:0]_not_zero 2624 */ 2625 writel(0, fep->hwp + FEC_MII_DATA); 2626 } 2627 2628 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2629 2630 /* Clear any pending transaction complete indication */ 2631 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2632 2633 fep->mii_bus = mdiobus_alloc(); 2634 if (fep->mii_bus == NULL) { 2635 err = -ENOMEM; 2636 goto err_out; 2637 } 2638 2639 fep->mii_bus->name = "fec_enet_mii_bus"; 2640 fep->mii_bus->read = fec_enet_mdio_read_c22; 2641 fep->mii_bus->write = fec_enet_mdio_write_c22; 2642 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) { 2643 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45; 2644 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45; 2645 } 2646 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2647 pdev->name, fep->dev_id + 1); 2648 fep->mii_bus->priv = fep; 2649 fep->mii_bus->parent = &pdev->dev; 2650 2651 err = of_mdiobus_register(fep->mii_bus, node); 2652 if (err) 2653 goto err_out_free_mdiobus; 2654 of_node_put(node); 2655 2656 /* find all the PHY devices on the bus and set mac_managed_pm to true */ 2657 mdiobus_for_each_phy(fep->mii_bus, phydev) 2658 phydev->mac_managed_pm = true; 2659 2660 mii_cnt++; 2661 2662 /* save fec0 mii_bus */ 2663 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2664 fec0_mii_bus = fep->mii_bus; 2665 2666 return 0; 2667 2668err_out_free_mdiobus: 2669 mdiobus_free(fep->mii_bus); 2670err_out: 2671 of_node_put(node); 2672 return err; 2673} 2674 2675static void fec_enet_mii_remove(struct fec_enet_private *fep) 2676{ 2677 if (--mii_cnt == 0) { 2678 mdiobus_unregister(fep->mii_bus); 2679 mdiobus_free(fep->mii_bus); 2680 } 2681} 2682 2683static void fec_enet_get_drvinfo(struct net_device *ndev, 2684 struct ethtool_drvinfo *info) 2685{ 2686 struct fec_enet_private *fep = netdev_priv(ndev); 2687 2688 strscpy(info->driver, fep->pdev->dev.driver->name, 2689 sizeof(info->driver)); 2690 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2691} 2692 2693static int fec_enet_get_regs_len(struct net_device *ndev) 2694{ 2695 struct fec_enet_private *fep = netdev_priv(ndev); 2696 struct resource *r; 2697 int s = 0; 2698 2699 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2700 if (r) 2701 s = resource_size(r); 2702 2703 return s; 2704} 2705 2706/* List of registers that can be safety be read to dump them with ethtool */ 2707#if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST) 2708static __u32 fec_enet_register_version = 2; 2709static u32 fec_enet_register_offset[] = { 2710 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2711 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2712 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2713 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2714 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2715 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2716 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2717 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2718 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2719 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2720 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2721 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2722 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2723 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2724 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2725 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2726 RMON_T_P_GTE2048, RMON_T_OCTETS, 2727 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2728 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2729 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2730 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2731 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2732 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2733 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2734 RMON_R_P_GTE2048, RMON_R_OCTETS, 2735 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2736 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2737}; 2738/* for i.MX6ul */ 2739static u32 fec_enet_register_offset_6ul[] = { 2740 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2741 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2742 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2743 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2744 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2745 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2746 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2747 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2748 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2749 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2750 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2751 RMON_T_P_GTE2048, RMON_T_OCTETS, 2752 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2753 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2754 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2755 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2756 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2757 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2758 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2759 RMON_R_P_GTE2048, RMON_R_OCTETS, 2760 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2761 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2762}; 2763#else 2764static __u32 fec_enet_register_version = 1; 2765static u32 fec_enet_register_offset[] = { 2766 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2767 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2768 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2769 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2770 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2771 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2772 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2773 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2774 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2775}; 2776#endif 2777 2778static void fec_enet_get_regs(struct net_device *ndev, 2779 struct ethtool_regs *regs, void *regbuf) 2780{ 2781 u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2782 struct fec_enet_private *fep = netdev_priv(ndev); 2783 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2784 u32 *reg_list = fec_enet_register_offset; 2785 struct device *dev = &fep->pdev->dev; 2786 u32 *buf = (u32 *)regbuf; 2787 u32 i, off; 2788 int ret; 2789 2790#if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST) 2791 if (of_machine_is_compatible("fsl,imx6ul")) { 2792 reg_list = fec_enet_register_offset_6ul; 2793 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2794 } 2795#endif 2796 2797 ret = pm_runtime_resume_and_get(dev); 2798 if (ret < 0) 2799 return; 2800 2801 regs->version = fec_enet_register_version; 2802 2803 memset(buf, 0, regs->len); 2804 2805 for (i = 0; i < reg_cnt; i++) { 2806 off = reg_list[i]; 2807 2808 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2809 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2810 continue; 2811 2812 off >>= 2; 2813 buf[off] = readl(&theregs[off]); 2814 } 2815 2816 pm_runtime_put_autosuspend(dev); 2817} 2818 2819static int fec_enet_get_ts_info(struct net_device *ndev, 2820 struct kernel_ethtool_ts_info *info) 2821{ 2822 struct fec_enet_private *fep = netdev_priv(ndev); 2823 2824 if (fep->bufdesc_ex) { 2825 2826 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2827 SOF_TIMESTAMPING_TX_HARDWARE | 2828 SOF_TIMESTAMPING_RX_HARDWARE | 2829 SOF_TIMESTAMPING_RAW_HARDWARE; 2830 if (fep->ptp_clock) 2831 info->phc_index = ptp_clock_index(fep->ptp_clock); 2832 2833 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2834 (1 << HWTSTAMP_TX_ON); 2835 2836 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2837 (1 << HWTSTAMP_FILTER_ALL); 2838 return 0; 2839 } else { 2840 return ethtool_op_get_ts_info(ndev, info); 2841 } 2842} 2843 2844#if !defined(CONFIG_M5272) 2845 2846static void fec_enet_get_pauseparam(struct net_device *ndev, 2847 struct ethtool_pauseparam *pause) 2848{ 2849 struct fec_enet_private *fep = netdev_priv(ndev); 2850 2851 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2852 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2853 pause->rx_pause = pause->tx_pause; 2854} 2855 2856static int fec_enet_set_pauseparam(struct net_device *ndev, 2857 struct ethtool_pauseparam *pause) 2858{ 2859 struct fec_enet_private *fep = netdev_priv(ndev); 2860 2861 if (!ndev->phydev) 2862 return -ENODEV; 2863 2864 if (pause->tx_pause != pause->rx_pause) { 2865 netdev_info(ndev, 2866 "hardware only support enable/disable both tx and rx"); 2867 return -EINVAL; 2868 } 2869 2870 fep->pause_flag = 0; 2871 2872 /* tx pause must be same as rx pause */ 2873 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2874 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2875 2876 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2877 pause->autoneg); 2878 2879 if (pause->autoneg) { 2880 if (netif_running(ndev)) 2881 fec_stop(ndev); 2882 phy_start_aneg(ndev->phydev); 2883 } 2884 if (netif_running(ndev)) { 2885 napi_disable(&fep->napi); 2886 netif_tx_lock_bh(ndev); 2887 fec_restart(ndev); 2888 netif_tx_wake_all_queues(ndev); 2889 netif_tx_unlock_bh(ndev); 2890 napi_enable(&fep->napi); 2891 } 2892 2893 return 0; 2894} 2895 2896static const struct fec_stat { 2897 char name[ETH_GSTRING_LEN]; 2898 u16 offset; 2899} fec_stats[] = { 2900 /* RMON TX */ 2901 { "tx_dropped", RMON_T_DROP }, 2902 { "tx_packets", RMON_T_PACKETS }, 2903 { "tx_broadcast", RMON_T_BC_PKT }, 2904 { "tx_multicast", RMON_T_MC_PKT }, 2905 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2906 { "tx_undersize", RMON_T_UNDERSIZE }, 2907 { "tx_oversize", RMON_T_OVERSIZE }, 2908 { "tx_fragment", RMON_T_FRAG }, 2909 { "tx_jabber", RMON_T_JAB }, 2910 { "tx_collision", RMON_T_COL }, 2911 { "tx_64byte", RMON_T_P64 }, 2912 { "tx_65to127byte", RMON_T_P65TO127 }, 2913 { "tx_128to255byte", RMON_T_P128TO255 }, 2914 { "tx_256to511byte", RMON_T_P256TO511 }, 2915 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2916 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2917 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2918 { "tx_octets", RMON_T_OCTETS }, 2919 2920 /* IEEE TX */ 2921 { "IEEE_tx_drop", IEEE_T_DROP }, 2922 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2923 { "IEEE_tx_1col", IEEE_T_1COL }, 2924 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2925 { "IEEE_tx_def", IEEE_T_DEF }, 2926 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2927 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2928 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2929 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2930 { "IEEE_tx_sqe", IEEE_T_SQE }, 2931 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2932 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2933 2934 /* RMON RX */ 2935 { "rx_packets", RMON_R_PACKETS }, 2936 { "rx_broadcast", RMON_R_BC_PKT }, 2937 { "rx_multicast", RMON_R_MC_PKT }, 2938 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2939 { "rx_undersize", RMON_R_UNDERSIZE }, 2940 { "rx_oversize", RMON_R_OVERSIZE }, 2941 { "rx_fragment", RMON_R_FRAG }, 2942 { "rx_jabber", RMON_R_JAB }, 2943 { "rx_64byte", RMON_R_P64 }, 2944 { "rx_65to127byte", RMON_R_P65TO127 }, 2945 { "rx_128to255byte", RMON_R_P128TO255 }, 2946 { "rx_256to511byte", RMON_R_P256TO511 }, 2947 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2948 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2949 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2950 { "rx_octets", RMON_R_OCTETS }, 2951 2952 /* IEEE RX */ 2953 { "IEEE_rx_drop", IEEE_R_DROP }, 2954 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2955 { "IEEE_rx_crc", IEEE_R_CRC }, 2956 { "IEEE_rx_align", IEEE_R_ALIGN }, 2957 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2958 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2959 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2960}; 2961 2962#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2963 2964static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = { 2965 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */ 2966 "rx_xdp_pass", /* RX_XDP_PASS, */ 2967 "rx_xdp_drop", /* RX_XDP_DROP, */ 2968 "rx_xdp_tx", /* RX_XDP_TX, */ 2969 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */ 2970 "tx_xdp_xmit", /* TX_XDP_XMIT, */ 2971 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */ 2972}; 2973 2974static void fec_enet_update_ethtool_stats(struct net_device *dev) 2975{ 2976 struct fec_enet_private *fep = netdev_priv(dev); 2977 int i; 2978 2979 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2980 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2981} 2982 2983static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) 2984{ 2985 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 }; 2986 struct fec_enet_priv_rx_q *rxq; 2987 int i, j; 2988 2989 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 2990 rxq = fep->rx_queue[i]; 2991 2992 for (j = 0; j < XDP_STATS_TOTAL; j++) 2993 xdp_stats[j] += rxq->stats[j]; 2994 } 2995 2996 memcpy(data, xdp_stats, sizeof(xdp_stats)); 2997} 2998 2999static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data) 3000{ 3001#ifdef CONFIG_PAGE_POOL_STATS 3002 struct page_pool_stats stats = {}; 3003 struct fec_enet_priv_rx_q *rxq; 3004 int i; 3005 3006 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3007 rxq = fep->rx_queue[i]; 3008 3009 if (!rxq->page_pool) 3010 continue; 3011 3012 page_pool_get_stats(rxq->page_pool, &stats); 3013 } 3014 3015 page_pool_ethtool_stats_get(data, &stats); 3016#endif 3017} 3018 3019static void fec_enet_get_ethtool_stats(struct net_device *dev, 3020 struct ethtool_stats *stats, u64 *data) 3021{ 3022 struct fec_enet_private *fep = netdev_priv(dev); 3023 3024 if (netif_running(dev)) 3025 fec_enet_update_ethtool_stats(dev); 3026 3027 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 3028 data += FEC_STATS_SIZE / sizeof(u64); 3029 3030 fec_enet_get_xdp_stats(fep, data); 3031 data += XDP_STATS_TOTAL; 3032 3033 fec_enet_page_pool_stats(fep, data); 3034} 3035 3036static void fec_enet_get_strings(struct net_device *netdev, 3037 u32 stringset, u8 *data) 3038{ 3039 int i; 3040 switch (stringset) { 3041 case ETH_SS_STATS: 3042 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { 3043 ethtool_puts(&data, fec_stats[i].name); 3044 } 3045 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) { 3046 ethtool_puts(&data, fec_xdp_stat_strs[i]); 3047 } 3048 page_pool_ethtool_stats_get_strings(data); 3049 3050 break; 3051 case ETH_SS_TEST: 3052 net_selftest_get_strings(data); 3053 break; 3054 } 3055} 3056 3057static int fec_enet_get_sset_count(struct net_device *dev, int sset) 3058{ 3059 int count; 3060 3061 switch (sset) { 3062 case ETH_SS_STATS: 3063 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL; 3064 count += page_pool_ethtool_stats_get_count(); 3065 return count; 3066 3067 case ETH_SS_TEST: 3068 return net_selftest_get_count(); 3069 default: 3070 return -EOPNOTSUPP; 3071 } 3072} 3073 3074static void fec_enet_clear_ethtool_stats(struct net_device *dev) 3075{ 3076 struct fec_enet_private *fep = netdev_priv(dev); 3077 struct fec_enet_priv_rx_q *rxq; 3078 int i, j; 3079 3080 /* Disable MIB statistics counters */ 3081 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 3082 3083 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 3084 writel(0, fep->hwp + fec_stats[i].offset); 3085 3086 for (i = fep->num_rx_queues - 1; i >= 0; i--) { 3087 rxq = fep->rx_queue[i]; 3088 for (j = 0; j < XDP_STATS_TOTAL; j++) 3089 rxq->stats[j] = 0; 3090 } 3091 3092 /* Don't disable MIB statistics counters */ 3093 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 3094} 3095 3096#else /* !defined(CONFIG_M5272) */ 3097#define FEC_STATS_SIZE 0 3098static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 3099{ 3100} 3101 3102static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 3103{ 3104} 3105#endif /* !defined(CONFIG_M5272) */ 3106 3107/* ITR clock source is enet system clock (clk_ahb). 3108 * TCTT unit is cycle_ns * 64 cycle 3109 * So, the ICTT value = X us / (cycle_ns * 64) 3110 */ 3111static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 3112{ 3113 struct fec_enet_private *fep = netdev_priv(ndev); 3114 3115 return us * (fep->itr_clk_rate / 64000) / 1000; 3116} 3117 3118/* Set threshold for interrupt coalescing */ 3119static void fec_enet_itr_coal_set(struct net_device *ndev) 3120{ 3121 struct fec_enet_private *fep = netdev_priv(ndev); 3122 u32 rx_itr = 0, tx_itr = 0; 3123 int rx_ictt, tx_ictt; 3124 3125 rx_ictt = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); 3126 tx_ictt = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); 3127 3128 if (rx_ictt > 0 && fep->rx_pkts_itr > 1) { 3129 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3130 rx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3131 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 3132 rx_itr |= FEC_ITR_ICTT(rx_ictt); 3133 } 3134 3135 if (tx_ictt > 0 && fep->tx_pkts_itr > 1) { 3136 /* Enable with enet system clock as Interrupt Coalescing timer Clock Source */ 3137 tx_itr = FEC_ITR_EN | FEC_ITR_CLK_SEL; 3138 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 3139 tx_itr |= FEC_ITR_ICTT(tx_ictt); 3140 } 3141 3142 writel(tx_itr, fep->hwp + FEC_TXIC0); 3143 writel(rx_itr, fep->hwp + FEC_RXIC0); 3144 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { 3145 writel(tx_itr, fep->hwp + FEC_TXIC1); 3146 writel(rx_itr, fep->hwp + FEC_RXIC1); 3147 writel(tx_itr, fep->hwp + FEC_TXIC2); 3148 writel(rx_itr, fep->hwp + FEC_RXIC2); 3149 } 3150} 3151 3152static int fec_enet_get_coalesce(struct net_device *ndev, 3153 struct ethtool_coalesce *ec, 3154 struct kernel_ethtool_coalesce *kernel_coal, 3155 struct netlink_ext_ack *extack) 3156{ 3157 struct fec_enet_private *fep = netdev_priv(ndev); 3158 3159 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3160 return -EOPNOTSUPP; 3161 3162 ec->rx_coalesce_usecs = fep->rx_time_itr; 3163 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 3164 3165 ec->tx_coalesce_usecs = fep->tx_time_itr; 3166 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 3167 3168 return 0; 3169} 3170 3171static int fec_enet_set_coalesce(struct net_device *ndev, 3172 struct ethtool_coalesce *ec, 3173 struct kernel_ethtool_coalesce *kernel_coal, 3174 struct netlink_ext_ack *extack) 3175{ 3176 struct fec_enet_private *fep = netdev_priv(ndev); 3177 struct device *dev = &fep->pdev->dev; 3178 unsigned int cycle; 3179 3180 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 3181 return -EOPNOTSUPP; 3182 3183 if (ec->rx_max_coalesced_frames > 255) { 3184 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 3185 return -EINVAL; 3186 } 3187 3188 if (ec->tx_max_coalesced_frames > 255) { 3189 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 3190 return -EINVAL; 3191 } 3192 3193 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 3194 if (cycle > 0xFFFF) { 3195 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 3196 return -EINVAL; 3197 } 3198 3199 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 3200 if (cycle > 0xFFFF) { 3201 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 3202 return -EINVAL; 3203 } 3204 3205 fep->rx_time_itr = ec->rx_coalesce_usecs; 3206 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 3207 3208 fep->tx_time_itr = ec->tx_coalesce_usecs; 3209 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 3210 3211 fec_enet_itr_coal_set(ndev); 3212 3213 return 0; 3214} 3215 3216static int 3217fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata) 3218{ 3219 struct fec_enet_private *fep = netdev_priv(ndev); 3220 3221 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3222 return -EOPNOTSUPP; 3223 3224 if (!netif_running(ndev)) 3225 return -ENETDOWN; 3226 3227 return phy_ethtool_get_eee(ndev->phydev, edata); 3228} 3229 3230static int 3231fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata) 3232{ 3233 struct fec_enet_private *fep = netdev_priv(ndev); 3234 3235 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) 3236 return -EOPNOTSUPP; 3237 3238 if (!netif_running(ndev)) 3239 return -ENETDOWN; 3240 3241 return phy_ethtool_set_eee(ndev->phydev, edata); 3242} 3243 3244static void 3245fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3246{ 3247 struct fec_enet_private *fep = netdev_priv(ndev); 3248 3249 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 3250 wol->supported = WAKE_MAGIC; 3251 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 3252 } else { 3253 wol->supported = wol->wolopts = 0; 3254 } 3255} 3256 3257static int 3258fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 3259{ 3260 struct fec_enet_private *fep = netdev_priv(ndev); 3261 3262 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 3263 return -EINVAL; 3264 3265 if (wol->wolopts & ~WAKE_MAGIC) 3266 return -EINVAL; 3267 3268 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 3269 if (device_may_wakeup(&ndev->dev)) 3270 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 3271 else 3272 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 3273 3274 return 0; 3275} 3276 3277static const struct ethtool_ops fec_enet_ethtool_ops = { 3278 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3279 ETHTOOL_COALESCE_MAX_FRAMES, 3280 .get_drvinfo = fec_enet_get_drvinfo, 3281 .get_regs_len = fec_enet_get_regs_len, 3282 .get_regs = fec_enet_get_regs, 3283 .nway_reset = phy_ethtool_nway_reset, 3284 .get_link = ethtool_op_get_link, 3285 .get_coalesce = fec_enet_get_coalesce, 3286 .set_coalesce = fec_enet_set_coalesce, 3287#ifndef CONFIG_M5272 3288 .get_pauseparam = fec_enet_get_pauseparam, 3289 .set_pauseparam = fec_enet_set_pauseparam, 3290 .get_strings = fec_enet_get_strings, 3291 .get_ethtool_stats = fec_enet_get_ethtool_stats, 3292 .get_sset_count = fec_enet_get_sset_count, 3293#endif 3294 .get_ts_info = fec_enet_get_ts_info, 3295 .get_wol = fec_enet_get_wol, 3296 .set_wol = fec_enet_set_wol, 3297 .get_eee = fec_enet_get_eee, 3298 .set_eee = fec_enet_set_eee, 3299 .get_link_ksettings = phy_ethtool_get_link_ksettings, 3300 .set_link_ksettings = phy_ethtool_set_link_ksettings, 3301 .self_test = net_selftest, 3302}; 3303 3304static void fec_enet_free_buffers(struct net_device *ndev) 3305{ 3306 struct fec_enet_private *fep = netdev_priv(ndev); 3307 unsigned int i; 3308 struct fec_enet_priv_tx_q *txq; 3309 struct fec_enet_priv_rx_q *rxq; 3310 unsigned int q; 3311 3312 for (q = 0; q < fep->num_rx_queues; q++) { 3313 rxq = fep->rx_queue[q]; 3314 for (i = 0; i < rxq->bd.ring_size; i++) 3315 page_pool_put_full_page(rxq->page_pool, rxq->rx_buf[i], 3316 false); 3317 3318 for (i = 0; i < XDP_STATS_TOTAL; i++) 3319 rxq->stats[i] = 0; 3320 3321 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 3322 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3323 page_pool_destroy(rxq->page_pool); 3324 rxq->page_pool = NULL; 3325 } 3326 3327 for (q = 0; q < fep->num_tx_queues; q++) { 3328 txq = fep->tx_queue[q]; 3329 for (i = 0; i < txq->bd.ring_size; i++) { 3330 kfree(txq->tx_bounce[i]); 3331 txq->tx_bounce[i] = NULL; 3332 3333 if (!txq->tx_buf[i].buf_p) { 3334 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3335 continue; 3336 } 3337 3338 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) { 3339 dev_kfree_skb(txq->tx_buf[i].buf_p); 3340 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) { 3341 xdp_return_frame(txq->tx_buf[i].buf_p); 3342 } else { 3343 struct page *page = txq->tx_buf[i].buf_p; 3344 3345 page_pool_put_page(pp_page_to_nmdesc(page)->pp, 3346 page, 0, false); 3347 } 3348 3349 txq->tx_buf[i].buf_p = NULL; 3350 txq->tx_buf[i].type = FEC_TXBUF_T_SKB; 3351 } 3352 } 3353} 3354 3355static void fec_enet_free_queue(struct net_device *ndev) 3356{ 3357 struct fec_enet_private *fep = netdev_priv(ndev); 3358 int i; 3359 struct fec_enet_priv_tx_q *txq; 3360 3361 for (i = 0; i < fep->num_tx_queues; i++) 3362 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 3363 txq = fep->tx_queue[i]; 3364 fec_dma_free(&fep->pdev->dev, 3365 txq->bd.ring_size * TSO_HEADER_SIZE, 3366 txq->tso_hdrs, txq->tso_hdrs_dma); 3367 } 3368 3369 for (i = 0; i < fep->num_rx_queues; i++) 3370 kfree(fep->rx_queue[i]); 3371 for (i = 0; i < fep->num_tx_queues; i++) 3372 kfree(fep->tx_queue[i]); 3373} 3374 3375static int fec_enet_alloc_queue(struct net_device *ndev) 3376{ 3377 struct fec_enet_private *fep = netdev_priv(ndev); 3378 int i; 3379 int ret = 0; 3380 struct fec_enet_priv_tx_q *txq; 3381 3382 for (i = 0; i < fep->num_tx_queues; i++) { 3383 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 3384 if (!txq) { 3385 ret = -ENOMEM; 3386 goto alloc_failed; 3387 } 3388 3389 fep->tx_queue[i] = txq; 3390 txq->bd.ring_size = TX_RING_SIZE; 3391 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 3392 3393 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 3394 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS; 3395 3396 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev, 3397 txq->bd.ring_size * TSO_HEADER_SIZE, 3398 &txq->tso_hdrs_dma, GFP_KERNEL); 3399 if (!txq->tso_hdrs) { 3400 ret = -ENOMEM; 3401 goto alloc_failed; 3402 } 3403 } 3404 3405 for (i = 0; i < fep->num_rx_queues; i++) { 3406 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 3407 GFP_KERNEL); 3408 if (!fep->rx_queue[i]) { 3409 ret = -ENOMEM; 3410 goto alloc_failed; 3411 } 3412 3413 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 3414 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 3415 } 3416 return ret; 3417 3418alloc_failed: 3419 fec_enet_free_queue(ndev); 3420 return ret; 3421} 3422 3423static int 3424fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 3425{ 3426 struct fec_enet_private *fep = netdev_priv(ndev); 3427 struct fec_enet_priv_rx_q *rxq; 3428 dma_addr_t phys_addr; 3429 struct bufdesc *bdp; 3430 struct page *page; 3431 int i, err; 3432 3433 rxq = fep->rx_queue[queue]; 3434 bdp = rxq->bd.base; 3435 3436 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size); 3437 if (err < 0) { 3438 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err); 3439 return err; 3440 } 3441 3442 /* Some platforms require the RX buffer must be 64 bytes alignment. 3443 * Some platforms require 16 bytes alignment. And some platforms 3444 * require 4 bytes alignment. But since the page pool have been 3445 * introduced into the driver, the address of RX buffer is always 3446 * the page address plus FEC_ENET_XDP_HEADROOM, and 3447 * FEC_ENET_XDP_HEADROOM is 256 bytes. Therefore, this address can 3448 * satisfy all platforms. To prevent future modifications to 3449 * FEC_ENET_XDP_HEADROOM from ignoring this hardware limitation, a 3450 * BUILD_BUG_ON() test has been added, which ensures that 3451 * FEC_ENET_XDP_HEADROOM provides the required alignment. 3452 */ 3453 BUILD_BUG_ON(FEC_ENET_XDP_HEADROOM & 0x3f); 3454 3455 for (i = 0; i < rxq->bd.ring_size; i++) { 3456 page = page_pool_dev_alloc_pages(rxq->page_pool); 3457 if (!page) 3458 goto err_alloc; 3459 3460 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM; 3461 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr); 3462 3463 rxq->rx_buf[i] = page; 3464 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 3465 3466 if (fep->bufdesc_ex) { 3467 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3468 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 3469 } 3470 3471 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 3472 } 3473 3474 /* Set the last buffer to wrap. */ 3475 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 3476 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_RX_WRAP); 3477 return 0; 3478 3479 err_alloc: 3480 fec_enet_free_buffers(ndev); 3481 return -ENOMEM; 3482} 3483 3484static int 3485fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 3486{ 3487 struct fec_enet_private *fep = netdev_priv(ndev); 3488 unsigned int i; 3489 struct bufdesc *bdp; 3490 struct fec_enet_priv_tx_q *txq; 3491 3492 txq = fep->tx_queue[queue]; 3493 bdp = txq->bd.base; 3494 for (i = 0; i < txq->bd.ring_size; i++) { 3495 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 3496 if (!txq->tx_bounce[i]) 3497 goto err_alloc; 3498 3499 bdp->cbd_sc = cpu_to_fec16(0); 3500 bdp->cbd_bufaddr = cpu_to_fec32(0); 3501 3502 if (fep->bufdesc_ex) { 3503 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3504 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 3505 } 3506 3507 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3508 } 3509 3510 /* Set the last buffer to wrap. */ 3511 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 3512 bdp->cbd_sc |= cpu_to_fec16(BD_ENET_TX_WRAP); 3513 3514 return 0; 3515 3516 err_alloc: 3517 fec_enet_free_buffers(ndev); 3518 return -ENOMEM; 3519} 3520 3521static int fec_enet_alloc_buffers(struct net_device *ndev) 3522{ 3523 struct fec_enet_private *fep = netdev_priv(ndev); 3524 unsigned int i; 3525 3526 for (i = 0; i < fep->num_rx_queues; i++) 3527 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3528 return -ENOMEM; 3529 3530 for (i = 0; i < fep->num_tx_queues; i++) 3531 if (fec_enet_alloc_txq_buffers(ndev, i)) 3532 return -ENOMEM; 3533 return 0; 3534} 3535 3536static int 3537fec_enet_open(struct net_device *ndev) 3538{ 3539 struct fec_enet_private *fep = netdev_priv(ndev); 3540 int ret; 3541 bool reset_again; 3542 3543 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3544 if (ret < 0) 3545 return ret; 3546 3547 pinctrl_pm_select_default_state(&fep->pdev->dev); 3548 ret = fec_enet_clk_enable(ndev, true); 3549 if (ret) 3550 goto clk_enable; 3551 3552 /* During the first fec_enet_open call the PHY isn't probed at this 3553 * point. Therefore the phy_reset_after_clk_enable() call within 3554 * fec_enet_clk_enable() fails. As we need this reset in order to be 3555 * sure the PHY is working correctly we check if we need to reset again 3556 * later when the PHY is probed 3557 */ 3558 if (ndev->phydev && ndev->phydev->drv) 3559 reset_again = false; 3560 else 3561 reset_again = true; 3562 3563 /* I should reset the ring buffers here, but I don't yet know 3564 * a simple way to do that. 3565 */ 3566 3567 ret = fec_enet_alloc_buffers(ndev); 3568 if (ret) 3569 goto err_enet_alloc; 3570 3571 /* Init MAC prior to mii bus probe */ 3572 fec_restart(ndev); 3573 3574 /* Call phy_reset_after_clk_enable() again if it failed during 3575 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3576 */ 3577 if (reset_again) 3578 fec_enet_phy_reset_after_clk_enable(ndev); 3579 3580 /* Probe and connect to PHY when open the interface */ 3581 ret = fec_enet_mii_probe(ndev); 3582 if (ret) 3583 goto err_enet_mii_probe; 3584 3585 if (fep->quirks & FEC_QUIRK_ERR006687) 3586 imx6q_cpuidle_fec_irqs_used(); 3587 3588 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3589 cpu_latency_qos_add_request(&fep->pm_qos_req, 0); 3590 3591 napi_enable(&fep->napi); 3592 phy_start(ndev->phydev); 3593 netif_tx_start_all_queues(ndev); 3594 3595 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3596 FEC_WOL_FLAG_ENABLE); 3597 3598 return 0; 3599 3600err_enet_mii_probe: 3601 fec_enet_free_buffers(ndev); 3602err_enet_alloc: 3603 fec_enet_clk_enable(ndev, false); 3604clk_enable: 3605 pm_runtime_put_autosuspend(&fep->pdev->dev); 3606 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3607 return ret; 3608} 3609 3610static int 3611fec_enet_close(struct net_device *ndev) 3612{ 3613 struct fec_enet_private *fep = netdev_priv(ndev); 3614 struct phy_device *phy_dev = ndev->phydev; 3615 3616 phy_stop(phy_dev); 3617 3618 if (netif_device_present(ndev)) { 3619 napi_disable(&fep->napi); 3620 netif_tx_disable(ndev); 3621 fec_stop(ndev); 3622 } 3623 3624 phy_disconnect(phy_dev); 3625 3626 if (!fep->phy_node && phy_is_pseudo_fixed_link(phy_dev)) 3627 fixed_phy_unregister(phy_dev); 3628 3629 if (fep->quirks & FEC_QUIRK_ERR006687) 3630 imx6q_cpuidle_fec_irqs_unused(); 3631 3632 fec_enet_update_ethtool_stats(ndev); 3633 3634 fec_enet_clk_enable(ndev, false); 3635 if (fep->quirks & FEC_QUIRK_HAS_PMQOS) 3636 cpu_latency_qos_remove_request(&fep->pm_qos_req); 3637 3638 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3639 pm_runtime_put_autosuspend(&fep->pdev->dev); 3640 3641 fec_enet_free_buffers(ndev); 3642 3643 return 0; 3644} 3645 3646/* Set or clear the multicast filter for this adaptor. 3647 * Skeleton taken from sunlance driver. 3648 * The CPM Ethernet implementation allows Multicast as well as individual 3649 * MAC address filtering. Some of the drivers check to make sure it is 3650 * a group multicast address, and discard those that are not. I guess I 3651 * will do the same for now, but just remove the test if you want 3652 * individual filtering as well (do the upper net layers want or support 3653 * this kind of feature?). 3654 */ 3655 3656#define FEC_HASH_BITS 6 /* #bits in hash */ 3657 3658static void set_multicast_list(struct net_device *ndev) 3659{ 3660 struct fec_enet_private *fep = netdev_priv(ndev); 3661 struct netdev_hw_addr *ha; 3662 unsigned int crc, tmp; 3663 unsigned char hash; 3664 unsigned int hash_high = 0, hash_low = 0; 3665 3666 if (ndev->flags & IFF_PROMISC) { 3667 tmp = readl(fep->hwp + FEC_R_CNTRL); 3668 tmp |= 0x8; 3669 writel(tmp, fep->hwp + FEC_R_CNTRL); 3670 return; 3671 } 3672 3673 tmp = readl(fep->hwp + FEC_R_CNTRL); 3674 tmp &= ~0x8; 3675 writel(tmp, fep->hwp + FEC_R_CNTRL); 3676 3677 if (ndev->flags & IFF_ALLMULTI) { 3678 /* Catch all multicast addresses, so set the 3679 * filter to all 1's 3680 */ 3681 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3682 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3683 3684 return; 3685 } 3686 3687 /* Add the addresses in hash register */ 3688 netdev_for_each_mc_addr(ha, ndev) { 3689 /* calculate crc32 value of mac address */ 3690 crc = ether_crc_le(ndev->addr_len, ha->addr); 3691 3692 /* only upper 6 bits (FEC_HASH_BITS) are used 3693 * which point to specific bit in the hash registers 3694 */ 3695 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3696 3697 if (hash > 31) 3698 hash_high |= 1 << (hash - 32); 3699 else 3700 hash_low |= 1 << hash; 3701 } 3702 3703 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3704 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3705} 3706 3707/* Set a MAC change in hardware. */ 3708static int 3709fec_set_mac_address(struct net_device *ndev, void *p) 3710{ 3711 struct sockaddr *addr = p; 3712 3713 if (addr) { 3714 if (!is_valid_ether_addr(addr->sa_data)) 3715 return -EADDRNOTAVAIL; 3716 eth_hw_addr_set(ndev, addr->sa_data); 3717 } 3718 3719 /* Add netif status check here to avoid system hang in below case: 3720 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3721 * After ethx down, fec all clocks are gated off and then register 3722 * access causes system hang. 3723 */ 3724 if (!netif_running(ndev)) 3725 return 0; 3726 3727 fec_set_hw_mac_addr(ndev); 3728 3729 return 0; 3730} 3731 3732static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3733 netdev_features_t features) 3734{ 3735 struct fec_enet_private *fep = netdev_priv(netdev); 3736 netdev_features_t changed = features ^ netdev->features; 3737 3738 netdev->features = features; 3739 3740 /* Receive checksum has been changed */ 3741 if (changed & NETIF_F_RXCSUM) { 3742 if (features & NETIF_F_RXCSUM) 3743 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3744 else 3745 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3746 } 3747} 3748 3749static int fec_set_features(struct net_device *netdev, 3750 netdev_features_t features) 3751{ 3752 struct fec_enet_private *fep = netdev_priv(netdev); 3753 netdev_features_t changed = features ^ netdev->features; 3754 3755 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3756 napi_disable(&fep->napi); 3757 netif_tx_lock_bh(netdev); 3758 fec_stop(netdev); 3759 fec_enet_set_netdev_features(netdev, features); 3760 fec_restart(netdev); 3761 netif_tx_wake_all_queues(netdev); 3762 netif_tx_unlock_bh(netdev); 3763 napi_enable(&fep->napi); 3764 } else { 3765 fec_enet_set_netdev_features(netdev, features); 3766 } 3767 3768 return 0; 3769} 3770 3771static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3772 struct net_device *sb_dev) 3773{ 3774 struct fec_enet_private *fep = netdev_priv(ndev); 3775 u16 vlan_tag = 0; 3776 3777 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3778 return netdev_pick_tx(ndev, skb, NULL); 3779 3780 /* VLAN is present in the payload.*/ 3781 if (eth_type_vlan(skb->protocol)) { 3782 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb); 3783 3784 vlan_tag = ntohs(vhdr->h_vlan_TCI); 3785 /* VLAN is present in the skb but not yet pushed in the payload.*/ 3786 } else if (skb_vlan_tag_present(skb)) { 3787 vlan_tag = skb->vlan_tci; 3788 } else { 3789 return vlan_tag; 3790 } 3791 3792 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3793} 3794 3795static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf) 3796{ 3797 struct fec_enet_private *fep = netdev_priv(dev); 3798 bool is_run = netif_running(dev); 3799 struct bpf_prog *old_prog; 3800 3801 switch (bpf->command) { 3802 case XDP_SETUP_PROG: 3803 /* No need to support the SoCs that require to 3804 * do the frame swap because the performance wouldn't be 3805 * better than the skb mode. 3806 */ 3807 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 3808 return -EOPNOTSUPP; 3809 3810 if (!bpf->prog) 3811 xdp_features_clear_redirect_target(dev); 3812 3813 if (is_run) { 3814 napi_disable(&fep->napi); 3815 netif_tx_disable(dev); 3816 } 3817 3818 old_prog = xchg(&fep->xdp_prog, bpf->prog); 3819 if (old_prog) 3820 bpf_prog_put(old_prog); 3821 3822 fec_restart(dev); 3823 3824 if (is_run) { 3825 napi_enable(&fep->napi); 3826 netif_tx_start_all_queues(dev); 3827 } 3828 3829 if (bpf->prog) 3830 xdp_features_set_redirect_target(dev, false); 3831 3832 return 0; 3833 3834 case XDP_SETUP_XSK_POOL: 3835 return -EOPNOTSUPP; 3836 3837 default: 3838 return -EOPNOTSUPP; 3839 } 3840} 3841 3842static int 3843fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index) 3844{ 3845 if (unlikely(index < 0)) 3846 return 0; 3847 3848 return (index % fep->num_tx_queues); 3849} 3850 3851static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep, 3852 struct fec_enet_priv_tx_q *txq, 3853 void *frame, u32 dma_sync_len, 3854 bool ndo_xmit) 3855{ 3856 unsigned int index, status, estatus; 3857 struct bufdesc *bdp; 3858 dma_addr_t dma_addr; 3859 int entries_free; 3860 u16 frame_len; 3861 3862 entries_free = fec_enet_get_free_txdesc_num(txq); 3863 if (entries_free < MAX_SKB_FRAGS + 1) { 3864 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n"); 3865 return -EBUSY; 3866 } 3867 3868 /* Fill in a Tx ring entry */ 3869 bdp = txq->bd.cur; 3870 status = fec16_to_cpu(bdp->cbd_sc); 3871 status &= ~BD_ENET_TX_STATS; 3872 3873 index = fec_enet_get_bd_index(bdp, &txq->bd); 3874 3875 if (ndo_xmit) { 3876 struct xdp_frame *xdpf = frame; 3877 3878 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data, 3879 xdpf->len, DMA_TO_DEVICE); 3880 if (dma_mapping_error(&fep->pdev->dev, dma_addr)) 3881 return -ENOMEM; 3882 3883 frame_len = xdpf->len; 3884 txq->tx_buf[index].buf_p = xdpf; 3885 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO; 3886 } else { 3887 struct xdp_buff *xdpb = frame; 3888 struct page *page; 3889 3890 page = virt_to_page(xdpb->data); 3891 dma_addr = page_pool_get_dma_addr(page) + 3892 (xdpb->data - xdpb->data_hard_start); 3893 dma_sync_single_for_device(&fep->pdev->dev, dma_addr, 3894 dma_sync_len, DMA_BIDIRECTIONAL); 3895 frame_len = xdpb->data_end - xdpb->data; 3896 txq->tx_buf[index].buf_p = page; 3897 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX; 3898 } 3899 3900 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 3901 if (fep->bufdesc_ex) 3902 estatus = BD_ENET_TX_INT; 3903 3904 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr); 3905 bdp->cbd_datlen = cpu_to_fec16(frame_len); 3906 3907 if (fep->bufdesc_ex) { 3908 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 3909 3910 if (fep->quirks & FEC_QUIRK_HAS_AVB) 3911 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 3912 3913 ebdp->cbd_bdu = 0; 3914 ebdp->cbd_esc = cpu_to_fec32(estatus); 3915 } 3916 3917 /* Make sure the updates to rest of the descriptor are performed before 3918 * transferring ownership. 3919 */ 3920 dma_wmb(); 3921 3922 /* Send it on its way. Tell FEC it's ready, interrupt when done, 3923 * it's the last BD of the frame, and to put the CRC on the end. 3924 */ 3925 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 3926 bdp->cbd_sc = cpu_to_fec16(status); 3927 3928 /* If this was the last BD in the ring, start at the beginning again. */ 3929 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 3930 3931 /* Make sure the update to bdp are performed before txq->bd.cur. */ 3932 dma_wmb(); 3933 3934 txq->bd.cur = bdp; 3935 3936 /* Trigger transmission start */ 3937 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 3938 !readl(txq->bd.reg_desc_active) || 3939 !readl(txq->bd.reg_desc_active) || 3940 !readl(txq->bd.reg_desc_active) || 3941 !readl(txq->bd.reg_desc_active)) 3942 writel(0, txq->bd.reg_desc_active); 3943 3944 return 0; 3945} 3946 3947static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep, 3948 int cpu, struct xdp_buff *xdp, 3949 u32 dma_sync_len) 3950{ 3951 struct fec_enet_priv_tx_q *txq; 3952 struct netdev_queue *nq; 3953 int queue, ret; 3954 3955 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3956 txq = fep->tx_queue[queue]; 3957 nq = netdev_get_tx_queue(fep->netdev, queue); 3958 3959 __netif_tx_lock(nq, cpu); 3960 3961 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3962 txq_trans_cond_update(nq); 3963 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false); 3964 3965 __netif_tx_unlock(nq); 3966 3967 return ret; 3968} 3969 3970static int fec_enet_xdp_xmit(struct net_device *dev, 3971 int num_frames, 3972 struct xdp_frame **frames, 3973 u32 flags) 3974{ 3975 struct fec_enet_private *fep = netdev_priv(dev); 3976 struct fec_enet_priv_tx_q *txq; 3977 int cpu = smp_processor_id(); 3978 unsigned int sent_frames = 0; 3979 struct netdev_queue *nq; 3980 unsigned int queue; 3981 int i; 3982 3983 queue = fec_enet_xdp_get_tx_queue(fep, cpu); 3984 txq = fep->tx_queue[queue]; 3985 nq = netdev_get_tx_queue(fep->netdev, queue); 3986 3987 __netif_tx_lock(nq, cpu); 3988 3989 /* Avoid tx timeout as XDP shares the queue with kernel stack */ 3990 txq_trans_cond_update(nq); 3991 for (i = 0; i < num_frames; i++) { 3992 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0) 3993 break; 3994 sent_frames++; 3995 } 3996 3997 __netif_tx_unlock(nq); 3998 3999 return sent_frames; 4000} 4001 4002static int fec_hwtstamp_get(struct net_device *ndev, 4003 struct kernel_hwtstamp_config *config) 4004{ 4005 struct fec_enet_private *fep = netdev_priv(ndev); 4006 4007 if (!netif_running(ndev)) 4008 return -EINVAL; 4009 4010 if (!fep->bufdesc_ex) 4011 return -EOPNOTSUPP; 4012 4013 fec_ptp_get(ndev, config); 4014 4015 return 0; 4016} 4017 4018static int fec_hwtstamp_set(struct net_device *ndev, 4019 struct kernel_hwtstamp_config *config, 4020 struct netlink_ext_ack *extack) 4021{ 4022 struct fec_enet_private *fep = netdev_priv(ndev); 4023 4024 if (!netif_running(ndev)) 4025 return -EINVAL; 4026 4027 if (!fep->bufdesc_ex) 4028 return -EOPNOTSUPP; 4029 4030 return fec_ptp_set(ndev, config, extack); 4031} 4032 4033static int fec_change_mtu(struct net_device *ndev, int new_mtu) 4034{ 4035 struct fec_enet_private *fep = netdev_priv(ndev); 4036 int order; 4037 4038 if (netif_running(ndev)) 4039 return -EBUSY; 4040 4041 order = get_order(new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN 4042 + FEC_DRV_RESERVE_SPACE); 4043 fep->rx_frame_size = (PAGE_SIZE << order) - FEC_DRV_RESERVE_SPACE; 4044 fep->pagepool_order = order; 4045 WRITE_ONCE(ndev->mtu, new_mtu); 4046 4047 return 0; 4048} 4049 4050static const struct net_device_ops fec_netdev_ops = { 4051 .ndo_open = fec_enet_open, 4052 .ndo_stop = fec_enet_close, 4053 .ndo_start_xmit = fec_enet_start_xmit, 4054 .ndo_select_queue = fec_enet_select_queue, 4055 .ndo_set_rx_mode = set_multicast_list, 4056 .ndo_validate_addr = eth_validate_addr, 4057 .ndo_tx_timeout = fec_timeout, 4058 .ndo_set_mac_address = fec_set_mac_address, 4059 .ndo_change_mtu = fec_change_mtu, 4060 .ndo_eth_ioctl = phy_do_ioctl_running, 4061 .ndo_set_features = fec_set_features, 4062 .ndo_bpf = fec_enet_bpf, 4063 .ndo_xdp_xmit = fec_enet_xdp_xmit, 4064 .ndo_hwtstamp_get = fec_hwtstamp_get, 4065 .ndo_hwtstamp_set = fec_hwtstamp_set, 4066}; 4067 4068static const unsigned short offset_des_active_rxq[] = { 4069 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 4070}; 4071 4072static const unsigned short offset_des_active_txq[] = { 4073 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 4074}; 4075 4076 /* 4077 * XXX: We need to clean up on failure exits here. 4078 * 4079 */ 4080static int fec_enet_init(struct net_device *ndev) 4081{ 4082 struct fec_enet_private *fep = netdev_priv(ndev); 4083 struct bufdesc *cbd_base; 4084 dma_addr_t bd_dma; 4085 int bd_size; 4086 unsigned int i; 4087 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 4088 sizeof(struct bufdesc); 4089 unsigned dsize_log2 = __fls(dsize); 4090 int ret; 4091 4092 WARN_ON(dsize != (1 << dsize_log2)); 4093#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 4094 fep->tx_align = 0xf; 4095#else 4096 fep->tx_align = 0x3; 4097#endif 4098 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4099 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT; 4100 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT; 4101 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT; 4102 4103 /* Check mask of the streaming and coherent API */ 4104 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 4105 if (ret < 0) { 4106 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 4107 return ret; 4108 } 4109 4110 ret = fec_enet_alloc_queue(ndev); 4111 if (ret) 4112 return ret; 4113 4114 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 4115 4116 /* Allocate memory for buffer descriptors. */ 4117 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma, 4118 GFP_KERNEL); 4119 if (!cbd_base) { 4120 ret = -ENOMEM; 4121 goto free_queue_mem; 4122 } 4123 4124 /* Get the Ethernet address */ 4125 ret = fec_get_mac(ndev); 4126 if (ret) 4127 goto free_queue_mem; 4128 4129 /* Set receive and transmit descriptor base. */ 4130 for (i = 0; i < fep->num_rx_queues; i++) { 4131 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 4132 unsigned size = dsize * rxq->bd.ring_size; 4133 4134 rxq->bd.qid = i; 4135 rxq->bd.base = cbd_base; 4136 rxq->bd.cur = cbd_base; 4137 rxq->bd.dma = bd_dma; 4138 rxq->bd.dsize = dsize; 4139 rxq->bd.dsize_log2 = dsize_log2; 4140 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 4141 bd_dma += size; 4142 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4143 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4144 } 4145 4146 for (i = 0; i < fep->num_tx_queues; i++) { 4147 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 4148 unsigned size = dsize * txq->bd.ring_size; 4149 4150 txq->bd.qid = i; 4151 txq->bd.base = cbd_base; 4152 txq->bd.cur = cbd_base; 4153 txq->bd.dma = bd_dma; 4154 txq->bd.dsize = dsize; 4155 txq->bd.dsize_log2 = dsize_log2; 4156 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 4157 bd_dma += size; 4158 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 4159 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 4160 } 4161 4162 4163 /* The FEC Ethernet specific entries in the device structure */ 4164 ndev->watchdog_timeo = TX_TIMEOUT; 4165 ndev->netdev_ops = &fec_netdev_ops; 4166 ndev->ethtool_ops = &fec_enet_ethtool_ops; 4167 4168 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 4169 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); 4170 4171 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 4172 /* enable hw VLAN support */ 4173 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 4174 4175 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 4176 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS); 4177 4178 /* enable hw accelerator */ 4179 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 4180 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 4181 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 4182 } 4183 4184 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) 4185 fep->tx_align = 0; 4186 4187 ndev->hw_features = ndev->features; 4188 4189 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME)) 4190 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 4191 NETDEV_XDP_ACT_REDIRECT; 4192 4193 fec_restart(ndev); 4194 4195 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 4196 fec_enet_clear_ethtool_stats(ndev); 4197 else 4198 fec_enet_update_ethtool_stats(ndev); 4199 4200 return 0; 4201 4202free_queue_mem: 4203 fec_enet_free_queue(ndev); 4204 return ret; 4205} 4206 4207static void fec_enet_deinit(struct net_device *ndev) 4208{ 4209 struct fec_enet_private *fep = netdev_priv(ndev); 4210 4211 netif_napi_del(&fep->napi); 4212 fec_enet_free_queue(ndev); 4213} 4214 4215#ifdef CONFIG_OF 4216static int fec_reset_phy(struct platform_device *pdev) 4217{ 4218 struct gpio_desc *phy_reset; 4219 int msec = 1, phy_post_delay = 0; 4220 struct device_node *np = pdev->dev.of_node; 4221 int err; 4222 4223 if (!np) 4224 return 0; 4225 4226 err = of_property_read_u32(np, "phy-reset-duration", &msec); 4227 /* A sane reset duration should not be longer than 1s */ 4228 if (!err && msec > 1000) 4229 msec = 1; 4230 4231 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 4232 /* valid reset duration should be less than 1s */ 4233 if (!err && phy_post_delay > 1000) 4234 return -EINVAL; 4235 4236 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset", 4237 GPIOD_OUT_HIGH); 4238 if (IS_ERR(phy_reset)) 4239 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset), 4240 "failed to get phy-reset-gpios\n"); 4241 4242 if (!phy_reset) 4243 return 0; 4244 4245 if (msec > 20) 4246 msleep(msec); 4247 else 4248 usleep_range(msec * 1000, msec * 1000 + 1000); 4249 4250 gpiod_set_value_cansleep(phy_reset, 0); 4251 4252 if (!phy_post_delay) 4253 return 0; 4254 4255 if (phy_post_delay > 20) 4256 msleep(phy_post_delay); 4257 else 4258 usleep_range(phy_post_delay * 1000, 4259 phy_post_delay * 1000 + 1000); 4260 4261 return 0; 4262} 4263#else /* CONFIG_OF */ 4264static int fec_reset_phy(struct platform_device *pdev) 4265{ 4266 /* 4267 * In case of platform probe, the reset has been done 4268 * by machine code. 4269 */ 4270 return 0; 4271} 4272#endif /* CONFIG_OF */ 4273 4274static void 4275fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 4276{ 4277 struct device_node *np = pdev->dev.of_node; 4278 4279 *num_tx = *num_rx = 1; 4280 4281 if (!np || !of_device_is_available(np)) 4282 return; 4283 4284 /* parse the num of tx and rx queues */ 4285 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 4286 4287 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 4288 4289 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 4290 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 4291 *num_tx); 4292 *num_tx = 1; 4293 return; 4294 } 4295 4296 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 4297 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 4298 *num_rx); 4299 *num_rx = 1; 4300 return; 4301 } 4302 4303} 4304 4305static int fec_enet_get_irq_cnt(struct platform_device *pdev) 4306{ 4307 int irq_cnt = platform_irq_count(pdev); 4308 4309 if (irq_cnt > FEC_IRQ_NUM) 4310 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 4311 else if (irq_cnt == 2) 4312 irq_cnt = 1; /* last for pps */ 4313 else if (irq_cnt <= 0) 4314 irq_cnt = 1; /* At least 1 irq is needed */ 4315 return irq_cnt; 4316} 4317 4318static void fec_enet_get_wakeup_irq(struct platform_device *pdev) 4319{ 4320 struct net_device *ndev = platform_get_drvdata(pdev); 4321 struct fec_enet_private *fep = netdev_priv(ndev); 4322 4323 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) 4324 fep->wake_irq = fep->irq[2]; 4325 else 4326 fep->wake_irq = fep->irq[0]; 4327} 4328 4329static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 4330 struct device_node *np) 4331{ 4332 struct device_node *gpr_np; 4333 u32 out_val[3]; 4334 int ret = 0; 4335 4336 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 4337 if (!gpr_np) 4338 return 0; 4339 4340 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 4341 ARRAY_SIZE(out_val)); 4342 if (ret) { 4343 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 4344 goto out; 4345 } 4346 4347 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 4348 if (IS_ERR(fep->stop_gpr.gpr)) { 4349 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 4350 ret = PTR_ERR(fep->stop_gpr.gpr); 4351 fep->stop_gpr.gpr = NULL; 4352 goto out; 4353 } 4354 4355 fep->stop_gpr.reg = out_val[1]; 4356 fep->stop_gpr.bit = out_val[2]; 4357 4358out: 4359 of_node_put(gpr_np); 4360 4361 return ret; 4362} 4363 4364static int 4365fec_probe(struct platform_device *pdev) 4366{ 4367 struct fec_enet_private *fep; 4368 struct fec_platform_data *pdata; 4369 phy_interface_t interface; 4370 struct net_device *ndev; 4371 int i, irq, ret = 0; 4372 static int dev_id; 4373 struct device_node *np = pdev->dev.of_node, *phy_node; 4374 int num_tx_qs; 4375 int num_rx_qs; 4376 char irq_name[8]; 4377 int irq_cnt; 4378 const struct fec_devinfo *dev_info; 4379 4380 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 4381 4382 /* Init network device */ 4383 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 4384 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 4385 if (!ndev) 4386 return -ENOMEM; 4387 4388 SET_NETDEV_DEV(ndev, &pdev->dev); 4389 4390 /* setup board info structure */ 4391 fep = netdev_priv(ndev); 4392 4393 dev_info = device_get_match_data(&pdev->dev); 4394 if (!dev_info) 4395 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data; 4396 if (dev_info) 4397 fep->quirks = dev_info->quirks; 4398 4399 fep->netdev = ndev; 4400 fep->num_rx_queues = num_rx_qs; 4401 fep->num_tx_queues = num_tx_qs; 4402 4403 /* default enable pause frame auto negotiation */ 4404 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 4405 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 4406 4407 /* Select default pin state */ 4408 pinctrl_pm_select_default_state(&pdev->dev); 4409 4410 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 4411 if (IS_ERR(fep->hwp)) { 4412 ret = PTR_ERR(fep->hwp); 4413 goto failed_ioremap; 4414 } 4415 4416 fep->pdev = pdev; 4417 fep->dev_id = dev_id++; 4418 4419 platform_set_drvdata(pdev, ndev); 4420 4421 if ((of_machine_is_compatible("fsl,imx6q") || 4422 of_machine_is_compatible("fsl,imx6dl")) && 4423 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 4424 fep->quirks |= FEC_QUIRK_ERR006687; 4425 4426 ret = fec_enet_ipc_handle_init(fep); 4427 if (ret) 4428 goto failed_ipc_init; 4429 4430 if (of_property_read_bool(np, "fsl,magic-packet")) 4431 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 4432 4433 ret = fec_enet_init_stop_mode(fep, np); 4434 if (ret) 4435 goto failed_stop_mode; 4436 4437 phy_node = of_parse_phandle(np, "phy-handle", 0); 4438 if (!phy_node && of_phy_is_fixed_link(np)) { 4439 ret = of_phy_register_fixed_link(np); 4440 if (ret < 0) { 4441 dev_err(&pdev->dev, 4442 "broken fixed-link specification\n"); 4443 goto failed_phy; 4444 } 4445 phy_node = of_node_get(np); 4446 } 4447 fep->phy_node = phy_node; 4448 4449 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 4450 if (ret) { 4451 pdata = dev_get_platdata(&pdev->dev); 4452 if (pdata) 4453 fep->phy_interface = pdata->phy; 4454 else 4455 fep->phy_interface = PHY_INTERFACE_MODE_MII; 4456 } else { 4457 fep->phy_interface = interface; 4458 } 4459 4460 ret = fec_enet_parse_rgmii_delay(fep, np); 4461 if (ret) 4462 goto failed_rgmii_delay; 4463 4464 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 4465 if (IS_ERR(fep->clk_ipg)) { 4466 ret = PTR_ERR(fep->clk_ipg); 4467 goto failed_clk; 4468 } 4469 4470 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 4471 if (IS_ERR(fep->clk_ahb)) { 4472 ret = PTR_ERR(fep->clk_ahb); 4473 goto failed_clk; 4474 } 4475 4476 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 4477 4478 /* enet_out is optional, depends on board */ 4479 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out"); 4480 if (IS_ERR(fep->clk_enet_out)) { 4481 ret = PTR_ERR(fep->clk_enet_out); 4482 goto failed_clk; 4483 } 4484 4485 fep->ptp_clk_on = false; 4486 mutex_init(&fep->ptp_clk_mutex); 4487 4488 /* clk_ref is optional, depends on board */ 4489 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref"); 4490 if (IS_ERR(fep->clk_ref)) { 4491 ret = PTR_ERR(fep->clk_ref); 4492 goto failed_clk; 4493 } 4494 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); 4495 4496 /* clk_2x_txclk is optional, depends on board */ 4497 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { 4498 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); 4499 if (IS_ERR(fep->clk_2x_txclk)) 4500 fep->clk_2x_txclk = NULL; 4501 } 4502 4503 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 4504 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 4505 if (IS_ERR(fep->clk_ptp)) { 4506 fep->clk_ptp = NULL; 4507 fep->bufdesc_ex = false; 4508 } 4509 4510 ret = fec_enet_clk_enable(ndev, true); 4511 if (ret) 4512 goto failed_clk; 4513 4514 ret = clk_prepare_enable(fep->clk_ipg); 4515 if (ret) 4516 goto failed_clk_ipg; 4517 ret = clk_prepare_enable(fep->clk_ahb); 4518 if (ret) 4519 goto failed_clk_ahb; 4520 4521 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 4522 if (!IS_ERR(fep->reg_phy)) { 4523 ret = regulator_enable(fep->reg_phy); 4524 if (ret) { 4525 dev_err(&pdev->dev, 4526 "Failed to enable phy regulator: %d\n", ret); 4527 goto failed_regulator; 4528 } 4529 } else { 4530 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 4531 ret = -EPROBE_DEFER; 4532 goto failed_regulator; 4533 } 4534 fep->reg_phy = NULL; 4535 } 4536 4537 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 4538 pm_runtime_use_autosuspend(&pdev->dev); 4539 pm_runtime_get_noresume(&pdev->dev); 4540 pm_runtime_set_active(&pdev->dev); 4541 pm_runtime_enable(&pdev->dev); 4542 4543 ret = fec_reset_phy(pdev); 4544 if (ret) 4545 goto failed_reset; 4546 4547 irq_cnt = fec_enet_get_irq_cnt(pdev); 4548 if (fep->bufdesc_ex) 4549 fec_ptp_init(pdev, irq_cnt); 4550 4551 ret = fec_enet_init(ndev); 4552 if (ret) 4553 goto failed_init; 4554 4555 for (i = 0; i < irq_cnt; i++) { 4556 snprintf(irq_name, sizeof(irq_name), "int%d", i); 4557 irq = platform_get_irq_byname_optional(pdev, irq_name); 4558 if (irq < 0) 4559 irq = platform_get_irq(pdev, i); 4560 if (irq < 0) { 4561 ret = irq; 4562 goto failed_irq; 4563 } 4564 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 4565 0, pdev->name, ndev); 4566 if (ret) 4567 goto failed_irq; 4568 4569 fep->irq[i] = irq; 4570 } 4571 4572 /* Decide which interrupt line is wakeup capable */ 4573 fec_enet_get_wakeup_irq(pdev); 4574 4575 ret = fec_enet_mii_init(pdev); 4576 if (ret) 4577 goto failed_mii_init; 4578 4579 /* Carrier starts down, phylib will bring it up */ 4580 netif_carrier_off(ndev); 4581 fec_enet_clk_enable(ndev, false); 4582 pinctrl_pm_select_sleep_state(&pdev->dev); 4583 4584 fep->pagepool_order = 0; 4585 fep->rx_frame_size = FEC_ENET_RX_FRSIZE; 4586 4587 if (fep->quirks & FEC_QUIRK_JUMBO_FRAME) 4588 fep->max_buf_size = MAX_JUMBO_BUF_SIZE; 4589 else 4590 fep->max_buf_size = PKT_MAXBUF_SIZE; 4591 4592 ndev->max_mtu = fep->max_buf_size - VLAN_ETH_HLEN - ETH_FCS_LEN; 4593 4594 ret = register_netdev(ndev); 4595 if (ret) 4596 goto failed_register; 4597 4598 device_init_wakeup(&ndev->dev, fep->wol_flag & 4599 FEC_WOL_HAS_MAGIC_PACKET); 4600 4601 if (fep->bufdesc_ex && fep->ptp_clock) 4602 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 4603 4604 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 4605 4606 pm_runtime_put_autosuspend(&pdev->dev); 4607 4608 return 0; 4609 4610failed_register: 4611 fec_enet_mii_remove(fep); 4612failed_mii_init: 4613failed_irq: 4614 fec_enet_deinit(ndev); 4615failed_init: 4616 fec_ptp_stop(pdev); 4617failed_reset: 4618 pm_runtime_put_noidle(&pdev->dev); 4619 pm_runtime_disable(&pdev->dev); 4620 if (fep->reg_phy) 4621 regulator_disable(fep->reg_phy); 4622failed_regulator: 4623 clk_disable_unprepare(fep->clk_ahb); 4624failed_clk_ahb: 4625 clk_disable_unprepare(fep->clk_ipg); 4626failed_clk_ipg: 4627 fec_enet_clk_enable(ndev, false); 4628failed_clk: 4629failed_rgmii_delay: 4630 if (of_phy_is_fixed_link(np)) 4631 of_phy_deregister_fixed_link(np); 4632 of_node_put(phy_node); 4633failed_stop_mode: 4634failed_ipc_init: 4635failed_phy: 4636 dev_id--; 4637failed_ioremap: 4638 free_netdev(ndev); 4639 4640 return ret; 4641} 4642 4643static void 4644fec_drv_remove(struct platform_device *pdev) 4645{ 4646 struct net_device *ndev = platform_get_drvdata(pdev); 4647 struct fec_enet_private *fep = netdev_priv(ndev); 4648 struct device_node *np = pdev->dev.of_node; 4649 int ret; 4650 4651 ret = pm_runtime_get_sync(&pdev->dev); 4652 if (ret < 0) 4653 dev_err(&pdev->dev, 4654 "Failed to resume device in remove callback (%pe)\n", 4655 ERR_PTR(ret)); 4656 4657 cancel_work_sync(&fep->tx_timeout_work); 4658 fec_ptp_stop(pdev); 4659 unregister_netdev(ndev); 4660 fec_enet_mii_remove(fep); 4661 if (fep->reg_phy) 4662 regulator_disable(fep->reg_phy); 4663 4664 if (of_phy_is_fixed_link(np)) 4665 of_phy_deregister_fixed_link(np); 4666 of_node_put(fep->phy_node); 4667 4668 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 4669 * disabling them again. 4670 */ 4671 if (ret >= 0) { 4672 clk_disable_unprepare(fep->clk_ahb); 4673 clk_disable_unprepare(fep->clk_ipg); 4674 } 4675 pm_runtime_put_noidle(&pdev->dev); 4676 pm_runtime_disable(&pdev->dev); 4677 4678 fec_enet_deinit(ndev); 4679 free_netdev(ndev); 4680} 4681 4682static int fec_suspend(struct device *dev) 4683{ 4684 struct net_device *ndev = dev_get_drvdata(dev); 4685 struct fec_enet_private *fep = netdev_priv(ndev); 4686 int ret; 4687 4688 rtnl_lock(); 4689 if (netif_running(ndev)) { 4690 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 4691 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 4692 phy_stop(ndev->phydev); 4693 napi_disable(&fep->napi); 4694 netif_tx_lock_bh(ndev); 4695 netif_device_detach(ndev); 4696 netif_tx_unlock_bh(ndev); 4697 fec_stop(ndev); 4698 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4699 fec_irqs_disable(ndev); 4700 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 4701 } else { 4702 fec_irqs_disable_except_wakeup(ndev); 4703 if (fep->wake_irq > 0) { 4704 disable_irq(fep->wake_irq); 4705 enable_irq_wake(fep->wake_irq); 4706 } 4707 fec_enet_stop_mode(fep, true); 4708 } 4709 /* It's safe to disable clocks since interrupts are masked */ 4710 fec_enet_clk_enable(ndev, false); 4711 4712 fep->rpm_active = !pm_runtime_status_suspended(dev); 4713 if (fep->rpm_active) { 4714 ret = pm_runtime_force_suspend(dev); 4715 if (ret < 0) { 4716 rtnl_unlock(); 4717 return ret; 4718 } 4719 } 4720 } 4721 rtnl_unlock(); 4722 4723 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 4724 regulator_disable(fep->reg_phy); 4725 4726 /* SOC supply clock to phy, when clock is disabled, phy link down 4727 * SOC control phy regulator, when regulator is disabled, phy link down 4728 */ 4729 if (fep->clk_enet_out || fep->reg_phy) 4730 fep->link = 0; 4731 4732 return 0; 4733} 4734 4735static int fec_resume(struct device *dev) 4736{ 4737 struct net_device *ndev = dev_get_drvdata(dev); 4738 struct fec_enet_private *fep = netdev_priv(ndev); 4739 int ret; 4740 int val; 4741 4742 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 4743 ret = regulator_enable(fep->reg_phy); 4744 if (ret) 4745 return ret; 4746 } 4747 4748 rtnl_lock(); 4749 if (netif_running(ndev)) { 4750 if (fep->rpm_active) 4751 pm_runtime_force_resume(dev); 4752 4753 ret = fec_enet_clk_enable(ndev, true); 4754 if (ret) { 4755 rtnl_unlock(); 4756 goto failed_clk; 4757 } 4758 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 4759 fec_enet_stop_mode(fep, false); 4760 if (fep->wake_irq) { 4761 disable_irq_wake(fep->wake_irq); 4762 enable_irq(fep->wake_irq); 4763 } 4764 4765 val = readl(fep->hwp + FEC_ECNTRL); 4766 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 4767 writel(val, fep->hwp + FEC_ECNTRL); 4768 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 4769 } else { 4770 pinctrl_pm_select_default_state(&fep->pdev->dev); 4771 } 4772 fec_restart(ndev); 4773 netif_tx_lock_bh(ndev); 4774 netif_device_attach(ndev); 4775 netif_tx_unlock_bh(ndev); 4776 napi_enable(&fep->napi); 4777 phy_init_hw(ndev->phydev); 4778 phy_start(ndev->phydev); 4779 } 4780 rtnl_unlock(); 4781 4782 return 0; 4783 4784failed_clk: 4785 if (fep->reg_phy) 4786 regulator_disable(fep->reg_phy); 4787 return ret; 4788} 4789 4790static int fec_runtime_suspend(struct device *dev) 4791{ 4792 struct net_device *ndev = dev_get_drvdata(dev); 4793 struct fec_enet_private *fep = netdev_priv(ndev); 4794 4795 clk_disable_unprepare(fep->clk_ahb); 4796 clk_disable_unprepare(fep->clk_ipg); 4797 4798 return 0; 4799} 4800 4801static int fec_runtime_resume(struct device *dev) 4802{ 4803 struct net_device *ndev = dev_get_drvdata(dev); 4804 struct fec_enet_private *fep = netdev_priv(ndev); 4805 int ret; 4806 4807 ret = clk_prepare_enable(fep->clk_ahb); 4808 if (ret) 4809 return ret; 4810 ret = clk_prepare_enable(fep->clk_ipg); 4811 if (ret) 4812 goto failed_clk_ipg; 4813 4814 return 0; 4815 4816failed_clk_ipg: 4817 clk_disable_unprepare(fep->clk_ahb); 4818 return ret; 4819} 4820 4821static const struct dev_pm_ops fec_pm_ops = { 4822 SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 4823 RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 4824}; 4825 4826static struct platform_driver fec_driver = { 4827 .driver = { 4828 .name = DRIVER_NAME, 4829 .pm = pm_ptr(&fec_pm_ops), 4830 .of_match_table = fec_dt_ids, 4831 .suppress_bind_attrs = true, 4832 }, 4833 .id_table = fec_devtype, 4834 .probe = fec_probe, 4835 .remove = fec_drv_remove, 4836}; 4837 4838module_platform_driver(fec_driver); 4839 4840MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver"); 4841MODULE_LICENSE("GPL");
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