fec.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/****************************************************************************/
  3
  4/*
  5 *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
  6 *		   processors.
  7 *
  8 *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
  9 *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
 10 */
 11
 12/****************************************************************************/
 13#ifndef FEC_H
 14#define	FEC_H
 15/****************************************************************************/
 16
 17#include <dt-bindings/firmware/imx/rsrc.h>
 18#include <linux/bpf.h>
 19#include <linux/clocksource.h>
 20#include <linux/firmware/imx/sci.h>
 21#include <linux/net_tstamp.h>
 22#include <linux/pm_qos.h>
 23#include <linux/ptp_clock_kernel.h>
 24#include <linux/timecounter.h>
 25#include <net/xdp.h>
 26
 27#if !defined(CONFIG_M5272) || defined(CONFIG_COMPILE_TEST)
 28/*
 29 *	Just figures, Motorola would have to change the offsets for
 30 *	registers in the same peripheral device on different models
 31 *	of the ColdFire!
 32 */
 33#define FEC_IEVENT		0x004 /* Interrupt event reg */
 34#define FEC_IMASK		0x008 /* Interrupt mask reg */
 35#define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
 36#define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
 37#define FEC_ECNTRL		0x024 /* Ethernet control reg */
 38#define FEC_MII_DATA		0x040 /* MII manage frame reg */
 39#define FEC_MII_SPEED		0x044 /* MII speed control reg */
 40#define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
 41#define FEC_R_CNTRL		0x084 /* Receive control reg */
 42#define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
 43#define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
 44#define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
 45#define FEC_OPD			0x0ec /* Opcode + Pause duration */
 46#define FEC_TXIC0		0x0f0 /* Tx Interrupt Coalescing for ring 0 */
 47#define FEC_TXIC1		0x0f4 /* Tx Interrupt Coalescing for ring 1 */
 48#define FEC_TXIC2		0x0f8 /* Tx Interrupt Coalescing for ring 2 */
 49#define FEC_RXIC0		0x100 /* Rx Interrupt Coalescing for ring 0 */
 50#define FEC_RXIC1		0x104 /* Rx Interrupt Coalescing for ring 1 */
 51#define FEC_RXIC2		0x108 /* Rx Interrupt Coalescing for ring 2 */
 52#define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
 53#define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
 54#define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
 55#define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
 56#define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
 57#define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
 58#define FEC_R_FSTART		0x150 /* FIFO receive start reg */
 59#define FEC_R_DES_START_1	0x160 /* Receive descriptor ring 1 */
 60#define FEC_X_DES_START_1	0x164 /* Transmit descriptor ring 1 */
 61#define FEC_R_BUFF_SIZE_1	0x168 /* Maximum receive buff ring1 size */
 62#define FEC_R_DES_START_2	0x16c /* Receive descriptor ring 2 */
 63#define FEC_X_DES_START_2	0x170 /* Transmit descriptor ring 2 */
 64#define FEC_R_BUFF_SIZE_2	0x174 /* Maximum receive buff ring2 size */
 65#define FEC_R_DES_START_0	0x180 /* Receive descriptor ring */
 66#define FEC_X_DES_START_0	0x184 /* Transmit descriptor ring */
 67#define FEC_R_BUFF_SIZE_0	0x188 /* Maximum receive buff size */
 68#define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
 69#define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
 70#define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
 71#define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
 72#define FEC_FTRL		0x1b0 /* Frame truncation receive length*/
 73#define FEC_RACC		0x1c4 /* Receive Accelerator function */
 74#define FEC_RCMR_1		0x1c8 /* Receive classification match ring 1 */
 75#define FEC_RCMR_2		0x1cc /* Receive classification match ring 2 */
 76#define FEC_DMA_CFG_1		0x1d8 /* DMA class configuration for ring 1 */
 77#define FEC_DMA_CFG_2		0x1dc /* DMA class Configuration for ring 2 */
 78#define FEC_R_DES_ACTIVE_1	0x1e0 /* Rx descriptor active for ring 1 */
 79#define FEC_X_DES_ACTIVE_1	0x1e4 /* Tx descriptor active for ring 1 */
 80#define FEC_R_DES_ACTIVE_2	0x1e8 /* Rx descriptor active for ring 2 */
 81#define FEC_X_DES_ACTIVE_2	0x1ec /* Tx descriptor active for ring 2 */
 82#define FEC_QOS_SCHEME		0x1f0 /* Set multi queues Qos scheme */
 83#define FEC_LPI_SLEEP		0x1f4 /* Set IEEE802.3az LPI Sleep Ts time */
 84#define FEC_LPI_WAKE		0x1f8 /* Set IEEE802.3az LPI Wake Tw time */
 85#define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */
 86#define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */
 87
 88#define BM_MIIGSK_CFGR_MII		0x00
 89#define BM_MIIGSK_CFGR_RMII		0x01
 90#define BM_MIIGSK_CFGR_FRCONT_10M	0x40
 91
 92#define RMON_T_DROP		0x200 /* Count of frames not cntd correctly */
 93#define RMON_T_PACKETS		0x204 /* RMON TX packet count */
 94#define RMON_T_BC_PKT		0x208 /* RMON TX broadcast pkts */
 95#define RMON_T_MC_PKT		0x20c /* RMON TX multicast pkts */
 96#define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
 97#define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
 98#define RMON_T_OVERSIZE		0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
 99#define RMON_T_FRAG		0x21c /* RMON TX pkts < 64 bytes, bad CRC */
100#define RMON_T_JAB		0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
101#define RMON_T_COL		0x224 /* RMON TX collision count */
102#define RMON_T_P64		0x228 /* RMON TX 64 byte pkts */
103#define RMON_T_P65TO127		0x22c /* RMON TX 65 to 127 byte pkts */
104#define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
105#define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
106#define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
107#define RMON_T_P1024TO2047	0x23c /* RMON TX 1024 to 2047 byte pkts */
108#define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
109#define RMON_T_OCTETS		0x244 /* RMON TX octets */
110#define IEEE_T_DROP		0x248 /* Count of frames not counted crtly */
111#define IEEE_T_FRAME_OK		0x24c /* Frames tx'd OK */
112#define IEEE_T_1COL		0x250 /* Frames tx'd with single collision */
113#define IEEE_T_MCOL		0x254 /* Frames tx'd with multiple collision */
114#define IEEE_T_DEF		0x258 /* Frames tx'd after deferral delay */
115#define IEEE_T_LCOL		0x25c /* Frames tx'd with late collision */
116#define IEEE_T_EXCOL		0x260 /* Frames tx'd with excessive collisions */
117#define IEEE_T_MACERR		0x264 /* Frames tx'd with TX FIFO underrun */
118#define IEEE_T_CSERR		0x268 /* Frames tx'd with carrier sense err */
119#define IEEE_T_SQE		0x26c /* Frames tx'd with SQE err */
120#define IEEE_T_FDXFC		0x270 /* Flow control pause frames tx'd */
121#define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
122#define RMON_R_PACKETS		0x284 /* RMON RX packet count */
123#define RMON_R_BC_PKT		0x288 /* RMON RX broadcast pkts */
124#define RMON_R_MC_PKT		0x28c /* RMON RX multicast pkts */
125#define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
126#define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
127#define RMON_R_OVERSIZE		0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
128#define RMON_R_FRAG		0x29c /* RMON RX pkts < 64 bytes, bad CRC */
129#define RMON_R_JAB		0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
130#define RMON_R_RESVD_O		0x2a4 /* Reserved */
131#define RMON_R_P64		0x2a8 /* RMON RX 64 byte pkts */
132#define RMON_R_P65TO127		0x2ac /* RMON RX 65 to 127 byte pkts */
133#define RMON_R_P128TO255	0x2b0 /* RMON RX 128 to 255 byte pkts */
134#define RMON_R_P256TO511	0x2b4 /* RMON RX 256 to 511 byte pkts */
135#define RMON_R_P512TO1023	0x2b8 /* RMON RX 512 to 1023 byte pkts */
136#define RMON_R_P1024TO2047	0x2bc /* RMON RX 1024 to 2047 byte pkts */
137#define RMON_R_P_GTE2048	0x2c0 /* RMON RX pkts > 2048 bytes */
138#define RMON_R_OCTETS		0x2c4 /* RMON RX octets */
139#define IEEE_R_DROP		0x2c8 /* Count frames not counted correctly */
140#define IEEE_R_FRAME_OK		0x2cc /* Frames rx'd OK */
141#define IEEE_R_CRC		0x2d0 /* Frames rx'd with CRC err */
142#define IEEE_R_ALIGN		0x2d4 /* Frames rx'd with alignment err */
143#define IEEE_R_MACERR		0x2d8 /* Receive FIFO overflow count */
144#define IEEE_R_FDXFC		0x2dc /* Flow control pause frames rx'd */
145#define IEEE_R_OCTETS_OK	0x2e0 /* Octet cnt for frames rx'd w/o err */
146
147#else
148
149#define FEC_ECNTRL		0x000 /* Ethernet control reg */
150#define FEC_IEVENT		0x004 /* Interrupt even reg */
151#define FEC_IMASK		0x008 /* Interrupt mask reg */
152#define FEC_IVEC		0x00c /* Interrupt vec status reg */
153#define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
154#define FEC_R_DES_ACTIVE_1	FEC_R_DES_ACTIVE_0
155#define FEC_R_DES_ACTIVE_2	FEC_R_DES_ACTIVE_0
156#define FEC_X_DES_ACTIVE_0	0x014 /* Transmit descriptor reg */
157#define FEC_X_DES_ACTIVE_1	FEC_X_DES_ACTIVE_0
158#define FEC_X_DES_ACTIVE_2	FEC_X_DES_ACTIVE_0
159#define FEC_MII_DATA		0x040 /* MII manage frame reg */
160#define FEC_MII_SPEED		0x044 /* MII speed control reg */
161#define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
162#define FEC_R_FSTART		0x090 /* FIFO receive start reg */
163#define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
164#define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
165#define FEC_R_CNTRL		0x104 /* Receive control reg */
166#define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
167#define FEC_X_CNTRL		0x144 /* Transmit Control reg */
168#define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
169#define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
170#define FEC_GRP_HASH_TABLE_HIGH	0x3c8 /* High 32bits hash table */
171#define FEC_GRP_HASH_TABLE_LOW	0x3cc /* Low 32bits hash table */
172#define FEC_R_DES_START_0	0x3d0 /* Receive descriptor ring */
173#define FEC_R_DES_START_1	FEC_R_DES_START_0
174#define FEC_R_DES_START_2	FEC_R_DES_START_0
175#define FEC_X_DES_START_0	0x3d4 /* Transmit descriptor ring */
176#define FEC_X_DES_START_1	FEC_X_DES_START_0
177#define FEC_X_DES_START_2	FEC_X_DES_START_0
178#define FEC_R_BUFF_SIZE_0	0x3d8 /* Maximum receive buff size */
179#define FEC_R_BUFF_SIZE_1	FEC_R_BUFF_SIZE_0
180#define FEC_R_BUFF_SIZE_2	FEC_R_BUFF_SIZE_0
181#define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */
182/* Not existed in real chip
183 * Just for pass build.
184 */
185#define FEC_RCMR_1		0xfff
186#define FEC_RCMR_2		0xfff
187#define FEC_DMA_CFG_1		0xfff
188#define FEC_DMA_CFG_2		0xfff
189#define FEC_TXIC0		0xfff
190#define FEC_TXIC1		0xfff
191#define FEC_TXIC2		0xfff
192#define FEC_RXIC0		0xfff
193#define FEC_RXIC1		0xfff
194#define FEC_RXIC2		0xfff
195#define FEC_LPI_SLEEP		0xfff
196#define FEC_LPI_WAKE		0xfff
197#endif /* CONFIG_M5272 */
198
199
200/*
201 *	Define the buffer descriptor structure.
202 *
203 *	Evidently, ARM SoCs have the FEC block generated in a
204 *	little endian mode so adjust endianness accordingly.
205 */
206#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
207#define fec32_to_cpu le32_to_cpu
208#define fec16_to_cpu le16_to_cpu
209#define cpu_to_fec32 cpu_to_le32
210#define cpu_to_fec16 cpu_to_le16
211#define __fec32 __le32
212#define __fec16 __le16
213
214struct bufdesc {
215	__fec16 cbd_datlen;	/* Data length */
216	__fec16 cbd_sc;		/* Control and status info */
217	__fec32 cbd_bufaddr;	/* Buffer address */
218};
219#else
220#define fec32_to_cpu be32_to_cpu
221#define fec16_to_cpu be16_to_cpu
222#define cpu_to_fec32 cpu_to_be32
223#define cpu_to_fec16 cpu_to_be16
224#define __fec32 __be32
225#define __fec16 __be16
226
227struct bufdesc {
228	__fec16	cbd_sc;		/* Control and status info */
229	__fec16	cbd_datlen;	/* Data length */
230	__fec32	cbd_bufaddr;	/* Buffer address */
231};
232#endif
233
234struct bufdesc_ex {
235	struct bufdesc desc;
236	__fec32 cbd_esc;
237	__fec32 cbd_prot;
238	__fec32 cbd_bdu;
239	__fec32 ts;
240	__fec16 res0[4];
241};
242
243/* Buffer descriptor control/status used by Ethernet receive.
244 */
245#define BD_ENET_RX_EMPTY	((ushort)0x8000)
246#define BD_ENET_RX_WRAP		((ushort)0x2000)
247#define BD_ENET_RX_INTR		((ushort)0x1000)
248#define BD_ENET_RX_LAST		((ushort)0x0800)
249#define BD_ENET_RX_FIRST	((ushort)0x0400)
250#define BD_ENET_RX_MISS		((ushort)0x0100)
251#define BD_ENET_RX_LG		((ushort)0x0020)
252#define BD_ENET_RX_NO		((ushort)0x0010)
253#define BD_ENET_RX_SH		((ushort)0x0008)
254#define BD_ENET_RX_CR		((ushort)0x0004)
255#define BD_ENET_RX_OV		((ushort)0x0002)
256#define BD_ENET_RX_CL		((ushort)0x0001)
257#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
258
259/* Enhanced buffer descriptor control/status used by Ethernet receive */
260#define BD_ENET_RX_VLAN		0x00000004
261
262/* Buffer descriptor control/status used by Ethernet transmit.
263 */
264#define BD_ENET_TX_READY	((ushort)0x8000)
265#define BD_ENET_TX_PAD		((ushort)0x4000)
266#define BD_ENET_TX_WRAP		((ushort)0x2000)
267#define BD_ENET_TX_INTR		((ushort)0x1000)
268#define BD_ENET_TX_LAST		((ushort)0x0800)
269#define BD_ENET_TX_TC		((ushort)0x0400)
270#define BD_ENET_TX_DEF		((ushort)0x0200)
271#define BD_ENET_TX_HB		((ushort)0x0100)
272#define BD_ENET_TX_LC		((ushort)0x0080)
273#define BD_ENET_TX_RL		((ushort)0x0040)
274#define BD_ENET_TX_RCMASK	((ushort)0x003c)
275#define BD_ENET_TX_UN		((ushort)0x0002)
276#define BD_ENET_TX_CSL		((ushort)0x0001)
277#define BD_ENET_TX_STATS	((ushort)0x0fff)	/* All status bits */
278
279/* enhanced buffer descriptor control/status used by Ethernet transmit */
280#define BD_ENET_TX_INT		0x40000000
281#define BD_ENET_TX_TS		0x20000000
282#define BD_ENET_TX_PINS		0x10000000
283#define BD_ENET_TX_IINS		0x08000000
284
285
286/* This device has up to three irqs on some platforms */
287#define FEC_IRQ_NUM		3
288
289/* Maximum number of queues supported
290 * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
291 * User can point the queue number that is less than or equal to 3.
292 */
293#define FEC_ENET_MAX_TX_QS	3
294#define FEC_ENET_MAX_RX_QS	3
295
296#define FEC_R_DES_START(X)	(((X) == 1) ? FEC_R_DES_START_1 : \
297				(((X) == 2) ? \
298					FEC_R_DES_START_2 : FEC_R_DES_START_0))
299#define FEC_X_DES_START(X)	(((X) == 1) ? FEC_X_DES_START_1 : \
300				(((X) == 2) ? \
301					FEC_X_DES_START_2 : FEC_X_DES_START_0))
302#define FEC_R_BUFF_SIZE(X)	(((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
303				(((X) == 2) ? \
304					FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
305
306#define FEC_DMA_CFG(X)		(((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
307
308#define DMA_CLASS_EN		(1 << 16)
309#define FEC_RCMR(X)		(((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
310#define IDLE_SLOPE_MASK		0xffff
311#define IDLE_SLOPE_1		0x200 /* BW fraction: 0.5 */
312#define IDLE_SLOPE_2		0x200 /* BW fraction: 0.5 */
313#define IDLE_SLOPE(X)		(((X) == 1) ?				\
314				(IDLE_SLOPE_1 & IDLE_SLOPE_MASK) :	\
315				(IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
316#define RCMR_MATCHEN		(0x1 << 16)
317#define RCMR_CMP_CFG(v, n)	(((v) & 0x7) <<  (n << 2))
318#define RCMR_CMP_1		(RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
319				RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
320#define RCMR_CMP_2		(RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
321				RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
322#define RCMR_CMP(X)		(((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
323#define FEC_TX_BD_FTYPE(X)	(((X) & 0xf) << 20)
324
325/* The number of Tx and Rx buffers.  These are allocated from the page
326 * pool.  The code may assume these are power of two, so it is best
327 * to keep them that size.
328 * We don't need to allocate pages for the transmitter.  We just use
329 * the skbuffer directly.
330 */
331
332#define FEC_DRV_RESERVE_SPACE (XDP_PACKET_HEADROOM + \
333		SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
334#define FEC_ENET_XDP_HEADROOM	(XDP_PACKET_HEADROOM)
335#define FEC_ENET_RX_PAGES	256
336#define FEC_ENET_RX_FRSIZE	(PAGE_SIZE - FEC_DRV_RESERVE_SPACE)
337#define FEC_ENET_RX_FRPPG	(PAGE_SIZE / FEC_ENET_RX_FRSIZE)
338#define RX_RING_SIZE		(FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
339#define FEC_ENET_TX_FRSIZE	2048
340#define FEC_ENET_TX_FRPPG	(PAGE_SIZE / FEC_ENET_TX_FRSIZE)
341#define TX_RING_SIZE		1024	/* Must be power of two */
342#define TX_RING_MOD_MASK	511	/*   for this to work */
343
344#define BD_ENET_RX_INT		0x00800000
345#define BD_ENET_RX_PTP		((ushort)0x0400)
346#define BD_ENET_RX_ICE		0x00000020
347#define BD_ENET_RX_PCR		0x00000010
348#define FLAG_RX_CSUM_ENABLED	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
349#define FLAG_RX_CSUM_ERROR	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
350
351/* Interrupt events/masks. */
352#define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
353#define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
354#define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
355#define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
356#define FEC_ENET_TXF_0	((uint)0x08000000)	/* Full frame transmitted */
357#define FEC_ENET_TXF_1	((uint)0x00000008)	/* Full frame transmitted */
358#define FEC_ENET_TXF_2	((uint)0x00000080)	/* Full frame transmitted */
359#define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
360#define FEC_ENET_RXF_0	((uint)0x02000000)	/* Full frame received */
361#define FEC_ENET_RXF_1	((uint)0x00000002)	/* Full frame received */
362#define FEC_ENET_RXF_2	((uint)0x00000020)	/* Full frame received */
363#define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
364#define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
365#define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
366#define FEC_ENET_WAKEUP	((uint)0x00020000)	/* Wakeup request */
367#define FEC_ENET_TXF	(FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
368#define FEC_ENET_RXF	(FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
369#define FEC_ENET_RXF_GET(X)	(((X) == 0) ? FEC_ENET_RXF_0 :	\
370				(((X) == 1) ? FEC_ENET_RXF_1 :	\
371				FEC_ENET_RXF_2))
372#define FEC_ENET_TS_AVAIL       ((uint)0x00010000)
373#define FEC_ENET_TS_TIMER       ((uint)0x00008000)
374
375#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF)
376#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
377
378#define FEC_ENET_TXC_DLY	((uint)0x00010000)
379#define FEC_ENET_RXC_DLY	((uint)0x00020000)
380
381/* ENET interrupt coalescing macro define */
382#define FEC_ITR_CLK_SEL		(0x1 << 30)
383#define FEC_ITR_EN		(0x1 << 31)
384#define FEC_ITR_ICFT(X)		(((X) & 0xff) << 20)
385#define FEC_ITR_ICTT(X)		((X) & 0xffff)
386#define FEC_ITR_ICFT_DEFAULT	200  /* Set 200 frame count threshold */
387#define FEC_ITR_ICTT_DEFAULT	1000 /* Set 1000us timer threshold */
388
389#define FEC_VLAN_TAG_LEN	0x04
390#define FEC_ETHTYPE_LEN		0x02
391
392/* Controller is ENET-MAC */
393#define FEC_QUIRK_ENET_MAC		(1 << 0)
394/* Controller needs driver to swap frame */
395#define FEC_QUIRK_SWAP_FRAME		(1 << 1)
396/* Controller uses gasket */
397#define FEC_QUIRK_USE_GASKET		(1 << 2)
398/* Controller has GBIT support */
399#define FEC_QUIRK_HAS_GBIT		(1 << 3)
400/* Controller has extend desc buffer */
401#define FEC_QUIRK_HAS_BUFDESC_EX	(1 << 4)
402/* Controller has hardware checksum support */
403#define FEC_QUIRK_HAS_CSUM		(1 << 5)
404/* Controller has hardware vlan support */
405#define FEC_QUIRK_HAS_VLAN		(1 << 6)
406/* ENET IP errata ERR006358
407 *
408 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
409 * detected as not set during a prior frame transmission, then the
410 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
411 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
412 * frames not being transmitted until there is a 0-to-1 transition on
413 * ENET_TDAR[TDAR].
414 */
415#define FEC_QUIRK_ERR006358		(1 << 7)
416/* ENET IP hw AVB
417 *
418 * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
419 * - Two class indicators on receive with configurable priority
420 * - Two class indicators and line speed timer on transmit allowing
421 *   implementation class credit based shapers externally
422 * - Additional DMA registers provisioned to allow managing up to 3
423 *   independent rings
424 */
425#define FEC_QUIRK_HAS_AVB		(1 << 8)
426/* There is a TDAR race condition for mutliQ when the software sets TDAR
427 * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
428 * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
429 * The issue exist at i.MX6SX enet IP.
430 */
431#define FEC_QUIRK_ERR007885		(1 << 9)
432/* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
433 * After set ENET_ATCR[Capture], there need some time cycles before the counter
434 * value is capture in the register clock domain.
435 * The wait-time-cycles is at least 6 clock cycles of the slower clock between
436 * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz,
437 * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
438 * (40ns * 6).
439 */
440#define FEC_QUIRK_BUG_CAPTURE		(1 << 10)
441/* Controller has only one MDIO bus */
442#define FEC_QUIRK_SINGLE_MDIO		(1 << 11)
443/* Controller supports RACC register */
444#define FEC_QUIRK_HAS_RACC		(1 << 12)
445/* Controller supports interrupt coalesce */
446#define FEC_QUIRK_HAS_COALESCE		(1 << 13)
447/* Interrupt doesn't wake CPU from deep idle */
448#define FEC_QUIRK_ERR006687		(1 << 14)
449/* The MIB counters should be cleared and enabled during
450 * initialisation.
451 */
452#define FEC_QUIRK_MIB_CLEAR		(1 << 15)
453/* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers,
454 * those FIFO receive registers are resolved in other platforms.
455 */
456#define FEC_QUIRK_HAS_FRREG		(1 << 16)
457
458/* Some FEC hardware blocks need the MMFR cleared at setup time to avoid
459 * the generation of an MII event. This must be avoided in the older
460 * FEC blocks where it will stop MII events being generated.
461 */
462#define FEC_QUIRK_CLEAR_SETUP_MII	(1 << 17)
463
464/* Some link partners do not tolerate the momentary reset of the REF_CLK
465 * frequency when the RNCTL register is cleared by hardware reset.
466 */
467#define FEC_QUIRK_NO_HARD_RESET		(1 << 18)
468
469/* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to
470 * represents this ENET IP.
471 */
472#define FEC_QUIRK_HAS_MULTI_QUEUES	(1 << 19)
473
474/* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE
475 * standard. For the transmission, MAC supply two user registers to set
476 * Sleep (TS) and Wake (TW) time.
477 */
478#define FEC_QUIRK_HAS_EEE		(1 << 20)
479
480/* i.MX8QM ENET IP version add new feature to generate delayed TXC/RXC
481 * as an alternative option to make sure it works well with various PHYs.
482 * For the implementation of delayed clock, ENET takes synchronized 250MHz
483 * clocks to generate 2ns delay.
484 */
485#define FEC_QUIRK_DELAYED_CLKS_SUPPORT	(1 << 21)
486
487/* i.MX8MQ SoC integration mix wakeup interrupt signal into "int2" interrupt line. */
488#define FEC_QUIRK_WAKEUP_FROM_INT2	(1 << 22)
489
490/* i.MX6Q adds pm_qos support */
491#define FEC_QUIRK_HAS_PMQOS			BIT(23)
492
493/* Not all FEC hardware block MDIOs support accesses in C45 mode.
494 * Older blocks in the ColdFire parts do not support it.
495 */
496#define FEC_QUIRK_HAS_MDIO_C45		BIT(24)
497
498/* Jumbo Frame support */
499#define FEC_QUIRK_JUMBO_FRAME		BIT(25)
500
501struct bufdesc_prop {
502	int qid;
503	/* Address of Rx and Tx buffers */
504	struct bufdesc	*base;
505	struct bufdesc	*last;
506	struct bufdesc	*cur;
507	void __iomem	*reg_desc_active;
508	dma_addr_t	dma;
509	unsigned short ring_size;
510	unsigned char dsize;
511	unsigned char dsize_log2;
512};
513
514enum {
515	RX_XDP_REDIRECT = 0,
516	RX_XDP_PASS,
517	RX_XDP_DROP,
518	RX_XDP_TX,
519	RX_XDP_TX_ERRORS,
520	TX_XDP_XMIT,
521	TX_XDP_XMIT_ERRORS,
522
523	/* The following must be the last one */
524	XDP_STATS_TOTAL,
525};
526
527enum fec_txbuf_type {
528	FEC_TXBUF_T_SKB,
529	FEC_TXBUF_T_XDP_NDO,
530	FEC_TXBUF_T_XDP_TX,
531};
532
533struct fec_tx_buffer {
534	void *buf_p;
535	enum fec_txbuf_type type;
536};
537
538struct fec_enet_priv_tx_q {
539	struct bufdesc_prop bd;
540	unsigned char *tx_bounce[TX_RING_SIZE];
541	struct fec_tx_buffer tx_buf[TX_RING_SIZE];
542
543	unsigned short tx_stop_threshold;
544	unsigned short tx_wake_threshold;
545
546	struct bufdesc	*dirty_tx;
547	char *tso_hdrs;
548	dma_addr_t tso_hdrs_dma;
549};
550
551struct fec_enet_priv_rx_q {
552	struct bufdesc_prop bd;
553	struct page *rx_buf[RX_RING_SIZE];
554
555	/* page_pool */
556	struct page_pool *page_pool;
557	struct xdp_rxq_info xdp_rxq;
558	u32 stats[XDP_STATS_TOTAL];
559
560	/* rx queue number, in the range 0-7 */
561	u8 id;
562};
563
564struct fec_stop_mode_gpr {
565	struct regmap *gpr;
566	u8 reg;
567	u8 bit;
568};
569
570/* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
571 * tx_bd_base always point to the base of the buffer descriptors.  The
572 * cur_rx and cur_tx point to the currently available buffer.
573 * The dirty_tx tracks the current buffer that is being sent by the
574 * controller.  The cur_tx and dirty_tx are equal under both completely
575 * empty and completely full conditions.  The empty/ready indicator in
576 * the buffer descriptor determines the actual condition.
577 */
578struct fec_enet_private {
579	/* Hardware registers of the FEC device */
580	void __iomem *hwp;
581
582	struct net_device *netdev;
583
584	struct clk *clk_ipg;
585	struct clk *clk_ahb;
586	struct clk *clk_ref;
587	struct clk *clk_enet_out;
588	struct clk *clk_ptp;
589	struct clk *clk_2x_txclk;
590
591	bool ptp_clk_on;
592	struct mutex ptp_clk_mutex;
593	unsigned int num_tx_queues;
594	unsigned int num_rx_queues;
595
596	struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
597	struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
598
599	unsigned int total_tx_ring_size;
600	unsigned int total_rx_ring_size;
601	unsigned int max_buf_size;
602	unsigned int pagepool_order;
603	unsigned int rx_frame_size;
604
605	struct	platform_device *pdev;
606
607	int	dev_id;
608
609	/* Phylib and MDIO interface */
610	struct	mii_bus *mii_bus;
611	uint	phy_speed;
612	phy_interface_t	phy_interface;
613	struct device_node *phy_node;
614	bool	rgmii_txc_dly;
615	bool	rgmii_rxc_dly;
616	bool	rpm_active;
617	int	link;
618	int	full_duplex;
619	int	speed;
620	int	irq[FEC_IRQ_NUM];
621	bool	bufdesc_ex;
622	int	pause_flag;
623	int	wol_flag;
624	int	wake_irq;
625	u32	quirks;
626
627	struct	napi_struct napi;
628	int	csum_flags;
629
630	struct work_struct tx_timeout_work;
631
632	struct ptp_clock *ptp_clock;
633	struct ptp_clock_info ptp_caps;
634	spinlock_t tmreg_lock;
635	struct cyclecounter cc;
636	struct timecounter tc;
637	u32 cycle_speed;
638	int hwts_rx_en;
639	int hwts_tx_en;
640	struct delayed_work time_keep;
641	struct regulator *reg_phy;
642	struct fec_stop_mode_gpr stop_gpr;
643	struct pm_qos_request pm_qos_req;
644
645	unsigned int tx_align;
646
647	/* hw interrupt coalesce */
648	unsigned int rx_pkts_itr;
649	unsigned int rx_time_itr;
650	unsigned int tx_pkts_itr;
651	unsigned int tx_time_itr;
652	unsigned int itr_clk_rate;
653
654	unsigned int clk_ref_rate;
655
656	/* ptp clock period in ns*/
657	unsigned int ptp_inc;
658
659	/* pps  */
660	int pps_channel;
661	unsigned int reload_period;
662	int pps_enable;
663	unsigned int next_counter;
664	bool perout_enable;
665	struct hrtimer perout_timer;
666	u64 perout_stime;
667
668	struct imx_sc_ipc *ipc_handle;
669
670	/* XDP BPF Program */
671	struct bpf_prog *xdp_prog;
672
673	struct {
674		int pps_enable;
675		u64 ns_sys, ns_phc;
676		u32 at_corr;
677		u8 at_inc_corr;
678	} ptp_saved_state;
679
680	u64 ethtool_stats[];
681};
682
683void fec_ptp_init(struct platform_device *pdev, int irq_idx);
684void fec_ptp_restore_state(struct fec_enet_private *fep);
685void fec_ptp_save_state(struct fec_enet_private *fep);
686void fec_ptp_stop(struct platform_device *pdev);
687void fec_ptp_start_cyclecounter(struct net_device *ndev);
688int fec_ptp_set(struct net_device *ndev, struct kernel_hwtstamp_config *config,
689		struct netlink_ext_ack *extack);
690void fec_ptp_get(struct net_device *ndev, struct kernel_hwtstamp_config *config);
691
692/****************************************************************************/
693#endif /* FEC_H */