netc_blk_ctrl.c

  1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2/*
  3 * NXP NETC Blocks Control Driver
  4 *
  5 * Copyright 2024 NXP
  6 *
  7 * This driver is used for pre-initialization of NETC, such as PCS and MII
  8 * protocols, LDID, warm reset, etc. Therefore, all NETC device drivers can
  9 * only be probed after the netc-blk-crtl driver has completed initialization.
 10 * In addition, when the system enters suspend mode, IERB, PRB, and NETCMIX
 11 * will be powered off, except for WOL. Therefore, when the system resumes,
 12 * these blocks need to be reinitialized.
 13 */
 14
 15#include <linux/bits.h>
 16#include <linux/clk.h>
 17#include <linux/debugfs.h>
 18#include <linux/delay.h>
 19#include <linux/fsl/netc_global.h>
 20#include <linux/module.h>
 21#include <linux/of.h>
 22#include <linux/of_device.h>
 23#include <linux/of_net.h>
 24#include <linux/of_platform.h>
 25#include <linux/phy.h>
 26#include <linux/platform_device.h>
 27#include <linux/seq_file.h>
 28
 29/* NETCMIX registers */
 30#define IMX95_CFG_LINK_IO_VAR		0x0
 31#define  IO_VAR_16FF_16G_SERDES		0x1
 32#define  IO_VAR(port, var)		(((var) & 0xf) << ((port) << 2))
 33
 34#define IMX95_CFG_LINK_MII_PROT		0x4
 35#define CFG_LINK_MII_PORT_0		GENMASK(3, 0)
 36#define CFG_LINK_MII_PORT_1		GENMASK(7, 4)
 37#define  MII_PROT_MII			0x0
 38#define  MII_PROT_RMII			0x1
 39#define  MII_PROT_RGMII			0x2
 40#define  MII_PROT_SERIAL		0x3
 41#define  MII_PROT(port, prot)		(((prot) & 0xf) << ((port) << 2))
 42
 43#define IMX95_CFG_LINK_PCS_PROT(a)	(0x8 + (a) * 4)
 44#define PCS_PROT_1G_SGMII		BIT(0)
 45#define PCS_PROT_2500M_SGMII		BIT(1)
 46#define PCS_PROT_XFI			BIT(3)
 47#define PCS_PROT_SFI			BIT(4)
 48#define PCS_PROT_10G_SXGMII		BIT(6)
 49
 50#define IMX94_EXT_PIN_CONTROL		0x10
 51#define  MAC2_MAC3_SEL			BIT(1)
 52
 53#define IMX94_NETC_LINK_CFG(a)		(0x4c + (a) * 4)
 54#define  NETC_LINK_CFG_MII_PROT		GENMASK(3, 0)
 55#define  NETC_LINK_CFG_IO_VAR		GENMASK(19, 16)
 56
 57/* NETC privileged register block register */
 58#define PRB_NETCRR			0x100
 59#define  NETCRR_SR			BIT(0)
 60#define  NETCRR_LOCK			BIT(1)
 61
 62#define PRB_NETCSR			0x104
 63#define  NETCSR_ERROR			BIT(0)
 64#define  NETCSR_STATE			BIT(1)
 65
 66/* NETC integrated endpoint register block register */
 67#define IERB_EMDIOFAUXR			0x344
 68#define IERB_T0FAUXR			0x444
 69#define IERB_ETBCR(a)			(0x300c + 0x100 * (a))
 70#define IERB_LBCR(a)			(0x1010 + 0x40 * (a))
 71#define  LBCR_MDIO_PHYAD_PRTAD(addr)	(((addr) & 0x1f) << 8)
 72
 73#define IERB_EFAUXR(a)			(0x3044 + 0x100 * (a))
 74#define IERB_VFAUXR(a)			(0x4004 + 0x40 * (a))
 75#define FAUXR_LDID			GENMASK(3, 0)
 76
 77/* Platform information */
 78#define IMX95_ENETC0_BUS_DEVFN		0x0
 79#define IMX95_ENETC1_BUS_DEVFN		0x40
 80#define IMX95_ENETC2_BUS_DEVFN		0x80
 81
 82#define IMX94_ENETC0_BUS_DEVFN		0x100
 83#define IMX94_ENETC1_BUS_DEVFN		0x140
 84#define IMX94_ENETC2_BUS_DEVFN		0x180
 85#define IMX94_TIMER0_BUS_DEVFN		0x1
 86#define IMX94_TIMER1_BUS_DEVFN		0x101
 87#define IMX94_TIMER2_BUS_DEVFN		0x181
 88#define IMX94_ENETC0_LINK		3
 89#define IMX94_ENETC1_LINK		4
 90#define IMX94_ENETC2_LINK		5
 91
 92#define NETC_ENETC_ID(a)		(a)
 93#define NETC_TIMER_ID(a)		(a)
 94
 95/* Flags for different platforms */
 96#define NETC_HAS_NETCMIX		BIT(0)
 97
 98struct netc_devinfo {
 99	u32 flags;
100	int (*netcmix_init)(struct platform_device *pdev);
101	int (*ierb_init)(struct platform_device *pdev);
102};
103
104struct netc_blk_ctrl {
105	void __iomem *prb;
106	void __iomem *ierb;
107	void __iomem *netcmix;
108
109	const struct netc_devinfo *devinfo;
110	struct platform_device *pdev;
111	struct dentry *debugfs_root;
112};
113
114static void netc_reg_write(void __iomem *base, u32 offset, u32 val)
115{
116	netc_write(base + offset, val);
117}
118
119static u32 netc_reg_read(void __iomem *base, u32 offset)
120{
121	return netc_read(base + offset);
122}
123
124static int netc_of_pci_get_bus_devfn(struct device_node *np)
125{
126	u32 reg[5];
127	int error;
128
129	error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
130	if (error)
131		return error;
132
133	return (reg[0] >> 8) & 0xffff;
134}
135
136static int netc_get_link_mii_protocol(phy_interface_t interface)
137{
138	switch (interface) {
139	case PHY_INTERFACE_MODE_MII:
140		return MII_PROT_MII;
141	case PHY_INTERFACE_MODE_RMII:
142		return MII_PROT_RMII;
143	case PHY_INTERFACE_MODE_RGMII:
144	case PHY_INTERFACE_MODE_RGMII_ID:
145	case PHY_INTERFACE_MODE_RGMII_RXID:
146	case PHY_INTERFACE_MODE_RGMII_TXID:
147		return MII_PROT_RGMII;
148	case PHY_INTERFACE_MODE_SGMII:
149	case PHY_INTERFACE_MODE_2500BASEX:
150	case PHY_INTERFACE_MODE_10GBASER:
151	case PHY_INTERFACE_MODE_XGMII:
152	case PHY_INTERFACE_MODE_USXGMII:
153		return MII_PROT_SERIAL;
154	default:
155		return -EINVAL;
156	}
157}
158
159static int imx95_netcmix_init(struct platform_device *pdev)
160{
161	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
162	struct device_node *np = pdev->dev.of_node;
163	phy_interface_t interface;
164	int bus_devfn, mii_proto;
165	u32 val;
166	int err;
167
168	/* Default setting of MII protocol */
169	val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII) |
170	      MII_PROT(2, MII_PROT_SERIAL);
171
172	/* Update the link MII protocol through parsing phy-mode */
173	for_each_available_child_of_node_scoped(np, child) {
174		for_each_available_child_of_node_scoped(child, gchild) {
175			if (!of_device_is_compatible(gchild, "pci1131,e101"))
176				continue;
177
178			bus_devfn = netc_of_pci_get_bus_devfn(gchild);
179			if (bus_devfn < 0)
180				return -EINVAL;
181
182			if (bus_devfn == IMX95_ENETC2_BUS_DEVFN)
183				continue;
184
185			err = of_get_phy_mode(gchild, &interface);
186			if (err)
187				continue;
188
189			mii_proto = netc_get_link_mii_protocol(interface);
190			if (mii_proto < 0)
191				return -EINVAL;
192
193			switch (bus_devfn) {
194			case IMX95_ENETC0_BUS_DEVFN:
195				val = u32_replace_bits(val, mii_proto,
196						       CFG_LINK_MII_PORT_0);
197				break;
198			case IMX95_ENETC1_BUS_DEVFN:
199				val = u32_replace_bits(val, mii_proto,
200						       CFG_LINK_MII_PORT_1);
201				break;
202			default:
203				return -EINVAL;
204			}
205		}
206	}
207
208	/* Configure Link I/O variant */
209	netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR,
210		       IO_VAR(2, IO_VAR_16FF_16G_SERDES));
211	/* Configure Link 2 PCS protocol */
212	netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(2),
213		       PCS_PROT_10G_SXGMII);
214	netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val);
215
216	return 0;
217}
218
219static int imx94_enetc_get_link_id(struct device_node *np)
220{
221	int bus_devfn = netc_of_pci_get_bus_devfn(np);
222
223	/* Parse ENETC link number */
224	switch (bus_devfn) {
225	case IMX94_ENETC0_BUS_DEVFN:
226		return IMX94_ENETC0_LINK;
227	case IMX94_ENETC1_BUS_DEVFN:
228		return IMX94_ENETC1_LINK;
229	case IMX94_ENETC2_BUS_DEVFN:
230		return IMX94_ENETC2_LINK;
231	default:
232		return -EINVAL;
233	}
234}
235
236static int imx94_link_config(struct netc_blk_ctrl *priv,
237			     struct device_node *np, int link_id)
238{
239	phy_interface_t interface;
240	int mii_proto;
241	u32 val;
242
243	/* The node may be disabled and does not have a 'phy-mode'
244	 * or 'phy-connection-type' property.
245	 */
246	if (of_get_phy_mode(np, &interface))
247		return 0;
248
249	mii_proto = netc_get_link_mii_protocol(interface);
250	if (mii_proto < 0)
251		return mii_proto;
252
253	val = mii_proto & NETC_LINK_CFG_MII_PROT;
254	if (val == MII_PROT_SERIAL)
255		val = u32_replace_bits(val, IO_VAR_16FF_16G_SERDES,
256				       NETC_LINK_CFG_IO_VAR);
257
258	netc_reg_write(priv->netcmix, IMX94_NETC_LINK_CFG(link_id), val);
259
260	return 0;
261}
262
263static int imx94_enetc_link_config(struct netc_blk_ctrl *priv,
264				   struct device_node *np)
265{
266	int link_id = imx94_enetc_get_link_id(np);
267
268	if (link_id < 0)
269		return link_id;
270
271	return imx94_link_config(priv, np, link_id);
272}
273
274static int imx94_netcmix_init(struct platform_device *pdev)
275{
276	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
277	struct device_node *np = pdev->dev.of_node;
278	u32 val;
279	int err;
280
281	for_each_child_of_node_scoped(np, child) {
282		for_each_child_of_node_scoped(child, gchild) {
283			if (!of_device_is_compatible(gchild, "pci1131,e101"))
284				continue;
285
286			err = imx94_enetc_link_config(priv, gchild);
287			if (err)
288				return err;
289		}
290	}
291
292	/* ENETC 0 and switch port 2 share the same parallel interface.
293	 * Currently, the switch is not supported, so this interface is
294	 * used by ENETC 0 by default.
295	 */
296	val = netc_reg_read(priv->netcmix, IMX94_EXT_PIN_CONTROL);
297	val |= MAC2_MAC3_SEL;
298	netc_reg_write(priv->netcmix, IMX94_EXT_PIN_CONTROL, val);
299
300	return 0;
301}
302
303static bool netc_ierb_is_locked(struct netc_blk_ctrl *priv)
304{
305	return !!(netc_reg_read(priv->prb, PRB_NETCRR) & NETCRR_LOCK);
306}
307
308static int netc_lock_ierb(struct netc_blk_ctrl *priv)
309{
310	u32 val;
311
312	netc_reg_write(priv->prb, PRB_NETCRR, NETCRR_LOCK);
313
314	return read_poll_timeout(netc_reg_read, val, !(val & NETCSR_STATE),
315				 100, 2000, false, priv->prb, PRB_NETCSR);
316}
317
318static int netc_unlock_ierb_with_warm_reset(struct netc_blk_ctrl *priv)
319{
320	u32 val;
321
322	netc_reg_write(priv->prb, PRB_NETCRR, 0);
323
324	return read_poll_timeout(netc_reg_read, val, !(val & NETCRR_LOCK),
325				 1000, 100000, true, priv->prb, PRB_NETCRR);
326}
327
328static int netc_get_phy_addr(struct device_node *np)
329{
330	struct device_node *mdio_node, *phy_node;
331	u32 addr = 0;
332	int err = 0;
333
334	mdio_node = of_get_child_by_name(np, "mdio");
335	if (!mdio_node)
336		return -ENODEV;
337
338	phy_node = of_get_next_child(mdio_node, NULL);
339	if (!phy_node) {
340		err = -ENODEV;
341		goto of_put_mdio_node;
342	}
343
344	err = of_property_read_u32(phy_node, "reg", &addr);
345	if (err)
346		goto of_put_phy_node;
347
348	if (addr >= PHY_MAX_ADDR)
349		err = -EINVAL;
350
351of_put_phy_node:
352	of_node_put(phy_node);
353
354of_put_mdio_node:
355	of_node_put(mdio_node);
356
357	return err ? err : addr;
358}
359
360static int netc_parse_emdio_phy_mask(struct device_node *np, u32 *phy_mask)
361{
362	u32 mask = 0;
363
364	for_each_child_of_node_scoped(np, child) {
365		u32 addr;
366		int err;
367
368		err = of_property_read_u32(child, "reg", &addr);
369		if (err)
370			return err;
371
372		if (addr >= PHY_MAX_ADDR)
373			return -EINVAL;
374
375		mask |= BIT(addr);
376	}
377
378	*phy_mask = mask;
379
380	return 0;
381}
382
383static int netc_get_emdio_phy_mask(struct device_node *np, u32 *phy_mask)
384{
385	for_each_child_of_node_scoped(np, child) {
386		for_each_child_of_node_scoped(child, gchild) {
387			if (!of_device_is_compatible(gchild, "pci1131,ee00"))
388				continue;
389
390			return netc_parse_emdio_phy_mask(gchild, phy_mask);
391		}
392	}
393
394	return 0;
395}
396
397static int imx95_enetc_mdio_phyaddr_config(struct platform_device *pdev)
398{
399	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
400	struct device_node *np = pdev->dev.of_node;
401	struct device *dev = &pdev->dev;
402	int bus_devfn, addr, err;
403	u32 phy_mask = 0;
404
405	err = netc_get_emdio_phy_mask(np, &phy_mask);
406	if (err) {
407		dev_err(dev, "Failed to get PHY address mask\n");
408		return err;
409	}
410
411	/* Update the port EMDIO PHY address through parsing phy properties.
412	 * This is needed when using the port EMDIO but it's harmless when
413	 * using the central EMDIO. So apply it on all cases.
414	 */
415	for_each_child_of_node_scoped(np, child) {
416		for_each_child_of_node_scoped(child, gchild) {
417			if (!of_device_is_compatible(gchild, "pci1131,e101"))
418				continue;
419
420			bus_devfn = netc_of_pci_get_bus_devfn(gchild);
421			if (bus_devfn < 0) {
422				dev_err(dev, "Failed to get BDF number\n");
423				return bus_devfn;
424			}
425
426			addr = netc_get_phy_addr(gchild);
427			if (addr < 0) {
428				if (addr == -ENODEV)
429					continue;
430
431				dev_err(dev, "Failed to get PHY address\n");
432				return addr;
433			}
434
435			if (phy_mask & BIT(addr)) {
436				dev_err(dev,
437					"Find same PHY address in EMDIO and ENETC node\n");
438				return -EINVAL;
439			}
440
441			switch (bus_devfn) {
442			case IMX95_ENETC0_BUS_DEVFN:
443				netc_reg_write(priv->ierb, IERB_LBCR(0),
444					       LBCR_MDIO_PHYAD_PRTAD(addr));
445				break;
446			case IMX95_ENETC1_BUS_DEVFN:
447				netc_reg_write(priv->ierb, IERB_LBCR(1),
448					       LBCR_MDIO_PHYAD_PRTAD(addr));
449				break;
450			case IMX95_ENETC2_BUS_DEVFN:
451				netc_reg_write(priv->ierb, IERB_LBCR(2),
452					       LBCR_MDIO_PHYAD_PRTAD(addr));
453				break;
454			default:
455				break;
456			}
457		}
458	}
459
460	return 0;
461}
462
463static int imx95_ierb_init(struct platform_device *pdev)
464{
465	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
466
467	/* EMDIO : No MSI-X intterupt */
468	netc_reg_write(priv->ierb, IERB_EMDIOFAUXR, 0);
469	/* ENETC0 PF */
470	netc_reg_write(priv->ierb, IERB_EFAUXR(0), 0);
471	/* ENETC0 VF0 */
472	netc_reg_write(priv->ierb, IERB_VFAUXR(0), 1);
473	/* ENETC0 VF1 */
474	netc_reg_write(priv->ierb, IERB_VFAUXR(1), 2);
475	/* ENETC1 PF */
476	netc_reg_write(priv->ierb, IERB_EFAUXR(1), 3);
477	/* ENETC1 VF0 */
478	netc_reg_write(priv->ierb, IERB_VFAUXR(2), 5);
479	/* ENETC1 VF1 */
480	netc_reg_write(priv->ierb, IERB_VFAUXR(3), 6);
481	/* ENETC2 PF */
482	netc_reg_write(priv->ierb, IERB_EFAUXR(2), 4);
483	/* ENETC2 VF0 */
484	netc_reg_write(priv->ierb, IERB_VFAUXR(4), 5);
485	/* ENETC2 VF1 */
486	netc_reg_write(priv->ierb, IERB_VFAUXR(5), 6);
487	/* NETC TIMER */
488	netc_reg_write(priv->ierb, IERB_T0FAUXR, 7);
489
490	return imx95_enetc_mdio_phyaddr_config(pdev);
491}
492
493static int imx94_get_enetc_id(struct device_node *np)
494{
495	int bus_devfn = netc_of_pci_get_bus_devfn(np);
496
497	/* Parse ENETC offset */
498	switch (bus_devfn) {
499	case IMX94_ENETC0_BUS_DEVFN:
500		return NETC_ENETC_ID(0);
501	case IMX94_ENETC1_BUS_DEVFN:
502		return NETC_ENETC_ID(1);
503	case IMX94_ENETC2_BUS_DEVFN:
504		return NETC_ENETC_ID(2);
505	default:
506		return -EINVAL;
507	}
508}
509
510static int imx94_get_timer_id(struct device_node *np)
511{
512	int bus_devfn = netc_of_pci_get_bus_devfn(np);
513
514	/* Parse NETC PTP timer ID, the timer0 is on bus 0,
515	 * the timer 1 and timer2 is on bus 1.
516	 */
517	switch (bus_devfn) {
518	case IMX94_TIMER0_BUS_DEVFN:
519		return NETC_TIMER_ID(0);
520	case IMX94_TIMER1_BUS_DEVFN:
521		return NETC_TIMER_ID(1);
522	case IMX94_TIMER2_BUS_DEVFN:
523		return NETC_TIMER_ID(2);
524	default:
525		return -EINVAL;
526	}
527}
528
529static int imx94_enetc_update_tid(struct netc_blk_ctrl *priv,
530				  struct device_node *np)
531{
532	struct device *dev = &priv->pdev->dev;
533	struct device_node *timer_np;
534	int eid, tid;
535
536	eid = imx94_get_enetc_id(np);
537	if (eid < 0) {
538		dev_err(dev, "Failed to get ENETC ID\n");
539		return eid;
540	}
541
542	timer_np = of_parse_phandle(np, "ptp-timer", 0);
543	if (!timer_np) {
544		/* If 'ptp-timer' is not present, the timer1 is the default
545		 * timer of all standalone ENETCs, which is on the same PCIe
546		 * bus as these ENETCs.
547		 */
548		tid = NETC_TIMER_ID(1);
549		goto end;
550	}
551
552	tid = imx94_get_timer_id(timer_np);
553	of_node_put(timer_np);
554	if (tid < 0) {
555		dev_err(dev, "Failed to get NETC Timer ID\n");
556		return tid;
557	}
558
559end:
560	netc_reg_write(priv->ierb, IERB_ETBCR(eid), tid);
561
562	return 0;
563}
564
565static int imx94_enetc_mdio_phyaddr_config(struct netc_blk_ctrl *priv,
566					   struct device_node *np,
567					   u32 phy_mask)
568{
569	struct device *dev = &priv->pdev->dev;
570	int bus_devfn, addr;
571
572	bus_devfn = netc_of_pci_get_bus_devfn(np);
573	if (bus_devfn < 0) {
574		dev_err(dev, "Failed to get BDF number\n");
575		return bus_devfn;
576	}
577
578	addr = netc_get_phy_addr(np);
579	if (addr < 0) {
580		if (addr == -ENODEV)
581			return 0;
582
583		dev_err(dev, "Failed to get PHY address\n");
584		return addr;
585	}
586
587	if (phy_mask & BIT(addr)) {
588		dev_err(dev,
589			"Find same PHY address in EMDIO and ENETC node\n");
590		return -EINVAL;
591	}
592
593	switch (bus_devfn) {
594	case IMX94_ENETC0_BUS_DEVFN:
595		netc_reg_write(priv->ierb, IERB_LBCR(IMX94_ENETC0_LINK),
596			       LBCR_MDIO_PHYAD_PRTAD(addr));
597		break;
598	case IMX94_ENETC1_BUS_DEVFN:
599		netc_reg_write(priv->ierb, IERB_LBCR(IMX94_ENETC1_LINK),
600			       LBCR_MDIO_PHYAD_PRTAD(addr));
601		break;
602	case IMX94_ENETC2_BUS_DEVFN:
603		netc_reg_write(priv->ierb, IERB_LBCR(IMX94_ENETC2_LINK),
604			       LBCR_MDIO_PHYAD_PRTAD(addr));
605		break;
606	default:
607		break;
608	}
609
610	return 0;
611}
612
613static int imx94_ierb_init(struct platform_device *pdev)
614{
615	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
616	struct device_node *np = pdev->dev.of_node;
617	u32 phy_mask = 0;
618	int err;
619
620	err = netc_get_emdio_phy_mask(np, &phy_mask);
621	if (err) {
622		dev_err(&pdev->dev, "Failed to get PHY address mask\n");
623		return err;
624	}
625
626	for_each_child_of_node_scoped(np, child) {
627		for_each_child_of_node_scoped(child, gchild) {
628			if (!of_device_is_compatible(gchild, "pci1131,e101"))
629				continue;
630
631			err = imx94_enetc_update_tid(priv, gchild);
632			if (err)
633				return err;
634
635			err = imx94_enetc_mdio_phyaddr_config(priv, gchild,
636							      phy_mask);
637			if (err)
638				return err;
639		}
640	}
641
642	return 0;
643}
644
645static int netc_ierb_init(struct platform_device *pdev)
646{
647	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
648	const struct netc_devinfo *devinfo = priv->devinfo;
649	int err;
650
651	if (netc_ierb_is_locked(priv)) {
652		err = netc_unlock_ierb_with_warm_reset(priv);
653		if (err) {
654			dev_err(&pdev->dev, "Unlock IERB failed.\n");
655			return err;
656		}
657	}
658
659	if (devinfo->ierb_init) {
660		err = devinfo->ierb_init(pdev);
661		if (err)
662			return err;
663	}
664
665	err = netc_lock_ierb(priv);
666	if (err) {
667		dev_err(&pdev->dev, "Lock IERB failed.\n");
668		return err;
669	}
670
671	return 0;
672}
673
674#if IS_ENABLED(CONFIG_DEBUG_FS)
675static int netc_prb_show(struct seq_file *s, void *data)
676{
677	struct netc_blk_ctrl *priv = s->private;
678	u32 val;
679
680	val = netc_reg_read(priv->prb, PRB_NETCRR);
681	seq_printf(s, "[PRB NETCRR] Lock:%d SR:%d\n",
682		   (val & NETCRR_LOCK) ? 1 : 0,
683		   (val & NETCRR_SR) ? 1 : 0);
684
685	val = netc_reg_read(priv->prb, PRB_NETCSR);
686	seq_printf(s, "[PRB NETCSR] State:%d Error:%d\n",
687		   (val & NETCSR_STATE) ? 1 : 0,
688		   (val & NETCSR_ERROR) ? 1 : 0);
689
690	return 0;
691}
692DEFINE_SHOW_ATTRIBUTE(netc_prb);
693
694static void netc_blk_ctrl_create_debugfs(struct netc_blk_ctrl *priv)
695{
696	struct dentry *root;
697
698	root = debugfs_create_dir("netc_blk_ctrl", NULL);
699	if (IS_ERR(root))
700		return;
701
702	priv->debugfs_root = root;
703
704	debugfs_create_file("prb", 0444, root, priv, &netc_prb_fops);
705}
706
707static void netc_blk_ctrl_remove_debugfs(struct netc_blk_ctrl *priv)
708{
709	debugfs_remove_recursive(priv->debugfs_root);
710	priv->debugfs_root = NULL;
711}
712
713#else
714
715static void netc_blk_ctrl_create_debugfs(struct netc_blk_ctrl *priv)
716{
717}
718
719static void netc_blk_ctrl_remove_debugfs(struct netc_blk_ctrl *priv)
720{
721}
722#endif
723
724static int netc_prb_check_error(struct netc_blk_ctrl *priv)
725{
726	if (netc_reg_read(priv->prb, PRB_NETCSR) & NETCSR_ERROR)
727		return -1;
728
729	return 0;
730}
731
732static const struct netc_devinfo imx95_devinfo = {
733	.flags = NETC_HAS_NETCMIX,
734	.netcmix_init = imx95_netcmix_init,
735	.ierb_init = imx95_ierb_init,
736};
737
738static const struct netc_devinfo imx94_devinfo = {
739	.flags = NETC_HAS_NETCMIX,
740	.netcmix_init = imx94_netcmix_init,
741	.ierb_init = imx94_ierb_init,
742};
743
744static const struct of_device_id netc_blk_ctrl_match[] = {
745	{ .compatible = "nxp,imx95-netc-blk-ctrl", .data = &imx95_devinfo },
746	{ .compatible = "nxp,imx94-netc-blk-ctrl", .data = &imx94_devinfo },
747	{},
748};
749MODULE_DEVICE_TABLE(of, netc_blk_ctrl_match);
750
751static int netc_blk_ctrl_probe(struct platform_device *pdev)
752{
753	struct device_node *node = pdev->dev.of_node;
754	const struct netc_devinfo *devinfo;
755	struct device *dev = &pdev->dev;
756	const struct of_device_id *id;
757	struct netc_blk_ctrl *priv;
758	struct clk *ipg_clk;
759	void __iomem *regs;
760	int err;
761
762	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
763	if (!priv)
764		return -ENOMEM;
765
766	priv->pdev = pdev;
767	ipg_clk = devm_clk_get_optional_enabled(dev, "ipg");
768	if (IS_ERR(ipg_clk))
769		return dev_err_probe(dev, PTR_ERR(ipg_clk),
770				     "Set ipg clock failed\n");
771
772	id = of_match_device(netc_blk_ctrl_match, dev);
773	if (!id)
774		return dev_err_probe(dev, -EINVAL, "Cannot match device\n");
775
776	devinfo = (struct netc_devinfo *)id->data;
777	if (!devinfo)
778		return dev_err_probe(dev, -EINVAL, "No device information\n");
779
780	priv->devinfo = devinfo;
781	regs = devm_platform_ioremap_resource_byname(pdev, "ierb");
782	if (IS_ERR(regs))
783		return dev_err_probe(dev, PTR_ERR(regs),
784				     "Missing IERB resource\n");
785
786	priv->ierb = regs;
787	regs = devm_platform_ioremap_resource_byname(pdev, "prb");
788	if (IS_ERR(regs))
789		return dev_err_probe(dev, PTR_ERR(regs),
790				     "Missing PRB resource\n");
791
792	priv->prb = regs;
793	if (devinfo->flags & NETC_HAS_NETCMIX) {
794		regs = devm_platform_ioremap_resource_byname(pdev, "netcmix");
795		if (IS_ERR(regs))
796			return dev_err_probe(dev, PTR_ERR(regs),
797					     "Missing NETCMIX resource\n");
798		priv->netcmix = regs;
799	}
800
801	platform_set_drvdata(pdev, priv);
802	if (devinfo->netcmix_init) {
803		err = devinfo->netcmix_init(pdev);
804		if (err)
805			return dev_err_probe(dev, err,
806					     "Initializing NETCMIX failed\n");
807	}
808
809	err = netc_ierb_init(pdev);
810	if (err)
811		return dev_err_probe(dev, err, "Initializing IERB failed\n");
812
813	if (netc_prb_check_error(priv) < 0)
814		dev_warn(dev, "The current IERB configuration is invalid\n");
815
816	netc_blk_ctrl_create_debugfs(priv);
817
818	err = of_platform_populate(node, NULL, NULL, dev);
819	if (err) {
820		netc_blk_ctrl_remove_debugfs(priv);
821		return dev_err_probe(dev, err, "of_platform_populate failed\n");
822	}
823
824	return 0;
825}
826
827static void netc_blk_ctrl_remove(struct platform_device *pdev)
828{
829	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
830
831	of_platform_depopulate(&pdev->dev);
832	netc_blk_ctrl_remove_debugfs(priv);
833}
834
835static struct platform_driver netc_blk_ctrl_driver = {
836	.driver = {
837		.name = "nxp-netc-blk-ctrl",
838		.of_match_table = netc_blk_ctrl_match,
839	},
840	.probe = netc_blk_ctrl_probe,
841	.remove = netc_blk_ctrl_remove,
842};
843
844module_platform_driver(netc_blk_ctrl_driver);
845
846MODULE_DESCRIPTION("NXP NETC Blocks Control Driver");
847MODULE_LICENSE("Dual BSD/GPL");