cn68xx_device.c

  1/**********************************************************************
  2 * Author: Cavium, Inc.
  3 *
  4 * Contact: support@cavium.com
  5 *          Please include "LiquidIO" in the subject.
  6 *
  7 * Copyright (c) 2003-2016 Cavium, Inc.
  8 *
  9 * This file is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License, Version 2, as
 11 * published by the Free Software Foundation.
 12 *
 13 * This file is distributed in the hope that it will be useful, but
 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 16 * NONINFRINGEMENT.  See the GNU General Public License for more details.
 17 ***********************************************************************/
 18#include <linux/pci.h>
 19#include <linux/netdevice.h>
 20#include "liquidio_common.h"
 21#include "octeon_droq.h"
 22#include "octeon_iq.h"
 23#include "response_manager.h"
 24#include "octeon_device.h"
 25#include "octeon_main.h"
 26#include "cn66xx_regs.h"
 27#include "cn66xx_device.h"
 28#include "cn68xx_device.h"
 29#include "cn68xx_regs.h"
 30
 31static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct)
 32{
 33	u32 i;
 34	u32 fifo_sizes[6] = { 3, 3, 1, 1, 1, 8 };
 35
 36	lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL);
 37	dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n",
 38		lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL));
 39
 40	for (i = 0; i < 6; i++) {
 41		/* Prevent service of instruction queue for all DMA engines
 42		 * Engine 5 will remain 0. Engines 0 - 4 will be setup by
 43		 * core.
 44		 */
 45		lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i));
 46		lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i));
 47		dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i,
 48			lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i)));
 49	}
 50
 51	/* DPI_SLI_PRT_CFG has MPS and MRRS settings that will be set
 52	 * separately.
 53	 */
 54
 55	lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL);
 56	dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n",
 57		lio_pci_readq(oct, CN6XXX_DPI_CTL));
 58}
 59
 60static int lio_cn68xx_soft_reset(struct octeon_device *oct)
 61{
 62	lio_cn6xxx_soft_reset(oct);
 63	lio_cn68xx_set_dpi_regs(oct);
 64
 65	return 0;
 66}
 67
 68static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct)
 69{
 70	struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;
 71	u64 pktctl, tx_pipe, max_oqs;
 72
 73	pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL);
 74
 75	/* 68XX specific */
 76	max_oqs = CFG_GET_OQ_MAX_Q(CHIP_CONF(oct, cn6xxx));
 77	tx_pipe  = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE);
 78	tx_pipe &= 0xffffffffff00ffffULL; /* clear out NUMP field */
 79	tx_pipe |= max_oqs << 16; /* put max_oqs in NUMP field */
 80	octeon_write_csr64(oct, CN68XX_SLI_TX_PIPE, tx_pipe);
 81
 82	if (CFG_GET_IS_SLI_BP_ON(cn68xx->conf))
 83		pktctl |= 0xF;
 84	else
 85		/* Disable per-port backpressure. */
 86		pktctl &= ~0xF;
 87	octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl);
 88}
 89
 90static int lio_cn68xx_setup_device_regs(struct octeon_device *oct)
 91{
 92	lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT);
 93	lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_256B);
 94	lio_cn6xxx_enable_error_reporting(oct);
 95
 96	lio_cn6xxx_setup_global_input_regs(oct);
 97	lio_cn68xx_setup_pkt_ctl_regs(oct);
 98	lio_cn6xxx_setup_global_output_regs(oct);
 99
100	/* Default error timeout value should be 0x200000 to avoid host hang
101	 * when reads invalid register
102	 */
103	octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL);
104
105	return 0;
106}
107
108static inline void lio_cn68xx_vendor_message_fix(struct octeon_device *oct)
109{
110	u32 val = 0;
111
112	/* Set M_VEND1_DRP and M_VEND0_DRP bits */
113	pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, &val);
114	val |= 0x3;
115	pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, val);
116}
117
118static int lio_is_210nv(struct octeon_device *oct)
119{
120	u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG);
121
122	return ((mio_qlm4_cfg & CN6XXX_MIO_QLM_CFG_MASK) == 0);
123}
124
125int lio_setup_cn68xx_octeon_device(struct octeon_device *oct)
126{
127	struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;
128	u16 card_type = LIO_410NV;
129
130	if (octeon_map_pci_barx(oct, 0, 0))
131		return 1;
132
133	if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) {
134		dev_err(&oct->pci_dev->dev, "%s CN68XX BAR1 map failed\n",
135			__func__);
136		octeon_unmap_pci_barx(oct, 0);
137		return 1;
138	}
139
140	spin_lock_init(&cn68xx->lock_for_droq_int_enb_reg);
141
142	oct->fn_list.setup_iq_regs = lio_cn6xxx_setup_iq_regs;
143	oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs;
144
145	oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs;
146	oct->fn_list.soft_reset = lio_cn68xx_soft_reset;
147	oct->fn_list.setup_device_regs = lio_cn68xx_setup_device_regs;
148	oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index;
149
150	oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup;
151	oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write;
152	oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read;
153
154	oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt;
155	oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt;
156
157	oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues;
158	oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues;
159
160	lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list);
161
162	/* Determine variant of card */
163	if (lio_is_210nv(oct))
164		card_type = LIO_210NV;
165
166	cn68xx->conf = (struct octeon_config *)
167		       oct_get_config_info(oct, card_type);
168	if (!cn68xx->conf) {
169		dev_err(&oct->pci_dev->dev, "%s No Config found for CN68XX %s\n",
170			__func__,
171			(card_type == LIO_410NV) ? LIO_410NV_NAME :
172			LIO_210NV_NAME);
173		octeon_unmap_pci_barx(oct, 0);
174		octeon_unmap_pci_barx(oct, 1);
175		return 1;
176	}
177
178	oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct);
179
180	lio_cn68xx_vendor_message_fix(oct);
181
182	return 0;
183}
184EXPORT_SYMBOL_GPL(lio_setup_cn68xx_octeon_device);