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bcmgenet.c
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linux-6.19.14/drivers/net/ethernet/broadcom/genet/bcmgenet.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2025 Broadcom 6 */ 7 8#define pr_fmt(fmt) "bcmgenet: " fmt 9 10#include <linux/acpi.h> 11#include <linux/kernel.h> 12#include <linux/module.h> 13#include <linux/sched.h> 14#include <linux/types.h> 15#include <linux/fcntl.h> 16#include <linux/interrupt.h> 17#include <linux/string.h> 18#include <linux/if_ether.h> 19#include <linux/init.h> 20#include <linux/errno.h> 21#include <linux/delay.h> 22#include <linux/platform_device.h> 23#include <linux/dma-mapping.h> 24#include <linux/pm.h> 25#include <linux/clk.h> 26#include <net/arp.h> 27 28#include <linux/mii.h> 29#include <linux/ethtool.h> 30#include <linux/netdevice.h> 31#include <linux/inetdevice.h> 32#include <linux/etherdevice.h> 33#include <linux/skbuff.h> 34#include <linux/in.h> 35#include <linux/ip.h> 36#include <linux/ipv6.h> 37#include <linux/phy.h> 38 39#include <linux/unaligned.h> 40 41#include "bcmgenet.h" 42 43/* Default highest priority queue for multi queue support */ 44#define GENET_Q1_PRIORITY 0 45#define GENET_Q0_PRIORITY 1 46 47#define GENET_Q0_RX_BD_CNT \ 48 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 49#define GENET_Q0_TX_BD_CNT \ 50 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 51 52#define RX_BUF_LENGTH 2048 53#define SKB_ALIGNMENT 32 54 55/* Tx/Rx DMA register offset, skip 256 descriptors */ 56#define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 57#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 58 59#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 60 TOTAL_DESC * DMA_DESC_SIZE) 61 62#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 63 TOTAL_DESC * DMA_DESC_SIZE) 64 65/* Forward declarations */ 66static void bcmgenet_set_rx_mode(struct net_device *dev); 67 68static inline void bcmgenet_writel(u32 value, void __iomem *offset) 69{ 70 /* MIPS chips strapped for BE will automagically configure the 71 * peripheral registers for CPU-native byte order. 72 */ 73 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 74 __raw_writel(value, offset); 75 else 76 writel_relaxed(value, offset); 77} 78 79static inline u32 bcmgenet_readl(void __iomem *offset) 80{ 81 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 82 return __raw_readl(offset); 83 else 84 return readl_relaxed(offset); 85} 86 87static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 88 void __iomem *d, u32 value) 89{ 90 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 91} 92 93static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 94 void __iomem *d, 95 dma_addr_t addr) 96{ 97 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 98 99 /* Register writes to GISB bus can take couple hundred nanoseconds 100 * and are done for each packet, save these expensive writes unless 101 * the platform is explicitly configured for 64-bits/LPAE. 102 */ 103#ifdef CONFIG_PHYS_ADDR_T_64BIT 104 if (bcmgenet_has_40bits(priv)) 105 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 106#endif 107} 108 109/* Combined address + length/status setter */ 110static inline void dmadesc_set(struct bcmgenet_priv *priv, 111 void __iomem *d, dma_addr_t addr, u32 val) 112{ 113 dmadesc_set_addr(priv, d, addr); 114 dmadesc_set_length_status(priv, d, val); 115} 116 117#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 118 119#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 120 NETIF_MSG_LINK) 121 122static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 123{ 124 if (GENET_IS_V1(priv)) 125 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 126 else 127 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 128} 129 130static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 131{ 132 if (GENET_IS_V1(priv)) 133 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 134 else 135 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 136} 137 138/* These macros are defined to deal with register map change 139 * between GENET1.1 and GENET2. Only those currently being used 140 * by driver are defined. 141 */ 142static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 143{ 144 if (GENET_IS_V1(priv)) 145 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 146 else 147 return bcmgenet_readl(priv->base + 148 priv->hw_params->tbuf_offset + TBUF_CTRL); 149} 150 151static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 152{ 153 if (GENET_IS_V1(priv)) 154 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 155 else 156 bcmgenet_writel(val, priv->base + 157 priv->hw_params->tbuf_offset + TBUF_CTRL); 158} 159 160static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 161{ 162 if (GENET_IS_V1(priv)) 163 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 164 else 165 return bcmgenet_readl(priv->base + 166 priv->hw_params->tbuf_offset + TBUF_BP_MC); 167} 168 169static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 170{ 171 if (GENET_IS_V1(priv)) 172 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 173 else 174 bcmgenet_writel(val, priv->base + 175 priv->hw_params->tbuf_offset + TBUF_BP_MC); 176} 177 178/* RX/TX DMA register accessors */ 179enum dma_reg { 180 DMA_RING_CFG = 0, 181 DMA_CTRL, 182 DMA_STATUS, 183 DMA_SCB_BURST_SIZE, 184 DMA_ARB_CTRL, 185 DMA_PRIORITY_0, 186 DMA_PRIORITY_1, 187 DMA_PRIORITY_2, 188 DMA_INDEX2RING_0, 189 DMA_INDEX2RING_1, 190 DMA_INDEX2RING_2, 191 DMA_INDEX2RING_3, 192 DMA_INDEX2RING_4, 193 DMA_INDEX2RING_5, 194 DMA_INDEX2RING_6, 195 DMA_INDEX2RING_7, 196 DMA_RING0_TIMEOUT, 197 DMA_RING1_TIMEOUT, 198 DMA_RING2_TIMEOUT, 199 DMA_RING3_TIMEOUT, 200 DMA_RING4_TIMEOUT, 201 DMA_RING5_TIMEOUT, 202 DMA_RING6_TIMEOUT, 203 DMA_RING7_TIMEOUT, 204 DMA_RING8_TIMEOUT, 205 DMA_RING9_TIMEOUT, 206 DMA_RING10_TIMEOUT, 207 DMA_RING11_TIMEOUT, 208 DMA_RING12_TIMEOUT, 209 DMA_RING13_TIMEOUT, 210 DMA_RING14_TIMEOUT, 211 DMA_RING15_TIMEOUT, 212 DMA_RING16_TIMEOUT, 213}; 214 215static const u8 bcmgenet_dma_regs_v3plus[] = { 216 [DMA_RING_CFG] = 0x00, 217 [DMA_CTRL] = 0x04, 218 [DMA_STATUS] = 0x08, 219 [DMA_SCB_BURST_SIZE] = 0x0C, 220 [DMA_ARB_CTRL] = 0x2C, 221 [DMA_PRIORITY_0] = 0x30, 222 [DMA_PRIORITY_1] = 0x34, 223 [DMA_PRIORITY_2] = 0x38, 224 [DMA_RING0_TIMEOUT] = 0x2C, 225 [DMA_RING1_TIMEOUT] = 0x30, 226 [DMA_RING2_TIMEOUT] = 0x34, 227 [DMA_RING3_TIMEOUT] = 0x38, 228 [DMA_RING4_TIMEOUT] = 0x3c, 229 [DMA_RING5_TIMEOUT] = 0x40, 230 [DMA_RING6_TIMEOUT] = 0x44, 231 [DMA_RING7_TIMEOUT] = 0x48, 232 [DMA_RING8_TIMEOUT] = 0x4c, 233 [DMA_RING9_TIMEOUT] = 0x50, 234 [DMA_RING10_TIMEOUT] = 0x54, 235 [DMA_RING11_TIMEOUT] = 0x58, 236 [DMA_RING12_TIMEOUT] = 0x5c, 237 [DMA_RING13_TIMEOUT] = 0x60, 238 [DMA_RING14_TIMEOUT] = 0x64, 239 [DMA_RING15_TIMEOUT] = 0x68, 240 [DMA_RING16_TIMEOUT] = 0x6C, 241 [DMA_INDEX2RING_0] = 0x70, 242 [DMA_INDEX2RING_1] = 0x74, 243 [DMA_INDEX2RING_2] = 0x78, 244 [DMA_INDEX2RING_3] = 0x7C, 245 [DMA_INDEX2RING_4] = 0x80, 246 [DMA_INDEX2RING_5] = 0x84, 247 [DMA_INDEX2RING_6] = 0x88, 248 [DMA_INDEX2RING_7] = 0x8C, 249}; 250 251static const u8 bcmgenet_dma_regs_v2[] = { 252 [DMA_RING_CFG] = 0x00, 253 [DMA_CTRL] = 0x04, 254 [DMA_STATUS] = 0x08, 255 [DMA_SCB_BURST_SIZE] = 0x0C, 256 [DMA_ARB_CTRL] = 0x30, 257 [DMA_PRIORITY_0] = 0x34, 258 [DMA_PRIORITY_1] = 0x38, 259 [DMA_PRIORITY_2] = 0x3C, 260 [DMA_RING0_TIMEOUT] = 0x2C, 261 [DMA_RING1_TIMEOUT] = 0x30, 262 [DMA_RING2_TIMEOUT] = 0x34, 263 [DMA_RING3_TIMEOUT] = 0x38, 264 [DMA_RING4_TIMEOUT] = 0x3c, 265 [DMA_RING5_TIMEOUT] = 0x40, 266 [DMA_RING6_TIMEOUT] = 0x44, 267 [DMA_RING7_TIMEOUT] = 0x48, 268 [DMA_RING8_TIMEOUT] = 0x4c, 269 [DMA_RING9_TIMEOUT] = 0x50, 270 [DMA_RING10_TIMEOUT] = 0x54, 271 [DMA_RING11_TIMEOUT] = 0x58, 272 [DMA_RING12_TIMEOUT] = 0x5c, 273 [DMA_RING13_TIMEOUT] = 0x60, 274 [DMA_RING14_TIMEOUT] = 0x64, 275 [DMA_RING15_TIMEOUT] = 0x68, 276 [DMA_RING16_TIMEOUT] = 0x6C, 277}; 278 279static const u8 bcmgenet_dma_regs_v1[] = { 280 [DMA_CTRL] = 0x00, 281 [DMA_STATUS] = 0x04, 282 [DMA_SCB_BURST_SIZE] = 0x0C, 283 [DMA_ARB_CTRL] = 0x30, 284 [DMA_PRIORITY_0] = 0x34, 285 [DMA_PRIORITY_1] = 0x38, 286 [DMA_PRIORITY_2] = 0x3C, 287 [DMA_RING0_TIMEOUT] = 0x2C, 288 [DMA_RING1_TIMEOUT] = 0x30, 289 [DMA_RING2_TIMEOUT] = 0x34, 290 [DMA_RING3_TIMEOUT] = 0x38, 291 [DMA_RING4_TIMEOUT] = 0x3c, 292 [DMA_RING5_TIMEOUT] = 0x40, 293 [DMA_RING6_TIMEOUT] = 0x44, 294 [DMA_RING7_TIMEOUT] = 0x48, 295 [DMA_RING8_TIMEOUT] = 0x4c, 296 [DMA_RING9_TIMEOUT] = 0x50, 297 [DMA_RING10_TIMEOUT] = 0x54, 298 [DMA_RING11_TIMEOUT] = 0x58, 299 [DMA_RING12_TIMEOUT] = 0x5c, 300 [DMA_RING13_TIMEOUT] = 0x60, 301 [DMA_RING14_TIMEOUT] = 0x64, 302 [DMA_RING15_TIMEOUT] = 0x68, 303 [DMA_RING16_TIMEOUT] = 0x6C, 304}; 305 306/* Set at runtime once bcmgenet version is known */ 307static const u8 *bcmgenet_dma_regs; 308 309static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 310{ 311 return netdev_priv(dev_get_drvdata(dev)); 312} 313 314static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 315 enum dma_reg r) 316{ 317 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 318 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 319} 320 321static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 322 u32 val, enum dma_reg r) 323{ 324 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 325 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 326} 327 328static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 329 enum dma_reg r) 330{ 331 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 332 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 333} 334 335static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 336 u32 val, enum dma_reg r) 337{ 338 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 340} 341 342/* RDMA/TDMA ring registers and accessors 343 * we merge the common fields and just prefix with T/D the registers 344 * having different meaning depending on the direction 345 */ 346enum dma_ring_reg { 347 TDMA_READ_PTR = 0, 348 RDMA_WRITE_PTR = TDMA_READ_PTR, 349 TDMA_READ_PTR_HI, 350 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 351 TDMA_CONS_INDEX, 352 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 353 TDMA_PROD_INDEX, 354 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 355 DMA_RING_BUF_SIZE, 356 DMA_START_ADDR, 357 DMA_START_ADDR_HI, 358 DMA_END_ADDR, 359 DMA_END_ADDR_HI, 360 DMA_MBUF_DONE_THRESH, 361 TDMA_FLOW_PERIOD, 362 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 363 TDMA_WRITE_PTR, 364 RDMA_READ_PTR = TDMA_WRITE_PTR, 365 TDMA_WRITE_PTR_HI, 366 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 367}; 368 369/* GENET v4 supports 40-bits pointer addressing 370 * for obvious reasons the LO and HI word parts 371 * are contiguous, but this offsets the other 372 * registers. 373 */ 374static const u8 genet_dma_ring_regs_v4[] = { 375 [TDMA_READ_PTR] = 0x00, 376 [TDMA_READ_PTR_HI] = 0x04, 377 [TDMA_CONS_INDEX] = 0x08, 378 [TDMA_PROD_INDEX] = 0x0C, 379 [DMA_RING_BUF_SIZE] = 0x10, 380 [DMA_START_ADDR] = 0x14, 381 [DMA_START_ADDR_HI] = 0x18, 382 [DMA_END_ADDR] = 0x1C, 383 [DMA_END_ADDR_HI] = 0x20, 384 [DMA_MBUF_DONE_THRESH] = 0x24, 385 [TDMA_FLOW_PERIOD] = 0x28, 386 [TDMA_WRITE_PTR] = 0x2C, 387 [TDMA_WRITE_PTR_HI] = 0x30, 388}; 389 390static const u8 genet_dma_ring_regs_v123[] = { 391 [TDMA_READ_PTR] = 0x00, 392 [TDMA_CONS_INDEX] = 0x04, 393 [TDMA_PROD_INDEX] = 0x08, 394 [DMA_RING_BUF_SIZE] = 0x0C, 395 [DMA_START_ADDR] = 0x10, 396 [DMA_END_ADDR] = 0x14, 397 [DMA_MBUF_DONE_THRESH] = 0x18, 398 [TDMA_FLOW_PERIOD] = 0x1C, 399 [TDMA_WRITE_PTR] = 0x20, 400}; 401 402/* Set at runtime once GENET version is known */ 403static const u8 *genet_dma_ring_regs; 404 405static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 406 unsigned int ring, 407 enum dma_ring_reg r) 408{ 409 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 410 (DMA_RING_SIZE * ring) + 411 genet_dma_ring_regs[r]); 412} 413 414static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 415 unsigned int ring, u32 val, 416 enum dma_ring_reg r) 417{ 418 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 419 (DMA_RING_SIZE * ring) + 420 genet_dma_ring_regs[r]); 421} 422 423static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 424 unsigned int ring, 425 enum dma_ring_reg r) 426{ 427 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 428 (DMA_RING_SIZE * ring) + 429 genet_dma_ring_regs[r]); 430} 431 432static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 433 unsigned int ring, u32 val, 434 enum dma_ring_reg r) 435{ 436 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 437 (DMA_RING_SIZE * ring) + 438 genet_dma_ring_regs[r]); 439} 440 441static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 442{ 443 u32 offset; 444 u32 reg; 445 446 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 447 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 448 reg |= (1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)) | 449 RBUF_HFB_EN; 450 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 451 } else { 452 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 453 reg = bcmgenet_hfb_reg_readl(priv, offset); 454 reg |= (1 << (f_index % 32)); 455 bcmgenet_hfb_reg_writel(priv, reg, offset); 456 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 457 reg |= RBUF_HFB_EN; 458 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 459 } 460} 461 462static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index) 463{ 464 u32 offset, reg, reg1; 465 466 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 467 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 468 reg &= ~(1 << ((f_index % 32) + RBUF_HFB_FILTER_EN_SHIFT)); 469 if (!(reg & RBUF_HFB_FILTER_EN_MASK)) 470 reg &= ~RBUF_HFB_EN; 471 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 472 } else { 473 offset = HFB_FLT_ENABLE_V3PLUS; 474 reg = bcmgenet_hfb_reg_readl(priv, offset); 475 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 476 if (f_index < 32) { 477 reg1 &= ~(1 << (f_index % 32)); 478 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32)); 479 } else { 480 reg &= ~(1 << (f_index % 32)); 481 bcmgenet_hfb_reg_writel(priv, reg, offset); 482 } 483 if (!reg && !reg1) { 484 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 485 reg &= ~RBUF_HFB_EN; 486 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 487 } 488 } 489} 490 491static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 492 u32 f_index, u32 rx_queue) 493{ 494 u32 offset; 495 u32 reg; 496 497 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 498 return; 499 500 offset = f_index / 8; 501 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 502 reg &= ~(0xF << (4 * (f_index % 8))); 503 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 504 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 505} 506 507static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 508 u32 f_index, u32 f_length) 509{ 510 u32 offset; 511 u32 reg; 512 513 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 514 offset = HFB_FLT_LEN_V2; 515 else 516 offset = HFB_FLT_LEN_V3PLUS; 517 518 offset += sizeof(u32) * 519 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4); 520 reg = bcmgenet_hfb_reg_readl(priv, offset); 521 reg &= ~(0xFF << (8 * (f_index % 4))); 522 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 523 bcmgenet_hfb_reg_writel(priv, reg, offset); 524} 525 526static int bcmgenet_hfb_validate_mask(void *mask, size_t size) 527{ 528 while (size) { 529 switch (*(unsigned char *)mask++) { 530 case 0x00: 531 case 0x0f: 532 case 0xf0: 533 case 0xff: 534 size--; 535 continue; 536 default: 537 return -EINVAL; 538 } 539 } 540 541 return 0; 542} 543 544#define VALIDATE_MASK(x) \ 545 bcmgenet_hfb_validate_mask(&(x), sizeof(x)) 546 547static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index, 548 u32 offset, void *val, void *mask, 549 size_t size) 550{ 551 u32 index, tmp; 552 553 index = f_index * priv->hw_params->hfb_filter_size + offset / 2; 554 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32)); 555 556 while (size--) { 557 if (offset++ & 1) { 558 tmp &= ~0x300FF; 559 tmp |= (*(unsigned char *)val++); 560 switch ((*(unsigned char *)mask++)) { 561 case 0xFF: 562 tmp |= 0x30000; 563 break; 564 case 0xF0: 565 tmp |= 0x20000; 566 break; 567 case 0x0F: 568 tmp |= 0x10000; 569 break; 570 } 571 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32)); 572 if (size) 573 tmp = bcmgenet_hfb_readl(priv, 574 index * sizeof(u32)); 575 } else { 576 tmp &= ~0xCFF00; 577 tmp |= (*(unsigned char *)val++) << 8; 578 switch ((*(unsigned char *)mask++)) { 579 case 0xFF: 580 tmp |= 0xC0000; 581 break; 582 case 0xF0: 583 tmp |= 0x80000; 584 break; 585 case 0x0F: 586 tmp |= 0x40000; 587 break; 588 } 589 if (!size) 590 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32)); 591 } 592 } 593 594 return 0; 595} 596 597static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv, 598 struct bcmgenet_rxnfc_rule *rule) 599{ 600 struct ethtool_rx_flow_spec *fs = &rule->fs; 601 u32 offset = 0, f_length = 0, f, q; 602 u8 val_8, mask_8; 603 __be16 val_16; 604 u16 mask_16; 605 size_t size; 606 607 f = fs->location + 1; 608 if (fs->flow_type & FLOW_MAC_EXT) { 609 bcmgenet_hfb_insert_data(priv, f, 0, 610 &fs->h_ext.h_dest, &fs->m_ext.h_dest, 611 sizeof(fs->h_ext.h_dest)); 612 } 613 614 if (fs->flow_type & FLOW_EXT) { 615 if (fs->m_ext.vlan_etype || 616 fs->m_ext.vlan_tci) { 617 bcmgenet_hfb_insert_data(priv, f, 12, 618 &fs->h_ext.vlan_etype, 619 &fs->m_ext.vlan_etype, 620 sizeof(fs->h_ext.vlan_etype)); 621 bcmgenet_hfb_insert_data(priv, f, 14, 622 &fs->h_ext.vlan_tci, 623 &fs->m_ext.vlan_tci, 624 sizeof(fs->h_ext.vlan_tci)); 625 offset += VLAN_HLEN; 626 f_length += DIV_ROUND_UP(VLAN_HLEN, 2); 627 } 628 } 629 630 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 631 case ETHER_FLOW: 632 f_length += DIV_ROUND_UP(ETH_HLEN, 2); 633 bcmgenet_hfb_insert_data(priv, f, 0, 634 &fs->h_u.ether_spec.h_dest, 635 &fs->m_u.ether_spec.h_dest, 636 sizeof(fs->h_u.ether_spec.h_dest)); 637 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN, 638 &fs->h_u.ether_spec.h_source, 639 &fs->m_u.ether_spec.h_source, 640 sizeof(fs->h_u.ether_spec.h_source)); 641 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 642 &fs->h_u.ether_spec.h_proto, 643 &fs->m_u.ether_spec.h_proto, 644 sizeof(fs->h_u.ether_spec.h_proto)); 645 break; 646 case IP_USER_FLOW: 647 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2); 648 /* Specify IP Ether Type */ 649 val_16 = htons(ETH_P_IP); 650 mask_16 = 0xFFFF; 651 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 652 &val_16, &mask_16, sizeof(val_16)); 653 bcmgenet_hfb_insert_data(priv, f, 15 + offset, 654 &fs->h_u.usr_ip4_spec.tos, 655 &fs->m_u.usr_ip4_spec.tos, 656 sizeof(fs->h_u.usr_ip4_spec.tos)); 657 bcmgenet_hfb_insert_data(priv, f, 23 + offset, 658 &fs->h_u.usr_ip4_spec.proto, 659 &fs->m_u.usr_ip4_spec.proto, 660 sizeof(fs->h_u.usr_ip4_spec.proto)); 661 bcmgenet_hfb_insert_data(priv, f, 26 + offset, 662 &fs->h_u.usr_ip4_spec.ip4src, 663 &fs->m_u.usr_ip4_spec.ip4src, 664 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 665 bcmgenet_hfb_insert_data(priv, f, 30 + offset, 666 &fs->h_u.usr_ip4_spec.ip4dst, 667 &fs->m_u.usr_ip4_spec.ip4dst, 668 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 669 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 670 break; 671 672 /* Only supports 20 byte IPv4 header */ 673 val_8 = 0x45; 674 mask_8 = 0xFF; 675 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset, 676 &val_8, &mask_8, 677 sizeof(val_8)); 678 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes); 679 bcmgenet_hfb_insert_data(priv, f, 680 ETH_HLEN + 20 + offset, 681 &fs->h_u.usr_ip4_spec.l4_4_bytes, 682 &fs->m_u.usr_ip4_spec.l4_4_bytes, 683 size); 684 f_length += DIV_ROUND_UP(size, 2); 685 break; 686 } 687 688 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length); 689 if (fs->ring_cookie == RX_CLS_FLOW_WAKE) 690 q = 0; 691 else if (fs->ring_cookie == RX_CLS_FLOW_DISC) 692 q = priv->hw_params->rx_queues + 1; 693 else 694 /* Other Rx rings are direct mapped here */ 695 q = fs->ring_cookie; 696 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, q); 697 bcmgenet_hfb_enable_filter(priv, f); 698 rule->state = BCMGENET_RXNFC_STATE_ENABLED; 699} 700 701/* bcmgenet_hfb_clear 702 * 703 * Clear Hardware Filter Block and disable all filtering. 704 */ 705static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index) 706{ 707 u32 base, i; 708 709 bcmgenet_hfb_set_filter_length(priv, f_index, 0); 710 base = f_index * priv->hw_params->hfb_filter_size; 711 for (i = 0; i < priv->hw_params->hfb_filter_size; i++) 712 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32)); 713} 714 715static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 716{ 717 u32 i; 718 719 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 720 721 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) { 722 bcmgenet_hfb_reg_writel(priv, 0, 723 HFB_FLT_ENABLE_V3PLUS); 724 bcmgenet_hfb_reg_writel(priv, 0, 725 HFB_FLT_ENABLE_V3PLUS + 4); 726 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 727 bcmgenet_rdma_writel(priv, 0, i); 728 } 729 730 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++) 731 bcmgenet_hfb_clear_filter(priv, i); 732 733 /* Enable filter 0 to send default flow to ring 0 */ 734 bcmgenet_hfb_set_filter_length(priv, 0, 4); 735 bcmgenet_hfb_enable_filter(priv, 0); 736} 737 738static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 739{ 740 int i; 741 742 INIT_LIST_HEAD(&priv->rxnfc_list); 743 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 744 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list); 745 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED; 746 } 747 748 bcmgenet_hfb_clear(priv); 749} 750 751static int bcmgenet_begin(struct net_device *dev) 752{ 753 struct bcmgenet_priv *priv = netdev_priv(dev); 754 755 /* Turn on the clock */ 756 return clk_prepare_enable(priv->clk); 757} 758 759static void bcmgenet_complete(struct net_device *dev) 760{ 761 struct bcmgenet_priv *priv = netdev_priv(dev); 762 763 /* Turn off the clock */ 764 clk_disable_unprepare(priv->clk); 765} 766 767static int bcmgenet_get_link_ksettings(struct net_device *dev, 768 struct ethtool_link_ksettings *cmd) 769{ 770 if (!netif_running(dev)) 771 return -EINVAL; 772 773 if (!dev->phydev) 774 return -ENODEV; 775 776 phy_ethtool_ksettings_get(dev->phydev, cmd); 777 778 return 0; 779} 780 781static int bcmgenet_set_link_ksettings(struct net_device *dev, 782 const struct ethtool_link_ksettings *cmd) 783{ 784 if (!netif_running(dev)) 785 return -EINVAL; 786 787 if (!dev->phydev) 788 return -ENODEV; 789 790 return phy_ethtool_ksettings_set(dev->phydev, cmd); 791} 792 793static int bcmgenet_set_features(struct net_device *dev, 794 netdev_features_t features) 795{ 796 struct bcmgenet_priv *priv = netdev_priv(dev); 797 u32 reg; 798 int ret; 799 800 ret = clk_prepare_enable(priv->clk); 801 if (ret) 802 return ret; 803 804 /* Make sure we reflect the value of CRC_CMD_FWD */ 805 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 806 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 807 808 clk_disable_unprepare(priv->clk); 809 810 return ret; 811} 812 813static u32 bcmgenet_get_msglevel(struct net_device *dev) 814{ 815 struct bcmgenet_priv *priv = netdev_priv(dev); 816 817 return priv->msg_enable; 818} 819 820static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 821{ 822 struct bcmgenet_priv *priv = netdev_priv(dev); 823 824 priv->msg_enable = level; 825} 826 827static int bcmgenet_get_coalesce(struct net_device *dev, 828 struct ethtool_coalesce *ec, 829 struct kernel_ethtool_coalesce *kernel_coal, 830 struct netlink_ext_ack *extack) 831{ 832 struct bcmgenet_priv *priv = netdev_priv(dev); 833 struct bcmgenet_rx_ring *ring; 834 unsigned int i; 835 836 ec->tx_max_coalesced_frames = 837 bcmgenet_tdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH); 838 ec->rx_max_coalesced_frames = 839 bcmgenet_rdma_ring_readl(priv, 0, DMA_MBUF_DONE_THRESH); 840 ec->rx_coalesce_usecs = 841 bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT) * 8192 / 1000; 842 843 for (i = 0; i <= priv->hw_params->rx_queues; i++) { 844 ring = &priv->rx_rings[i]; 845 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 846 } 847 848 return 0; 849} 850 851static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 852 u32 usecs, u32 pkts) 853{ 854 struct bcmgenet_priv *priv = ring->priv; 855 unsigned int i = ring->index; 856 u32 reg; 857 858 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 859 860 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 861 reg &= ~DMA_TIMEOUT_MASK; 862 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 863 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 864} 865 866static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 867 struct ethtool_coalesce *ec) 868{ 869 struct dim_cq_moder moder; 870 u32 usecs, pkts; 871 872 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 873 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 874 usecs = ring->rx_coalesce_usecs; 875 pkts = ring->rx_max_coalesced_frames; 876 877 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 878 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 879 usecs = moder.usec; 880 pkts = moder.pkts; 881 } 882 883 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 884 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 885} 886 887static int bcmgenet_set_coalesce(struct net_device *dev, 888 struct ethtool_coalesce *ec, 889 struct kernel_ethtool_coalesce *kernel_coal, 890 struct netlink_ext_ack *extack) 891{ 892 struct bcmgenet_priv *priv = netdev_priv(dev); 893 unsigned int i; 894 895 /* Base system clock is 125Mhz, DMA timeout is this reference clock 896 * divided by 1024, which yields roughly 8.192us, our maximum value 897 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 898 */ 899 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 900 ec->tx_max_coalesced_frames == 0 || 901 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 902 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 903 return -EINVAL; 904 905 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 906 return -EINVAL; 907 908 /* GENET TDMA hardware does not support a configurable timeout, but will 909 * always generate an interrupt either after MBDONE packets have been 910 * transmitted, or when the ring is empty. 911 */ 912 913 /* Program all TX queues with the same values, as there is no 914 * ethtool knob to do coalescing on a per-queue basis 915 */ 916 for (i = 0; i <= priv->hw_params->tx_queues; i++) 917 bcmgenet_tdma_ring_writel(priv, i, 918 ec->tx_max_coalesced_frames, 919 DMA_MBUF_DONE_THRESH); 920 921 for (i = 0; i <= priv->hw_params->rx_queues; i++) 922 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 923 924 return 0; 925} 926 927static void bcmgenet_get_pauseparam(struct net_device *dev, 928 struct ethtool_pauseparam *epause) 929{ 930 struct bcmgenet_priv *priv; 931 u32 umac_cmd; 932 933 priv = netdev_priv(dev); 934 935 epause->autoneg = priv->autoneg_pause; 936 937 if (netif_carrier_ok(dev)) { 938 /* report active state when link is up */ 939 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD); 940 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE); 941 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE); 942 } else { 943 /* otherwise report stored settings */ 944 epause->tx_pause = priv->tx_pause; 945 epause->rx_pause = priv->rx_pause; 946 } 947} 948 949static int bcmgenet_set_pauseparam(struct net_device *dev, 950 struct ethtool_pauseparam *epause) 951{ 952 struct bcmgenet_priv *priv = netdev_priv(dev); 953 954 if (!dev->phydev) 955 return -ENODEV; 956 957 if (!phy_validate_pause(dev->phydev, epause)) 958 return -EINVAL; 959 960 priv->autoneg_pause = !!epause->autoneg; 961 priv->tx_pause = !!epause->tx_pause; 962 priv->rx_pause = !!epause->rx_pause; 963 964 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 965 966 return 0; 967} 968 969/* standard ethtool support functions. */ 970enum bcmgenet_stat_type { 971 BCMGENET_STAT_RTNL = -1, 972 BCMGENET_STAT_MIB_RX, 973 BCMGENET_STAT_MIB_TX, 974 BCMGENET_STAT_RUNT, 975 BCMGENET_STAT_MISC, 976 BCMGENET_STAT_SOFT, 977 BCMGENET_STAT_SOFT64, 978}; 979 980struct bcmgenet_stats { 981 char stat_string[ETH_GSTRING_LEN]; 982 int stat_sizeof; 983 int stat_offset; 984 enum bcmgenet_stat_type type; 985 /* reg offset from UMAC base for misc counters */ 986 u16 reg_offset; 987 /* sync for u64 stats counters */ 988 int syncp_offset; 989}; 990 991#define STAT_RTNL(m) { \ 992 .stat_string = __stringify(m), \ 993 .stat_sizeof = sizeof(((struct rtnl_link_stats64 *)0)->m), \ 994 .stat_offset = offsetof(struct rtnl_link_stats64, m), \ 995 .type = BCMGENET_STAT_RTNL, \ 996} 997 998#define STAT_GENET_MIB(str, m, _type) { \ 999 .stat_string = str, \ 1000 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1001 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1002 .type = _type, \ 1003} 1004 1005#define STAT_GENET_SOFT_MIB64(str, s, m) { \ 1006 .stat_string = str, \ 1007 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->s.m), \ 1008 .stat_offset = offsetof(struct bcmgenet_priv, s.m), \ 1009 .type = BCMGENET_STAT_SOFT64, \ 1010 .syncp_offset = offsetof(struct bcmgenet_priv, s.syncp), \ 1011} 1012 1013#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 1014#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 1015#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 1016#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 1017 1018#define STAT_GENET_MISC(str, m, offset) { \ 1019 .stat_string = str, \ 1020 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1021 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1022 .type = BCMGENET_STAT_MISC, \ 1023 .reg_offset = offset, \ 1024} 1025 1026#define STAT_GENET_Q(num) \ 1027 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_packets", \ 1028 tx_rings[num].stats64, packets), \ 1029 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_bytes", \ 1030 tx_rings[num].stats64, bytes), \ 1031 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_errors", \ 1032 tx_rings[num].stats64, errors), \ 1033 STAT_GENET_SOFT_MIB64("txq" __stringify(num) "_dropped", \ 1034 tx_rings[num].stats64, dropped), \ 1035 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_bytes", \ 1036 rx_rings[num].stats64, bytes), \ 1037 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_packets", \ 1038 rx_rings[num].stats64, packets), \ 1039 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_errors", \ 1040 rx_rings[num].stats64, errors), \ 1041 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_dropped", \ 1042 rx_rings[num].stats64, dropped), \ 1043 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_multicast", \ 1044 rx_rings[num].stats64, multicast), \ 1045 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_missed", \ 1046 rx_rings[num].stats64, missed), \ 1047 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_length_errors", \ 1048 rx_rings[num].stats64, length_errors), \ 1049 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_over_errors", \ 1050 rx_rings[num].stats64, over_errors), \ 1051 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_crc_errors", \ 1052 rx_rings[num].stats64, crc_errors), \ 1053 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_frame_errors", \ 1054 rx_rings[num].stats64, frame_errors), \ 1055 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_fragmented_errors", \ 1056 rx_rings[num].stats64, fragmented_errors), \ 1057 STAT_GENET_SOFT_MIB64("rxq" __stringify(num) "_broadcast", \ 1058 rx_rings[num].stats64, broadcast) 1059 1060/* There is a 0xC gap between the end of RX and beginning of TX stats and then 1061 * between the end of TX stats and the beginning of the RX RUNT 1062 */ 1063#define BCMGENET_STAT_OFFSET 0xc 1064 1065/* Hardware counters must be kept in sync because the order/offset 1066 * is important here (order in structure declaration = order in hardware) 1067 */ 1068static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 1069 /* general stats */ 1070 STAT_RTNL(rx_packets), 1071 STAT_RTNL(tx_packets), 1072 STAT_RTNL(rx_bytes), 1073 STAT_RTNL(tx_bytes), 1074 STAT_RTNL(rx_errors), 1075 STAT_RTNL(tx_errors), 1076 STAT_RTNL(rx_dropped), 1077 STAT_RTNL(tx_dropped), 1078 STAT_RTNL(multicast), 1079 STAT_RTNL(rx_missed_errors), 1080 STAT_RTNL(rx_length_errors), 1081 STAT_RTNL(rx_over_errors), 1082 STAT_RTNL(rx_crc_errors), 1083 STAT_RTNL(rx_frame_errors), 1084 /* UniMAC RSV counters */ 1085 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 1086 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 1087 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 1088 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 1089 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 1090 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 1091 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 1092 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 1093 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 1094 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 1095 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 1096 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 1097 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 1098 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 1099 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 1100 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 1101 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 1102 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 1103 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 1104 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 1105 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 1106 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 1107 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 1108 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 1109 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 1110 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 1111 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 1112 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 1113 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 1114 /* UniMAC TSV counters */ 1115 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 1116 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 1117 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 1118 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 1119 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 1120 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 1121 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 1122 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 1123 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 1124 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 1125 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 1126 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 1127 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 1128 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 1129 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 1130 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 1131 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 1132 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 1133 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 1134 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 1135 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 1136 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 1137 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 1138 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 1139 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 1140 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 1141 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 1142 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 1143 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 1144 /* UniMAC RUNT counters */ 1145 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 1146 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 1147 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 1148 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 1149 /* Misc UniMAC counters */ 1150 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 1151 UMAC_RBUF_OVFL_CNT_V1), 1152 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 1153 UMAC_RBUF_ERR_CNT_V1), 1154 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 1155 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 1156 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 1157 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 1158 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 1159 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 1160 mib.tx_realloc_tsb_failed), 1161 /* Per TX queues */ 1162 STAT_GENET_Q(0), 1163 STAT_GENET_Q(1), 1164 STAT_GENET_Q(2), 1165 STAT_GENET_Q(3), 1166 STAT_GENET_Q(4), 1167}; 1168 1169#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 1170 1171#define BCMGENET_STATS64_ADD(stats, m, v) \ 1172 do { \ 1173 u64_stats_update_begin(&stats->syncp); \ 1174 u64_stats_add(&stats->m, v); \ 1175 u64_stats_update_end(&stats->syncp); \ 1176 } while (0) 1177 1178#define BCMGENET_STATS64_INC(stats, m) \ 1179 do { \ 1180 u64_stats_update_begin(&stats->syncp); \ 1181 u64_stats_inc(&stats->m); \ 1182 u64_stats_update_end(&stats->syncp); \ 1183 } while (0) 1184 1185static void bcmgenet_get_drvinfo(struct net_device *dev, 1186 struct ethtool_drvinfo *info) 1187{ 1188 strscpy(info->driver, "bcmgenet", sizeof(info->driver)); 1189} 1190 1191static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 1192{ 1193 switch (string_set) { 1194 case ETH_SS_STATS: 1195 return BCMGENET_STATS_LEN; 1196 default: 1197 return -EOPNOTSUPP; 1198 } 1199} 1200 1201static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 1202 u8 *data) 1203{ 1204 const char *str; 1205 int i; 1206 1207 switch (stringset) { 1208 case ETH_SS_STATS: 1209 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1210 str = bcmgenet_gstrings_stats[i].stat_string; 1211 ethtool_puts(&data, str); 1212 } 1213 break; 1214 } 1215} 1216 1217static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 1218{ 1219 u16 new_offset; 1220 u32 val; 1221 1222 switch (offset) { 1223 case UMAC_RBUF_OVFL_CNT_V1: 1224 if (GENET_IS_V2(priv)) 1225 new_offset = RBUF_OVFL_CNT_V2; 1226 else 1227 new_offset = RBUF_OVFL_CNT_V3PLUS; 1228 1229 val = bcmgenet_rbuf_readl(priv, new_offset); 1230 /* clear if overflowed */ 1231 if (val == ~0) 1232 bcmgenet_rbuf_writel(priv, 0, new_offset); 1233 break; 1234 case UMAC_RBUF_ERR_CNT_V1: 1235 if (GENET_IS_V2(priv)) 1236 new_offset = RBUF_ERR_CNT_V2; 1237 else 1238 new_offset = RBUF_ERR_CNT_V3PLUS; 1239 1240 val = bcmgenet_rbuf_readl(priv, new_offset); 1241 /* clear if overflowed */ 1242 if (val == ~0) 1243 bcmgenet_rbuf_writel(priv, 0, new_offset); 1244 break; 1245 default: 1246 val = bcmgenet_umac_readl(priv, offset); 1247 /* clear if overflowed */ 1248 if (val == ~0) 1249 bcmgenet_umac_writel(priv, 0, offset); 1250 break; 1251 } 1252 1253 return val; 1254} 1255 1256static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 1257{ 1258 int i, j = 0; 1259 1260 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1261 const struct bcmgenet_stats *s; 1262 u8 offset = 0; 1263 u32 val = 0; 1264 char *p; 1265 1266 s = &bcmgenet_gstrings_stats[i]; 1267 switch (s->type) { 1268 case BCMGENET_STAT_RTNL: 1269 case BCMGENET_STAT_SOFT: 1270 case BCMGENET_STAT_SOFT64: 1271 continue; 1272 case BCMGENET_STAT_RUNT: 1273 offset += BCMGENET_STAT_OFFSET; 1274 fallthrough; 1275 case BCMGENET_STAT_MIB_TX: 1276 offset += BCMGENET_STAT_OFFSET; 1277 fallthrough; 1278 case BCMGENET_STAT_MIB_RX: 1279 val = bcmgenet_umac_readl(priv, 1280 UMAC_MIB_START + j + offset); 1281 offset = 0; /* Reset Offset */ 1282 break; 1283 case BCMGENET_STAT_MISC: 1284 if (GENET_IS_V1(priv)) { 1285 val = bcmgenet_umac_readl(priv, s->reg_offset); 1286 /* clear if overflowed */ 1287 if (val == ~0) 1288 bcmgenet_umac_writel(priv, 0, 1289 s->reg_offset); 1290 } else { 1291 val = bcmgenet_update_stat_misc(priv, 1292 s->reg_offset); 1293 } 1294 break; 1295 } 1296 1297 j += s->stat_sizeof; 1298 p = (char *)priv + s->stat_offset; 1299 *(u32 *)p = val; 1300 } 1301} 1302 1303static void bcmgenet_get_ethtool_stats(struct net_device *dev, 1304 struct ethtool_stats *stats, 1305 u64 *data) 1306{ 1307 struct bcmgenet_priv *priv = netdev_priv(dev); 1308 struct rtnl_link_stats64 stats64; 1309 struct u64_stats_sync *syncp; 1310 unsigned int start; 1311 int i; 1312 1313 if (netif_running(dev)) 1314 bcmgenet_update_mib_counters(priv); 1315 1316 dev_get_stats(dev, &stats64); 1317 1318 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1319 const struct bcmgenet_stats *s; 1320 char *p; 1321 1322 s = &bcmgenet_gstrings_stats[i]; 1323 p = (char *)priv; 1324 1325 if (s->type == BCMGENET_STAT_SOFT64) { 1326 syncp = (struct u64_stats_sync *)(p + s->syncp_offset); 1327 do { 1328 start = u64_stats_fetch_begin(syncp); 1329 data[i] = u64_stats_read((u64_stats_t *)(p + s->stat_offset)); 1330 } while (u64_stats_fetch_retry(syncp, start)); 1331 } else { 1332 if (s->type == BCMGENET_STAT_RTNL) 1333 p = (char *)&stats64; 1334 1335 p += s->stat_offset; 1336 if (sizeof(unsigned long) != sizeof(u32) && 1337 s->stat_sizeof == sizeof(unsigned long)) 1338 data[i] = *(unsigned long *)p; 1339 else 1340 data[i] = *(u32 *)p; 1341 } 1342 } 1343} 1344 1345void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1346{ 1347 struct bcmgenet_priv *priv = netdev_priv(dev); 1348 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1349 u32 reg; 1350 1351 if (enable && !priv->clk_eee_enabled) { 1352 clk_prepare_enable(priv->clk_eee); 1353 priv->clk_eee_enabled = true; 1354 } 1355 1356 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1357 if (enable) 1358 reg |= EEE_EN; 1359 else 1360 reg &= ~EEE_EN; 1361 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1362 1363 /* Enable EEE and switch to a 27Mhz clock automatically */ 1364 reg = bcmgenet_readl(priv->base + off); 1365 if (enable) 1366 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1367 else 1368 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1369 bcmgenet_writel(reg, priv->base + off); 1370 1371 /* Do the same for thing for RBUF */ 1372 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1373 if (enable) 1374 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1375 else 1376 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1377 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1378 1379 if (!enable && priv->clk_eee_enabled) { 1380 clk_disable_unprepare(priv->clk_eee); 1381 priv->clk_eee_enabled = false; 1382 } 1383 1384} 1385 1386static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_keee *e) 1387{ 1388 struct bcmgenet_priv *priv = netdev_priv(dev); 1389 int ret; 1390 1391 if (GENET_IS_V1(priv)) 1392 return -EOPNOTSUPP; 1393 1394 if (!dev->phydev) 1395 return -ENODEV; 1396 1397 ret = phy_ethtool_get_eee(dev->phydev, e); 1398 if (ret) 1399 return ret; 1400 1401 /* tx_lpi_timer is maintained by the MAC hardware register; the 1402 * PHY-level eee_cfg timer is not set for GENET. 1403 */ 1404 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1405 1406 return 0; 1407} 1408 1409static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_keee *e) 1410{ 1411 struct bcmgenet_priv *priv = netdev_priv(dev); 1412 1413 if (GENET_IS_V1(priv)) 1414 return -EOPNOTSUPP; 1415 1416 if (!dev->phydev) 1417 return -ENODEV; 1418 1419 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1420 1421 return phy_ethtool_set_eee(dev->phydev, e); 1422} 1423 1424static int bcmgenet_validate_flow(struct net_device *dev, 1425 struct ethtool_rxnfc *cmd) 1426{ 1427 struct ethtool_usrip4_spec *l4_mask; 1428 struct ethhdr *eth_mask; 1429 1430 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES && 1431 cmd->fs.location != RX_CLS_LOC_ANY) { 1432 netdev_err(dev, "rxnfc: Invalid location (%d)\n", 1433 cmd->fs.location); 1434 return -EINVAL; 1435 } 1436 1437 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1438 case IP_USER_FLOW: 1439 l4_mask = &cmd->fs.m_u.usr_ip4_spec; 1440 /* don't allow mask which isn't valid */ 1441 if (VALIDATE_MASK(l4_mask->ip4src) || 1442 VALIDATE_MASK(l4_mask->ip4dst) || 1443 VALIDATE_MASK(l4_mask->l4_4_bytes) || 1444 VALIDATE_MASK(l4_mask->proto) || 1445 VALIDATE_MASK(l4_mask->ip_ver) || 1446 VALIDATE_MASK(l4_mask->tos)) { 1447 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1448 return -EINVAL; 1449 } 1450 break; 1451 case ETHER_FLOW: 1452 eth_mask = &cmd->fs.m_u.ether_spec; 1453 /* don't allow mask which isn't valid */ 1454 if (VALIDATE_MASK(eth_mask->h_dest) || 1455 VALIDATE_MASK(eth_mask->h_source) || 1456 VALIDATE_MASK(eth_mask->h_proto)) { 1457 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1458 return -EINVAL; 1459 } 1460 break; 1461 default: 1462 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n", 1463 cmd->fs.flow_type); 1464 return -EINVAL; 1465 } 1466 1467 if ((cmd->fs.flow_type & FLOW_EXT)) { 1468 /* don't allow mask which isn't valid */ 1469 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) || 1470 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) { 1471 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1472 return -EINVAL; 1473 } 1474 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) { 1475 netdev_err(dev, "rxnfc: user-def not supported\n"); 1476 return -EINVAL; 1477 } 1478 } 1479 1480 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) { 1481 /* don't allow mask which isn't valid */ 1482 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) { 1483 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1484 return -EINVAL; 1485 } 1486 } 1487 1488 return 0; 1489} 1490 1491static int bcmgenet_insert_flow(struct net_device *dev, 1492 struct ethtool_rxnfc *cmd) 1493{ 1494 struct bcmgenet_priv *priv = netdev_priv(dev); 1495 struct bcmgenet_rxnfc_rule *loc_rule; 1496 int err, i; 1497 1498 if (priv->hw_params->hfb_filter_size < 128) { 1499 netdev_err(dev, "rxnfc: Not supported by this device\n"); 1500 return -EINVAL; 1501 } 1502 1503 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues && 1504 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE && 1505 cmd->fs.ring_cookie != RX_CLS_FLOW_DISC) { 1506 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n", 1507 cmd->fs.ring_cookie); 1508 return -EINVAL; 1509 } 1510 1511 err = bcmgenet_validate_flow(dev, cmd); 1512 if (err) 1513 return err; 1514 1515 if (cmd->fs.location == RX_CLS_LOC_ANY) { 1516 list_for_each_entry(loc_rule, &priv->rxnfc_list, list) { 1517 cmd->fs.location = loc_rule->fs.location; 1518 err = memcmp(&loc_rule->fs, &cmd->fs, 1519 sizeof(struct ethtool_rx_flow_spec)); 1520 if (!err) 1521 /* rule exists so return current location */ 1522 return 0; 1523 } 1524 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1525 loc_rule = &priv->rxnfc_rules[i]; 1526 if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1527 cmd->fs.location = i; 1528 break; 1529 } 1530 } 1531 if (i == MAX_NUM_OF_FS_RULES) { 1532 cmd->fs.location = RX_CLS_LOC_ANY; 1533 return -ENOSPC; 1534 } 1535 } else { 1536 loc_rule = &priv->rxnfc_rules[cmd->fs.location]; 1537 } 1538 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1539 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1); 1540 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1541 list_del(&loc_rule->list); 1542 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1); 1543 } 1544 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1545 memcpy(&loc_rule->fs, &cmd->fs, 1546 sizeof(struct ethtool_rx_flow_spec)); 1547 1548 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule); 1549 1550 list_add_tail(&loc_rule->list, &priv->rxnfc_list); 1551 1552 return 0; 1553} 1554 1555static int bcmgenet_delete_flow(struct net_device *dev, 1556 struct ethtool_rxnfc *cmd) 1557{ 1558 struct bcmgenet_priv *priv = netdev_priv(dev); 1559 struct bcmgenet_rxnfc_rule *rule; 1560 int err = 0; 1561 1562 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1563 return -EINVAL; 1564 1565 rule = &priv->rxnfc_rules[cmd->fs.location]; 1566 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1567 err = -ENOENT; 1568 goto out; 1569 } 1570 1571 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1572 bcmgenet_hfb_disable_filter(priv, cmd->fs.location + 1); 1573 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1574 list_del(&rule->list); 1575 bcmgenet_hfb_clear_filter(priv, cmd->fs.location + 1); 1576 } 1577 rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1578 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec)); 1579 1580out: 1581 return err; 1582} 1583 1584static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1585{ 1586 struct bcmgenet_priv *priv = netdev_priv(dev); 1587 int err = 0; 1588 1589 switch (cmd->cmd) { 1590 case ETHTOOL_SRXCLSRLINS: 1591 err = bcmgenet_insert_flow(dev, cmd); 1592 break; 1593 case ETHTOOL_SRXCLSRLDEL: 1594 err = bcmgenet_delete_flow(dev, cmd); 1595 break; 1596 default: 1597 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n", 1598 cmd->cmd); 1599 return -EINVAL; 1600 } 1601 1602 return err; 1603} 1604 1605static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1606 int loc) 1607{ 1608 struct bcmgenet_priv *priv = netdev_priv(dev); 1609 struct bcmgenet_rxnfc_rule *rule; 1610 int err = 0; 1611 1612 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1613 return -EINVAL; 1614 1615 rule = &priv->rxnfc_rules[loc]; 1616 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) 1617 err = -ENOENT; 1618 else 1619 memcpy(&cmd->fs, &rule->fs, 1620 sizeof(struct ethtool_rx_flow_spec)); 1621 1622 return err; 1623} 1624 1625static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv) 1626{ 1627 struct list_head *pos; 1628 int res = 0; 1629 1630 list_for_each(pos, &priv->rxnfc_list) 1631 res++; 1632 1633 return res; 1634} 1635 1636static u32 bcmgenet_get_rx_ring_count(struct net_device *dev) 1637{ 1638 struct bcmgenet_priv *priv = netdev_priv(dev); 1639 1640 return priv->hw_params->rx_queues ?: 1; 1641} 1642 1643static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1644 u32 *rule_locs) 1645{ 1646 struct bcmgenet_priv *priv = netdev_priv(dev); 1647 struct bcmgenet_rxnfc_rule *rule; 1648 int err = 0; 1649 int i = 0; 1650 1651 switch (cmd->cmd) { 1652 case ETHTOOL_GRXCLSRLCNT: 1653 cmd->rule_cnt = bcmgenet_get_num_flows(priv); 1654 cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL; 1655 break; 1656 case ETHTOOL_GRXCLSRULE: 1657 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location); 1658 break; 1659 case ETHTOOL_GRXCLSRLALL: 1660 list_for_each_entry(rule, &priv->rxnfc_list, list) 1661 if (i < cmd->rule_cnt) 1662 rule_locs[i++] = rule->fs.location; 1663 cmd->rule_cnt = i; 1664 cmd->data = MAX_NUM_OF_FS_RULES; 1665 break; 1666 default: 1667 err = -EOPNOTSUPP; 1668 break; 1669 } 1670 1671 return err; 1672} 1673 1674/* standard ethtool support functions. */ 1675static const struct ethtool_ops bcmgenet_ethtool_ops = { 1676 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1677 ETHTOOL_COALESCE_MAX_FRAMES | 1678 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1679 .begin = bcmgenet_begin, 1680 .complete = bcmgenet_complete, 1681 .get_strings = bcmgenet_get_strings, 1682 .get_sset_count = bcmgenet_get_sset_count, 1683 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1684 .get_drvinfo = bcmgenet_get_drvinfo, 1685 .get_link = ethtool_op_get_link, 1686 .get_msglevel = bcmgenet_get_msglevel, 1687 .set_msglevel = bcmgenet_set_msglevel, 1688 .get_wol = bcmgenet_get_wol, 1689 .set_wol = bcmgenet_set_wol, 1690 .get_eee = bcmgenet_get_eee, 1691 .set_eee = bcmgenet_set_eee, 1692 .nway_reset = phy_ethtool_nway_reset, 1693 .get_coalesce = bcmgenet_get_coalesce, 1694 .set_coalesce = bcmgenet_set_coalesce, 1695 .get_link_ksettings = bcmgenet_get_link_ksettings, 1696 .set_link_ksettings = bcmgenet_set_link_ksettings, 1697 .get_ts_info = ethtool_op_get_ts_info, 1698 .get_rxnfc = bcmgenet_get_rxnfc, 1699 .set_rxnfc = bcmgenet_set_rxnfc, 1700 .get_rx_ring_count = bcmgenet_get_rx_ring_count, 1701 .get_pauseparam = bcmgenet_get_pauseparam, 1702 .set_pauseparam = bcmgenet_set_pauseparam, 1703}; 1704 1705/* Power down the unimac, based on mode. */ 1706static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1707 enum bcmgenet_power_mode mode) 1708{ 1709 int ret = 0; 1710 u32 reg; 1711 1712 switch (mode) { 1713 case GENET_POWER_CABLE_SENSE: 1714 phy_detach(priv->dev->phydev); 1715 break; 1716 1717 case GENET_POWER_WOL_MAGIC: 1718 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1719 break; 1720 1721 case GENET_POWER_PASSIVE: 1722 /* Power down LED */ 1723 if (bcmgenet_has_ext(priv)) { 1724 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1725 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) 1726 reg |= EXT_PWR_DOWN_PHY_EN | 1727 EXT_PWR_DOWN_PHY_RD | 1728 EXT_PWR_DOWN_PHY_SD | 1729 EXT_PWR_DOWN_PHY_RX | 1730 EXT_PWR_DOWN_PHY_TX | 1731 EXT_IDDQ_GLBL_PWR; 1732 else 1733 reg |= EXT_PWR_DOWN_PHY; 1734 1735 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1736 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1737 1738 bcmgenet_phy_power_set(priv->dev, false); 1739 } 1740 break; 1741 default: 1742 break; 1743 } 1744 1745 return ret; 1746} 1747 1748static int bcmgenet_power_up(struct bcmgenet_priv *priv, 1749 enum bcmgenet_power_mode mode) 1750{ 1751 int ret = 0; 1752 u32 reg; 1753 1754 if (!bcmgenet_has_ext(priv)) 1755 return ret; 1756 1757 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1758 1759 switch (mode) { 1760 case GENET_POWER_PASSIVE: 1761 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS | 1762 EXT_ENERGY_DET_MASK); 1763 if (GENET_IS_V5(priv) && !bcmgenet_has_ephy_16nm(priv)) { 1764 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1765 EXT_PWR_DOWN_PHY_RD | 1766 EXT_PWR_DOWN_PHY_SD | 1767 EXT_PWR_DOWN_PHY_RX | 1768 EXT_PWR_DOWN_PHY_TX | 1769 EXT_IDDQ_GLBL_PWR); 1770 reg |= EXT_PHY_RESET; 1771 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1772 mdelay(1); 1773 1774 reg &= ~EXT_PHY_RESET; 1775 } else { 1776 reg &= ~EXT_PWR_DOWN_PHY; 1777 reg |= EXT_PWR_DN_EN_LD; 1778 } 1779 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1780 bcmgenet_phy_power_set(priv->dev, true); 1781 break; 1782 1783 case GENET_POWER_CABLE_SENSE: 1784 /* enable APD */ 1785 if (!GENET_IS_V5(priv)) { 1786 reg |= EXT_PWR_DN_EN_LD; 1787 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1788 } 1789 break; 1790 case GENET_POWER_WOL_MAGIC: 1791 ret = bcmgenet_wol_power_up_cfg(priv, mode); 1792 break; 1793 default: 1794 break; 1795 } 1796 1797 return ret; 1798} 1799 1800static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1801 struct bcmgenet_tx_ring *ring) 1802{ 1803 struct enet_cb *tx_cb_ptr; 1804 1805 tx_cb_ptr = ring->cbs; 1806 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1807 1808 /* Advancing local write pointer */ 1809 if (ring->write_ptr == ring->end_ptr) 1810 ring->write_ptr = ring->cb_ptr; 1811 else 1812 ring->write_ptr++; 1813 1814 return tx_cb_ptr; 1815} 1816 1817static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1818 struct bcmgenet_tx_ring *ring) 1819{ 1820 struct enet_cb *tx_cb_ptr; 1821 1822 tx_cb_ptr = ring->cbs; 1823 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1824 1825 /* Rewinding local write pointer */ 1826 if (ring->write_ptr == ring->cb_ptr) 1827 ring->write_ptr = ring->end_ptr; 1828 else 1829 ring->write_ptr--; 1830 1831 return tx_cb_ptr; 1832} 1833 1834static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1835{ 1836 bcmgenet_intrl2_1_writel(ring->priv, 1837 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1838 INTRL2_CPU_MASK_SET); 1839} 1840 1841static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1842{ 1843 bcmgenet_intrl2_1_writel(ring->priv, 1844 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1845 INTRL2_CPU_MASK_CLEAR); 1846} 1847 1848static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1849{ 1850 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1851 INTRL2_CPU_MASK_CLEAR); 1852} 1853 1854static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1855{ 1856 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1857 INTRL2_CPU_MASK_SET); 1858} 1859 1860/* Simple helper to free a transmit control block's resources 1861 * Returns an skb when the last transmit control block associated with the 1862 * skb is freed. The skb should be freed by the caller if necessary. 1863 */ 1864static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1865 struct enet_cb *cb) 1866{ 1867 struct sk_buff *skb; 1868 1869 skb = cb->skb; 1870 1871 if (skb) { 1872 cb->skb = NULL; 1873 if (cb == GENET_CB(skb)->first_cb) 1874 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1875 dma_unmap_len(cb, dma_len), 1876 DMA_TO_DEVICE); 1877 else 1878 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1879 dma_unmap_len(cb, dma_len), 1880 DMA_TO_DEVICE); 1881 dma_unmap_addr_set(cb, dma_addr, 0); 1882 1883 if (cb == GENET_CB(skb)->last_cb) 1884 return skb; 1885 1886 } else if (dma_unmap_addr(cb, dma_addr)) { 1887 dma_unmap_page(dev, 1888 dma_unmap_addr(cb, dma_addr), 1889 dma_unmap_len(cb, dma_len), 1890 DMA_TO_DEVICE); 1891 dma_unmap_addr_set(cb, dma_addr, 0); 1892 } 1893 1894 return NULL; 1895} 1896 1897/* Simple helper to free a receive control block's resources */ 1898static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1899 struct enet_cb *cb) 1900{ 1901 struct sk_buff *skb; 1902 1903 skb = cb->skb; 1904 cb->skb = NULL; 1905 1906 if (dma_unmap_addr(cb, dma_addr)) { 1907 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1908 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1909 dma_unmap_addr_set(cb, dma_addr, 0); 1910 } 1911 1912 return skb; 1913} 1914 1915/* Unlocked version of the reclaim routine */ 1916static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1917 struct bcmgenet_tx_ring *ring) 1918{ 1919 struct bcmgenet_tx_stats64 *stats = &ring->stats64; 1920 struct bcmgenet_priv *priv = netdev_priv(dev); 1921 unsigned int txbds_processed = 0; 1922 unsigned int bytes_compl = 0; 1923 unsigned int pkts_compl = 0; 1924 unsigned int txbds_ready; 1925 unsigned int c_index; 1926 struct sk_buff *skb; 1927 1928 /* Clear status before servicing to reduce spurious interrupts */ 1929 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), INTRL2_CPU_CLEAR); 1930 1931 /* Compute how many buffers are transmitted since last xmit call */ 1932 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1933 & DMA_C_INDEX_MASK; 1934 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1935 1936 netif_dbg(priv, tx_done, dev, 1937 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1938 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1939 1940 /* Reclaim transmitted buffers */ 1941 while (txbds_processed < txbds_ready) { 1942 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1943 &priv->tx_cbs[ring->clean_ptr]); 1944 if (skb) { 1945 pkts_compl++; 1946 bytes_compl += GENET_CB(skb)->bytes_sent; 1947 dev_consume_skb_any(skb); 1948 } 1949 1950 txbds_processed++; 1951 if (likely(ring->clean_ptr < ring->end_ptr)) 1952 ring->clean_ptr++; 1953 else 1954 ring->clean_ptr = ring->cb_ptr; 1955 } 1956 1957 ring->free_bds += txbds_processed; 1958 ring->c_index = c_index; 1959 1960 u64_stats_update_begin(&stats->syncp); 1961 u64_stats_add(&stats->packets, pkts_compl); 1962 u64_stats_add(&stats->bytes, bytes_compl); 1963 u64_stats_update_end(&stats->syncp); 1964 1965 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->index), 1966 pkts_compl, bytes_compl); 1967 1968 return txbds_processed; 1969} 1970 1971static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1972 struct bcmgenet_tx_ring *ring, 1973 bool all) 1974{ 1975 struct bcmgenet_priv *priv = netdev_priv(dev); 1976 struct device *kdev = &priv->pdev->dev; 1977 unsigned int released, drop, wr_ptr; 1978 struct enet_cb *cb_ptr; 1979 struct sk_buff *skb; 1980 1981 spin_lock_bh(&ring->lock); 1982 released = __bcmgenet_tx_reclaim(dev, ring); 1983 if (all) { 1984 skb = NULL; 1985 drop = (ring->prod_index - ring->c_index) & DMA_C_INDEX_MASK; 1986 released += drop; 1987 ring->prod_index = ring->c_index & DMA_C_INDEX_MASK; 1988 while (drop--) { 1989 cb_ptr = bcmgenet_put_txcb(priv, ring); 1990 skb = cb_ptr->skb; 1991 bcmgenet_free_tx_cb(kdev, cb_ptr); 1992 if (skb && cb_ptr == GENET_CB(skb)->first_cb) { 1993 dev_consume_skb_any(skb); 1994 skb = NULL; 1995 } 1996 } 1997 if (skb) 1998 dev_consume_skb_any(skb); 1999 bcmgenet_tdma_ring_writel(priv, ring->index, 2000 ring->prod_index, TDMA_PROD_INDEX); 2001 wr_ptr = ring->write_ptr * WORDS_PER_BD(priv); 2002 bcmgenet_tdma_ring_writel(priv, ring->index, wr_ptr, 2003 TDMA_WRITE_PTR); 2004 } 2005 spin_unlock_bh(&ring->lock); 2006 2007 return released; 2008} 2009 2010static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 2011{ 2012 struct bcmgenet_tx_ring *ring = 2013 container_of(napi, struct bcmgenet_tx_ring, napi); 2014 unsigned int work_done = 0; 2015 struct netdev_queue *txq; 2016 2017 spin_lock(&ring->lock); 2018 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 2019 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 2020 txq = netdev_get_tx_queue(ring->priv->dev, ring->index); 2021 netif_tx_wake_queue(txq); 2022 } 2023 spin_unlock(&ring->lock); 2024 2025 if (work_done == 0) { 2026 napi_complete(napi); 2027 bcmgenet_tx_ring_int_enable(ring); 2028 2029 return 0; 2030 } 2031 2032 return budget; 2033} 2034 2035static void bcmgenet_tx_reclaim_all(struct net_device *dev) 2036{ 2037 struct bcmgenet_priv *priv = netdev_priv(dev); 2038 int i = 0; 2039 2040 do { 2041 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i++], true); 2042 } while (i <= priv->hw_params->tx_queues && netif_is_multiqueue(dev)); 2043} 2044 2045/* Reallocate the SKB to put enough headroom in front of it and insert 2046 * the transmit checksum offsets in the descriptors 2047 */ 2048static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 2049 struct sk_buff *skb, 2050 struct bcmgenet_tx_ring *ring) 2051{ 2052 struct bcmgenet_tx_stats64 *stats = &ring->stats64; 2053 struct bcmgenet_priv *priv = netdev_priv(dev); 2054 struct status_64 *status = NULL; 2055 struct sk_buff *new_skb; 2056 u16 offset; 2057 u8 ip_proto; 2058 __be16 ip_ver; 2059 u32 tx_csum_info; 2060 2061 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 2062 /* If 64 byte status block enabled, must make sure skb has 2063 * enough headroom for us to insert 64B status block. 2064 */ 2065 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 2066 if (!new_skb) { 2067 dev_kfree_skb_any(skb); 2068 priv->mib.tx_realloc_tsb_failed++; 2069 BCMGENET_STATS64_INC(stats, dropped); 2070 return NULL; 2071 } 2072 dev_consume_skb_any(skb); 2073 skb = new_skb; 2074 priv->mib.tx_realloc_tsb++; 2075 } 2076 2077 skb_push(skb, sizeof(*status)); 2078 status = (struct status_64 *)skb->data; 2079 2080 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2081 ip_ver = skb->protocol; 2082 switch (ip_ver) { 2083 case htons(ETH_P_IP): 2084 ip_proto = ip_hdr(skb)->protocol; 2085 break; 2086 case htons(ETH_P_IPV6): 2087 ip_proto = ipv6_hdr(skb)->nexthdr; 2088 break; 2089 default: 2090 /* don't use UDP flag */ 2091 ip_proto = 0; 2092 break; 2093 } 2094 2095 offset = skb_checksum_start_offset(skb) - sizeof(*status); 2096 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 2097 (offset + skb->csum_offset) | 2098 STATUS_TX_CSUM_LV; 2099 2100 /* Set the special UDP flag for UDP */ 2101 if (ip_proto == IPPROTO_UDP) 2102 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 2103 2104 status->tx_csum_info = tx_csum_info; 2105 } 2106 2107 return skb; 2108} 2109 2110static void bcmgenet_hide_tsb(struct sk_buff *skb) 2111{ 2112 __skb_pull(skb, sizeof(struct status_64)); 2113} 2114 2115static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 2116{ 2117 struct bcmgenet_priv *priv = netdev_priv(dev); 2118 struct device *kdev = &priv->pdev->dev; 2119 struct bcmgenet_tx_ring *ring = NULL; 2120 struct enet_cb *tx_cb_ptr; 2121 struct netdev_queue *txq; 2122 int nr_frags, index; 2123 dma_addr_t mapping; 2124 unsigned int size; 2125 skb_frag_t *frag; 2126 u32 len_stat; 2127 int ret; 2128 int i; 2129 2130 index = skb_get_queue_mapping(skb); 2131 /* Mapping strategy: 2132 * queue_mapping = 0, unclassified, packet xmited through ring 0 2133 * queue_mapping = 1, goes to ring 1. (highest priority queue) 2134 * queue_mapping = 2, goes to ring 2. 2135 * queue_mapping = 3, goes to ring 3. 2136 * queue_mapping = 4, goes to ring 4. 2137 */ 2138 ring = &priv->tx_rings[index]; 2139 txq = netdev_get_tx_queue(dev, index); 2140 2141 nr_frags = skb_shinfo(skb)->nr_frags; 2142 2143 spin_lock(&ring->lock); 2144 if (ring->free_bds <= (nr_frags + 1)) { 2145 if (!netif_tx_queue_stopped(txq)) 2146 netif_tx_stop_queue(txq); 2147 ret = NETDEV_TX_BUSY; 2148 goto out; 2149 } 2150 2151 /* Retain how many bytes will be sent on the wire, without TSB inserted 2152 * by transmit checksum offload 2153 */ 2154 GENET_CB(skb)->bytes_sent = skb->len; 2155 2156 /* add the Transmit Status Block */ 2157 skb = bcmgenet_add_tsb(dev, skb, ring); 2158 if (!skb) { 2159 ret = NETDEV_TX_OK; 2160 goto out; 2161 } 2162 2163 for (i = 0; i <= nr_frags; i++) { 2164 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 2165 2166 BUG_ON(!tx_cb_ptr); 2167 2168 if (!i) { 2169 /* Transmit single SKB or head of fragment list */ 2170 GENET_CB(skb)->first_cb = tx_cb_ptr; 2171 size = skb_headlen(skb); 2172 mapping = dma_map_single(kdev, skb->data, size, 2173 DMA_TO_DEVICE); 2174 } else { 2175 /* xmit fragment */ 2176 frag = &skb_shinfo(skb)->frags[i - 1]; 2177 size = skb_frag_size(frag); 2178 mapping = skb_frag_dma_map(kdev, frag, 0, size, 2179 DMA_TO_DEVICE); 2180 } 2181 2182 ret = dma_mapping_error(kdev, mapping); 2183 if (ret) { 2184 priv->mib.tx_dma_failed++; 2185 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 2186 ret = NETDEV_TX_OK; 2187 goto out_unmap_frags; 2188 } 2189 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 2190 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 2191 2192 tx_cb_ptr->skb = skb; 2193 2194 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 2195 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 2196 2197 /* Note: if we ever change from DMA_TX_APPEND_CRC below we 2198 * will need to restore software padding of "runt" packets 2199 */ 2200 len_stat |= DMA_TX_APPEND_CRC; 2201 2202 if (!i) { 2203 len_stat |= DMA_SOP; 2204 if (skb->ip_summed == CHECKSUM_PARTIAL) 2205 len_stat |= DMA_TX_DO_CSUM; 2206 } 2207 if (i == nr_frags) 2208 len_stat |= DMA_EOP; 2209 2210 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 2211 } 2212 2213 GENET_CB(skb)->last_cb = tx_cb_ptr; 2214 2215 bcmgenet_hide_tsb(skb); 2216 skb_tx_timestamp(skb); 2217 2218 /* Decrement total BD count and advance our write pointer */ 2219 ring->free_bds -= nr_frags + 1; 2220 ring->prod_index += nr_frags + 1; 2221 ring->prod_index &= DMA_P_INDEX_MASK; 2222 2223 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 2224 2225 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 2226 netif_tx_stop_queue(txq); 2227 2228 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 2229 /* Packets are ready, update producer index */ 2230 bcmgenet_tdma_ring_writel(priv, ring->index, 2231 ring->prod_index, TDMA_PROD_INDEX); 2232out: 2233 spin_unlock(&ring->lock); 2234 2235 return ret; 2236 2237out_unmap_frags: 2238 /* Back up for failed control block mapping */ 2239 bcmgenet_put_txcb(priv, ring); 2240 2241 /* Unmap successfully mapped control blocks */ 2242 while (i-- > 0) { 2243 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 2244 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 2245 } 2246 2247 dev_kfree_skb(skb); 2248 goto out; 2249} 2250 2251static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 2252 struct enet_cb *cb) 2253{ 2254 struct device *kdev = &priv->pdev->dev; 2255 struct sk_buff *skb; 2256 struct sk_buff *rx_skb; 2257 dma_addr_t mapping; 2258 2259 /* Allocate a new Rx skb */ 2260 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT, 2261 GFP_ATOMIC | __GFP_NOWARN); 2262 if (!skb) { 2263 priv->mib.alloc_rx_buff_failed++; 2264 netif_err(priv, rx_err, priv->dev, 2265 "%s: Rx skb allocation failed\n", __func__); 2266 return NULL; 2267 } 2268 2269 /* DMA-map the new Rx skb */ 2270 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 2271 DMA_FROM_DEVICE); 2272 if (dma_mapping_error(kdev, mapping)) { 2273 priv->mib.rx_dma_failed++; 2274 dev_kfree_skb_any(skb); 2275 netif_err(priv, rx_err, priv->dev, 2276 "%s: Rx skb DMA mapping failed\n", __func__); 2277 return NULL; 2278 } 2279 2280 /* Grab the current Rx skb from the ring and DMA-unmap it */ 2281 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 2282 2283 /* Put the new Rx skb on the ring */ 2284 cb->skb = skb; 2285 dma_unmap_addr_set(cb, dma_addr, mapping); 2286 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 2287 dmadesc_set_addr(priv, cb->bd_addr, mapping); 2288 2289 /* Return the current Rx skb to caller */ 2290 return rx_skb; 2291} 2292 2293/* bcmgenet_desc_rx - descriptor based rx process. 2294 * this could be called from bottom half, or from NAPI polling method. 2295 */ 2296static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 2297 unsigned int budget) 2298{ 2299 struct bcmgenet_rx_stats64 *stats = &ring->stats64; 2300 struct bcmgenet_priv *priv = ring->priv; 2301 struct net_device *dev = priv->dev; 2302 struct enet_cb *cb; 2303 struct sk_buff *skb; 2304 u32 dma_length_status; 2305 unsigned long dma_flag; 2306 int len; 2307 unsigned int rxpktprocessed = 0, rxpkttoprocess; 2308 unsigned int bytes_processed = 0; 2309 unsigned int p_index, mask; 2310 unsigned int discards; 2311 2312 /* Clear status before servicing to reduce spurious interrupts */ 2313 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 2314 bcmgenet_intrl2_1_writel(priv, mask, INTRL2_CPU_CLEAR); 2315 2316 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 2317 2318 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 2319 DMA_P_INDEX_DISCARD_CNT_MASK; 2320 if (discards > ring->old_discards) { 2321 discards = discards - ring->old_discards; 2322 BCMGENET_STATS64_ADD(stats, missed, discards); 2323 ring->old_discards += discards; 2324 2325 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 2326 if (ring->old_discards >= 0xC000) { 2327 ring->old_discards = 0; 2328 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 2329 RDMA_PROD_INDEX); 2330 } 2331 } 2332 2333 p_index &= DMA_P_INDEX_MASK; 2334 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 2335 2336 netif_dbg(priv, rx_status, dev, 2337 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 2338 2339 while ((rxpktprocessed < rxpkttoprocess) && 2340 (rxpktprocessed < budget)) { 2341 struct status_64 *status; 2342 __be16 rx_csum; 2343 2344 cb = &priv->rx_cbs[ring->read_ptr]; 2345 skb = bcmgenet_rx_refill(priv, cb); 2346 2347 if (unlikely(!skb)) { 2348 BCMGENET_STATS64_INC(stats, dropped); 2349 goto next; 2350 } 2351 2352 status = (struct status_64 *)skb->data; 2353 dma_length_status = status->length_status; 2354 if (dev->features & NETIF_F_RXCSUM) { 2355 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 2356 if (rx_csum) { 2357 skb->csum = (__force __wsum)ntohs(rx_csum); 2358 skb->ip_summed = CHECKSUM_COMPLETE; 2359 } 2360 } 2361 2362 /* DMA flags and length are still valid no matter how 2363 * we got the Receive Status Vector (64B RSB or register) 2364 */ 2365 dma_flag = dma_length_status & 0xffff; 2366 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 2367 2368 netif_dbg(priv, rx_status, dev, 2369 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 2370 __func__, p_index, ring->c_index, 2371 ring->read_ptr, dma_length_status); 2372 2373 if (unlikely(len > RX_BUF_LENGTH)) { 2374 netif_err(priv, rx_status, dev, "oversized packet\n"); 2375 BCMGENET_STATS64_INC(stats, length_errors); 2376 dev_kfree_skb_any(skb); 2377 goto next; 2378 } 2379 2380 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 2381 netif_err(priv, rx_status, dev, 2382 "dropping fragmented packet!\n"); 2383 BCMGENET_STATS64_INC(stats, fragmented_errors); 2384 dev_kfree_skb_any(skb); 2385 goto next; 2386 } 2387 2388 /* report errors */ 2389 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 2390 DMA_RX_OV | 2391 DMA_RX_NO | 2392 DMA_RX_LG | 2393 DMA_RX_RXER))) { 2394 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 2395 (unsigned int)dma_flag); 2396 u64_stats_update_begin(&stats->syncp); 2397 if (dma_flag & DMA_RX_CRC_ERROR) 2398 u64_stats_inc(&stats->crc_errors); 2399 if (dma_flag & DMA_RX_OV) 2400 u64_stats_inc(&stats->over_errors); 2401 if (dma_flag & DMA_RX_NO) 2402 u64_stats_inc(&stats->frame_errors); 2403 if (dma_flag & DMA_RX_LG) 2404 u64_stats_inc(&stats->length_errors); 2405 if ((dma_flag & (DMA_RX_CRC_ERROR | 2406 DMA_RX_OV | 2407 DMA_RX_NO | 2408 DMA_RX_LG | 2409 DMA_RX_RXER)) == DMA_RX_RXER) 2410 u64_stats_inc(&stats->errors); 2411 u64_stats_update_end(&stats->syncp); 2412 dev_kfree_skb_any(skb); 2413 goto next; 2414 } /* error packet */ 2415 2416 skb_put(skb, len); 2417 2418 /* remove RSB and hardware 2bytes added for IP alignment */ 2419 skb_pull(skb, 66); 2420 len -= 66; 2421 2422 if (priv->crc_fwd_en) { 2423 skb_trim(skb, len - ETH_FCS_LEN); 2424 len -= ETH_FCS_LEN; 2425 } 2426 2427 bytes_processed += len; 2428 2429 /*Finish setting up the received SKB and send it to the kernel*/ 2430 skb->protocol = eth_type_trans(skb, priv->dev); 2431 2432 u64_stats_update_begin(&stats->syncp); 2433 u64_stats_inc(&stats->packets); 2434 u64_stats_add(&stats->bytes, len); 2435 if (dma_flag & DMA_RX_MULT) 2436 u64_stats_inc(&stats->multicast); 2437 else if (dma_flag & DMA_RX_BRDCAST) 2438 u64_stats_inc(&stats->broadcast); 2439 u64_stats_update_end(&stats->syncp); 2440 2441 /* Notify kernel */ 2442 napi_gro_receive(&ring->napi, skb); 2443 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 2444 2445next: 2446 rxpktprocessed++; 2447 if (likely(ring->read_ptr < ring->end_ptr)) 2448 ring->read_ptr++; 2449 else 2450 ring->read_ptr = ring->cb_ptr; 2451 2452 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 2453 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 2454 } 2455 2456 ring->dim.bytes = bytes_processed; 2457 ring->dim.packets = rxpktprocessed; 2458 2459 return rxpktprocessed; 2460} 2461 2462/* Rx NAPI polling method */ 2463static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 2464{ 2465 struct bcmgenet_rx_ring *ring = container_of(napi, 2466 struct bcmgenet_rx_ring, napi); 2467 struct dim_sample dim_sample = {}; 2468 unsigned int work_done; 2469 2470 work_done = bcmgenet_desc_rx(ring, budget); 2471 2472 if (work_done < budget && napi_complete_done(napi, work_done)) 2473 bcmgenet_rx_ring_int_enable(ring); 2474 2475 if (ring->dim.use_dim) { 2476 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 2477 ring->dim.bytes, &dim_sample); 2478 net_dim(&ring->dim.dim, &dim_sample); 2479 } 2480 2481 return work_done; 2482} 2483 2484static void bcmgenet_dim_work(struct work_struct *work) 2485{ 2486 struct dim *dim = container_of(work, struct dim, work); 2487 struct bcmgenet_net_dim *ndim = 2488 container_of(dim, struct bcmgenet_net_dim, dim); 2489 struct bcmgenet_rx_ring *ring = 2490 container_of(ndim, struct bcmgenet_rx_ring, dim); 2491 struct dim_cq_moder cur_profile = 2492 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 2493 2494 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 2495 dim->state = DIM_START_MEASURE; 2496} 2497 2498/* Assign skb to RX DMA descriptor. */ 2499static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 2500 struct bcmgenet_rx_ring *ring) 2501{ 2502 struct enet_cb *cb; 2503 struct sk_buff *skb; 2504 int i; 2505 2506 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2507 2508 /* loop here for each buffer needing assign */ 2509 for (i = 0; i < ring->size; i++) { 2510 cb = ring->cbs + i; 2511 skb = bcmgenet_rx_refill(priv, cb); 2512 if (skb) 2513 dev_consume_skb_any(skb); 2514 if (!cb->skb) 2515 return -ENOMEM; 2516 } 2517 2518 return 0; 2519} 2520 2521static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 2522{ 2523 struct sk_buff *skb; 2524 struct enet_cb *cb; 2525 int i; 2526 2527 for (i = 0; i < priv->num_rx_bds; i++) { 2528 cb = &priv->rx_cbs[i]; 2529 2530 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 2531 if (skb) 2532 dev_consume_skb_any(skb); 2533 } 2534} 2535 2536static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 2537{ 2538 u32 reg; 2539 2540 spin_lock_bh(&priv->reg_lock); 2541 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2542 if (reg & CMD_SW_RESET) { 2543 spin_unlock_bh(&priv->reg_lock); 2544 return; 2545 } 2546 if (enable) 2547 reg |= mask; 2548 else 2549 reg &= ~mask; 2550 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2551 spin_unlock_bh(&priv->reg_lock); 2552 2553 /* UniMAC stops on a packet boundary, wait for a full-size packet 2554 * to be processed 2555 */ 2556 if (enable == 0) 2557 usleep_range(1000, 2000); 2558} 2559 2560static void reset_umac(struct bcmgenet_priv *priv) 2561{ 2562 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 2563 bcmgenet_rbuf_ctrl_set(priv, 0); 2564 udelay(10); 2565 2566 /* issue soft reset and disable MAC while updating its registers */ 2567 spin_lock_bh(&priv->reg_lock); 2568 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 2569 udelay(2); 2570 spin_unlock_bh(&priv->reg_lock); 2571} 2572 2573static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2574{ 2575 /* Mask all interrupts.*/ 2576 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2577 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2578 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2579 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2580} 2581 2582static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2583{ 2584 u32 int0_enable = 0; 2585 2586 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2587 * and MoCA PHY 2588 */ 2589 if (priv->internal_phy) { 2590 int0_enable |= UMAC_IRQ_LINK_EVENT; 2591 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2592 int0_enable |= UMAC_IRQ_PHY_DET_R; 2593 } else if (priv->ext_phy) { 2594 int0_enable |= UMAC_IRQ_LINK_EVENT; 2595 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2596 if (bcmgenet_has_moca_link_det(priv)) 2597 int0_enable |= UMAC_IRQ_LINK_EVENT; 2598 } 2599 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2600} 2601 2602static void init_umac(struct bcmgenet_priv *priv) 2603{ 2604 struct device *kdev = &priv->pdev->dev; 2605 u32 reg; 2606 u32 int0_enable = 0; 2607 2608 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2609 2610 reset_umac(priv); 2611 2612 /* clear tx/rx counter */ 2613 bcmgenet_umac_writel(priv, 2614 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2615 UMAC_MIB_CTRL); 2616 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2617 2618 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2619 2620 /* init tx registers, enable TSB */ 2621 reg = bcmgenet_tbuf_ctrl_get(priv); 2622 reg |= TBUF_64B_EN; 2623 bcmgenet_tbuf_ctrl_set(priv, reg); 2624 2625 /* init rx registers, enable ip header optimization and RSB */ 2626 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2627 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 2628 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2629 2630 /* enable rx checksumming */ 2631 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 2632 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 2633 /* If UniMAC forwards CRC, we need to skip over it to get 2634 * a valid CHK bit to be set in the per-packet status word 2635 */ 2636 if (priv->crc_fwd_en) 2637 reg |= RBUF_SKIP_FCS; 2638 else 2639 reg &= ~RBUF_SKIP_FCS; 2640 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 2641 2642 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2643 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2644 2645 bcmgenet_intr_disable(priv); 2646 2647 /* Configure backpressure vectors for MoCA */ 2648 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2649 reg = bcmgenet_bp_mc_get(priv); 2650 reg |= BIT(priv->hw_params->bp_in_en_shift); 2651 2652 /* bp_mask: back pressure mask */ 2653 if (netif_is_multiqueue(priv->dev)) 2654 reg |= priv->hw_params->bp_in_mask; 2655 else 2656 reg &= ~priv->hw_params->bp_in_mask; 2657 bcmgenet_bp_mc_set(priv, reg); 2658 } 2659 2660 /* Enable MDIO interrupts on GENET v3+ */ 2661 if (bcmgenet_has_mdio_intr(priv)) 2662 int0_enable |= UMAC_IRQ_MDIO_EVENT; 2663 2664 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2665 2666 dev_dbg(kdev, "done init umac\n"); 2667} 2668 2669static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2670 void (*cb)(struct work_struct *work)) 2671{ 2672 struct bcmgenet_net_dim *dim = &ring->dim; 2673 2674 INIT_WORK(&dim->dim.work, cb); 2675 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2676 dim->event_ctr = 0; 2677 dim->packets = 0; 2678 dim->bytes = 0; 2679} 2680 2681static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2682{ 2683 struct bcmgenet_net_dim *dim = &ring->dim; 2684 struct dim_cq_moder moder; 2685 u32 usecs, pkts; 2686 2687 usecs = ring->rx_coalesce_usecs; 2688 pkts = ring->rx_max_coalesced_frames; 2689 2690 /* If DIM was enabled, re-apply default parameters */ 2691 if (dim->use_dim) { 2692 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2693 usecs = moder.usec; 2694 pkts = moder.pkts; 2695 } 2696 2697 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2698} 2699 2700/* Initialize a Tx ring along with corresponding hardware registers */ 2701static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2702 unsigned int index, unsigned int size, 2703 unsigned int start_ptr, unsigned int end_ptr) 2704{ 2705 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2706 u32 words_per_bd = WORDS_PER_BD(priv); 2707 u32 flow_period_val = 0; 2708 2709 spin_lock_init(&ring->lock); 2710 ring->priv = priv; 2711 ring->index = index; 2712 ring->cbs = priv->tx_cbs + start_ptr; 2713 ring->size = size; 2714 ring->clean_ptr = start_ptr; 2715 ring->c_index = 0; 2716 ring->free_bds = size; 2717 ring->write_ptr = start_ptr; 2718 ring->cb_ptr = start_ptr; 2719 ring->end_ptr = end_ptr - 1; 2720 ring->prod_index = 0; 2721 2722 /* Set flow period for ring != 0 */ 2723 if (index) 2724 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2725 2726 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2727 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2728 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2729 /* Disable rate control for now */ 2730 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2731 TDMA_FLOW_PERIOD); 2732 bcmgenet_tdma_ring_writel(priv, index, 2733 ((size << DMA_RING_SIZE_SHIFT) | 2734 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2735 2736 /* Set start and end address, read and write pointers */ 2737 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2738 DMA_START_ADDR); 2739 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2740 TDMA_READ_PTR); 2741 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2742 TDMA_WRITE_PTR); 2743 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2744 DMA_END_ADDR); 2745 2746 /* Initialize Tx NAPI */ 2747 netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll); 2748} 2749 2750/* Initialize a RDMA ring */ 2751static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2752 unsigned int index, unsigned int size, 2753 unsigned int start_ptr, unsigned int end_ptr) 2754{ 2755 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2756 u32 words_per_bd = WORDS_PER_BD(priv); 2757 int ret; 2758 2759 ring->priv = priv; 2760 ring->index = index; 2761 ring->cbs = priv->rx_cbs + start_ptr; 2762 ring->size = size; 2763 ring->c_index = 0; 2764 ring->read_ptr = start_ptr; 2765 ring->cb_ptr = start_ptr; 2766 ring->end_ptr = end_ptr - 1; 2767 2768 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2769 if (ret) 2770 return ret; 2771 2772 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2773 bcmgenet_init_rx_coalesce(ring); 2774 2775 /* Initialize Rx NAPI */ 2776 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll); 2777 2778 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2779 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2780 bcmgenet_rdma_ring_writel(priv, index, 2781 ((size << DMA_RING_SIZE_SHIFT) | 2782 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2783 bcmgenet_rdma_ring_writel(priv, index, 2784 (DMA_FC_THRESH_LO << 2785 DMA_XOFF_THRESHOLD_SHIFT) | 2786 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2787 2788 /* Set start and end address, read and write pointers */ 2789 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2790 DMA_START_ADDR); 2791 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2792 RDMA_READ_PTR); 2793 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2794 RDMA_WRITE_PTR); 2795 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2796 DMA_END_ADDR); 2797 2798 return ret; 2799} 2800 2801static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2802{ 2803 unsigned int i; 2804 struct bcmgenet_tx_ring *ring; 2805 2806 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2807 ring = &priv->tx_rings[i]; 2808 napi_enable(&ring->napi); 2809 bcmgenet_tx_ring_int_enable(ring); 2810 } 2811} 2812 2813static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2814{ 2815 unsigned int i; 2816 struct bcmgenet_tx_ring *ring; 2817 2818 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2819 ring = &priv->tx_rings[i]; 2820 napi_disable(&ring->napi); 2821 } 2822} 2823 2824static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2825{ 2826 unsigned int i; 2827 struct bcmgenet_tx_ring *ring; 2828 2829 for (i = 0; i <= priv->hw_params->tx_queues; ++i) { 2830 ring = &priv->tx_rings[i]; 2831 netif_napi_del(&ring->napi); 2832 } 2833} 2834 2835static int bcmgenet_tdma_disable(struct bcmgenet_priv *priv) 2836{ 2837 int timeout = 0; 2838 u32 reg, mask; 2839 2840 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2841 mask = (1 << (priv->hw_params->tx_queues + 1)) - 1; 2842 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2843 reg &= ~mask; 2844 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2845 2846 /* Check DMA status register to confirm DMA is disabled */ 2847 while (timeout++ < DMA_TIMEOUT_VAL) { 2848 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2849 if ((reg & mask) == mask) 2850 return 0; 2851 2852 udelay(1); 2853 } 2854 2855 return -ETIMEDOUT; 2856} 2857 2858static int bcmgenet_rdma_disable(struct bcmgenet_priv *priv) 2859{ 2860 int timeout = 0; 2861 u32 reg, mask; 2862 2863 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2864 mask = (1 << (priv->hw_params->rx_queues + 1)) - 1; 2865 mask = (mask << DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2866 reg &= ~mask; 2867 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2868 2869 /* Check DMA status register to confirm DMA is disabled */ 2870 while (timeout++ < DMA_TIMEOUT_VAL) { 2871 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2872 if ((reg & mask) == mask) 2873 return 0; 2874 2875 udelay(1); 2876 } 2877 2878 return -ETIMEDOUT; 2879} 2880 2881/* Initialize Tx queues 2882 * 2883 * Queues 1-4 are priority-based, each one has 32 descriptors, 2884 * with queue 1 being the highest priority queue. 2885 * 2886 * Queue 0 is the default Tx queue with 2887 * GENET_Q0_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2888 * 2889 * The transmit control block pool is then partitioned as follows: 2890 * - Tx queue 0 uses tx_cbs[0..127] 2891 * - Tx queue 1 uses tx_cbs[128..159] 2892 * - Tx queue 2 uses tx_cbs[160..191] 2893 * - Tx queue 3 uses tx_cbs[192..223] 2894 * - Tx queue 4 uses tx_cbs[224..255] 2895 */ 2896static void bcmgenet_init_tx_queues(struct net_device *dev) 2897{ 2898 struct bcmgenet_priv *priv = netdev_priv(dev); 2899 unsigned int start = 0, end = GENET_Q0_TX_BD_CNT; 2900 u32 i, ring_mask, dma_priority[3] = {0, 0, 0}; 2901 2902 /* Enable strict priority arbiter mode */ 2903 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2904 2905 /* Initialize Tx priority queues */ 2906 for (i = 0; i <= priv->hw_params->tx_queues; i++) { 2907 bcmgenet_init_tx_ring(priv, i, end - start, start, end); 2908 start = end; 2909 end += priv->hw_params->tx_bds_per_q; 2910 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2911 (i ? GENET_Q1_PRIORITY : GENET_Q0_PRIORITY) 2912 << DMA_PRIO_REG_SHIFT(i); 2913 } 2914 2915 /* Set Tx queue priorities */ 2916 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2917 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2918 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2919 2920 /* Configure Tx queues as descriptor rings */ 2921 ring_mask = (1 << (priv->hw_params->tx_queues + 1)) - 1; 2922 bcmgenet_tdma_writel(priv, ring_mask, DMA_RING_CFG); 2923 2924 /* Enable Tx rings */ 2925 ring_mask <<= DMA_RING_BUF_EN_SHIFT; 2926 bcmgenet_tdma_writel(priv, ring_mask, DMA_CTRL); 2927} 2928 2929static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2930{ 2931 unsigned int i; 2932 struct bcmgenet_rx_ring *ring; 2933 2934 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2935 ring = &priv->rx_rings[i]; 2936 napi_enable(&ring->napi); 2937 bcmgenet_rx_ring_int_enable(ring); 2938 } 2939} 2940 2941static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2942{ 2943 unsigned int i; 2944 struct bcmgenet_rx_ring *ring; 2945 2946 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2947 ring = &priv->rx_rings[i]; 2948 napi_disable(&ring->napi); 2949 cancel_work_sync(&ring->dim.dim.work); 2950 } 2951} 2952 2953static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2954{ 2955 unsigned int i; 2956 struct bcmgenet_rx_ring *ring; 2957 2958 for (i = 0; i <= priv->hw_params->rx_queues; ++i) { 2959 ring = &priv->rx_rings[i]; 2960 netif_napi_del(&ring->napi); 2961 } 2962} 2963 2964/* Initialize Rx queues 2965 * 2966 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2967 * used to direct traffic to these queues. 2968 * 2969 * Queue 0 is also the default Rx queue with GENET_Q0_RX_BD_CNT descriptors. 2970 */ 2971static int bcmgenet_init_rx_queues(struct net_device *dev) 2972{ 2973 struct bcmgenet_priv *priv = netdev_priv(dev); 2974 unsigned int start = 0, end = GENET_Q0_RX_BD_CNT; 2975 u32 i, ring_mask; 2976 int ret; 2977 2978 /* Initialize Rx priority queues */ 2979 for (i = 0; i <= priv->hw_params->rx_queues; i++) { 2980 ret = bcmgenet_init_rx_ring(priv, i, end - start, start, end); 2981 if (ret) 2982 return ret; 2983 2984 start = end; 2985 end += priv->hw_params->rx_bds_per_q; 2986 } 2987 2988 /* Configure Rx queues as descriptor rings */ 2989 ring_mask = (1 << (priv->hw_params->rx_queues + 1)) - 1; 2990 bcmgenet_rdma_writel(priv, ring_mask, DMA_RING_CFG); 2991 2992 /* Enable Rx rings */ 2993 ring_mask <<= DMA_RING_BUF_EN_SHIFT; 2994 bcmgenet_rdma_writel(priv, ring_mask, DMA_CTRL); 2995 2996 return 0; 2997} 2998 2999static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 3000{ 3001 int ret = 0; 3002 3003 /* Disable TDMA to stop add more frames in TX DMA */ 3004 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) { 3005 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 3006 ret = -ETIMEDOUT; 3007 } 3008 3009 /* Wait 10ms for packet drain in both tx and rx dma */ 3010 usleep_range(10000, 20000); 3011 3012 /* Disable RDMA */ 3013 if (-ETIMEDOUT == bcmgenet_rdma_disable(priv)) { 3014 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 3015 ret = -ETIMEDOUT; 3016 } 3017 3018 return ret; 3019} 3020 3021static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 3022{ 3023 struct netdev_queue *txq; 3024 int i; 3025 3026 bcmgenet_fini_rx_napi(priv); 3027 bcmgenet_fini_tx_napi(priv); 3028 3029 for (i = 0; i <= priv->hw_params->tx_queues; i++) { 3030 txq = netdev_get_tx_queue(priv->dev, i); 3031 netdev_tx_reset_queue(txq); 3032 } 3033 3034 bcmgenet_free_rx_buffers(priv); 3035 kfree(priv->rx_cbs); 3036 kfree(priv->tx_cbs); 3037} 3038 3039/* init_edma: Initialize DMA control register */ 3040static int bcmgenet_init_dma(struct bcmgenet_priv *priv, bool flush_rx) 3041{ 3042 struct enet_cb *cb; 3043 unsigned int i; 3044 int ret; 3045 u32 reg; 3046 3047 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 3048 3049 /* Disable TX DMA */ 3050 ret = bcmgenet_tdma_disable(priv); 3051 if (ret) { 3052 netdev_err(priv->dev, "failed to halt Tx DMA\n"); 3053 return ret; 3054 } 3055 3056 /* Disable RX DMA */ 3057 ret = bcmgenet_rdma_disable(priv); 3058 if (ret) { 3059 netdev_err(priv->dev, "failed to halt Rx DMA\n"); 3060 return ret; 3061 } 3062 3063 /* Flush TX queues */ 3064 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 3065 udelay(10); 3066 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 3067 3068 if (flush_rx) { 3069 reg = bcmgenet_rbuf_ctrl_get(priv); 3070 bcmgenet_rbuf_ctrl_set(priv, reg | BIT(0)); 3071 udelay(10); 3072 bcmgenet_rbuf_ctrl_set(priv, reg); 3073 udelay(10); 3074 } 3075 3076 /* Initialize common Rx ring structures */ 3077 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 3078 priv->num_rx_bds = TOTAL_DESC; 3079 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 3080 GFP_KERNEL); 3081 if (!priv->rx_cbs) 3082 return -ENOMEM; 3083 3084 for (i = 0; i < priv->num_rx_bds; i++) { 3085 cb = priv->rx_cbs + i; 3086 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 3087 } 3088 3089 /* Initialize common TX ring structures */ 3090 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 3091 priv->num_tx_bds = TOTAL_DESC; 3092 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 3093 GFP_KERNEL); 3094 if (!priv->tx_cbs) { 3095 kfree(priv->rx_cbs); 3096 return -ENOMEM; 3097 } 3098 3099 for (i = 0; i < priv->num_tx_bds; i++) { 3100 cb = priv->tx_cbs + i; 3101 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 3102 } 3103 3104 /* Init rDma */ 3105 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 3106 DMA_SCB_BURST_SIZE); 3107 3108 /* Initialize Rx queues */ 3109 ret = bcmgenet_init_rx_queues(priv->dev); 3110 if (ret) { 3111 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 3112 bcmgenet_free_rx_buffers(priv); 3113 kfree(priv->rx_cbs); 3114 kfree(priv->tx_cbs); 3115 return ret; 3116 } 3117 3118 /* Init tDma */ 3119 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 3120 DMA_SCB_BURST_SIZE); 3121 3122 /* Initialize Tx queues */ 3123 bcmgenet_init_tx_queues(priv->dev); 3124 3125 /* Enable RX/TX DMA */ 3126 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3127 reg |= DMA_EN; 3128 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3129 3130 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3131 reg |= DMA_EN; 3132 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3133 3134 return 0; 3135} 3136 3137/* Interrupt bottom half */ 3138static void bcmgenet_irq_task(struct work_struct *work) 3139{ 3140 unsigned int status; 3141 struct bcmgenet_priv *priv = container_of( 3142 work, struct bcmgenet_priv, bcmgenet_irq_work); 3143 3144 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 3145 3146 spin_lock_irq(&priv->lock); 3147 status = priv->irq0_stat; 3148 priv->irq0_stat = 0; 3149 spin_unlock_irq(&priv->lock); 3150 3151 if (status & UMAC_IRQ_PHY_DET_R && 3152 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 3153 phy_init_hw(priv->dev->phydev); 3154 genphy_config_aneg(priv->dev->phydev); 3155 } 3156 3157 /* Link UP/DOWN event */ 3158 if (status & UMAC_IRQ_LINK_EVENT) 3159 phy_mac_interrupt(priv->dev->phydev); 3160 3161} 3162 3163/* bcmgenet_isr1: handle Rx and Tx queues */ 3164static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 3165{ 3166 struct bcmgenet_priv *priv = dev_id; 3167 struct bcmgenet_rx_ring *rx_ring; 3168 struct bcmgenet_tx_ring *tx_ring; 3169 unsigned int index, status; 3170 3171 /* Read irq status */ 3172 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 3173 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3174 3175 /* clear interrupts */ 3176 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 3177 3178 netif_dbg(priv, intr, priv->dev, 3179 "%s: IRQ=0x%x\n", __func__, status); 3180 3181 /* Check Rx priority queue interrupts */ 3182 for (index = 0; index <= priv->hw_params->rx_queues; index++) { 3183 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 3184 continue; 3185 3186 rx_ring = &priv->rx_rings[index]; 3187 rx_ring->dim.event_ctr++; 3188 3189 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3190 bcmgenet_rx_ring_int_disable(rx_ring); 3191 __napi_schedule_irqoff(&rx_ring->napi); 3192 } 3193 } 3194 3195 /* Check Tx priority queue interrupts */ 3196 for (index = 0; index <= priv->hw_params->tx_queues; index++) { 3197 if (!(status & BIT(index))) 3198 continue; 3199 3200 tx_ring = &priv->tx_rings[index]; 3201 3202 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3203 bcmgenet_tx_ring_int_disable(tx_ring); 3204 __napi_schedule_irqoff(&tx_ring->napi); 3205 } 3206 } 3207 3208 return IRQ_HANDLED; 3209} 3210 3211/* bcmgenet_isr0: handle other stuff */ 3212static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 3213{ 3214 struct bcmgenet_priv *priv = dev_id; 3215 unsigned int status; 3216 unsigned long flags; 3217 3218 /* Read irq status */ 3219 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 3220 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3221 3222 /* clear interrupts */ 3223 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 3224 3225 netif_dbg(priv, intr, priv->dev, 3226 "IRQ=0x%x\n", status); 3227 3228 if (bcmgenet_has_mdio_intr(priv) && status & UMAC_IRQ_MDIO_EVENT) 3229 wake_up(&priv->wq); 3230 3231 /* all other interested interrupts handled in bottom half */ 3232 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 3233 if (status) { 3234 /* Save irq status for bottom-half processing. */ 3235 spin_lock_irqsave(&priv->lock, flags); 3236 priv->irq0_stat |= status; 3237 spin_unlock_irqrestore(&priv->lock, flags); 3238 3239 schedule_work(&priv->bcmgenet_irq_work); 3240 } 3241 3242 return IRQ_HANDLED; 3243} 3244 3245static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 3246{ 3247 /* Acknowledge the interrupt */ 3248 return IRQ_HANDLED; 3249} 3250 3251static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 3252{ 3253 u32 reg; 3254 3255 reg = bcmgenet_rbuf_ctrl_get(priv); 3256 reg |= BIT(1); 3257 bcmgenet_rbuf_ctrl_set(priv, reg); 3258 udelay(10); 3259 3260 reg &= ~BIT(1); 3261 bcmgenet_rbuf_ctrl_set(priv, reg); 3262 udelay(10); 3263} 3264 3265static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 3266 const unsigned char *addr) 3267{ 3268 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0); 3269 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1); 3270} 3271 3272static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 3273 unsigned char *addr) 3274{ 3275 u32 addr_tmp; 3276 3277 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 3278 put_unaligned_be32(addr_tmp, &addr[0]); 3279 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 3280 put_unaligned_be16(addr_tmp, &addr[4]); 3281} 3282 3283static void bcmgenet_netif_start(struct net_device *dev) 3284{ 3285 struct bcmgenet_priv *priv = netdev_priv(dev); 3286 3287 /* Start the network engine */ 3288 netif_addr_lock_bh(dev); 3289 bcmgenet_set_rx_mode(dev); 3290 netif_addr_unlock_bh(dev); 3291 bcmgenet_enable_rx_napi(priv); 3292 3293 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 3294 3295 bcmgenet_enable_tx_napi(priv); 3296 3297 /* Monitor link interrupts now */ 3298 bcmgenet_link_intr_enable(priv); 3299 3300 phy_start(dev->phydev); 3301} 3302 3303static int bcmgenet_open(struct net_device *dev) 3304{ 3305 struct bcmgenet_priv *priv = netdev_priv(dev); 3306 int ret; 3307 3308 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 3309 3310 /* Turn on the clock */ 3311 clk_prepare_enable(priv->clk); 3312 3313 /* If this is an internal GPHY, power it back on now, before UniMAC is 3314 * brought out of reset as absolutely no UniMAC activity is allowed 3315 */ 3316 if (priv->internal_phy) 3317 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3318 3319 /* take MAC out of reset */ 3320 bcmgenet_umac_reset(priv); 3321 3322 init_umac(priv); 3323 3324 /* Apply features again in case we changed them while interface was 3325 * down 3326 */ 3327 bcmgenet_set_features(dev, dev->features); 3328 3329 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3330 3331 /* HFB init */ 3332 bcmgenet_hfb_init(priv); 3333 3334 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3335 ret = bcmgenet_init_dma(priv, true); 3336 if (ret) { 3337 netdev_err(dev, "failed to initialize DMA\n"); 3338 goto err_clk_disable; 3339 } 3340 3341 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 3342 dev->name, priv); 3343 if (ret < 0) { 3344 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 3345 goto err_fini_dma; 3346 } 3347 3348 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 3349 dev->name, priv); 3350 if (ret < 0) { 3351 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 3352 goto err_irq0; 3353 } 3354 3355 ret = bcmgenet_mii_probe(dev); 3356 if (ret) { 3357 netdev_err(dev, "failed to connect to PHY\n"); 3358 goto err_irq1; 3359 } 3360 3361 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); 3362 3363 bcmgenet_netif_start(dev); 3364 3365 netif_tx_start_all_queues(dev); 3366 3367 return 0; 3368 3369err_irq1: 3370 free_irq(priv->irq1, priv); 3371err_irq0: 3372 free_irq(priv->irq0, priv); 3373err_fini_dma: 3374 bcmgenet_dma_teardown(priv); 3375 bcmgenet_fini_dma(priv); 3376err_clk_disable: 3377 if (priv->internal_phy) 3378 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3379 clk_disable_unprepare(priv->clk); 3380 return ret; 3381} 3382 3383static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy) 3384{ 3385 struct bcmgenet_priv *priv = netdev_priv(dev); 3386 3387 netif_tx_disable(dev); 3388 3389 /* Disable MAC receive */ 3390 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 3391 umac_enable_set(priv, CMD_RX_EN, false); 3392 3393 if (stop_phy) 3394 phy_stop(dev->phydev); 3395 3396 bcmgenet_dma_teardown(priv); 3397 3398 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3399 umac_enable_set(priv, CMD_TX_EN, false); 3400 3401 bcmgenet_disable_tx_napi(priv); 3402 bcmgenet_disable_rx_napi(priv); 3403 bcmgenet_intr_disable(priv); 3404 3405 /* Wait for pending work items to complete. Since interrupts are 3406 * disabled no new work will be scheduled. 3407 */ 3408 cancel_work_sync(&priv->bcmgenet_irq_work); 3409 3410 /* tx reclaim */ 3411 bcmgenet_tx_reclaim_all(dev); 3412 bcmgenet_fini_dma(priv); 3413} 3414 3415static int bcmgenet_close(struct net_device *dev) 3416{ 3417 struct bcmgenet_priv *priv = netdev_priv(dev); 3418 int ret = 0; 3419 3420 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3421 3422 bcmgenet_netif_stop(dev, false); 3423 3424 /* Really kill the PHY state machine and disconnect from it */ 3425 phy_disconnect(dev->phydev); 3426 3427 free_irq(priv->irq0, priv); 3428 free_irq(priv->irq1, priv); 3429 3430 if (priv->internal_phy) 3431 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3432 3433 clk_disable_unprepare(priv->clk); 3434 3435 return ret; 3436} 3437 3438static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3439{ 3440 struct bcmgenet_priv *priv = ring->priv; 3441 u32 p_index, c_index, intsts, intmsk; 3442 struct netdev_queue *txq; 3443 unsigned int free_bds; 3444 bool txq_stopped; 3445 3446 if (!netif_msg_tx_err(priv)) 3447 return; 3448 3449 txq = netdev_get_tx_queue(priv->dev, ring->index); 3450 3451 spin_lock(&ring->lock); 3452 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3453 intmsk = 1 << ring->index; 3454 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3455 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3456 txq_stopped = netif_tx_queue_stopped(txq); 3457 free_bds = ring->free_bds; 3458 spin_unlock(&ring->lock); 3459 3460 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3461 "TX queue status: %s, interrupts: %s\n" 3462 "(sw)free_bds: %d (sw)size: %d\n" 3463 "(sw)p_index: %d (hw)p_index: %d\n" 3464 "(sw)c_index: %d (hw)c_index: %d\n" 3465 "(sw)clean_p: %d (sw)write_p: %d\n" 3466 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3467 ring->index, ring->index, 3468 txq_stopped ? "stopped" : "active", 3469 intsts & intmsk ? "enabled" : "disabled", 3470 free_bds, ring->size, 3471 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3472 ring->c_index, c_index & DMA_C_INDEX_MASK, 3473 ring->clean_ptr, ring->write_ptr, 3474 ring->cb_ptr, ring->end_ptr); 3475} 3476 3477static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3478{ 3479 struct bcmgenet_priv *priv = netdev_priv(dev); 3480 u32 int1_enable = 0; 3481 unsigned int q; 3482 3483 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3484 3485 for (q = 0; q <= priv->hw_params->tx_queues; q++) 3486 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3487 3488 bcmgenet_tx_reclaim_all(dev); 3489 3490 for (q = 0; q <= priv->hw_params->tx_queues; q++) 3491 int1_enable |= (1 << q); 3492 3493 /* Re-enable TX interrupts if disabled */ 3494 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3495 3496 netif_trans_update(dev); 3497 3498 BCMGENET_STATS64_INC((&priv->tx_rings[txqueue].stats64), errors); 3499 3500 netif_tx_wake_all_queues(dev); 3501} 3502 3503#define MAX_MDF_FILTER 17 3504 3505static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3506 const unsigned char *addr, 3507 int *i) 3508{ 3509 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3510 UMAC_MDF_ADDR + (*i * 4)); 3511 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3512 addr[4] << 8 | addr[5], 3513 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3514 *i += 2; 3515} 3516 3517static void bcmgenet_set_rx_mode(struct net_device *dev) 3518{ 3519 struct bcmgenet_priv *priv = netdev_priv(dev); 3520 struct netdev_hw_addr *ha; 3521 int i, nfilter; 3522 u32 reg; 3523 3524 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3525 3526 /* Number of filters needed */ 3527 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3528 3529 /* 3530 * Turn on promicuous mode for three scenarios 3531 * 1. IFF_PROMISC flag is set 3532 * 2. IFF_ALLMULTI flag is set 3533 * 3. The number of filters needed exceeds the number filters 3534 * supported by the hardware. 3535 */ 3536 spin_lock(&priv->reg_lock); 3537 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3538 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3539 (nfilter > MAX_MDF_FILTER)) { 3540 reg |= CMD_PROMISC; 3541 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3542 spin_unlock(&priv->reg_lock); 3543 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3544 return; 3545 } else { 3546 reg &= ~CMD_PROMISC; 3547 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3548 spin_unlock(&priv->reg_lock); 3549 } 3550 3551 /* update MDF filter */ 3552 i = 0; 3553 /* Broadcast */ 3554 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3555 /* my own address.*/ 3556 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3557 3558 /* Unicast */ 3559 netdev_for_each_uc_addr(ha, dev) 3560 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3561 3562 /* Multicast */ 3563 netdev_for_each_mc_addr(ha, dev) 3564 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3565 3566 /* Enable filters */ 3567 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3568 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3569} 3570 3571/* Set the hardware MAC address. */ 3572static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3573{ 3574 struct sockaddr *addr = p; 3575 3576 /* Setting the MAC address at the hardware level is not possible 3577 * without disabling the UniMAC RX/TX enable bits. 3578 */ 3579 if (netif_running(dev)) 3580 return -EBUSY; 3581 3582 eth_hw_addr_set(dev, addr->sa_data); 3583 3584 return 0; 3585} 3586 3587static void bcmgenet_get_stats64(struct net_device *dev, 3588 struct rtnl_link_stats64 *stats) 3589{ 3590 struct bcmgenet_priv *priv = netdev_priv(dev); 3591 struct bcmgenet_tx_stats64 *tx_stats; 3592 struct bcmgenet_rx_stats64 *rx_stats; 3593 u64 rx_length_errors, rx_over_errors; 3594 u64 rx_missed, rx_fragmented_errors; 3595 u64 rx_crc_errors, rx_frame_errors; 3596 u64 tx_errors, tx_dropped; 3597 u64 rx_errors, rx_dropped; 3598 u64 tx_bytes, tx_packets; 3599 u64 rx_bytes, rx_packets; 3600 unsigned int start; 3601 unsigned int q; 3602 u64 multicast; 3603 3604 for (q = 0; q <= priv->hw_params->tx_queues; q++) { 3605 tx_stats = &priv->tx_rings[q].stats64; 3606 do { 3607 start = u64_stats_fetch_begin(&tx_stats->syncp); 3608 tx_bytes = u64_stats_read(&tx_stats->bytes); 3609 tx_packets = u64_stats_read(&tx_stats->packets); 3610 tx_errors = u64_stats_read(&tx_stats->errors); 3611 tx_dropped = u64_stats_read(&tx_stats->dropped); 3612 } while (u64_stats_fetch_retry(&tx_stats->syncp, start)); 3613 3614 stats->tx_bytes += tx_bytes; 3615 stats->tx_packets += tx_packets; 3616 stats->tx_errors += tx_errors; 3617 stats->tx_dropped += tx_dropped; 3618 } 3619 3620 for (q = 0; q <= priv->hw_params->rx_queues; q++) { 3621 rx_stats = &priv->rx_rings[q].stats64; 3622 do { 3623 start = u64_stats_fetch_begin(&rx_stats->syncp); 3624 rx_bytes = u64_stats_read(&rx_stats->bytes); 3625 rx_packets = u64_stats_read(&rx_stats->packets); 3626 rx_errors = u64_stats_read(&rx_stats->errors); 3627 rx_dropped = u64_stats_read(&rx_stats->dropped); 3628 rx_missed = u64_stats_read(&rx_stats->missed); 3629 rx_length_errors = u64_stats_read(&rx_stats->length_errors); 3630 rx_over_errors = u64_stats_read(&rx_stats->over_errors); 3631 rx_crc_errors = u64_stats_read(&rx_stats->crc_errors); 3632 rx_frame_errors = u64_stats_read(&rx_stats->frame_errors); 3633 rx_fragmented_errors = u64_stats_read(&rx_stats->fragmented_errors); 3634 multicast = u64_stats_read(&rx_stats->multicast); 3635 } while (u64_stats_fetch_retry(&rx_stats->syncp, start)); 3636 3637 rx_errors += rx_length_errors; 3638 rx_errors += rx_crc_errors; 3639 rx_errors += rx_frame_errors; 3640 rx_errors += rx_fragmented_errors; 3641 3642 stats->rx_bytes += rx_bytes; 3643 stats->rx_packets += rx_packets; 3644 stats->rx_errors += rx_errors; 3645 stats->rx_dropped += rx_dropped; 3646 stats->rx_missed_errors += rx_missed; 3647 stats->rx_length_errors += rx_length_errors; 3648 stats->rx_over_errors += rx_over_errors; 3649 stats->rx_crc_errors += rx_crc_errors; 3650 stats->rx_frame_errors += rx_frame_errors; 3651 stats->multicast += multicast; 3652 } 3653} 3654 3655static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier) 3656{ 3657 struct bcmgenet_priv *priv = netdev_priv(dev); 3658 3659 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) || 3660 priv->phy_interface != PHY_INTERFACE_MODE_MOCA) 3661 return -EOPNOTSUPP; 3662 3663 if (new_carrier) 3664 netif_carrier_on(dev); 3665 else 3666 netif_carrier_off(dev); 3667 3668 return 0; 3669} 3670 3671static const struct net_device_ops bcmgenet_netdev_ops = { 3672 .ndo_open = bcmgenet_open, 3673 .ndo_stop = bcmgenet_close, 3674 .ndo_start_xmit = bcmgenet_xmit, 3675 .ndo_tx_timeout = bcmgenet_timeout, 3676 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3677 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3678 .ndo_eth_ioctl = phy_do_ioctl_running, 3679 .ndo_set_features = bcmgenet_set_features, 3680 .ndo_get_stats64 = bcmgenet_get_stats64, 3681 .ndo_change_carrier = bcmgenet_change_carrier, 3682}; 3683 3684/* GENET hardware parameters/characteristics */ 3685static const struct bcmgenet_hw_params bcmgenet_hw_params_v1 = { 3686 .tx_queues = 0, 3687 .tx_bds_per_q = 0, 3688 .rx_queues = 0, 3689 .rx_bds_per_q = 0, 3690 .bp_in_en_shift = 16, 3691 .bp_in_mask = 0xffff, 3692 .hfb_filter_cnt = 16, 3693 .hfb_filter_size = 64, 3694 .qtag_mask = 0x1F, 3695 .hfb_offset = 0x1000, 3696 .hfb_reg_offset = GENET_RBUF_OFF + RBUF_HFB_CTRL_V1, 3697 .rdma_offset = 0x2000, 3698 .tdma_offset = 0x3000, 3699 .words_per_bd = 2, 3700}; 3701 3702static const struct bcmgenet_hw_params bcmgenet_hw_params_v2 = { 3703 .tx_queues = 4, 3704 .tx_bds_per_q = 32, 3705 .rx_queues = 0, 3706 .rx_bds_per_q = 0, 3707 .bp_in_en_shift = 16, 3708 .bp_in_mask = 0xffff, 3709 .hfb_filter_cnt = 16, 3710 .hfb_filter_size = 64, 3711 .qtag_mask = 0x1F, 3712 .tbuf_offset = 0x0600, 3713 .hfb_offset = 0x1000, 3714 .hfb_reg_offset = 0x2000, 3715 .rdma_offset = 0x3000, 3716 .tdma_offset = 0x4000, 3717 .words_per_bd = 2, 3718}; 3719 3720static const struct bcmgenet_hw_params bcmgenet_hw_params_v3 = { 3721 .tx_queues = 4, 3722 .tx_bds_per_q = 32, 3723 .rx_queues = 0, 3724 .rx_bds_per_q = 0, 3725 .bp_in_en_shift = 17, 3726 .bp_in_mask = 0x1ffff, 3727 .hfb_filter_cnt = 48, 3728 .hfb_filter_size = 128, 3729 .qtag_mask = 0x3F, 3730 .tbuf_offset = 0x0600, 3731 .hfb_offset = 0x8000, 3732 .hfb_reg_offset = 0xfc00, 3733 .rdma_offset = 0x10000, 3734 .tdma_offset = 0x11000, 3735 .words_per_bd = 2, 3736}; 3737 3738static const struct bcmgenet_hw_params bcmgenet_hw_params_v4 = { 3739 .tx_queues = 4, 3740 .tx_bds_per_q = 32, 3741 .rx_queues = 0, 3742 .rx_bds_per_q = 0, 3743 .bp_in_en_shift = 17, 3744 .bp_in_mask = 0x1ffff, 3745 .hfb_filter_cnt = 48, 3746 .hfb_filter_size = 128, 3747 .qtag_mask = 0x3F, 3748 .tbuf_offset = 0x0600, 3749 .hfb_offset = 0x8000, 3750 .hfb_reg_offset = 0xfc00, 3751 .rdma_offset = 0x2000, 3752 .tdma_offset = 0x4000, 3753 .words_per_bd = 3, 3754}; 3755 3756/* Infer hardware parameters from the detected GENET version */ 3757static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3758{ 3759 const struct bcmgenet_hw_params *params; 3760 u32 reg; 3761 u8 major; 3762 u16 gphy_rev; 3763 3764 /* default to latest values */ 3765 params = &bcmgenet_hw_params_v4; 3766 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3767 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3768 if (GENET_IS_V3(priv)) { 3769 params = &bcmgenet_hw_params_v3; 3770 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3771 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3772 } else if (GENET_IS_V2(priv)) { 3773 params = &bcmgenet_hw_params_v2; 3774 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3775 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3776 } else if (GENET_IS_V1(priv)) { 3777 params = &bcmgenet_hw_params_v1; 3778 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3779 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3780 } 3781 priv->hw_params = params; 3782 3783 /* Read GENET HW version */ 3784 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3785 major = (reg >> 24 & 0x0f); 3786 if (major == 6 || major == 7) 3787 major = 5; 3788 else if (major == 5) 3789 major = 4; 3790 else if (major == 0) 3791 major = 1; 3792 if (major != priv->version) { 3793 dev_err(&priv->pdev->dev, 3794 "GENET version mismatch, got: %d, configured for: %d\n", 3795 major, priv->version); 3796 } 3797 3798 /* Print the GENET core version */ 3799 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3800 major, (reg >> 16) & 0x0f, reg & 0xffff); 3801 3802 /* Store the integrated PHY revision for the MDIO probing function 3803 * to pass this information to the PHY driver. The PHY driver expects 3804 * to find the PHY major revision in bits 15:8 while the GENET register 3805 * stores that information in bits 7:0, account for that. 3806 * 3807 * On newer chips, starting with PHY revision G0, a new scheme is 3808 * deployed similar to the Starfighter 2 switch with GPHY major 3809 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3810 * is reserved as well as special value 0x01ff, we have a small 3811 * heuristic to check for the new GPHY revision and re-arrange things 3812 * so the GPHY driver is happy. 3813 */ 3814 gphy_rev = reg & 0xffff; 3815 3816 if (GENET_IS_V5(priv)) { 3817 /* The EPHY revision should come from the MDIO registers of 3818 * the PHY not from GENET. 3819 */ 3820 if (gphy_rev != 0) { 3821 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3822 gphy_rev); 3823 } 3824 /* This is reserved so should require special treatment */ 3825 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3826 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3827 return; 3828 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3829 } else if ((gphy_rev & 0xf0) != 0) { 3830 priv->gphy_rev = gphy_rev << 8; 3831 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3832 } else if ((gphy_rev & 0xff00) != 0) { 3833 priv->gphy_rev = gphy_rev; 3834 } 3835 3836#ifdef CONFIG_PHYS_ADDR_T_64BIT 3837 if (!bcmgenet_has_40bits(priv)) 3838 pr_warn("GENET does not support 40-bits PA\n"); 3839#endif 3840 3841 pr_debug("Configuration for version: %d\n" 3842 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3843 "BP << en: %2d, BP msk: 0x%05x\n" 3844 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3845 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3846 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3847 "Words/BD: %d\n", 3848 priv->version, 3849 params->tx_queues, params->tx_bds_per_q, 3850 params->rx_queues, params->rx_bds_per_q, 3851 params->bp_in_en_shift, params->bp_in_mask, 3852 params->hfb_filter_cnt, params->qtag_mask, 3853 params->tbuf_offset, params->hfb_offset, 3854 params->hfb_reg_offset, 3855 params->rdma_offset, params->tdma_offset, 3856 params->words_per_bd); 3857} 3858 3859struct bcmgenet_plat_data { 3860 enum bcmgenet_version version; 3861 u32 dma_max_burst_length; 3862 u32 flags; 3863}; 3864 3865static const struct bcmgenet_plat_data v1_plat_data = { 3866 .version = GENET_V1, 3867 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3868}; 3869 3870static const struct bcmgenet_plat_data v2_plat_data = { 3871 .version = GENET_V2, 3872 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3873 .flags = GENET_HAS_EXT, 3874}; 3875 3876static const struct bcmgenet_plat_data v3_plat_data = { 3877 .version = GENET_V3, 3878 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3879 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3880 GENET_HAS_MOCA_LINK_DET, 3881}; 3882 3883static const struct bcmgenet_plat_data v4_plat_data = { 3884 .version = GENET_V4, 3885 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3886 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3887 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3888}; 3889 3890static const struct bcmgenet_plat_data v5_plat_data = { 3891 .version = GENET_V5, 3892 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3893 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3894 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3895}; 3896 3897static const struct bcmgenet_plat_data bcm2711_plat_data = { 3898 .version = GENET_V5, 3899 .dma_max_burst_length = 0x08, 3900 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3901 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3902}; 3903 3904static const struct bcmgenet_plat_data bcm7712_plat_data = { 3905 .version = GENET_V5, 3906 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3907 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3908 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET | 3909 GENET_HAS_EPHY_16NM, 3910}; 3911 3912static const struct of_device_id bcmgenet_match[] = { 3913 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3914 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3915 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3916 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3917 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3918 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3919 { .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data }, 3920 { }, 3921}; 3922MODULE_DEVICE_TABLE(of, bcmgenet_match); 3923 3924static int bcmgenet_probe(struct platform_device *pdev) 3925{ 3926 const struct bcmgenet_plat_data *pdata; 3927 struct bcmgenet_priv *priv; 3928 struct net_device *dev; 3929 unsigned int i; 3930 int err = -EIO; 3931 3932 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3933 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3934 GENET_MAX_MQ_CNT + 1); 3935 if (!dev) { 3936 dev_err(&pdev->dev, "can't allocate net device\n"); 3937 return -ENOMEM; 3938 } 3939 3940 priv = netdev_priv(dev); 3941 priv->irq0 = platform_get_irq(pdev, 0); 3942 if (priv->irq0 < 0) { 3943 err = priv->irq0; 3944 goto err; 3945 } 3946 priv->irq1 = platform_get_irq(pdev, 1); 3947 if (priv->irq1 < 0) { 3948 err = priv->irq1; 3949 goto err; 3950 } 3951 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3952 if (priv->wol_irq == -EPROBE_DEFER) { 3953 err = priv->wol_irq; 3954 goto err; 3955 } 3956 3957 priv->base = devm_platform_ioremap_resource(pdev, 0); 3958 if (IS_ERR(priv->base)) { 3959 err = PTR_ERR(priv->base); 3960 goto err; 3961 } 3962 3963 spin_lock_init(&priv->reg_lock); 3964 spin_lock_init(&priv->lock); 3965 3966 /* Set default pause parameters */ 3967 priv->autoneg_pause = 1; 3968 priv->tx_pause = 1; 3969 priv->rx_pause = 1; 3970 3971 SET_NETDEV_DEV(dev, &pdev->dev); 3972 dev_set_drvdata(&pdev->dev, dev); 3973 dev->watchdog_timeo = 2 * HZ; 3974 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3975 dev->netdev_ops = &bcmgenet_netdev_ops; 3976 3977 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3978 3979 /* Set default features */ 3980 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 3981 NETIF_F_RXCSUM; 3982 dev->hw_features |= dev->features; 3983 dev->vlan_features |= dev->features; 3984 3985 netdev_sw_irq_coalesce_default_on(dev); 3986 3987 /* Request the WOL interrupt and advertise suspend if available */ 3988 priv->wol_irq_disabled = true; 3989 if (priv->wol_irq > 0) { 3990 err = devm_request_irq(&pdev->dev, priv->wol_irq, 3991 bcmgenet_wol_isr, 0, dev->name, priv); 3992 if (!err) 3993 device_set_wakeup_capable(&pdev->dev, 1); 3994 } 3995 3996 /* Set the needed headroom to account for any possible 3997 * features enabling/disabling at runtime 3998 */ 3999 dev->needed_headroom += 64; 4000 4001 priv->dev = dev; 4002 priv->pdev = pdev; 4003 4004 pdata = device_get_match_data(&pdev->dev); 4005 if (pdata) { 4006 priv->version = pdata->version; 4007 priv->dma_max_burst_length = pdata->dma_max_burst_length; 4008 priv->flags = pdata->flags; 4009 } 4010 4011 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet"); 4012 if (IS_ERR(priv->clk)) { 4013 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 4014 err = PTR_ERR(priv->clk); 4015 goto err; 4016 } 4017 4018 err = clk_prepare_enable(priv->clk); 4019 if (err) 4020 goto err; 4021 4022 bcmgenet_set_hw_params(priv); 4023 4024 err = -EIO; 4025 if (bcmgenet_has_40bits(priv)) 4026 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 4027 if (err) 4028 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 4029 if (err) 4030 goto err_clk_disable; 4031 4032 /* Mii wait queue */ 4033 init_waitqueue_head(&priv->wq); 4034 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 4035 priv->rx_buf_len = RX_BUF_LENGTH; 4036 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 4037 4038 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol"); 4039 if (IS_ERR(priv->clk_wol)) { 4040 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 4041 err = PTR_ERR(priv->clk_wol); 4042 goto err_clk_disable; 4043 } 4044 4045 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee"); 4046 if (IS_ERR(priv->clk_eee)) { 4047 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 4048 err = PTR_ERR(priv->clk_eee); 4049 goto err_clk_disable; 4050 } 4051 4052 /* If this is an internal GPHY, power it on now, before UniMAC is 4053 * brought out of reset as absolutely no UniMAC activity is allowed 4054 */ 4055 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 4056 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4057 4058 if (device_get_ethdev_address(&pdev->dev, dev)) 4059 if (has_acpi_companion(&pdev->dev)) { 4060 u8 addr[ETH_ALEN]; 4061 4062 bcmgenet_get_hw_addr(priv, addr); 4063 eth_hw_addr_set(dev, addr); 4064 } 4065 4066 if (!is_valid_ether_addr(dev->dev_addr)) { 4067 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 4068 eth_hw_addr_random(dev); 4069 } 4070 4071 reset_umac(priv); 4072 4073 err = bcmgenet_mii_init(dev); 4074 if (err) 4075 goto err_clk_disable; 4076 4077 /* setup number of real queues + 1 */ 4078 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 4079 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 4080 4081 /* Set default coalescing parameters */ 4082 for (i = 0; i <= priv->hw_params->rx_queues; i++) 4083 priv->rx_rings[i].rx_max_coalesced_frames = 1; 4084 4085 /* Initialize u64 stats seq counter for 32bit machines */ 4086 for (i = 0; i <= priv->hw_params->rx_queues; i++) 4087 u64_stats_init(&priv->rx_rings[i].stats64.syncp); 4088 for (i = 0; i <= priv->hw_params->tx_queues; i++) 4089 u64_stats_init(&priv->tx_rings[i].stats64.syncp); 4090 4091 /* libphy will determine the link state */ 4092 netif_carrier_off(dev); 4093 4094 /* Turn off the main clock, WOL clock is handled separately */ 4095 clk_disable_unprepare(priv->clk); 4096 4097 err = register_netdev(dev); 4098 if (err) { 4099 bcmgenet_mii_exit(dev); 4100 goto err; 4101 } 4102 4103 return err; 4104 4105err_clk_disable: 4106 clk_disable_unprepare(priv->clk); 4107err: 4108 free_netdev(dev); 4109 return err; 4110} 4111 4112static void bcmgenet_remove(struct platform_device *pdev) 4113{ 4114 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 4115 4116 dev_set_drvdata(&pdev->dev, NULL); 4117 unregister_netdev(priv->dev); 4118 bcmgenet_mii_exit(priv->dev); 4119 free_netdev(priv->dev); 4120} 4121 4122static void bcmgenet_shutdown(struct platform_device *pdev) 4123{ 4124 bcmgenet_remove(pdev); 4125} 4126 4127#ifdef CONFIG_PM_SLEEP 4128static int bcmgenet_resume_noirq(struct device *d) 4129{ 4130 struct net_device *dev = dev_get_drvdata(d); 4131 struct bcmgenet_priv *priv = netdev_priv(dev); 4132 int ret; 4133 u32 reg; 4134 4135 if (!netif_running(dev)) 4136 return 0; 4137 4138 /* Turn on the clock */ 4139 ret = clk_prepare_enable(priv->clk); 4140 if (ret) 4141 return ret; 4142 4143 if (device_may_wakeup(d) && priv->wolopts) { 4144 /* Account for Wake-on-LAN events and clear those events 4145 * (Some devices need more time between enabling the clocks 4146 * and the interrupt register reflecting the wake event so 4147 * read the register twice) 4148 */ 4149 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4150 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4151 if (reg & UMAC_IRQ_WAKE_EVENT) 4152 pm_wakeup_event(&priv->pdev->dev, 0); 4153 4154 /* From WOL-enabled suspend, switch to regular clock */ 4155 if (!bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC)) 4156 return 0; 4157 4158 /* Failed so fall through to reset MAC */ 4159 } 4160 4161 /* If this is an internal GPHY, power it back on now, before UniMAC is 4162 * brought out of reset as absolutely no UniMAC activity is allowed 4163 */ 4164 if (priv->internal_phy) 4165 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4166 4167 /* take MAC out of reset */ 4168 bcmgenet_umac_reset(priv); 4169 4170 return 0; 4171} 4172 4173static int bcmgenet_resume(struct device *d) 4174{ 4175 struct net_device *dev = dev_get_drvdata(d); 4176 struct bcmgenet_priv *priv = netdev_priv(dev); 4177 struct bcmgenet_rxnfc_rule *rule; 4178 int ret; 4179 u32 reg; 4180 4181 if (!netif_running(dev)) 4182 return 0; 4183 4184 if (device_may_wakeup(d) && priv->wolopts) { 4185 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 4186 if (reg & CMD_RX_EN) { 4187 /* Successfully exited WoL, just resume data flows */ 4188 list_for_each_entry(rule, &priv->rxnfc_list, list) 4189 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 4190 bcmgenet_hfb_enable_filter(priv, 4191 rule->fs.location + 1); 4192 bcmgenet_hfb_enable_filter(priv, 0); 4193 bcmgenet_set_rx_mode(dev); 4194 bcmgenet_enable_rx_napi(priv); 4195 4196 /* Reinitialize Tx flows */ 4197 bcmgenet_tdma_disable(priv); 4198 bcmgenet_init_tx_queues(priv->dev); 4199 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 4200 reg |= DMA_EN; 4201 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 4202 bcmgenet_enable_tx_napi(priv); 4203 4204 bcmgenet_link_intr_enable(priv); 4205 phy_start_machine(dev->phydev); 4206 4207 netif_device_attach(dev); 4208 enable_irq(priv->irq1); 4209 return 0; 4210 } 4211 /* MAC was reset so complete bcmgenet_netif_stop() */ 4212 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, false); 4213 bcmgenet_rdma_disable(priv); 4214 bcmgenet_intr_disable(priv); 4215 bcmgenet_fini_dma(priv); 4216 enable_irq(priv->irq1); 4217 } 4218 4219 init_umac(priv); 4220 4221 phy_init_hw(dev->phydev); 4222 4223 /* Speed settings must be restored */ 4224 genphy_config_aneg(dev->phydev); 4225 bcmgenet_mii_config(priv->dev, false); 4226 4227 /* Restore enabled features */ 4228 bcmgenet_set_features(dev, dev->features); 4229 4230 bcmgenet_set_hw_addr(priv, dev->dev_addr); 4231 4232 /* Restore hardware filters */ 4233 bcmgenet_hfb_clear(priv); 4234 list_for_each_entry(rule, &priv->rxnfc_list, list) 4235 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) 4236 bcmgenet_hfb_create_rxnfc_filter(priv, rule); 4237 4238 /* Reinitialize TDMA and RDMA and SW housekeeping */ 4239 ret = bcmgenet_init_dma(priv, false); 4240 if (ret) { 4241 netdev_err(dev, "failed to initialize DMA\n"); 4242 goto out_clk_disable; 4243 } 4244 4245 if (!device_may_wakeup(d)) 4246 phy_resume(dev->phydev); 4247 4248 bcmgenet_netif_start(dev); 4249 4250 netif_device_attach(dev); 4251 4252 return 0; 4253 4254out_clk_disable: 4255 if (priv->internal_phy) 4256 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4257 clk_disable_unprepare(priv->clk); 4258 return ret; 4259} 4260 4261static int bcmgenet_suspend(struct device *d) 4262{ 4263 struct net_device *dev = dev_get_drvdata(d); 4264 struct bcmgenet_priv *priv = netdev_priv(dev); 4265 struct bcmgenet_rxnfc_rule *rule; 4266 u32 reg, hfb_enable = 0; 4267 4268 if (!netif_running(dev)) 4269 return 0; 4270 4271 netif_device_detach(dev); 4272 4273 if (device_may_wakeup(d) && priv->wolopts) { 4274 netif_tx_disable(dev); 4275 4276 /* Suspend non-wake Rx data flows */ 4277 if (priv->wolopts & WAKE_FILTER) 4278 list_for_each_entry(rule, &priv->rxnfc_list, list) 4279 if (rule->fs.ring_cookie == RX_CLS_FLOW_WAKE && 4280 rule->state == BCMGENET_RXNFC_STATE_ENABLED) 4281 hfb_enable |= 1 << rule->fs.location; 4282 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 4283 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) { 4284 reg &= ~RBUF_HFB_FILTER_EN_MASK; 4285 reg |= hfb_enable << (RBUF_HFB_FILTER_EN_SHIFT + 1); 4286 } else { 4287 bcmgenet_hfb_reg_writel(priv, hfb_enable << 1, 4288 HFB_FLT_ENABLE_V3PLUS + 4); 4289 } 4290 if (!hfb_enable) 4291 reg &= ~RBUF_HFB_EN; 4292 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 4293 4294 /* Clear any old filter matches so only new matches wake */ 4295 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 4296 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 4297 4298 if (-ETIMEDOUT == bcmgenet_tdma_disable(priv)) 4299 netdev_warn(priv->dev, 4300 "Timed out while disabling TX DMA\n"); 4301 4302 bcmgenet_disable_tx_napi(priv); 4303 bcmgenet_disable_rx_napi(priv); 4304 disable_irq(priv->irq1); 4305 bcmgenet_tx_reclaim_all(dev); 4306 bcmgenet_fini_tx_napi(priv); 4307 } else { 4308 /* Teardown the interface */ 4309 bcmgenet_netif_stop(dev, true); 4310 } 4311 4312 return 0; 4313} 4314 4315static int bcmgenet_suspend_noirq(struct device *d) 4316{ 4317 struct net_device *dev = dev_get_drvdata(d); 4318 struct bcmgenet_priv *priv = netdev_priv(dev); 4319 int ret = 0; 4320 4321 if (!netif_running(dev)) 4322 return 0; 4323 4324 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 4325 if (device_may_wakeup(d) && priv->wolopts) 4326 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 4327 else if (priv->internal_phy) 4328 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4329 4330 /* Let the framework handle resumption and leave the clocks on */ 4331 if (ret) 4332 return ret; 4333 4334 /* Turn off the clocks */ 4335 clk_disable_unprepare(priv->clk); 4336 4337 return 0; 4338} 4339#else 4340#define bcmgenet_suspend NULL 4341#define bcmgenet_suspend_noirq NULL 4342#define bcmgenet_resume NULL 4343#define bcmgenet_resume_noirq NULL 4344#endif /* CONFIG_PM_SLEEP */ 4345 4346static const struct dev_pm_ops bcmgenet_pm_ops = { 4347 .suspend = bcmgenet_suspend, 4348 .suspend_noirq = bcmgenet_suspend_noirq, 4349 .resume = bcmgenet_resume, 4350 .resume_noirq = bcmgenet_resume_noirq, 4351}; 4352 4353static const struct acpi_device_id genet_acpi_match[] = { 4354 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 4355 { }, 4356}; 4357MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 4358 4359static struct platform_driver bcmgenet_driver = { 4360 .probe = bcmgenet_probe, 4361 .remove = bcmgenet_remove, 4362 .shutdown = bcmgenet_shutdown, 4363 .driver = { 4364 .name = "bcmgenet", 4365 .of_match_table = bcmgenet_match, 4366 .pm = &bcmgenet_pm_ops, 4367 .acpi_match_table = genet_acpi_match, 4368 }, 4369}; 4370module_platform_driver(bcmgenet_driver); 4371 4372MODULE_AUTHOR("Broadcom Corporation"); 4373MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 4374MODULE_ALIAS("platform:bcmgenet"); 4375MODULE_LICENSE("GPL"); 4376MODULE_SOFTDEP("pre: mdio-bcm-unimac");
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