bnxt_ethtool.c

   1/* Broadcom NetXtreme-C/E network driver.
   2 *
   3 * Copyright (c) 2014-2016 Broadcom Corporation
   4 * Copyright (c) 2016-2017 Broadcom Limited
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation.
   9 */
  10
  11#include <linux/bitops.h>
  12#include <linux/ctype.h>
  13#include <linux/stringify.h>
  14#include <linux/ethtool.h>
  15#include <linux/ethtool_netlink.h>
  16#include <linux/linkmode.h>
  17#include <linux/interrupt.h>
  18#include <linux/pci.h>
  19#include <linux/etherdevice.h>
  20#include <linux/crc32.h>
  21#include <linux/firmware.h>
  22#include <linux/utsname.h>
  23#include <linux/time.h>
  24#include <linux/ptp_clock_kernel.h>
  25#include <linux/net_tstamp.h>
  26#include <linux/timecounter.h>
  27#include <net/netdev_queues.h>
  28#include <net/netlink.h>
  29#include <linux/bnxt/hsi.h>
  30#include "bnxt.h"
  31#include "bnxt_hwrm.h"
  32#include "bnxt_ulp.h"
  33#include "bnxt_xdp.h"
  34#include "bnxt_ptp.h"
  35#include "bnxt_ethtool.h"
  36#include "bnxt_nvm_defs.h"	/* NVRAM content constant and structure defs */
  37#include "bnxt_fw_hdr.h"	/* Firmware hdr constant and structure defs */
  38#include "bnxt_coredump.h"
  39
  40#define BNXT_NVM_ERR_MSG(dev, extack, msg)			\
  41	do {							\
  42		if (extack)					\
  43			NL_SET_ERR_MSG_MOD(extack, msg);	\
  44		netdev_err(dev, "%s\n", msg);			\
  45	} while (0)
  46
  47static u32 bnxt_get_msglevel(struct net_device *dev)
  48{
  49	struct bnxt *bp = netdev_priv(dev);
  50
  51	return bp->msg_enable;
  52}
  53
  54static void bnxt_set_msglevel(struct net_device *dev, u32 value)
  55{
  56	struct bnxt *bp = netdev_priv(dev);
  57
  58	bp->msg_enable = value;
  59}
  60
  61static int bnxt_get_coalesce(struct net_device *dev,
  62			     struct ethtool_coalesce *coal,
  63			     struct kernel_ethtool_coalesce *kernel_coal,
  64			     struct netlink_ext_ack *extack)
  65{
  66	struct bnxt *bp = netdev_priv(dev);
  67	struct bnxt_coal *hw_coal;
  68	u16 mult;
  69
  70	memset(coal, 0, sizeof(*coal));
  71
  72	coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
  73
  74	hw_coal = &bp->rx_coal;
  75	mult = hw_coal->bufs_per_record;
  76	coal->rx_coalesce_usecs = hw_coal->coal_ticks;
  77	coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
  78	coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
  79	coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
  80	if (hw_coal->flags &
  81	    RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
  82		kernel_coal->use_cqe_mode_rx = true;
  83
  84	hw_coal = &bp->tx_coal;
  85	mult = hw_coal->bufs_per_record;
  86	coal->tx_coalesce_usecs = hw_coal->coal_ticks;
  87	coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
  88	coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
  89	coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
  90	if (hw_coal->flags &
  91	    RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
  92		kernel_coal->use_cqe_mode_tx = true;
  93
  94	coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
  95
  96	return 0;
  97}
  98
  99static int bnxt_set_coalesce(struct net_device *dev,
 100			     struct ethtool_coalesce *coal,
 101			     struct kernel_ethtool_coalesce *kernel_coal,
 102			     struct netlink_ext_ack *extack)
 103{
 104	struct bnxt *bp = netdev_priv(dev);
 105	bool update_stats = false;
 106	struct bnxt_coal *hw_coal;
 107	int rc = 0;
 108	u16 mult;
 109
 110	if (coal->use_adaptive_rx_coalesce) {
 111		bp->flags |= BNXT_FLAG_DIM;
 112	} else {
 113		if (bp->flags & BNXT_FLAG_DIM) {
 114			bp->flags &= ~(BNXT_FLAG_DIM);
 115			goto reset_coalesce;
 116		}
 117	}
 118
 119	if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
 120	    !(bp->coal_cap.cmpl_params &
 121	      RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET))
 122		return -EOPNOTSUPP;
 123
 124	hw_coal = &bp->rx_coal;
 125	mult = hw_coal->bufs_per_record;
 126	hw_coal->coal_ticks = coal->rx_coalesce_usecs;
 127	hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
 128	hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
 129	hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
 130	hw_coal->flags &=
 131		~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
 132	if (kernel_coal->use_cqe_mode_rx)
 133		hw_coal->flags |=
 134			RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
 135
 136	hw_coal = &bp->tx_coal;
 137	mult = hw_coal->bufs_per_record;
 138	hw_coal->coal_ticks = coal->tx_coalesce_usecs;
 139	hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
 140	hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
 141	hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
 142	hw_coal->flags &=
 143		~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
 144	if (kernel_coal->use_cqe_mode_tx)
 145		hw_coal->flags |=
 146			RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
 147
 148	if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
 149		u32 stats_ticks = coal->stats_block_coalesce_usecs;
 150
 151		/* Allow 0, which means disable. */
 152		if (stats_ticks)
 153			stats_ticks = clamp_t(u32, stats_ticks,
 154					      BNXT_MIN_STATS_COAL_TICKS,
 155					      BNXT_MAX_STATS_COAL_TICKS);
 156		stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
 157		bp->stats_coal_ticks = stats_ticks;
 158		if (bp->stats_coal_ticks)
 159			bp->current_interval =
 160				bp->stats_coal_ticks * HZ / 1000000;
 161		else
 162			bp->current_interval = BNXT_TIMER_INTERVAL;
 163		update_stats = true;
 164	}
 165
 166reset_coalesce:
 167	if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
 168		if (update_stats) {
 169			bnxt_close_nic(bp, true, false);
 170			rc = bnxt_open_nic(bp, true, false);
 171		} else {
 172			rc = bnxt_hwrm_set_coal(bp);
 173		}
 174	}
 175
 176	return rc;
 177}
 178
 179static const char * const bnxt_ring_rx_stats_str[] = {
 180	"rx_ucast_packets",
 181	"rx_mcast_packets",
 182	"rx_bcast_packets",
 183	"rx_discards",
 184	"rx_errors",
 185	"rx_ucast_bytes",
 186	"rx_mcast_bytes",
 187	"rx_bcast_bytes",
 188};
 189
 190static const char * const bnxt_ring_tx_stats_str[] = {
 191	"tx_ucast_packets",
 192	"tx_mcast_packets",
 193	"tx_bcast_packets",
 194	"tx_errors",
 195	"tx_discards",
 196	"tx_ucast_bytes",
 197	"tx_mcast_bytes",
 198	"tx_bcast_bytes",
 199};
 200
 201static const char * const bnxt_ring_tpa_stats_str[] = {
 202	"tpa_packets",
 203	"tpa_bytes",
 204	"tpa_events",
 205	"tpa_aborts",
 206};
 207
 208static const char * const bnxt_ring_tpa2_stats_str[] = {
 209	"rx_tpa_eligible_pkt",
 210	"rx_tpa_eligible_bytes",
 211	"rx_tpa_pkt",
 212	"rx_tpa_bytes",
 213	"rx_tpa_errors",
 214	"rx_tpa_events",
 215};
 216
 217static const char * const bnxt_rx_sw_stats_str[] = {
 218	"rx_l4_csum_errors",
 219	"rx_resets",
 220	"rx_buf_errors",
 221};
 222
 223static const char * const bnxt_cmn_sw_stats_str[] = {
 224	"missed_irqs",
 225};
 226
 227#define BNXT_RX_STATS_ENTRY(counter)	\
 228	{ BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
 229
 230#define BNXT_TX_STATS_ENTRY(counter)	\
 231	{ BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
 232
 233#define BNXT_RX_STATS_EXT_ENTRY(counter)	\
 234	{ BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
 235
 236#define BNXT_TX_STATS_EXT_ENTRY(counter)	\
 237	{ BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
 238
 239#define BNXT_RX_STATS_EXT_PFC_ENTRY(n)				\
 240	BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us),	\
 241	BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
 242
 243#define BNXT_TX_STATS_EXT_PFC_ENTRY(n)				\
 244	BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us),	\
 245	BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
 246
 247#define BNXT_RX_STATS_EXT_PFC_ENTRIES				\
 248	BNXT_RX_STATS_EXT_PFC_ENTRY(0),				\
 249	BNXT_RX_STATS_EXT_PFC_ENTRY(1),				\
 250	BNXT_RX_STATS_EXT_PFC_ENTRY(2),				\
 251	BNXT_RX_STATS_EXT_PFC_ENTRY(3),				\
 252	BNXT_RX_STATS_EXT_PFC_ENTRY(4),				\
 253	BNXT_RX_STATS_EXT_PFC_ENTRY(5),				\
 254	BNXT_RX_STATS_EXT_PFC_ENTRY(6),				\
 255	BNXT_RX_STATS_EXT_PFC_ENTRY(7)
 256
 257#define BNXT_TX_STATS_EXT_PFC_ENTRIES				\
 258	BNXT_TX_STATS_EXT_PFC_ENTRY(0),				\
 259	BNXT_TX_STATS_EXT_PFC_ENTRY(1),				\
 260	BNXT_TX_STATS_EXT_PFC_ENTRY(2),				\
 261	BNXT_TX_STATS_EXT_PFC_ENTRY(3),				\
 262	BNXT_TX_STATS_EXT_PFC_ENTRY(4),				\
 263	BNXT_TX_STATS_EXT_PFC_ENTRY(5),				\
 264	BNXT_TX_STATS_EXT_PFC_ENTRY(6),				\
 265	BNXT_TX_STATS_EXT_PFC_ENTRY(7)
 266
 267#define BNXT_RX_STATS_EXT_COS_ENTRY(n)				\
 268	BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n),		\
 269	BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
 270
 271#define BNXT_TX_STATS_EXT_COS_ENTRY(n)				\
 272	BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n),		\
 273	BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
 274
 275#define BNXT_RX_STATS_EXT_COS_ENTRIES				\
 276	BNXT_RX_STATS_EXT_COS_ENTRY(0),				\
 277	BNXT_RX_STATS_EXT_COS_ENTRY(1),				\
 278	BNXT_RX_STATS_EXT_COS_ENTRY(2),				\
 279	BNXT_RX_STATS_EXT_COS_ENTRY(3),				\
 280	BNXT_RX_STATS_EXT_COS_ENTRY(4),				\
 281	BNXT_RX_STATS_EXT_COS_ENTRY(5),				\
 282	BNXT_RX_STATS_EXT_COS_ENTRY(6),				\
 283	BNXT_RX_STATS_EXT_COS_ENTRY(7)				\
 284
 285#define BNXT_TX_STATS_EXT_COS_ENTRIES				\
 286	BNXT_TX_STATS_EXT_COS_ENTRY(0),				\
 287	BNXT_TX_STATS_EXT_COS_ENTRY(1),				\
 288	BNXT_TX_STATS_EXT_COS_ENTRY(2),				\
 289	BNXT_TX_STATS_EXT_COS_ENTRY(3),				\
 290	BNXT_TX_STATS_EXT_COS_ENTRY(4),				\
 291	BNXT_TX_STATS_EXT_COS_ENTRY(5),				\
 292	BNXT_TX_STATS_EXT_COS_ENTRY(6),				\
 293	BNXT_TX_STATS_EXT_COS_ENTRY(7)				\
 294
 295#define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n)			\
 296	BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n),	\
 297	BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
 298
 299#define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES				\
 300	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0),				\
 301	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1),				\
 302	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2),				\
 303	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3),				\
 304	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4),				\
 305	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5),				\
 306	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6),				\
 307	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
 308
 309#define BNXT_RX_STATS_PRI_ENTRY(counter, n)		\
 310	{ BNXT_RX_STATS_EXT_OFFSET(counter##_cos0),	\
 311	  __stringify(counter##_pri##n) }
 312
 313#define BNXT_TX_STATS_PRI_ENTRY(counter, n)		\
 314	{ BNXT_TX_STATS_EXT_OFFSET(counter##_cos0),	\
 315	  __stringify(counter##_pri##n) }
 316
 317#define BNXT_RX_STATS_PRI_ENTRIES(counter)		\
 318	BNXT_RX_STATS_PRI_ENTRY(counter, 0),		\
 319	BNXT_RX_STATS_PRI_ENTRY(counter, 1),		\
 320	BNXT_RX_STATS_PRI_ENTRY(counter, 2),		\
 321	BNXT_RX_STATS_PRI_ENTRY(counter, 3),		\
 322	BNXT_RX_STATS_PRI_ENTRY(counter, 4),		\
 323	BNXT_RX_STATS_PRI_ENTRY(counter, 5),		\
 324	BNXT_RX_STATS_PRI_ENTRY(counter, 6),		\
 325	BNXT_RX_STATS_PRI_ENTRY(counter, 7)
 326
 327#define BNXT_TX_STATS_PRI_ENTRIES(counter)		\
 328	BNXT_TX_STATS_PRI_ENTRY(counter, 0),		\
 329	BNXT_TX_STATS_PRI_ENTRY(counter, 1),		\
 330	BNXT_TX_STATS_PRI_ENTRY(counter, 2),		\
 331	BNXT_TX_STATS_PRI_ENTRY(counter, 3),		\
 332	BNXT_TX_STATS_PRI_ENTRY(counter, 4),		\
 333	BNXT_TX_STATS_PRI_ENTRY(counter, 5),		\
 334	BNXT_TX_STATS_PRI_ENTRY(counter, 6),		\
 335	BNXT_TX_STATS_PRI_ENTRY(counter, 7)
 336
 337enum {
 338	RX_TOTAL_DISCARDS,
 339	TX_TOTAL_DISCARDS,
 340	RX_NETPOLL_DISCARDS,
 341};
 342
 343static const char *const bnxt_ring_err_stats_arr[] = {
 344	"rx_total_l4_csum_errors",
 345	"rx_total_resets",
 346	"rx_total_buf_errors",
 347	"rx_total_oom_discards",
 348	"rx_total_netpoll_discards",
 349	"rx_total_ring_discards",
 350	"tx_total_resets",
 351	"tx_total_ring_discards",
 352	"total_missed_irqs",
 353};
 354
 355#define NUM_RING_RX_SW_STATS		ARRAY_SIZE(bnxt_rx_sw_stats_str)
 356#define NUM_RING_CMN_SW_STATS		ARRAY_SIZE(bnxt_cmn_sw_stats_str)
 357#define NUM_RING_RX_HW_STATS		ARRAY_SIZE(bnxt_ring_rx_stats_str)
 358#define NUM_RING_TX_HW_STATS		ARRAY_SIZE(bnxt_ring_tx_stats_str)
 359
 360static const struct {
 361	long offset;
 362	char string[ETH_GSTRING_LEN];
 363} bnxt_port_stats_arr[] = {
 364	BNXT_RX_STATS_ENTRY(rx_64b_frames),
 365	BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
 366	BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
 367	BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
 368	BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
 369	BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
 370	BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
 371	BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
 372	BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
 373	BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
 374	BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
 375	BNXT_RX_STATS_ENTRY(rx_total_frames),
 376	BNXT_RX_STATS_ENTRY(rx_ucast_frames),
 377	BNXT_RX_STATS_ENTRY(rx_mcast_frames),
 378	BNXT_RX_STATS_ENTRY(rx_bcast_frames),
 379	BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
 380	BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
 381	BNXT_RX_STATS_ENTRY(rx_pause_frames),
 382	BNXT_RX_STATS_ENTRY(rx_pfc_frames),
 383	BNXT_RX_STATS_ENTRY(rx_align_err_frames),
 384	BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
 385	BNXT_RX_STATS_ENTRY(rx_jbr_frames),
 386	BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
 387	BNXT_RX_STATS_ENTRY(rx_tagged_frames),
 388	BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
 389	BNXT_RX_STATS_ENTRY(rx_good_frames),
 390	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
 391	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
 392	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
 393	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
 394	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
 395	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
 396	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
 397	BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
 398	BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
 399	BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
 400	BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
 401	BNXT_RX_STATS_ENTRY(rx_bytes),
 402	BNXT_RX_STATS_ENTRY(rx_runt_bytes),
 403	BNXT_RX_STATS_ENTRY(rx_runt_frames),
 404	BNXT_RX_STATS_ENTRY(rx_stat_discard),
 405	BNXT_RX_STATS_ENTRY(rx_stat_err),
 406
 407	BNXT_TX_STATS_ENTRY(tx_64b_frames),
 408	BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
 409	BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
 410	BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
 411	BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
 412	BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
 413	BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
 414	BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
 415	BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
 416	BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
 417	BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
 418	BNXT_TX_STATS_ENTRY(tx_good_frames),
 419	BNXT_TX_STATS_ENTRY(tx_total_frames),
 420	BNXT_TX_STATS_ENTRY(tx_ucast_frames),
 421	BNXT_TX_STATS_ENTRY(tx_mcast_frames),
 422	BNXT_TX_STATS_ENTRY(tx_bcast_frames),
 423	BNXT_TX_STATS_ENTRY(tx_pause_frames),
 424	BNXT_TX_STATS_ENTRY(tx_pfc_frames),
 425	BNXT_TX_STATS_ENTRY(tx_jabber_frames),
 426	BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
 427	BNXT_TX_STATS_ENTRY(tx_err),
 428	BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
 429	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
 430	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
 431	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
 432	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
 433	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
 434	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
 435	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
 436	BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
 437	BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
 438	BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
 439	BNXT_TX_STATS_ENTRY(tx_total_collisions),
 440	BNXT_TX_STATS_ENTRY(tx_bytes),
 441	BNXT_TX_STATS_ENTRY(tx_xthol_frames),
 442	BNXT_TX_STATS_ENTRY(tx_stat_discard),
 443	BNXT_TX_STATS_ENTRY(tx_stat_error),
 444};
 445
 446static const struct {
 447	long offset;
 448	char string[ETH_GSTRING_LEN];
 449} bnxt_port_stats_ext_arr[] = {
 450	BNXT_RX_STATS_EXT_ENTRY(link_down_events),
 451	BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
 452	BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
 453	BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
 454	BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
 455	BNXT_RX_STATS_EXT_COS_ENTRIES,
 456	BNXT_RX_STATS_EXT_PFC_ENTRIES,
 457	BNXT_RX_STATS_EXT_ENTRY(rx_bits),
 458	BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
 459	BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
 460	BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
 461	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
 462	BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks),
 463	BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks),
 464	BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss),
 465};
 466
 467static const struct {
 468	long offset;
 469	char string[ETH_GSTRING_LEN];
 470} bnxt_tx_port_stats_ext_arr[] = {
 471	BNXT_TX_STATS_EXT_COS_ENTRIES,
 472	BNXT_TX_STATS_EXT_PFC_ENTRIES,
 473};
 474
 475static const struct {
 476	long base_off;
 477	char string[ETH_GSTRING_LEN];
 478} bnxt_rx_bytes_pri_arr[] = {
 479	BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
 480};
 481
 482static const struct {
 483	long base_off;
 484	char string[ETH_GSTRING_LEN];
 485} bnxt_rx_pkts_pri_arr[] = {
 486	BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
 487};
 488
 489static const struct {
 490	long base_off;
 491	char string[ETH_GSTRING_LEN];
 492} bnxt_tx_bytes_pri_arr[] = {
 493	BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
 494};
 495
 496static const struct {
 497	long base_off;
 498	char string[ETH_GSTRING_LEN];
 499} bnxt_tx_pkts_pri_arr[] = {
 500	BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
 501};
 502
 503#define BNXT_NUM_RING_ERR_STATS	ARRAY_SIZE(bnxt_ring_err_stats_arr)
 504#define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
 505#define BNXT_NUM_STATS_PRI			\
 506	(ARRAY_SIZE(bnxt_rx_bytes_pri_arr) +	\
 507	 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) +	\
 508	 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) +	\
 509	 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
 510
 511static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
 512{
 513	if (BNXT_SUPPORTS_TPA(bp)) {
 514		if (bp->max_tpa_v2) {
 515			if (BNXT_CHIP_P5(bp))
 516				return BNXT_NUM_TPA_RING_STATS_P5;
 517			return BNXT_NUM_TPA_RING_STATS_P7;
 518		}
 519		return BNXT_NUM_TPA_RING_STATS;
 520	}
 521	return 0;
 522}
 523
 524static int bnxt_get_num_ring_stats(struct bnxt *bp)
 525{
 526	int rx, tx, cmn;
 527
 528	rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
 529	     bnxt_get_num_tpa_ring_stats(bp);
 530	tx = NUM_RING_TX_HW_STATS;
 531	cmn = NUM_RING_CMN_SW_STATS;
 532	return rx * bp->rx_nr_rings +
 533	       tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) +
 534	       cmn * bp->cp_nr_rings;
 535}
 536
 537static int bnxt_get_num_stats(struct bnxt *bp)
 538{
 539	int num_stats = bnxt_get_num_ring_stats(bp);
 540	int len;
 541
 542	num_stats += BNXT_NUM_RING_ERR_STATS;
 543
 544	if (bp->flags & BNXT_FLAG_PORT_STATS)
 545		num_stats += BNXT_NUM_PORT_STATS;
 546
 547	if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
 548		len = min_t(int, bp->fw_rx_stats_ext_size,
 549			    ARRAY_SIZE(bnxt_port_stats_ext_arr));
 550		num_stats += len;
 551		len = min_t(int, bp->fw_tx_stats_ext_size,
 552			    ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
 553		num_stats += len;
 554		if (bp->pri2cos_valid)
 555			num_stats += BNXT_NUM_STATS_PRI;
 556	}
 557
 558	return num_stats;
 559}
 560
 561static int bnxt_get_sset_count(struct net_device *dev, int sset)
 562{
 563	struct bnxt *bp = netdev_priv(dev);
 564
 565	switch (sset) {
 566	case ETH_SS_STATS:
 567		return bnxt_get_num_stats(bp);
 568	case ETH_SS_TEST:
 569		if (!bp->num_tests)
 570			return -EOPNOTSUPP;
 571		return bp->num_tests;
 572	default:
 573		return -EOPNOTSUPP;
 574	}
 575}
 576
 577static bool is_rx_ring(struct bnxt *bp, int ring_num)
 578{
 579	return ring_num < bp->rx_nr_rings;
 580}
 581
 582static bool is_tx_ring(struct bnxt *bp, int ring_num)
 583{
 584	int tx_base = 0;
 585
 586	if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
 587		tx_base = bp->rx_nr_rings;
 588
 589	if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
 590		return true;
 591	return false;
 592}
 593
 594static void bnxt_get_ethtool_stats(struct net_device *dev,
 595				   struct ethtool_stats *stats, u64 *buf)
 596{
 597	struct bnxt_total_ring_err_stats ring_err_stats = {0};
 598	struct bnxt *bp = netdev_priv(dev);
 599	u64 *curr, *prev;
 600	u32 tpa_stats;
 601	u32 i, j = 0;
 602
 603	if (!bp->bnapi) {
 604		j += bnxt_get_num_ring_stats(bp);
 605		goto skip_ring_stats;
 606	}
 607
 608	tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
 609	for (i = 0; i < bp->cp_nr_rings; i++) {
 610		struct bnxt_napi *bnapi = bp->bnapi[i];
 611		struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 612		u64 *sw_stats = cpr->stats.sw_stats;
 613		u64 *sw;
 614		int k;
 615
 616		if (is_rx_ring(bp, i)) {
 617			for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
 618				buf[j] = sw_stats[k];
 619		}
 620		if (is_tx_ring(bp, i)) {
 621			k = NUM_RING_RX_HW_STATS;
 622			for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
 623			       j++, k++)
 624				buf[j] = sw_stats[k];
 625		}
 626		if (!tpa_stats || !is_rx_ring(bp, i))
 627			goto skip_tpa_ring_stats;
 628
 629		k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
 630		for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
 631			   tpa_stats; j++, k++)
 632			buf[j] = sw_stats[k];
 633
 634skip_tpa_ring_stats:
 635		sw = (u64 *)&cpr->sw_stats->rx;
 636		if (is_rx_ring(bp, i)) {
 637			for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
 638				buf[j] = sw[k];
 639		}
 640
 641		sw = (u64 *)&cpr->sw_stats->cmn;
 642		for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
 643			buf[j] = sw[k];
 644	}
 645
 646	bnxt_get_ring_err_stats(bp, &ring_err_stats);
 647
 648skip_ring_stats:
 649	curr = &ring_err_stats.rx_total_l4_csum_errors;
 650	prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors;
 651	for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++)
 652		buf[j] = *curr + *prev;
 653
 654	if (bp->flags & BNXT_FLAG_PORT_STATS) {
 655		u64 *port_stats = bp->port_stats.sw_stats;
 656
 657		for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
 658			buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
 659	}
 660	if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
 661		u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
 662		u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
 663		u32 len;
 664
 665		len = min_t(u32, bp->fw_rx_stats_ext_size,
 666			    ARRAY_SIZE(bnxt_port_stats_ext_arr));
 667		for (i = 0; i < len; i++, j++) {
 668			buf[j] = *(rx_port_stats_ext +
 669				   bnxt_port_stats_ext_arr[i].offset);
 670		}
 671		len = min_t(u32, bp->fw_tx_stats_ext_size,
 672			    ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
 673		for (i = 0; i < len; i++, j++) {
 674			buf[j] = *(tx_port_stats_ext +
 675				   bnxt_tx_port_stats_ext_arr[i].offset);
 676		}
 677		if (bp->pri2cos_valid) {
 678			for (i = 0; i < 8; i++, j++) {
 679				long n = bnxt_rx_bytes_pri_arr[i].base_off +
 680					 bp->pri2cos_idx[i];
 681
 682				buf[j] = *(rx_port_stats_ext + n);
 683			}
 684			for (i = 0; i < 8; i++, j++) {
 685				long n = bnxt_rx_pkts_pri_arr[i].base_off +
 686					 bp->pri2cos_idx[i];
 687
 688				buf[j] = *(rx_port_stats_ext + n);
 689			}
 690			for (i = 0; i < 8; i++, j++) {
 691				u8 cos_idx = bp->pri2cos_idx[i];
 692				long n;
 693
 694				n = bnxt_tx_bytes_pri_arr[i].base_off + cos_idx;
 695				buf[j] = *(tx_port_stats_ext + n);
 696				if (bp->cos0_cos1_shared && !cos_idx)
 697					buf[j] += *(tx_port_stats_ext + n + 1);
 698			}
 699			for (i = 0; i < 8; i++, j++) {
 700				u8 cos_idx = bp->pri2cos_idx[i];
 701				long n;
 702
 703				n = bnxt_tx_pkts_pri_arr[i].base_off + cos_idx;
 704				buf[j] = *(tx_port_stats_ext + n);
 705				if (bp->cos0_cos1_shared && !cos_idx)
 706					buf[j] += *(tx_port_stats_ext + n + 1);
 707			}
 708		}
 709	}
 710}
 711
 712static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
 713{
 714	struct bnxt *bp = netdev_priv(dev);
 715	u32 i, j, num_str;
 716	const char *str;
 717
 718	switch (stringset) {
 719	case ETH_SS_STATS:
 720		for (i = 0; i < bp->cp_nr_rings; i++) {
 721			if (is_rx_ring(bp, i))
 722				for (j = 0; j < NUM_RING_RX_HW_STATS; j++) {
 723					str = bnxt_ring_rx_stats_str[j];
 724					ethtool_sprintf(&buf, "[%d]: %s", i,
 725							str);
 726				}
 727			if (is_tx_ring(bp, i))
 728				for (j = 0; j < NUM_RING_TX_HW_STATS; j++) {
 729					str = bnxt_ring_tx_stats_str[j];
 730					ethtool_sprintf(&buf, "[%d]: %s", i,
 731							str);
 732				}
 733			num_str = bnxt_get_num_tpa_ring_stats(bp);
 734			if (!num_str || !is_rx_ring(bp, i))
 735				goto skip_tpa_stats;
 736
 737			if (bp->max_tpa_v2)
 738				for (j = 0; j < num_str; j++) {
 739					str = bnxt_ring_tpa2_stats_str[j];
 740					ethtool_sprintf(&buf, "[%d]: %s", i,
 741							str);
 742				}
 743			else
 744				for (j = 0; j < num_str; j++) {
 745					str = bnxt_ring_tpa_stats_str[j];
 746					ethtool_sprintf(&buf, "[%d]: %s", i,
 747							str);
 748				}
 749skip_tpa_stats:
 750			if (is_rx_ring(bp, i))
 751				for (j = 0; j < NUM_RING_RX_SW_STATS; j++) {
 752					str = bnxt_rx_sw_stats_str[j];
 753					ethtool_sprintf(&buf, "[%d]: %s", i,
 754							str);
 755				}
 756			for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) {
 757				str = bnxt_cmn_sw_stats_str[j];
 758				ethtool_sprintf(&buf, "[%d]: %s", i, str);
 759			}
 760		}
 761		for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++)
 762			ethtool_puts(&buf, bnxt_ring_err_stats_arr[i]);
 763
 764		if (bp->flags & BNXT_FLAG_PORT_STATS)
 765			for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
 766				str = bnxt_port_stats_arr[i].string;
 767				ethtool_puts(&buf, str);
 768			}
 769
 770		if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
 771			u32 len;
 772
 773			len = min_t(u32, bp->fw_rx_stats_ext_size,
 774				    ARRAY_SIZE(bnxt_port_stats_ext_arr));
 775			for (i = 0; i < len; i++) {
 776				str = bnxt_port_stats_ext_arr[i].string;
 777				ethtool_puts(&buf, str);
 778			}
 779
 780			len = min_t(u32, bp->fw_tx_stats_ext_size,
 781				    ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
 782			for (i = 0; i < len; i++) {
 783				str = bnxt_tx_port_stats_ext_arr[i].string;
 784				ethtool_puts(&buf, str);
 785			}
 786
 787			if (bp->pri2cos_valid) {
 788				for (i = 0; i < 8; i++) {
 789					str = bnxt_rx_bytes_pri_arr[i].string;
 790					ethtool_puts(&buf, str);
 791				}
 792
 793				for (i = 0; i < 8; i++) {
 794					str = bnxt_rx_pkts_pri_arr[i].string;
 795					ethtool_puts(&buf, str);
 796				}
 797
 798				for (i = 0; i < 8; i++) {
 799					str = bnxt_tx_bytes_pri_arr[i].string;
 800					ethtool_puts(&buf, str);
 801				}
 802
 803				for (i = 0; i < 8; i++) {
 804					str = bnxt_tx_pkts_pri_arr[i].string;
 805					ethtool_puts(&buf, str);
 806				}
 807			}
 808		}
 809		break;
 810	case ETH_SS_TEST:
 811		if (bp->num_tests)
 812			for (i = 0; i < bp->num_tests; i++)
 813				ethtool_puts(&buf, bp->test_info->string[i]);
 814		break;
 815	default:
 816		netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
 817			   stringset);
 818		break;
 819	}
 820}
 821
 822static void bnxt_get_ringparam(struct net_device *dev,
 823			       struct ethtool_ringparam *ering,
 824			       struct kernel_ethtool_ringparam *kernel_ering,
 825			       struct netlink_ext_ack *extack)
 826{
 827	struct bnxt *bp = netdev_priv(dev);
 828
 829	if (bp->flags & BNXT_FLAG_AGG_RINGS) {
 830		ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
 831		ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
 832		kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED;
 833	} else {
 834		ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
 835		ering->rx_jumbo_max_pending = 0;
 836		kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED;
 837	}
 838	ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
 839
 840	ering->rx_pending = bp->rx_ring_size;
 841	ering->rx_jumbo_pending = bp->rx_agg_ring_size;
 842	ering->tx_pending = bp->tx_ring_size;
 843
 844	kernel_ering->hds_thresh_max = BNXT_HDS_THRESHOLD_MAX;
 845}
 846
 847static int bnxt_set_ringparam(struct net_device *dev,
 848			      struct ethtool_ringparam *ering,
 849			      struct kernel_ethtool_ringparam *kernel_ering,
 850			      struct netlink_ext_ack *extack)
 851{
 852	u8 tcp_data_split = kernel_ering->tcp_data_split;
 853	struct bnxt *bp = netdev_priv(dev);
 854	u8 hds_config_mod;
 855
 856	if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
 857	    (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
 858	    (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
 859		return -EINVAL;
 860
 861	hds_config_mod = tcp_data_split != dev->cfg->hds_config;
 862	if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED && hds_config_mod)
 863		return -EINVAL;
 864
 865	if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED &&
 866	    hds_config_mod && BNXT_RX_PAGE_MODE(bp)) {
 867		NL_SET_ERR_MSG_MOD(extack, "tcp-data-split is disallowed when XDP is attached");
 868		return -EINVAL;
 869	}
 870
 871	if (netif_running(dev))
 872		bnxt_close_nic(bp, false, false);
 873
 874	if (hds_config_mod) {
 875		if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED)
 876			bp->flags |= BNXT_FLAG_HDS;
 877		else if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_UNKNOWN)
 878			bp->flags &= ~BNXT_FLAG_HDS;
 879	}
 880
 881	bp->rx_ring_size = ering->rx_pending;
 882	bp->tx_ring_size = ering->tx_pending;
 883	bnxt_set_ring_params(bp);
 884
 885	if (netif_running(dev))
 886		return bnxt_open_nic(bp, false, false);
 887
 888	return 0;
 889}
 890
 891static void bnxt_get_channels(struct net_device *dev,
 892			      struct ethtool_channels *channel)
 893{
 894	struct bnxt *bp = netdev_priv(dev);
 895	struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
 896	int max_rx_rings, max_tx_rings, tcs;
 897	int max_tx_sch_inputs, tx_grps;
 898
 899	/* Get the most up-to-date max_tx_sch_inputs. */
 900	if (netif_running(dev) && BNXT_NEW_RM(bp))
 901		bnxt_hwrm_func_resc_qcaps(bp, false);
 902	max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
 903
 904	bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
 905	if (max_tx_sch_inputs)
 906		max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
 907
 908	tcs = bp->num_tc;
 909	tx_grps = max(tcs, 1);
 910	if (bp->tx_nr_rings_xdp)
 911		tx_grps++;
 912	max_tx_rings /= tx_grps;
 913	channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
 914
 915	if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
 916		max_rx_rings = 0;
 917		max_tx_rings = 0;
 918	}
 919	if (max_tx_sch_inputs)
 920		max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
 921
 922	if (tcs > 1)
 923		max_tx_rings /= tcs;
 924
 925	channel->max_rx = max_rx_rings;
 926	channel->max_tx = max_tx_rings;
 927	channel->max_other = 0;
 928	if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
 929		channel->combined_count = bp->rx_nr_rings;
 930		if (BNXT_CHIP_TYPE_NITRO_A0(bp))
 931			channel->combined_count--;
 932	} else {
 933		if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
 934			channel->rx_count = bp->rx_nr_rings;
 935			channel->tx_count = bp->tx_nr_rings_per_tc;
 936		}
 937	}
 938}
 939
 940static int bnxt_set_channels(struct net_device *dev,
 941			     struct ethtool_channels *channel)
 942{
 943	struct bnxt *bp = netdev_priv(dev);
 944	int req_tx_rings, req_rx_rings, tcs;
 945	bool sh = false;
 946	int tx_xdp = 0;
 947	int rc = 0;
 948
 949	if (channel->other_count)
 950		return -EINVAL;
 951
 952	if (!channel->combined_count &&
 953	    (!channel->rx_count || !channel->tx_count))
 954		return -EINVAL;
 955
 956	if (channel->combined_count &&
 957	    (channel->rx_count || channel->tx_count))
 958		return -EINVAL;
 959
 960	if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
 961					    channel->tx_count))
 962		return -EINVAL;
 963
 964	if (channel->combined_count)
 965		sh = true;
 966
 967	tcs = bp->num_tc;
 968
 969	req_tx_rings = sh ? channel->combined_count : channel->tx_count;
 970	req_rx_rings = sh ? channel->combined_count : channel->rx_count;
 971	if (bp->tx_nr_rings_xdp) {
 972		if (!sh) {
 973			netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
 974			return -EINVAL;
 975		}
 976		tx_xdp = req_rx_rings;
 977	}
 978
 979	if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
 980	    bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
 981	    (netif_is_rxfh_configured(dev) || bp->num_rss_ctx)) {
 982		netdev_warn(dev, "RSS table size change required, RSS table entries must be default (with no additional RSS contexts present) to proceed\n");
 983		return -EINVAL;
 984	}
 985
 986	rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
 987	if (rc) {
 988		netdev_warn(dev, "Unable to allocate the requested rings\n");
 989		return rc;
 990	}
 991
 992	if (netif_running(dev)) {
 993		if (BNXT_PF(bp)) {
 994			/* TODO CHIMP_FW: Send message to all VF's
 995			 * before PF unload
 996			 */
 997		}
 998		bnxt_close_nic(bp, true, false);
 999	}
1000
1001	if (sh) {
1002		bp->flags |= BNXT_FLAG_SHARED_RINGS;
1003		bp->rx_nr_rings = channel->combined_count;
1004		bp->tx_nr_rings_per_tc = channel->combined_count;
1005	} else {
1006		bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
1007		bp->rx_nr_rings = channel->rx_count;
1008		bp->tx_nr_rings_per_tc = channel->tx_count;
1009	}
1010	bp->tx_nr_rings_xdp = tx_xdp;
1011	bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
1012	if (tcs > 1)
1013		bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
1014
1015	bnxt_set_cp_rings(bp, sh);
1016
1017	/* After changing number of rx channels, update NTUPLE feature. */
1018	netdev_update_features(dev);
1019	if (netif_running(dev)) {
1020		rc = bnxt_open_nic(bp, true, false);
1021		if ((!rc) && BNXT_PF(bp)) {
1022			/* TODO CHIMP_FW: Send message to all VF's
1023			 * to renable
1024			 */
1025		}
1026	} else {
1027		rc = bnxt_reserve_rings(bp, true);
1028	}
1029
1030	return rc;
1031}
1032
1033static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[],
1034				     int tbl_size, u32 *ids, u32 start,
1035				     u32 id_cnt)
1036{
1037	int i, j = start;
1038
1039	if (j >= id_cnt)
1040		return j;
1041	for (i = 0; i < tbl_size; i++) {
1042		struct hlist_head *head;
1043		struct bnxt_filter_base *fltr;
1044
1045		head = &tbl[i];
1046		hlist_for_each_entry_rcu(fltr, head, hash) {
1047			if (!fltr->flags ||
1048			    test_bit(BNXT_FLTR_FW_DELETED, &fltr->state))
1049				continue;
1050			ids[j++] = fltr->sw_id;
1051			if (j == id_cnt)
1052				return j;
1053		}
1054	}
1055	return j;
1056}
1057
1058static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp,
1059						      struct hlist_head tbl[],
1060						      int tbl_size, u32 id)
1061{
1062	int i;
1063
1064	for (i = 0; i < tbl_size; i++) {
1065		struct hlist_head *head;
1066		struct bnxt_filter_base *fltr;
1067
1068		head = &tbl[i];
1069		hlist_for_each_entry_rcu(fltr, head, hash) {
1070			if (fltr->flags && fltr->sw_id == id)
1071				return fltr;
1072		}
1073	}
1074	return NULL;
1075}
1076
1077static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
1078			    u32 *rule_locs)
1079{
1080	u32 count;
1081
1082	cmd->data = bp->ntp_fltr_count;
1083	rcu_read_lock();
1084	count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl,
1085					  BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0,
1086					  cmd->rule_cnt);
1087	cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl,
1088						  BNXT_NTP_FLTR_HASH_SIZE,
1089						  rule_locs, count,
1090						  cmd->rule_cnt);
1091	rcu_read_unlock();
1092
1093	return 0;
1094}
1095
1096static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1097{
1098	struct ethtool_rx_flow_spec *fs =
1099		(struct ethtool_rx_flow_spec *)&cmd->fs;
1100	struct bnxt_filter_base *fltr_base;
1101	struct bnxt_ntuple_filter *fltr;
1102	struct bnxt_flow_masks *fmasks;
1103	struct flow_keys *fkeys;
1104	int rc = -EINVAL;
1105
1106	if (fs->location >= bp->max_fltr)
1107		return rc;
1108
1109	rcu_read_lock();
1110	fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl,
1111					  BNXT_L2_FLTR_HASH_SIZE,
1112					  fs->location);
1113	if (fltr_base) {
1114		struct ethhdr *h_ether = &fs->h_u.ether_spec;
1115		struct ethhdr *m_ether = &fs->m_u.ether_spec;
1116		struct bnxt_l2_filter *l2_fltr;
1117		struct bnxt_l2_key *l2_key;
1118
1119		l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base);
1120		l2_key = &l2_fltr->l2_key;
1121		fs->flow_type = ETHER_FLOW;
1122		ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr);
1123		eth_broadcast_addr(m_ether->h_dest);
1124		if (l2_key->vlan) {
1125			struct ethtool_flow_ext *m_ext = &fs->m_ext;
1126			struct ethtool_flow_ext *h_ext = &fs->h_ext;
1127
1128			fs->flow_type |= FLOW_EXT;
1129			m_ext->vlan_tci = htons(0xfff);
1130			h_ext->vlan_tci = htons(l2_key->vlan);
1131		}
1132		if (fltr_base->flags & BNXT_ACT_RING_DST)
1133			fs->ring_cookie = fltr_base->rxq;
1134		if (fltr_base->flags & BNXT_ACT_FUNC_DST)
1135			fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) <<
1136					  ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
1137		rcu_read_unlock();
1138		return 0;
1139	}
1140	fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1141					  BNXT_NTP_FLTR_HASH_SIZE,
1142					  fs->location);
1143	if (!fltr_base) {
1144		rcu_read_unlock();
1145		return rc;
1146	}
1147	fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1148
1149	fkeys = &fltr->fkeys;
1150	fmasks = &fltr->fmasks;
1151	if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
1152		if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) {
1153			fs->flow_type = IP_USER_FLOW;
1154			fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
1155			fs->h_u.usr_ip4_spec.proto = BNXT_IP_PROTO_WILDCARD;
1156			fs->m_u.usr_ip4_spec.proto = 0;
1157		} else if (fkeys->basic.ip_proto == IPPROTO_ICMP) {
1158			fs->flow_type = IP_USER_FLOW;
1159			fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
1160			fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP;
1161			fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK;
1162		} else if (fkeys->basic.ip_proto == IPPROTO_TCP) {
1163			fs->flow_type = TCP_V4_FLOW;
1164		} else if (fkeys->basic.ip_proto == IPPROTO_UDP) {
1165			fs->flow_type = UDP_V4_FLOW;
1166		} else {
1167			goto fltr_err;
1168		}
1169
1170		fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1171		fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src;
1172		fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1173		fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst;
1174		if (fs->flow_type == TCP_V4_FLOW ||
1175		    fs->flow_type == UDP_V4_FLOW) {
1176			fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1177			fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src;
1178			fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1179			fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst;
1180		}
1181	} else {
1182		if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) {
1183			fs->flow_type = IPV6_USER_FLOW;
1184			fs->h_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_WILDCARD;
1185			fs->m_u.usr_ip6_spec.l4_proto = 0;
1186		} else if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) {
1187			fs->flow_type = IPV6_USER_FLOW;
1188			fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6;
1189			fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK;
1190		} else if (fkeys->basic.ip_proto == IPPROTO_TCP) {
1191			fs->flow_type = TCP_V6_FLOW;
1192		} else if (fkeys->basic.ip_proto == IPPROTO_UDP) {
1193			fs->flow_type = UDP_V6_FLOW;
1194		} else {
1195			goto fltr_err;
1196		}
1197
1198		*(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1199			fkeys->addrs.v6addrs.src;
1200		*(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] =
1201			fmasks->addrs.v6addrs.src;
1202		*(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1203			fkeys->addrs.v6addrs.dst;
1204		*(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] =
1205			fmasks->addrs.v6addrs.dst;
1206		if (fs->flow_type == TCP_V6_FLOW ||
1207		    fs->flow_type == UDP_V6_FLOW) {
1208			fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1209			fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src;
1210			fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1211			fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst;
1212		}
1213	}
1214
1215	if (fltr->base.flags & BNXT_ACT_DROP) {
1216		fs->ring_cookie = RX_CLS_FLOW_DISC;
1217	} else if (fltr->base.flags & BNXT_ACT_RSS_CTX) {
1218		fs->flow_type |= FLOW_RSS;
1219		cmd->rss_context = fltr->base.fw_vnic_id;
1220	} else {
1221		fs->ring_cookie = fltr->base.rxq;
1222	}
1223	rc = 0;
1224
1225fltr_err:
1226	rcu_read_unlock();
1227
1228	return rc;
1229}
1230
1231static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp,
1232							u32 index)
1233{
1234	struct ethtool_rxfh_context *ctx;
1235
1236	ctx = xa_load(&bp->dev->ethtool->rss_ctx, index);
1237	if (!ctx)
1238		return NULL;
1239	return ethtool_rxfh_context_priv(ctx);
1240}
1241
1242static int bnxt_alloc_vnic_rss_table(struct bnxt *bp,
1243				     struct bnxt_vnic_info *vnic)
1244{
1245	int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
1246
1247	vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
1248	vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev,
1249					     vnic->rss_table_size,
1250					     &vnic->rss_table_dma_addr,
1251					     GFP_KERNEL);
1252	if (!vnic->rss_table)
1253		return -ENOMEM;
1254
1255	vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
1256	vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
1257	return 0;
1258}
1259
1260static int bnxt_add_l2_cls_rule(struct bnxt *bp,
1261				struct ethtool_rx_flow_spec *fs)
1262{
1263	u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1264	u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1265	struct ethhdr *h_ether = &fs->h_u.ether_spec;
1266	struct ethhdr *m_ether = &fs->m_u.ether_spec;
1267	struct bnxt_l2_filter *fltr;
1268	struct bnxt_l2_key key;
1269	u16 vnic_id;
1270	u8 flags;
1271	int rc;
1272
1273	if (BNXT_CHIP_P5_PLUS(bp))
1274		return -EOPNOTSUPP;
1275
1276	if (!is_broadcast_ether_addr(m_ether->h_dest))
1277		return -EINVAL;
1278	ether_addr_copy(key.dst_mac_addr, h_ether->h_dest);
1279	key.vlan = 0;
1280	if (fs->flow_type & FLOW_EXT) {
1281		struct ethtool_flow_ext *m_ext = &fs->m_ext;
1282		struct ethtool_flow_ext *h_ext = &fs->h_ext;
1283
1284		if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci)
1285			return -EINVAL;
1286		key.vlan = ntohs(h_ext->vlan_tci);
1287	}
1288
1289	if (vf) {
1290		flags = BNXT_ACT_FUNC_DST;
1291		vnic_id = 0xffff;
1292		vf--;
1293	} else {
1294		flags = BNXT_ACT_RING_DST;
1295		vnic_id = bp->vnic_info[ring + 1].fw_vnic_id;
1296	}
1297	fltr = bnxt_alloc_new_l2_filter(bp, &key, flags);
1298	if (IS_ERR(fltr))
1299		return PTR_ERR(fltr);
1300
1301	fltr->base.fw_vnic_id = vnic_id;
1302	fltr->base.rxq = ring;
1303	fltr->base.vf_idx = vf;
1304	rc = bnxt_hwrm_l2_filter_alloc(bp, fltr);
1305	if (rc)
1306		bnxt_del_l2_filter(bp, fltr);
1307	else
1308		fs->location = fltr->base.sw_id;
1309	return rc;
1310}
1311
1312static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec,
1313					struct ethtool_usrip4_spec *ip_mask)
1314{
1315	u8 mproto = ip_mask->proto;
1316	u8 sproto = ip_spec->proto;
1317
1318	if (ip_mask->l4_4_bytes || ip_mask->tos ||
1319	    ip_spec->ip_ver != ETH_RX_NFC_IP4 ||
1320	    (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMP)))
1321		return false;
1322	return true;
1323}
1324
1325static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec,
1326					struct ethtool_usrip6_spec *ip_mask)
1327{
1328	u8 mproto = ip_mask->l4_proto;
1329	u8 sproto = ip_spec->l4_proto;
1330
1331	if (ip_mask->l4_4_bytes || ip_mask->tclass ||
1332	    (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMPV6)))
1333		return false;
1334	return true;
1335}
1336
1337static int bnxt_add_ntuple_cls_rule(struct bnxt *bp,
1338				    struct ethtool_rxnfc *cmd)
1339{
1340	struct ethtool_rx_flow_spec *fs = &cmd->fs;
1341	struct bnxt_ntuple_filter *new_fltr, *fltr;
1342	u32 flow_type = fs->flow_type & 0xff;
1343	struct bnxt_l2_filter *l2_fltr;
1344	struct bnxt_flow_masks *fmasks;
1345	struct flow_keys *fkeys;
1346	u32 idx;
1347	int rc;
1348
1349	if (!bp->vnic_info)
1350		return -EAGAIN;
1351
1352	if (fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT))
1353		return -EOPNOTSUPP;
1354
1355	if (fs->ring_cookie != RX_CLS_FLOW_DISC &&
1356	    ethtool_get_flow_spec_ring_vf(fs->ring_cookie))
1357		return -EOPNOTSUPP;
1358
1359	if (flow_type == IP_USER_FLOW) {
1360		if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec,
1361						 &fs->m_u.usr_ip4_spec))
1362			return -EOPNOTSUPP;
1363	}
1364
1365	if (flow_type == IPV6_USER_FLOW) {
1366		if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec,
1367						 &fs->m_u.usr_ip6_spec))
1368			return -EOPNOTSUPP;
1369	}
1370
1371	new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL);
1372	if (!new_fltr)
1373		return -ENOMEM;
1374
1375	l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0];
1376	atomic_inc(&l2_fltr->refcnt);
1377	new_fltr->l2_fltr = l2_fltr;
1378	fmasks = &new_fltr->fmasks;
1379	fkeys = &new_fltr->fkeys;
1380
1381	rc = -EOPNOTSUPP;
1382	switch (flow_type) {
1383	case IP_USER_FLOW: {
1384		struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec;
1385		struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec;
1386
1387		fkeys->basic.ip_proto = ip_mask->proto ? ip_spec->proto
1388						       : BNXT_IP_PROTO_WILDCARD;
1389		fkeys->basic.n_proto = htons(ETH_P_IP);
1390		fkeys->addrs.v4addrs.src = ip_spec->ip4src;
1391		fmasks->addrs.v4addrs.src = ip_mask->ip4src;
1392		fkeys->addrs.v4addrs.dst = ip_spec->ip4dst;
1393		fmasks->addrs.v4addrs.dst = ip_mask->ip4dst;
1394		break;
1395	}
1396	case TCP_V4_FLOW:
1397	case UDP_V4_FLOW: {
1398		struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec;
1399		struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec;
1400
1401		fkeys->basic.ip_proto = IPPROTO_TCP;
1402		if (flow_type == UDP_V4_FLOW)
1403			fkeys->basic.ip_proto = IPPROTO_UDP;
1404		fkeys->basic.n_proto = htons(ETH_P_IP);
1405		fkeys->addrs.v4addrs.src = ip_spec->ip4src;
1406		fmasks->addrs.v4addrs.src = ip_mask->ip4src;
1407		fkeys->addrs.v4addrs.dst = ip_spec->ip4dst;
1408		fmasks->addrs.v4addrs.dst = ip_mask->ip4dst;
1409		fkeys->ports.src = ip_spec->psrc;
1410		fmasks->ports.src = ip_mask->psrc;
1411		fkeys->ports.dst = ip_spec->pdst;
1412		fmasks->ports.dst = ip_mask->pdst;
1413		break;
1414	}
1415	case IPV6_USER_FLOW: {
1416		struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec;
1417		struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec;
1418
1419		fkeys->basic.ip_proto = ip_mask->l4_proto ? ip_spec->l4_proto
1420							  : BNXT_IP_PROTO_WILDCARD;
1421		fkeys->basic.n_proto = htons(ETH_P_IPV6);
1422		fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src;
1423		fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src;
1424		fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst;
1425		fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst;
1426		break;
1427	}
1428	case TCP_V6_FLOW:
1429	case UDP_V6_FLOW: {
1430		struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec;
1431		struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec;
1432
1433		fkeys->basic.ip_proto = IPPROTO_TCP;
1434		if (flow_type == UDP_V6_FLOW)
1435			fkeys->basic.ip_proto = IPPROTO_UDP;
1436		fkeys->basic.n_proto = htons(ETH_P_IPV6);
1437
1438		fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src;
1439		fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src;
1440		fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst;
1441		fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst;
1442		fkeys->ports.src = ip_spec->psrc;
1443		fmasks->ports.src = ip_mask->psrc;
1444		fkeys->ports.dst = ip_spec->pdst;
1445		fmasks->ports.dst = ip_mask->pdst;
1446		break;
1447	}
1448	default:
1449		rc = -EOPNOTSUPP;
1450		goto ntuple_err;
1451	}
1452	if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks)))
1453		goto ntuple_err;
1454
1455	idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL);
1456	rcu_read_lock();
1457	fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx);
1458	if (fltr) {
1459		rcu_read_unlock();
1460		rc = -EEXIST;
1461		goto ntuple_err;
1462	}
1463	rcu_read_unlock();
1464
1465	new_fltr->base.flags = BNXT_ACT_NO_AGING;
1466	if (fs->flow_type & FLOW_RSS) {
1467		struct bnxt_rss_ctx *rss_ctx;
1468
1469		new_fltr->base.fw_vnic_id = 0;
1470		new_fltr->base.flags |= BNXT_ACT_RSS_CTX;
1471		rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context);
1472		if (rss_ctx) {
1473			new_fltr->base.fw_vnic_id = rss_ctx->index;
1474		} else {
1475			rc = -EINVAL;
1476			goto ntuple_err;
1477		}
1478	}
1479	if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1480		new_fltr->base.flags |= BNXT_ACT_DROP;
1481	else
1482		new_fltr->base.rxq = ethtool_get_flow_spec_ring(fs->ring_cookie);
1483	__set_bit(BNXT_FLTR_VALID, &new_fltr->base.state);
1484	rc = bnxt_insert_ntp_filter(bp, new_fltr, idx);
1485	if (!rc) {
1486		rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr);
1487		if (rc) {
1488			bnxt_del_ntp_filter(bp, new_fltr);
1489			return rc;
1490		}
1491		fs->location = new_fltr->base.sw_id;
1492		return 0;
1493	}
1494
1495ntuple_err:
1496	atomic_dec(&l2_fltr->refcnt);
1497	kfree(new_fltr);
1498	return rc;
1499}
1500
1501static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1502{
1503	struct ethtool_rx_flow_spec *fs = &cmd->fs;
1504	u32 ring, flow_type;
1505	int rc;
1506	u8 vf;
1507
1508	if (!netif_running(bp->dev))
1509		return -EAGAIN;
1510	if (!(bp->flags & BNXT_FLAG_RFS))
1511		return -EPERM;
1512	if (fs->location != RX_CLS_LOC_ANY)
1513		return -EINVAL;
1514
1515	flow_type = fs->flow_type;
1516	if ((flow_type == IP_USER_FLOW ||
1517	     flow_type == IPV6_USER_FLOW) &&
1518	    !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO))
1519		return -EOPNOTSUPP;
1520	if (flow_type & FLOW_MAC_EXT)
1521		return -EINVAL;
1522	flow_type &= ~FLOW_EXT;
1523
1524	if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW)
1525		return bnxt_add_ntuple_cls_rule(bp, cmd);
1526
1527	ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1528	vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1529	if (BNXT_VF(bp) && vf)
1530		return -EINVAL;
1531	if (BNXT_PF(bp) && vf > bp->pf.active_vfs)
1532		return -EINVAL;
1533	if (!vf && ring >= bp->rx_nr_rings)
1534		return -EINVAL;
1535
1536	if (flow_type == ETHER_FLOW)
1537		rc = bnxt_add_l2_cls_rule(bp, fs);
1538	else
1539		rc = bnxt_add_ntuple_cls_rule(bp, cmd);
1540	return rc;
1541}
1542
1543static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1544{
1545	struct ethtool_rx_flow_spec *fs = &cmd->fs;
1546	struct bnxt_filter_base *fltr_base;
1547	struct bnxt_ntuple_filter *fltr;
1548	u32 id = fs->location;
1549
1550	rcu_read_lock();
1551	fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl,
1552					  BNXT_L2_FLTR_HASH_SIZE, id);
1553	if (fltr_base) {
1554		struct bnxt_l2_filter *l2_fltr;
1555
1556		l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base);
1557		rcu_read_unlock();
1558		bnxt_hwrm_l2_filter_free(bp, l2_fltr);
1559		bnxt_del_l2_filter(bp, l2_fltr);
1560		return 0;
1561	}
1562	fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1563					  BNXT_NTP_FLTR_HASH_SIZE, id);
1564	if (!fltr_base) {
1565		rcu_read_unlock();
1566		return -ENOENT;
1567	}
1568
1569	fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1570	if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) {
1571		rcu_read_unlock();
1572		return -EINVAL;
1573	}
1574	rcu_read_unlock();
1575	bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr);
1576	bnxt_del_ntp_filter(bp, fltr);
1577	return 0;
1578}
1579
1580static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1581{
1582	if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1583		return RXH_IP_SRC | RXH_IP_DST;
1584	return 0;
1585}
1586
1587static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1588{
1589	if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1590		return RXH_IP_SRC | RXH_IP_DST;
1591	if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL)
1592		return RXH_IP_SRC | RXH_IP_DST | RXH_IP6_FL;
1593	return 0;
1594}
1595
1596static int bnxt_get_rxfh_fields(struct net_device *dev,
1597				struct ethtool_rxfh_fields *cmd)
1598{
1599	struct bnxt *bp = netdev_priv(dev);
1600
1601	cmd->data = 0;
1602	switch (cmd->flow_type) {
1603	case TCP_V4_FLOW:
1604		if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1605			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1606				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1607		cmd->data |= get_ethtool_ipv4_rss(bp);
1608		break;
1609	case UDP_V4_FLOW:
1610		if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1611			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1612				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1613		fallthrough;
1614	case AH_ESP_V4_FLOW:
1615		if (bp->rss_hash_cfg &
1616		    (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1617		     VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4))
1618			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1619				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1620		fallthrough;
1621	case SCTP_V4_FLOW:
1622	case AH_V4_FLOW:
1623	case ESP_V4_FLOW:
1624	case IPV4_FLOW:
1625		cmd->data |= get_ethtool_ipv4_rss(bp);
1626		break;
1627
1628	case TCP_V6_FLOW:
1629		if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1630			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1631				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1632		cmd->data |= get_ethtool_ipv6_rss(bp);
1633		break;
1634	case UDP_V6_FLOW:
1635		if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1636			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1637				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1638		fallthrough;
1639	case AH_ESP_V6_FLOW:
1640		if (bp->rss_hash_cfg &
1641		    (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1642		     VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6))
1643			cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1644				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
1645		fallthrough;
1646	case SCTP_V6_FLOW:
1647	case AH_V6_FLOW:
1648	case ESP_V6_FLOW:
1649	case IPV6_FLOW:
1650		cmd->data |= get_ethtool_ipv6_rss(bp);
1651		break;
1652	}
1653	return 0;
1654}
1655
1656#define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1657#define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1658
1659static int bnxt_set_rxfh_fields(struct net_device *dev,
1660				const struct ethtool_rxfh_fields *cmd,
1661				struct netlink_ext_ack *extack)
1662{
1663	struct bnxt *bp = netdev_priv(dev);
1664	int tuple, rc = 0;
1665	u32 rss_hash_cfg;
1666
1667	rss_hash_cfg = bp->rss_hash_cfg;
1668
1669	if (cmd->data == RXH_4TUPLE)
1670		tuple = 4;
1671	else if (cmd->data == RXH_2TUPLE ||
1672		 cmd->data == (RXH_2TUPLE | RXH_IP6_FL))
1673		tuple = 2;
1674	else if (!cmd->data)
1675		tuple = 0;
1676	else
1677		return -EINVAL;
1678
1679	if (cmd->data & RXH_IP6_FL &&
1680	    !(bp->rss_cap & BNXT_RSS_CAP_IPV6_FLOW_LABEL_RSS_CAP))
1681		return -EINVAL;
1682
1683	if (cmd->flow_type == TCP_V4_FLOW) {
1684		rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1685		if (tuple == 4)
1686			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1687	} else if (cmd->flow_type == UDP_V4_FLOW) {
1688		if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1689			return -EINVAL;
1690		rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1691		if (tuple == 4)
1692			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1693	} else if (cmd->flow_type == TCP_V6_FLOW) {
1694		rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1695		if (tuple == 4)
1696			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1697	} else if (cmd->flow_type == UDP_V6_FLOW) {
1698		if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1699			return -EINVAL;
1700		rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1701		if (tuple == 4)
1702			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1703	} else if (cmd->flow_type == AH_ESP_V4_FLOW) {
1704		if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) ||
1705				   !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP)))
1706			return -EINVAL;
1707		rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1708				  VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4);
1709		if (tuple == 4)
1710			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1711					VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4;
1712	} else if (cmd->flow_type == AH_ESP_V6_FLOW) {
1713		if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) ||
1714				   !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP)))
1715			return -EINVAL;
1716		rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1717				  VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6);
1718		if (tuple == 4)
1719			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1720					VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6;
1721	} else if (tuple == 4) {
1722		return -EINVAL;
1723	}
1724
1725	switch (cmd->flow_type) {
1726	case TCP_V4_FLOW:
1727	case UDP_V4_FLOW:
1728	case SCTP_V4_FLOW:
1729	case AH_ESP_V4_FLOW:
1730	case AH_V4_FLOW:
1731	case ESP_V4_FLOW:
1732	case IPV4_FLOW:
1733		if (tuple == 2)
1734			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1735		else if (!tuple)
1736			rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1737		break;
1738
1739	case TCP_V6_FLOW:
1740	case UDP_V6_FLOW:
1741	case SCTP_V6_FLOW:
1742	case AH_ESP_V6_FLOW:
1743	case AH_V6_FLOW:
1744	case ESP_V6_FLOW:
1745	case IPV6_FLOW:
1746		rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
1747				  VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL);
1748		if (!tuple)
1749			break;
1750		if (cmd->data & RXH_IP6_FL)
1751			rss_hash_cfg |=
1752				VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL;
1753		else if (tuple == 2)
1754			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1755		break;
1756	}
1757
1758	if (bp->rss_hash_cfg == rss_hash_cfg)
1759		return 0;
1760
1761	if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)
1762		bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg;
1763	bp->rss_hash_cfg = rss_hash_cfg;
1764	if (netif_running(bp->dev)) {
1765		bnxt_close_nic(bp, false, false);
1766		rc = bnxt_open_nic(bp, false, false);
1767	}
1768	return rc;
1769}
1770
1771static u32 bnxt_get_rx_ring_count(struct net_device *dev)
1772{
1773	struct bnxt *bp = netdev_priv(dev);
1774
1775	return bp->rx_nr_rings;
1776}
1777
1778static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1779			  u32 *rule_locs)
1780{
1781	struct bnxt *bp = netdev_priv(dev);
1782	int rc = 0;
1783
1784	switch (cmd->cmd) {
1785	case ETHTOOL_GRXCLSRLCNT:
1786		cmd->rule_cnt = bp->ntp_fltr_count;
1787		cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL;
1788		break;
1789
1790	case ETHTOOL_GRXCLSRLALL:
1791		rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1792		break;
1793
1794	case ETHTOOL_GRXCLSRULE:
1795		rc = bnxt_grxclsrule(bp, cmd);
1796		break;
1797
1798	default:
1799		rc = -EOPNOTSUPP;
1800		break;
1801	}
1802
1803	return rc;
1804}
1805
1806static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1807{
1808	struct bnxt *bp = netdev_priv(dev);
1809	int rc;
1810
1811	switch (cmd->cmd) {
1812	case ETHTOOL_SRXCLSRLINS:
1813		rc = bnxt_srxclsrlins(bp, cmd);
1814		break;
1815
1816	case ETHTOOL_SRXCLSRLDEL:
1817		rc = bnxt_srxclsrldel(bp, cmd);
1818		break;
1819
1820	default:
1821		rc = -EOPNOTSUPP;
1822		break;
1823	}
1824	return rc;
1825}
1826
1827u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1828{
1829	struct bnxt *bp = netdev_priv(dev);
1830
1831	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
1832		return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) *
1833		       BNXT_RSS_TABLE_ENTRIES_P5;
1834	return HW_HASH_INDEX_SIZE;
1835}
1836
1837static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1838{
1839	return HW_HASH_KEY_SIZE;
1840}
1841
1842static int bnxt_get_rxfh(struct net_device *dev,
1843			 struct ethtool_rxfh_param *rxfh)
1844{
1845	struct bnxt_rss_ctx *rss_ctx = NULL;
1846	struct bnxt *bp = netdev_priv(dev);
1847	u32 *indir_tbl = bp->rss_indir_tbl;
1848	struct bnxt_vnic_info *vnic;
1849	u32 i, tbl_size;
1850
1851	rxfh->hfunc = ETH_RSS_HASH_TOP;
1852
1853	if (!bp->vnic_info)
1854		return 0;
1855
1856	vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
1857	if (rxfh->rss_context) {
1858		struct ethtool_rxfh_context *ctx;
1859
1860		ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context);
1861		if (!ctx)
1862			return -EINVAL;
1863		indir_tbl = ethtool_rxfh_context_indir(ctx);
1864		rss_ctx = ethtool_rxfh_context_priv(ctx);
1865		vnic = &rss_ctx->vnic;
1866	}
1867
1868	if (rxfh->indir && indir_tbl) {
1869		tbl_size = bnxt_get_rxfh_indir_size(dev);
1870		for (i = 0; i < tbl_size; i++)
1871			rxfh->indir[i] = indir_tbl[i];
1872	}
1873
1874	if (rxfh->key && vnic->rss_hash_key)
1875		memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1876
1877	return 0;
1878}
1879
1880static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx,
1881			    struct bnxt_rss_ctx *rss_ctx,
1882			    const struct ethtool_rxfh_param *rxfh)
1883{
1884	if (rxfh->key) {
1885		if (rss_ctx) {
1886			memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key,
1887			       HW_HASH_KEY_SIZE);
1888		} else {
1889			memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE);
1890			bp->rss_hash_key_updated = true;
1891		}
1892	}
1893	if (rxfh->indir) {
1894		u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
1895		u32 *indir_tbl = bp->rss_indir_tbl;
1896
1897		if (rss_ctx)
1898			indir_tbl = ethtool_rxfh_context_indir(ctx);
1899		for (i = 0; i < tbl_size; i++)
1900			indir_tbl[i] = rxfh->indir[i];
1901		pad = bp->rss_indir_tbl_entries - tbl_size;
1902		if (pad)
1903			memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl));
1904	}
1905}
1906
1907static int bnxt_rxfh_context_check(struct bnxt *bp,
1908				   const struct ethtool_rxfh_param *rxfh,
1909				   struct netlink_ext_ack *extack)
1910{
1911	if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) {
1912		NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported");
1913		return -EOPNOTSUPP;
1914	}
1915
1916	if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) {
1917		NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported");
1918		return -EOPNOTSUPP;
1919	}
1920
1921	if (!netif_running(bp->dev)) {
1922		NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down");
1923		return -EAGAIN;
1924	}
1925
1926	return 0;
1927}
1928
1929static int bnxt_create_rxfh_context(struct net_device *dev,
1930				    struct ethtool_rxfh_context *ctx,
1931				    const struct ethtool_rxfh_param *rxfh,
1932				    struct netlink_ext_ack *extack)
1933{
1934	struct bnxt *bp = netdev_priv(dev);
1935	struct bnxt_rss_ctx *rss_ctx;
1936	struct bnxt_vnic_info *vnic;
1937	int rc;
1938
1939	rc = bnxt_rxfh_context_check(bp, rxfh, extack);
1940	if (rc)
1941		return rc;
1942
1943	if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) {
1944		NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u",
1945				       BNXT_MAX_ETH_RSS_CTX);
1946		return -EINVAL;
1947	}
1948
1949	if (!bnxt_rfs_capable(bp, true)) {
1950		NL_SET_ERR_MSG_MOD(extack, "Out hardware resources");
1951		return -ENOMEM;
1952	}
1953
1954	rss_ctx = ethtool_rxfh_context_priv(ctx);
1955
1956	bp->num_rss_ctx++;
1957
1958	vnic = &rss_ctx->vnic;
1959	vnic->rss_ctx = ctx;
1960	vnic->flags |= BNXT_VNIC_RSSCTX_FLAG;
1961	vnic->vnic_id = BNXT_VNIC_ID_INVALID;
1962	rc = bnxt_alloc_vnic_rss_table(bp, vnic);
1963	if (rc)
1964		goto out;
1965
1966	/* Populate defaults in the context */
1967	bnxt_set_dflt_rss_indir_tbl(bp, ctx);
1968	ctx->hfunc = ETH_RSS_HASH_TOP;
1969	memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE);
1970	memcpy(ethtool_rxfh_context_key(ctx),
1971	       bp->rss_hash_key, HW_HASH_KEY_SIZE);
1972
1973	rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings);
1974	if (rc) {
1975		NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC");
1976		goto out;
1977	}
1978
1979	rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA);
1980	if (rc) {
1981		NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA");
1982		goto out;
1983	}
1984	bnxt_modify_rss(bp, ctx, rss_ctx, rxfh);
1985
1986	rc = __bnxt_setup_vnic_p5(bp, vnic);
1987	if (rc) {
1988		NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA");
1989		goto out;
1990	}
1991
1992	rss_ctx->index = rxfh->rss_context;
1993	return 0;
1994out:
1995	bnxt_del_one_rss_ctx(bp, rss_ctx, true);
1996	return rc;
1997}
1998
1999static int bnxt_modify_rxfh_context(struct net_device *dev,
2000				    struct ethtool_rxfh_context *ctx,
2001				    const struct ethtool_rxfh_param *rxfh,
2002				    struct netlink_ext_ack *extack)
2003{
2004	struct bnxt *bp = netdev_priv(dev);
2005	struct bnxt_rss_ctx *rss_ctx;
2006	int rc;
2007
2008	rc = bnxt_rxfh_context_check(bp, rxfh, extack);
2009	if (rc)
2010		return rc;
2011
2012	rss_ctx = ethtool_rxfh_context_priv(ctx);
2013
2014	bnxt_modify_rss(bp, ctx, rss_ctx, rxfh);
2015
2016	return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic);
2017}
2018
2019static int bnxt_remove_rxfh_context(struct net_device *dev,
2020				    struct ethtool_rxfh_context *ctx,
2021				    u32 rss_context,
2022				    struct netlink_ext_ack *extack)
2023{
2024	struct bnxt *bp = netdev_priv(dev);
2025	struct bnxt_rss_ctx *rss_ctx;
2026
2027	rss_ctx = ethtool_rxfh_context_priv(ctx);
2028
2029	bnxt_del_one_rss_ctx(bp, rss_ctx, true);
2030	return 0;
2031}
2032
2033static int bnxt_set_rxfh(struct net_device *dev,
2034			 struct ethtool_rxfh_param *rxfh,
2035			 struct netlink_ext_ack *extack)
2036{
2037	struct bnxt *bp = netdev_priv(dev);
2038	int rc = 0;
2039
2040	if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP)
2041		return -EOPNOTSUPP;
2042
2043	bnxt_modify_rss(bp, NULL, NULL, rxfh);
2044
2045	if (netif_running(bp->dev)) {
2046		bnxt_close_nic(bp, false, false);
2047		rc = bnxt_open_nic(bp, false, false);
2048	}
2049	return rc;
2050}
2051
2052static void bnxt_get_drvinfo(struct net_device *dev,
2053			     struct ethtool_drvinfo *info)
2054{
2055	struct bnxt *bp = netdev_priv(dev);
2056
2057	strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
2058	strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
2059	strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
2060	info->n_stats = bnxt_get_num_stats(bp);
2061	info->testinfo_len = bp->num_tests;
2062	/* TODO CHIMP_FW: eeprom dump details */
2063	info->eedump_len = 0;
2064	/* TODO CHIMP FW: reg dump details */
2065	info->regdump_len = 0;
2066}
2067
2068static int bnxt_get_regs_len(struct net_device *dev)
2069{
2070	struct bnxt *bp = netdev_priv(dev);
2071
2072	if (!BNXT_PF(bp))
2073		return -EOPNOTSUPP;
2074
2075	return BNXT_PXP_REG_LEN + bp->pcie_stat_len;
2076}
2077
2078static void *
2079__bnxt_hwrm_pcie_qstats(struct bnxt *bp, struct hwrm_pcie_qstats_input *req)
2080{
2081	struct pcie_ctx_hw_stats_v2 *hw_pcie_stats;
2082	dma_addr_t hw_pcie_stats_addr;
2083	int rc;
2084
2085	hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
2086					   &hw_pcie_stats_addr);
2087	if (!hw_pcie_stats)
2088		return NULL;
2089
2090	req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
2091	req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
2092	rc = hwrm_req_send(bp, req);
2093
2094	return rc ? NULL : hw_pcie_stats;
2095}
2096
2097#define BNXT_PCIE_32B_ENTRY(start, end)			\
2098	 { offsetof(struct pcie_ctx_hw_stats_v2, start),\
2099	   offsetof(struct pcie_ctx_hw_stats_v2, end) }
2100
2101static const struct {
2102	u16 start;
2103	u16 end;
2104} bnxt_pcie_32b_entries[] = {
2105	BNXT_PCIE_32B_ENTRY(pcie_ltssm_histogram[0], pcie_ltssm_histogram[3]),
2106	BNXT_PCIE_32B_ENTRY(pcie_tl_credit_nph_histogram[0], unused_1),
2107	BNXT_PCIE_32B_ENTRY(pcie_rd_latency_histogram[0], unused_2),
2108};
2109
2110static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2111			  void *_p)
2112{
2113	struct hwrm_pcie_qstats_output *resp;
2114	struct hwrm_pcie_qstats_input *req;
2115	struct bnxt *bp = netdev_priv(dev);
2116	u8 *src;
2117
2118	regs->version = 0;
2119	if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED))
2120		bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
2121
2122	if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
2123		return;
2124
2125	if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
2126		return;
2127
2128	resp = hwrm_req_hold(bp, req);
2129	src = __bnxt_hwrm_pcie_qstats(bp, req);
2130	if (src) {
2131		u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN);
2132		int i, j, len;
2133
2134		len = min(bp->pcie_stat_len, le16_to_cpu(resp->pcie_stat_size));
2135		if (len <= sizeof(struct pcie_ctx_hw_stats))
2136			regs->version = 1;
2137		else if (len < sizeof(struct pcie_ctx_hw_stats_v2))
2138			regs->version = 2;
2139		else
2140			regs->version = 3;
2141
2142		for (i = 0, j = 0; i < len; ) {
2143			if (i >= bnxt_pcie_32b_entries[j].start &&
2144			    i <= bnxt_pcie_32b_entries[j].end) {
2145				u32 *dst32 = (u32 *)(dst + i);
2146
2147				*dst32 = le32_to_cpu(*(__le32 *)(src + i));
2148				i += 4;
2149				if (i > bnxt_pcie_32b_entries[j].end &&
2150				    j < ARRAY_SIZE(bnxt_pcie_32b_entries) - 1)
2151					j++;
2152			} else {
2153				u64 *dst64 = (u64 *)(dst + i);
2154
2155				*dst64 = le64_to_cpu(*(__le64 *)(src + i));
2156				i += 8;
2157			}
2158		}
2159	}
2160	hwrm_req_drop(bp, req);
2161}
2162
2163static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2164{
2165	struct bnxt *bp = netdev_priv(dev);
2166
2167	wol->supported = 0;
2168	wol->wolopts = 0;
2169	memset(&wol->sopass, 0, sizeof(wol->sopass));
2170	if (bp->flags & BNXT_FLAG_WOL_CAP) {
2171		wol->supported = WAKE_MAGIC;
2172		if (bp->wol)
2173			wol->wolopts = WAKE_MAGIC;
2174	}
2175}
2176
2177static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2178{
2179	struct bnxt *bp = netdev_priv(dev);
2180
2181	if (wol->wolopts & ~WAKE_MAGIC)
2182		return -EINVAL;
2183
2184	if (wol->wolopts & WAKE_MAGIC) {
2185		if (!(bp->flags & BNXT_FLAG_WOL_CAP))
2186			return -EINVAL;
2187		if (!bp->wol) {
2188			if (bnxt_hwrm_alloc_wol_fltr(bp))
2189				return -EBUSY;
2190			bp->wol = 1;
2191		}
2192	} else {
2193		if (bp->wol) {
2194			if (bnxt_hwrm_free_wol_fltr(bp))
2195				return -EBUSY;
2196			bp->wol = 0;
2197		}
2198	}
2199	return 0;
2200}
2201
2202/* TODO: support 25GB, 40GB, 50GB with different cable type */
2203void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds)
2204{
2205	linkmode_zero(mode);
2206
2207	if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
2208		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode);
2209	if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
2210		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode);
2211	if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
2212		linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode);
2213	if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
2214		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode);
2215	if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
2216		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode);
2217}
2218
2219enum bnxt_media_type {
2220	BNXT_MEDIA_UNKNOWN = 0,
2221	BNXT_MEDIA_TP,
2222	BNXT_MEDIA_CR,
2223	BNXT_MEDIA_SR,
2224	BNXT_MEDIA_LR_ER_FR,
2225	BNXT_MEDIA_KR,
2226	BNXT_MEDIA_KX,
2227	BNXT_MEDIA_X,
2228	__BNXT_MEDIA_END,
2229};
2230
2231static const enum bnxt_media_type bnxt_phy_types[] = {
2232	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR,
2233	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] =  BNXT_MEDIA_KR,
2234	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR,
2235	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR,
2236	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR,
2237	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX,
2238	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR,
2239	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP,
2240	[PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP,
2241	[PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR,
2242	[PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR,
2243	[PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR,
2244	[PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR,
2245	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR,
2246	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR,
2247	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2248	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2249	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR,
2250	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR,
2251	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR,
2252	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2253	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2254	[PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR,
2255	[PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP,
2256	[PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X,
2257	[PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X,
2258	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR,
2259	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR,
2260	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2261	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2262	[PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR,
2263	[PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR,
2264	[PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR,
2265	[PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR,
2266	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR,
2267	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR,
2268	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
2269	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
2270	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR,
2271	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR,
2272	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR,
2273	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR,
2274	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR,
2275	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR,
2276	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
2277	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
2278	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR,
2279	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR,
2280	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR,
2281	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR,
2282	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR,
2283	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR,
2284	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2285	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2286};
2287
2288static enum bnxt_media_type
2289bnxt_get_media(struct bnxt_link_info *link_info)
2290{
2291	switch (link_info->media_type) {
2292	case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP:
2293		return BNXT_MEDIA_TP;
2294	case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC:
2295		return BNXT_MEDIA_CR;
2296	default:
2297		if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types))
2298			return bnxt_phy_types[link_info->phy_type];
2299		return BNXT_MEDIA_UNKNOWN;
2300	}
2301}
2302
2303enum bnxt_link_speed_indices {
2304	BNXT_LINK_SPEED_UNKNOWN = 0,
2305	BNXT_LINK_SPEED_100MB_IDX,
2306	BNXT_LINK_SPEED_1GB_IDX,
2307	BNXT_LINK_SPEED_10GB_IDX,
2308	BNXT_LINK_SPEED_25GB_IDX,
2309	BNXT_LINK_SPEED_40GB_IDX,
2310	BNXT_LINK_SPEED_50GB_IDX,
2311	BNXT_LINK_SPEED_100GB_IDX,
2312	BNXT_LINK_SPEED_200GB_IDX,
2313	BNXT_LINK_SPEED_400GB_IDX,
2314	__BNXT_LINK_SPEED_END
2315};
2316
2317static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed)
2318{
2319	switch (speed) {
2320	case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX;
2321	case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX;
2322	case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX;
2323	case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX;
2324	case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX;
2325	case BNXT_LINK_SPEED_50GB:
2326	case BNXT_LINK_SPEED_50GB_PAM4:
2327		return BNXT_LINK_SPEED_50GB_IDX;
2328	case BNXT_LINK_SPEED_100GB:
2329	case BNXT_LINK_SPEED_100GB_PAM4:
2330	case BNXT_LINK_SPEED_100GB_PAM4_112:
2331		return BNXT_LINK_SPEED_100GB_IDX;
2332	case BNXT_LINK_SPEED_200GB:
2333	case BNXT_LINK_SPEED_200GB_PAM4:
2334	case BNXT_LINK_SPEED_200GB_PAM4_112:
2335		return BNXT_LINK_SPEED_200GB_IDX;
2336	case BNXT_LINK_SPEED_400GB:
2337	case BNXT_LINK_SPEED_400GB_PAM4:
2338	case BNXT_LINK_SPEED_400GB_PAM4_112:
2339		return BNXT_LINK_SPEED_400GB_IDX;
2340	default: return BNXT_LINK_SPEED_UNKNOWN;
2341	}
2342}
2343
2344static const enum ethtool_link_mode_bit_indices
2345bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = {
2346	[BNXT_LINK_SPEED_100MB_IDX] = {
2347		{
2348			[BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2349		},
2350	},
2351	[BNXT_LINK_SPEED_1GB_IDX] = {
2352		{
2353			[BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2354			/* historically baseT, but DAC is more correctly baseX */
2355			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2356			[BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2357			[BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2358			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2359		},
2360	},
2361	[BNXT_LINK_SPEED_10GB_IDX] = {
2362		{
2363			[BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2364			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2365			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2366			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2367			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2368			[BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2369		},
2370	},
2371	[BNXT_LINK_SPEED_25GB_IDX] = {
2372		{
2373			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2374			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2375			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2376		},
2377	},
2378	[BNXT_LINK_SPEED_40GB_IDX] = {
2379		{
2380			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2381			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2382			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2383			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2384		},
2385	},
2386	[BNXT_LINK_SPEED_50GB_IDX] = {
2387		[BNXT_SIG_MODE_NRZ] = {
2388			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2389			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2390			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2391		},
2392		[BNXT_SIG_MODE_PAM4] = {
2393			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2394			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2395			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2396			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2397		},
2398	},
2399	[BNXT_LINK_SPEED_100GB_IDX] = {
2400		[BNXT_SIG_MODE_NRZ] = {
2401			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2402			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2403			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2404			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2405		},
2406		[BNXT_SIG_MODE_PAM4] = {
2407			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2408			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2409			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2410			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2411		},
2412		[BNXT_SIG_MODE_PAM4_112] = {
2413			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT,
2414			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
2415			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
2416			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
2417		},
2418	},
2419	[BNXT_LINK_SPEED_200GB_IDX] = {
2420		[BNXT_SIG_MODE_PAM4] = {
2421			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2422			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2423			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2424			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2425		},
2426		[BNXT_SIG_MODE_PAM4_112] = {
2427			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT,
2428			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
2429			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
2430			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
2431		},
2432	},
2433	[BNXT_LINK_SPEED_400GB_IDX] = {
2434		[BNXT_SIG_MODE_PAM4] = {
2435			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
2436			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
2437			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
2438			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
2439		},
2440		[BNXT_SIG_MODE_PAM4_112] = {
2441			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT,
2442			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
2443			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
2444			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
2445		},
2446	},
2447};
2448
2449#define BNXT_LINK_MODE_UNKNOWN -1
2450
2451static enum ethtool_link_mode_bit_indices
2452bnxt_get_link_mode(struct bnxt_link_info *link_info)
2453{
2454	enum ethtool_link_mode_bit_indices link_mode;
2455	enum bnxt_link_speed_indices speed;
2456	enum bnxt_media_type media;
2457	u8 sig_mode;
2458
2459	if (link_info->phy_link_status != BNXT_LINK_LINK)
2460		return BNXT_LINK_MODE_UNKNOWN;
2461
2462	media = bnxt_get_media(link_info);
2463	if (BNXT_AUTO_MODE(link_info->auto_mode)) {
2464		speed = bnxt_fw_speed_idx(link_info->link_speed);
2465		sig_mode = link_info->active_fec_sig_mode &
2466			PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
2467	} else {
2468		speed = bnxt_fw_speed_idx(link_info->req_link_speed);
2469		sig_mode = link_info->req_signal_mode;
2470	}
2471	if (sig_mode >= BNXT_SIG_MODE_MAX)
2472		return BNXT_LINK_MODE_UNKNOWN;
2473
2474	/* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux
2475	 * link mode, but since no such devices exist, the zeroes in the
2476	 * map can be conveniently used to represent unknown link modes.
2477	 */
2478	link_mode = bnxt_link_modes[speed][sig_mode][media];
2479	if (!link_mode)
2480		return BNXT_LINK_MODE_UNKNOWN;
2481
2482	switch (link_mode) {
2483	case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
2484		if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2485			link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT;
2486		break;
2487	case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
2488		if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2489			link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT;
2490		break;
2491	default:
2492		break;
2493	}
2494
2495	return link_mode;
2496}
2497
2498static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info,
2499				   struct ethtool_link_ksettings *lk_ksettings)
2500{
2501	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2502
2503	if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) {
2504		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2505				 lk_ksettings->link_modes.supported);
2506		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2507				 lk_ksettings->link_modes.supported);
2508	}
2509
2510	if (link_info->support_auto_speeds || link_info->support_auto_speeds2 ||
2511	    link_info->support_pam4_auto_speeds)
2512		linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2513				 lk_ksettings->link_modes.supported);
2514
2515	if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2516		return;
2517
2518	if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX)
2519		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2520				 lk_ksettings->link_modes.advertising);
2521	if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1)
2522		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2523				 lk_ksettings->link_modes.advertising);
2524	if (link_info->lp_pause & BNXT_LINK_PAUSE_RX)
2525		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2526				 lk_ksettings->link_modes.lp_advertising);
2527	if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1)
2528		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2529				 lk_ksettings->link_modes.lp_advertising);
2530}
2531
2532static const u16 bnxt_nrz_speed_masks[] = {
2533	[BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB,
2534	[BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB,
2535	[BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB,
2536	[BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB,
2537	[BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB,
2538	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB,
2539	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB,
2540	[__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2541};
2542
2543static const u16 bnxt_pam4_speed_masks[] = {
2544	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB,
2545	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB,
2546	[BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB,
2547	[__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2548};
2549
2550static const u16 bnxt_nrz_speeds2_masks[] = {
2551	[BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB,
2552	[BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB,
2553	[BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB,
2554	[BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB,
2555	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB,
2556	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB,
2557	[__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2558};
2559
2560static const u16 bnxt_pam4_speeds2_masks[] = {
2561	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4,
2562	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4,
2563	[BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4,
2564	[BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4,
2565};
2566
2567static const u16 bnxt_pam4_112_speeds2_masks[] = {
2568	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112,
2569	[BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112,
2570	[BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112,
2571};
2572
2573static enum bnxt_link_speed_indices
2574bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk)
2575{
2576	const u16 *speeds;
2577	int idx, len;
2578
2579	switch (sig_mode) {
2580	case BNXT_SIG_MODE_NRZ:
2581		if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2582			speeds = bnxt_nrz_speeds2_masks;
2583			len = ARRAY_SIZE(bnxt_nrz_speeds2_masks);
2584		} else {
2585			speeds = bnxt_nrz_speed_masks;
2586			len = ARRAY_SIZE(bnxt_nrz_speed_masks);
2587		}
2588		break;
2589	case BNXT_SIG_MODE_PAM4:
2590		if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2591			speeds = bnxt_pam4_speeds2_masks;
2592			len = ARRAY_SIZE(bnxt_pam4_speeds2_masks);
2593		} else {
2594			speeds = bnxt_pam4_speed_masks;
2595			len = ARRAY_SIZE(bnxt_pam4_speed_masks);
2596		}
2597		break;
2598	case BNXT_SIG_MODE_PAM4_112:
2599		speeds = bnxt_pam4_112_speeds2_masks;
2600		len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks);
2601		break;
2602	default:
2603		return BNXT_LINK_SPEED_UNKNOWN;
2604	}
2605
2606	for (idx = 0; idx < len; idx++) {
2607		if (speeds[idx] == speed_msk)
2608			return idx;
2609	}
2610
2611	return BNXT_LINK_SPEED_UNKNOWN;
2612}
2613
2614#define BNXT_FW_SPEED_MSK_BITS 16
2615
2616static void
2617__bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2618			  u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2619{
2620	enum ethtool_link_mode_bit_indices link_mode;
2621	enum bnxt_link_speed_indices speed;
2622	u8 bit;
2623
2624	for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) {
2625		speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit);
2626		if (!speed)
2627			continue;
2628
2629		link_mode = bnxt_link_modes[speed][sig_mode][media];
2630		if (!link_mode)
2631			continue;
2632
2633		linkmode_set_bit(link_mode, et_mask);
2634	}
2635}
2636
2637static void
2638bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2639			u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2640{
2641	if (media) {
2642		__bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2643					  et_mask);
2644		return;
2645	}
2646
2647	/* list speeds for all media if unknown */
2648	for (media = 1; media < __BNXT_MEDIA_END; media++)
2649		__bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2650					  et_mask);
2651}
2652
2653static void
2654bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info,
2655				    enum bnxt_media_type media,
2656				    struct ethtool_link_ksettings *lk_ksettings)
2657{
2658	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2659	u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2660	u16 phy_flags = bp->phy_flags;
2661
2662	if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2663		sp_nrz = link_info->support_speeds2;
2664		sp_pam4 = link_info->support_speeds2;
2665		sp_pam4_112 = link_info->support_speeds2;
2666	} else {
2667		sp_nrz = link_info->support_speeds;
2668		sp_pam4 = link_info->support_pam4_speeds;
2669	}
2670	bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2671				lk_ksettings->link_modes.supported);
2672	bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2673				lk_ksettings->link_modes.supported);
2674	bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2675				phy_flags, lk_ksettings->link_modes.supported);
2676}
2677
2678static void
2679bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info,
2680				enum bnxt_media_type media,
2681				struct ethtool_link_ksettings *lk_ksettings)
2682{
2683	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2684	u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2685	u16 phy_flags = bp->phy_flags;
2686
2687	sp_nrz = link_info->advertising;
2688	if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2689		sp_pam4 = link_info->advertising;
2690		sp_pam4_112 = link_info->advertising;
2691	} else {
2692		sp_pam4 = link_info->advertising_pam4;
2693	}
2694	bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2695				lk_ksettings->link_modes.advertising);
2696	bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2697				lk_ksettings->link_modes.advertising);
2698	bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2699				phy_flags, lk_ksettings->link_modes.advertising);
2700}
2701
2702static void
2703bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info,
2704			       enum bnxt_media_type media,
2705			       struct ethtool_link_ksettings *lk_ksettings)
2706{
2707	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2708	u16 phy_flags = bp->phy_flags;
2709
2710	bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media,
2711				BNXT_SIG_MODE_NRZ, phy_flags,
2712				lk_ksettings->link_modes.lp_advertising);
2713	bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media,
2714				BNXT_SIG_MODE_PAM4, phy_flags,
2715				lk_ksettings->link_modes.lp_advertising);
2716}
2717
2718static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds,
2719			      u16 speed_msk, const unsigned long *et_mask,
2720			      enum ethtool_link_mode_bit_indices mode)
2721{
2722	bool mode_desired = linkmode_test_bit(mode, et_mask);
2723
2724	if (!mode)
2725		return;
2726
2727	/* enabled speeds for installed media should override */
2728	if (installed_media && mode_desired) {
2729		*speeds |= speed_msk;
2730		*delta |= speed_msk;
2731		return;
2732	}
2733
2734	/* many to one mapping, only allow one change per fw_speed bit */
2735	if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) {
2736		*speeds ^= speed_msk;
2737		*delta |= speed_msk;
2738	}
2739}
2740
2741static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info,
2742				    const unsigned long *et_mask)
2743{
2744	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2745	u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks;
2746	enum bnxt_media_type media = bnxt_get_media(link_info);
2747	u16 *adv, *adv_pam4, *adv_pam4_112 = NULL;
2748	u32 delta_pam4_112 = 0;
2749	u32 delta_pam4 = 0;
2750	u32 delta_nrz = 0;
2751	int i, m;
2752
2753	adv = &link_info->advertising;
2754	if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
2755		adv_pam4 = &link_info->advertising;
2756		adv_pam4_112 = &link_info->advertising;
2757		sp_msks = bnxt_nrz_speeds2_masks;
2758		sp_pam4_msks = bnxt_pam4_speeds2_masks;
2759		sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks;
2760	} else {
2761		adv_pam4 = &link_info->advertising_pam4;
2762		sp_msks = bnxt_nrz_speed_masks;
2763		sp_pam4_msks = bnxt_pam4_speed_masks;
2764	}
2765	for (i = 1; i < __BNXT_LINK_SPEED_END; i++) {
2766		/* accept any legal media from user */
2767		for (m = 1; m < __BNXT_MEDIA_END; m++) {
2768			bnxt_update_speed(&delta_nrz, m == media,
2769					  adv, sp_msks[i], et_mask,
2770					  bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]);
2771			bnxt_update_speed(&delta_pam4, m == media,
2772					  adv_pam4, sp_pam4_msks[i], et_mask,
2773					  bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]);
2774			if (!adv_pam4_112)
2775				continue;
2776
2777			bnxt_update_speed(&delta_pam4_112, m == media,
2778					  adv_pam4_112, sp_pam4_112_msks[i], et_mask,
2779					  bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]);
2780		}
2781	}
2782}
2783
2784static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
2785				struct ethtool_link_ksettings *lk_ksettings)
2786{
2787	u16 fec_cfg = link_info->fec_cfg;
2788
2789	if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
2790		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2791				 lk_ksettings->link_modes.advertising);
2792		return;
2793	}
2794	if (fec_cfg & BNXT_FEC_ENC_BASE_R)
2795		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2796				 lk_ksettings->link_modes.advertising);
2797	if (fec_cfg & BNXT_FEC_ENC_RS)
2798		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2799				 lk_ksettings->link_modes.advertising);
2800	if (fec_cfg & BNXT_FEC_ENC_LLRS)
2801		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2802				 lk_ksettings->link_modes.advertising);
2803}
2804
2805static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
2806				struct ethtool_link_ksettings *lk_ksettings)
2807{
2808	u16 fec_cfg = link_info->fec_cfg;
2809
2810	if (fec_cfg & BNXT_FEC_NONE) {
2811		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2812				 lk_ksettings->link_modes.supported);
2813		return;
2814	}
2815	if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
2816		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2817				 lk_ksettings->link_modes.supported);
2818	if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
2819		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2820				 lk_ksettings->link_modes.supported);
2821	if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
2822		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2823				 lk_ksettings->link_modes.supported);
2824}
2825
2826u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
2827{
2828	switch (fw_link_speed) {
2829	case BNXT_LINK_SPEED_100MB:
2830		return SPEED_100;
2831	case BNXT_LINK_SPEED_1GB:
2832		return SPEED_1000;
2833	case BNXT_LINK_SPEED_2_5GB:
2834		return SPEED_2500;
2835	case BNXT_LINK_SPEED_10GB:
2836		return SPEED_10000;
2837	case BNXT_LINK_SPEED_20GB:
2838		return SPEED_20000;
2839	case BNXT_LINK_SPEED_25GB:
2840		return SPEED_25000;
2841	case BNXT_LINK_SPEED_40GB:
2842		return SPEED_40000;
2843	case BNXT_LINK_SPEED_50GB:
2844	case BNXT_LINK_SPEED_50GB_PAM4:
2845		return SPEED_50000;
2846	case BNXT_LINK_SPEED_100GB:
2847	case BNXT_LINK_SPEED_100GB_PAM4:
2848	case BNXT_LINK_SPEED_100GB_PAM4_112:
2849		return SPEED_100000;
2850	case BNXT_LINK_SPEED_200GB:
2851	case BNXT_LINK_SPEED_200GB_PAM4:
2852	case BNXT_LINK_SPEED_200GB_PAM4_112:
2853		return SPEED_200000;
2854	case BNXT_LINK_SPEED_400GB:
2855	case BNXT_LINK_SPEED_400GB_PAM4:
2856	case BNXT_LINK_SPEED_400GB_PAM4_112:
2857		return SPEED_400000;
2858	default:
2859		return SPEED_UNKNOWN;
2860	}
2861}
2862
2863static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings,
2864				    struct bnxt_link_info *link_info)
2865{
2866	struct ethtool_link_settings *base = &lk_ksettings->base;
2867
2868	if (link_info->link_state == BNXT_LINK_STATE_UP) {
2869		base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
2870		base->duplex = DUPLEX_HALF;
2871		if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2872			base->duplex = DUPLEX_FULL;
2873		lk_ksettings->lanes = link_info->active_lanes;
2874	} else if (!link_info->autoneg) {
2875		base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
2876		base->duplex = DUPLEX_HALF;
2877		if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
2878			base->duplex = DUPLEX_FULL;
2879	}
2880}
2881
2882static int bnxt_get_link_ksettings(struct net_device *dev,
2883				   struct ethtool_link_ksettings *lk_ksettings)
2884{
2885	struct ethtool_link_settings *base = &lk_ksettings->base;
2886	enum ethtool_link_mode_bit_indices link_mode;
2887	struct bnxt *bp = netdev_priv(dev);
2888	struct bnxt_link_info *link_info;
2889	enum bnxt_media_type media;
2890
2891	ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising);
2892	ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
2893	ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
2894	base->duplex = DUPLEX_UNKNOWN;
2895	base->speed = SPEED_UNKNOWN;
2896	link_info = &bp->link_info;
2897
2898	mutex_lock(&bp->link_lock);
2899	bnxt_get_ethtool_modes(link_info, lk_ksettings);
2900	media = bnxt_get_media(link_info);
2901	bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings);
2902	bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
2903	link_mode = bnxt_get_link_mode(link_info);
2904	if (link_mode != BNXT_LINK_MODE_UNKNOWN)
2905		ethtool_params_from_link_mode(lk_ksettings, link_mode);
2906	else
2907		bnxt_get_default_speeds(lk_ksettings, link_info);
2908
2909	if (link_info->autoneg) {
2910		bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
2911		linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2912				 lk_ksettings->link_modes.advertising);
2913		base->autoneg = AUTONEG_ENABLE;
2914		bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings);
2915		if (link_info->phy_link_status == BNXT_LINK_LINK)
2916			bnxt_get_all_ethtool_lp_speeds(link_info, media,
2917						       lk_ksettings);
2918	} else {
2919		base->autoneg = AUTONEG_DISABLE;
2920	}
2921
2922	base->port = PORT_NONE;
2923	if (media == BNXT_MEDIA_TP) {
2924		base->port = PORT_TP;
2925		linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2926				 lk_ksettings->link_modes.supported);
2927		linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2928				 lk_ksettings->link_modes.advertising);
2929	} else if (media == BNXT_MEDIA_KR) {
2930		linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT,
2931				 lk_ksettings->link_modes.supported);
2932		linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT,
2933				 lk_ksettings->link_modes.advertising);
2934	} else {
2935		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2936				 lk_ksettings->link_modes.supported);
2937		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2938				 lk_ksettings->link_modes.advertising);
2939
2940		if (media == BNXT_MEDIA_CR)
2941			base->port = PORT_DA;
2942		else
2943			base->port = PORT_FIBRE;
2944	}
2945	base->phy_address = link_info->phy_addr;
2946	mutex_unlock(&bp->link_lock);
2947
2948	return 0;
2949}
2950
2951static int
2952bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)
2953{
2954	struct bnxt *bp = netdev_priv(dev);
2955	struct bnxt_link_info *link_info = &bp->link_info;
2956	u16 support_pam4_spds = link_info->support_pam4_speeds;
2957	u16 support_spds2 = link_info->support_speeds2;
2958	u16 support_spds = link_info->support_speeds;
2959	u8 sig_mode = BNXT_SIG_MODE_NRZ;
2960	u32 lanes_needed = 1;
2961	u16 fw_speed = 0;
2962
2963	switch (ethtool_speed) {
2964	case SPEED_100:
2965		if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
2966			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
2967		break;
2968	case SPEED_1000:
2969		if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) ||
2970		    (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB))
2971			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
2972		break;
2973	case SPEED_2500:
2974		if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
2975			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
2976		break;
2977	case SPEED_10000:
2978		if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) ||
2979		    (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB))
2980			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
2981		break;
2982	case SPEED_20000:
2983		if (support_spds & BNXT_LINK_SPEED_MSK_20GB) {
2984			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
2985			lanes_needed = 2;
2986		}
2987		break;
2988	case SPEED_25000:
2989		if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) ||
2990		    (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB))
2991			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
2992		break;
2993	case SPEED_40000:
2994		if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) ||
2995		    (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) {
2996			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
2997			lanes_needed = 4;
2998		}
2999		break;
3000	case SPEED_50000:
3001		if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) ||
3002		     (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) &&
3003		    lanes != 1) {
3004			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
3005			lanes_needed = 2;
3006		} else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
3007			fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
3008			sig_mode = BNXT_SIG_MODE_PAM4;
3009		} else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) {
3010			fw_speed = BNXT_LINK_SPEED_50GB_PAM4;
3011			sig_mode = BNXT_SIG_MODE_PAM4;
3012		}
3013		break;
3014	case SPEED_100000:
3015		if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) ||
3016		     (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) &&
3017		    lanes != 2 && lanes != 1) {
3018			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
3019			lanes_needed = 4;
3020		} else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
3021			fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
3022			sig_mode = BNXT_SIG_MODE_PAM4;
3023			lanes_needed = 2;
3024		} else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) &&
3025			   lanes != 1) {
3026			fw_speed = BNXT_LINK_SPEED_100GB_PAM4;
3027			sig_mode = BNXT_SIG_MODE_PAM4;
3028			lanes_needed = 2;
3029		} else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) {
3030			fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112;
3031			sig_mode = BNXT_SIG_MODE_PAM4_112;
3032		}
3033		break;
3034	case SPEED_200000:
3035		if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
3036			fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
3037			sig_mode = BNXT_SIG_MODE_PAM4;
3038			lanes_needed = 4;
3039		} else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) &&
3040			   lanes != 2) {
3041			fw_speed = BNXT_LINK_SPEED_200GB_PAM4;
3042			sig_mode = BNXT_SIG_MODE_PAM4;
3043			lanes_needed = 4;
3044		} else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) {
3045			fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112;
3046			sig_mode = BNXT_SIG_MODE_PAM4_112;
3047			lanes_needed = 2;
3048		}
3049		break;
3050	case SPEED_400000:
3051		if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) &&
3052		    lanes != 4) {
3053			fw_speed = BNXT_LINK_SPEED_400GB_PAM4;
3054			sig_mode = BNXT_SIG_MODE_PAM4;
3055			lanes_needed = 8;
3056		} else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) {
3057			fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112;
3058			sig_mode = BNXT_SIG_MODE_PAM4_112;
3059			lanes_needed = 4;
3060		}
3061		break;
3062	}
3063
3064	if (!fw_speed) {
3065		netdev_err(dev, "unsupported speed!\n");
3066		return -EINVAL;
3067	}
3068
3069	if (lanes && lanes != lanes_needed) {
3070		netdev_err(dev, "unsupported number of lanes for speed\n");
3071		return -EINVAL;
3072	}
3073
3074	if (link_info->req_link_speed == fw_speed &&
3075	    link_info->req_signal_mode == sig_mode &&
3076	    link_info->autoneg == 0)
3077		return -EALREADY;
3078
3079	link_info->req_link_speed = fw_speed;
3080	link_info->req_signal_mode = sig_mode;
3081	link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
3082	link_info->autoneg = 0;
3083	link_info->advertising = 0;
3084	link_info->advertising_pam4 = 0;
3085
3086	return 0;
3087}
3088
3089u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode)
3090{
3091	u16 fw_speed_mask = 0;
3092
3093	if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) ||
3094	    linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode))
3095		fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
3096
3097	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) ||
3098	    linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode))
3099		fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
3100
3101	if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode))
3102		fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
3103
3104	if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode))
3105		fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
3106
3107	return fw_speed_mask;
3108}
3109
3110static int bnxt_set_link_ksettings(struct net_device *dev,
3111			   const struct ethtool_link_ksettings *lk_ksettings)
3112{
3113	struct bnxt *bp = netdev_priv(dev);
3114	struct bnxt_link_info *link_info = &bp->link_info;
3115	const struct ethtool_link_settings *base = &lk_ksettings->base;
3116	bool set_pause = false;
3117	u32 speed, lanes = 0;
3118	int rc = 0;
3119
3120	if (!BNXT_PHY_CFG_ABLE(bp))
3121		return -EOPNOTSUPP;
3122
3123	mutex_lock(&bp->link_lock);
3124	if (base->autoneg == AUTONEG_ENABLE) {
3125		bnxt_set_ethtool_speeds(link_info,
3126					lk_ksettings->link_modes.advertising);
3127		link_info->autoneg |= BNXT_AUTONEG_SPEED;
3128		if (!link_info->advertising && !link_info->advertising_pam4) {
3129			link_info->advertising = link_info->support_auto_speeds;
3130			link_info->advertising_pam4 =
3131				link_info->support_pam4_auto_speeds;
3132		}
3133		/* any change to autoneg will cause link change, therefore the
3134		 * driver should put back the original pause setting in autoneg
3135		 */
3136		if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
3137			set_pause = true;
3138	} else {
3139		u8 phy_type = link_info->phy_type;
3140
3141		if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET  ||
3142		    phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
3143		    link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
3144			netdev_err(dev, "10GBase-T devices must autoneg\n");
3145			rc = -EINVAL;
3146			goto set_setting_exit;
3147		}
3148		if (base->duplex == DUPLEX_HALF) {
3149			netdev_err(dev, "HALF DUPLEX is not supported!\n");
3150			rc = -EINVAL;
3151			goto set_setting_exit;
3152		}
3153		speed = base->speed;
3154		lanes = lk_ksettings->lanes;
3155		rc = bnxt_force_link_speed(dev, speed, lanes);
3156		if (rc) {
3157			if (rc == -EALREADY)
3158				rc = 0;
3159			goto set_setting_exit;
3160		}
3161	}
3162
3163	if (netif_running(dev))
3164		rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
3165
3166set_setting_exit:
3167	mutex_unlock(&bp->link_lock);
3168	return rc;
3169}
3170
3171static int bnxt_get_fecparam(struct net_device *dev,
3172			     struct ethtool_fecparam *fec)
3173{
3174	struct bnxt *bp = netdev_priv(dev);
3175	struct bnxt_link_info *link_info;
3176	u8 active_fec;
3177	u16 fec_cfg;
3178
3179	link_info = &bp->link_info;
3180	fec_cfg = link_info->fec_cfg;
3181	active_fec = link_info->active_fec_sig_mode &
3182		     PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
3183	if (fec_cfg & BNXT_FEC_NONE) {
3184		fec->fec = ETHTOOL_FEC_NONE;
3185		fec->active_fec = ETHTOOL_FEC_NONE;
3186		return 0;
3187	}
3188	if (fec_cfg & BNXT_FEC_AUTONEG)
3189		fec->fec |= ETHTOOL_FEC_AUTO;
3190	if (fec_cfg & BNXT_FEC_ENC_BASE_R)
3191		fec->fec |= ETHTOOL_FEC_BASER;
3192	if (fec_cfg & BNXT_FEC_ENC_RS)
3193		fec->fec |= ETHTOOL_FEC_RS;
3194	if (fec_cfg & BNXT_FEC_ENC_LLRS)
3195		fec->fec |= ETHTOOL_FEC_LLRS;
3196
3197	switch (active_fec) {
3198	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
3199		fec->active_fec |= ETHTOOL_FEC_BASER;
3200		break;
3201	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
3202	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
3203	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
3204		fec->active_fec |= ETHTOOL_FEC_RS;
3205		break;
3206	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
3207	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
3208		fec->active_fec |= ETHTOOL_FEC_LLRS;
3209		break;
3210	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
3211		fec->active_fec |= ETHTOOL_FEC_OFF;
3212		break;
3213	}
3214	return 0;
3215}
3216
3217static void bnxt_get_fec_stats(struct net_device *dev,
3218			       struct ethtool_fec_stats *fec_stats,
3219			       struct ethtool_fec_hist *hist)
3220{
3221	struct bnxt *bp = netdev_priv(dev);
3222	u64 *rx;
3223
3224	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
3225		return;
3226
3227	rx = bp->rx_port_stats_ext.sw_stats;
3228	fec_stats->corrected_bits.total =
3229		*(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits));
3230
3231	if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY)
3232		return;
3233
3234	fec_stats->corrected_blocks.total =
3235		*(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks));
3236	fec_stats->uncorrectable_blocks.total =
3237		*(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks));
3238}
3239
3240static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
3241					 u32 fec)
3242{
3243	u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
3244
3245	if (fec & ETHTOOL_FEC_BASER)
3246		fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
3247	else if (fec & ETHTOOL_FEC_RS)
3248		fw_fec |= BNXT_FEC_RS_ON(link_info);
3249	else if (fec & ETHTOOL_FEC_LLRS)
3250		fw_fec |= BNXT_FEC_LLRS_ON;
3251	return fw_fec;
3252}
3253
3254static int bnxt_set_fecparam(struct net_device *dev,
3255			     struct ethtool_fecparam *fecparam)
3256{
3257	struct hwrm_port_phy_cfg_input *req;
3258	struct bnxt *bp = netdev_priv(dev);
3259	struct bnxt_link_info *link_info;
3260	u32 new_cfg, fec = fecparam->fec;
3261	u16 fec_cfg;
3262	int rc;
3263
3264	link_info = &bp->link_info;
3265	fec_cfg = link_info->fec_cfg;
3266	if (fec_cfg & BNXT_FEC_NONE)
3267		return -EOPNOTSUPP;
3268
3269	if (fec & ETHTOOL_FEC_OFF) {
3270		new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
3271			  BNXT_FEC_ALL_OFF(link_info);
3272		goto apply_fec;
3273	}
3274	if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
3275	    ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
3276	    ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
3277	    ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
3278		return -EINVAL;
3279
3280	if (fec & ETHTOOL_FEC_AUTO) {
3281		if (!link_info->autoneg)
3282			return -EINVAL;
3283		new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
3284	} else {
3285		new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
3286	}
3287
3288apply_fec:
3289	rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
3290	if (rc)
3291		return rc;
3292	req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3293	rc = hwrm_req_send(bp, req);
3294	/* update current settings */
3295	if (!rc) {
3296		mutex_lock(&bp->link_lock);
3297		bnxt_update_link(bp, false);
3298		mutex_unlock(&bp->link_lock);
3299	}
3300	return rc;
3301}
3302
3303static void bnxt_get_pauseparam(struct net_device *dev,
3304				struct ethtool_pauseparam *epause)
3305{
3306	struct bnxt *bp = netdev_priv(dev);
3307	struct bnxt_link_info *link_info = &bp->link_info;
3308
3309	if (BNXT_VF(bp))
3310		return;
3311	epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
3312	epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
3313	epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
3314}
3315
3316static void bnxt_get_pause_stats(struct net_device *dev,
3317				 struct ethtool_pause_stats *epstat)
3318{
3319	struct bnxt *bp = netdev_priv(dev);
3320	u64 *rx, *tx;
3321
3322	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3323		return;
3324
3325	rx = bp->port_stats.sw_stats;
3326	tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3327
3328	epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
3329	epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
3330}
3331
3332static int bnxt_set_pauseparam(struct net_device *dev,
3333			       struct ethtool_pauseparam *epause)
3334{
3335	int rc = 0;
3336	struct bnxt *bp = netdev_priv(dev);
3337	struct bnxt_link_info *link_info = &bp->link_info;
3338
3339	if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
3340		return -EOPNOTSUPP;
3341
3342	mutex_lock(&bp->link_lock);
3343	if (epause->autoneg) {
3344		if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
3345			rc = -EINVAL;
3346			goto pause_exit;
3347		}
3348
3349		link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
3350		link_info->req_flow_ctrl = 0;
3351	} else {
3352		/* when transition from auto pause to force pause,
3353		 * force a link change
3354		 */
3355		if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
3356			link_info->force_link_chng = true;
3357		link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
3358		link_info->req_flow_ctrl = 0;
3359	}
3360	if (epause->rx_pause)
3361		link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
3362
3363	if (epause->tx_pause)
3364		link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
3365
3366	if (netif_running(dev))
3367		rc = bnxt_hwrm_set_pause(bp);
3368
3369pause_exit:
3370	mutex_unlock(&bp->link_lock);
3371	return rc;
3372}
3373
3374static u32 bnxt_get_link(struct net_device *dev)
3375{
3376	struct bnxt *bp = netdev_priv(dev);
3377
3378	/* TODO: handle MF, VF, driver close case */
3379	return BNXT_LINK_IS_UP(bp);
3380}
3381
3382int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
3383			       struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
3384{
3385	struct hwrm_nvm_get_dev_info_output *resp;
3386	struct hwrm_nvm_get_dev_info_input *req;
3387	int rc;
3388
3389	if (BNXT_VF(bp))
3390		return -EOPNOTSUPP;
3391
3392	rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO);
3393	if (rc)
3394		return rc;
3395
3396	resp = hwrm_req_hold(bp, req);
3397	rc = hwrm_req_send(bp, req);
3398	if (!rc)
3399		memcpy(nvm_dev_info, resp, sizeof(*resp));
3400	hwrm_req_drop(bp, req);
3401	return rc;
3402}
3403
3404static void bnxt_print_admin_err(struct bnxt *bp)
3405{
3406	netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
3407}
3408
3409int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
3410			 u16 ext, u16 *index, u32 *item_length,
3411			 u32 *data_length);
3412
3413int bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
3414		     u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
3415		     u32 dir_item_len, const u8 *data,
3416		     size_t data_len)
3417{
3418	struct bnxt *bp = netdev_priv(dev);
3419	struct hwrm_nvm_write_input *req;
3420	int rc;
3421
3422	rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE);
3423	if (rc)
3424		return rc;
3425
3426	if (data_len && data) {
3427		dma_addr_t dma_handle;
3428		u8 *kmem;
3429
3430		kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle);
3431		if (!kmem) {
3432			hwrm_req_drop(bp, req);
3433			return -ENOMEM;
3434		}
3435
3436		req->dir_data_length = cpu_to_le32(data_len);
3437
3438		memcpy(kmem, data, data_len);
3439		req->host_src_addr = cpu_to_le64(dma_handle);
3440	}
3441
3442	hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
3443	req->dir_type = cpu_to_le16(dir_type);
3444	req->dir_ordinal = cpu_to_le16(dir_ordinal);
3445	req->dir_ext = cpu_to_le16(dir_ext);
3446	req->dir_attr = cpu_to_le16(dir_attr);
3447	req->dir_item_length = cpu_to_le32(dir_item_len);
3448	rc = hwrm_req_send(bp, req);
3449
3450	if (rc == -EACCES)
3451		bnxt_print_admin_err(bp);
3452	return rc;
3453}
3454
3455int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
3456			     u8 self_reset, u8 flags)
3457{
3458	struct bnxt *bp = netdev_priv(dev);
3459	struct hwrm_fw_reset_input *req;
3460	int rc;
3461
3462	if (!bnxt_hwrm_reset_permitted(bp)) {
3463		netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver");
3464		return -EPERM;
3465	}
3466
3467	rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
3468	if (rc)
3469		return rc;
3470
3471	req->embedded_proc_type = proc_type;
3472	req->selfrst_status = self_reset;
3473	req->flags = flags;
3474
3475	if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
3476		rc = hwrm_req_send_silent(bp, req);
3477	} else {
3478		rc = hwrm_req_send(bp, req);
3479		if (rc == -EACCES)
3480			bnxt_print_admin_err(bp);
3481	}
3482	return rc;
3483}
3484
3485static int bnxt_firmware_reset(struct net_device *dev,
3486			       enum bnxt_nvm_directory_type dir_type)
3487{
3488	u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
3489	u8 proc_type, flags = 0;
3490
3491	/* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
3492	/*       (e.g. when firmware isn't already running) */
3493	switch (dir_type) {
3494	case BNX_DIR_TYPE_CHIMP_PATCH:
3495	case BNX_DIR_TYPE_BOOTCODE:
3496	case BNX_DIR_TYPE_BOOTCODE_2:
3497		proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
3498		/* Self-reset ChiMP upon next PCIe reset: */
3499		self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3500		break;
3501	case BNX_DIR_TYPE_APE_FW:
3502	case BNX_DIR_TYPE_APE_PATCH:
3503		proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
3504		/* Self-reset APE upon next PCIe reset: */
3505		self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3506		break;
3507	case BNX_DIR_TYPE_KONG_FW:
3508	case BNX_DIR_TYPE_KONG_PATCH:
3509		proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
3510		break;
3511	case BNX_DIR_TYPE_BONO_FW:
3512	case BNX_DIR_TYPE_BONO_PATCH:
3513		proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
3514		break;
3515	default:
3516		return -EINVAL;
3517	}
3518
3519	return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
3520}
3521
3522static int bnxt_firmware_reset_chip(struct net_device *dev)
3523{
3524	struct bnxt *bp = netdev_priv(dev);
3525	u8 flags = 0;
3526
3527	if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
3528		flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
3529
3530	return bnxt_hwrm_firmware_reset(dev,
3531					FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
3532					FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
3533					flags);
3534}
3535
3536static int bnxt_firmware_reset_ap(struct net_device *dev)
3537{
3538	return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
3539					FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
3540					0);
3541}
3542
3543static int bnxt_flash_firmware(struct net_device *dev,
3544			       u16 dir_type,
3545			       const u8 *fw_data,
3546			       size_t fw_size)
3547{
3548	int	rc = 0;
3549	u16	code_type;
3550	u32	stored_crc;
3551	u32	calculated_crc;
3552	struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
3553
3554	switch (dir_type) {
3555	case BNX_DIR_TYPE_BOOTCODE:
3556	case BNX_DIR_TYPE_BOOTCODE_2:
3557		code_type = CODE_BOOT;
3558		break;
3559	case BNX_DIR_TYPE_CHIMP_PATCH:
3560		code_type = CODE_CHIMP_PATCH;
3561		break;
3562	case BNX_DIR_TYPE_APE_FW:
3563		code_type = CODE_MCTP_PASSTHRU;
3564		break;
3565	case BNX_DIR_TYPE_APE_PATCH:
3566		code_type = CODE_APE_PATCH;
3567		break;
3568	case BNX_DIR_TYPE_KONG_FW:
3569		code_type = CODE_KONG_FW;
3570		break;
3571	case BNX_DIR_TYPE_KONG_PATCH:
3572		code_type = CODE_KONG_PATCH;
3573		break;
3574	case BNX_DIR_TYPE_BONO_FW:
3575		code_type = CODE_BONO_FW;
3576		break;
3577	case BNX_DIR_TYPE_BONO_PATCH:
3578		code_type = CODE_BONO_PATCH;
3579		break;
3580	default:
3581		netdev_err(dev, "Unsupported directory entry type: %u\n",
3582			   dir_type);
3583		return -EINVAL;
3584	}
3585	if (fw_size < sizeof(struct bnxt_fw_header)) {
3586		netdev_err(dev, "Invalid firmware file size: %u\n",
3587			   (unsigned int)fw_size);
3588		return -EINVAL;
3589	}
3590	if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
3591		netdev_err(dev, "Invalid firmware signature: %08X\n",
3592			   le32_to_cpu(header->signature));
3593		return -EINVAL;
3594	}
3595	if (header->code_type != code_type) {
3596		netdev_err(dev, "Expected firmware type: %d, read: %d\n",
3597			   code_type, header->code_type);
3598		return -EINVAL;
3599	}
3600	if (header->device != DEVICE_CUMULUS_FAMILY) {
3601		netdev_err(dev, "Expected firmware device family %d, read: %d\n",
3602			   DEVICE_CUMULUS_FAMILY, header->device);
3603		return -EINVAL;
3604	}
3605	/* Confirm the CRC32 checksum of the file: */
3606	stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3607					     sizeof(stored_crc)));
3608	calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3609	if (calculated_crc != stored_crc) {
3610		netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
3611			   (unsigned long)stored_crc,
3612			   (unsigned long)calculated_crc);
3613		return -EINVAL;
3614	}
3615	rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3616			      0, 0, 0, fw_data, fw_size);
3617	if (rc == 0)	/* Firmware update successful */
3618		rc = bnxt_firmware_reset(dev, dir_type);
3619
3620	return rc;
3621}
3622
3623static int bnxt_flash_microcode(struct net_device *dev,
3624				u16 dir_type,
3625				const u8 *fw_data,
3626				size_t fw_size)
3627{
3628	struct bnxt_ucode_trailer *trailer;
3629	u32 calculated_crc;
3630	u32 stored_crc;
3631	int rc = 0;
3632
3633	if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
3634		netdev_err(dev, "Invalid microcode file size: %u\n",
3635			   (unsigned int)fw_size);
3636		return -EINVAL;
3637	}
3638	trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
3639						sizeof(*trailer)));
3640	if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
3641		netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
3642			   le32_to_cpu(trailer->sig));
3643		return -EINVAL;
3644	}
3645	if (le16_to_cpu(trailer->dir_type) != dir_type) {
3646		netdev_err(dev, "Expected microcode type: %d, read: %d\n",
3647			   dir_type, le16_to_cpu(trailer->dir_type));
3648		return -EINVAL;
3649	}
3650	if (le16_to_cpu(trailer->trailer_length) <
3651		sizeof(struct bnxt_ucode_trailer)) {
3652		netdev_err(dev, "Invalid microcode trailer length: %d\n",
3653			   le16_to_cpu(trailer->trailer_length));
3654		return -EINVAL;
3655	}
3656
3657	/* Confirm the CRC32 checksum of the file: */
3658	stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3659					     sizeof(stored_crc)));
3660	calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3661	if (calculated_crc != stored_crc) {
3662		netdev_err(dev,
3663			   "CRC32 (%08lX) does not match calculated: %08lX\n",
3664			   (unsigned long)stored_crc,
3665			   (unsigned long)calculated_crc);
3666		return -EINVAL;
3667	}
3668	rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3669			      0, 0, 0, fw_data, fw_size);
3670
3671	return rc;
3672}
3673
3674static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
3675{
3676	switch (dir_type) {
3677	case BNX_DIR_TYPE_CHIMP_PATCH:
3678	case BNX_DIR_TYPE_BOOTCODE:
3679	case BNX_DIR_TYPE_BOOTCODE_2:
3680	case BNX_DIR_TYPE_APE_FW:
3681	case BNX_DIR_TYPE_APE_PATCH:
3682	case BNX_DIR_TYPE_KONG_FW:
3683	case BNX_DIR_TYPE_KONG_PATCH:
3684	case BNX_DIR_TYPE_BONO_FW:
3685	case BNX_DIR_TYPE_BONO_PATCH:
3686		return true;
3687	}
3688
3689	return false;
3690}
3691
3692static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
3693{
3694	switch (dir_type) {
3695	case BNX_DIR_TYPE_AVS:
3696	case BNX_DIR_TYPE_EXP_ROM_MBA:
3697	case BNX_DIR_TYPE_PCIE:
3698	case BNX_DIR_TYPE_TSCF_UCODE:
3699	case BNX_DIR_TYPE_EXT_PHY:
3700	case BNX_DIR_TYPE_CCM:
3701	case BNX_DIR_TYPE_ISCSI_BOOT:
3702	case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3703	case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3704		return true;
3705	}
3706
3707	return false;
3708}
3709
3710static bool bnxt_dir_type_is_executable(u16 dir_type)
3711{
3712	return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3713		bnxt_dir_type_is_other_exec_format(dir_type);
3714}
3715
3716static int bnxt_flash_firmware_from_file(struct net_device *dev,
3717					 u16 dir_type,
3718					 const char *filename)
3719{
3720	const struct firmware  *fw;
3721	int			rc;
3722
3723	rc = request_firmware(&fw, filename, &dev->dev);
3724	if (rc != 0) {
3725		netdev_err(dev, "Error %d requesting firmware file: %s\n",
3726			   rc, filename);
3727		return rc;
3728	}
3729	if (bnxt_dir_type_is_ape_bin_format(dir_type))
3730		rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
3731	else if (bnxt_dir_type_is_other_exec_format(dir_type))
3732		rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
3733	else
3734		rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3735				      0, 0, 0, fw->data, fw->size);
3736	release_firmware(fw);
3737	return rc;
3738}
3739
3740#define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM"
3741#define MSG_INVALID_PKG "PKG install error : Invalid package"
3742#define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error"
3743#define MSG_INVALID_DEV "PKG install error : Invalid device"
3744#define MSG_INTERNAL_ERR "PKG install error : Internal error"
3745#define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram"
3746#define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram"
3747#define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error"
3748#define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected"
3749#define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure"
3750
3751static int nvm_update_err_to_stderr(struct net_device *dev, u8 result,
3752				    struct netlink_ext_ack *extack)
3753{
3754	switch (result) {
3755	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER:
3756	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER:
3757	case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR:
3758	case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR:
3759	case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND:
3760	case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED:
3761		BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR);
3762		return -EINVAL;
3763	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE:
3764	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER:
3765	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE:
3766	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM:
3767	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH:
3768	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST:
3769	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER:
3770	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM:
3771	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM:
3772	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH:
3773	case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE:
3774	case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM:
3775	case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM:
3776		BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG);
3777		return -ENOPKG;
3778	case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR:
3779		BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR);
3780		return -EPERM;
3781	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV:
3782	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID:
3783	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR:
3784	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID:
3785	case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM:
3786		BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV);
3787		return -EOPNOTSUPP;
3788	default:
3789		BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR);
3790		return -EIO;
3791	}
3792}
3793
3794#define BNXT_PKG_DMA_SIZE	0x40000
3795#define BNXT_NVM_MORE_FLAG	(cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE))
3796#define BNXT_NVM_LAST_FLAG	(cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST))
3797
3798static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size,
3799				    struct netlink_ext_ack *extack)
3800{
3801	u32 item_len;
3802	int rc;
3803
3804	rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
3805				  BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL,
3806				  &item_len, NULL);
3807	if (rc) {
3808		BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
3809		return rc;
3810	}
3811
3812	if (fw_size > item_len) {
3813		rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE,
3814				      BNX_DIR_ORDINAL_FIRST, 0, 1,
3815				      round_up(fw_size, 4096), NULL, 0);
3816		if (rc) {
3817			BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR);
3818			return rc;
3819		}
3820	}
3821	return 0;
3822}
3823
3824int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw,
3825				   u32 install_type, struct netlink_ext_ack *extack)
3826{
3827	struct hwrm_nvm_install_update_input *install;
3828	struct hwrm_nvm_install_update_output *resp;
3829	struct hwrm_nvm_modify_input *modify;
3830	struct bnxt *bp = netdev_priv(dev);
3831	bool defrag_attempted = false;
3832	dma_addr_t dma_handle;
3833	u8 *kmem = NULL;
3834	u32 modify_len;
3835	u32 item_len;
3836	u8 cmd_err;
3837	u16 index;
3838	int rc;
3839
3840	/* resize before flashing larger image than available space */
3841	rc = bnxt_resize_update_entry(dev, fw->size, extack);
3842	if (rc)
3843		return rc;
3844
3845	bnxt_hwrm_fw_set_time(bp);
3846
3847	rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY);
3848	if (rc)
3849		return rc;
3850
3851	/* Try allocating a large DMA buffer first.  Older fw will
3852	 * cause excessive NVRAM erases when using small blocks.
3853	 */
3854	modify_len = roundup_pow_of_two(fw->size);
3855	modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE);
3856	while (1) {
3857		kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle);
3858		if (!kmem && modify_len > PAGE_SIZE)
3859			modify_len /= 2;
3860		else
3861			break;
3862	}
3863	if (!kmem) {
3864		hwrm_req_drop(bp, modify);
3865		return -ENOMEM;
3866	}
3867
3868	rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE);
3869	if (rc) {
3870		hwrm_req_drop(bp, modify);
3871		return rc;
3872	}
3873
3874	hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout);
3875	hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout);
3876
3877	hwrm_req_hold(bp, modify);
3878	modify->host_src_addr = cpu_to_le64(dma_handle);
3879
3880	resp = hwrm_req_hold(bp, install);
3881	if ((install_type & 0xffff) == 0)
3882		install_type >>= 16;
3883	install->install_type = cpu_to_le32(install_type);
3884
3885	do {
3886		u32 copied = 0, len = modify_len;
3887
3888		rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
3889					  BNX_DIR_ORDINAL_FIRST,
3890					  BNX_DIR_EXT_NONE,
3891					  &index, &item_len, NULL);
3892		if (rc) {
3893			BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
3894			break;
3895		}
3896		if (fw->size > item_len) {
3897			BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR);
3898			rc = -EFBIG;
3899			break;
3900		}
3901
3902		modify->dir_idx = cpu_to_le16(index);
3903
3904		if (fw->size > modify_len)
3905			modify->flags = BNXT_NVM_MORE_FLAG;
3906		while (copied < fw->size) {
3907			u32 balance = fw->size - copied;
3908
3909			if (balance <= modify_len) {
3910				len = balance;
3911				if (copied)
3912					modify->flags |= BNXT_NVM_LAST_FLAG;
3913			}
3914			memcpy(kmem, fw->data + copied, len);
3915			modify->len = cpu_to_le32(len);
3916			modify->offset = cpu_to_le32(copied);
3917			rc = hwrm_req_send(bp, modify);
3918			if (rc)
3919				goto pkg_abort;
3920			copied += len;
3921		}
3922
3923		rc = hwrm_req_send_silent(bp, install);
3924		if (!rc)
3925			break;
3926
3927		if (defrag_attempted) {
3928			/* We have tried to defragment already in the previous
3929			 * iteration. Return with the result for INSTALL_UPDATE
3930			 */
3931			break;
3932		}
3933
3934		cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
3935
3936		switch (cmd_err) {
3937		case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK:
3938			BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR);
3939			rc = -EALREADY;
3940			break;
3941		case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR:
3942			install->flags =
3943				cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
3944
3945			rc = hwrm_req_send_silent(bp, install);
3946			if (!rc)
3947				break;
3948
3949			cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
3950
3951			if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) {
3952				/* FW has cleared NVM area, driver will create
3953				 * UPDATE directory and try the flash again
3954				 */
3955				defrag_attempted = true;
3956				install->flags = 0;
3957				rc = bnxt_flash_nvram(bp->dev,
3958						      BNX_DIR_TYPE_UPDATE,
3959						      BNX_DIR_ORDINAL_FIRST,
3960						      0, 0, item_len, NULL, 0);
3961				if (!rc)
3962					break;
3963			}
3964			fallthrough;
3965		default:
3966			BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR);
3967		}
3968	} while (defrag_attempted && !rc);
3969
3970pkg_abort:
3971	hwrm_req_drop(bp, modify);
3972	hwrm_req_drop(bp, install);
3973
3974	if (resp->result) {
3975		netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
3976			   (s8)resp->result, (int)resp->problem_item);
3977		rc = nvm_update_err_to_stderr(dev, resp->result, extack);
3978	}
3979	if (rc == -EACCES)
3980		bnxt_print_admin_err(bp);
3981	return rc;
3982}
3983
3984static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
3985					u32 install_type, struct netlink_ext_ack *extack)
3986{
3987	const struct firmware *fw;
3988	int rc;
3989
3990	rc = request_firmware(&fw, filename, &dev->dev);
3991	if (rc != 0) {
3992		netdev_err(dev, "PKG error %d requesting file: %s\n",
3993			   rc, filename);
3994		return rc;
3995	}
3996
3997	rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack);
3998
3999	release_firmware(fw);
4000
4001	return rc;
4002}
4003
4004static int bnxt_flash_device(struct net_device *dev,
4005			     struct ethtool_flash *flash)
4006{
4007	if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
4008		netdev_err(dev, "flashdev not supported from a virtual function\n");
4009		return -EINVAL;
4010	}
4011
4012	if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
4013	    flash->region > 0xffff)
4014		return bnxt_flash_package_from_file(dev, flash->data,
4015						    flash->region, NULL);
4016
4017	return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
4018}
4019
4020static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
4021{
4022	struct hwrm_nvm_get_dir_info_output *output;
4023	struct hwrm_nvm_get_dir_info_input *req;
4024	struct bnxt *bp = netdev_priv(dev);
4025	int rc;
4026
4027	rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO);
4028	if (rc)
4029		return rc;
4030
4031	output = hwrm_req_hold(bp, req);
4032	rc = hwrm_req_send(bp, req);
4033	if (!rc) {
4034		*entries = le32_to_cpu(output->entries);
4035		*length = le32_to_cpu(output->entry_length);
4036	}
4037	hwrm_req_drop(bp, req);
4038	return rc;
4039}
4040
4041static int bnxt_get_eeprom_len(struct net_device *dev)
4042{
4043	struct bnxt *bp = netdev_priv(dev);
4044
4045	if (BNXT_VF(bp))
4046		return 0;
4047
4048	/* The -1 return value allows the entire 32-bit range of offsets to be
4049	 * passed via the ethtool command-line utility.
4050	 */
4051	return -1;
4052}
4053
4054static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
4055{
4056	struct bnxt *bp = netdev_priv(dev);
4057	int rc;
4058	u32 dir_entries;
4059	u32 entry_length;
4060	u8 *buf;
4061	size_t buflen;
4062	dma_addr_t dma_handle;
4063	struct hwrm_nvm_get_dir_entries_input *req;
4064
4065	rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
4066	if (rc != 0)
4067		return rc;
4068
4069	if (!dir_entries || !entry_length)
4070		return -EIO;
4071
4072	/* Insert 2 bytes of directory info (count and size of entries) */
4073	if (len < 2)
4074		return -EINVAL;
4075
4076	*data++ = dir_entries;
4077	*data++ = entry_length;
4078	len -= 2;
4079	memset(data, 0xff, len);
4080
4081	rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES);
4082	if (rc)
4083		return rc;
4084
4085	buflen = mul_u32_u32(dir_entries, entry_length);
4086	buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle);
4087	if (!buf) {
4088		hwrm_req_drop(bp, req);
4089		return -ENOMEM;
4090	}
4091	req->host_dest_addr = cpu_to_le64(dma_handle);
4092
4093	hwrm_req_hold(bp, req); /* hold the slice */
4094	rc = hwrm_req_send(bp, req);
4095	if (rc == 0)
4096		memcpy(data, buf, len > buflen ? buflen : len);
4097	hwrm_req_drop(bp, req);
4098	return rc;
4099}
4100
4101int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
4102			u32 length, u8 *data)
4103{
4104	struct bnxt *bp = netdev_priv(dev);
4105	int rc;
4106	u8 *buf;
4107	dma_addr_t dma_handle;
4108	struct hwrm_nvm_read_input *req;
4109
4110	if (!length)
4111		return -EINVAL;
4112
4113	rc = hwrm_req_init(bp, req, HWRM_NVM_READ);
4114	if (rc)
4115		return rc;
4116
4117	buf = hwrm_req_dma_slice(bp, req, length, &dma_handle);
4118	if (!buf) {
4119		hwrm_req_drop(bp, req);
4120		return -ENOMEM;
4121	}
4122
4123	req->host_dest_addr = cpu_to_le64(dma_handle);
4124	req->dir_idx = cpu_to_le16(index);
4125	req->offset = cpu_to_le32(offset);
4126	req->len = cpu_to_le32(length);
4127
4128	hwrm_req_hold(bp, req); /* hold the slice */
4129	rc = hwrm_req_send(bp, req);
4130	if (rc == 0)
4131		memcpy(data, buf, length);
4132	hwrm_req_drop(bp, req);
4133	return rc;
4134}
4135
4136int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
4137			 u16 ext, u16 *index, u32 *item_length,
4138			 u32 *data_length)
4139{
4140	struct hwrm_nvm_find_dir_entry_output *output;
4141	struct hwrm_nvm_find_dir_entry_input *req;
4142	struct bnxt *bp = netdev_priv(dev);
4143	int rc;
4144
4145	rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY);
4146	if (rc)
4147		return rc;
4148
4149	req->enables = 0;
4150	req->dir_idx = 0;
4151	req->dir_type = cpu_to_le16(type);
4152	req->dir_ordinal = cpu_to_le16(ordinal);
4153	req->dir_ext = cpu_to_le16(ext);
4154	req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
4155	output = hwrm_req_hold(bp, req);
4156	rc = hwrm_req_send_silent(bp, req);
4157	if (rc == 0) {
4158		if (index)
4159			*index = le16_to_cpu(output->dir_idx);
4160		if (item_length)
4161			*item_length = le32_to_cpu(output->dir_item_length);
4162		if (data_length)
4163			*data_length = le32_to_cpu(output->dir_data_length);
4164	}
4165	hwrm_req_drop(bp, req);
4166	return rc;
4167}
4168
4169static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
4170{
4171	char	*retval = NULL;
4172	char	*p;
4173	char	*value;
4174	int	field = 0;
4175
4176	if (datalen < 1)
4177		return NULL;
4178	/* null-terminate the log data (removing last '\n'): */
4179	data[datalen - 1] = 0;
4180	for (p = data; *p != 0; p++) {
4181		field = 0;
4182		retval = NULL;
4183		while (*p != 0 && *p != '\n') {
4184			value = p;
4185			while (*p != 0 && *p != '\t' && *p != '\n')
4186				p++;
4187			if (field == desired_field)
4188				retval = value;
4189			if (*p != '\t')
4190				break;
4191			*p = 0;
4192			field++;
4193			p++;
4194		}
4195		if (*p == 0)
4196			break;
4197		*p = 0;
4198	}
4199	return retval;
4200}
4201
4202int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size)
4203{
4204	struct bnxt *bp = netdev_priv(dev);
4205	u16 index = 0;
4206	char *pkgver;
4207	u32 pkglen;
4208	u8 *pkgbuf;
4209	int rc;
4210
4211	rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
4212				  BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
4213				  &index, NULL, &pkglen);
4214	if (rc)
4215		return rc;
4216
4217	pkgbuf = kzalloc(pkglen, GFP_KERNEL);
4218	if (!pkgbuf) {
4219		dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
4220			pkglen);
4221		return -ENOMEM;
4222	}
4223
4224	rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf);
4225	if (rc)
4226		goto err;
4227
4228	pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
4229				   pkglen);
4230	if (pkgver && *pkgver != 0 && isdigit(*pkgver))
4231		strscpy(ver, pkgver, size);
4232	else
4233		rc = -ENOENT;
4234
4235err:
4236	kfree(pkgbuf);
4237
4238	return rc;
4239}
4240
4241static void bnxt_get_pkgver(struct net_device *dev)
4242{
4243	struct bnxt *bp = netdev_priv(dev);
4244	char buf[FW_VER_STR_LEN - 5];
4245	int len;
4246
4247	if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) {
4248		len = strlen(bp->fw_ver_str);
4249		snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len,
4250			 "/pkg %s", buf);
4251	}
4252}
4253
4254static int bnxt_get_eeprom(struct net_device *dev,
4255			   struct ethtool_eeprom *eeprom,
4256			   u8 *data)
4257{
4258	u32 index;
4259	u32 offset;
4260
4261	if (eeprom->offset == 0) /* special offset value to get directory */
4262		return bnxt_get_nvram_directory(dev, eeprom->len, data);
4263
4264	index = eeprom->offset >> 24;
4265	offset = eeprom->offset & 0xffffff;
4266
4267	if (index == 0) {
4268		netdev_err(dev, "unsupported index value: %d\n", index);
4269		return -EINVAL;
4270	}
4271
4272	return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
4273}
4274
4275static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
4276{
4277	struct hwrm_nvm_erase_dir_entry_input *req;
4278	struct bnxt *bp = netdev_priv(dev);
4279	int rc;
4280
4281	rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY);
4282	if (rc)
4283		return rc;
4284
4285	req->dir_idx = cpu_to_le16(index);
4286	return hwrm_req_send(bp, req);
4287}
4288
4289static int bnxt_set_eeprom(struct net_device *dev,
4290			   struct ethtool_eeprom *eeprom,
4291			   u8 *data)
4292{
4293	struct bnxt *bp = netdev_priv(dev);
4294	u8 index, dir_op;
4295	u16 type, ext, ordinal, attr;
4296
4297	if (!BNXT_PF(bp)) {
4298		netdev_err(dev, "NVM write not supported from a virtual function\n");
4299		return -EINVAL;
4300	}
4301
4302	type = eeprom->magic >> 16;
4303
4304	if (type == 0xffff) { /* special value for directory operations */
4305		index = eeprom->magic & 0xff;
4306		dir_op = eeprom->magic >> 8;
4307		if (index == 0)
4308			return -EINVAL;
4309		switch (dir_op) {
4310		case 0x0e: /* erase */
4311			if (eeprom->offset != ~eeprom->magic)
4312				return -EINVAL;
4313			return bnxt_erase_nvram_directory(dev, index - 1);
4314		default:
4315			return -EINVAL;
4316		}
4317	}
4318
4319	/* Create or re-write an NVM item: */
4320	if (bnxt_dir_type_is_executable(type))
4321		return -EOPNOTSUPP;
4322	ext = eeprom->magic & 0xffff;
4323	ordinal = eeprom->offset >> 16;
4324	attr = eeprom->offset & 0xffff;
4325
4326	return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data,
4327				eeprom->len);
4328}
4329
4330static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata)
4331{
4332	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
4333	__ETHTOOL_DECLARE_LINK_MODE_MASK(tmp);
4334	struct bnxt *bp = netdev_priv(dev);
4335	struct ethtool_keee *eee = &bp->eee;
4336	struct bnxt_link_info *link_info = &bp->link_info;
4337	int rc = 0;
4338
4339	if (!BNXT_PHY_CFG_ABLE(bp))
4340		return -EOPNOTSUPP;
4341
4342	if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
4343		return -EOPNOTSUPP;
4344
4345	mutex_lock(&bp->link_lock);
4346	_bnxt_fw_to_linkmode(advertising, link_info->advertising);
4347	if (!edata->eee_enabled)
4348		goto eee_ok;
4349
4350	if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4351		netdev_warn(dev, "EEE requires autoneg\n");
4352		rc = -EINVAL;
4353		goto eee_exit;
4354	}
4355	if (edata->tx_lpi_enabled) {
4356		if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
4357				       edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
4358			netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
4359				    bp->lpi_tmr_lo, bp->lpi_tmr_hi);
4360			rc = -EINVAL;
4361			goto eee_exit;
4362		} else if (!bp->lpi_tmr_hi) {
4363			edata->tx_lpi_timer = eee->tx_lpi_timer;
4364		}
4365	}
4366	if (linkmode_empty(edata->advertised)) {
4367		linkmode_and(edata->advertised, advertising, eee->supported);
4368	} else if (linkmode_andnot(tmp, edata->advertised, advertising)) {
4369		netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n");
4370		rc = -EINVAL;
4371		goto eee_exit;
4372	}
4373
4374	linkmode_copy(eee->advertised, edata->advertised);
4375	eee->tx_lpi_enabled = edata->tx_lpi_enabled;
4376	eee->tx_lpi_timer = edata->tx_lpi_timer;
4377eee_ok:
4378	eee->eee_enabled = edata->eee_enabled;
4379
4380	if (netif_running(dev))
4381		rc = bnxt_hwrm_set_link_setting(bp, false, true);
4382
4383eee_exit:
4384	mutex_unlock(&bp->link_lock);
4385	return rc;
4386}
4387
4388static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata)
4389{
4390	struct bnxt *bp = netdev_priv(dev);
4391
4392	if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
4393		return -EOPNOTSUPP;
4394
4395	*edata = bp->eee;
4396	if (!bp->eee.eee_enabled) {
4397		/* Preserve tx_lpi_timer so that the last value will be used
4398		 * by default when it is re-enabled.
4399		 */
4400		linkmode_zero(edata->advertised);
4401		edata->tx_lpi_enabled = 0;
4402	}
4403
4404	if (!bp->eee.eee_active)
4405		linkmode_zero(edata->lp_advertised);
4406
4407	return 0;
4408}
4409
4410static int bnxt_hwrm_pfcwd_qcfg(struct bnxt *bp, u16 *val)
4411{
4412	struct hwrm_queue_pfcwd_timeout_qcfg_output *resp;
4413	struct hwrm_queue_pfcwd_timeout_qcfg_input *req;
4414	int rc;
4415
4416	rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_QCFG);
4417	if (rc)
4418		return rc;
4419	resp = hwrm_req_hold(bp, req);
4420	rc = hwrm_req_send(bp, req);
4421	if (!rc)
4422		*val = le16_to_cpu(resp->pfcwd_timeout_value);
4423	hwrm_req_drop(bp, req);
4424	return rc;
4425}
4426
4427static int bnxt_hwrm_pfcwd_cfg(struct bnxt *bp, u16 val)
4428{
4429	struct hwrm_queue_pfcwd_timeout_cfg_input *req;
4430	int rc;
4431
4432	rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_CFG);
4433	if (rc)
4434		return rc;
4435	req->pfcwd_timeout_value = cpu_to_le16(val);
4436	rc = hwrm_req_send(bp, req);
4437	return rc;
4438}
4439
4440static int bnxt_set_tunable(struct net_device *dev,
4441			    const struct ethtool_tunable *tuna,
4442			    const void *data)
4443{
4444	struct bnxt *bp = netdev_priv(dev);
4445	u32 rx_copybreak, val;
4446
4447	switch (tuna->id) {
4448	case ETHTOOL_RX_COPYBREAK:
4449		rx_copybreak = *(u32 *)data;
4450		if (rx_copybreak > BNXT_MAX_RX_COPYBREAK)
4451			return -ERANGE;
4452		if (rx_copybreak != bp->rx_copybreak) {
4453			if (netif_running(dev))
4454				return -EBUSY;
4455			bp->rx_copybreak = rx_copybreak;
4456		}
4457		return 0;
4458	case ETHTOOL_PFC_PREVENTION_TOUT:
4459		if (BNXT_VF(bp) || !bp->max_pfcwd_tmo_ms)
4460			return -EOPNOTSUPP;
4461
4462		val = *(u16 *)data;
4463		if (val > bp->max_pfcwd_tmo_ms &&
4464		    val != PFC_STORM_PREVENTION_AUTO)
4465			return -EINVAL;
4466		return bnxt_hwrm_pfcwd_cfg(bp, val);
4467	default:
4468		return -EOPNOTSUPP;
4469	}
4470}
4471
4472static int bnxt_get_tunable(struct net_device *dev,
4473			    const struct ethtool_tunable *tuna, void *data)
4474{
4475	struct bnxt *bp = netdev_priv(dev);
4476
4477	switch (tuna->id) {
4478	case ETHTOOL_RX_COPYBREAK:
4479		*(u32 *)data = bp->rx_copybreak;
4480		break;
4481	case ETHTOOL_PFC_PREVENTION_TOUT:
4482		if (!bp->max_pfcwd_tmo_ms)
4483			return -EOPNOTSUPP;
4484		return bnxt_hwrm_pfcwd_qcfg(bp, data);
4485	default:
4486		return -EOPNOTSUPP;
4487	}
4488
4489	return 0;
4490}
4491
4492static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
4493					    u16 page_number, u8 bank,
4494					    u16 start_addr, u16 data_length,
4495					    u8 *buf)
4496{
4497	struct hwrm_port_phy_i2c_read_output *output;
4498	struct hwrm_port_phy_i2c_read_input *req;
4499	int rc, byte_offset = 0;
4500
4501	rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ);
4502	if (rc)
4503		return rc;
4504
4505	output = hwrm_req_hold(bp, req);
4506	req->i2c_slave_addr = i2c_addr;
4507	req->page_number = cpu_to_le16(page_number);
4508	req->port_id = cpu_to_le16(bp->pf.port_id);
4509	do {
4510		u16 xfer_size;
4511
4512		xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
4513		data_length -= xfer_size;
4514		req->page_offset = cpu_to_le16(start_addr + byte_offset);
4515		req->data_length = xfer_size;
4516		req->enables =
4517			cpu_to_le32((start_addr + byte_offset ?
4518				     PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET :
4519				     0) |
4520				    (bank ?
4521				     PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER :
4522				     0));
4523		rc = hwrm_req_send(bp, req);
4524		if (!rc)
4525			memcpy(buf + byte_offset, output->data, xfer_size);
4526		byte_offset += xfer_size;
4527	} while (!rc && data_length > 0);
4528	hwrm_req_drop(bp, req);
4529
4530	return rc;
4531}
4532
4533static int bnxt_get_module_info(struct net_device *dev,
4534				struct ethtool_modinfo *modinfo)
4535{
4536	u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
4537	struct bnxt *bp = netdev_priv(dev);
4538	int rc;
4539
4540	if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4541		return -EPERM;
4542
4543	/* No point in going further if phy status indicates
4544	 * module is not inserted or if it is powered down or
4545	 * if it is of type 10GBase-T
4546	 */
4547	if (bp->link_info.module_status >
4548		PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4549		return -EOPNOTSUPP;
4550
4551	/* This feature is not supported in older firmware versions */
4552	if (bp->hwrm_spec_code < 0x10202)
4553		return -EOPNOTSUPP;
4554
4555	rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0,
4556					      SFF_DIAG_SUPPORT_OFFSET + 1,
4557					      data);
4558	if (!rc) {
4559		u8 module_id = data[0];
4560		u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
4561
4562		switch (module_id) {
4563		case SFF_MODULE_ID_SFP:
4564			modinfo->type = ETH_MODULE_SFF_8472;
4565			modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
4566			if (!diag_supported)
4567				modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4568			break;
4569		case SFF_MODULE_ID_QSFP:
4570		case SFF_MODULE_ID_QSFP_PLUS:
4571			modinfo->type = ETH_MODULE_SFF_8436;
4572			modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4573			break;
4574		case SFF_MODULE_ID_QSFP28:
4575			modinfo->type = ETH_MODULE_SFF_8636;
4576			modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
4577			break;
4578		default:
4579			rc = -EOPNOTSUPP;
4580			break;
4581		}
4582	}
4583	return rc;
4584}
4585
4586static int bnxt_get_module_eeprom(struct net_device *dev,
4587				  struct ethtool_eeprom *eeprom,
4588				  u8 *data)
4589{
4590	struct bnxt *bp = netdev_priv(dev);
4591	u16  start = eeprom->offset, length = eeprom->len;
4592	int rc = 0;
4593
4594	if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4595		return -EPERM;
4596
4597	memset(data, 0, eeprom->len);
4598
4599	/* Read A0 portion of the EEPROM */
4600	if (start < ETH_MODULE_SFF_8436_LEN) {
4601		if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
4602			length = ETH_MODULE_SFF_8436_LEN - start;
4603		rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
4604						      start, length, data);
4605		if (rc)
4606			return rc;
4607		start += length;
4608		data += length;
4609		length = eeprom->len - length;
4610	}
4611
4612	/* Read A2 portion of the EEPROM */
4613	if (length) {
4614		start -= ETH_MODULE_SFF_8436_LEN;
4615		rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0,
4616						      start, length, data);
4617	}
4618	return rc;
4619}
4620
4621static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack)
4622{
4623	if (bp->link_info.module_status <=
4624	    PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4625		return 0;
4626
4627	if (bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
4628	    bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE){
4629		NL_SET_ERR_MSG_MOD(extack, "Operation not supported as PHY type is Base-T");
4630		return -EOPNOTSUPP;
4631	}
4632	switch (bp->link_info.module_status) {
4633	case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
4634		NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down");
4635		break;
4636	case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED:
4637		NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted");
4638		break;
4639	case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT:
4640		NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault");
4641		break;
4642	default:
4643		NL_SET_ERR_MSG_MOD(extack, "Unknown error");
4644		break;
4645	}
4646	return -EINVAL;
4647}
4648
4649static int
4650bnxt_mod_eeprom_by_page_precheck(struct bnxt *bp,
4651				 const struct ethtool_module_eeprom *page_data,
4652				 struct netlink_ext_ack *extack)
4653{
4654	int rc;
4655
4656	if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
4657		NL_SET_ERR_MSG_MOD(extack,
4658				   "Module read/write not permitted on untrusted VF");
4659		return -EPERM;
4660	}
4661
4662	rc = bnxt_get_module_status(bp, extack);
4663	if (rc)
4664		return rc;
4665
4666	if (bp->hwrm_spec_code < 0x10202) {
4667		NL_SET_ERR_MSG_MOD(extack, "Firmware version too old");
4668		return -EINVAL;
4669	}
4670
4671	if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) {
4672		NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection");
4673		return -EINVAL;
4674	}
4675	return 0;
4676}
4677
4678static int bnxt_get_module_eeprom_by_page(struct net_device *dev,
4679					  const struct ethtool_module_eeprom *page_data,
4680					  struct netlink_ext_ack *extack)
4681{
4682	struct bnxt *bp = netdev_priv(dev);
4683	int rc;
4684
4685	rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack);
4686	if (rc)
4687		return rc;
4688
4689	rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1,
4690					      page_data->page, page_data->bank,
4691					      page_data->offset,
4692					      page_data->length,
4693					      page_data->data);
4694	if (rc) {
4695		NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed");
4696		return rc;
4697	}
4698	return page_data->length;
4699}
4700
4701static int bnxt_write_sfp_module_eeprom_info(struct bnxt *bp,
4702					     const struct ethtool_module_eeprom *page)
4703{
4704	struct hwrm_port_phy_i2c_write_input *req;
4705	int bytes_written = 0;
4706	int rc;
4707
4708	rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_WRITE);
4709	if (rc)
4710		return rc;
4711
4712	hwrm_req_hold(bp, req);
4713	req->i2c_slave_addr = page->i2c_address << 1;
4714	req->page_number = cpu_to_le16(page->page);
4715	req->bank_number = page->bank;
4716	req->port_id = cpu_to_le16(bp->pf.port_id);
4717	req->enables = cpu_to_le32(PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET |
4718				   PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER);
4719
4720	while (bytes_written < page->length) {
4721		u16 xfer_size;
4722
4723		xfer_size = min_t(u16, page->length - bytes_written,
4724				  BNXT_MAX_PHY_I2C_RESP_SIZE);
4725		req->page_offset = cpu_to_le16(page->offset + bytes_written);
4726		req->data_length = xfer_size;
4727		memcpy(req->data, page->data + bytes_written, xfer_size);
4728		rc = hwrm_req_send(bp, req);
4729		if (rc)
4730			break;
4731		bytes_written += xfer_size;
4732	}
4733
4734	hwrm_req_drop(bp, req);
4735	return rc;
4736}
4737
4738static int bnxt_set_module_eeprom_by_page(struct net_device *dev,
4739					  const struct ethtool_module_eeprom *page_data,
4740					  struct netlink_ext_ack *extack)
4741{
4742	struct bnxt *bp = netdev_priv(dev);
4743	int rc;
4744
4745	rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack);
4746	if (rc)
4747		return rc;
4748
4749	rc = bnxt_write_sfp_module_eeprom_info(bp, page_data);
4750	if (rc) {
4751		NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom write failed");
4752		return rc;
4753	}
4754	return page_data->length;
4755}
4756
4757static int bnxt_nway_reset(struct net_device *dev)
4758{
4759	int rc = 0;
4760
4761	struct bnxt *bp = netdev_priv(dev);
4762	struct bnxt_link_info *link_info = &bp->link_info;
4763
4764	if (!BNXT_PHY_CFG_ABLE(bp))
4765		return -EOPNOTSUPP;
4766
4767	if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
4768		return -EINVAL;
4769
4770	if (netif_running(dev))
4771		rc = bnxt_hwrm_set_link_setting(bp, true, false);
4772
4773	return rc;
4774}
4775
4776static int bnxt_set_phys_id(struct net_device *dev,
4777			    enum ethtool_phys_id_state state)
4778{
4779	struct hwrm_port_led_cfg_input *req;
4780	struct bnxt *bp = netdev_priv(dev);
4781	struct bnxt_pf_info *pf = &bp->pf;
4782	struct bnxt_led_cfg *led_cfg;
4783	u8 led_state;
4784	__le16 duration;
4785	int rc, i;
4786
4787	if (!bp->num_leds || BNXT_VF(bp))
4788		return -EOPNOTSUPP;
4789
4790	if (state == ETHTOOL_ID_ACTIVE) {
4791		led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
4792		duration = cpu_to_le16(500);
4793	} else if (state == ETHTOOL_ID_INACTIVE) {
4794		led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
4795		duration = cpu_to_le16(0);
4796	} else {
4797		return -EINVAL;
4798	}
4799	rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG);
4800	if (rc)
4801		return rc;
4802
4803	req->port_id = cpu_to_le16(pf->port_id);
4804	req->num_leds = bp->num_leds;
4805	led_cfg = (struct bnxt_led_cfg *)&req->led0_id;
4806	for (i = 0; i < bp->num_leds; i++, led_cfg++) {
4807		req->enables |= BNXT_LED_DFLT_ENABLES(i);
4808		led_cfg->led_id = bp->leds[i].led_id;
4809		led_cfg->led_state = led_state;
4810		led_cfg->led_blink_on = duration;
4811		led_cfg->led_blink_off = duration;
4812		led_cfg->led_group_id = bp->leds[i].led_group_id;
4813	}
4814	return hwrm_req_send(bp, req);
4815}
4816
4817static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
4818{
4819	struct hwrm_selftest_irq_input *req;
4820	int rc;
4821
4822	rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ);
4823	if (rc)
4824		return rc;
4825
4826	req->cmpl_ring = cpu_to_le16(cmpl_ring);
4827	return hwrm_req_send(bp, req);
4828}
4829
4830static int bnxt_test_irq(struct bnxt *bp)
4831{
4832	int i;
4833
4834	for (i = 0; i < bp->cp_nr_rings; i++) {
4835		u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
4836		int rc;
4837
4838		rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
4839		if (rc)
4840			return rc;
4841	}
4842	return 0;
4843}
4844
4845static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
4846{
4847	struct hwrm_port_mac_cfg_input *req;
4848	int rc;
4849
4850	rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
4851	if (rc)
4852		return rc;
4853
4854	req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
4855	if (enable)
4856		req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
4857	else
4858		req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
4859	return hwrm_req_send(bp, req);
4860}
4861
4862static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
4863{
4864	struct hwrm_port_phy_qcaps_output *resp;
4865	struct hwrm_port_phy_qcaps_input *req;
4866	int rc;
4867
4868	rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
4869	if (rc)
4870		return rc;
4871
4872	resp = hwrm_req_hold(bp, req);
4873	rc = hwrm_req_send(bp, req);
4874	if (!rc)
4875		*force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
4876
4877	hwrm_req_drop(bp, req);
4878	return rc;
4879}
4880
4881static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
4882				    struct hwrm_port_phy_cfg_input *req)
4883{
4884	struct bnxt_link_info *link_info = &bp->link_info;
4885	u16 fw_advertising;
4886	u16 fw_speed;
4887	int rc;
4888
4889	if (!link_info->autoneg ||
4890	    (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK))
4891		return 0;
4892
4893	rc = bnxt_query_force_speeds(bp, &fw_advertising);
4894	if (rc)
4895		return rc;
4896
4897	fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
4898	if (BNXT_LINK_IS_UP(bp))
4899		fw_speed = bp->link_info.link_speed;
4900	else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
4901		fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
4902	else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
4903		fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
4904	else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
4905		fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
4906	else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
4907		fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
4908
4909	req->force_link_speed = cpu_to_le16(fw_speed);
4910	req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
4911				  PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4912	rc = hwrm_req_send(bp, req);
4913	req->flags = 0;
4914	req->force_link_speed = cpu_to_le16(0);
4915	return rc;
4916}
4917
4918static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
4919{
4920	struct hwrm_port_phy_cfg_input *req;
4921	int rc;
4922
4923	rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
4924	if (rc)
4925		return rc;
4926
4927	/* prevent bnxt_disable_an_for_lpbk() from consuming the request */
4928	hwrm_req_hold(bp, req);
4929
4930	if (enable) {
4931		bnxt_disable_an_for_lpbk(bp, req);
4932		if (ext)
4933			req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
4934		else
4935			req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
4936	} else {
4937		req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
4938	}
4939	req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
4940	rc = hwrm_req_send(bp, req);
4941	hwrm_req_drop(bp, req);
4942	return rc;
4943}
4944
4945static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
4946			    u32 raw_cons, int pkt_size)
4947{
4948	struct bnxt_napi *bnapi = cpr->bnapi;
4949	struct bnxt_rx_ring_info *rxr;
4950	struct bnxt_sw_rx_bd *rx_buf;
4951	struct rx_cmp *rxcmp;
4952	u16 cp_cons, cons;
4953	u8 *data;
4954	u32 len;
4955	int i;
4956
4957	rxr = bnapi->rx_ring;
4958	cp_cons = RING_CMP(raw_cons);
4959	rxcmp = (struct rx_cmp *)
4960		&cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
4961	cons = rxcmp->rx_cmp_opaque;
4962	rx_buf = &rxr->rx_buf_ring[cons];
4963	data = rx_buf->data_ptr;
4964	len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
4965	if (len != pkt_size)
4966		return -EIO;
4967	i = ETH_ALEN;
4968	if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
4969		return -EIO;
4970	i += ETH_ALEN;
4971	for (  ; i < pkt_size; i++) {
4972		if (data[i] != (u8)(i & 0xff))
4973			return -EIO;
4974	}
4975	return 0;
4976}
4977
4978static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
4979			      int pkt_size)
4980{
4981	struct tx_cmp *txcmp;
4982	int rc = -EIO;
4983	u32 raw_cons;
4984	u32 cons;
4985	int i;
4986
4987	raw_cons = cpr->cp_raw_cons;
4988	for (i = 0; i < 200; i++) {
4989		cons = RING_CMP(raw_cons);
4990		txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
4991
4992		if (!TX_CMP_VALID(txcmp, raw_cons)) {
4993			udelay(5);
4994			continue;
4995		}
4996
4997		/* The valid test of the entry must be done first before
4998		 * reading any further.
4999		 */
5000		dma_rmb();
5001		if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP ||
5002		    TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) {
5003			rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
5004			raw_cons = NEXT_RAW_CMP(raw_cons);
5005			raw_cons = NEXT_RAW_CMP(raw_cons);
5006			break;
5007		}
5008		raw_cons = NEXT_RAW_CMP(raw_cons);
5009	}
5010	cpr->cp_raw_cons = raw_cons;
5011	return rc;
5012}
5013
5014static int bnxt_run_loopback(struct bnxt *bp)
5015{
5016	struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
5017	struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
5018	struct bnxt_cp_ring_info *cpr;
5019	int pkt_size, i = 0;
5020	struct sk_buff *skb;
5021	dma_addr_t map;
5022	u8 *data;
5023	int rc;
5024
5025	cpr = &rxr->bnapi->cp_ring;
5026	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
5027		cpr = rxr->rx_cpr;
5028	pkt_size = min(bp->dev->mtu + ETH_HLEN, max(BNXT_DEFAULT_RX_COPYBREAK,
5029						    bp->rx_copybreak));
5030	skb = netdev_alloc_skb(bp->dev, pkt_size);
5031	if (!skb)
5032		return -ENOMEM;
5033	data = skb_put(skb, pkt_size);
5034	ether_addr_copy(&data[i], bp->dev->dev_addr);
5035	i += ETH_ALEN;
5036	ether_addr_copy(&data[i], bp->dev->dev_addr);
5037	i += ETH_ALEN;
5038	for ( ; i < pkt_size; i++)
5039		data[i] = (u8)(i & 0xff);
5040
5041	map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5042			     DMA_TO_DEVICE);
5043	if (dma_mapping_error(&bp->pdev->dev, map)) {
5044		dev_kfree_skb(skb);
5045		return -EIO;
5046	}
5047	bnxt_xmit_bd(bp, txr, map, pkt_size, NULL);
5048
5049	/* Sync BD data before updating doorbell */
5050	wmb();
5051
5052	bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
5053	rc = bnxt_poll_loopback(bp, cpr, pkt_size);
5054
5055	dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
5056	dev_kfree_skb(skb);
5057	return rc;
5058}
5059
5060static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
5061{
5062	struct hwrm_selftest_exec_output *resp;
5063	struct hwrm_selftest_exec_input *req;
5064	int rc;
5065
5066	rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC);
5067	if (rc)
5068		return rc;
5069
5070	hwrm_req_timeout(bp, req, bp->test_info->timeout);
5071	req->flags = test_mask;
5072
5073	resp = hwrm_req_hold(bp, req);
5074	rc = hwrm_req_send(bp, req);
5075	*test_results = resp->test_success;
5076	hwrm_req_drop(bp, req);
5077	return rc;
5078}
5079
5080#define BNXT_DRV_TESTS			4
5081#define BNXT_MACLPBK_TEST_IDX		(bp->num_tests - BNXT_DRV_TESTS)
5082#define BNXT_PHYLPBK_TEST_IDX		(BNXT_MACLPBK_TEST_IDX + 1)
5083#define BNXT_EXTLPBK_TEST_IDX		(BNXT_MACLPBK_TEST_IDX + 2)
5084#define BNXT_IRQ_TEST_IDX		(BNXT_MACLPBK_TEST_IDX + 3)
5085
5086static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
5087			   u64 *buf)
5088{
5089	struct bnxt *bp = netdev_priv(dev);
5090	bool do_ext_lpbk = false;
5091	bool offline = false;
5092	u8 test_results = 0;
5093	u8 test_mask = 0;
5094	int rc = 0, i;
5095
5096	if (!bp->num_tests || !BNXT_PF(bp))
5097		return;
5098
5099	memset(buf, 0, sizeof(u64) * bp->num_tests);
5100	if (etest->flags & ETH_TEST_FL_OFFLINE &&
5101	    bnxt_ulp_registered(bp->edev)) {
5102		etest->flags |= ETH_TEST_FL_FAILED;
5103		netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n");
5104		return;
5105	}
5106
5107	if (!netif_running(dev)) {
5108		etest->flags |= ETH_TEST_FL_FAILED;
5109		return;
5110	}
5111
5112	if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
5113	    (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK))
5114		do_ext_lpbk = true;
5115
5116	if (etest->flags & ETH_TEST_FL_OFFLINE) {
5117		if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
5118			etest->flags |= ETH_TEST_FL_FAILED;
5119			netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
5120			return;
5121		}
5122		offline = true;
5123	}
5124
5125	for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
5126		u8 bit_val = 1 << i;
5127
5128		if (!(bp->test_info->offline_mask & bit_val))
5129			test_mask |= bit_val;
5130		else if (offline)
5131			test_mask |= bit_val;
5132	}
5133	if (!offline) {
5134		bnxt_run_fw_tests(bp, test_mask, &test_results);
5135	} else {
5136		bnxt_close_nic(bp, true, false);
5137		bnxt_run_fw_tests(bp, test_mask, &test_results);
5138
5139		rc = bnxt_half_open_nic(bp);
5140		if (rc) {
5141			etest->flags |= ETH_TEST_FL_FAILED;
5142			return;
5143		}
5144		buf[BNXT_MACLPBK_TEST_IDX] = 1;
5145		if (bp->mac_flags & BNXT_MAC_FL_NO_MAC_LPBK)
5146			goto skip_mac_loopback;
5147
5148		bnxt_hwrm_mac_loopback(bp, true);
5149		msleep(250);
5150		if (bnxt_run_loopback(bp))
5151			etest->flags |= ETH_TEST_FL_FAILED;
5152		else
5153			buf[BNXT_MACLPBK_TEST_IDX] = 0;
5154
5155		bnxt_hwrm_mac_loopback(bp, false);
5156skip_mac_loopback:
5157		buf[BNXT_PHYLPBK_TEST_IDX] = 1;
5158		if (bp->phy_flags & BNXT_PHY_FL_NO_PHY_LPBK)
5159			goto skip_phy_loopback;
5160
5161		bnxt_hwrm_phy_loopback(bp, true, false);
5162		msleep(1000);
5163		if (bnxt_run_loopback(bp))
5164			etest->flags |= ETH_TEST_FL_FAILED;
5165		else
5166			buf[BNXT_PHYLPBK_TEST_IDX] = 0;
5167skip_phy_loopback:
5168		buf[BNXT_EXTLPBK_TEST_IDX] = 1;
5169		if (do_ext_lpbk) {
5170			etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
5171			bnxt_hwrm_phy_loopback(bp, true, true);
5172			msleep(1000);
5173			if (bnxt_run_loopback(bp))
5174				etest->flags |= ETH_TEST_FL_FAILED;
5175			else
5176				buf[BNXT_EXTLPBK_TEST_IDX] = 0;
5177		}
5178		bnxt_hwrm_phy_loopback(bp, false, false);
5179		bnxt_half_close_nic(bp);
5180		rc = bnxt_open_nic(bp, true, true);
5181	}
5182	if (rc || bnxt_test_irq(bp)) {
5183		buf[BNXT_IRQ_TEST_IDX] = 1;
5184		etest->flags |= ETH_TEST_FL_FAILED;
5185	}
5186	for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
5187		u8 bit_val = 1 << i;
5188
5189		if ((test_mask & bit_val) && !(test_results & bit_val)) {
5190			buf[i] = 1;
5191			etest->flags |= ETH_TEST_FL_FAILED;
5192		}
5193	}
5194}
5195
5196static int bnxt_reset(struct net_device *dev, u32 *flags)
5197{
5198	struct bnxt *bp = netdev_priv(dev);
5199	bool reload = false;
5200	u32 req = *flags;
5201
5202	if (!req)
5203		return -EINVAL;
5204
5205	if (!BNXT_PF(bp)) {
5206		netdev_err(dev, "Reset is not supported from a VF\n");
5207		return -EOPNOTSUPP;
5208	}
5209
5210	if (pci_vfs_assigned(bp->pdev) &&
5211	    !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
5212		netdev_err(dev,
5213			   "Reset not allowed when VFs are assigned to VMs\n");
5214		return -EBUSY;
5215	}
5216
5217	if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
5218		/* This feature is not supported in older firmware versions */
5219		if (bp->hwrm_spec_code >= 0x10803) {
5220			if (!bnxt_firmware_reset_chip(dev)) {
5221				netdev_info(dev, "Firmware reset request successful.\n");
5222				if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
5223					reload = true;
5224				*flags &= ~BNXT_FW_RESET_CHIP;
5225			}
5226		} else if (req == BNXT_FW_RESET_CHIP) {
5227			return -EOPNOTSUPP; /* only request, fail hard */
5228		}
5229	}
5230
5231	if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) {
5232		/* This feature is not supported in older firmware versions */
5233		if (bp->hwrm_spec_code >= 0x10803) {
5234			if (!bnxt_firmware_reset_ap(dev)) {
5235				netdev_info(dev, "Reset application processor successful.\n");
5236				reload = true;
5237				*flags &= ~BNXT_FW_RESET_AP;
5238			}
5239		} else if (req == BNXT_FW_RESET_AP) {
5240			return -EOPNOTSUPP; /* only request, fail hard */
5241		}
5242	}
5243
5244	if (reload)
5245		netdev_info(dev, "Reload driver to complete reset\n");
5246
5247	return 0;
5248}
5249
5250static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
5251{
5252	struct bnxt *bp = netdev_priv(dev);
5253
5254	if (dump->flag > BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE) {
5255		netdev_info(dev,
5256			    "Supports only Live(0), Crash(1), Driver(2), Live with cached context(3) dumps.\n");
5257		return -EINVAL;
5258	}
5259
5260	if (dump->flag == BNXT_DUMP_CRASH) {
5261		if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR &&
5262		    (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) {
5263			netdev_info(dev,
5264				    "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
5265			return -EOPNOTSUPP;
5266		} else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) {
5267			netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n");
5268			return -EOPNOTSUPP;
5269		}
5270	}
5271
5272	bp->dump_flag = dump->flag;
5273	return 0;
5274}
5275
5276static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
5277{
5278	struct bnxt *bp = netdev_priv(dev);
5279
5280	if (bp->hwrm_spec_code < 0x10801)
5281		return -EOPNOTSUPP;
5282
5283	dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
5284			bp->ver_resp.hwrm_fw_min_8b << 16 |
5285			bp->ver_resp.hwrm_fw_bld_8b << 8 |
5286			bp->ver_resp.hwrm_fw_rsvd_8b;
5287
5288	dump->flag = bp->dump_flag;
5289	dump->len = bnxt_get_coredump_length(bp, bp->dump_flag);
5290	return 0;
5291}
5292
5293static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
5294			      void *buf)
5295{
5296	struct bnxt *bp = netdev_priv(dev);
5297
5298	if (bp->hwrm_spec_code < 0x10801)
5299		return -EOPNOTSUPP;
5300
5301	memset(buf, 0, dump->len);
5302
5303	dump->flag = bp->dump_flag;
5304	return bnxt_get_coredump(bp, dump->flag, buf, &dump->len);
5305}
5306
5307static int bnxt_get_ts_info(struct net_device *dev,
5308			    struct kernel_ethtool_ts_info *info)
5309{
5310	struct bnxt *bp = netdev_priv(dev);
5311	struct bnxt_ptp_cfg *ptp;
5312
5313	ptp = bp->ptp_cfg;
5314	info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE;
5315
5316	if (!ptp)
5317		return 0;
5318
5319	info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
5320				 SOF_TIMESTAMPING_RX_HARDWARE |
5321				 SOF_TIMESTAMPING_RAW_HARDWARE;
5322	if (ptp->ptp_clock)
5323		info->phc_index = ptp_clock_index(ptp->ptp_clock);
5324
5325	info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
5326
5327	info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
5328			   (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
5329			   (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
5330
5331	if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
5332		info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL);
5333	return 0;
5334}
5335
5336static void bnxt_hwrm_pcie_qstats(struct bnxt *bp)
5337{
5338	struct hwrm_pcie_qstats_output *resp;
5339	struct hwrm_pcie_qstats_input *req;
5340
5341	bp->pcie_stat_len = 0;
5342	if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
5343		return;
5344
5345	if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
5346		return;
5347
5348	resp = hwrm_req_hold(bp, req);
5349	if (__bnxt_hwrm_pcie_qstats(bp, req))
5350		bp->pcie_stat_len = min_t(u16,
5351					  le16_to_cpu(resp->pcie_stat_size),
5352					  sizeof(struct pcie_ctx_hw_stats_v2));
5353	hwrm_req_drop(bp, req);
5354}
5355
5356void bnxt_ethtool_init(struct bnxt *bp)
5357{
5358	struct hwrm_selftest_qlist_output *resp;
5359	struct hwrm_selftest_qlist_input *req;
5360	struct bnxt_test_info *test_info;
5361	struct net_device *dev = bp->dev;
5362	int i, rc;
5363
5364	bnxt_hwrm_pcie_qstats(bp);
5365	if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
5366		bnxt_get_pkgver(dev);
5367
5368	bp->num_tests = 0;
5369	if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
5370		return;
5371
5372	test_info = bp->test_info;
5373	if (!test_info) {
5374		test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
5375		if (!test_info)
5376			return;
5377		bp->test_info = test_info;
5378	}
5379
5380	if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST))
5381		return;
5382
5383	resp = hwrm_req_hold(bp, req);
5384	rc = hwrm_req_send_silent(bp, req);
5385	if (rc)
5386		goto ethtool_init_exit;
5387
5388	bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
5389	if (bp->num_tests > BNXT_MAX_TEST)
5390		bp->num_tests = BNXT_MAX_TEST;
5391
5392	test_info->offline_mask = resp->offline_tests;
5393	test_info->timeout = le16_to_cpu(resp->test_timeout);
5394	if (!test_info->timeout)
5395		test_info->timeout = HWRM_CMD_TIMEOUT;
5396	for (i = 0; i < bp->num_tests; i++) {
5397		char *str = test_info->string[i];
5398		char *fw_str = resp->test_name[i];
5399
5400		if (i == BNXT_MACLPBK_TEST_IDX) {
5401			strcpy(str, "Mac loopback test (offline)");
5402		} else if (i == BNXT_PHYLPBK_TEST_IDX) {
5403			strcpy(str, "Phy loopback test (offline)");
5404		} else if (i == BNXT_EXTLPBK_TEST_IDX) {
5405			strcpy(str, "Ext loopback test (offline)");
5406		} else if (i == BNXT_IRQ_TEST_IDX) {
5407			strcpy(str, "Interrupt_test (offline)");
5408		} else {
5409			snprintf(str, ETH_GSTRING_LEN, "%s test (%s)",
5410				 fw_str, test_info->offline_mask & (1 << i) ?
5411					"offline" : "online");
5412		}
5413	}
5414
5415ethtool_init_exit:
5416	hwrm_req_drop(bp, req);
5417}
5418
5419static void bnxt_get_eth_phy_stats(struct net_device *dev,
5420				   struct ethtool_eth_phy_stats *phy_stats)
5421{
5422	struct bnxt *bp = netdev_priv(dev);
5423	u64 *rx;
5424
5425	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5426		return;
5427
5428	rx = bp->rx_port_stats_ext.sw_stats;
5429	phy_stats->SymbolErrorDuringCarrier =
5430		*(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err));
5431}
5432
5433static void bnxt_get_eth_mac_stats(struct net_device *dev,
5434				   struct ethtool_eth_mac_stats *mac_stats)
5435{
5436	struct bnxt *bp = netdev_priv(dev);
5437	u64 *rx, *tx;
5438
5439	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5440		return;
5441
5442	rx = bp->port_stats.sw_stats;
5443	tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
5444
5445	mac_stats->FramesReceivedOK =
5446		BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames);
5447	mac_stats->FramesTransmittedOK =
5448		BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames);
5449	mac_stats->FrameCheckSequenceErrors =
5450		BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
5451	mac_stats->AlignmentErrors =
5452		BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
5453	mac_stats->OutOfRangeLengthField =
5454		BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames);
5455}
5456
5457static void bnxt_get_eth_ctrl_stats(struct net_device *dev,
5458				    struct ethtool_eth_ctrl_stats *ctrl_stats)
5459{
5460	struct bnxt *bp = netdev_priv(dev);
5461	u64 *rx;
5462
5463	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5464		return;
5465
5466	rx = bp->port_stats.sw_stats;
5467	ctrl_stats->MACControlFramesReceived =
5468		BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames);
5469}
5470
5471static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = {
5472	{    0,    64 },
5473	{   65,   127 },
5474	{  128,   255 },
5475	{  256,   511 },
5476	{  512,  1023 },
5477	{ 1024,  1518 },
5478	{ 1519,  2047 },
5479	{ 2048,  4095 },
5480	{ 4096,  9216 },
5481	{ 9217, 16383 },
5482	{}
5483};
5484
5485static void bnxt_get_rmon_stats(struct net_device *dev,
5486				struct ethtool_rmon_stats *rmon_stats,
5487				const struct ethtool_rmon_hist_range **ranges)
5488{
5489	struct bnxt *bp = netdev_priv(dev);
5490	u64 *rx, *tx;
5491
5492	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5493		return;
5494
5495	rx = bp->port_stats.sw_stats;
5496	tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
5497
5498	rmon_stats->jabbers =
5499		BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
5500	rmon_stats->oversize_pkts =
5501		BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames);
5502	rmon_stats->undersize_pkts =
5503		BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames);
5504
5505	rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames);
5506	rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames);
5507	rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames);
5508	rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames);
5509	rmon_stats->hist[4] =
5510		BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames);
5511	rmon_stats->hist[5] =
5512		BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames);
5513	rmon_stats->hist[6] =
5514		BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames);
5515	rmon_stats->hist[7] =
5516		BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames);
5517	rmon_stats->hist[8] =
5518		BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames);
5519	rmon_stats->hist[9] =
5520		BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames);
5521
5522	rmon_stats->hist_tx[0] =
5523		BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames);
5524	rmon_stats->hist_tx[1] =
5525		BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames);
5526	rmon_stats->hist_tx[2] =
5527		BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames);
5528	rmon_stats->hist_tx[3] =
5529		BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames);
5530	rmon_stats->hist_tx[4] =
5531		BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames);
5532	rmon_stats->hist_tx[5] =
5533		BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames);
5534	rmon_stats->hist_tx[6] =
5535		BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames);
5536	rmon_stats->hist_tx[7] =
5537		BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames);
5538	rmon_stats->hist_tx[8] =
5539		BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames);
5540	rmon_stats->hist_tx[9] =
5541		BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames);
5542
5543	*ranges = bnxt_rmon_ranges;
5544}
5545
5546static void bnxt_get_ptp_stats(struct net_device *dev,
5547			       struct ethtool_ts_stats *ts_stats)
5548{
5549	struct bnxt *bp = netdev_priv(dev);
5550	struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5551
5552	if (ptp) {
5553		ts_stats->pkts = ptp->stats.ts_pkts;
5554		ts_stats->lost = ptp->stats.ts_lost;
5555		ts_stats->err = atomic64_read(&ptp->stats.ts_err);
5556	}
5557}
5558
5559static void bnxt_get_link_ext_stats(struct net_device *dev,
5560				    struct ethtool_link_ext_stats *stats)
5561{
5562	struct bnxt *bp = netdev_priv(dev);
5563	u64 *rx;
5564
5565	if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5566		return;
5567
5568	rx = bp->rx_port_stats_ext.sw_stats;
5569	stats->link_down_events =
5570		*(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events));
5571}
5572
5573void bnxt_ethtool_free(struct bnxt *bp)
5574{
5575	kfree(bp->test_info);
5576	bp->test_info = NULL;
5577}
5578
5579const struct ethtool_ops bnxt_ethtool_ops = {
5580	.cap_link_lanes_supported	= 1,
5581	.rxfh_per_ctx_key		= 1,
5582	.rxfh_max_num_contexts		= BNXT_MAX_ETH_RSS_CTX + 1,
5583	.rxfh_indir_space		= BNXT_MAX_RSS_TABLE_ENTRIES_P5,
5584	.rxfh_priv_size			= sizeof(struct bnxt_rss_ctx),
5585	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5586				     ETHTOOL_COALESCE_MAX_FRAMES |
5587				     ETHTOOL_COALESCE_USECS_IRQ |
5588				     ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
5589				     ETHTOOL_COALESCE_STATS_BLOCK_USECS |
5590				     ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
5591				     ETHTOOL_COALESCE_USE_CQE,
5592	.supported_ring_params	= ETHTOOL_RING_USE_TCP_DATA_SPLIT |
5593				  ETHTOOL_RING_USE_HDS_THRS,
5594	.get_link_ksettings	= bnxt_get_link_ksettings,
5595	.set_link_ksettings	= bnxt_set_link_ksettings,
5596	.get_fec_stats		= bnxt_get_fec_stats,
5597	.get_fecparam		= bnxt_get_fecparam,
5598	.set_fecparam		= bnxt_set_fecparam,
5599	.get_pause_stats	= bnxt_get_pause_stats,
5600	.get_pauseparam		= bnxt_get_pauseparam,
5601	.set_pauseparam		= bnxt_set_pauseparam,
5602	.get_drvinfo		= bnxt_get_drvinfo,
5603	.get_regs_len		= bnxt_get_regs_len,
5604	.get_regs		= bnxt_get_regs,
5605	.get_wol		= bnxt_get_wol,
5606	.set_wol		= bnxt_set_wol,
5607	.get_coalesce		= bnxt_get_coalesce,
5608	.set_coalesce		= bnxt_set_coalesce,
5609	.get_msglevel		= bnxt_get_msglevel,
5610	.set_msglevel		= bnxt_set_msglevel,
5611	.get_sset_count		= bnxt_get_sset_count,
5612	.get_strings		= bnxt_get_strings,
5613	.get_ethtool_stats	= bnxt_get_ethtool_stats,
5614	.set_ringparam		= bnxt_set_ringparam,
5615	.get_ringparam		= bnxt_get_ringparam,
5616	.get_channels		= bnxt_get_channels,
5617	.set_channels		= bnxt_set_channels,
5618	.get_rxnfc		= bnxt_get_rxnfc,
5619	.set_rxnfc		= bnxt_set_rxnfc,
5620	.get_rx_ring_count	= bnxt_get_rx_ring_count,
5621	.get_rxfh_indir_size    = bnxt_get_rxfh_indir_size,
5622	.get_rxfh_key_size      = bnxt_get_rxfh_key_size,
5623	.get_rxfh               = bnxt_get_rxfh,
5624	.set_rxfh		= bnxt_set_rxfh,
5625	.get_rxfh_fields        = bnxt_get_rxfh_fields,
5626	.set_rxfh_fields        = bnxt_set_rxfh_fields,
5627	.create_rxfh_context	= bnxt_create_rxfh_context,
5628	.modify_rxfh_context	= bnxt_modify_rxfh_context,
5629	.remove_rxfh_context	= bnxt_remove_rxfh_context,
5630	.flash_device		= bnxt_flash_device,
5631	.get_eeprom_len         = bnxt_get_eeprom_len,
5632	.get_eeprom             = bnxt_get_eeprom,
5633	.set_eeprom		= bnxt_set_eeprom,
5634	.get_link		= bnxt_get_link,
5635	.get_link_ext_stats	= bnxt_get_link_ext_stats,
5636	.get_eee		= bnxt_get_eee,
5637	.set_eee		= bnxt_set_eee,
5638	.get_tunable		= bnxt_get_tunable,
5639	.set_tunable		= bnxt_set_tunable,
5640	.get_module_info	= bnxt_get_module_info,
5641	.get_module_eeprom	= bnxt_get_module_eeprom,
5642	.get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page,
5643	.set_module_eeprom_by_page = bnxt_set_module_eeprom_by_page,
5644	.nway_reset		= bnxt_nway_reset,
5645	.set_phys_id		= bnxt_set_phys_id,
5646	.self_test		= bnxt_self_test,
5647	.get_ts_info		= bnxt_get_ts_info,
5648	.reset			= bnxt_reset,
5649	.set_dump		= bnxt_set_dump,
5650	.get_dump_flag		= bnxt_get_dump_flag,
5651	.get_dump_data		= bnxt_get_dump_data,
5652	.get_eth_phy_stats	= bnxt_get_eth_phy_stats,
5653	.get_eth_mac_stats	= bnxt_get_eth_mac_stats,
5654	.get_eth_ctrl_stats	= bnxt_get_eth_ctrl_stats,
5655	.get_rmon_stats		= bnxt_get_rmon_stats,
5656	.get_ts_stats		= bnxt_get_ptp_stats,
5657};