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bnx2x_main.c
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linux-6.19.14/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
1/* bnx2x_main.c: QLogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12 * Written by: Eliezer Tamir 13 * Based on code from Michael Chan's bnx2 driver 14 * UDP CSUM errata workaround by Arik Gendelman 15 * Slowpath and fastpath rework by Vladislav Zolotarov 16 * Statistics and Link management by Yitchak Gertner 17 * 18 */ 19 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22#include <linux/module.h> 23#include <linux/moduleparam.h> 24#include <linux/kernel.h> 25#include <linux/device.h> /* for dev_info() */ 26#include <linux/timer.h> 27#include <linux/errno.h> 28#include <linux/ioport.h> 29#include <linux/slab.h> 30#include <linux/interrupt.h> 31#include <linux/pci.h> 32#include <linux/init.h> 33#include <linux/netdevice.h> 34#include <linux/etherdevice.h> 35#include <linux/skbuff.h> 36#include <linux/dma-mapping.h> 37#include <linux/bitops.h> 38#include <linux/irq.h> 39#include <linux/delay.h> 40#include <asm/byteorder.h> 41#include <linux/time.h> 42#include <linux/ethtool.h> 43#include <linux/mii.h> 44#include <linux/if_vlan.h> 45#include <linux/crash_dump.h> 46#include <net/ip.h> 47#include <net/ipv6.h> 48#include <net/tcp.h> 49#include <net/vxlan.h> 50#include <net/checksum.h> 51#include <net/ip6_checksum.h> 52#include <linux/workqueue.h> 53#include <linux/crc32.h> 54#include <linux/crc32c.h> 55#include <linux/prefetch.h> 56#include <linux/zlib.h> 57#include <linux/io.h> 58#include <linux/semaphore.h> 59#include <linux/stringify.h> 60#include <linux/vmalloc.h> 61#include "bnx2x.h" 62#include "bnx2x_init.h" 63#include "bnx2x_init_ops.h" 64#include "bnx2x_cmn.h" 65#include "bnx2x_vfpf.h" 66#include "bnx2x_dcb.h" 67#include "bnx2x_sp.h" 68#include <linux/firmware.h> 69#include "bnx2x_fw_file_hdr.h" 70/* FW files */ 71#define FW_FILE_VERSION \ 72 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 73 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 74 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 75 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 76 77#define FW_FILE_VERSION_V15 \ 78 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 79 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 80 __stringify(BCM_5710_FW_REVISION_VERSION_V15) "." \ 81 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 82 83#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 84#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 85#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 86#define FW_FILE_NAME_E1_V15 "bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw" 87#define FW_FILE_NAME_E1H_V15 "bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw" 88#define FW_FILE_NAME_E2_V15 "bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw" 89 90/* Time in jiffies before concluding the transmitter is hung */ 91#define TX_TIMEOUT (5*HZ) 92 93MODULE_AUTHOR("Eliezer Tamir"); 94MODULE_DESCRIPTION("QLogic " 95 "BCM57710/57711/57711E/" 96 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 97 "57840/57840_MF Driver"); 98MODULE_LICENSE("GPL"); 99MODULE_FIRMWARE(FW_FILE_NAME_E1); 100MODULE_FIRMWARE(FW_FILE_NAME_E1H); 101MODULE_FIRMWARE(FW_FILE_NAME_E2); 102MODULE_FIRMWARE(FW_FILE_NAME_E1_V15); 103MODULE_FIRMWARE(FW_FILE_NAME_E1H_V15); 104MODULE_FIRMWARE(FW_FILE_NAME_E2_V15); 105 106int bnx2x_num_queues; 107module_param_named(num_queues, bnx2x_num_queues, int, 0444); 108MODULE_PARM_DESC(num_queues, 109 " Set number of queues (default is as a number of CPUs)"); 110 111static int disable_tpa; 112module_param(disable_tpa, int, 0444); 113MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 114 115static int int_mode; 116module_param(int_mode, int, 0444); 117MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 118 "(1 INT#x; 2 MSI)"); 119 120static int dropless_fc; 121module_param(dropless_fc, int, 0444); 122MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 123 124static int mrrs = -1; 125module_param(mrrs, int, 0444); 126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 127 128static int debug; 129module_param(debug, int, 0444); 130MODULE_PARM_DESC(debug, " Default debug msglevel"); 131 132static struct workqueue_struct *bnx2x_wq; 133struct workqueue_struct *bnx2x_iov_wq; 134 135struct bnx2x_mac_vals { 136 u32 xmac_addr; 137 u32 xmac_val; 138 u32 emac_addr; 139 u32 emac_val; 140 u32 umac_addr[2]; 141 u32 umac_val[2]; 142 u32 bmac_addr; 143 u32 bmac_val[2]; 144}; 145 146enum bnx2x_board_type { 147 BCM57710 = 0, 148 BCM57711, 149 BCM57711E, 150 BCM57712, 151 BCM57712_MF, 152 BCM57712_VF, 153 BCM57800, 154 BCM57800_MF, 155 BCM57800_VF, 156 BCM57810, 157 BCM57810_MF, 158 BCM57810_VF, 159 BCM57840_4_10, 160 BCM57840_2_20, 161 BCM57840_MF, 162 BCM57840_VF, 163 BCM57811, 164 BCM57811_MF, 165 BCM57840_O, 166 BCM57840_MFO, 167 BCM57811_VF 168}; 169 170/* indexed by board_type, above */ 171static struct { 172 char *name; 173} board_info[] = { 174 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" }, 175 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" }, 176 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" }, 177 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" }, 178 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" }, 179 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" }, 180 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" }, 181 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" }, 182 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" }, 183 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" }, 184 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" }, 185 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" }, 186 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" }, 187 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" }, 188 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, 189 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }, 190 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" }, 191 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" }, 192 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" }, 193 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, 194 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" } 195}; 196 197#ifndef PCI_DEVICE_ID_NX2_57710 198#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 199#endif 200#ifndef PCI_DEVICE_ID_NX2_57711 201#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 202#endif 203#ifndef PCI_DEVICE_ID_NX2_57711E 204#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 205#endif 206#ifndef PCI_DEVICE_ID_NX2_57712 207#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 208#endif 209#ifndef PCI_DEVICE_ID_NX2_57712_MF 210#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 211#endif 212#ifndef PCI_DEVICE_ID_NX2_57712_VF 213#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF 214#endif 215#ifndef PCI_DEVICE_ID_NX2_57800 216#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 217#endif 218#ifndef PCI_DEVICE_ID_NX2_57800_MF 219#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 220#endif 221#ifndef PCI_DEVICE_ID_NX2_57800_VF 222#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF 223#endif 224#ifndef PCI_DEVICE_ID_NX2_57810 225#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 226#endif 227#ifndef PCI_DEVICE_ID_NX2_57810_MF 228#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 229#endif 230#ifndef PCI_DEVICE_ID_NX2_57840_O 231#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE 232#endif 233#ifndef PCI_DEVICE_ID_NX2_57810_VF 234#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF 235#endif 236#ifndef PCI_DEVICE_ID_NX2_57840_4_10 237#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 238#endif 239#ifndef PCI_DEVICE_ID_NX2_57840_2_20 240#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 241#endif 242#ifndef PCI_DEVICE_ID_NX2_57840_MFO 243#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE 244#endif 245#ifndef PCI_DEVICE_ID_NX2_57840_MF 246#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 247#endif 248#ifndef PCI_DEVICE_ID_NX2_57840_VF 249#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF 250#endif 251#ifndef PCI_DEVICE_ID_NX2_57811 252#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 253#endif 254#ifndef PCI_DEVICE_ID_NX2_57811_MF 255#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF 256#endif 257#ifndef PCI_DEVICE_ID_NX2_57811_VF 258#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF 259#endif 260 261static const struct pci_device_id bnx2x_pci_tbl[] = { 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, 274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, 275 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, 276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, 277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, 278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, 279 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 280 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 281 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, 282 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, 283 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, 284 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, 285 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, 286 { 0 } 287}; 288 289MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 290 291const u32 dmae_reg_go_c[] = { 292 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 293 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 294 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 295 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 296}; 297 298/* Global resources for unloading a previously loaded device */ 299#define BNX2X_PREV_WAIT_NEEDED 1 300static DEFINE_SEMAPHORE(bnx2x_prev_sem, 1); 301static LIST_HEAD(bnx2x_prev_list); 302 303/* Forward declaration */ 304static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); 305static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); 306static int bnx2x_set_storm_rx_mode(struct bnx2x *bp); 307 308/**************************************************************************** 309* General service functions 310****************************************************************************/ 311static int bnx2x_hwtstamp_set(struct net_device *dev, 312 struct kernel_hwtstamp_config *config, 313 struct netlink_ext_ack *extack); 314static int bnx2x_hwtstamp_get(struct net_device *dev, 315 struct kernel_hwtstamp_config *config); 316 317static void __storm_memset_dma_mapping(struct bnx2x *bp, 318 u32 addr, dma_addr_t mapping) 319{ 320 REG_WR(bp, addr, U64_LO(mapping)); 321 REG_WR(bp, addr + 4, U64_HI(mapping)); 322} 323 324static void storm_memset_spq_addr(struct bnx2x *bp, 325 dma_addr_t mapping, u16 abs_fid) 326{ 327 u32 addr = XSEM_REG_FAST_MEMORY + 328 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 329 330 __storm_memset_dma_mapping(bp, addr, mapping); 331} 332 333static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 334 u16 pf_id) 335{ 336 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 337 pf_id); 338 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 339 pf_id); 340 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 341 pf_id); 342 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 343 pf_id); 344} 345 346static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 347 u8 enable) 348{ 349 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 350 enable); 351 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 352 enable); 353 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 354 enable); 355 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 356 enable); 357} 358 359static void storm_memset_eq_data(struct bnx2x *bp, 360 struct event_ring_data *eq_data, 361 u16 pfid) 362{ 363 size_t size = sizeof(struct event_ring_data); 364 365 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 366 367 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 368} 369 370static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 371 u16 pfid) 372{ 373 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 374 REG_WR16(bp, addr, eq_prod); 375} 376 377/* used only at init 378 * locking is done by mcp 379 */ 380static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 381{ 382 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 383 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 384 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 385 PCICFG_VENDOR_ID_OFFSET); 386} 387 388static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 389{ 390 u32 val; 391 392 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 393 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 394 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 395 PCICFG_VENDOR_ID_OFFSET); 396 397 return val; 398} 399 400#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 401#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 402#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 403#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 404#define DMAE_DP_DST_NONE "dst_addr [none]" 405 406static void bnx2x_dp_dmae(struct bnx2x *bp, 407 struct dmae_command *dmae, int msglvl) 408{ 409 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 410 int i; 411 412 switch (dmae->opcode & DMAE_COMMAND_DST) { 413 case DMAE_CMD_DST_PCI: 414 if (src_type == DMAE_CMD_SRC_PCI) 415 DP(msglvl, "DMAE: opcode 0x%08x\n" 416 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 417 "comp_addr [%x:%08x], comp_val 0x%08x\n", 418 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 419 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 420 dmae->comp_addr_hi, dmae->comp_addr_lo, 421 dmae->comp_val); 422 else 423 DP(msglvl, "DMAE: opcode 0x%08x\n" 424 "src [%08x], len [%d*4], dst [%x:%08x]\n" 425 "comp_addr [%x:%08x], comp_val 0x%08x\n", 426 dmae->opcode, dmae->src_addr_lo >> 2, 427 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 428 dmae->comp_addr_hi, dmae->comp_addr_lo, 429 dmae->comp_val); 430 break; 431 case DMAE_CMD_DST_GRC: 432 if (src_type == DMAE_CMD_SRC_PCI) 433 DP(msglvl, "DMAE: opcode 0x%08x\n" 434 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 435 "comp_addr [%x:%08x], comp_val 0x%08x\n", 436 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 437 dmae->len, dmae->dst_addr_lo >> 2, 438 dmae->comp_addr_hi, dmae->comp_addr_lo, 439 dmae->comp_val); 440 else 441 DP(msglvl, "DMAE: opcode 0x%08x\n" 442 "src [%08x], len [%d*4], dst [%08x]\n" 443 "comp_addr [%x:%08x], comp_val 0x%08x\n", 444 dmae->opcode, dmae->src_addr_lo >> 2, 445 dmae->len, dmae->dst_addr_lo >> 2, 446 dmae->comp_addr_hi, dmae->comp_addr_lo, 447 dmae->comp_val); 448 break; 449 default: 450 if (src_type == DMAE_CMD_SRC_PCI) 451 DP(msglvl, "DMAE: opcode 0x%08x\n" 452 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 453 "comp_addr [%x:%08x] comp_val 0x%08x\n", 454 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 455 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 456 dmae->comp_val); 457 else 458 DP(msglvl, "DMAE: opcode 0x%08x\n" 459 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 460 "comp_addr [%x:%08x] comp_val 0x%08x\n", 461 dmae->opcode, dmae->src_addr_lo >> 2, 462 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 463 dmae->comp_val); 464 break; 465 } 466 467 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) 468 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", 469 i, *(((u32 *)dmae) + i)); 470} 471 472/* copy command into DMAE command memory and set DMAE command go */ 473void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 474{ 475 u32 cmd_offset; 476 int i; 477 478 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 479 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 480 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 481 } 482 REG_WR(bp, dmae_reg_go_c[idx], 1); 483} 484 485u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 486{ 487 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 488 DMAE_CMD_C_ENABLE); 489} 490 491u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 492{ 493 return opcode & ~DMAE_CMD_SRC_RESET; 494} 495 496u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 497 bool with_comp, u8 comp_type) 498{ 499 u32 opcode = 0; 500 501 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 502 (dst_type << DMAE_COMMAND_DST_SHIFT)); 503 504 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 505 506 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 507 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 508 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 509 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 510 511#ifdef __BIG_ENDIAN 512 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 513#else 514 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 515#endif 516 if (with_comp) 517 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 518 return opcode; 519} 520 521void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 522 struct dmae_command *dmae, 523 u8 src_type, u8 dst_type) 524{ 525 memset(dmae, 0, sizeof(struct dmae_command)); 526 527 /* set the opcode */ 528 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 529 true, DMAE_COMP_PCI); 530 531 /* fill in the completion parameters */ 532 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 533 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 534 dmae->comp_val = DMAE_COMP_VAL; 535} 536 537/* issue a dmae command over the init-channel and wait for completion */ 538int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 539 u32 *comp) 540{ 541 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 542 int rc = 0; 543 544 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); 545 546 /* Lock the dmae channel. Disable BHs to prevent a dead-lock 547 * as long as this code is called both from syscall context and 548 * from ndo_set_rx_mode() flow that may be called from BH. 549 */ 550 551 spin_lock_bh(&bp->dmae_lock); 552 553 /* reset completion */ 554 *comp = 0; 555 556 /* post the command on the channel used for initializations */ 557 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 558 559 /* wait for completion */ 560 udelay(5); 561 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 562 563 if (!cnt || 564 (bp->recovery_state != BNX2X_RECOVERY_DONE && 565 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 566 BNX2X_ERR("DMAE timeout!\n"); 567 rc = DMAE_TIMEOUT; 568 goto unlock; 569 } 570 cnt--; 571 udelay(50); 572 } 573 if (*comp & DMAE_PCI_ERR_FLAG) { 574 BNX2X_ERR("DMAE PCI error!\n"); 575 rc = DMAE_PCI_ERROR; 576 } 577 578unlock: 579 580 spin_unlock_bh(&bp->dmae_lock); 581 582 return rc; 583} 584 585void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 586 u32 len32) 587{ 588 int rc; 589 struct dmae_command dmae; 590 591 if (!bp->dmae_ready) { 592 u32 *data = bnx2x_sp(bp, wb_data[0]); 593 594 if (CHIP_IS_E1(bp)) 595 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 596 else 597 bnx2x_init_str_wr(bp, dst_addr, data, len32); 598 return; 599 } 600 601 /* set opcode and fixed command fields */ 602 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 603 604 /* fill in addresses and len */ 605 dmae.src_addr_lo = U64_LO(dma_addr); 606 dmae.src_addr_hi = U64_HI(dma_addr); 607 dmae.dst_addr_lo = dst_addr >> 2; 608 dmae.dst_addr_hi = 0; 609 dmae.len = len32; 610 611 /* issue the command and wait for completion */ 612 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); 613 if (rc) { 614 BNX2X_ERR("DMAE returned failure %d\n", rc); 615#ifdef BNX2X_STOP_ON_ERROR 616 bnx2x_panic(); 617#endif 618 } 619} 620 621void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 622{ 623 int rc; 624 struct dmae_command dmae; 625 626 if (!bp->dmae_ready) { 627 u32 *data = bnx2x_sp(bp, wb_data[0]); 628 int i; 629 630 if (CHIP_IS_E1(bp)) 631 for (i = 0; i < len32; i++) 632 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 633 else 634 for (i = 0; i < len32; i++) 635 data[i] = REG_RD(bp, src_addr + i*4); 636 637 return; 638 } 639 640 /* set opcode and fixed command fields */ 641 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 642 643 /* fill in addresses and len */ 644 dmae.src_addr_lo = src_addr >> 2; 645 dmae.src_addr_hi = 0; 646 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 647 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 648 dmae.len = len32; 649 650 /* issue the command and wait for completion */ 651 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); 652 if (rc) { 653 BNX2X_ERR("DMAE returned failure %d\n", rc); 654#ifdef BNX2X_STOP_ON_ERROR 655 bnx2x_panic(); 656#endif 657 } 658} 659 660static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 661 u32 addr, u32 len) 662{ 663 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 664 int offset = 0; 665 666 while (len > dmae_wr_max) { 667 bnx2x_write_dmae(bp, phys_addr + offset, 668 addr + offset, dmae_wr_max); 669 offset += dmae_wr_max * 4; 670 len -= dmae_wr_max; 671 } 672 673 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 674} 675 676enum storms { 677 XSTORM, 678 TSTORM, 679 CSTORM, 680 USTORM, 681 MAX_STORMS 682}; 683 684#define STORMS_NUM 4 685#define REGS_IN_ENTRY 4 686 687static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, 688 enum storms storm, 689 int entry) 690{ 691 switch (storm) { 692 case XSTORM: 693 return XSTORM_ASSERT_LIST_OFFSET(entry); 694 case TSTORM: 695 return TSTORM_ASSERT_LIST_OFFSET(entry); 696 case CSTORM: 697 return CSTORM_ASSERT_LIST_OFFSET(entry); 698 case USTORM: 699 return USTORM_ASSERT_LIST_OFFSET(entry); 700 case MAX_STORMS: 701 default: 702 BNX2X_ERR("unknown storm\n"); 703 } 704 return -EINVAL; 705} 706 707static int bnx2x_mc_assert(struct bnx2x *bp) 708{ 709 char last_idx; 710 int i, j, rc = 0; 711 enum storms storm; 712 u32 regs[REGS_IN_ENTRY]; 713 u32 bar_storm_intmem[STORMS_NUM] = { 714 BAR_XSTRORM_INTMEM, 715 BAR_TSTRORM_INTMEM, 716 BAR_CSTRORM_INTMEM, 717 BAR_USTRORM_INTMEM 718 }; 719 u32 storm_assert_list_index[STORMS_NUM] = { 720 XSTORM_ASSERT_LIST_INDEX_OFFSET, 721 TSTORM_ASSERT_LIST_INDEX_OFFSET, 722 CSTORM_ASSERT_LIST_INDEX_OFFSET, 723 USTORM_ASSERT_LIST_INDEX_OFFSET 724 }; 725 char *storms_string[STORMS_NUM] = { 726 "XSTORM", 727 "TSTORM", 728 "CSTORM", 729 "USTORM" 730 }; 731 732 for (storm = XSTORM; storm < MAX_STORMS; storm++) { 733 last_idx = REG_RD8(bp, bar_storm_intmem[storm] + 734 storm_assert_list_index[storm]); 735 if (last_idx) 736 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n", 737 storms_string[storm], last_idx); 738 739 /* print the asserts */ 740 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 741 /* read a single assert entry */ 742 for (j = 0; j < REGS_IN_ENTRY; j++) 743 regs[j] = REG_RD(bp, bar_storm_intmem[storm] + 744 bnx2x_get_assert_list_entry(bp, 745 storm, 746 i) + 747 sizeof(u32) * j); 748 749 /* log entry if it contains a valid assert */ 750 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) { 751 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 752 storms_string[storm], i, regs[3], 753 regs[2], regs[1], regs[0]); 754 rc++; 755 } else { 756 break; 757 } 758 } 759 } 760 761 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n", 762 CHIP_IS_E1(bp) ? "everest1" : 763 CHIP_IS_E1H(bp) ? "everest1h" : 764 CHIP_IS_E2(bp) ? "everest2" : "everest3", 765 bp->fw_major, bp->fw_minor, bp->fw_rev); 766 767 return rc; 768} 769 770#define MCPR_TRACE_BUFFER_SIZE (0x800) 771#define SCRATCH_BUFFER_SIZE(bp) \ 772 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000)) 773 774void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 775{ 776 u32 addr, val; 777 u32 mark, offset; 778 __be32 data[9]; 779 int word; 780 u32 trace_shmem_base; 781 if (BP_NOMCP(bp)) { 782 BNX2X_ERR("NO MCP - can not dump\n"); 783 return; 784 } 785 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 786 (bp->common.bc_ver & 0xff0000) >> 16, 787 (bp->common.bc_ver & 0xff00) >> 8, 788 (bp->common.bc_ver & 0xff)); 789 790 if (pci_channel_offline(bp->pdev)) { 791 BNX2X_ERR("Cannot dump MCP info while in PCI error\n"); 792 return; 793 } 794 795 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 796 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 797 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); 798 799 if (BP_PATH(bp) == 0) 800 trace_shmem_base = bp->common.shmem_base; 801 else 802 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 803 804 /* sanity */ 805 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || 806 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + 807 SCRATCH_BUFFER_SIZE(bp)) { 808 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n", 809 trace_shmem_base); 810 return; 811 } 812 813 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE; 814 815 /* validate TRCB signature */ 816 mark = REG_RD(bp, addr); 817 if (mark != MFW_TRACE_SIGNATURE) { 818 BNX2X_ERR("Trace buffer signature is missing."); 819 return ; 820 } 821 822 /* read cyclic buffer pointer */ 823 addr += 4; 824 mark = REG_RD(bp, addr); 825 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; 826 if (mark >= trace_shmem_base || mark < addr + 4) { 827 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n"); 828 return; 829 } 830 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 831 832 printk("%s", lvl); 833 834 /* dump buffer after the mark */ 835 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) { 836 for (word = 0; word < 8; word++) 837 data[word] = htonl(REG_RD(bp, offset + 4*word)); 838 data[8] = 0x0; 839 pr_cont("%s", (char *)data); 840 } 841 842 /* dump buffer before the mark */ 843 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 844 for (word = 0; word < 8; word++) 845 data[word] = htonl(REG_RD(bp, offset + 4*word)); 846 data[8] = 0x0; 847 pr_cont("%s", (char *)data); 848 } 849 printk("%s" "end of fw dump\n", lvl); 850} 851 852static void bnx2x_fw_dump(struct bnx2x *bp) 853{ 854 bnx2x_fw_dump_lvl(bp, KERN_ERR); 855} 856 857static void bnx2x_hc_int_disable(struct bnx2x *bp) 858{ 859 int port = BP_PORT(bp); 860 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 861 u32 val = REG_RD(bp, addr); 862 863 /* in E1 we must use only PCI configuration space to disable 864 * MSI/MSIX capability 865 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 866 */ 867 if (CHIP_IS_E1(bp)) { 868 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 869 * Use mask register to prevent from HC sending interrupts 870 * after we exit the function 871 */ 872 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 873 874 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 875 HC_CONFIG_0_REG_INT_LINE_EN_0 | 876 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 877 } else 878 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 879 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 880 HC_CONFIG_0_REG_INT_LINE_EN_0 | 881 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 882 883 DP(NETIF_MSG_IFDOWN, 884 "write %x to HC %d (addr 0x%x)\n", 885 val, port, addr); 886 887 REG_WR(bp, addr, val); 888 if (REG_RD(bp, addr) != val) 889 BNX2X_ERR("BUG! Proper val not read from IGU!\n"); 890} 891 892static void bnx2x_igu_int_disable(struct bnx2x *bp) 893{ 894 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 895 896 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 897 IGU_PF_CONF_INT_LINE_EN | 898 IGU_PF_CONF_ATTN_BIT_EN); 899 900 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); 901 902 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 903 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 904 BNX2X_ERR("BUG! Proper val not read from IGU!\n"); 905} 906 907static void bnx2x_int_disable(struct bnx2x *bp) 908{ 909 if (bp->common.int_block == INT_BLOCK_HC) 910 bnx2x_hc_int_disable(bp); 911 else 912 bnx2x_igu_int_disable(bp); 913} 914 915void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) 916{ 917 int i; 918 u16 j; 919 struct hc_sp_status_block_data sp_sb_data; 920 int func = BP_FUNC(bp); 921#ifdef BNX2X_STOP_ON_ERROR 922 u16 start = 0, end = 0; 923 u8 cos; 924#endif 925 if (IS_PF(bp) && disable_int) 926 bnx2x_int_disable(bp); 927 928 bp->stats_state = STATS_STATE_DISABLED; 929 bp->eth_stats.unrecoverable_error++; 930 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 931 932 BNX2X_ERR("begin crash dump -----------------\n"); 933 934 /* Indices */ 935 /* Common */ 936 if (IS_PF(bp)) { 937 struct host_sp_status_block *def_sb = bp->def_status_blk; 938 int data_size, cstorm_offset; 939 940 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 941 bp->def_idx, bp->def_att_idx, bp->attn_state, 942 bp->spq_prod_idx, bp->stats_counter); 943 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 944 def_sb->atten_status_block.attn_bits, 945 def_sb->atten_status_block.attn_bits_ack, 946 def_sb->atten_status_block.status_block_id, 947 def_sb->atten_status_block.attn_bits_index); 948 BNX2X_ERR(" def ("); 949 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 950 pr_cont("0x%x%s", 951 def_sb->sp_sb.index_values[i], 952 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 953 954 data_size = sizeof(struct hc_sp_status_block_data) / 955 sizeof(u32); 956 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func); 957 for (i = 0; i < data_size; i++) 958 *((u32 *)&sp_sb_data + i) = 959 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + 960 i * sizeof(u32)); 961 962 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 963 sp_sb_data.igu_sb_id, 964 sp_sb_data.igu_seg_id, 965 sp_sb_data.p_func.pf_id, 966 sp_sb_data.p_func.vnic_id, 967 sp_sb_data.p_func.vf_id, 968 sp_sb_data.p_func.vf_valid, 969 sp_sb_data.state); 970 } 971 972 for_each_eth_queue(bp, i) { 973 struct bnx2x_fastpath *fp = &bp->fp[i]; 974 int loop; 975 struct hc_status_block_data_e2 sb_data_e2; 976 struct hc_status_block_data_e1x sb_data_e1x; 977 struct hc_status_block_sm *hc_sm_p = 978 CHIP_IS_E1x(bp) ? 979 sb_data_e1x.common.state_machine : 980 sb_data_e2.common.state_machine; 981 struct hc_index_data *hc_index_p = 982 CHIP_IS_E1x(bp) ? 983 sb_data_e1x.index_data : 984 sb_data_e2.index_data; 985 u8 data_size, cos; 986 u32 *sb_data_p; 987 struct bnx2x_fp_txdata txdata; 988 989 if (!bp->fp) 990 break; 991 992 if (!fp->rx_cons_sb) 993 continue; 994 995 /* Rx */ 996 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 997 i, fp->rx_bd_prod, fp->rx_bd_cons, 998 fp->rx_comp_prod, 999 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 1000 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", 1001 fp->rx_sge_prod, fp->last_max_sge, 1002 le16_to_cpu(fp->fp_hc_idx)); 1003 1004 /* Tx */ 1005 for_each_cos_in_tx_queue(fp, cos) 1006 { 1007 if (!fp->txdata_ptr[cos]) 1008 break; 1009 1010 txdata = *fp->txdata_ptr[cos]; 1011 1012 if (!txdata.tx_cons_sb) 1013 continue; 1014 1015 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", 1016 i, txdata.tx_pkt_prod, 1017 txdata.tx_pkt_cons, txdata.tx_bd_prod, 1018 txdata.tx_bd_cons, 1019 le16_to_cpu(*txdata.tx_cons_sb)); 1020 } 1021 1022 loop = CHIP_IS_E1x(bp) ? 1023 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 1024 1025 /* host sb data */ 1026 1027 if (IS_FCOE_FP(fp)) 1028 continue; 1029 1030 BNX2X_ERR(" run indexes ("); 1031 for (j = 0; j < HC_SB_MAX_SM; j++) 1032 pr_cont("0x%x%s", 1033 fp->sb_running_index[j], 1034 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 1035 1036 BNX2X_ERR(" indexes ("); 1037 for (j = 0; j < loop; j++) 1038 pr_cont("0x%x%s", 1039 fp->sb_index_values[j], 1040 (j == loop - 1) ? ")" : " "); 1041 1042 /* VF cannot access FW refelection for status block */ 1043 if (IS_VF(bp)) 1044 continue; 1045 1046 /* fw sb data */ 1047 data_size = CHIP_IS_E1x(bp) ? 1048 sizeof(struct hc_status_block_data_e1x) : 1049 sizeof(struct hc_status_block_data_e2); 1050 data_size /= sizeof(u32); 1051 sb_data_p = CHIP_IS_E1x(bp) ? 1052 (u32 *)&sb_data_e1x : 1053 (u32 *)&sb_data_e2; 1054 /* copy sb data in here */ 1055 for (j = 0; j < data_size; j++) 1056 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 1057 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 1058 j * sizeof(u32)); 1059 1060 if (!CHIP_IS_E1x(bp)) { 1061 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 1062 sb_data_e2.common.p_func.pf_id, 1063 sb_data_e2.common.p_func.vf_id, 1064 sb_data_e2.common.p_func.vf_valid, 1065 sb_data_e2.common.p_func.vnic_id, 1066 sb_data_e2.common.same_igu_sb_1b, 1067 sb_data_e2.common.state); 1068 } else { 1069 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 1070 sb_data_e1x.common.p_func.pf_id, 1071 sb_data_e1x.common.p_func.vf_id, 1072 sb_data_e1x.common.p_func.vf_valid, 1073 sb_data_e1x.common.p_func.vnic_id, 1074 sb_data_e1x.common.same_igu_sb_1b, 1075 sb_data_e1x.common.state); 1076 } 1077 1078 /* SB_SMs data */ 1079 for (j = 0; j < HC_SB_MAX_SM; j++) { 1080 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", 1081 j, hc_sm_p[j].__flags, 1082 hc_sm_p[j].igu_sb_id, 1083 hc_sm_p[j].igu_seg_id, 1084 hc_sm_p[j].time_to_expire, 1085 hc_sm_p[j].timer_value); 1086 } 1087 1088 /* Indices data */ 1089 for (j = 0; j < loop; j++) { 1090 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, 1091 hc_index_p[j].flags, 1092 hc_index_p[j].timeout); 1093 } 1094 } 1095 1096#ifdef BNX2X_STOP_ON_ERROR 1097 if (IS_PF(bp)) { 1098 /* event queue */ 1099 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); 1100 for (i = 0; i < NUM_EQ_DESC; i++) { 1101 u32 *data = (u32 *)&bp->eq_ring[i].message.data; 1102 1103 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", 1104 i, bp->eq_ring[i].message.opcode, 1105 bp->eq_ring[i].message.error); 1106 BNX2X_ERR("data: %x %x %x\n", 1107 data[0], data[1], data[2]); 1108 } 1109 } 1110 1111 /* Rings */ 1112 /* Rx */ 1113 for_each_valid_rx_queue(bp, i) { 1114 struct bnx2x_fastpath *fp = &bp->fp[i]; 1115 1116 if (!bp->fp) 1117 break; 1118 1119 if (!fp->rx_cons_sb) 1120 continue; 1121 1122 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 1123 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 1124 for (j = start; j != end; j = RX_BD(j + 1)) { 1125 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 1126 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 1127 1128 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 1129 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 1130 } 1131 1132 start = RX_SGE(fp->rx_sge_prod); 1133 end = RX_SGE(fp->last_max_sge); 1134 for (j = start; j != end; j = RX_SGE(j + 1)) { 1135 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 1136 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 1137 1138 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 1139 i, j, rx_sge[1], rx_sge[0], sw_page->page); 1140 } 1141 1142 start = RCQ_BD(fp->rx_comp_cons - 10); 1143 end = RCQ_BD(fp->rx_comp_cons + 503); 1144 for (j = start; j != end; j = RCQ_BD(j + 1)) { 1145 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 1146 1147 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 1148 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 1149 } 1150 } 1151 1152 /* Tx */ 1153 for_each_valid_tx_queue(bp, i) { 1154 struct bnx2x_fastpath *fp = &bp->fp[i]; 1155 1156 if (!bp->fp) 1157 break; 1158 1159 for_each_cos_in_tx_queue(fp, cos) { 1160 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; 1161 1162 if (!fp->txdata_ptr[cos]) 1163 break; 1164 1165 if (!txdata->tx_cons_sb) 1166 continue; 1167 1168 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 1169 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 1170 for (j = start; j != end; j = TX_BD(j + 1)) { 1171 struct sw_tx_bd *sw_bd = 1172 &txdata->tx_buf_ring[j]; 1173 1174 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", 1175 i, cos, j, sw_bd->skb, 1176 sw_bd->first_bd); 1177 } 1178 1179 start = TX_BD(txdata->tx_bd_cons - 10); 1180 end = TX_BD(txdata->tx_bd_cons + 254); 1181 for (j = start; j != end; j = TX_BD(j + 1)) { 1182 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 1183 1184 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", 1185 i, cos, j, tx_bd[0], tx_bd[1], 1186 tx_bd[2], tx_bd[3]); 1187 } 1188 } 1189 } 1190#endif 1191 if (IS_PF(bp)) { 1192 int tmp_msg_en = bp->msg_enable; 1193 1194 bnx2x_fw_dump(bp); 1195 bp->msg_enable |= NETIF_MSG_HW; 1196 BNX2X_ERR("Idle check (1st round) ----------\n"); 1197 bnx2x_idle_chk(bp); 1198 BNX2X_ERR("Idle check (2nd round) ----------\n"); 1199 bnx2x_idle_chk(bp); 1200 bp->msg_enable = tmp_msg_en; 1201 bnx2x_mc_assert(bp); 1202 } 1203 1204 BNX2X_ERR("end crash dump -----------------\n"); 1205} 1206 1207/* 1208 * FLR Support for E2 1209 * 1210 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1211 * initialization. 1212 */ 1213#define FLR_WAIT_USEC 10000 /* 10 milliseconds */ 1214#define FLR_WAIT_INTERVAL 50 /* usec */ 1215#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1216 1217struct pbf_pN_buf_regs { 1218 int pN; 1219 u32 init_crd; 1220 u32 crd; 1221 u32 crd_freed; 1222}; 1223 1224struct pbf_pN_cmd_regs { 1225 int pN; 1226 u32 lines_occup; 1227 u32 lines_freed; 1228}; 1229 1230static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1231 struct pbf_pN_buf_regs *regs, 1232 u32 poll_count) 1233{ 1234 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1235 u32 cur_cnt = poll_count; 1236 1237 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1238 crd = crd_start = REG_RD(bp, regs->crd); 1239 init_crd = REG_RD(bp, regs->init_crd); 1240 1241 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1242 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1243 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1244 1245 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1246 (init_crd - crd_start))) { 1247 if (cur_cnt--) { 1248 udelay(FLR_WAIT_INTERVAL); 1249 crd = REG_RD(bp, regs->crd); 1250 crd_freed = REG_RD(bp, regs->crd_freed); 1251 } else { 1252 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1253 regs->pN); 1254 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1255 regs->pN, crd); 1256 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1257 regs->pN, crd_freed); 1258 break; 1259 } 1260 } 1261 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1262 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1263} 1264 1265static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1266 struct pbf_pN_cmd_regs *regs, 1267 u32 poll_count) 1268{ 1269 u32 occup, to_free, freed, freed_start; 1270 u32 cur_cnt = poll_count; 1271 1272 occup = to_free = REG_RD(bp, regs->lines_occup); 1273 freed = freed_start = REG_RD(bp, regs->lines_freed); 1274 1275 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1276 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1277 1278 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1279 if (cur_cnt--) { 1280 udelay(FLR_WAIT_INTERVAL); 1281 occup = REG_RD(bp, regs->lines_occup); 1282 freed = REG_RD(bp, regs->lines_freed); 1283 } else { 1284 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1285 regs->pN); 1286 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1287 regs->pN, occup); 1288 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1289 regs->pN, freed); 1290 break; 1291 } 1292 } 1293 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1294 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1295} 1296 1297static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1298 u32 expected, u32 poll_count) 1299{ 1300 u32 cur_cnt = poll_count; 1301 u32 val; 1302 1303 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1304 udelay(FLR_WAIT_INTERVAL); 1305 1306 return val; 1307} 1308 1309int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1310 char *msg, u32 poll_cnt) 1311{ 1312 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1313 if (val != 0) { 1314 BNX2X_ERR("%s usage count=%d\n", msg, val); 1315 return 1; 1316 } 1317 return 0; 1318} 1319 1320/* Common routines with VF FLR cleanup */ 1321u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1322{ 1323 /* adjust polling timeout */ 1324 if (CHIP_REV_IS_EMUL(bp)) 1325 return FLR_POLL_CNT * 2000; 1326 1327 if (CHIP_REV_IS_FPGA(bp)) 1328 return FLR_POLL_CNT * 120; 1329 1330 return FLR_POLL_CNT; 1331} 1332 1333void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1334{ 1335 struct pbf_pN_cmd_regs cmd_regs[] = { 1336 {0, (CHIP_IS_E3B0(bp)) ? 1337 PBF_REG_TQ_OCCUPANCY_Q0 : 1338 PBF_REG_P0_TQ_OCCUPANCY, 1339 (CHIP_IS_E3B0(bp)) ? 1340 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1341 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1342 {1, (CHIP_IS_E3B0(bp)) ? 1343 PBF_REG_TQ_OCCUPANCY_Q1 : 1344 PBF_REG_P1_TQ_OCCUPANCY, 1345 (CHIP_IS_E3B0(bp)) ? 1346 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1347 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1348 {4, (CHIP_IS_E3B0(bp)) ? 1349 PBF_REG_TQ_OCCUPANCY_LB_Q : 1350 PBF_REG_P4_TQ_OCCUPANCY, 1351 (CHIP_IS_E3B0(bp)) ? 1352 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1353 PBF_REG_P4_TQ_LINES_FREED_CNT} 1354 }; 1355 1356 struct pbf_pN_buf_regs buf_regs[] = { 1357 {0, (CHIP_IS_E3B0(bp)) ? 1358 PBF_REG_INIT_CRD_Q0 : 1359 PBF_REG_P0_INIT_CRD , 1360 (CHIP_IS_E3B0(bp)) ? 1361 PBF_REG_CREDIT_Q0 : 1362 PBF_REG_P0_CREDIT, 1363 (CHIP_IS_E3B0(bp)) ? 1364 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1365 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1366 {1, (CHIP_IS_E3B0(bp)) ? 1367 PBF_REG_INIT_CRD_Q1 : 1368 PBF_REG_P1_INIT_CRD, 1369 (CHIP_IS_E3B0(bp)) ? 1370 PBF_REG_CREDIT_Q1 : 1371 PBF_REG_P1_CREDIT, 1372 (CHIP_IS_E3B0(bp)) ? 1373 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1374 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1375 {4, (CHIP_IS_E3B0(bp)) ? 1376 PBF_REG_INIT_CRD_LB_Q : 1377 PBF_REG_P4_INIT_CRD, 1378 (CHIP_IS_E3B0(bp)) ? 1379 PBF_REG_CREDIT_LB_Q : 1380 PBF_REG_P4_CREDIT, 1381 (CHIP_IS_E3B0(bp)) ? 1382 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1383 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1384 }; 1385 1386 int i; 1387 1388 /* Verify the command queues are flushed P0, P1, P4 */ 1389 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1390 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1391 1392 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1393 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1394 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1395} 1396 1397#define OP_GEN_PARAM(param) \ 1398 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1399 1400#define OP_GEN_TYPE(type) \ 1401 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1402 1403#define OP_GEN_AGG_VECT(index) \ 1404 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1405 1406int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) 1407{ 1408 u32 op_gen_command = 0; 1409 u32 comp_addr = BAR_CSTRORM_INTMEM + 1410 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1411 1412 if (REG_RD(bp, comp_addr)) { 1413 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1414 return 1; 1415 } 1416 1417 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1418 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1419 op_gen_command |= OP_GEN_AGG_VECT(clnup_func); 1420 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1421 1422 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1423 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); 1424 1425 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1426 BNX2X_ERR("FW final cleanup did not succeed\n"); 1427 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", 1428 (REG_RD(bp, comp_addr))); 1429 bnx2x_panic(); 1430 return 1; 1431 } 1432 /* Zero completion for next FLR */ 1433 REG_WR(bp, comp_addr, 0); 1434 1435 return 0; 1436} 1437 1438u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1439{ 1440 u16 status; 1441 1442 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 1443 return status & PCI_EXP_DEVSTA_TRPND; 1444} 1445 1446/* PF FLR specific routines 1447*/ 1448static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1449{ 1450 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1451 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1452 CFC_REG_NUM_LCIDS_INSIDE_PF, 1453 "CFC PF usage counter timed out", 1454 poll_cnt)) 1455 return 1; 1456 1457 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1458 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1459 DORQ_REG_PF_USAGE_CNT, 1460 "DQ PF usage counter timed out", 1461 poll_cnt)) 1462 return 1; 1463 1464 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1465 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1466 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1467 "QM PF usage counter timed out", 1468 poll_cnt)) 1469 return 1; 1470 1471 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1472 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1473 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1474 "Timers VNIC usage counter timed out", 1475 poll_cnt)) 1476 return 1; 1477 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1478 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1479 "Timers NUM_SCANS usage counter timed out", 1480 poll_cnt)) 1481 return 1; 1482 1483 /* Wait DMAE PF usage counter to zero */ 1484 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1485 dmae_reg_go_c[INIT_DMAE_C(bp)], 1486 "DMAE command register timed out", 1487 poll_cnt)) 1488 return 1; 1489 1490 return 0; 1491} 1492 1493static void bnx2x_hw_enable_status(struct bnx2x *bp) 1494{ 1495 u32 val; 1496 1497 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1498 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1499 1500 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1501 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1502 1503 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1504 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1505 1506 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1507 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1508 1509 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1510 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1511 1512 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1513 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1514 1515 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1516 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1517 1518 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1519 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1520 val); 1521} 1522 1523static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1524{ 1525 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1526 1527 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1528 1529 /* Re-enable PF target read access */ 1530 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1531 1532 /* Poll HW usage counters */ 1533 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1534 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1535 return -EBUSY; 1536 1537 /* Zero the igu 'trailing edge' and 'leading edge' */ 1538 1539 /* Send the FW cleanup command */ 1540 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1541 return -EBUSY; 1542 1543 /* ATC cleanup */ 1544 1545 /* Verify TX hw is flushed */ 1546 bnx2x_tx_hw_flushed(bp, poll_cnt); 1547 1548 /* Wait 100ms (not adjusted according to platform) */ 1549 msleep(100); 1550 1551 /* Verify no pending pci transactions */ 1552 if (bnx2x_is_pcie_pending(bp->pdev)) 1553 BNX2X_ERR("PCIE Transactions still pending\n"); 1554 1555 /* Debug */ 1556 bnx2x_hw_enable_status(bp); 1557 1558 /* 1559 * Master enable - Due to WB DMAE writes performed before this 1560 * register is re-initialized as part of the regular function init 1561 */ 1562 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1563 1564 return 0; 1565} 1566 1567static void bnx2x_hc_int_enable(struct bnx2x *bp) 1568{ 1569 int port = BP_PORT(bp); 1570 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1571 u32 val = REG_RD(bp, addr); 1572 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1573 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1574 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1575 1576 if (msix) { 1577 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1578 HC_CONFIG_0_REG_INT_LINE_EN_0); 1579 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1580 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1581 if (single_msix) 1582 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; 1583 } else if (msi) { 1584 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1585 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1586 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1587 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1588 } else { 1589 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1590 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1591 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1592 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1593 1594 if (!CHIP_IS_E1(bp)) { 1595 DP(NETIF_MSG_IFUP, 1596 "write %x to HC %d (addr 0x%x)\n", val, port, addr); 1597 1598 REG_WR(bp, addr, val); 1599 1600 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1601 } 1602 } 1603 1604 if (CHIP_IS_E1(bp)) 1605 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1606 1607 DP(NETIF_MSG_IFUP, 1608 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, 1609 (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1610 1611 REG_WR(bp, addr, val); 1612 /* 1613 * Ensure that HC_CONFIG is written before leading/trailing edge config 1614 */ 1615 barrier(); 1616 1617 if (!CHIP_IS_E1(bp)) { 1618 /* init leading/trailing edge */ 1619 if (IS_MF(bp)) { 1620 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1621 if (bp->port.pmf) 1622 /* enable nig and gpio3 attention */ 1623 val |= 0x1100; 1624 } else 1625 val = 0xffff; 1626 1627 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1628 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1629 } 1630} 1631 1632static void bnx2x_igu_int_enable(struct bnx2x *bp) 1633{ 1634 u32 val; 1635 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1636 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1637 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1638 1639 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1640 1641 if (msix) { 1642 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1643 IGU_PF_CONF_SINGLE_ISR_EN); 1644 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1645 IGU_PF_CONF_ATTN_BIT_EN); 1646 1647 if (single_msix) 1648 val |= IGU_PF_CONF_SINGLE_ISR_EN; 1649 } else if (msi) { 1650 val &= ~IGU_PF_CONF_INT_LINE_EN; 1651 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1652 IGU_PF_CONF_ATTN_BIT_EN | 1653 IGU_PF_CONF_SINGLE_ISR_EN); 1654 } else { 1655 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1656 val |= (IGU_PF_CONF_INT_LINE_EN | 1657 IGU_PF_CONF_ATTN_BIT_EN | 1658 IGU_PF_CONF_SINGLE_ISR_EN); 1659 } 1660 1661 /* Clean previous status - need to configure igu prior to ack*/ 1662 if ((!msix) || single_msix) { 1663 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1664 bnx2x_ack_int(bp); 1665 } 1666 1667 val |= IGU_PF_CONF_FUNC_EN; 1668 1669 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", 1670 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1671 1672 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1673 1674 if (val & IGU_PF_CONF_INT_LINE_EN) 1675 pci_intx(bp->pdev, true); 1676 1677 barrier(); 1678 1679 /* init leading/trailing edge */ 1680 if (IS_MF(bp)) { 1681 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1682 if (bp->port.pmf) 1683 /* enable nig and gpio3 attention */ 1684 val |= 0x1100; 1685 } else 1686 val = 0xffff; 1687 1688 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1689 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1690} 1691 1692void bnx2x_int_enable(struct bnx2x *bp) 1693{ 1694 if (bp->common.int_block == INT_BLOCK_HC) 1695 bnx2x_hc_int_enable(bp); 1696 else 1697 bnx2x_igu_int_enable(bp); 1698} 1699 1700void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1701{ 1702 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1703 int i, offset; 1704 1705 if (disable_hw) 1706 /* prevent the HW from sending interrupts */ 1707 bnx2x_int_disable(bp); 1708 1709 /* make sure all ISRs are done */ 1710 if (msix) { 1711 synchronize_irq(bp->msix_table[0].vector); 1712 offset = 1; 1713 if (CNIC_SUPPORT(bp)) 1714 offset++; 1715 for_each_eth_queue(bp, i) 1716 synchronize_irq(bp->msix_table[offset++].vector); 1717 } else 1718 synchronize_irq(bp->pdev->irq); 1719 1720 /* make sure sp_task is not running */ 1721 cancel_delayed_work(&bp->sp_task); 1722 cancel_delayed_work(&bp->period_task); 1723 flush_workqueue(bnx2x_wq); 1724} 1725 1726/* fast path */ 1727 1728/* 1729 * General service functions 1730 */ 1731 1732/* Return true if succeeded to acquire the lock */ 1733static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1734{ 1735 u32 lock_status; 1736 u32 resource_bit = (1 << resource); 1737 int func = BP_FUNC(bp); 1738 u32 hw_lock_control_reg; 1739 1740 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1741 "Trying to take a lock on resource %d\n", resource); 1742 1743 /* Validating that the resource is within range */ 1744 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1745 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1746 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1747 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1748 return false; 1749 } 1750 1751 if (func <= 5) 1752 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1753 else 1754 hw_lock_control_reg = 1755 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1756 1757 /* Try to acquire the lock */ 1758 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1759 lock_status = REG_RD(bp, hw_lock_control_reg); 1760 if (lock_status & resource_bit) 1761 return true; 1762 1763 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1764 "Failed to get a lock on resource %d\n", resource); 1765 return false; 1766} 1767 1768/** 1769 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1770 * 1771 * @bp: driver handle 1772 * 1773 * Returns the recovery leader resource id according to the engine this function 1774 * belongs to. Currently only 2 engines is supported. 1775 */ 1776static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1777{ 1778 if (BP_PATH(bp)) 1779 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1780 else 1781 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1782} 1783 1784/** 1785 * bnx2x_trylock_leader_lock- try to acquire a leader lock. 1786 * 1787 * @bp: driver handle 1788 * 1789 * Tries to acquire a leader lock for current engine. 1790 */ 1791static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1792{ 1793 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1794} 1795 1796static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1797 1798/* schedule the sp task and mark that interrupt occurred (runs from ISR) */ 1799static int bnx2x_schedule_sp_task(struct bnx2x *bp) 1800{ 1801 /* Set the interrupt occurred bit for the sp-task to recognize it 1802 * must ack the interrupt and transition according to the IGU 1803 * state machine. 1804 */ 1805 atomic_set(&bp->interrupt_occurred, 1); 1806 1807 /* The sp_task must execute only after this bit 1808 * is set, otherwise we will get out of sync and miss all 1809 * further interrupts. Hence, the barrier. 1810 */ 1811 smp_wmb(); 1812 1813 /* schedule sp_task to workqueue */ 1814 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1815} 1816 1817void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1818{ 1819 struct bnx2x *bp = fp->bp; 1820 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1821 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1822 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1823 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 1824 1825 DP(BNX2X_MSG_SP, 1826 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1827 fp->index, cid, command, bp->state, 1828 rr_cqe->ramrod_cqe.ramrod_type); 1829 1830 /* If cid is within VF range, replace the slowpath object with the 1831 * one corresponding to this VF 1832 */ 1833 if (cid >= BNX2X_FIRST_VF_CID && 1834 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) 1835 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); 1836 1837 switch (command) { 1838 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1839 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1840 drv_cmd = BNX2X_Q_CMD_UPDATE; 1841 break; 1842 1843 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1844 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1845 drv_cmd = BNX2X_Q_CMD_SETUP; 1846 break; 1847 1848 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1849 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1850 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1851 break; 1852 1853 case (RAMROD_CMD_ID_ETH_HALT): 1854 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1855 drv_cmd = BNX2X_Q_CMD_HALT; 1856 break; 1857 1858 case (RAMROD_CMD_ID_ETH_TERMINATE): 1859 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); 1860 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1861 break; 1862 1863 case (RAMROD_CMD_ID_ETH_EMPTY): 1864 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1865 drv_cmd = BNX2X_Q_CMD_EMPTY; 1866 break; 1867 1868 case (RAMROD_CMD_ID_ETH_TPA_UPDATE): 1869 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid); 1870 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA; 1871 break; 1872 1873 default: 1874 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1875 command, fp->index); 1876 return; 1877 } 1878 1879 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1880 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1881 /* q_obj->complete_cmd() failure means that this was 1882 * an unexpected completion. 1883 * 1884 * In this case we don't want to increase the bp->spq_left 1885 * because apparently we haven't sent this command the first 1886 * place. 1887 */ 1888#ifdef BNX2X_STOP_ON_ERROR 1889 bnx2x_panic(); 1890#else 1891 return; 1892#endif 1893 1894 smp_mb__before_atomic(); 1895 atomic_inc(&bp->cq_spq_left); 1896 /* push the change in bp->spq_left and towards the memory */ 1897 smp_mb__after_atomic(); 1898 1899 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1900 1901 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && 1902 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { 1903 /* if Q update ramrod is completed for last Q in AFEX vif set 1904 * flow, then ACK MCP at the end 1905 * 1906 * mark pending ACK to MCP bit. 1907 * prevent case that both bits are cleared. 1908 * At the end of load/unload driver checks that 1909 * sp_state is cleared, and this order prevents 1910 * races 1911 */ 1912 smp_mb__before_atomic(); 1913 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); 1914 wmb(); 1915 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 1916 smp_mb__after_atomic(); 1917 1918 /* schedule the sp task as mcp ack is required */ 1919 bnx2x_schedule_sp_task(bp); 1920 } 1921 1922 return; 1923} 1924 1925irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1926{ 1927 struct bnx2x *bp = netdev_priv(dev_instance); 1928 u16 status = bnx2x_ack_int(bp); 1929 u16 mask; 1930 int i; 1931 u8 cos; 1932 1933 /* Return here if interrupt is shared and it's not for us */ 1934 if (unlikely(status == 0)) { 1935 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1936 return IRQ_NONE; 1937 } 1938 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1939 1940#ifdef BNX2X_STOP_ON_ERROR 1941 if (unlikely(bp->panic)) 1942 return IRQ_HANDLED; 1943#endif 1944 1945 for_each_eth_queue(bp, i) { 1946 struct bnx2x_fastpath *fp = &bp->fp[i]; 1947 1948 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); 1949 if (status & mask) { 1950 /* Handle Rx or Tx according to SB id */ 1951 for_each_cos_in_tx_queue(fp, cos) 1952 prefetch(fp->txdata_ptr[cos]->tx_cons_sb); 1953 prefetch(&fp->sb_running_index[SM_RX_ID]); 1954 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); 1955 status &= ~mask; 1956 } 1957 } 1958 1959 if (CNIC_SUPPORT(bp)) { 1960 mask = 0x2; 1961 if (status & (mask | 0x1)) { 1962 struct cnic_ops *c_ops = NULL; 1963 1964 rcu_read_lock(); 1965 c_ops = rcu_dereference(bp->cnic_ops); 1966 if (c_ops && (bp->cnic_eth_dev.drv_state & 1967 CNIC_DRV_STATE_HANDLES_IRQ)) 1968 c_ops->cnic_handler(bp->cnic_data, NULL); 1969 rcu_read_unlock(); 1970 1971 status &= ~mask; 1972 } 1973 } 1974 1975 if (unlikely(status & 0x1)) { 1976 1977 /* schedule sp task to perform default status block work, ack 1978 * attentions and enable interrupts. 1979 */ 1980 bnx2x_schedule_sp_task(bp); 1981 1982 status &= ~0x1; 1983 if (!status) 1984 return IRQ_HANDLED; 1985 } 1986 1987 if (unlikely(status)) 1988 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1989 status); 1990 1991 return IRQ_HANDLED; 1992} 1993 1994/* Link */ 1995 1996/* 1997 * General service functions 1998 */ 1999 2000int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 2001{ 2002 u32 lock_status; 2003 u32 resource_bit = (1 << resource); 2004 int func = BP_FUNC(bp); 2005 u32 hw_lock_control_reg; 2006 int cnt; 2007 2008 /* Validating that the resource is within range */ 2009 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 2010 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 2011 resource, HW_LOCK_MAX_RESOURCE_VALUE); 2012 return -EINVAL; 2013 } 2014 2015 if (func <= 5) { 2016 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 2017 } else { 2018 hw_lock_control_reg = 2019 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 2020 } 2021 2022 /* Validating that the resource is not already taken */ 2023 lock_status = REG_RD(bp, hw_lock_control_reg); 2024 if (lock_status & resource_bit) { 2025 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", 2026 lock_status, resource_bit); 2027 return -EEXIST; 2028 } 2029 2030 /* Try for 5 second every 5ms */ 2031 for (cnt = 0; cnt < 1000; cnt++) { 2032 /* Try to acquire the lock */ 2033 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 2034 lock_status = REG_RD(bp, hw_lock_control_reg); 2035 if (lock_status & resource_bit) 2036 return 0; 2037 2038 usleep_range(5000, 10000); 2039 } 2040 BNX2X_ERR("Timeout\n"); 2041 return -EAGAIN; 2042} 2043 2044int bnx2x_release_leader_lock(struct bnx2x *bp) 2045{ 2046 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 2047} 2048 2049int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 2050{ 2051 u32 lock_status; 2052 u32 resource_bit = (1 << resource); 2053 int func = BP_FUNC(bp); 2054 u32 hw_lock_control_reg; 2055 2056 /* Validating that the resource is within range */ 2057 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 2058 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 2059 resource, HW_LOCK_MAX_RESOURCE_VALUE); 2060 return -EINVAL; 2061 } 2062 2063 if (func <= 5) { 2064 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 2065 } else { 2066 hw_lock_control_reg = 2067 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 2068 } 2069 2070 /* Validating that the resource is currently taken */ 2071 lock_status = REG_RD(bp, hw_lock_control_reg); 2072 if (!(lock_status & resource_bit)) { 2073 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", 2074 lock_status, resource_bit); 2075 return -EFAULT; 2076 } 2077 2078 REG_WR(bp, hw_lock_control_reg, resource_bit); 2079 return 0; 2080} 2081 2082int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 2083{ 2084 /* The GPIO should be swapped if swap register is set and active */ 2085 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2086 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2087 int gpio_shift = gpio_num + 2088 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2089 u32 gpio_mask = (1 << gpio_shift); 2090 u32 gpio_reg; 2091 int value; 2092 2093 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2094 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2095 return -EINVAL; 2096 } 2097 2098 /* read GPIO value */ 2099 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2100 2101 /* get the requested pin value */ 2102 if ((gpio_reg & gpio_mask) == gpio_mask) 2103 value = 1; 2104 else 2105 value = 0; 2106 2107 return value; 2108} 2109 2110int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2111{ 2112 /* The GPIO should be swapped if swap register is set and active */ 2113 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2114 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2115 int gpio_shift = gpio_num + 2116 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2117 u32 gpio_mask = (1 << gpio_shift); 2118 u32 gpio_reg; 2119 2120 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2121 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2122 return -EINVAL; 2123 } 2124 2125 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2126 /* read GPIO and mask except the float bits */ 2127 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 2128 2129 switch (mode) { 2130 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2131 DP(NETIF_MSG_LINK, 2132 "Set GPIO %d (shift %d) -> output low\n", 2133 gpio_num, gpio_shift); 2134 /* clear FLOAT and set CLR */ 2135 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2136 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 2137 break; 2138 2139 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2140 DP(NETIF_MSG_LINK, 2141 "Set GPIO %d (shift %d) -> output high\n", 2142 gpio_num, gpio_shift); 2143 /* clear FLOAT and set SET */ 2144 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2145 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 2146 break; 2147 2148 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2149 DP(NETIF_MSG_LINK, 2150 "Set GPIO %d (shift %d) -> input\n", 2151 gpio_num, gpio_shift); 2152 /* set FLOAT */ 2153 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2154 break; 2155 2156 default: 2157 break; 2158 } 2159 2160 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2161 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2162 2163 return 0; 2164} 2165 2166int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 2167{ 2168 u32 gpio_reg = 0; 2169 int rc = 0; 2170 2171 /* Any port swapping should be handled by caller. */ 2172 2173 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2174 /* read GPIO and mask except the float bits */ 2175 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2176 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2177 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2178 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2179 2180 switch (mode) { 2181 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2182 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2183 /* set CLR */ 2184 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2185 break; 2186 2187 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2188 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2189 /* set SET */ 2190 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2191 break; 2192 2193 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2194 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2195 /* set FLOAT */ 2196 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2197 break; 2198 2199 default: 2200 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2201 rc = -EINVAL; 2202 break; 2203 } 2204 2205 if (rc == 0) 2206 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2207 2208 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2209 2210 return rc; 2211} 2212 2213int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2214{ 2215 /* The GPIO should be swapped if swap register is set and active */ 2216 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2217 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2218 int gpio_shift = gpio_num + 2219 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2220 u32 gpio_mask = (1 << gpio_shift); 2221 u32 gpio_reg; 2222 2223 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2224 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2225 return -EINVAL; 2226 } 2227 2228 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2229 /* read GPIO int */ 2230 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2231 2232 switch (mode) { 2233 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2234 DP(NETIF_MSG_LINK, 2235 "Clear GPIO INT %d (shift %d) -> output low\n", 2236 gpio_num, gpio_shift); 2237 /* clear SET and set CLR */ 2238 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2239 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2240 break; 2241 2242 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2243 DP(NETIF_MSG_LINK, 2244 "Set GPIO INT %d (shift %d) -> output high\n", 2245 gpio_num, gpio_shift); 2246 /* clear CLR and set SET */ 2247 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2248 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2249 break; 2250 2251 default: 2252 break; 2253 } 2254 2255 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2256 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2257 2258 return 0; 2259} 2260 2261static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) 2262{ 2263 u32 spio_reg; 2264 2265 /* Only 2 SPIOs are configurable */ 2266 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { 2267 BNX2X_ERR("Invalid SPIO 0x%x\n", spio); 2268 return -EINVAL; 2269 } 2270 2271 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2272 /* read SPIO and mask except the float bits */ 2273 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); 2274 2275 switch (mode) { 2276 case MISC_SPIO_OUTPUT_LOW: 2277 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); 2278 /* clear FLOAT and set CLR */ 2279 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2280 spio_reg |= (spio << MISC_SPIO_CLR_POS); 2281 break; 2282 2283 case MISC_SPIO_OUTPUT_HIGH: 2284 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); 2285 /* clear FLOAT and set SET */ 2286 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2287 spio_reg |= (spio << MISC_SPIO_SET_POS); 2288 break; 2289 2290 case MISC_SPIO_INPUT_HI_Z: 2291 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); 2292 /* set FLOAT */ 2293 spio_reg |= (spio << MISC_SPIO_FLOAT_POS); 2294 break; 2295 2296 default: 2297 break; 2298 } 2299 2300 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2301 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2302 2303 return 0; 2304} 2305 2306void bnx2x_calc_fc_adv(struct bnx2x *bp) 2307{ 2308 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2309 2310 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2311 ADVERTISED_Pause); 2312 switch (bp->link_vars.ieee_fc & 2313 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2314 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2315 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2316 ADVERTISED_Pause); 2317 break; 2318 2319 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2320 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2321 break; 2322 2323 default: 2324 break; 2325 } 2326} 2327 2328static void bnx2x_set_requested_fc(struct bnx2x *bp) 2329{ 2330 /* Initialize link parameters structure variables 2331 * It is recommended to turn off RX FC for jumbo frames 2332 * for better performance 2333 */ 2334 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2335 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2336 else 2337 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2338} 2339 2340static void bnx2x_init_dropless_fc(struct bnx2x *bp) 2341{ 2342 u32 pause_enabled = 0; 2343 2344 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { 2345 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2346 pause_enabled = 1; 2347 2348 REG_WR(bp, BAR_USTRORM_INTMEM + 2349 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), 2350 pause_enabled); 2351 } 2352 2353 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", 2354 pause_enabled ? "enabled" : "disabled"); 2355} 2356 2357int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2358{ 2359 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); 2360 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2361 2362 if (!BP_NOMCP(bp)) { 2363 bnx2x_set_requested_fc(bp); 2364 bnx2x_acquire_phy_lock(bp); 2365 2366 if (load_mode == LOAD_DIAG) { 2367 struct link_params *lp = &bp->link_params; 2368 lp->loopback_mode = LOOPBACK_XGXS; 2369 /* Prefer doing PHY loopback at highest speed */ 2370 if (lp->req_line_speed[cfx_idx] < SPEED_20000) { 2371 if (lp->speed_cap_mask[cfx_idx] & 2372 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 2373 lp->req_line_speed[cfx_idx] = 2374 SPEED_20000; 2375 else if (lp->speed_cap_mask[cfx_idx] & 2376 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2377 lp->req_line_speed[cfx_idx] = 2378 SPEED_10000; 2379 else 2380 lp->req_line_speed[cfx_idx] = 2381 SPEED_1000; 2382 } 2383 } 2384 2385 if (load_mode == LOAD_LOOPBACK_EXT) { 2386 struct link_params *lp = &bp->link_params; 2387 lp->loopback_mode = LOOPBACK_EXT; 2388 } 2389 2390 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2391 2392 bnx2x_release_phy_lock(bp); 2393 2394 bnx2x_init_dropless_fc(bp); 2395 2396 bnx2x_calc_fc_adv(bp); 2397 2398 if (bp->link_vars.link_up) { 2399 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2400 bnx2x_link_report(bp); 2401 } 2402 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2403 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2404 return rc; 2405 } 2406 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2407 return -EINVAL; 2408} 2409 2410void bnx2x_link_set(struct bnx2x *bp) 2411{ 2412 if (!BP_NOMCP(bp)) { 2413 bnx2x_acquire_phy_lock(bp); 2414 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2415 bnx2x_release_phy_lock(bp); 2416 2417 bnx2x_init_dropless_fc(bp); 2418 2419 bnx2x_calc_fc_adv(bp); 2420 } else 2421 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2422} 2423 2424static void bnx2x__link_reset(struct bnx2x *bp) 2425{ 2426 if (!BP_NOMCP(bp)) { 2427 bnx2x_acquire_phy_lock(bp); 2428 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); 2429 bnx2x_release_phy_lock(bp); 2430 } else 2431 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2432} 2433 2434void bnx2x_force_link_reset(struct bnx2x *bp) 2435{ 2436 bnx2x_acquire_phy_lock(bp); 2437 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2438 bnx2x_release_phy_lock(bp); 2439} 2440 2441u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2442{ 2443 u8 rc = 0; 2444 2445 if (!BP_NOMCP(bp)) { 2446 bnx2x_acquire_phy_lock(bp); 2447 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2448 is_serdes); 2449 bnx2x_release_phy_lock(bp); 2450 } else 2451 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2452 2453 return rc; 2454} 2455 2456/* Calculates the sum of vn_min_rates. 2457 It's needed for further normalizing of the min_rates. 2458 Returns: 2459 sum of vn_min_rates. 2460 or 2461 0 - if all the min_rates are 0. 2462 In the later case fairness algorithm should be deactivated. 2463 If not all min_rates are zero then those that are zeroes will be set to 1. 2464 */ 2465static void bnx2x_calc_vn_min(struct bnx2x *bp, 2466 struct cmng_init_input *input) 2467{ 2468 int all_zero = 1; 2469 int vn; 2470 2471 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2472 u32 vn_cfg = bp->mf_config[vn]; 2473 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2474 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2475 2476 /* Skip hidden vns */ 2477 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2478 vn_min_rate = 0; 2479 /* If min rate is zero - set it to 1 */ 2480 else if (!vn_min_rate) 2481 vn_min_rate = DEF_MIN_RATE; 2482 else 2483 all_zero = 0; 2484 2485 input->vnic_min_rate[vn] = vn_min_rate; 2486 } 2487 2488 /* if ETS or all min rates are zeros - disable fairness */ 2489 if (BNX2X_IS_ETS_ENABLED(bp)) { 2490 input->flags.cmng_enables &= 2491 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2492 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2493 } else if (all_zero) { 2494 input->flags.cmng_enables &= 2495 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2496 DP(NETIF_MSG_IFUP, 2497 "All MIN values are zeroes fairness will be disabled\n"); 2498 } else 2499 input->flags.cmng_enables |= 2500 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2501} 2502 2503static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, 2504 struct cmng_init_input *input) 2505{ 2506 u16 vn_max_rate; 2507 u32 vn_cfg = bp->mf_config[vn]; 2508 2509 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2510 vn_max_rate = 0; 2511 else { 2512 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2513 2514 if (IS_MF_PERCENT_BW(bp)) { 2515 /* maxCfg in percents of linkspeed */ 2516 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2517 } else /* SD modes */ 2518 /* maxCfg is absolute in 100Mb units */ 2519 vn_max_rate = maxCfg * 100; 2520 } 2521 2522 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); 2523 2524 input->vnic_max_rate[vn] = vn_max_rate; 2525} 2526 2527static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2528{ 2529 if (CHIP_REV_IS_SLOW(bp)) 2530 return CMNG_FNS_NONE; 2531 if (IS_MF(bp)) 2532 return CMNG_FNS_MINMAX; 2533 2534 return CMNG_FNS_NONE; 2535} 2536 2537void bnx2x_read_mf_cfg(struct bnx2x *bp) 2538{ 2539 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2540 2541 if (BP_NOMCP(bp)) 2542 return; /* what should be the default value in this case */ 2543 2544 /* For 2 port configuration the absolute function number formula 2545 * is: 2546 * abs_func = 2 * vn + BP_PORT + BP_PATH 2547 * 2548 * and there are 4 functions per port 2549 * 2550 * For 4 port configuration it is 2551 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2552 * 2553 * and there are 2 functions per port 2554 */ 2555 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2556 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2557 2558 if (func >= E1H_FUNC_MAX) 2559 break; 2560 2561 bp->mf_config[vn] = 2562 MF_CFG_RD(bp, func_mf_config[func].config); 2563 } 2564 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 2565 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); 2566 bp->flags |= MF_FUNC_DIS; 2567 } else { 2568 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 2569 bp->flags &= ~MF_FUNC_DIS; 2570 } 2571} 2572 2573static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2574{ 2575 struct cmng_init_input input; 2576 memset(&input, 0, sizeof(struct cmng_init_input)); 2577 2578 input.port_rate = bp->link_vars.line_speed; 2579 2580 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { 2581 int vn; 2582 2583 /* read mf conf from shmem */ 2584 if (read_cfg) 2585 bnx2x_read_mf_cfg(bp); 2586 2587 /* vn_weight_sum and enable fairness if not 0 */ 2588 bnx2x_calc_vn_min(bp, &input); 2589 2590 /* calculate and set min-max rate for each vn */ 2591 if (bp->port.pmf) 2592 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2593 bnx2x_calc_vn_max(bp, vn, &input); 2594 2595 /* always enable rate shaping and fairness */ 2596 input.flags.cmng_enables |= 2597 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2598 2599 bnx2x_init_cmng(&input, &bp->cmng); 2600 return; 2601 } 2602 2603 /* rate shaping and fairness are disabled */ 2604 DP(NETIF_MSG_IFUP, 2605 "rate shaping and fairness are disabled\n"); 2606} 2607 2608static void storm_memset_cmng(struct bnx2x *bp, 2609 struct cmng_init *cmng, 2610 u8 port) 2611{ 2612 int vn; 2613 size_t size = sizeof(struct cmng_struct_per_port); 2614 2615 u32 addr = BAR_XSTRORM_INTMEM + 2616 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); 2617 2618 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); 2619 2620 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2621 int func = func_by_vn(bp, vn); 2622 2623 addr = BAR_XSTRORM_INTMEM + 2624 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); 2625 size = sizeof(struct rate_shaping_vars_per_vn); 2626 __storm_memset_struct(bp, addr, size, 2627 (u32 *)&cmng->vnic.vnic_max_rate[vn]); 2628 2629 addr = BAR_XSTRORM_INTMEM + 2630 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); 2631 size = sizeof(struct fairness_vars_per_vn); 2632 __storm_memset_struct(bp, addr, size, 2633 (u32 *)&cmng->vnic.vnic_min_rate[vn]); 2634 } 2635} 2636 2637/* init cmng mode in HW according to local configuration */ 2638void bnx2x_set_local_cmng(struct bnx2x *bp) 2639{ 2640 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2641 2642 if (cmng_fns != CMNG_FNS_NONE) { 2643 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2644 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2645 } else { 2646 /* rate shaping and fairness are disabled */ 2647 DP(NETIF_MSG_IFUP, 2648 "single function mode without fairness\n"); 2649 } 2650} 2651 2652/* This function is called upon link interrupt */ 2653static void bnx2x_link_attn(struct bnx2x *bp) 2654{ 2655 /* Make sure that we are synced with the current statistics */ 2656 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2657 2658 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2659 2660 bnx2x_init_dropless_fc(bp); 2661 2662 if (bp->link_vars.link_up) { 2663 2664 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2665 struct host_port_stats *pstats; 2666 2667 pstats = bnx2x_sp(bp, port_stats); 2668 /* reset old mac stats */ 2669 memset(&(pstats->mac_stx[0]), 0, 2670 sizeof(struct mac_stx)); 2671 } 2672 if (bp->state == BNX2X_STATE_OPEN) 2673 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2674 } 2675 2676 if (bp->link_vars.link_up && bp->link_vars.line_speed) 2677 bnx2x_set_local_cmng(bp); 2678 2679 __bnx2x_link_report(bp); 2680 2681 if (IS_MF(bp)) 2682 bnx2x_link_sync_notify(bp); 2683} 2684 2685void bnx2x__link_status_update(struct bnx2x *bp) 2686{ 2687 if (bp->state != BNX2X_STATE_OPEN) 2688 return; 2689 2690 /* read updated dcb configuration */ 2691 if (IS_PF(bp)) { 2692 bnx2x_dcbx_pmf_update(bp); 2693 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2694 if (bp->link_vars.link_up) 2695 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2696 else 2697 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2698 /* indicate link status */ 2699 bnx2x_link_report(bp); 2700 2701 } else { /* VF */ 2702 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | 2703 SUPPORTED_10baseT_Full | 2704 SUPPORTED_100baseT_Half | 2705 SUPPORTED_100baseT_Full | 2706 SUPPORTED_1000baseT_Full | 2707 SUPPORTED_2500baseX_Full | 2708 SUPPORTED_10000baseT_Full | 2709 SUPPORTED_TP | 2710 SUPPORTED_FIBRE | 2711 SUPPORTED_Autoneg | 2712 SUPPORTED_Pause | 2713 SUPPORTED_Asym_Pause); 2714 bp->port.advertising[0] = bp->port.supported[0]; 2715 2716 bp->link_params.bp = bp; 2717 bp->link_params.port = BP_PORT(bp); 2718 bp->link_params.req_duplex[0] = DUPLEX_FULL; 2719 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; 2720 bp->link_params.req_line_speed[0] = SPEED_10000; 2721 bp->link_params.speed_cap_mask[0] = 0x7f0000; 2722 bp->link_params.switch_cfg = SWITCH_CFG_10G; 2723 bp->link_vars.mac_type = MAC_TYPE_BMAC; 2724 bp->link_vars.line_speed = SPEED_10000; 2725 bp->link_vars.link_status = 2726 (LINK_STATUS_LINK_UP | 2727 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); 2728 bp->link_vars.link_up = 1; 2729 bp->link_vars.duplex = DUPLEX_FULL; 2730 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; 2731 __bnx2x_link_report(bp); 2732 2733 bnx2x_sample_bulletin(bp); 2734 2735 /* if bulletin board did not have an update for link status 2736 * __bnx2x_link_report will report current status 2737 * but it will NOT duplicate report in case of already reported 2738 * during sampling bulletin board. 2739 */ 2740 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2741 } 2742} 2743 2744static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, 2745 u16 vlan_val, u8 allowed_prio) 2746{ 2747 struct bnx2x_func_state_params func_params = {NULL}; 2748 struct bnx2x_func_afex_update_params *f_update_params = 2749 &func_params.params.afex_update; 2750 2751 func_params.f_obj = &bp->func_obj; 2752 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; 2753 2754 /* no need to wait for RAMROD completion, so don't 2755 * set RAMROD_COMP_WAIT flag 2756 */ 2757 2758 f_update_params->vif_id = vifid; 2759 f_update_params->afex_default_vlan = vlan_val; 2760 f_update_params->allowed_priorities = allowed_prio; 2761 2762 /* if ramrod can not be sent, response to MCP immediately */ 2763 if (bnx2x_func_state_change(bp, &func_params) < 0) 2764 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 2765 2766 return 0; 2767} 2768 2769static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, 2770 u16 vif_index, u8 func_bit_map) 2771{ 2772 struct bnx2x_func_state_params func_params = {NULL}; 2773 struct bnx2x_func_afex_viflists_params *update_params = 2774 &func_params.params.afex_viflists; 2775 int rc; 2776 u32 drv_msg_code; 2777 2778 /* validate only LIST_SET and LIST_GET are received from switch */ 2779 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) 2780 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", 2781 cmd_type); 2782 2783 func_params.f_obj = &bp->func_obj; 2784 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; 2785 2786 /* set parameters according to cmd_type */ 2787 update_params->afex_vif_list_command = cmd_type; 2788 update_params->vif_list_index = vif_index; 2789 update_params->func_bit_map = 2790 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; 2791 update_params->func_to_clear = 0; 2792 drv_msg_code = 2793 (cmd_type == VIF_LIST_RULE_GET) ? 2794 DRV_MSG_CODE_AFEX_LISTGET_ACK : 2795 DRV_MSG_CODE_AFEX_LISTSET_ACK; 2796 2797 /* if ramrod can not be sent, respond to MCP immediately for 2798 * SET and GET requests (other are not triggered from MCP) 2799 */ 2800 rc = bnx2x_func_state_change(bp, &func_params); 2801 if (rc < 0) 2802 bnx2x_fw_command(bp, drv_msg_code, 0); 2803 2804 return 0; 2805} 2806 2807static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) 2808{ 2809 struct afex_stats afex_stats; 2810 u32 func = BP_ABS_FUNC(bp); 2811 u32 mf_config; 2812 u16 vlan_val; 2813 u32 vlan_prio; 2814 u16 vif_id; 2815 u8 allowed_prio; 2816 u8 vlan_mode; 2817 u32 addr_to_write, vifid, addrs, stats_type, i; 2818 2819 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { 2820 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2821 DP(BNX2X_MSG_MCP, 2822 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); 2823 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); 2824 } 2825 2826 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { 2827 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2828 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); 2829 DP(BNX2X_MSG_MCP, 2830 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", 2831 vifid, addrs); 2832 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, 2833 addrs); 2834 } 2835 2836 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { 2837 addr_to_write = SHMEM2_RD(bp, 2838 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); 2839 stats_type = SHMEM2_RD(bp, 2840 afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2841 2842 DP(BNX2X_MSG_MCP, 2843 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", 2844 addr_to_write); 2845 2846 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); 2847 2848 /* write response to scratchpad, for MCP */ 2849 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) 2850 REG_WR(bp, addr_to_write + i*sizeof(u32), 2851 *(((u32 *)(&afex_stats))+i)); 2852 2853 /* send ack message to MCP */ 2854 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); 2855 } 2856 2857 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { 2858 mf_config = MF_CFG_RD(bp, func_mf_config[func].config); 2859 bp->mf_config[BP_VN(bp)] = mf_config; 2860 DP(BNX2X_MSG_MCP, 2861 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", 2862 mf_config); 2863 2864 /* if VIF_SET is "enabled" */ 2865 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { 2866 /* set rate limit directly to internal RAM */ 2867 struct cmng_init_input cmng_input; 2868 struct rate_shaping_vars_per_vn m_rs_vn; 2869 size_t size = sizeof(struct rate_shaping_vars_per_vn); 2870 u32 addr = BAR_XSTRORM_INTMEM + 2871 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); 2872 2873 bp->mf_config[BP_VN(bp)] = mf_config; 2874 2875 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); 2876 m_rs_vn.vn_counter.rate = 2877 cmng_input.vnic_max_rate[BP_VN(bp)]; 2878 m_rs_vn.vn_counter.quota = 2879 (m_rs_vn.vn_counter.rate * 2880 RS_PERIODIC_TIMEOUT_USEC) / 8; 2881 2882 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); 2883 2884 /* read relevant values from mf_cfg struct in shmem */ 2885 vif_id = 2886 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2887 FUNC_MF_CFG_E1HOV_TAG_MASK) >> 2888 FUNC_MF_CFG_E1HOV_TAG_SHIFT; 2889 vlan_val = 2890 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2891 FUNC_MF_CFG_AFEX_VLAN_MASK) >> 2892 FUNC_MF_CFG_AFEX_VLAN_SHIFT; 2893 vlan_prio = (mf_config & 2894 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> 2895 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; 2896 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); 2897 vlan_mode = 2898 (MF_CFG_RD(bp, 2899 func_mf_config[func].afex_config) & 2900 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> 2901 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; 2902 allowed_prio = 2903 (MF_CFG_RD(bp, 2904 func_mf_config[func].afex_config) & 2905 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> 2906 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; 2907 2908 /* send ramrod to FW, return in case of failure */ 2909 if (bnx2x_afex_func_update(bp, vif_id, vlan_val, 2910 allowed_prio)) 2911 return; 2912 2913 bp->afex_def_vlan_tag = vlan_val; 2914 bp->afex_vlan_mode = vlan_mode; 2915 } else { 2916 /* notify link down because BP->flags is disabled */ 2917 bnx2x_link_report(bp); 2918 2919 /* send INVALID VIF ramrod to FW */ 2920 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); 2921 2922 /* Reset the default afex VLAN */ 2923 bp->afex_def_vlan_tag = -1; 2924 } 2925 } 2926} 2927 2928static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) 2929{ 2930 struct bnx2x_func_switch_update_params *switch_update_params; 2931 struct bnx2x_func_state_params func_params; 2932 2933 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params)); 2934 switch_update_params = &func_params.params.switch_update; 2935 func_params.f_obj = &bp->func_obj; 2936 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 2937 2938 /* Prepare parameters for function state transitions */ 2939 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 2940 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 2941 2942 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) { 2943 int func = BP_ABS_FUNC(bp); 2944 u32 val; 2945 2946 /* Re-learn the S-tag from shmem */ 2947 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2948 FUNC_MF_CFG_E1HOV_TAG_MASK; 2949 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 2950 bp->mf_ov = val; 2951 } else { 2952 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n"); 2953 goto fail; 2954 } 2955 2956 /* Configure new S-tag in LLH */ 2957 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, 2958 bp->mf_ov); 2959 2960 /* Send Ramrod to update FW of change */ 2961 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, 2962 &switch_update_params->changes); 2963 switch_update_params->vlan = bp->mf_ov; 2964 2965 if (bnx2x_func_state_change(bp, &func_params) < 0) { 2966 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n", 2967 bp->mf_ov); 2968 goto fail; 2969 } else { 2970 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", 2971 bp->mf_ov); 2972 } 2973 } else { 2974 goto fail; 2975 } 2976 2977 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); 2978 return; 2979fail: 2980 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); 2981} 2982 2983static void bnx2x_pmf_update(struct bnx2x *bp) 2984{ 2985 int port = BP_PORT(bp); 2986 u32 val; 2987 2988 bp->port.pmf = 1; 2989 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); 2990 2991 /* 2992 * We need the mb() to ensure the ordering between the writing to 2993 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2994 */ 2995 smp_mb(); 2996 2997 /* queue a periodic task */ 2998 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2999 3000 bnx2x_dcbx_pmf_update(bp); 3001 3002 /* enable nig attention */ 3003 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 3004 if (bp->common.int_block == INT_BLOCK_HC) { 3005 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 3006 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 3007 } else if (!CHIP_IS_E1x(bp)) { 3008 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 3009 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 3010 } 3011 3012 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 3013} 3014 3015/* end of Link */ 3016 3017/* slow path */ 3018 3019/* 3020 * General service functions 3021 */ 3022 3023/* send the MCP a request, block until there is a reply */ 3024u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 3025{ 3026 int mb_idx = BP_FW_MB_IDX(bp); 3027 u32 seq; 3028 u32 rc = 0; 3029 u32 cnt = 1; 3030 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 3031 3032 mutex_lock(&bp->fw_mb_mutex); 3033 seq = ++bp->fw_seq; 3034 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 3035 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 3036 3037 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 3038 (command | seq), param); 3039 3040 do { 3041 /* let the FW do it's magic ... */ 3042 msleep(delay); 3043 3044 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 3045 3046 /* Give the FW up to 5 second (500*10ms) */ 3047 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 3048 3049 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 3050 cnt*delay, rc, seq); 3051 3052 /* is this a reply to our command? */ 3053 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 3054 rc &= FW_MSG_CODE_MASK; 3055 else { 3056 /* FW BUG! */ 3057 BNX2X_ERR("FW failed to respond!\n"); 3058 bnx2x_fw_dump(bp); 3059 rc = 0; 3060 } 3061 mutex_unlock(&bp->fw_mb_mutex); 3062 3063 return rc; 3064} 3065 3066static void storm_memset_func_cfg(struct bnx2x *bp, 3067 struct tstorm_eth_function_common_config *tcfg, 3068 u16 abs_fid) 3069{ 3070 size_t size = sizeof(struct tstorm_eth_function_common_config); 3071 3072 u32 addr = BAR_TSTRORM_INTMEM + 3073 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); 3074 3075 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); 3076} 3077 3078void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 3079{ 3080 if (CHIP_IS_E1x(bp)) { 3081 struct tstorm_eth_function_common_config tcfg = {0}; 3082 3083 storm_memset_func_cfg(bp, &tcfg, p->func_id); 3084 } 3085 3086 /* Enable the function in the FW */ 3087 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 3088 storm_memset_func_en(bp, p->func_id, 1); 3089 3090 /* spq */ 3091 if (p->spq_active) { 3092 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 3093 REG_WR(bp, XSEM_REG_FAST_MEMORY + 3094 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 3095 } 3096} 3097 3098/** 3099 * bnx2x_get_common_flags - Return common flags 3100 * 3101 * @bp: device handle 3102 * @fp: queue handle 3103 * @zero_stats: TRUE if statistics zeroing is needed 3104 * 3105 * Return the flags that are common for the Tx-only and not normal connections. 3106 */ 3107static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 3108 struct bnx2x_fastpath *fp, 3109 bool zero_stats) 3110{ 3111 unsigned long flags = 0; 3112 3113 /* PF driver will always initialize the Queue to an ACTIVE state */ 3114 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 3115 3116 /* tx only connections collect statistics (on the same index as the 3117 * parent connection). The statistics are zeroed when the parent 3118 * connection is initialized. 3119 */ 3120 3121 __set_bit(BNX2X_Q_FLG_STATS, &flags); 3122 if (zero_stats) 3123 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 3124 3125 if (bp->flags & TX_SWITCHING) 3126 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags); 3127 3128 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); 3129 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); 3130 3131#ifdef BNX2X_STOP_ON_ERROR 3132 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); 3133#endif 3134 3135 return flags; 3136} 3137 3138static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 3139 struct bnx2x_fastpath *fp, 3140 bool leading) 3141{ 3142 unsigned long flags = 0; 3143 3144 /* calculate other queue flags */ 3145 if (IS_MF_SD(bp)) 3146 __set_bit(BNX2X_Q_FLG_OV, &flags); 3147 3148 if (IS_FCOE_FP(fp)) { 3149 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 3150 /* For FCoE - force usage of default priority (for afex) */ 3151 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); 3152 } 3153 3154 if (fp->mode != TPA_MODE_DISABLED) { 3155 __set_bit(BNX2X_Q_FLG_TPA, &flags); 3156 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 3157 if (fp->mode == TPA_MODE_GRO) 3158 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 3159 } 3160 3161 if (leading) { 3162 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 3163 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 3164 } 3165 3166 /* Always set HW VLAN stripping */ 3167 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 3168 3169 /* configure silent vlan removal */ 3170 if (IS_MF_AFEX(bp)) 3171 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); 3172 3173 return flags | bnx2x_get_common_flags(bp, fp, true); 3174} 3175 3176static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 3177 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 3178 u8 cos) 3179{ 3180 gen_init->stat_id = bnx2x_stats_id(fp); 3181 gen_init->spcl_id = fp->cl_id; 3182 3183 /* Always use mini-jumbo MTU for FCoE L2 ring */ 3184 if (IS_FCOE_FP(fp)) 3185 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 3186 else 3187 gen_init->mtu = bp->dev->mtu; 3188 3189 gen_init->cos = cos; 3190 3191 gen_init->fp_hsi = ETH_FP_HSI_VERSION; 3192} 3193 3194static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 3195 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 3196 struct bnx2x_rxq_setup_params *rxq_init) 3197{ 3198 u8 max_sge = 0; 3199 u16 sge_sz = 0; 3200 u16 tpa_agg_size = 0; 3201 3202 if (fp->mode != TPA_MODE_DISABLED) { 3203 pause->sge_th_lo = SGE_TH_LO(bp); 3204 pause->sge_th_hi = SGE_TH_HI(bp); 3205 3206 /* validate SGE ring has enough to cross high threshold */ 3207 WARN_ON(bp->dropless_fc && 3208 pause->sge_th_hi + FW_PREFETCH_CNT > 3209 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 3210 3211 tpa_agg_size = TPA_AGG_SIZE; 3212 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 3213 SGE_PAGE_SHIFT; 3214 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 3215 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 3216 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); 3217 } 3218 3219 /* pause - not for e1 */ 3220 if (!CHIP_IS_E1(bp)) { 3221 pause->bd_th_lo = BD_TH_LO(bp); 3222 pause->bd_th_hi = BD_TH_HI(bp); 3223 3224 pause->rcq_th_lo = RCQ_TH_LO(bp); 3225 pause->rcq_th_hi = RCQ_TH_HI(bp); 3226 /* 3227 * validate that rings have enough entries to cross 3228 * high thresholds 3229 */ 3230 WARN_ON(bp->dropless_fc && 3231 pause->bd_th_hi + FW_PREFETCH_CNT > 3232 bp->rx_ring_size); 3233 WARN_ON(bp->dropless_fc && 3234 pause->rcq_th_hi + FW_PREFETCH_CNT > 3235 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 3236 3237 pause->pri_map = 1; 3238 } 3239 3240 /* rxq setup */ 3241 rxq_init->dscr_map = fp->rx_desc_mapping; 3242 rxq_init->sge_map = fp->rx_sge_mapping; 3243 rxq_init->rcq_map = fp->rx_comp_mapping; 3244 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 3245 3246 /* This should be a maximum number of data bytes that may be 3247 * placed on the BD (not including paddings). 3248 */ 3249 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 3250 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 3251 3252 rxq_init->cl_qzone_id = fp->cl_qzone_id; 3253 rxq_init->tpa_agg_sz = tpa_agg_size; 3254 rxq_init->sge_buf_sz = sge_sz; 3255 rxq_init->max_sges_pkt = max_sge; 3256 rxq_init->rss_engine_id = BP_FUNC(bp); 3257 rxq_init->mcast_engine_id = BP_FUNC(bp); 3258 3259 /* Maximum number or simultaneous TPA aggregation for this Queue. 3260 * 3261 * For PF Clients it should be the maximum available number. 3262 * VF driver(s) may want to define it to a smaller value. 3263 */ 3264 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 3265 3266 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 3267 rxq_init->fw_sb_id = fp->fw_sb_id; 3268 3269 if (IS_FCOE_FP(fp)) 3270 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 3271 else 3272 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 3273 /* configure silent vlan removal 3274 * if multi function mode is afex, then mask default vlan 3275 */ 3276 if (IS_MF_AFEX(bp)) { 3277 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; 3278 rxq_init->silent_removal_mask = VLAN_VID_MASK; 3279 } 3280} 3281 3282static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 3283 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 3284 u8 cos) 3285{ 3286 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; 3287 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 3288 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 3289 txq_init->fw_sb_id = fp->fw_sb_id; 3290 3291 /* 3292 * set the tss leading client id for TX classification == 3293 * leading RSS client id 3294 */ 3295 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 3296 3297 if (IS_FCOE_FP(fp)) { 3298 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 3299 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 3300 } 3301} 3302 3303static void bnx2x_pf_init(struct bnx2x *bp) 3304{ 3305 struct bnx2x_func_init_params func_init = {0}; 3306 struct event_ring_data eq_data = { {0} }; 3307 3308 if (!CHIP_IS_E1x(bp)) { 3309 /* reset IGU PF statistics: MSIX + ATTN */ 3310 /* PF */ 3311 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3312 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3313 (CHIP_MODE_IS_4_PORT(bp) ? 3314 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3315 /* ATTN */ 3316 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3317 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3318 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 3319 (CHIP_MODE_IS_4_PORT(bp) ? 3320 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3321 } 3322 3323 func_init.spq_active = true; 3324 func_init.pf_id = BP_FUNC(bp); 3325 func_init.func_id = BP_FUNC(bp); 3326 func_init.spq_map = bp->spq_mapping; 3327 func_init.spq_prod = bp->spq_prod_idx; 3328 3329 bnx2x_func_init(bp, &func_init); 3330 3331 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 3332 3333 /* 3334 * Congestion management values depend on the link rate 3335 * There is no active link so initial link rate is set to 10 Gbps. 3336 * When the link comes up The congestion management values are 3337 * re-calculated according to the actual link rate. 3338 */ 3339 bp->link_vars.line_speed = SPEED_10000; 3340 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 3341 3342 /* Only the PMF sets the HW */ 3343 if (bp->port.pmf) 3344 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3345 3346 /* init Event Queue - PCI bus guarantees correct endianity*/ 3347 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 3348 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 3349 eq_data.producer = bp->eq_prod; 3350 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 3351 eq_data.sb_id = DEF_SB_ID; 3352 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 3353} 3354 3355static void bnx2x_e1h_disable(struct bnx2x *bp) 3356{ 3357 int port = BP_PORT(bp); 3358 3359 bnx2x_tx_disable(bp); 3360 3361 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 3362} 3363 3364static void bnx2x_e1h_enable(struct bnx2x *bp) 3365{ 3366 int port = BP_PORT(bp); 3367 3368 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 3369 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); 3370 3371 /* Tx queue should be only re-enabled */ 3372 netif_tx_wake_all_queues(bp->dev); 3373 3374 /* 3375 * Should not call netif_carrier_on since it will be called if the link 3376 * is up when checking for link state 3377 */ 3378} 3379 3380#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 3381 3382static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 3383{ 3384 struct eth_stats_info *ether_stat = 3385 &bp->slowpath->drv_info_to_mcp.ether_stat; 3386 struct bnx2x_vlan_mac_obj *mac_obj = 3387 &bp->sp_objs->mac_obj; 3388 int i; 3389 3390 strscpy(ether_stat->version, DRV_MODULE_VERSION, 3391 ETH_STAT_INFO_VERSION_LEN); 3392 3393 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the 3394 * mac_local field in ether_stat struct. The base address is offset by 2 3395 * bytes to account for the field being 8 bytes but a mac address is 3396 * only 6 bytes. Likewise, the stride for the get_n_elements function is 3397 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes 3398 * allocated by the ether_stat struct, so the macs will land in their 3399 * proper positions. 3400 */ 3401 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) 3402 memset(ether_stat->mac_local + i, 0, 3403 sizeof(ether_stat->mac_local[0])); 3404 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, 3405 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 3406 ether_stat->mac_local + MAC_PAD, MAC_PAD, 3407 ETH_ALEN); 3408 ether_stat->mtu_size = bp->dev->mtu; 3409 if (bp->dev->features & NETIF_F_RXCSUM) 3410 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 3411 if (bp->dev->features & NETIF_F_TSO) 3412 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 3413 ether_stat->feature_flags |= bp->common.boot_mode; 3414 3415 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 3416 3417 ether_stat->txq_size = bp->tx_ring_size; 3418 ether_stat->rxq_size = bp->rx_ring_size; 3419 3420#ifdef CONFIG_BNX2X_SRIOV 3421 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; 3422#endif 3423} 3424 3425static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 3426{ 3427 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3428 struct fcoe_stats_info *fcoe_stat = 3429 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 3430 3431 if (!CNIC_LOADED(bp)) 3432 return; 3433 3434 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); 3435 3436 fcoe_stat->qos_priority = 3437 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 3438 3439 /* insert FCoE stats from ramrod response */ 3440 if (!NO_FCOE(bp)) { 3441 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 3442 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3443 tstorm_queue_statistics; 3444 3445 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 3446 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3447 xstorm_queue_statistics; 3448 3449 struct fcoe_statistics_params *fw_fcoe_stat = 3450 &bp->fw_stats_data->fcoe; 3451 3452 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, 3453 fcoe_stat->rx_bytes_lo, 3454 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 3455 3456 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3457 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 3458 fcoe_stat->rx_bytes_lo, 3459 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 3460 3461 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3462 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 3463 fcoe_stat->rx_bytes_lo, 3464 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 3465 3466 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3467 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 3468 fcoe_stat->rx_bytes_lo, 3469 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 3470 3471 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3472 fcoe_stat->rx_frames_lo, 3473 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3474 3475 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3476 fcoe_stat->rx_frames_lo, 3477 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3478 3479 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3480 fcoe_stat->rx_frames_lo, 3481 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3482 3483 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3484 fcoe_stat->rx_frames_lo, 3485 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3486 3487 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, 3488 fcoe_stat->tx_bytes_lo, 3489 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3490 3491 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3492 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3493 fcoe_stat->tx_bytes_lo, 3494 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3495 3496 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3497 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3498 fcoe_stat->tx_bytes_lo, 3499 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3500 3501 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3502 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3503 fcoe_stat->tx_bytes_lo, 3504 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3505 3506 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3507 fcoe_stat->tx_frames_lo, 3508 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3509 3510 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3511 fcoe_stat->tx_frames_lo, 3512 fcoe_q_xstorm_stats->ucast_pkts_sent); 3513 3514 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3515 fcoe_stat->tx_frames_lo, 3516 fcoe_q_xstorm_stats->bcast_pkts_sent); 3517 3518 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3519 fcoe_stat->tx_frames_lo, 3520 fcoe_q_xstorm_stats->mcast_pkts_sent); 3521 } 3522 3523 /* ask L5 driver to add data to the struct */ 3524 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3525} 3526 3527static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3528{ 3529 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3530 struct iscsi_stats_info *iscsi_stat = 3531 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3532 3533 if (!CNIC_LOADED(bp)) 3534 return; 3535 3536 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, 3537 ETH_ALEN); 3538 3539 iscsi_stat->qos_priority = 3540 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3541 3542 /* ask L5 driver to add data to the struct */ 3543 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3544} 3545 3546/* called due to MCP event (on pmf): 3547 * reread new bandwidth configuration 3548 * configure FW 3549 * notify others function about the change 3550 */ 3551static void bnx2x_config_mf_bw(struct bnx2x *bp) 3552{ 3553 /* Workaround for MFW bug. 3554 * MFW is not supposed to generate BW attention in 3555 * single function mode. 3556 */ 3557 if (!IS_MF(bp)) { 3558 DP(BNX2X_MSG_MCP, 3559 "Ignoring MF BW config in single function mode\n"); 3560 return; 3561 } 3562 3563 if (bp->link_vars.link_up) { 3564 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3565 bnx2x_link_sync_notify(bp); 3566 } 3567 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3568} 3569 3570static void bnx2x_set_mf_bw(struct bnx2x *bp) 3571{ 3572 bnx2x_config_mf_bw(bp); 3573 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3574} 3575 3576static void bnx2x_handle_eee_event(struct bnx2x *bp) 3577{ 3578 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); 3579 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); 3580} 3581 3582#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20) 3583#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25) 3584 3585static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3586{ 3587 enum drv_info_opcode op_code; 3588 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3589 bool release = false; 3590 int wait; 3591 3592 /* if drv_info version supported by MFW doesn't match - send NACK */ 3593 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3594 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3595 return; 3596 } 3597 3598 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3599 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3600 3601 /* Must prevent other flows from accessing drv_info_to_mcp */ 3602 mutex_lock(&bp->drv_info_mutex); 3603 3604 memset(&bp->slowpath->drv_info_to_mcp, 0, 3605 sizeof(union drv_info_to_mcp)); 3606 3607 switch (op_code) { 3608 case ETH_STATS_OPCODE: 3609 bnx2x_drv_info_ether_stat(bp); 3610 break; 3611 case FCOE_STATS_OPCODE: 3612 bnx2x_drv_info_fcoe_stat(bp); 3613 break; 3614 case ISCSI_STATS_OPCODE: 3615 bnx2x_drv_info_iscsi_stat(bp); 3616 break; 3617 default: 3618 /* if op code isn't supported - send NACK */ 3619 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3620 goto out; 3621 } 3622 3623 /* if we got drv_info attn from MFW then these fields are defined in 3624 * shmem2 for sure 3625 */ 3626 SHMEM2_WR(bp, drv_info_host_addr_lo, 3627 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3628 SHMEM2_WR(bp, drv_info_host_addr_hi, 3629 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3630 3631 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3632 3633 /* Since possible management wants both this and get_driver_version 3634 * need to wait until management notifies us it finished utilizing 3635 * the buffer. 3636 */ 3637 if (!SHMEM2_HAS(bp, mfw_drv_indication)) { 3638 DP(BNX2X_MSG_MCP, "Management does not support indication\n"); 3639 } else if (!bp->drv_info_mng_owner) { 3640 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); 3641 3642 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) { 3643 u32 indication = SHMEM2_RD(bp, mfw_drv_indication); 3644 3645 /* Management is done; need to clear indication */ 3646 if (indication & bit) { 3647 SHMEM2_WR(bp, mfw_drv_indication, 3648 indication & ~bit); 3649 release = true; 3650 break; 3651 } 3652 3653 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH); 3654 } 3655 } 3656 if (!release) { 3657 DP(BNX2X_MSG_MCP, "Management did not release indication\n"); 3658 bp->drv_info_mng_owner = true; 3659 } 3660 3661out: 3662 mutex_unlock(&bp->drv_info_mutex); 3663} 3664 3665static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format) 3666{ 3667 u8 vals[4]; 3668 int i = 0; 3669 3670 if (bnx2x_format) { 3671 i = sscanf(version, "1.%c%hhd.%hhd.%hhd", 3672 &vals[0], &vals[1], &vals[2], &vals[3]); 3673 if (i > 0) 3674 vals[0] -= '0'; 3675 } else { 3676 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd", 3677 &vals[0], &vals[1], &vals[2], &vals[3]); 3678 } 3679 3680 while (i < 4) 3681 vals[i++] = 0; 3682 3683 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3]; 3684} 3685 3686void bnx2x_update_mng_version(struct bnx2x *bp) 3687{ 3688 u32 iscsiver = DRV_VER_NOT_LOADED; 3689 u32 fcoever = DRV_VER_NOT_LOADED; 3690 u32 ethver = DRV_VER_NOT_LOADED; 3691 int idx = BP_FW_MB_IDX(bp); 3692 u8 *version; 3693 3694 if (!SHMEM2_HAS(bp, func_os_drv_ver)) 3695 return; 3696 3697 mutex_lock(&bp->drv_info_mutex); 3698 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */ 3699 if (bp->drv_info_mng_owner) 3700 goto out; 3701 3702 if (bp->state != BNX2X_STATE_OPEN) 3703 goto out; 3704 3705 /* Parse ethernet driver version */ 3706 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); 3707 if (!CNIC_LOADED(bp)) 3708 goto out; 3709 3710 /* Try getting storage driver version via cnic */ 3711 memset(&bp->slowpath->drv_info_to_mcp, 0, 3712 sizeof(union drv_info_to_mcp)); 3713 bnx2x_drv_info_iscsi_stat(bp); 3714 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; 3715 iscsiver = bnx2x_update_mng_version_utility(version, false); 3716 3717 memset(&bp->slowpath->drv_info_to_mcp, 0, 3718 sizeof(union drv_info_to_mcp)); 3719 bnx2x_drv_info_fcoe_stat(bp); 3720 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; 3721 fcoever = bnx2x_update_mng_version_utility(version, false); 3722 3723out: 3724 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); 3725 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); 3726 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); 3727 3728 mutex_unlock(&bp->drv_info_mutex); 3729 3730 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n", 3731 ethver, iscsiver, fcoever); 3732} 3733 3734void bnx2x_update_mfw_dump(struct bnx2x *bp) 3735{ 3736 u32 drv_ver; 3737 u32 valid_dump; 3738 3739 if (!SHMEM2_HAS(bp, drv_info)) 3740 return; 3741 3742 /* Update Driver load time, possibly broken in y2038 */ 3743 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds()); 3744 3745 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); 3746 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver); 3747 3748 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM)); 3749 3750 /* Check & notify On-Chip dump. */ 3751 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump); 3752 3753 if (valid_dump & FIRST_DUMP_VALID) 3754 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n"); 3755 3756 if (valid_dump & SECOND_DUMP_VALID) 3757 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n"); 3758} 3759 3760static void bnx2x_oem_event(struct bnx2x *bp, u32 event) 3761{ 3762 u32 cmd_ok, cmd_fail; 3763 3764 /* sanity */ 3765 if (event & DRV_STATUS_DCC_EVENT_MASK && 3766 event & DRV_STATUS_OEM_EVENT_MASK) { 3767 BNX2X_ERR("Received simultaneous events %08x\n", event); 3768 return; 3769 } 3770 3771 if (event & DRV_STATUS_DCC_EVENT_MASK) { 3772 cmd_fail = DRV_MSG_CODE_DCC_FAILURE; 3773 cmd_ok = DRV_MSG_CODE_DCC_OK; 3774 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ { 3775 cmd_fail = DRV_MSG_CODE_OEM_FAILURE; 3776 cmd_ok = DRV_MSG_CODE_OEM_OK; 3777 } 3778 3779 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event); 3780 3781 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF | 3782 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) { 3783 /* This is the only place besides the function initialization 3784 * where the bp->flags can change so it is done without any 3785 * locks 3786 */ 3787 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3788 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); 3789 bp->flags |= MF_FUNC_DIS; 3790 3791 bnx2x_e1h_disable(bp); 3792 } else { 3793 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); 3794 bp->flags &= ~MF_FUNC_DIS; 3795 3796 bnx2x_e1h_enable(bp); 3797 } 3798 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF | 3799 DRV_STATUS_OEM_DISABLE_ENABLE_PF); 3800 } 3801 3802 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | 3803 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) { 3804 bnx2x_config_mf_bw(bp); 3805 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | 3806 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION); 3807 } 3808 3809 /* Report results to MCP */ 3810 if (event) 3811 bnx2x_fw_command(bp, cmd_fail, 0); 3812 else 3813 bnx2x_fw_command(bp, cmd_ok, 0); 3814} 3815 3816/* must be called under the spq lock */ 3817static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3818{ 3819 struct eth_spe *next_spe = bp->spq_prod_bd; 3820 3821 if (bp->spq_prod_bd == bp->spq_last_bd) { 3822 bp->spq_prod_bd = bp->spq; 3823 bp->spq_prod_idx = 0; 3824 DP(BNX2X_MSG_SP, "end of spq\n"); 3825 } else { 3826 bp->spq_prod_bd++; 3827 bp->spq_prod_idx++; 3828 } 3829 return next_spe; 3830} 3831 3832/* must be called under the spq lock */ 3833static void bnx2x_sp_prod_update(struct bnx2x *bp) 3834{ 3835 int func = BP_FUNC(bp); 3836 3837 /* 3838 * Make sure that BD data is updated before writing the producer: 3839 * BD data is written to the memory, the producer is read from the 3840 * memory, thus we need a full memory barrier to ensure the ordering. 3841 */ 3842 mb(); 3843 3844 REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3845 bp->spq_prod_idx); 3846} 3847 3848/** 3849 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3850 * 3851 * @cmd: command to check 3852 * @cmd_type: command type 3853 */ 3854static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3855{ 3856 if ((cmd_type == NONE_CONNECTION_TYPE) || 3857 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3858 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3859 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3860 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3861 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3862 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3863 return true; 3864 else 3865 return false; 3866} 3867 3868/** 3869 * bnx2x_sp_post - place a single command on an SP ring 3870 * 3871 * @bp: driver handle 3872 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3873 * @cid: SW CID the command is related to 3874 * @data_hi: command private data address (high 32 bits) 3875 * @data_lo: command private data address (low 32 bits) 3876 * @cmd_type: command type (e.g. NONE, ETH) 3877 * 3878 * SP data is handled as if it's always an address pair, thus data fields are 3879 * not swapped to little endian in upper functions. Instead this function swaps 3880 * data as if it's two u32 fields. 3881 */ 3882int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3883 u32 data_hi, u32 data_lo, int cmd_type) 3884{ 3885 struct eth_spe *spe; 3886 u16 type; 3887 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3888 3889#ifdef BNX2X_STOP_ON_ERROR 3890 if (unlikely(bp->panic)) { 3891 BNX2X_ERR("Can't post SP when there is panic\n"); 3892 return -EIO; 3893 } 3894#endif 3895 3896 spin_lock_bh(&bp->spq_lock); 3897 3898 if (common) { 3899 if (!atomic_read(&bp->eq_spq_left)) { 3900 BNX2X_ERR("BUG! EQ ring full!\n"); 3901 spin_unlock_bh(&bp->spq_lock); 3902 bnx2x_panic(); 3903 return -EBUSY; 3904 } 3905 } else if (!atomic_read(&bp->cq_spq_left)) { 3906 BNX2X_ERR("BUG! SPQ ring full!\n"); 3907 spin_unlock_bh(&bp->spq_lock); 3908 bnx2x_panic(); 3909 return -EBUSY; 3910 } 3911 3912 spe = bnx2x_sp_get_next(bp); 3913 3914 /* CID needs port number to be encoded int it */ 3915 spe->hdr.conn_and_cmd_data = 3916 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3917 HW_CID(bp, cid)); 3918 3919 /* In some cases, type may already contain the func-id 3920 * mainly in SRIOV related use cases, so we add it here only 3921 * if it's not already set. 3922 */ 3923 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) { 3924 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & 3925 SPE_HDR_CONN_TYPE; 3926 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3927 SPE_HDR_FUNCTION_ID); 3928 } else { 3929 type = cmd_type; 3930 } 3931 3932 spe->hdr.type = cpu_to_le16(type); 3933 3934 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3935 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3936 3937 /* 3938 * It's ok if the actual decrement is issued towards the memory 3939 * somewhere between the spin_lock and spin_unlock. Thus no 3940 * more explicit memory barrier is needed. 3941 */ 3942 if (common) 3943 atomic_dec(&bp->eq_spq_left); 3944 else 3945 atomic_dec(&bp->cq_spq_left); 3946 3947 DP(BNX2X_MSG_SP, 3948 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", 3949 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3950 (u32)(U64_LO(bp->spq_mapping) + 3951 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3952 HW_CID(bp, cid), data_hi, data_lo, type, 3953 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3954 3955 bnx2x_sp_prod_update(bp); 3956 spin_unlock_bh(&bp->spq_lock); 3957 return 0; 3958} 3959 3960/* acquire split MCP access lock register */ 3961static int bnx2x_acquire_alr(struct bnx2x *bp) 3962{ 3963 u32 j, val; 3964 int rc = 0; 3965 3966 might_sleep(); 3967 for (j = 0; j < 1000; j++) { 3968 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); 3969 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); 3970 if (val & MCPR_ACCESS_LOCK_LOCK) 3971 break; 3972 3973 usleep_range(5000, 10000); 3974 } 3975 if (!(val & MCPR_ACCESS_LOCK_LOCK)) { 3976 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3977 rc = -EBUSY; 3978 } 3979 3980 return rc; 3981} 3982 3983/* release split MCP access lock register */ 3984static void bnx2x_release_alr(struct bnx2x *bp) 3985{ 3986 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); 3987} 3988 3989#define BNX2X_DEF_SB_ATT_IDX 0x0001 3990#define BNX2X_DEF_SB_IDX 0x0002 3991 3992static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3993{ 3994 struct host_sp_status_block *def_sb = bp->def_status_blk; 3995 u16 rc = 0; 3996 3997 barrier(); /* status block is written to by the chip */ 3998 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3999 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 4000 rc |= BNX2X_DEF_SB_ATT_IDX; 4001 } 4002 4003 if (bp->def_idx != def_sb->sp_sb.running_index) { 4004 bp->def_idx = def_sb->sp_sb.running_index; 4005 rc |= BNX2X_DEF_SB_IDX; 4006 } 4007 4008 /* Do not reorder: indices reading should complete before handling */ 4009 barrier(); 4010 return rc; 4011} 4012 4013/* 4014 * slow path service functions 4015 */ 4016 4017static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 4018{ 4019 int port = BP_PORT(bp); 4020 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4021 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4022 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 4023 NIG_REG_MASK_INTERRUPT_PORT0; 4024 u32 aeu_mask; 4025 u32 nig_mask = 0; 4026 u32 reg_addr; 4027 4028 if (bp->attn_state & asserted) 4029 BNX2X_ERR("IGU ERROR\n"); 4030 4031 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4032 aeu_mask = REG_RD(bp, aeu_addr); 4033 4034 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 4035 aeu_mask, asserted); 4036 aeu_mask &= ~(asserted & 0x3ff); 4037 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4038 4039 REG_WR(bp, aeu_addr, aeu_mask); 4040 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4041 4042 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4043 bp->attn_state |= asserted; 4044 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4045 4046 if (asserted & ATTN_HARD_WIRED_MASK) { 4047 if (asserted & ATTN_NIG_FOR_FUNC) { 4048 4049 bnx2x_acquire_phy_lock(bp); 4050 4051 /* save nig interrupt mask */ 4052 nig_mask = REG_RD(bp, nig_int_mask_addr); 4053 4054 /* If nig_mask is not set, no need to call the update 4055 * function. 4056 */ 4057 if (nig_mask) { 4058 REG_WR(bp, nig_int_mask_addr, 0); 4059 4060 bnx2x_link_attn(bp); 4061 } 4062 4063 /* handle unicore attn? */ 4064 } 4065 if (asserted & ATTN_SW_TIMER_4_FUNC) 4066 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 4067 4068 if (asserted & GPIO_2_FUNC) 4069 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 4070 4071 if (asserted & GPIO_3_FUNC) 4072 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 4073 4074 if (asserted & GPIO_4_FUNC) 4075 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 4076 4077 if (port == 0) { 4078 if (asserted & ATTN_GENERAL_ATTN_1) { 4079 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 4080 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 4081 } 4082 if (asserted & ATTN_GENERAL_ATTN_2) { 4083 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 4084 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 4085 } 4086 if (asserted & ATTN_GENERAL_ATTN_3) { 4087 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 4088 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 4089 } 4090 } else { 4091 if (asserted & ATTN_GENERAL_ATTN_4) { 4092 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 4093 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 4094 } 4095 if (asserted & ATTN_GENERAL_ATTN_5) { 4096 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 4097 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 4098 } 4099 if (asserted & ATTN_GENERAL_ATTN_6) { 4100 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 4101 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 4102 } 4103 } 4104 4105 } /* if hardwired */ 4106 4107 if (bp->common.int_block == INT_BLOCK_HC) 4108 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4109 COMMAND_REG_ATTN_BITS_SET); 4110 else 4111 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 4112 4113 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 4114 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4115 REG_WR(bp, reg_addr, asserted); 4116 4117 /* now set back the mask */ 4118 if (asserted & ATTN_NIG_FOR_FUNC) { 4119 /* Verify that IGU ack through BAR was written before restoring 4120 * NIG mask. This loop should exit after 2-3 iterations max. 4121 */ 4122 if (bp->common.int_block != INT_BLOCK_HC) { 4123 u32 cnt = 0, igu_acked; 4124 do { 4125 igu_acked = REG_RD(bp, 4126 IGU_REG_ATTENTION_ACK_BITS); 4127 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && 4128 (++cnt < MAX_IGU_ATTN_ACK_TO)); 4129 if (!igu_acked) 4130 DP(NETIF_MSG_HW, 4131 "Failed to verify IGU ack on time\n"); 4132 barrier(); 4133 } 4134 REG_WR(bp, nig_int_mask_addr, nig_mask); 4135 bnx2x_release_phy_lock(bp); 4136 } 4137} 4138 4139static void bnx2x_fan_failure(struct bnx2x *bp) 4140{ 4141 int port = BP_PORT(bp); 4142 u32 ext_phy_config; 4143 /* mark the failure */ 4144 ext_phy_config = 4145 SHMEM_RD(bp, 4146 dev_info.port_hw_config[port].external_phy_config); 4147 4148 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 4149 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 4150 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 4151 ext_phy_config); 4152 4153 /* log the failure */ 4154 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" 4155 "Please contact OEM Support for assistance\n"); 4156 4157 /* Schedule device reset (unload) 4158 * This is due to some boards consuming sufficient power when driver is 4159 * up to overheat if fan fails. 4160 */ 4161 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); 4162} 4163 4164static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 4165{ 4166 int port = BP_PORT(bp); 4167 int reg_offset; 4168 u32 val; 4169 4170 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4171 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 4172 4173 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 4174 4175 val = REG_RD(bp, reg_offset); 4176 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 4177 REG_WR(bp, reg_offset, val); 4178 4179 BNX2X_ERR("SPIO5 hw attention\n"); 4180 4181 /* Fan failure attention */ 4182 bnx2x_hw_reset_phy(&bp->link_params); 4183 bnx2x_fan_failure(bp); 4184 } 4185 4186 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 4187 bnx2x_acquire_phy_lock(bp); 4188 bnx2x_handle_module_detect_int(&bp->link_params); 4189 bnx2x_release_phy_lock(bp); 4190 } 4191 4192 if (attn & HW_INTERRUPT_ASSERT_SET_0) { 4193 4194 val = REG_RD(bp, reg_offset); 4195 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0); 4196 REG_WR(bp, reg_offset, val); 4197 4198 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 4199 (u32)(attn & HW_INTERRUPT_ASSERT_SET_0)); 4200 bnx2x_panic(); 4201 } 4202} 4203 4204static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 4205{ 4206 u32 val; 4207 4208 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 4209 4210 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 4211 BNX2X_ERR("DB hw attention 0x%x\n", val); 4212 /* DORQ discard attention */ 4213 if (val & 0x2) 4214 BNX2X_ERR("FATAL error from DORQ\n"); 4215 } 4216 4217 if (attn & HW_INTERRUPT_ASSERT_SET_1) { 4218 4219 int port = BP_PORT(bp); 4220 int reg_offset; 4221 4222 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 4223 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 4224 4225 val = REG_RD(bp, reg_offset); 4226 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1); 4227 REG_WR(bp, reg_offset, val); 4228 4229 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 4230 (u32)(attn & HW_INTERRUPT_ASSERT_SET_1)); 4231 bnx2x_panic(); 4232 } 4233} 4234 4235static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 4236{ 4237 u32 val; 4238 4239 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 4240 4241 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 4242 BNX2X_ERR("CFC hw attention 0x%x\n", val); 4243 /* CFC error attention */ 4244 if (val & 0x2) 4245 BNX2X_ERR("FATAL error from CFC\n"); 4246 } 4247 4248 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 4249 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 4250 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 4251 /* RQ_USDMDP_FIFO_OVERFLOW */ 4252 if (val & 0x18000) 4253 BNX2X_ERR("FATAL error from PXP\n"); 4254 4255 if (!CHIP_IS_E1x(bp)) { 4256 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 4257 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 4258 } 4259 } 4260 4261 if (attn & HW_INTERRUPT_ASSERT_SET_2) { 4262 4263 int port = BP_PORT(bp); 4264 int reg_offset; 4265 4266 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 4267 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 4268 4269 val = REG_RD(bp, reg_offset); 4270 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2); 4271 REG_WR(bp, reg_offset, val); 4272 4273 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 4274 (u32)(attn & HW_INTERRUPT_ASSERT_SET_2)); 4275 bnx2x_panic(); 4276 } 4277} 4278 4279static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 4280{ 4281 u32 val; 4282 4283 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 4284 4285 if (attn & BNX2X_PMF_LINK_ASSERT) { 4286 int func = BP_FUNC(bp); 4287 4288 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 4289 bnx2x_read_mf_cfg(bp); 4290 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 4291 func_mf_config[BP_ABS_FUNC(bp)].config); 4292 val = SHMEM_RD(bp, 4293 func_mb[BP_FW_MB_IDX(bp)].drv_status); 4294 4295 if (val & (DRV_STATUS_DCC_EVENT_MASK | 4296 DRV_STATUS_OEM_EVENT_MASK)) 4297 bnx2x_oem_event(bp, 4298 (val & (DRV_STATUS_DCC_EVENT_MASK | 4299 DRV_STATUS_OEM_EVENT_MASK))); 4300 4301 if (val & DRV_STATUS_SET_MF_BW) 4302 bnx2x_set_mf_bw(bp); 4303 4304 if (val & DRV_STATUS_DRV_INFO_REQ) 4305 bnx2x_handle_drv_info_req(bp); 4306 4307 if (val & DRV_STATUS_VF_DISABLED) 4308 bnx2x_schedule_iov_task(bp, 4309 BNX2X_IOV_HANDLE_FLR); 4310 4311 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 4312 bnx2x_pmf_update(bp); 4313 4314 if (bp->port.pmf && 4315 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 4316 bp->dcbx_enabled > 0) 4317 /* start dcbx state machine */ 4318 bnx2x_dcbx_set_params(bp, 4319 BNX2X_DCBX_STATE_NEG_RECEIVED); 4320 if (val & DRV_STATUS_AFEX_EVENT_MASK) 4321 bnx2x_handle_afex_cmd(bp, 4322 val & DRV_STATUS_AFEX_EVENT_MASK); 4323 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) 4324 bnx2x_handle_eee_event(bp); 4325 4326 if (val & DRV_STATUS_OEM_UPDATE_SVID) 4327 bnx2x_schedule_sp_rtnl(bp, 4328 BNX2X_SP_RTNL_UPDATE_SVID, 0); 4329 4330 if (bp->link_vars.periodic_flags & 4331 PERIODIC_FLAGS_LINK_EVENT) { 4332 /* sync with link */ 4333 bnx2x_acquire_phy_lock(bp); 4334 bp->link_vars.periodic_flags &= 4335 ~PERIODIC_FLAGS_LINK_EVENT; 4336 bnx2x_release_phy_lock(bp); 4337 if (IS_MF(bp)) 4338 bnx2x_link_sync_notify(bp); 4339 bnx2x_link_report(bp); 4340 } 4341 /* Always call it here: bnx2x_link_report() will 4342 * prevent the link indication duplication. 4343 */ 4344 bnx2x__link_status_update(bp); 4345 } else if (attn & BNX2X_MC_ASSERT_BITS) { 4346 4347 BNX2X_ERR("MC assert!\n"); 4348 bnx2x_mc_assert(bp); 4349 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 4350 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 4351 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 4352 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 4353 bnx2x_panic(); 4354 4355 } else if (attn & BNX2X_MCP_ASSERT) { 4356 4357 BNX2X_ERR("MCP assert!\n"); 4358 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 4359 bnx2x_fw_dump(bp); 4360 4361 } else 4362 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 4363 } 4364 4365 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 4366 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 4367 if (attn & BNX2X_GRC_TIMEOUT) { 4368 val = CHIP_IS_E1(bp) ? 0 : 4369 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 4370 BNX2X_ERR("GRC time-out 0x%08x\n", val); 4371 } 4372 if (attn & BNX2X_GRC_RSV) { 4373 val = CHIP_IS_E1(bp) ? 0 : 4374 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 4375 BNX2X_ERR("GRC reserved 0x%08x\n", val); 4376 } 4377 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 4378 } 4379} 4380 4381/* 4382 * Bits map: 4383 * 0-7 - Engine0 load counter. 4384 * 8-15 - Engine1 load counter. 4385 * 16 - Engine0 RESET_IN_PROGRESS bit. 4386 * 17 - Engine1 RESET_IN_PROGRESS bit. 4387 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 4388 * on the engine 4389 * 19 - Engine1 ONE_IS_LOADED. 4390 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 4391 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 4392 * just the one belonging to its engine). 4393 * 4394 */ 4395#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 4396 4397#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 4398#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 4399#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 4400#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 4401#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 4402#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 4403#define BNX2X_GLOBAL_RESET_BIT 0x00040000 4404 4405/* 4406 * Set the GLOBAL_RESET bit. 4407 * 4408 * Should be run under rtnl lock 4409 */ 4410void bnx2x_set_reset_global(struct bnx2x *bp) 4411{ 4412 u32 val; 4413 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4414 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4415 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 4416 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4417} 4418 4419/* 4420 * Clear the GLOBAL_RESET bit. 4421 * 4422 * Should be run under rtnl lock 4423 */ 4424static void bnx2x_clear_reset_global(struct bnx2x *bp) 4425{ 4426 u32 val; 4427 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4428 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4429 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 4430 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4431} 4432 4433/* 4434 * Checks the GLOBAL_RESET bit. 4435 * 4436 * should be run under rtnl lock 4437 */ 4438static bool bnx2x_reset_is_global(struct bnx2x *bp) 4439{ 4440 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4441 4442 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 4443 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 4444} 4445 4446/* 4447 * Clear RESET_IN_PROGRESS bit for the current engine. 4448 * 4449 * Should be run under rtnl lock 4450 */ 4451static void bnx2x_set_reset_done(struct bnx2x *bp) 4452{ 4453 u32 val; 4454 u32 bit = BP_PATH(bp) ? 4455 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4456 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4457 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4458 4459 /* Clear the bit */ 4460 val &= ~bit; 4461 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4462 4463 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4464} 4465 4466/* 4467 * Set RESET_IN_PROGRESS for the current engine. 4468 * 4469 * should be run under rtnl lock 4470 */ 4471void bnx2x_set_reset_in_progress(struct bnx2x *bp) 4472{ 4473 u32 val; 4474 u32 bit = BP_PATH(bp) ? 4475 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4476 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4477 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4478 4479 /* Set the bit */ 4480 val |= bit; 4481 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4482 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4483} 4484 4485/* 4486 * Checks the RESET_IN_PROGRESS bit for the given engine. 4487 * should be run under rtnl lock 4488 */ 4489bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 4490{ 4491 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4492 u32 bit = engine ? 4493 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4494 4495 /* return false if bit is set */ 4496 return (val & bit) ? false : true; 4497} 4498 4499/* 4500 * set pf load for the current pf. 4501 * 4502 * should be run under rtnl lock 4503 */ 4504void bnx2x_set_pf_load(struct bnx2x *bp) 4505{ 4506 u32 val1, val; 4507 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4508 BNX2X_PATH0_LOAD_CNT_MASK; 4509 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4510 BNX2X_PATH0_LOAD_CNT_SHIFT; 4511 4512 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4513 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4514 4515 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); 4516 4517 /* get the current counter value */ 4518 val1 = (val & mask) >> shift; 4519 4520 /* set bit of that PF */ 4521 val1 |= (1 << bp->pf_num); 4522 4523 /* clear the old value */ 4524 val &= ~mask; 4525 4526 /* set the new one */ 4527 val |= ((val1 << shift) & mask); 4528 4529 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4530 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4531} 4532 4533/** 4534 * bnx2x_clear_pf_load - clear pf load mark 4535 * 4536 * @bp: driver handle 4537 * 4538 * Should be run under rtnl lock. 4539 * Decrements the load counter for the current engine. Returns 4540 * whether other functions are still loaded 4541 */ 4542bool bnx2x_clear_pf_load(struct bnx2x *bp) 4543{ 4544 u32 val1, val; 4545 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4546 BNX2X_PATH0_LOAD_CNT_MASK; 4547 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4548 BNX2X_PATH0_LOAD_CNT_SHIFT; 4549 4550 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4551 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4552 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); 4553 4554 /* get the current counter value */ 4555 val1 = (val & mask) >> shift; 4556 4557 /* clear bit of that PF */ 4558 val1 &= ~(1 << bp->pf_num); 4559 4560 /* clear the old value */ 4561 val &= ~mask; 4562 4563 /* set the new one */ 4564 val |= ((val1 << shift) & mask); 4565 4566 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4567 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4568 return val1 != 0; 4569} 4570 4571/* 4572 * Read the load status for the current engine. 4573 * 4574 * should be run under rtnl lock 4575 */ 4576static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 4577{ 4578 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 4579 BNX2X_PATH0_LOAD_CNT_MASK); 4580 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4581 BNX2X_PATH0_LOAD_CNT_SHIFT); 4582 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4583 4584 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); 4585 4586 val = (val & mask) >> shift; 4587 4588 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", 4589 engine, val); 4590 4591 return val != 0; 4592} 4593 4594static void _print_parity(struct bnx2x *bp, u32 reg) 4595{ 4596 pr_cont(" [0x%08x] ", REG_RD(bp, reg)); 4597} 4598 4599static void _print_next_block(int idx, const char *blk) 4600{ 4601 pr_cont("%s%s", idx ? ", " : "", blk); 4602} 4603 4604static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, 4605 int *par_num, bool print) 4606{ 4607 u32 cur_bit; 4608 bool res; 4609 int i; 4610 4611 res = false; 4612 4613 for (i = 0; sig; i++) { 4614 cur_bit = (0x1UL << i); 4615 if (sig & cur_bit) { 4616 res |= true; /* Each bit is real error! */ 4617 4618 if (print) { 4619 switch (cur_bit) { 4620 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 4621 _print_next_block((*par_num)++, "BRB"); 4622 _print_parity(bp, 4623 BRB1_REG_BRB1_PRTY_STS); 4624 break; 4625 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 4626 _print_next_block((*par_num)++, 4627 "PARSER"); 4628 _print_parity(bp, PRS_REG_PRS_PRTY_STS); 4629 break; 4630 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 4631 _print_next_block((*par_num)++, "TSDM"); 4632 _print_parity(bp, 4633 TSDM_REG_TSDM_PRTY_STS); 4634 break; 4635 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 4636 _print_next_block((*par_num)++, 4637 "SEARCHER"); 4638 _print_parity(bp, SRC_REG_SRC_PRTY_STS); 4639 break; 4640 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 4641 _print_next_block((*par_num)++, "TCM"); 4642 _print_parity(bp, TCM_REG_TCM_PRTY_STS); 4643 break; 4644 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 4645 _print_next_block((*par_num)++, 4646 "TSEMI"); 4647 _print_parity(bp, 4648 TSEM_REG_TSEM_PRTY_STS_0); 4649 _print_parity(bp, 4650 TSEM_REG_TSEM_PRTY_STS_1); 4651 break; 4652 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 4653 _print_next_block((*par_num)++, "XPB"); 4654 _print_parity(bp, GRCBASE_XPB + 4655 PB_REG_PB_PRTY_STS); 4656 break; 4657 } 4658 } 4659 4660 /* Clear the bit */ 4661 sig &= ~cur_bit; 4662 } 4663 } 4664 4665 return res; 4666} 4667 4668static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, 4669 int *par_num, bool *global, 4670 bool print) 4671{ 4672 u32 cur_bit; 4673 bool res; 4674 int i; 4675 4676 res = false; 4677 4678 for (i = 0; sig; i++) { 4679 cur_bit = (0x1UL << i); 4680 if (sig & cur_bit) { 4681 res |= true; /* Each bit is real error! */ 4682 switch (cur_bit) { 4683 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 4684 if (print) { 4685 _print_next_block((*par_num)++, "PBF"); 4686 _print_parity(bp, PBF_REG_PBF_PRTY_STS); 4687 } 4688 break; 4689 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 4690 if (print) { 4691 _print_next_block((*par_num)++, "QM"); 4692 _print_parity(bp, QM_REG_QM_PRTY_STS); 4693 } 4694 break; 4695 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 4696 if (print) { 4697 _print_next_block((*par_num)++, "TM"); 4698 _print_parity(bp, TM_REG_TM_PRTY_STS); 4699 } 4700 break; 4701 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 4702 if (print) { 4703 _print_next_block((*par_num)++, "XSDM"); 4704 _print_parity(bp, 4705 XSDM_REG_XSDM_PRTY_STS); 4706 } 4707 break; 4708 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4709 if (print) { 4710 _print_next_block((*par_num)++, "XCM"); 4711 _print_parity(bp, XCM_REG_XCM_PRTY_STS); 4712 } 4713 break; 4714 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4715 if (print) { 4716 _print_next_block((*par_num)++, 4717 "XSEMI"); 4718 _print_parity(bp, 4719 XSEM_REG_XSEM_PRTY_STS_0); 4720 _print_parity(bp, 4721 XSEM_REG_XSEM_PRTY_STS_1); 4722 } 4723 break; 4724 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4725 if (print) { 4726 _print_next_block((*par_num)++, 4727 "DOORBELLQ"); 4728 _print_parity(bp, 4729 DORQ_REG_DORQ_PRTY_STS); 4730 } 4731 break; 4732 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4733 if (print) { 4734 _print_next_block((*par_num)++, "NIG"); 4735 if (CHIP_IS_E1x(bp)) { 4736 _print_parity(bp, 4737 NIG_REG_NIG_PRTY_STS); 4738 } else { 4739 _print_parity(bp, 4740 NIG_REG_NIG_PRTY_STS_0); 4741 _print_parity(bp, 4742 NIG_REG_NIG_PRTY_STS_1); 4743 } 4744 } 4745 break; 4746 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4747 if (print) 4748 _print_next_block((*par_num)++, 4749 "VAUX PCI CORE"); 4750 *global = true; 4751 break; 4752 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4753 if (print) { 4754 _print_next_block((*par_num)++, 4755 "DEBUG"); 4756 _print_parity(bp, DBG_REG_DBG_PRTY_STS); 4757 } 4758 break; 4759 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4760 if (print) { 4761 _print_next_block((*par_num)++, "USDM"); 4762 _print_parity(bp, 4763 USDM_REG_USDM_PRTY_STS); 4764 } 4765 break; 4766 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4767 if (print) { 4768 _print_next_block((*par_num)++, "UCM"); 4769 _print_parity(bp, UCM_REG_UCM_PRTY_STS); 4770 } 4771 break; 4772 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4773 if (print) { 4774 _print_next_block((*par_num)++, 4775 "USEMI"); 4776 _print_parity(bp, 4777 USEM_REG_USEM_PRTY_STS_0); 4778 _print_parity(bp, 4779 USEM_REG_USEM_PRTY_STS_1); 4780 } 4781 break; 4782 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4783 if (print) { 4784 _print_next_block((*par_num)++, "UPB"); 4785 _print_parity(bp, GRCBASE_UPB + 4786 PB_REG_PB_PRTY_STS); 4787 } 4788 break; 4789 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4790 if (print) { 4791 _print_next_block((*par_num)++, "CSDM"); 4792 _print_parity(bp, 4793 CSDM_REG_CSDM_PRTY_STS); 4794 } 4795 break; 4796 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4797 if (print) { 4798 _print_next_block((*par_num)++, "CCM"); 4799 _print_parity(bp, CCM_REG_CCM_PRTY_STS); 4800 } 4801 break; 4802 } 4803 4804 /* Clear the bit */ 4805 sig &= ~cur_bit; 4806 } 4807 } 4808 4809 return res; 4810} 4811 4812static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, 4813 int *par_num, bool print) 4814{ 4815 u32 cur_bit; 4816 bool res; 4817 int i; 4818 4819 res = false; 4820 4821 for (i = 0; sig; i++) { 4822 cur_bit = (0x1UL << i); 4823 if (sig & cur_bit) { 4824 res = true; /* Each bit is real error! */ 4825 if (print) { 4826 switch (cur_bit) { 4827 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4828 _print_next_block((*par_num)++, 4829 "CSEMI"); 4830 _print_parity(bp, 4831 CSEM_REG_CSEM_PRTY_STS_0); 4832 _print_parity(bp, 4833 CSEM_REG_CSEM_PRTY_STS_1); 4834 break; 4835 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4836 _print_next_block((*par_num)++, "PXP"); 4837 _print_parity(bp, PXP_REG_PXP_PRTY_STS); 4838 _print_parity(bp, 4839 PXP2_REG_PXP2_PRTY_STS_0); 4840 _print_parity(bp, 4841 PXP2_REG_PXP2_PRTY_STS_1); 4842 break; 4843 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4844 _print_next_block((*par_num)++, 4845 "PXPPCICLOCKCLIENT"); 4846 break; 4847 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4848 _print_next_block((*par_num)++, "CFC"); 4849 _print_parity(bp, 4850 CFC_REG_CFC_PRTY_STS); 4851 break; 4852 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4853 _print_next_block((*par_num)++, "CDU"); 4854 _print_parity(bp, CDU_REG_CDU_PRTY_STS); 4855 break; 4856 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4857 _print_next_block((*par_num)++, "DMAE"); 4858 _print_parity(bp, 4859 DMAE_REG_DMAE_PRTY_STS); 4860 break; 4861 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4862 _print_next_block((*par_num)++, "IGU"); 4863 if (CHIP_IS_E1x(bp)) 4864 _print_parity(bp, 4865 HC_REG_HC_PRTY_STS); 4866 else 4867 _print_parity(bp, 4868 IGU_REG_IGU_PRTY_STS); 4869 break; 4870 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4871 _print_next_block((*par_num)++, "MISC"); 4872 _print_parity(bp, 4873 MISC_REG_MISC_PRTY_STS); 4874 break; 4875 } 4876 } 4877 4878 /* Clear the bit */ 4879 sig &= ~cur_bit; 4880 } 4881 } 4882 4883 return res; 4884} 4885 4886static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, 4887 int *par_num, bool *global, 4888 bool print) 4889{ 4890 bool res = false; 4891 u32 cur_bit; 4892 int i; 4893 4894 for (i = 0; sig; i++) { 4895 cur_bit = (0x1UL << i); 4896 if (sig & cur_bit) { 4897 switch (cur_bit) { 4898 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4899 if (print) 4900 _print_next_block((*par_num)++, 4901 "MCP ROM"); 4902 *global = true; 4903 res = true; 4904 break; 4905 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4906 if (print) 4907 _print_next_block((*par_num)++, 4908 "MCP UMP RX"); 4909 *global = true; 4910 res = true; 4911 break; 4912 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4913 if (print) 4914 _print_next_block((*par_num)++, 4915 "MCP UMP TX"); 4916 *global = true; 4917 res = true; 4918 break; 4919 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4920 (*par_num)++; 4921 /* clear latched SCPAD PATIRY from MCP */ 4922 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 4923 1UL << 10); 4924 break; 4925 } 4926 4927 /* Clear the bit */ 4928 sig &= ~cur_bit; 4929 } 4930 } 4931 4932 return res; 4933} 4934 4935static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, 4936 int *par_num, bool print) 4937{ 4938 u32 cur_bit; 4939 bool res; 4940 int i; 4941 4942 res = false; 4943 4944 for (i = 0; sig; i++) { 4945 cur_bit = (0x1UL << i); 4946 if (sig & cur_bit) { 4947 res = true; /* Each bit is real error! */ 4948 if (print) { 4949 switch (cur_bit) { 4950 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4951 _print_next_block((*par_num)++, 4952 "PGLUE_B"); 4953 _print_parity(bp, 4954 PGLUE_B_REG_PGLUE_B_PRTY_STS); 4955 break; 4956 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4957 _print_next_block((*par_num)++, "ATC"); 4958 _print_parity(bp, 4959 ATC_REG_ATC_PRTY_STS); 4960 break; 4961 } 4962 } 4963 /* Clear the bit */ 4964 sig &= ~cur_bit; 4965 } 4966 } 4967 4968 return res; 4969} 4970 4971static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4972 u32 *sig) 4973{ 4974 bool res = false; 4975 4976 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4977 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4978 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4979 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4980 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4981 int par_num = 0; 4982 4983 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" 4984 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 4985 sig[0] & HW_PRTY_ASSERT_SET_0, 4986 sig[1] & HW_PRTY_ASSERT_SET_1, 4987 sig[2] & HW_PRTY_ASSERT_SET_2, 4988 sig[3] & HW_PRTY_ASSERT_SET_3, 4989 sig[4] & HW_PRTY_ASSERT_SET_4); 4990 if (print) { 4991 if (((sig[0] & HW_PRTY_ASSERT_SET_0) || 4992 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4993 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4994 (sig[4] & HW_PRTY_ASSERT_SET_4)) || 4995 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) { 4996 netdev_err(bp->dev, 4997 "Parity errors detected in blocks: "); 4998 } else { 4999 print = false; 5000 } 5001 } 5002 res |= bnx2x_check_blocks_with_parity0(bp, 5003 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print); 5004 res |= bnx2x_check_blocks_with_parity1(bp, 5005 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print); 5006 res |= bnx2x_check_blocks_with_parity2(bp, 5007 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print); 5008 res |= bnx2x_check_blocks_with_parity3(bp, 5009 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print); 5010 res |= bnx2x_check_blocks_with_parity4(bp, 5011 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print); 5012 5013 if (print) 5014 pr_cont("\n"); 5015 } 5016 5017 return res; 5018} 5019 5020/** 5021 * bnx2x_chk_parity_attn - checks for parity attentions. 5022 * 5023 * @bp: driver handle 5024 * @global: true if there was a global attention 5025 * @print: show parity attention in syslog 5026 */ 5027bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 5028{ 5029 struct attn_route attn = { {0} }; 5030 int port = BP_PORT(bp); 5031 5032 attn.sig[0] = REG_RD(bp, 5033 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 5034 port*4); 5035 attn.sig[1] = REG_RD(bp, 5036 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 5037 port*4); 5038 attn.sig[2] = REG_RD(bp, 5039 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 5040 port*4); 5041 attn.sig[3] = REG_RD(bp, 5042 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 5043 port*4); 5044 /* Since MCP attentions can't be disabled inside the block, we need to 5045 * read AEU registers to see whether they're currently disabled 5046 */ 5047 attn.sig[3] &= ((REG_RD(bp, 5048 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 5049 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) & 5050 MISC_AEU_ENABLE_MCP_PRTY_BITS) | 5051 ~MISC_AEU_ENABLE_MCP_PRTY_BITS); 5052 5053 if (!CHIP_IS_E1x(bp)) 5054 attn.sig[4] = REG_RD(bp, 5055 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 5056 port*4); 5057 5058 return bnx2x_parity_attn(bp, global, print, attn.sig); 5059} 5060 5061static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 5062{ 5063 u32 val; 5064 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 5065 5066 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 5067 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 5068 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 5069 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 5070 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 5071 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 5072 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 5073 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 5074 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 5075 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 5076 if (val & 5077 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 5078 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 5079 if (val & 5080 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 5081 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 5082 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 5083 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 5084 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 5085 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 5086 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 5087 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 5088 } 5089 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 5090 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 5091 BNX2X_ERR("ATC hw attention 0x%x\n", val); 5092 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 5093 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 5094 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 5095 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 5096 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 5097 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 5098 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 5099 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 5100 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 5101 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 5102 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 5103 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 5104 } 5105 5106 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 5107 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 5108 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 5109 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 5110 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 5111 } 5112} 5113 5114static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 5115{ 5116 struct attn_route attn, *group_mask; 5117 int port = BP_PORT(bp); 5118 int index; 5119 u32 reg_addr; 5120 u32 val; 5121 u32 aeu_mask; 5122 bool global = false; 5123 5124 /* need to take HW lock because MCP or other port might also 5125 try to handle this event */ 5126 bnx2x_acquire_alr(bp); 5127 5128 if (bnx2x_chk_parity_attn(bp, &global, true)) { 5129#ifndef BNX2X_STOP_ON_ERROR 5130 bp->recovery_state = BNX2X_RECOVERY_INIT; 5131 schedule_delayed_work(&bp->sp_rtnl_task, 0); 5132 /* Disable HW interrupts */ 5133 bnx2x_int_disable(bp); 5134 /* In case of parity errors don't handle attentions so that 5135 * other function would "see" parity errors. 5136 */ 5137#else 5138 bnx2x_panic(); 5139#endif 5140 bnx2x_release_alr(bp); 5141 return; 5142 } 5143 5144 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 5145 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 5146 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 5147 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 5148 if (!CHIP_IS_E1x(bp)) 5149 attn.sig[4] = 5150 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 5151 else 5152 attn.sig[4] = 0; 5153 5154 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 5155 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 5156 5157 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5158 if (deasserted & (1 << index)) { 5159 group_mask = &bp->attn_group[index]; 5160 5161 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", 5162 index, 5163 group_mask->sig[0], group_mask->sig[1], 5164 group_mask->sig[2], group_mask->sig[3], 5165 group_mask->sig[4]); 5166 5167 bnx2x_attn_int_deasserted4(bp, 5168 attn.sig[4] & group_mask->sig[4]); 5169 bnx2x_attn_int_deasserted3(bp, 5170 attn.sig[3] & group_mask->sig[3]); 5171 bnx2x_attn_int_deasserted1(bp, 5172 attn.sig[1] & group_mask->sig[1]); 5173 bnx2x_attn_int_deasserted2(bp, 5174 attn.sig[2] & group_mask->sig[2]); 5175 bnx2x_attn_int_deasserted0(bp, 5176 attn.sig[0] & group_mask->sig[0]); 5177 } 5178 } 5179 5180 bnx2x_release_alr(bp); 5181 5182 if (bp->common.int_block == INT_BLOCK_HC) 5183 reg_addr = (HC_REG_COMMAND_REG + port*32 + 5184 COMMAND_REG_ATTN_BITS_CLR); 5185 else 5186 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 5187 5188 val = ~deasserted; 5189 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 5190 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 5191 REG_WR(bp, reg_addr, val); 5192 5193 if (~bp->attn_state & deasserted) 5194 BNX2X_ERR("IGU ERROR\n"); 5195 5196 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 5197 MISC_REG_AEU_MASK_ATTN_FUNC_0; 5198 5199 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 5200 aeu_mask = REG_RD(bp, reg_addr); 5201 5202 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 5203 aeu_mask, deasserted); 5204 aeu_mask |= (deasserted & 0x3ff); 5205 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 5206 5207 REG_WR(bp, reg_addr, aeu_mask); 5208 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 5209 5210 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 5211 bp->attn_state &= ~deasserted; 5212 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 5213} 5214 5215static void bnx2x_attn_int(struct bnx2x *bp) 5216{ 5217 /* read local copy of bits */ 5218 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 5219 attn_bits); 5220 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 5221 attn_bits_ack); 5222 u32 attn_state = bp->attn_state; 5223 5224 /* look for changed bits */ 5225 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 5226 u32 deasserted = ~attn_bits & attn_ack & attn_state; 5227 5228 DP(NETIF_MSG_HW, 5229 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 5230 attn_bits, attn_ack, asserted, deasserted); 5231 5232 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 5233 BNX2X_ERR("BAD attention state\n"); 5234 5235 /* handle bits that were raised */ 5236 if (asserted) 5237 bnx2x_attn_int_asserted(bp, asserted); 5238 5239 if (deasserted) 5240 bnx2x_attn_int_deasserted(bp, deasserted); 5241} 5242 5243void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 5244 u16 index, u8 op, u8 update) 5245{ 5246 u32 igu_addr = bp->igu_base_addr; 5247 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 5248 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 5249 igu_addr); 5250} 5251 5252static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 5253{ 5254 /* No memory barriers */ 5255 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 5256} 5257 5258static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 5259 union event_ring_elem *elem) 5260{ 5261 u8 err = elem->message.error; 5262 5263 if (!bp->cnic_eth_dev.starting_cid || 5264 (cid < bp->cnic_eth_dev.starting_cid && 5265 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 5266 return 1; 5267 5268 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 5269 5270 if (unlikely(err)) { 5271 5272 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 5273 cid); 5274 bnx2x_panic_dump(bp, false); 5275 } 5276 bnx2x_cnic_cfc_comp(bp, cid, err); 5277 return 0; 5278} 5279 5280static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 5281{ 5282 struct bnx2x_mcast_ramrod_params rparam; 5283 int rc; 5284 5285 memset(&rparam, 0, sizeof(rparam)); 5286 5287 rparam.mcast_obj = &bp->mcast_obj; 5288 5289 netif_addr_lock_bh(bp->dev); 5290 5291 /* Clear pending state for the last command */ 5292 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 5293 5294 /* If there are pending mcast commands - send them */ 5295 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 5296 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 5297 if (rc < 0) 5298 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 5299 rc); 5300 } 5301 5302 netif_addr_unlock_bh(bp->dev); 5303} 5304 5305static void bnx2x_handle_classification_eqe(struct bnx2x *bp, 5306 union event_ring_elem *elem) 5307{ 5308 unsigned long ramrod_flags = 0; 5309 int rc = 0; 5310 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo); 5311 u32 cid = echo & BNX2X_SWCID_MASK; 5312 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 5313 5314 /* Always push next commands out, don't wait here */ 5315 __set_bit(RAMROD_CONT, &ramrod_flags); 5316 5317 switch (echo >> BNX2X_SWCID_SHIFT) { 5318 case BNX2X_FILTER_MAC_PENDING: 5319 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); 5320 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) 5321 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 5322 else 5323 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; 5324 5325 break; 5326 case BNX2X_FILTER_VLAN_PENDING: 5327 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n"); 5328 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; 5329 break; 5330 case BNX2X_FILTER_MCAST_PENDING: 5331 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); 5332 /* This is only relevant for 57710 where multicast MACs are 5333 * configured as unicast MACs using the same ramrod. 5334 */ 5335 bnx2x_handle_mcast_eqe(bp); 5336 return; 5337 default: 5338 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); 5339 return; 5340 } 5341 5342 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 5343 5344 if (rc < 0) 5345 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 5346 else if (rc > 0) 5347 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 5348} 5349 5350static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 5351 5352static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 5353{ 5354 netif_addr_lock_bh(bp->dev); 5355 5356 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5357 5358 /* Send rx_mode command again if was requested */ 5359 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 5360 bnx2x_set_storm_rx_mode(bp); 5361 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 5362 &bp->sp_state)) 5363 bnx2x_set_iscsi_eth_rx_mode(bp, true); 5364 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 5365 &bp->sp_state)) 5366 bnx2x_set_iscsi_eth_rx_mode(bp, false); 5367 5368 netif_addr_unlock_bh(bp->dev); 5369} 5370 5371static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, 5372 union event_ring_elem *elem) 5373{ 5374 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { 5375 DP(BNX2X_MSG_SP, 5376 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", 5377 elem->message.data.vif_list_event.func_bit_map); 5378 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, 5379 elem->message.data.vif_list_event.func_bit_map); 5380 } else if (elem->message.data.vif_list_event.echo == 5381 VIF_LIST_RULE_SET) { 5382 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); 5383 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); 5384 } 5385} 5386 5387/* called with rtnl_lock */ 5388static void bnx2x_after_function_update(struct bnx2x *bp) 5389{ 5390 int q, rc; 5391 struct bnx2x_fastpath *fp; 5392 struct bnx2x_queue_state_params queue_params = {NULL}; 5393 struct bnx2x_queue_update_params *q_update_params = 5394 &queue_params.params.update; 5395 5396 /* Send Q update command with afex vlan removal values for all Qs */ 5397 queue_params.cmd = BNX2X_Q_CMD_UPDATE; 5398 5399 /* set silent vlan removal values according to vlan mode */ 5400 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 5401 &q_update_params->update_flags); 5402 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 5403 &q_update_params->update_flags); 5404 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 5405 5406 /* in access mode mark mask and value are 0 to strip all vlans */ 5407 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { 5408 q_update_params->silent_removal_value = 0; 5409 q_update_params->silent_removal_mask = 0; 5410 } else { 5411 q_update_params->silent_removal_value = 5412 (bp->afex_def_vlan_tag & VLAN_VID_MASK); 5413 q_update_params->silent_removal_mask = VLAN_VID_MASK; 5414 } 5415 5416 for_each_eth_queue(bp, q) { 5417 /* Set the appropriate Queue object */ 5418 fp = &bp->fp[q]; 5419 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 5420 5421 /* send the ramrod */ 5422 rc = bnx2x_queue_state_change(bp, &queue_params); 5423 if (rc < 0) 5424 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 5425 q); 5426 } 5427 5428 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { 5429 fp = &bp->fp[FCOE_IDX(bp)]; 5430 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 5431 5432 /* clear pending completion bit */ 5433 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 5434 5435 /* mark latest Q bit */ 5436 smp_mb__before_atomic(); 5437 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 5438 smp_mb__after_atomic(); 5439 5440 /* send Q update ramrod for FCoE Q */ 5441 rc = bnx2x_queue_state_change(bp, &queue_params); 5442 if (rc < 0) 5443 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 5444 q); 5445 } else { 5446 /* If no FCoE ring - ACK MCP now */ 5447 bnx2x_link_report(bp); 5448 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5449 } 5450} 5451 5452static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 5453 struct bnx2x *bp, u32 cid) 5454{ 5455 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 5456 5457 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) 5458 return &bnx2x_fcoe_sp_obj(bp, q_obj); 5459 else 5460 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; 5461} 5462 5463static void bnx2x_eq_int(struct bnx2x *bp) 5464{ 5465 u16 hw_cons, sw_cons, sw_prod; 5466 union event_ring_elem *elem; 5467 u8 echo; 5468 u32 cid; 5469 u8 opcode; 5470 int rc, spqe_cnt = 0; 5471 struct bnx2x_queue_sp_obj *q_obj; 5472 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 5473 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 5474 5475 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 5476 5477 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 5478 * when we get the next-page we need to adjust so the loop 5479 * condition below will be met. The next element is the size of a 5480 * regular element and hence incrementing by 1 5481 */ 5482 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 5483 hw_cons++; 5484 5485 /* This function may never run in parallel with itself for a 5486 * specific bp, thus there is no need in "paired" read memory 5487 * barrier here. 5488 */ 5489 sw_cons = bp->eq_cons; 5490 sw_prod = bp->eq_prod; 5491 5492 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 5493 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 5494 5495 for (; sw_cons != hw_cons; 5496 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 5497 5498 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 5499 5500 rc = bnx2x_iov_eq_sp_event(bp, elem); 5501 if (!rc) { 5502 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", 5503 rc); 5504 goto next_spqe; 5505 } 5506 5507 opcode = elem->message.opcode; 5508 5509 /* handle eq element */ 5510 switch (opcode) { 5511 case EVENT_RING_OPCODE_VF_PF_CHANNEL: 5512 bnx2x_vf_mbx_schedule(bp, 5513 &elem->message.data.vf_pf_event); 5514 continue; 5515 5516 case EVENT_RING_OPCODE_STAT_QUERY: 5517 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS), 5518 "got statistics comp event %d\n", 5519 bp->stats_comp++); 5520 /* nothing to do with stats comp */ 5521 goto next_spqe; 5522 5523 case EVENT_RING_OPCODE_CFC_DEL: 5524 /* handle according to cid range */ 5525 /* 5526 * we may want to verify here that the bp state is 5527 * HALTING 5528 */ 5529 5530 /* elem CID originates from FW; actually LE */ 5531 cid = SW_CID(elem->message.data.cfc_del_event.cid); 5532 5533 DP(BNX2X_MSG_SP, 5534 "got delete ramrod for MULTI[%d]\n", cid); 5535 5536 if (CNIC_LOADED(bp) && 5537 !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 5538 goto next_spqe; 5539 5540 q_obj = bnx2x_cid_to_q_obj(bp, cid); 5541 5542 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 5543 break; 5544 5545 goto next_spqe; 5546 5547 case EVENT_RING_OPCODE_STOP_TRAFFIC: 5548 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); 5549 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 5550 if (f_obj->complete_cmd(bp, f_obj, 5551 BNX2X_F_CMD_TX_STOP)) 5552 break; 5553 goto next_spqe; 5554 5555 case EVENT_RING_OPCODE_START_TRAFFIC: 5556 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); 5557 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 5558 if (f_obj->complete_cmd(bp, f_obj, 5559 BNX2X_F_CMD_TX_START)) 5560 break; 5561 goto next_spqe; 5562 5563 case EVENT_RING_OPCODE_FUNCTION_UPDATE: 5564 echo = elem->message.data.function_update_event.echo; 5565 if (echo == SWITCH_UPDATE) { 5566 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5567 "got FUNC_SWITCH_UPDATE ramrod\n"); 5568 if (f_obj->complete_cmd( 5569 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) 5570 break; 5571 5572 } else { 5573 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE; 5574 5575 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, 5576 "AFEX: ramrod completed FUNCTION_UPDATE\n"); 5577 f_obj->complete_cmd(bp, f_obj, 5578 BNX2X_F_CMD_AFEX_UPDATE); 5579 5580 /* We will perform the Queues update from 5581 * sp_rtnl task as all Queue SP operations 5582 * should run under rtnl_lock. 5583 */ 5584 bnx2x_schedule_sp_rtnl(bp, cmd, 0); 5585 } 5586 5587 goto next_spqe; 5588 5589 case EVENT_RING_OPCODE_AFEX_VIF_LISTS: 5590 f_obj->complete_cmd(bp, f_obj, 5591 BNX2X_F_CMD_AFEX_VIFLISTS); 5592 bnx2x_after_afex_vif_lists(bp, elem); 5593 goto next_spqe; 5594 case EVENT_RING_OPCODE_FUNCTION_START: 5595 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5596 "got FUNC_START ramrod\n"); 5597 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 5598 break; 5599 5600 goto next_spqe; 5601 5602 case EVENT_RING_OPCODE_FUNCTION_STOP: 5603 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5604 "got FUNC_STOP ramrod\n"); 5605 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 5606 break; 5607 5608 goto next_spqe; 5609 5610 case EVENT_RING_OPCODE_SET_TIMESYNC: 5611 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP, 5612 "got set_timesync ramrod completion\n"); 5613 if (f_obj->complete_cmd(bp, f_obj, 5614 BNX2X_F_CMD_SET_TIMESYNC)) 5615 break; 5616 goto next_spqe; 5617 } 5618 5619 switch (opcode | bp->state) { 5620 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5621 BNX2X_STATE_OPEN): 5622 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5623 BNX2X_STATE_OPENING_WAIT4_PORT): 5624 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5625 BNX2X_STATE_CLOSING_WAIT4_HALT): 5626 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 5627 SW_CID(elem->message.data.eth_event.echo)); 5628 rss_raw->clear_pending(rss_raw); 5629 break; 5630 5631 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 5632 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 5633 case (EVENT_RING_OPCODE_SET_MAC | 5634 BNX2X_STATE_CLOSING_WAIT4_HALT): 5635 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5636 BNX2X_STATE_OPEN): 5637 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5638 BNX2X_STATE_DIAG): 5639 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5640 BNX2X_STATE_CLOSING_WAIT4_HALT): 5641 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n"); 5642 bnx2x_handle_classification_eqe(bp, elem); 5643 break; 5644 5645 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5646 BNX2X_STATE_OPEN): 5647 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5648 BNX2X_STATE_DIAG): 5649 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5650 BNX2X_STATE_CLOSING_WAIT4_HALT): 5651 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 5652 bnx2x_handle_mcast_eqe(bp); 5653 break; 5654 5655 case (EVENT_RING_OPCODE_FILTERS_RULES | 5656 BNX2X_STATE_OPEN): 5657 case (EVENT_RING_OPCODE_FILTERS_RULES | 5658 BNX2X_STATE_DIAG): 5659 case (EVENT_RING_OPCODE_FILTERS_RULES | 5660 BNX2X_STATE_CLOSING_WAIT4_HALT): 5661 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 5662 bnx2x_handle_rx_mode_eqe(bp); 5663 break; 5664 default: 5665 /* unknown event log error and continue */ 5666 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 5667 elem->message.opcode, bp->state); 5668 } 5669next_spqe: 5670 spqe_cnt++; 5671 } /* for */ 5672 5673 smp_mb__before_atomic(); 5674 atomic_add(spqe_cnt, &bp->eq_spq_left); 5675 5676 bp->eq_cons = sw_cons; 5677 bp->eq_prod = sw_prod; 5678 /* Make sure that above mem writes were issued towards the memory */ 5679 smp_wmb(); 5680 5681 /* update producer */ 5682 bnx2x_update_eq_prod(bp, bp->eq_prod); 5683} 5684 5685static void bnx2x_sp_task(struct work_struct *work) 5686{ 5687 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 5688 5689 DP(BNX2X_MSG_SP, "sp task invoked\n"); 5690 5691 /* make sure the atomic interrupt_occurred has been written */ 5692 smp_rmb(); 5693 if (atomic_read(&bp->interrupt_occurred)) { 5694 5695 /* what work needs to be performed? */ 5696 u16 status = bnx2x_update_dsb_idx(bp); 5697 5698 DP(BNX2X_MSG_SP, "status %x\n", status); 5699 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); 5700 atomic_set(&bp->interrupt_occurred, 0); 5701 5702 /* HW attentions */ 5703 if (status & BNX2X_DEF_SB_ATT_IDX) { 5704 bnx2x_attn_int(bp); 5705 status &= ~BNX2X_DEF_SB_ATT_IDX; 5706 } 5707 5708 /* SP events: STAT_QUERY and others */ 5709 if (status & BNX2X_DEF_SB_IDX) { 5710 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 5711 5712 if (FCOE_INIT(bp) && 5713 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 5714 /* Prevent local bottom-halves from running as 5715 * we are going to change the local NAPI list. 5716 */ 5717 local_bh_disable(); 5718 napi_schedule(&bnx2x_fcoe(bp, napi)); 5719 local_bh_enable(); 5720 } 5721 5722 /* Handle EQ completions */ 5723 bnx2x_eq_int(bp); 5724 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 5725 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 5726 5727 status &= ~BNX2X_DEF_SB_IDX; 5728 } 5729 5730 /* if status is non zero then perhaps something went wrong */ 5731 if (unlikely(status)) 5732 DP(BNX2X_MSG_SP, 5733 "got an unknown interrupt! (status 0x%x)\n", status); 5734 5735 /* ack status block only if something was actually handled */ 5736 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 5737 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 5738 } 5739 5740 /* afex - poll to check if VIFSET_ACK should be sent to MFW */ 5741 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, 5742 &bp->sp_state)) { 5743 bnx2x_link_report(bp); 5744 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5745 } 5746} 5747 5748irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 5749{ 5750 struct net_device *dev = dev_instance; 5751 struct bnx2x *bp = netdev_priv(dev); 5752 5753 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 5754 IGU_INT_DISABLE, 0); 5755 5756#ifdef BNX2X_STOP_ON_ERROR 5757 if (unlikely(bp->panic)) 5758 return IRQ_HANDLED; 5759#endif 5760 5761 if (CNIC_LOADED(bp)) { 5762 struct cnic_ops *c_ops; 5763 5764 rcu_read_lock(); 5765 c_ops = rcu_dereference(bp->cnic_ops); 5766 if (c_ops) 5767 c_ops->cnic_handler(bp->cnic_data, NULL); 5768 rcu_read_unlock(); 5769 } 5770 5771 /* schedule sp task to perform default status block work, ack 5772 * attentions and enable interrupts. 5773 */ 5774 bnx2x_schedule_sp_task(bp); 5775 5776 return IRQ_HANDLED; 5777} 5778 5779/* end of slow path */ 5780 5781void bnx2x_drv_pulse(struct bnx2x *bp) 5782{ 5783 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 5784 bp->fw_drv_pulse_wr_seq); 5785} 5786 5787static void bnx2x_timer(struct timer_list *t) 5788{ 5789 struct bnx2x *bp = timer_container_of(bp, t, timer); 5790 5791 if (!netif_running(bp->dev)) 5792 return; 5793 5794 if (IS_PF(bp) && 5795 !BP_NOMCP(bp)) { 5796 int mb_idx = BP_FW_MB_IDX(bp); 5797 u16 drv_pulse; 5798 u16 mcp_pulse; 5799 5800 ++bp->fw_drv_pulse_wr_seq; 5801 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 5802 drv_pulse = bp->fw_drv_pulse_wr_seq; 5803 bnx2x_drv_pulse(bp); 5804 5805 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 5806 MCP_PULSE_SEQ_MASK); 5807 /* The delta between driver pulse and mcp response 5808 * should not get too big. If the MFW is more than 5 pulses 5809 * behind, we should worry about it enough to generate an error 5810 * log. 5811 */ 5812 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5) 5813 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 5814 drv_pulse, mcp_pulse); 5815 } 5816 5817 if (bp->state == BNX2X_STATE_OPEN) 5818 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 5819 5820 /* sample pf vf bulletin board for new posts from pf */ 5821 if (IS_VF(bp)) 5822 bnx2x_timer_sriov(bp); 5823 5824 mod_timer(&bp->timer, jiffies + bp->current_interval); 5825} 5826 5827/* end of Statistics */ 5828 5829/* nic init */ 5830 5831/* 5832 * nic init service functions 5833 */ 5834 5835static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 5836{ 5837 u32 i; 5838 if (!(len%4) && !(addr%4)) 5839 for (i = 0; i < len; i += 4) 5840 REG_WR(bp, addr + i, fill); 5841 else 5842 for (i = 0; i < len; i++) 5843 REG_WR8(bp, addr + i, fill); 5844} 5845 5846/* helper: writes FP SP data to FW - data_size in dwords */ 5847static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 5848 int fw_sb_id, 5849 u32 *sb_data_p, 5850 u32 data_size) 5851{ 5852 int index; 5853 for (index = 0; index < data_size; index++) 5854 REG_WR(bp, BAR_CSTRORM_INTMEM + 5855 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 5856 sizeof(u32)*index, 5857 *(sb_data_p + index)); 5858} 5859 5860static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 5861{ 5862 u32 *sb_data_p; 5863 u32 data_size = 0; 5864 struct hc_status_block_data_e2 sb_data_e2; 5865 struct hc_status_block_data_e1x sb_data_e1x; 5866 5867 /* disable the function first */ 5868 if (!CHIP_IS_E1x(bp)) { 5869 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5870 sb_data_e2.common.state = SB_DISABLED; 5871 sb_data_e2.common.p_func.vf_valid = false; 5872 sb_data_p = (u32 *)&sb_data_e2; 5873 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5874 } else { 5875 memset(&sb_data_e1x, 0, 5876 sizeof(struct hc_status_block_data_e1x)); 5877 sb_data_e1x.common.state = SB_DISABLED; 5878 sb_data_e1x.common.p_func.vf_valid = false; 5879 sb_data_p = (u32 *)&sb_data_e1x; 5880 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5881 } 5882 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5883 5884 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5885 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 5886 CSTORM_STATUS_BLOCK_SIZE); 5887 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5888 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 5889 CSTORM_SYNC_BLOCK_SIZE); 5890} 5891 5892/* helper: writes SP SB data to FW */ 5893static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 5894 struct hc_sp_status_block_data *sp_sb_data) 5895{ 5896 int func = BP_FUNC(bp); 5897 int i; 5898 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 5899 REG_WR(bp, BAR_CSTRORM_INTMEM + 5900 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 5901 i*sizeof(u32), 5902 *((u32 *)sp_sb_data + i)); 5903} 5904 5905static void bnx2x_zero_sp_sb(struct bnx2x *bp) 5906{ 5907 int func = BP_FUNC(bp); 5908 struct hc_sp_status_block_data sp_sb_data; 5909 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5910 5911 sp_sb_data.state = SB_DISABLED; 5912 sp_sb_data.p_func.vf_valid = false; 5913 5914 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5915 5916 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5917 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 5918 CSTORM_SP_STATUS_BLOCK_SIZE); 5919 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5920 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 5921 CSTORM_SP_SYNC_BLOCK_SIZE); 5922} 5923 5924static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 5925 int igu_sb_id, int igu_seg_id) 5926{ 5927 hc_sm->igu_sb_id = igu_sb_id; 5928 hc_sm->igu_seg_id = igu_seg_id; 5929 hc_sm->timer_value = 0xFF; 5930 hc_sm->time_to_expire = 0xFFFFFFFF; 5931} 5932 5933/* allocates state machine ids. */ 5934static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5935{ 5936 /* zero out state machine indices */ 5937 /* rx indices */ 5938 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5939 5940 /* tx indices */ 5941 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5942 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5943 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5944 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5945 5946 /* map indices */ 5947 /* rx indices */ 5948 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5949 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5950 5951 /* tx indices */ 5952 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5953 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5954 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5955 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5956 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5957 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5958 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5959 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5960} 5961 5962void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5963 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5964{ 5965 int igu_seg_id; 5966 5967 struct hc_status_block_data_e2 sb_data_e2; 5968 struct hc_status_block_data_e1x sb_data_e1x; 5969 struct hc_status_block_sm *hc_sm_p; 5970 int data_size; 5971 u32 *sb_data_p; 5972 5973 if (CHIP_INT_MODE_IS_BC(bp)) 5974 igu_seg_id = HC_SEG_ACCESS_NORM; 5975 else 5976 igu_seg_id = IGU_SEG_ACCESS_NORM; 5977 5978 bnx2x_zero_fp_sb(bp, fw_sb_id); 5979 5980 if (!CHIP_IS_E1x(bp)) { 5981 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5982 sb_data_e2.common.state = SB_ENABLED; 5983 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5984 sb_data_e2.common.p_func.vf_id = vfid; 5985 sb_data_e2.common.p_func.vf_valid = vf_valid; 5986 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5987 sb_data_e2.common.same_igu_sb_1b = true; 5988 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5989 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5990 hc_sm_p = sb_data_e2.common.state_machine; 5991 sb_data_p = (u32 *)&sb_data_e2; 5992 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5993 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5994 } else { 5995 memset(&sb_data_e1x, 0, 5996 sizeof(struct hc_status_block_data_e1x)); 5997 sb_data_e1x.common.state = SB_ENABLED; 5998 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5999 sb_data_e1x.common.p_func.vf_id = 0xff; 6000 sb_data_e1x.common.p_func.vf_valid = false; 6001 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 6002 sb_data_e1x.common.same_igu_sb_1b = true; 6003 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 6004 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 6005 hc_sm_p = sb_data_e1x.common.state_machine; 6006 sb_data_p = (u32 *)&sb_data_e1x; 6007 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 6008 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 6009 } 6010 6011 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 6012 igu_sb_id, igu_seg_id); 6013 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 6014 igu_sb_id, igu_seg_id); 6015 6016 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); 6017 6018 /* write indices to HW - PCI guarantees endianity of regpairs */ 6019 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 6020} 6021 6022static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 6023 u16 tx_usec, u16 rx_usec) 6024{ 6025 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 6026 false, rx_usec); 6027 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 6028 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 6029 tx_usec); 6030 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 6031 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 6032 tx_usec); 6033 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 6034 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 6035 tx_usec); 6036} 6037 6038static void bnx2x_init_def_sb(struct bnx2x *bp) 6039{ 6040 struct host_sp_status_block *def_sb = bp->def_status_blk; 6041 dma_addr_t mapping = bp->def_status_blk_mapping; 6042 int igu_sp_sb_index; 6043 int igu_seg_id; 6044 int port = BP_PORT(bp); 6045 int func = BP_FUNC(bp); 6046 int reg_offset, reg_offset_en5; 6047 u64 section; 6048 int index; 6049 struct hc_sp_status_block_data sp_sb_data; 6050 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 6051 6052 if (CHIP_INT_MODE_IS_BC(bp)) { 6053 igu_sp_sb_index = DEF_SB_IGU_ID; 6054 igu_seg_id = HC_SEG_ACCESS_DEF; 6055 } else { 6056 igu_sp_sb_index = bp->igu_dsb_id; 6057 igu_seg_id = IGU_SEG_ACCESS_DEF; 6058 } 6059 6060 /* ATTN */ 6061 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 6062 atten_status_block); 6063 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 6064 6065 bp->attn_state = 0; 6066 6067 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6068 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6069 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 6070 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 6071 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 6072 int sindex; 6073 /* take care of sig[0]..sig[4] */ 6074 for (sindex = 0; sindex < 4; sindex++) 6075 bp->attn_group[index].sig[sindex] = 6076 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 6077 6078 if (!CHIP_IS_E1x(bp)) 6079 /* 6080 * enable5 is separate from the rest of the registers, 6081 * and therefore the address skip is 4 6082 * and not 16 between the different groups 6083 */ 6084 bp->attn_group[index].sig[4] = REG_RD(bp, 6085 reg_offset_en5 + 0x4*index); 6086 else 6087 bp->attn_group[index].sig[4] = 0; 6088 } 6089 6090 if (bp->common.int_block == INT_BLOCK_HC) { 6091 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 6092 HC_REG_ATTN_MSG0_ADDR_L); 6093 6094 REG_WR(bp, reg_offset, U64_LO(section)); 6095 REG_WR(bp, reg_offset + 4, U64_HI(section)); 6096 } else if (!CHIP_IS_E1x(bp)) { 6097 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 6098 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 6099 } 6100 6101 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 6102 sp_sb); 6103 6104 bnx2x_zero_sp_sb(bp); 6105 6106 /* PCI guarantees endianity of regpairs */ 6107 sp_sb_data.state = SB_ENABLED; 6108 sp_sb_data.host_sb_addr.lo = U64_LO(section); 6109 sp_sb_data.host_sb_addr.hi = U64_HI(section); 6110 sp_sb_data.igu_sb_id = igu_sp_sb_index; 6111 sp_sb_data.igu_seg_id = igu_seg_id; 6112 sp_sb_data.p_func.pf_id = func; 6113 sp_sb_data.p_func.vnic_id = BP_VN(bp); 6114 sp_sb_data.p_func.vf_id = 0xff; 6115 6116 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 6117 6118 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 6119} 6120 6121void bnx2x_update_coalesce(struct bnx2x *bp) 6122{ 6123 int i; 6124 6125 for_each_eth_queue(bp, i) 6126 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 6127 bp->tx_ticks, bp->rx_ticks); 6128} 6129 6130static void bnx2x_init_sp_ring(struct bnx2x *bp) 6131{ 6132 spin_lock_init(&bp->spq_lock); 6133 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 6134 6135 bp->spq_prod_idx = 0; 6136 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 6137 bp->spq_prod_bd = bp->spq; 6138 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 6139} 6140 6141static void bnx2x_init_eq_ring(struct bnx2x *bp) 6142{ 6143 int i; 6144 for (i = 1; i <= NUM_EQ_PAGES; i++) { 6145 union event_ring_elem *elem = 6146 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 6147 6148 elem->next_page.addr.hi = 6149 cpu_to_le32(U64_HI(bp->eq_mapping + 6150 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 6151 elem->next_page.addr.lo = 6152 cpu_to_le32(U64_LO(bp->eq_mapping + 6153 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 6154 } 6155 bp->eq_cons = 0; 6156 bp->eq_prod = NUM_EQ_DESC; 6157 bp->eq_cons_sb = BNX2X_EQ_INDEX; 6158 /* we want a warning message before it gets wrought... */ 6159 atomic_set(&bp->eq_spq_left, 6160 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 6161} 6162 6163/* called with netif_addr_lock_bh() */ 6164static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 6165 unsigned long rx_mode_flags, 6166 unsigned long rx_accept_flags, 6167 unsigned long tx_accept_flags, 6168 unsigned long ramrod_flags) 6169{ 6170 struct bnx2x_rx_mode_ramrod_params ramrod_param; 6171 int rc; 6172 6173 memset(&ramrod_param, 0, sizeof(ramrod_param)); 6174 6175 /* Prepare ramrod parameters */ 6176 ramrod_param.cid = 0; 6177 ramrod_param.cl_id = cl_id; 6178 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 6179 ramrod_param.func_id = BP_FUNC(bp); 6180 6181 ramrod_param.pstate = &bp->sp_state; 6182 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 6183 6184 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 6185 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 6186 6187 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 6188 6189 ramrod_param.ramrod_flags = ramrod_flags; 6190 ramrod_param.rx_mode_flags = rx_mode_flags; 6191 6192 ramrod_param.rx_accept_flags = rx_accept_flags; 6193 ramrod_param.tx_accept_flags = tx_accept_flags; 6194 6195 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 6196 if (rc < 0) { 6197 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 6198 return rc; 6199 } 6200 6201 return 0; 6202} 6203 6204static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, 6205 unsigned long *rx_accept_flags, 6206 unsigned long *tx_accept_flags) 6207{ 6208 /* Clear the flags first */ 6209 *rx_accept_flags = 0; 6210 *tx_accept_flags = 0; 6211 6212 switch (rx_mode) { 6213 case BNX2X_RX_MODE_NONE: 6214 /* 6215 * 'drop all' supersedes any accept flags that may have been 6216 * passed to the function. 6217 */ 6218 break; 6219 case BNX2X_RX_MODE_NORMAL: 6220 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 6221 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); 6222 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 6223 6224 /* internal switching mode */ 6225 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 6226 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); 6227 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 6228 6229 if (bp->accept_any_vlan) { 6230 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 6231 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 6232 } 6233 6234 break; 6235 case BNX2X_RX_MODE_ALLMULTI: 6236 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 6237 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 6238 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 6239 6240 /* internal switching mode */ 6241 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 6242 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 6243 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 6244 6245 if (bp->accept_any_vlan) { 6246 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 6247 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 6248 } 6249 6250 break; 6251 case BNX2X_RX_MODE_PROMISC: 6252 /* According to definition of SI mode, iface in promisc mode 6253 * should receive matched and unmatched (in resolution of port) 6254 * unicast packets. 6255 */ 6256 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); 6257 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 6258 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 6259 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 6260 6261 /* internal switching mode */ 6262 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 6263 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 6264 6265 if (IS_MF_SI(bp)) 6266 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); 6267 else 6268 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 6269 6270 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 6271 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 6272 6273 break; 6274 default: 6275 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); 6276 return -EINVAL; 6277 } 6278 6279 return 0; 6280} 6281 6282/* called with netif_addr_lock_bh() */ 6283static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) 6284{ 6285 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 6286 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 6287 int rc; 6288 6289 if (!NO_FCOE(bp)) 6290 /* Configure rx_mode of FCoE Queue */ 6291 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 6292 6293 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, 6294 &tx_accept_flags); 6295 if (rc) 6296 return rc; 6297 6298 __set_bit(RAMROD_RX, &ramrod_flags); 6299 __set_bit(RAMROD_TX, &ramrod_flags); 6300 6301 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, 6302 rx_accept_flags, tx_accept_flags, 6303 ramrod_flags); 6304} 6305 6306static void bnx2x_init_internal_common(struct bnx2x *bp) 6307{ 6308 int i; 6309 6310 /* Zero this manually as its initialization is 6311 currently missing in the initTool */ 6312 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 6313 REG_WR(bp, BAR_USTRORM_INTMEM + 6314 USTORM_AGG_DATA_OFFSET + i * 4, 0); 6315 if (!CHIP_IS_E1x(bp)) { 6316 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 6317 CHIP_INT_MODE_IS_BC(bp) ? 6318 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 6319 } 6320} 6321 6322static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 6323{ 6324 switch (load_code) { 6325 case FW_MSG_CODE_DRV_LOAD_COMMON: 6326 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 6327 bnx2x_init_internal_common(bp); 6328 fallthrough; 6329 6330 case FW_MSG_CODE_DRV_LOAD_PORT: 6331 /* nothing to do */ 6332 fallthrough; 6333 6334 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 6335 /* internal memory per function is 6336 initialized inside bnx2x_pf_init */ 6337 break; 6338 6339 default: 6340 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 6341 break; 6342 } 6343} 6344 6345static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 6346{ 6347 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); 6348} 6349 6350static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 6351{ 6352 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); 6353} 6354 6355static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 6356{ 6357 if (CHIP_IS_E1x(fp->bp)) 6358 return BP_L_ID(fp->bp) + fp->index; 6359 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 6360 return bnx2x_fp_igu_sb_id(fp); 6361} 6362 6363static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 6364{ 6365 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 6366 u8 cos; 6367 unsigned long q_type = 0; 6368 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 6369 fp->rx_queue = fp_idx; 6370 fp->cid = fp_idx; 6371 fp->cl_id = bnx2x_fp_cl_id(fp); 6372 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 6373 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 6374 /* qZone id equals to FW (per path) client id */ 6375 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 6376 6377 /* init shortcut */ 6378 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 6379 6380 /* Setup SB indices */ 6381 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 6382 6383 /* Configure Queue State object */ 6384 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 6385 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 6386 6387 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 6388 6389 /* init tx data */ 6390 for_each_cos_in_tx_queue(fp, cos) { 6391 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], 6392 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), 6393 FP_COS_TO_TXQ(fp, cos, bp), 6394 BNX2X_TX_SB_INDEX_BASE + cos, fp); 6395 cids[cos] = fp->txdata_ptr[cos]->cid; 6396 } 6397 6398 /* nothing more for vf to do here */ 6399 if (IS_VF(bp)) 6400 return; 6401 6402 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 6403 fp->fw_sb_id, fp->igu_sb_id); 6404 bnx2x_update_fpsb_idx(fp); 6405 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, 6406 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 6407 bnx2x_sp_mapping(bp, q_rdata), q_type); 6408 6409 /** 6410 * Configure classification DBs: Always enable Tx switching 6411 */ 6412 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 6413 6414 DP(NETIF_MSG_IFUP, 6415 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 6416 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 6417 fp->igu_sb_id); 6418} 6419 6420static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) 6421{ 6422 int i; 6423 6424 for (i = 1; i <= NUM_TX_RINGS; i++) { 6425 struct eth_tx_next_bd *tx_next_bd = 6426 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; 6427 6428 tx_next_bd->addr_hi = 6429 cpu_to_le32(U64_HI(txdata->tx_desc_mapping + 6430 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 6431 tx_next_bd->addr_lo = 6432 cpu_to_le32(U64_LO(txdata->tx_desc_mapping + 6433 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 6434 } 6435 6436 *txdata->tx_cons_sb = cpu_to_le16(0); 6437 6438 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 6439 txdata->tx_db.data.zero_fill1 = 0; 6440 txdata->tx_db.data.prod = 0; 6441 6442 txdata->tx_pkt_prod = 0; 6443 txdata->tx_pkt_cons = 0; 6444 txdata->tx_bd_prod = 0; 6445 txdata->tx_bd_cons = 0; 6446 txdata->tx_pkt = 0; 6447} 6448 6449static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) 6450{ 6451 int i; 6452 6453 for_each_tx_queue_cnic(bp, i) 6454 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); 6455} 6456 6457static void bnx2x_init_tx_rings(struct bnx2x *bp) 6458{ 6459 int i; 6460 u8 cos; 6461 6462 for_each_eth_queue(bp, i) 6463 for_each_cos_in_tx_queue(&bp->fp[i], cos) 6464 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); 6465} 6466 6467static void bnx2x_init_fcoe_fp(struct bnx2x *bp) 6468{ 6469 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 6470 unsigned long q_type = 0; 6471 6472 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 6473 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 6474 BNX2X_FCOE_ETH_CL_ID_IDX); 6475 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 6476 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 6477 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 6478 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 6479 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 6480 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 6481 fp); 6482 6483 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 6484 6485 /* qZone id equals to FW (per path) client id */ 6486 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 6487 /* init shortcut */ 6488 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 6489 bnx2x_rx_ustorm_prods_offset(fp); 6490 6491 /* Configure Queue State object */ 6492 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 6493 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 6494 6495 /* No multi-CoS for FCoE L2 client */ 6496 BUG_ON(fp->max_cos != 1); 6497 6498 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 6499 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 6500 bnx2x_sp_mapping(bp, q_rdata), q_type); 6501 6502 DP(NETIF_MSG_IFUP, 6503 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 6504 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 6505 fp->igu_sb_id); 6506} 6507 6508void bnx2x_nic_init_cnic(struct bnx2x *bp) 6509{ 6510 if (!NO_FCOE(bp)) 6511 bnx2x_init_fcoe_fp(bp); 6512 6513 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 6514 BNX2X_VF_ID_INVALID, false, 6515 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 6516 6517 /* ensure status block indices were read */ 6518 rmb(); 6519 bnx2x_init_rx_rings_cnic(bp); 6520 bnx2x_init_tx_rings_cnic(bp); 6521 6522 /* flush all */ 6523 mb(); 6524} 6525 6526void bnx2x_pre_irq_nic_init(struct bnx2x *bp) 6527{ 6528 int i; 6529 6530 /* Setup NIC internals and enable interrupts */ 6531 for_each_eth_queue(bp, i) 6532 bnx2x_init_eth_fp(bp, i); 6533 6534 /* ensure status block indices were read */ 6535 rmb(); 6536 bnx2x_init_rx_rings(bp); 6537 bnx2x_init_tx_rings(bp); 6538 6539 if (IS_PF(bp)) { 6540 /* Initialize MOD_ABS interrupts */ 6541 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 6542 bp->common.shmem_base, 6543 bp->common.shmem2_base, BP_PORT(bp)); 6544 6545 /* initialize the default status block and sp ring */ 6546 bnx2x_init_def_sb(bp); 6547 bnx2x_update_dsb_idx(bp); 6548 bnx2x_init_sp_ring(bp); 6549 } else { 6550 bnx2x_memset_stats(bp); 6551 } 6552} 6553 6554void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) 6555{ 6556 bnx2x_init_eq_ring(bp); 6557 bnx2x_init_internal(bp, load_code); 6558 bnx2x_pf_init(bp); 6559 bnx2x_stats_init(bp); 6560 6561 /* flush all before enabling interrupts */ 6562 mb(); 6563 6564 bnx2x_int_enable(bp); 6565 6566 /* Check for SPIO5 */ 6567 bnx2x_attn_int_deasserted0(bp, 6568 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 6569 AEU_INPUTS_ATTN_BITS_SPIO5); 6570} 6571 6572/* gzip service functions */ 6573static int bnx2x_gunzip_init(struct bnx2x *bp) 6574{ 6575 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 6576 &bp->gunzip_mapping, GFP_KERNEL); 6577 if (bp->gunzip_buf == NULL) 6578 goto gunzip_nomem1; 6579 6580 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 6581 if (bp->strm == NULL) 6582 goto gunzip_nomem2; 6583 6584 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 6585 if (bp->strm->workspace == NULL) 6586 goto gunzip_nomem3; 6587 6588 return 0; 6589 6590gunzip_nomem3: 6591 kfree(bp->strm); 6592 bp->strm = NULL; 6593 6594gunzip_nomem2: 6595 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6596 bp->gunzip_mapping); 6597 bp->gunzip_buf = NULL; 6598 6599gunzip_nomem1: 6600 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); 6601 return -ENOMEM; 6602} 6603 6604static void bnx2x_gunzip_end(struct bnx2x *bp) 6605{ 6606 if (bp->strm) { 6607 vfree(bp->strm->workspace); 6608 kfree(bp->strm); 6609 bp->strm = NULL; 6610 } 6611 6612 if (bp->gunzip_buf) { 6613 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6614 bp->gunzip_mapping); 6615 bp->gunzip_buf = NULL; 6616 } 6617} 6618 6619static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 6620{ 6621 int n, rc; 6622 6623 /* check gzip header */ 6624 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 6625 BNX2X_ERR("Bad gzip header\n"); 6626 return -EINVAL; 6627 } 6628 6629 n = 10; 6630 6631#define FNAME 0x8 6632 6633 if (zbuf[3] & FNAME) 6634 while ((zbuf[n++] != 0) && (n < len)); 6635 6636 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 6637 bp->strm->avail_in = len - n; 6638 bp->strm->next_out = bp->gunzip_buf; 6639 bp->strm->avail_out = FW_BUF_SIZE; 6640 6641 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 6642 if (rc != Z_OK) 6643 return rc; 6644 6645 rc = zlib_inflate(bp->strm, Z_FINISH); 6646 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 6647 netdev_err(bp->dev, "Firmware decompression error: %s\n", 6648 bp->strm->msg); 6649 6650 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 6651 if (bp->gunzip_outlen & 0x3) 6652 netdev_err(bp->dev, 6653 "Firmware decompression error: gunzip_outlen (%d) not aligned\n", 6654 bp->gunzip_outlen); 6655 bp->gunzip_outlen >>= 2; 6656 6657 zlib_inflateEnd(bp->strm); 6658 6659 if (rc == Z_STREAM_END) 6660 return 0; 6661 6662 return rc; 6663} 6664 6665/* nic load/unload */ 6666 6667/* 6668 * General service functions 6669 */ 6670 6671/* send a NIG loopback debug packet */ 6672static void bnx2x_lb_pckt(struct bnx2x *bp) 6673{ 6674 u32 wb_write[3]; 6675 6676 /* Ethernet source and destination addresses */ 6677 wb_write[0] = 0x55555555; 6678 wb_write[1] = 0x55555555; 6679 wb_write[2] = 0x20; /* SOP */ 6680 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6681 6682 /* NON-IP protocol */ 6683 wb_write[0] = 0x09000000; 6684 wb_write[1] = 0x55555555; 6685 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 6686 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6687} 6688 6689/* some of the internal memories 6690 * are not directly readable from the driver 6691 * to test them we send debug packets 6692 */ 6693static int bnx2x_int_mem_test(struct bnx2x *bp) 6694{ 6695 int factor; 6696 int count, i; 6697 u32 val = 0; 6698 6699 if (CHIP_REV_IS_FPGA(bp)) 6700 factor = 120; 6701 else if (CHIP_REV_IS_EMUL(bp)) 6702 factor = 200; 6703 else 6704 factor = 1; 6705 6706 /* Disable inputs of parser neighbor blocks */ 6707 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6708 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6709 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6710 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6711 6712 /* Write 0 to parser credits for CFC search request */ 6713 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6714 6715 /* send Ethernet packet */ 6716 bnx2x_lb_pckt(bp); 6717 6718 /* TODO do i reset NIG statistic? */ 6719 /* Wait until NIG register shows 1 packet of size 0x10 */ 6720 count = 1000 * factor; 6721 while (count) { 6722 6723 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6724 val = *bnx2x_sp(bp, wb_data[0]); 6725 if (val == 0x10) 6726 break; 6727 6728 usleep_range(10000, 20000); 6729 count--; 6730 } 6731 if (val != 0x10) { 6732 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6733 return -1; 6734 } 6735 6736 /* Wait until PRS register shows 1 packet */ 6737 count = 1000 * factor; 6738 while (count) { 6739 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6740 if (val == 1) 6741 break; 6742 6743 usleep_range(10000, 20000); 6744 count--; 6745 } 6746 if (val != 0x1) { 6747 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6748 return -2; 6749 } 6750 6751 /* Reset and init BRB, PRS */ 6752 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6753 msleep(50); 6754 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6755 msleep(50); 6756 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6757 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6758 6759 DP(NETIF_MSG_HW, "part2\n"); 6760 6761 /* Disable inputs of parser neighbor blocks */ 6762 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6763 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6764 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6765 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6766 6767 /* Write 0 to parser credits for CFC search request */ 6768 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6769 6770 /* send 10 Ethernet packets */ 6771 for (i = 0; i < 10; i++) 6772 bnx2x_lb_pckt(bp); 6773 6774 /* Wait until NIG register shows 10 + 1 6775 packets of size 11*0x10 = 0xb0 */ 6776 count = 1000 * factor; 6777 while (count) { 6778 6779 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6780 val = *bnx2x_sp(bp, wb_data[0]); 6781 if (val == 0xb0) 6782 break; 6783 6784 usleep_range(10000, 20000); 6785 count--; 6786 } 6787 if (val != 0xb0) { 6788 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6789 return -3; 6790 } 6791 6792 /* Wait until PRS register shows 2 packets */ 6793 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6794 if (val != 2) 6795 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6796 6797 /* Write 1 to parser credits for CFC search request */ 6798 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 6799 6800 /* Wait until PRS register shows 3 packets */ 6801 msleep(10 * factor); 6802 /* Wait until NIG register shows 1 packet of size 0x10 */ 6803 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6804 if (val != 3) 6805 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6806 6807 /* clear NIG EOP FIFO */ 6808 for (i = 0; i < 11; i++) 6809 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 6810 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 6811 if (val != 1) { 6812 BNX2X_ERR("clear of NIG failed\n"); 6813 return -4; 6814 } 6815 6816 /* Reset and init BRB, PRS, NIG */ 6817 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6818 msleep(50); 6819 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6820 msleep(50); 6821 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6822 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6823 if (!CNIC_SUPPORT(bp)) 6824 /* set NIC mode */ 6825 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6826 6827 /* Enable inputs of parser neighbor blocks */ 6828 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 6829 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 6830 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 6831 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 6832 6833 DP(NETIF_MSG_HW, "done\n"); 6834 6835 return 0; /* OK */ 6836} 6837 6838static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 6839{ 6840 u32 val; 6841 6842 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6843 if (!CHIP_IS_E1x(bp)) 6844 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 6845 else 6846 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 6847 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6848 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6849 /* 6850 * mask read length error interrupts in brb for parser 6851 * (parsing unit and 'checksum and crc' unit) 6852 * these errors are legal (PU reads fixed length and CAC can cause 6853 * read length error on truncated packets) 6854 */ 6855 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 6856 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 6857 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 6858 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 6859 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 6860 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 6861/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 6862/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 6863 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 6864 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 6865 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 6866/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 6867/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 6868 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 6869 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 6870 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 6871 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 6872/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 6873/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 6874 6875 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | 6876 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | 6877 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; 6878 if (!CHIP_IS_E1x(bp)) 6879 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | 6880 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; 6881 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); 6882 6883 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 6884 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 6885 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 6886/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 6887 6888 if (!CHIP_IS_E1x(bp)) 6889 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 6890 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 6891 6892 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 6893 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 6894/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 6895 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 6896} 6897 6898static void bnx2x_reset_common(struct bnx2x *bp) 6899{ 6900 u32 val = 0x1400; 6901 6902 /* reset_common */ 6903 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6904 0xd3ffff7f); 6905 6906 if (CHIP_IS_E3(bp)) { 6907 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6908 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6909 } 6910 6911 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 6912} 6913 6914static void bnx2x_setup_dmae(struct bnx2x *bp) 6915{ 6916 bp->dmae_ready = 0; 6917 spin_lock_init(&bp->dmae_lock); 6918} 6919 6920static void bnx2x_init_pxp(struct bnx2x *bp) 6921{ 6922 u16 devctl; 6923 int r_order, w_order; 6924 6925 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); 6926 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 6927 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 6928 if (bp->mrrs == -1) 6929 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 6930 else { 6931 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 6932 r_order = bp->mrrs; 6933 } 6934 6935 bnx2x_init_pxp_arb(bp, r_order, w_order); 6936} 6937 6938static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 6939{ 6940 int is_required; 6941 u32 val; 6942 int port; 6943 6944 if (BP_NOMCP(bp)) 6945 return; 6946 6947 is_required = 0; 6948 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 6949 SHARED_HW_CFG_FAN_FAILURE_MASK; 6950 6951 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 6952 is_required = 1; 6953 6954 /* 6955 * The fan failure mechanism is usually related to the PHY type since 6956 * the power consumption of the board is affected by the PHY. Currently, 6957 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 6958 */ 6959 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 6960 for (port = PORT_0; port < PORT_MAX; port++) { 6961 is_required |= 6962 bnx2x_fan_failure_det_req( 6963 bp, 6964 bp->common.shmem_base, 6965 bp->common.shmem2_base, 6966 port); 6967 } 6968 6969 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 6970 6971 if (is_required == 0) 6972 return; 6973 6974 /* Fan failure is indicated by SPIO 5 */ 6975 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); 6976 6977 /* set to active low mode */ 6978 val = REG_RD(bp, MISC_REG_SPIO_INT); 6979 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); 6980 REG_WR(bp, MISC_REG_SPIO_INT, val); 6981 6982 /* enable interrupt to signal the IGU */ 6983 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6984 val |= MISC_SPIO_SPIO5; 6985 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 6986} 6987 6988void bnx2x_pf_disable(struct bnx2x *bp) 6989{ 6990 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 6991 val &= ~IGU_PF_CONF_FUNC_EN; 6992 6993 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 6994 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6995 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 6996} 6997 6998static void bnx2x__common_init_phy(struct bnx2x *bp) 6999{ 7000 u32 shmem_base[2], shmem2_base[2]; 7001 /* Avoid common init in case MFW supports LFA */ 7002 if (SHMEM2_RD(bp, size) > 7003 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 7004 return; 7005 shmem_base[0] = bp->common.shmem_base; 7006 shmem2_base[0] = bp->common.shmem2_base; 7007 if (!CHIP_IS_E1x(bp)) { 7008 shmem_base[1] = 7009 SHMEM2_RD(bp, other_shmem_base_addr); 7010 shmem2_base[1] = 7011 SHMEM2_RD(bp, other_shmem2_base_addr); 7012 } 7013 bnx2x_acquire_phy_lock(bp); 7014 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 7015 bp->common.chip_id); 7016 bnx2x_release_phy_lock(bp); 7017} 7018 7019static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) 7020{ 7021 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); 7022 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); 7023 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); 7024 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); 7025 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); 7026 7027 /* make sure this value is 0 */ 7028 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 7029 7030 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); 7031 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); 7032 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); 7033 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); 7034} 7035 7036static void bnx2x_set_endianity(struct bnx2x *bp) 7037{ 7038#ifdef __BIG_ENDIAN 7039 bnx2x_config_endianity(bp, 1); 7040#else 7041 bnx2x_config_endianity(bp, 0); 7042#endif 7043} 7044 7045static void bnx2x_reset_endianity(struct bnx2x *bp) 7046{ 7047 bnx2x_config_endianity(bp, 0); 7048} 7049 7050/** 7051 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 7052 * 7053 * @bp: driver handle 7054 */ 7055static int bnx2x_init_hw_common(struct bnx2x *bp) 7056{ 7057 u32 val; 7058 7059 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); 7060 7061 /* 7062 * take the RESET lock to protect undi_unload flow from accessing 7063 * registers while we're resetting the chip 7064 */ 7065 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 7066 7067 bnx2x_reset_common(bp); 7068 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 7069 7070 val = 0xfffc; 7071 if (CHIP_IS_E3(bp)) { 7072 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 7073 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 7074 } 7075 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 7076 7077 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 7078 7079 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 7080 7081 if (!CHIP_IS_E1x(bp)) { 7082 u8 abs_func_id; 7083 7084 /** 7085 * 4-port mode or 2-port mode we need to turn of master-enable 7086 * for everyone, after that, turn it back on for self. 7087 * so, we disregard multi-function or not, and always disable 7088 * for all functions on the given path, this means 0,2,4,6 for 7089 * path 0 and 1,3,5,7 for path 1 7090 */ 7091 for (abs_func_id = BP_PATH(bp); 7092 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 7093 if (abs_func_id == BP_ABS_FUNC(bp)) { 7094 REG_WR(bp, 7095 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 7096 1); 7097 continue; 7098 } 7099 7100 bnx2x_pretend_func(bp, abs_func_id); 7101 /* clear pf enable */ 7102 bnx2x_pf_disable(bp); 7103 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 7104 } 7105 } 7106 7107 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 7108 if (CHIP_IS_E1(bp)) { 7109 /* enable HW interrupt from PXP on USDM overflow 7110 bit 16 on INT_MASK_0 */ 7111 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 7112 } 7113 7114 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 7115 bnx2x_init_pxp(bp); 7116 bnx2x_set_endianity(bp); 7117 bnx2x_ilt_init_page_size(bp, INITOP_SET); 7118 7119 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 7120 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 7121 7122 /* let the HW do it's magic ... */ 7123 msleep(100); 7124 /* finish PXP init */ 7125 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 7126 if (val != 1) { 7127 BNX2X_ERR("PXP2 CFG failed\n"); 7128 return -EBUSY; 7129 } 7130 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 7131 if (val != 1) { 7132 BNX2X_ERR("PXP2 RD_INIT failed\n"); 7133 return -EBUSY; 7134 } 7135 7136 /* Timers bug workaround E2 only. We need to set the entire ILT to 7137 * have entries with value "0" and valid bit on. 7138 * This needs to be done by the first PF that is loaded in a path 7139 * (i.e. common phase) 7140 */ 7141 if (!CHIP_IS_E1x(bp)) { 7142/* In E2 there is a bug in the timers block that can cause function 6 / 7 7143 * (i.e. vnic3) to start even if it is marked as "scan-off". 7144 * This occurs when a different function (func2,3) is being marked 7145 * as "scan-off". Real-life scenario for example: if a driver is being 7146 * load-unloaded while func6,7 are down. This will cause the timer to access 7147 * the ilt, translate to a logical address and send a request to read/write. 7148 * Since the ilt for the function that is down is not valid, this will cause 7149 * a translation error which is unrecoverable. 7150 * The Workaround is intended to make sure that when this happens nothing fatal 7151 * will occur. The workaround: 7152 * 1. First PF driver which loads on a path will: 7153 * a. After taking the chip out of reset, by using pretend, 7154 * it will write "0" to the following registers of 7155 * the other vnics. 7156 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 7157 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 7158 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 7159 * And for itself it will write '1' to 7160 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 7161 * dmae-operations (writing to pram for example.) 7162 * note: can be done for only function 6,7 but cleaner this 7163 * way. 7164 * b. Write zero+valid to the entire ILT. 7165 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 7166 * VNIC3 (of that port). The range allocated will be the 7167 * entire ILT. This is needed to prevent ILT range error. 7168 * 2. Any PF driver load flow: 7169 * a. ILT update with the physical addresses of the allocated 7170 * logical pages. 7171 * b. Wait 20msec. - note that this timeout is needed to make 7172 * sure there are no requests in one of the PXP internal 7173 * queues with "old" ILT addresses. 7174 * c. PF enable in the PGLC. 7175 * d. Clear the was_error of the PF in the PGLC. (could have 7176 * occurred while driver was down) 7177 * e. PF enable in the CFC (WEAK + STRONG) 7178 * f. Timers scan enable 7179 * 3. PF driver unload flow: 7180 * a. Clear the Timers scan_en. 7181 * b. Polling for scan_on=0 for that PF. 7182 * c. Clear the PF enable bit in the PXP. 7183 * d. Clear the PF enable in the CFC (WEAK + STRONG) 7184 * e. Write zero+valid to all ILT entries (The valid bit must 7185 * stay set) 7186 * f. If this is VNIC 3 of a port then also init 7187 * first_timers_ilt_entry to zero and last_timers_ilt_entry 7188 * to the last entry in the ILT. 7189 * 7190 * Notes: 7191 * Currently the PF error in the PGLC is non recoverable. 7192 * In the future the there will be a recovery routine for this error. 7193 * Currently attention is masked. 7194 * Having an MCP lock on the load/unload process does not guarantee that 7195 * there is no Timer disable during Func6/7 enable. This is because the 7196 * Timers scan is currently being cleared by the MCP on FLR. 7197 * Step 2.d can be done only for PF6/7 and the driver can also check if 7198 * there is error before clearing it. But the flow above is simpler and 7199 * more general. 7200 * All ILT entries are written by zero+valid and not just PF6/7 7201 * ILT entries since in the future the ILT entries allocation for 7202 * PF-s might be dynamic. 7203 */ 7204 struct ilt_client_info ilt_cli; 7205 struct bnx2x_ilt ilt; 7206 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7207 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 7208 7209 /* initialize dummy TM client */ 7210 ilt_cli.start = 0; 7211 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7212 ilt_cli.client_num = ILT_CLIENT_TM; 7213 7214 /* Step 1: set zeroes to all ilt page entries with valid bit on 7215 * Step 2: set the timers first/last ilt entry to point 7216 * to the entire range to prevent ILT range error for 3rd/4th 7217 * vnic (this code assumes existence of the vnic) 7218 * 7219 * both steps performed by call to bnx2x_ilt_client_init_op() 7220 * with dummy TM client 7221 * 7222 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 7223 * and his brother are split registers 7224 */ 7225 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 7226 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 7227 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 7228 7229 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 7230 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 7231 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 7232 } 7233 7234 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 7235 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 7236 7237 if (!CHIP_IS_E1x(bp)) { 7238 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 7239 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 7240 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 7241 7242 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 7243 7244 /* let the HW do it's magic ... */ 7245 do { 7246 msleep(200); 7247 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 7248 } while (factor-- && (val != 1)); 7249 7250 if (val != 1) { 7251 BNX2X_ERR("ATC_INIT failed\n"); 7252 return -EBUSY; 7253 } 7254 } 7255 7256 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 7257 7258 bnx2x_iov_init_dmae(bp); 7259 7260 /* clean the DMAE memory */ 7261 bp->dmae_ready = 1; 7262 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 7263 7264 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 7265 7266 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 7267 7268 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 7269 7270 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 7271 7272 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 7273 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 7274 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 7275 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 7276 7277 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 7278 7279 /* QM queues pointers table */ 7280 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 7281 7282 /* soft reset pulse */ 7283 REG_WR(bp, QM_REG_SOFT_RESET, 1); 7284 REG_WR(bp, QM_REG_SOFT_RESET, 0); 7285 7286 if (CNIC_SUPPORT(bp)) 7287 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 7288 7289 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 7290 7291 if (!CHIP_REV_IS_SLOW(bp)) 7292 /* enable hw interrupt from doorbell Q */ 7293 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 7294 7295 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 7296 7297 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 7298 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 7299 7300 if (!CHIP_IS_E1(bp)) 7301 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 7302 7303 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { 7304 if (IS_MF_AFEX(bp)) { 7305 /* configure that VNTag and VLAN headers must be 7306 * received in afex mode 7307 */ 7308 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); 7309 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); 7310 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); 7311 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); 7312 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); 7313 } else { 7314 /* Bit-map indicating which L2 hdrs may appear 7315 * after the basic Ethernet header 7316 */ 7317 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 7318 bp->path_has_ovlan ? 7 : 6); 7319 } 7320 } 7321 7322 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 7323 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 7324 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 7325 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 7326 7327 if (!CHIP_IS_E1x(bp)) { 7328 /* reset VFC memories */ 7329 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 7330 VFC_MEMORIES_RST_REG_CAM_RST | 7331 VFC_MEMORIES_RST_REG_RAM_RST); 7332 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 7333 VFC_MEMORIES_RST_REG_CAM_RST | 7334 VFC_MEMORIES_RST_REG_RAM_RST); 7335 7336 msleep(20); 7337 } 7338 7339 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 7340 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 7341 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 7342 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 7343 7344 /* sync semi rtc */ 7345 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 7346 0x80000000); 7347 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 7348 0x80000000); 7349 7350 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 7351 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 7352 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 7353 7354 if (!CHIP_IS_E1x(bp)) { 7355 if (IS_MF_AFEX(bp)) { 7356 /* configure that VNTag and VLAN headers must be 7357 * sent in afex mode 7358 */ 7359 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); 7360 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); 7361 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); 7362 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); 7363 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); 7364 } else { 7365 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 7366 bp->path_has_ovlan ? 7 : 6); 7367 } 7368 } 7369 7370 REG_WR(bp, SRC_REG_SOFT_RST, 1); 7371 7372 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 7373 7374 if (CNIC_SUPPORT(bp)) { 7375 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 7376 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 7377 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 7378 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 7379 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 7380 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 7381 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 7382 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 7383 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 7384 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 7385 } 7386 REG_WR(bp, SRC_REG_SOFT_RST, 0); 7387 7388 if (sizeof(union cdu_context) != 1024) 7389 /* we currently assume that a context is 1024 bytes */ 7390 dev_alert(&bp->pdev->dev, 7391 "please adjust the size of cdu_context(%ld)\n", 7392 (long)sizeof(union cdu_context)); 7393 7394 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 7395 val = (4 << 24) + (0 << 12) + 1024; 7396 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 7397 7398 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 7399 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 7400 /* enable context validation interrupt from CFC */ 7401 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 7402 7403 /* set the thresholds to prevent CFC/CDU race */ 7404 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 7405 7406 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 7407 7408 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 7409 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 7410 7411 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 7412 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 7413 7414 /* Reset PCIE errors for debug */ 7415 REG_WR(bp, 0x2814, 0xffffffff); 7416 REG_WR(bp, 0x3820, 0xffffffff); 7417 7418 if (!CHIP_IS_E1x(bp)) { 7419 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 7420 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 7421 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 7422 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 7423 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 7424 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 7425 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 7426 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 7427 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 7428 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 7429 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 7430 } 7431 7432 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 7433 if (!CHIP_IS_E1(bp)) { 7434 /* in E3 this done in per-port section */ 7435 if (!CHIP_IS_E3(bp)) 7436 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 7437 } 7438 if (CHIP_IS_E1H(bp)) 7439 /* not applicable for E2 (and above ...) */ 7440 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 7441 7442 if (CHIP_REV_IS_SLOW(bp)) 7443 msleep(200); 7444 7445 /* finish CFC init */ 7446 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 7447 if (val != 1) { 7448 BNX2X_ERR("CFC LL_INIT failed\n"); 7449 return -EBUSY; 7450 } 7451 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 7452 if (val != 1) { 7453 BNX2X_ERR("CFC AC_INIT failed\n"); 7454 return -EBUSY; 7455 } 7456 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 7457 if (val != 1) { 7458 BNX2X_ERR("CFC CAM_INIT failed\n"); 7459 return -EBUSY; 7460 } 7461 REG_WR(bp, CFC_REG_DEBUG0, 0); 7462 7463 if (CHIP_IS_E1(bp)) { 7464 /* read NIG statistic 7465 to see if this is our first up since powerup */ 7466 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 7467 val = *bnx2x_sp(bp, wb_data[0]); 7468 7469 /* do internal memory self test */ 7470 if ((val == 0) && bnx2x_int_mem_test(bp)) { 7471 BNX2X_ERR("internal mem self test failed\n"); 7472 return -EBUSY; 7473 } 7474 } 7475 7476 bnx2x_setup_fan_failure_detection(bp); 7477 7478 /* clear PXP2 attentions */ 7479 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 7480 7481 bnx2x_enable_blocks_attention(bp); 7482 bnx2x_enable_blocks_parity(bp); 7483 7484 if (!BP_NOMCP(bp)) { 7485 if (CHIP_IS_E1x(bp)) 7486 bnx2x__common_init_phy(bp); 7487 } else 7488 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 7489 7490 if (SHMEM2_HAS(bp, netproc_fw_ver)) 7491 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM)); 7492 7493 return 0; 7494} 7495 7496/** 7497 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 7498 * 7499 * @bp: driver handle 7500 */ 7501static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 7502{ 7503 int rc = bnx2x_init_hw_common(bp); 7504 7505 if (rc) 7506 return rc; 7507 7508 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 7509 if (!BP_NOMCP(bp)) 7510 bnx2x__common_init_phy(bp); 7511 7512 return 0; 7513} 7514 7515static int bnx2x_init_hw_port(struct bnx2x *bp) 7516{ 7517 int port = BP_PORT(bp); 7518 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 7519 u32 low, high; 7520 u32 val, reg; 7521 7522 DP(NETIF_MSG_HW, "starting port init port %d\n", port); 7523 7524 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7525 7526 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 7527 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 7528 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 7529 7530 /* Timers bug workaround: disables the pf_master bit in pglue at 7531 * common phase, we need to enable it here before any dmae access are 7532 * attempted. Therefore we manually added the enable-master to the 7533 * port phase (it also happens in the function phase) 7534 */ 7535 if (!CHIP_IS_E1x(bp)) 7536 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 7537 7538 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 7539 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 7540 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 7541 bnx2x_init_block(bp, BLOCK_QM, init_phase); 7542 7543 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 7544 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 7545 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 7546 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 7547 7548 /* QM cid (connection) count */ 7549 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 7550 7551 if (CNIC_SUPPORT(bp)) { 7552 bnx2x_init_block(bp, BLOCK_TM, init_phase); 7553 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 7554 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 7555 } 7556 7557 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 7558 7559 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 7560 7561 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 7562 7563 if (IS_MF(bp)) 7564 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 7565 else if (bp->dev->mtu > 4096) { 7566 if (bp->flags & ONE_PORT_FLAG) 7567 low = 160; 7568 else { 7569 val = bp->dev->mtu; 7570 /* (24*1024 + val*4)/256 */ 7571 low = 96 + (val/64) + 7572 ((val % 64) ? 1 : 0); 7573 } 7574 } else 7575 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 7576 high = low + 56; /* 14*1024/256 */ 7577 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 7578 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 7579 } 7580 7581 if (CHIP_MODE_IS_4_PORT(bp)) 7582 REG_WR(bp, (BP_PORT(bp) ? 7583 BRB1_REG_MAC_GUARANTIED_1 : 7584 BRB1_REG_MAC_GUARANTIED_0), 40); 7585 7586 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 7587 if (CHIP_IS_E3B0(bp)) { 7588 if (IS_MF_AFEX(bp)) { 7589 /* configure headers for AFEX mode */ 7590 REG_WR(bp, BP_PORT(bp) ? 7591 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7592 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); 7593 REG_WR(bp, BP_PORT(bp) ? 7594 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : 7595 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); 7596 REG_WR(bp, BP_PORT(bp) ? 7597 PRS_REG_MUST_HAVE_HDRS_PORT_1 : 7598 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); 7599 } else { 7600 /* Ovlan exists only if we are in multi-function + 7601 * switch-dependent mode, in switch-independent there 7602 * is no ovlan headers 7603 */ 7604 REG_WR(bp, BP_PORT(bp) ? 7605 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7606 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 7607 (bp->path_has_ovlan ? 7 : 6)); 7608 } 7609 } 7610 7611 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 7612 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 7613 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 7614 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 7615 7616 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 7617 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 7618 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 7619 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 7620 7621 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 7622 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 7623 7624 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 7625 7626 if (CHIP_IS_E1x(bp)) { 7627 /* configure PBF to work without PAUSE mtu 9000 */ 7628 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 7629 7630 /* update threshold */ 7631 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 7632 /* update init credit */ 7633 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 7634 7635 /* probe changes */ 7636 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 7637 udelay(50); 7638 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 7639 } 7640 7641 if (CNIC_SUPPORT(bp)) 7642 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 7643 7644 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 7645 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 7646 7647 if (CHIP_IS_E1(bp)) { 7648 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7649 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7650 } 7651 bnx2x_init_block(bp, BLOCK_HC, init_phase); 7652 7653 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 7654 7655 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 7656 /* init aeu_mask_attn_func_0/1: 7657 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use 7658 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF 7659 * bits 4-7 are used for "per vn group attention" */ 7660 val = IS_MF(bp) ? 0xF7 : 0x7; 7661 /* Enable DCBX attention for all but E1 */ 7662 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 7663 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 7664 7665 /* SCPAD_PARITY should NOT trigger close the gates */ 7666 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0; 7667 REG_WR(bp, reg, 7668 REG_RD(bp, reg) & 7669 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); 7670 7671 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0; 7672 REG_WR(bp, reg, 7673 REG_RD(bp, reg) & 7674 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); 7675 7676 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 7677 7678 if (!CHIP_IS_E1x(bp)) { 7679 /* Bit-map indicating which L2 hdrs may appear after the 7680 * basic Ethernet header 7681 */ 7682 if (IS_MF_AFEX(bp)) 7683 REG_WR(bp, BP_PORT(bp) ? 7684 NIG_REG_P1_HDRS_AFTER_BASIC : 7685 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); 7686 else 7687 REG_WR(bp, BP_PORT(bp) ? 7688 NIG_REG_P1_HDRS_AFTER_BASIC : 7689 NIG_REG_P0_HDRS_AFTER_BASIC, 7690 IS_MF_SD(bp) ? 7 : 6); 7691 7692 if (CHIP_IS_E3(bp)) 7693 REG_WR(bp, BP_PORT(bp) ? 7694 NIG_REG_LLH1_MF_MODE : 7695 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 7696 } 7697 if (!CHIP_IS_E3(bp)) 7698 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 7699 7700 if (!CHIP_IS_E1(bp)) { 7701 /* 0x2 disable mf_ov, 0x1 enable */ 7702 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 7703 (IS_MF_SD(bp) ? 0x1 : 0x2)); 7704 7705 if (!CHIP_IS_E1x(bp)) { 7706 val = 0; 7707 switch (bp->mf_mode) { 7708 case MULTI_FUNCTION_SD: 7709 val = 1; 7710 break; 7711 case MULTI_FUNCTION_SI: 7712 case MULTI_FUNCTION_AFEX: 7713 val = 2; 7714 break; 7715 } 7716 7717 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 7718 NIG_REG_LLH0_CLS_TYPE), val); 7719 } 7720 { 7721 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 7722 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 7723 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 7724 } 7725 } 7726 7727 /* If SPIO5 is set to generate interrupts, enable it for this port */ 7728 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 7729 if (val & MISC_SPIO_SPIO5) { 7730 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 7731 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 7732 val = REG_RD(bp, reg_addr); 7733 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 7734 REG_WR(bp, reg_addr, val); 7735 } 7736 7737 if (CHIP_IS_E3B0(bp)) 7738 bp->flags |= PTP_SUPPORTED; 7739 7740 return 0; 7741} 7742 7743static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 7744{ 7745 int reg; 7746 u32 wb_write[2]; 7747 7748 if (CHIP_IS_E1(bp)) 7749 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 7750 else 7751 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 7752 7753 wb_write[0] = ONCHIP_ADDR1(addr); 7754 wb_write[1] = ONCHIP_ADDR2(addr); 7755 REG_WR_DMAE(bp, reg, wb_write, 2); 7756} 7757 7758void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) 7759{ 7760 u32 data, ctl, cnt = 100; 7761 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 7762 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 7763 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 7764 u32 sb_bit = 1 << (idu_sb_id%32); 7765 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; 7766 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 7767 7768 /* Not supported in BC mode */ 7769 if (CHIP_INT_MODE_IS_BC(bp)) 7770 return; 7771 7772 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 7773 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 7774 IGU_REGULAR_CLEANUP_SET | 7775 IGU_REGULAR_BCLEANUP; 7776 7777 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 7778 func_encode << IGU_CTRL_REG_FID_SHIFT | 7779 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 7780 7781 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7782 data, igu_addr_data); 7783 REG_WR(bp, igu_addr_data, data); 7784 barrier(); 7785 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7786 ctl, igu_addr_ctl); 7787 REG_WR(bp, igu_addr_ctl, ctl); 7788 barrier(); 7789 7790 /* wait for clean up to finish */ 7791 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) 7792 msleep(20); 7793 7794 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { 7795 DP(NETIF_MSG_HW, 7796 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", 7797 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 7798 } 7799} 7800 7801static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 7802{ 7803 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 7804} 7805 7806static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 7807{ 7808 u32 i, base = FUNC_ILT_BASE(func); 7809 for (i = base; i < base + ILT_PER_FUNC; i++) 7810 bnx2x_ilt_wr(bp, i, 0); 7811} 7812 7813static void bnx2x_init_searcher(struct bnx2x *bp) 7814{ 7815 int port = BP_PORT(bp); 7816 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 7817 /* T1 hash bits value determines the T1 number of entries */ 7818 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 7819} 7820 7821static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) 7822{ 7823 int rc; 7824 struct bnx2x_func_state_params func_params = {NULL}; 7825 struct bnx2x_func_switch_update_params *switch_update_params = 7826 &func_params.params.switch_update; 7827 7828 /* Prepare parameters for function state transitions */ 7829 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7830 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 7831 7832 func_params.f_obj = &bp->func_obj; 7833 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 7834 7835 /* Function parameters */ 7836 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, 7837 &switch_update_params->changes); 7838 if (suspend) 7839 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, 7840 &switch_update_params->changes); 7841 7842 rc = bnx2x_func_state_change(bp, &func_params); 7843 7844 return rc; 7845} 7846 7847static int bnx2x_reset_nic_mode(struct bnx2x *bp) 7848{ 7849 int rc, i, port = BP_PORT(bp); 7850 int vlan_en = 0, mac_en[NUM_MACS]; 7851 7852 /* Close input from network */ 7853 if (bp->mf_mode == SINGLE_FUNCTION) { 7854 bnx2x_set_rx_filter(&bp->link_params, 0); 7855 } else { 7856 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : 7857 NIG_REG_LLH0_FUNC_EN); 7858 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7859 NIG_REG_LLH0_FUNC_EN, 0); 7860 for (i = 0; i < NUM_MACS; i++) { 7861 mac_en[i] = REG_RD(bp, port ? 7862 (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7863 4 * i) : 7864 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 7865 4 * i)); 7866 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7867 4 * i) : 7868 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); 7869 } 7870 } 7871 7872 /* Close BMC to host */ 7873 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7874 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); 7875 7876 /* Suspend Tx switching to the PF. Completion of this ramrod 7877 * further guarantees that all the packets of that PF / child 7878 * VFs in BRB were processed by the Parser, so it is safe to 7879 * change the NIC_MODE register. 7880 */ 7881 rc = bnx2x_func_switch_update(bp, 1); 7882 if (rc) { 7883 BNX2X_ERR("Can't suspend tx-switching!\n"); 7884 return rc; 7885 } 7886 7887 /* Change NIC_MODE register */ 7888 REG_WR(bp, PRS_REG_NIC_MODE, 0); 7889 7890 /* Open input from network */ 7891 if (bp->mf_mode == SINGLE_FUNCTION) { 7892 bnx2x_set_rx_filter(&bp->link_params, 1); 7893 } else { 7894 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7895 NIG_REG_LLH0_FUNC_EN, vlan_en); 7896 for (i = 0; i < NUM_MACS; i++) { 7897 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7898 4 * i) : 7899 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 7900 mac_en[i]); 7901 } 7902 } 7903 7904 /* Enable BMC to host */ 7905 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7906 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); 7907 7908 /* Resume Tx switching to the PF */ 7909 rc = bnx2x_func_switch_update(bp, 0); 7910 if (rc) { 7911 BNX2X_ERR("Can't resume tx-switching!\n"); 7912 return rc; 7913 } 7914 7915 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 7916 return 0; 7917} 7918 7919int bnx2x_init_hw_func_cnic(struct bnx2x *bp) 7920{ 7921 int rc; 7922 7923 bnx2x_ilt_init_op_cnic(bp, INITOP_SET); 7924 7925 if (CONFIGURE_NIC_MODE(bp)) { 7926 /* Configure searcher as part of function hw init */ 7927 bnx2x_init_searcher(bp); 7928 7929 /* Reset NIC mode */ 7930 rc = bnx2x_reset_nic_mode(bp); 7931 if (rc) 7932 BNX2X_ERR("Can't change NIC mode!\n"); 7933 return rc; 7934 } 7935 7936 return 0; 7937} 7938 7939/* previous driver DMAE transaction may have occurred when pre-boot stage ended 7940 * and boot began, or when kdump kernel was loaded. Either case would invalidate 7941 * the addresses of the transaction, resulting in was-error bit set in the pci 7942 * causing all hw-to-host pcie transactions to timeout. If this happened we want 7943 * to clear the interrupt which detected this from the pglueb and the was done 7944 * bit 7945 */ 7946static void bnx2x_clean_pglue_errors(struct bnx2x *bp) 7947{ 7948 if (!CHIP_IS_E1x(bp)) 7949 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 7950 1 << BP_ABS_FUNC(bp)); 7951} 7952 7953static int bnx2x_init_hw_func(struct bnx2x *bp) 7954{ 7955 int port = BP_PORT(bp); 7956 int func = BP_FUNC(bp); 7957 int init_phase = PHASE_PF0 + func; 7958 struct bnx2x_ilt *ilt = BP_ILT(bp); 7959 u16 cdu_ilt_start; 7960 u32 addr, val; 7961 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 7962 int i, main_mem_width, rc; 7963 7964 DP(NETIF_MSG_HW, "starting func init func %d\n", func); 7965 7966 /* FLR cleanup - hmmm */ 7967 if (!CHIP_IS_E1x(bp)) { 7968 rc = bnx2x_pf_flr_clnup(bp); 7969 if (rc) { 7970 bnx2x_fw_dump(bp); 7971 return rc; 7972 } 7973 } 7974 7975 /* set MSI reconfigure capability */ 7976 if (bp->common.int_block == INT_BLOCK_HC) { 7977 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 7978 val = REG_RD(bp, addr); 7979 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 7980 REG_WR(bp, addr, val); 7981 } 7982 7983 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 7984 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 7985 7986 ilt = BP_ILT(bp); 7987 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7988 7989 if (IS_SRIOV(bp)) 7990 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; 7991 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); 7992 7993 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes 7994 * those of the VFs, so start line should be reset 7995 */ 7996 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7997 for (i = 0; i < L2_ILT_LINES(bp); i++) { 7998 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; 7999 ilt->lines[cdu_ilt_start + i].page_mapping = 8000 bp->context[i].cxt_mapping; 8001 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; 8002 } 8003 8004 bnx2x_ilt_init_op(bp, INITOP_SET); 8005 8006 if (!CONFIGURE_NIC_MODE(bp)) { 8007 bnx2x_init_searcher(bp); 8008 REG_WR(bp, PRS_REG_NIC_MODE, 0); 8009 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 8010 } else { 8011 /* Set NIC mode */ 8012 REG_WR(bp, PRS_REG_NIC_MODE, 1); 8013 DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); 8014 } 8015 8016 if (!CHIP_IS_E1x(bp)) { 8017 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 8018 8019 /* Turn on a single ISR mode in IGU if driver is going to use 8020 * INT#x or MSI 8021 */ 8022 if (!(bp->flags & USING_MSIX_FLAG)) 8023 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 8024 /* 8025 * Timers workaround bug: function init part. 8026 * Need to wait 20msec after initializing ILT, 8027 * needed to make sure there are no requests in 8028 * one of the PXP internal queues with "old" ILT addresses 8029 */ 8030 msleep(20); 8031 /* 8032 * Master enable - Due to WB DMAE writes performed before this 8033 * register is re-initialized as part of the regular function 8034 * init 8035 */ 8036 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 8037 /* Enable the function in IGU */ 8038 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 8039 } 8040 8041 bp->dmae_ready = 1; 8042 8043 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 8044 8045 bnx2x_clean_pglue_errors(bp); 8046 8047 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 8048 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 8049 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 8050 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 8051 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 8052 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 8053 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 8054 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 8055 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 8056 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 8057 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 8058 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 8059 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 8060 8061 if (!CHIP_IS_E1x(bp)) 8062 REG_WR(bp, QM_REG_PF_EN, 1); 8063 8064 if (!CHIP_IS_E1x(bp)) { 8065 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8066 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8067 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8068 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8069 } 8070 bnx2x_init_block(bp, BLOCK_QM, init_phase); 8071 8072 bnx2x_init_block(bp, BLOCK_TM, init_phase); 8073 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 8074 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ 8075 8076 bnx2x_iov_init_dq(bp); 8077 8078 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 8079 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 8080 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 8081 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 8082 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 8083 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 8084 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 8085 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 8086 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 8087 if (!CHIP_IS_E1x(bp)) 8088 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 8089 8090 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 8091 8092 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 8093 8094 if (!CHIP_IS_E1x(bp)) 8095 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 8096 8097 if (IS_MF(bp)) { 8098 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { 8099 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); 8100 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, 8101 bp->mf_ov); 8102 } 8103 } 8104 8105 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 8106 8107 /* HC init per function */ 8108 if (bp->common.int_block == INT_BLOCK_HC) { 8109 if (CHIP_IS_E1H(bp)) { 8110 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 8111 8112 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 8113 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 8114 } 8115 bnx2x_init_block(bp, BLOCK_HC, init_phase); 8116 8117 } else { 8118 int num_segs, sb_idx, prod_offset; 8119 8120 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 8121 8122 if (!CHIP_IS_E1x(bp)) { 8123 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 8124 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 8125 } 8126 8127 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 8128 8129 if (!CHIP_IS_E1x(bp)) { 8130 int dsb_idx = 0; 8131 /** 8132 * Producer memory: 8133 * E2 mode: address 0-135 match to the mapping memory; 8134 * 136 - PF0 default prod; 137 - PF1 default prod; 8135 * 138 - PF2 default prod; 139 - PF3 default prod; 8136 * 140 - PF0 attn prod; 141 - PF1 attn prod; 8137 * 142 - PF2 attn prod; 143 - PF3 attn prod; 8138 * 144-147 reserved. 8139 * 8140 * E1.5 mode - In backward compatible mode; 8141 * for non default SB; each even line in the memory 8142 * holds the U producer and each odd line hold 8143 * the C producer. The first 128 producers are for 8144 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 8145 * producers are for the DSB for each PF. 8146 * Each PF has five segments: (the order inside each 8147 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 8148 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 8149 * 144-147 attn prods; 8150 */ 8151 /* non-default-status-blocks */ 8152 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 8153 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 8154 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 8155 prod_offset = (bp->igu_base_sb + sb_idx) * 8156 num_segs; 8157 8158 for (i = 0; i < num_segs; i++) { 8159 addr = IGU_REG_PROD_CONS_MEMORY + 8160 (prod_offset + i) * 4; 8161 REG_WR(bp, addr, 0); 8162 } 8163 /* send consumer update with value 0 */ 8164 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 8165 USTORM_ID, 0, IGU_INT_NOP, 1); 8166 bnx2x_igu_clear_sb(bp, 8167 bp->igu_base_sb + sb_idx); 8168 } 8169 8170 /* default-status-blocks */ 8171 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 8172 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 8173 8174 if (CHIP_MODE_IS_4_PORT(bp)) 8175 dsb_idx = BP_FUNC(bp); 8176 else 8177 dsb_idx = BP_VN(bp); 8178 8179 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 8180 IGU_BC_BASE_DSB_PROD + dsb_idx : 8181 IGU_NORM_BASE_DSB_PROD + dsb_idx); 8182 8183 /* 8184 * igu prods come in chunks of E1HVN_MAX (4) - 8185 * does not matters what is the current chip mode 8186 */ 8187 for (i = 0; i < (num_segs * E1HVN_MAX); 8188 i += E1HVN_MAX) { 8189 addr = IGU_REG_PROD_CONS_MEMORY + 8190 (prod_offset + i)*4; 8191 REG_WR(bp, addr, 0); 8192 } 8193 /* send consumer update with 0 */ 8194 if (CHIP_INT_MODE_IS_BC(bp)) { 8195 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8196 USTORM_ID, 0, IGU_INT_NOP, 1); 8197 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8198 CSTORM_ID, 0, IGU_INT_NOP, 1); 8199 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8200 XSTORM_ID, 0, IGU_INT_NOP, 1); 8201 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8202 TSTORM_ID, 0, IGU_INT_NOP, 1); 8203 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8204 ATTENTION_ID, 0, IGU_INT_NOP, 1); 8205 } else { 8206 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8207 USTORM_ID, 0, IGU_INT_NOP, 1); 8208 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8209 ATTENTION_ID, 0, IGU_INT_NOP, 1); 8210 } 8211 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 8212 8213 /* !!! These should become driver const once 8214 rf-tool supports split-68 const */ 8215 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 8216 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 8217 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 8218 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 8219 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 8220 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 8221 } 8222 } 8223 8224 /* Reset PCIE errors for debug */ 8225 REG_WR(bp, 0x2114, 0xffffffff); 8226 REG_WR(bp, 0x2120, 0xffffffff); 8227 8228 if (CHIP_IS_E1x(bp)) { 8229 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 8230 main_mem_base = HC_REG_MAIN_MEMORY + 8231 BP_PORT(bp) * (main_mem_size * 4); 8232 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 8233 main_mem_width = 8; 8234 8235 val = REG_RD(bp, main_mem_prty_clr); 8236 if (val) 8237 DP(NETIF_MSG_HW, 8238 "Hmmm... Parity errors in HC block during function init (0x%x)!\n", 8239 val); 8240 8241 /* Clear "false" parity errors in MSI-X table */ 8242 for (i = main_mem_base; 8243 i < main_mem_base + main_mem_size * 4; 8244 i += main_mem_width) { 8245 bnx2x_read_dmae(bp, i, main_mem_width / 4); 8246 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 8247 i, main_mem_width / 4); 8248 } 8249 /* Clear HC parity attention */ 8250 REG_RD(bp, main_mem_prty_clr); 8251 } 8252 8253#ifdef BNX2X_STOP_ON_ERROR 8254 /* Enable STORMs SP logging */ 8255 REG_WR8(bp, BAR_USTRORM_INTMEM + 8256 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8257 REG_WR8(bp, BAR_TSTRORM_INTMEM + 8258 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8259 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8260 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8261 REG_WR8(bp, BAR_XSTRORM_INTMEM + 8262 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8263#endif 8264 8265 bnx2x_phy_probe(&bp->link_params); 8266 8267 return 0; 8268} 8269 8270void bnx2x_free_mem_cnic(struct bnx2x *bp) 8271{ 8272 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); 8273 8274 if (!CHIP_IS_E1x(bp)) 8275 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 8276 sizeof(struct host_hc_status_block_e2)); 8277 else 8278 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 8279 sizeof(struct host_hc_status_block_e1x)); 8280 8281 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 8282} 8283 8284void bnx2x_free_mem(struct bnx2x *bp) 8285{ 8286 int i; 8287 8288 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 8289 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 8290 8291 if (IS_VF(bp)) 8292 return; 8293 8294 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 8295 sizeof(struct host_sp_status_block)); 8296 8297 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 8298 sizeof(struct bnx2x_slowpath)); 8299 8300 for (i = 0; i < L2_ILT_LINES(bp); i++) 8301 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, 8302 bp->context[i].size); 8303 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 8304 8305 BNX2X_FREE(bp->ilt->lines); 8306 8307 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 8308 8309 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 8310 BCM_PAGE_SIZE * NUM_EQ_PAGES); 8311 8312 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 8313 8314 bnx2x_iov_free_mem(bp); 8315} 8316 8317int bnx2x_alloc_mem_cnic(struct bnx2x *bp) 8318{ 8319 if (!CHIP_IS_E1x(bp)) { 8320 /* size = the status block + ramrod buffers */ 8321 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, 8322 sizeof(struct host_hc_status_block_e2)); 8323 if (!bp->cnic_sb.e2_sb) 8324 goto alloc_mem_err; 8325 } else { 8326 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, 8327 sizeof(struct host_hc_status_block_e1x)); 8328 if (!bp->cnic_sb.e1x_sb) 8329 goto alloc_mem_err; 8330 } 8331 8332 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { 8333 /* allocate searcher T2 table, as it wasn't allocated before */ 8334 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); 8335 if (!bp->t2) 8336 goto alloc_mem_err; 8337 } 8338 8339 /* write address to which L5 should insert its values */ 8340 bp->cnic_eth_dev.addr_drv_info_to_mcp = 8341 &bp->slowpath->drv_info_to_mcp; 8342 8343 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) 8344 goto alloc_mem_err; 8345 8346 return 0; 8347 8348alloc_mem_err: 8349 bnx2x_free_mem_cnic(bp); 8350 BNX2X_ERR("Can't allocate memory\n"); 8351 return -ENOMEM; 8352} 8353 8354int bnx2x_alloc_mem(struct bnx2x *bp) 8355{ 8356 int i, allocated, context_size; 8357 8358 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { 8359 /* allocate searcher T2 table */ 8360 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); 8361 if (!bp->t2) 8362 goto alloc_mem_err; 8363 } 8364 8365 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, 8366 sizeof(struct host_sp_status_block)); 8367 if (!bp->def_status_blk) 8368 goto alloc_mem_err; 8369 8370 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, 8371 sizeof(struct bnx2x_slowpath)); 8372 if (!bp->slowpath) 8373 goto alloc_mem_err; 8374 8375 /* Allocate memory for CDU context: 8376 * This memory is allocated separately and not in the generic ILT 8377 * functions because CDU differs in few aspects: 8378 * 1. There are multiple entities allocating memory for context - 8379 * 'regular' driver, CNIC and SRIOV driver. Each separately controls 8380 * its own ILT lines. 8381 * 2. Since CDU page-size is not a single 4KB page (which is the case 8382 * for the other ILT clients), to be efficient we want to support 8383 * allocation of sub-page-size in the last entry. 8384 * 3. Context pointers are used by the driver to pass to FW / update 8385 * the context (for the other ILT clients the pointers are used just to 8386 * free the memory during unload). 8387 */ 8388 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 8389 8390 for (i = 0, allocated = 0; allocated < context_size; i++) { 8391 bp->context[i].size = min(CDU_ILT_PAGE_SZ, 8392 (context_size - allocated)); 8393 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, 8394 bp->context[i].size); 8395 if (!bp->context[i].vcxt) 8396 goto alloc_mem_err; 8397 allocated += bp->context[i].size; 8398 } 8399 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), 8400 GFP_KERNEL); 8401 if (!bp->ilt->lines) 8402 goto alloc_mem_err; 8403 8404 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 8405 goto alloc_mem_err; 8406 8407 if (bnx2x_iov_alloc_mem(bp)) 8408 goto alloc_mem_err; 8409 8410 /* Slow path ring */ 8411 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); 8412 if (!bp->spq) 8413 goto alloc_mem_err; 8414 8415 /* EQ */ 8416 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, 8417 BCM_PAGE_SIZE * NUM_EQ_PAGES); 8418 if (!bp->eq_ring) 8419 goto alloc_mem_err; 8420 8421 return 0; 8422 8423alloc_mem_err: 8424 bnx2x_free_mem(bp); 8425 BNX2X_ERR("Can't allocate memory\n"); 8426 return -ENOMEM; 8427} 8428 8429/* 8430 * Init service functions 8431 */ 8432 8433int bnx2x_set_mac_one(struct bnx2x *bp, const u8 *mac, 8434 struct bnx2x_vlan_mac_obj *obj, bool set, 8435 int mac_type, unsigned long *ramrod_flags) 8436{ 8437 int rc; 8438 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 8439 8440 memset(&ramrod_param, 0, sizeof(ramrod_param)); 8441 8442 /* Fill general parameters */ 8443 ramrod_param.vlan_mac_obj = obj; 8444 ramrod_param.ramrod_flags = *ramrod_flags; 8445 8446 /* Fill a user request section if needed */ 8447 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 8448 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 8449 8450 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 8451 8452 /* Set the command: ADD or DEL */ 8453 if (set) 8454 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 8455 else 8456 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 8457 } 8458 8459 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 8460 8461 if (rc == -EEXIST) { 8462 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); 8463 /* do not treat adding same MAC as error */ 8464 rc = 0; 8465 } else if (rc < 0) 8466 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 8467 8468 return rc; 8469} 8470 8471int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, 8472 struct bnx2x_vlan_mac_obj *obj, bool set, 8473 unsigned long *ramrod_flags) 8474{ 8475 int rc; 8476 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 8477 8478 memset(&ramrod_param, 0, sizeof(ramrod_param)); 8479 8480 /* Fill general parameters */ 8481 ramrod_param.vlan_mac_obj = obj; 8482 ramrod_param.ramrod_flags = *ramrod_flags; 8483 8484 /* Fill a user request section if needed */ 8485 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 8486 ramrod_param.user_req.u.vlan.vlan = vlan; 8487 __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags); 8488 /* Set the command: ADD or DEL */ 8489 if (set) 8490 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 8491 else 8492 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 8493 } 8494 8495 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 8496 8497 if (rc == -EEXIST) { 8498 /* Do not treat adding same vlan as error. */ 8499 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); 8500 rc = 0; 8501 } else if (rc < 0) { 8502 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del")); 8503 } 8504 8505 return rc; 8506} 8507 8508void bnx2x_clear_vlan_info(struct bnx2x *bp) 8509{ 8510 struct bnx2x_vlan_entry *vlan; 8511 8512 /* Mark that hw forgot all entries */ 8513 list_for_each_entry(vlan, &bp->vlan_reg, link) 8514 vlan->hw = false; 8515 8516 bp->vlan_cnt = 0; 8517} 8518 8519static int bnx2x_del_all_vlans(struct bnx2x *bp) 8520{ 8521 struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj; 8522 unsigned long ramrod_flags = 0, vlan_flags = 0; 8523 int rc; 8524 8525 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8526 __set_bit(BNX2X_VLAN, &vlan_flags); 8527 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags); 8528 if (rc) 8529 return rc; 8530 8531 bnx2x_clear_vlan_info(bp); 8532 8533 return 0; 8534} 8535 8536int bnx2x_del_all_macs(struct bnx2x *bp, 8537 struct bnx2x_vlan_mac_obj *mac_obj, 8538 int mac_type, bool wait_for_comp) 8539{ 8540 int rc; 8541 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 8542 8543 /* Wait for completion of requested */ 8544 if (wait_for_comp) 8545 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8546 8547 /* Set the mac type of addresses we want to clear */ 8548 __set_bit(mac_type, &vlan_mac_flags); 8549 8550 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 8551 if (rc < 0) 8552 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 8553 8554 return rc; 8555} 8556 8557int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 8558{ 8559 if (IS_PF(bp)) { 8560 unsigned long ramrod_flags = 0; 8561 8562 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 8563 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8564 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, 8565 &bp->sp_objs->mac_obj, set, 8566 BNX2X_ETH_MAC, &ramrod_flags); 8567 } else { /* vf */ 8568 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, 8569 bp->fp->index, set); 8570 } 8571} 8572 8573int bnx2x_setup_leading(struct bnx2x *bp) 8574{ 8575 if (IS_PF(bp)) 8576 return bnx2x_setup_queue(bp, &bp->fp[0], true); 8577 else /* VF */ 8578 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); 8579} 8580 8581/** 8582 * bnx2x_set_int_mode - configure interrupt mode 8583 * 8584 * @bp: driver handle 8585 * 8586 * In case of MSI-X it will also try to enable MSI-X. 8587 */ 8588int bnx2x_set_int_mode(struct bnx2x *bp) 8589{ 8590 int rc = 0; 8591 8592 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { 8593 BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); 8594 return -EINVAL; 8595 } 8596 8597 switch (int_mode) { 8598 case BNX2X_INT_MODE_MSIX: 8599 /* attempt to enable msix */ 8600 rc = bnx2x_enable_msix(bp); 8601 8602 /* msix attained */ 8603 if (!rc) 8604 return 0; 8605 8606 /* vfs use only msix */ 8607 if (rc && IS_VF(bp)) 8608 return rc; 8609 8610 /* failed to enable multiple MSI-X */ 8611 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", 8612 bp->num_queues, 8613 1 + bp->num_cnic_queues); 8614 8615 fallthrough; 8616 case BNX2X_INT_MODE_MSI: 8617 bnx2x_enable_msi(bp); 8618 8619 fallthrough; 8620 case BNX2X_INT_MODE_INTX: 8621 bp->num_ethernet_queues = 1; 8622 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 8623 BNX2X_DEV_INFO("set number of queues to 1\n"); 8624 break; 8625 default: 8626 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); 8627 return -EINVAL; 8628 } 8629 return 0; 8630} 8631 8632/* must be called prior to any HW initializations */ 8633static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 8634{ 8635 if (IS_SRIOV(bp)) 8636 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; 8637 return L2_ILT_LINES(bp); 8638} 8639 8640void bnx2x_ilt_set_info(struct bnx2x *bp) 8641{ 8642 struct ilt_client_info *ilt_client; 8643 struct bnx2x_ilt *ilt = BP_ILT(bp); 8644 u16 line = 0; 8645 8646 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 8647 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 8648 8649 /* CDU */ 8650 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 8651 ilt_client->client_num = ILT_CLIENT_CDU; 8652 ilt_client->page_size = CDU_ILT_PAGE_SZ; 8653 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 8654 ilt_client->start = line; 8655 line += bnx2x_cid_ilt_lines(bp); 8656 8657 if (CNIC_SUPPORT(bp)) 8658 line += CNIC_ILT_LINES; 8659 ilt_client->end = line - 1; 8660 8661 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8662 ilt_client->start, 8663 ilt_client->end, 8664 ilt_client->page_size, 8665 ilt_client->flags, 8666 ilog2(ilt_client->page_size >> 12)); 8667 8668 /* QM */ 8669 if (QM_INIT(bp->qm_cid_count)) { 8670 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 8671 ilt_client->client_num = ILT_CLIENT_QM; 8672 ilt_client->page_size = QM_ILT_PAGE_SZ; 8673 ilt_client->flags = 0; 8674 ilt_client->start = line; 8675 8676 /* 4 bytes for each cid */ 8677 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 8678 QM_ILT_PAGE_SZ); 8679 8680 ilt_client->end = line - 1; 8681 8682 DP(NETIF_MSG_IFUP, 8683 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8684 ilt_client->start, 8685 ilt_client->end, 8686 ilt_client->page_size, 8687 ilt_client->flags, 8688 ilog2(ilt_client->page_size >> 12)); 8689 } 8690 8691 if (CNIC_SUPPORT(bp)) { 8692 /* SRC */ 8693 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 8694 ilt_client->client_num = ILT_CLIENT_SRC; 8695 ilt_client->page_size = SRC_ILT_PAGE_SZ; 8696 ilt_client->flags = 0; 8697 ilt_client->start = line; 8698 line += SRC_ILT_LINES; 8699 ilt_client->end = line - 1; 8700 8701 DP(NETIF_MSG_IFUP, 8702 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8703 ilt_client->start, 8704 ilt_client->end, 8705 ilt_client->page_size, 8706 ilt_client->flags, 8707 ilog2(ilt_client->page_size >> 12)); 8708 8709 /* TM */ 8710 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 8711 ilt_client->client_num = ILT_CLIENT_TM; 8712 ilt_client->page_size = TM_ILT_PAGE_SZ; 8713 ilt_client->flags = 0; 8714 ilt_client->start = line; 8715 line += TM_ILT_LINES; 8716 ilt_client->end = line - 1; 8717 8718 DP(NETIF_MSG_IFUP, 8719 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8720 ilt_client->start, 8721 ilt_client->end, 8722 ilt_client->page_size, 8723 ilt_client->flags, 8724 ilog2(ilt_client->page_size >> 12)); 8725 } 8726 8727 BUG_ON(line > ILT_MAX_LINES); 8728} 8729 8730/** 8731 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 8732 * 8733 * @bp: driver handle 8734 * @fp: pointer to fastpath 8735 * @init_params: pointer to parameters structure 8736 * 8737 * parameters configured: 8738 * - HC configuration 8739 * - Queue's CDU context 8740 */ 8741static void bnx2x_pf_q_prep_init(struct bnx2x *bp, 8742 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 8743{ 8744 u8 cos; 8745 int cxt_index, cxt_offset; 8746 8747 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 8748 if (!IS_FCOE_FP(fp)) { 8749 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 8750 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 8751 8752 /* If HC is supported, enable host coalescing in the transition 8753 * to INIT state. 8754 */ 8755 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 8756 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 8757 8758 /* HC rate */ 8759 init_params->rx.hc_rate = bp->rx_ticks ? 8760 (1000000 / bp->rx_ticks) : 0; 8761 init_params->tx.hc_rate = bp->tx_ticks ? 8762 (1000000 / bp->tx_ticks) : 0; 8763 8764 /* FW SB ID */ 8765 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 8766 fp->fw_sb_id; 8767 8768 /* 8769 * CQ index among the SB indices: FCoE clients uses the default 8770 * SB, therefore it's different. 8771 */ 8772 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 8773 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 8774 } 8775 8776 /* set maximum number of COSs supported by this queue */ 8777 init_params->max_cos = fp->max_cos; 8778 8779 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", 8780 fp->index, init_params->max_cos); 8781 8782 /* set the context pointers queue object */ 8783 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { 8784 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; 8785 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * 8786 ILT_PAGE_CIDS); 8787 init_params->cxts[cos] = 8788 &bp->context[cxt_index].vcxt[cxt_offset].eth; 8789 } 8790} 8791 8792static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8793 struct bnx2x_queue_state_params *q_params, 8794 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 8795 int tx_index, bool leading) 8796{ 8797 memset(tx_only_params, 0, sizeof(*tx_only_params)); 8798 8799 /* Set the command */ 8800 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 8801 8802 /* Set tx-only QUEUE flags: don't zero statistics */ 8803 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 8804 8805 /* choose the index of the cid to send the slow path on */ 8806 tx_only_params->cid_index = tx_index; 8807 8808 /* Set general TX_ONLY_SETUP parameters */ 8809 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 8810 8811 /* Set Tx TX_ONLY_SETUP parameters */ 8812 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 8813 8814 DP(NETIF_MSG_IFUP, 8815 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", 8816 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 8817 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 8818 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 8819 8820 /* send the ramrod */ 8821 return bnx2x_queue_state_change(bp, q_params); 8822} 8823 8824/** 8825 * bnx2x_setup_queue - setup queue 8826 * 8827 * @bp: driver handle 8828 * @fp: pointer to fastpath 8829 * @leading: is leading 8830 * 8831 * This function performs 2 steps in a Queue state machine 8832 * actually: 1) RESET->INIT 2) INIT->SETUP 8833 */ 8834 8835int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8836 bool leading) 8837{ 8838 struct bnx2x_queue_state_params q_params = {NULL}; 8839 struct bnx2x_queue_setup_params *setup_params = 8840 &q_params.params.setup; 8841 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 8842 &q_params.params.tx_only; 8843 int rc; 8844 u8 tx_index; 8845 8846 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); 8847 8848 /* reset IGU state skip FCoE L2 queue */ 8849 if (!IS_FCOE_FP(fp)) 8850 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 8851 IGU_INT_ENABLE, 0); 8852 8853 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8854 /* We want to wait for completion in this context */ 8855 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8856 8857 /* Prepare the INIT parameters */ 8858 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 8859 8860 /* Set the command */ 8861 q_params.cmd = BNX2X_Q_CMD_INIT; 8862 8863 /* Change the state to INIT */ 8864 rc = bnx2x_queue_state_change(bp, &q_params); 8865 if (rc) { 8866 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 8867 return rc; 8868 } 8869 8870 DP(NETIF_MSG_IFUP, "init complete\n"); 8871 8872 /* Now move the Queue to the SETUP state... */ 8873 memset(setup_params, 0, sizeof(*setup_params)); 8874 8875 /* Set QUEUE flags */ 8876 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 8877 8878 /* Set general SETUP parameters */ 8879 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 8880 FIRST_TX_COS_INDEX); 8881 8882 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 8883 &setup_params->rxq_params); 8884 8885 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 8886 FIRST_TX_COS_INDEX); 8887 8888 /* Set the command */ 8889 q_params.cmd = BNX2X_Q_CMD_SETUP; 8890 8891 if (IS_FCOE_FP(fp)) 8892 bp->fcoe_init = true; 8893 8894 /* Change the state to SETUP */ 8895 rc = bnx2x_queue_state_change(bp, &q_params); 8896 if (rc) { 8897 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 8898 return rc; 8899 } 8900 8901 /* loop through the relevant tx-only indices */ 8902 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8903 tx_index < fp->max_cos; 8904 tx_index++) { 8905 8906 /* prepare and send tx-only ramrod*/ 8907 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 8908 tx_only_params, tx_index, leading); 8909 if (rc) { 8910 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 8911 fp->index, tx_index); 8912 return rc; 8913 } 8914 } 8915 8916 return rc; 8917} 8918 8919static int bnx2x_stop_queue(struct bnx2x *bp, int index) 8920{ 8921 struct bnx2x_fastpath *fp = &bp->fp[index]; 8922 struct bnx2x_fp_txdata *txdata; 8923 struct bnx2x_queue_state_params q_params = {NULL}; 8924 int rc, tx_index; 8925 8926 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); 8927 8928 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8929 /* We want to wait for completion in this context */ 8930 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8931 8932 /* close tx-only connections */ 8933 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8934 tx_index < fp->max_cos; 8935 tx_index++){ 8936 8937 /* ascertain this is a normal queue*/ 8938 txdata = fp->txdata_ptr[tx_index]; 8939 8940 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", 8941 txdata->txq_index); 8942 8943 /* send halt terminate on tx-only connection */ 8944 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8945 memset(&q_params.params.terminate, 0, 8946 sizeof(q_params.params.terminate)); 8947 q_params.params.terminate.cid_index = tx_index; 8948 8949 rc = bnx2x_queue_state_change(bp, &q_params); 8950 if (rc) 8951 return rc; 8952 8953 /* send halt terminate on tx-only connection */ 8954 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8955 memset(&q_params.params.cfc_del, 0, 8956 sizeof(q_params.params.cfc_del)); 8957 q_params.params.cfc_del.cid_index = tx_index; 8958 rc = bnx2x_queue_state_change(bp, &q_params); 8959 if (rc) 8960 return rc; 8961 } 8962 /* Stop the primary connection: */ 8963 /* ...halt the connection */ 8964 q_params.cmd = BNX2X_Q_CMD_HALT; 8965 rc = bnx2x_queue_state_change(bp, &q_params); 8966 if (rc) 8967 return rc; 8968 8969 /* ...terminate the connection */ 8970 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8971 memset(&q_params.params.terminate, 0, 8972 sizeof(q_params.params.terminate)); 8973 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 8974 rc = bnx2x_queue_state_change(bp, &q_params); 8975 if (rc) 8976 return rc; 8977 /* ...delete cfc entry */ 8978 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8979 memset(&q_params.params.cfc_del, 0, 8980 sizeof(q_params.params.cfc_del)); 8981 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 8982 return bnx2x_queue_state_change(bp, &q_params); 8983} 8984 8985static void bnx2x_reset_func(struct bnx2x *bp) 8986{ 8987 int port = BP_PORT(bp); 8988 int func = BP_FUNC(bp); 8989 int i; 8990 8991 /* Disable the function in the FW */ 8992 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 8993 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 8994 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 8995 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 8996 8997 /* FP SBs */ 8998 for_each_eth_queue(bp, i) { 8999 struct bnx2x_fastpath *fp = &bp->fp[i]; 9000 REG_WR8(bp, BAR_CSTRORM_INTMEM + 9001 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 9002 SB_DISABLED); 9003 } 9004 9005 if (CNIC_LOADED(bp)) 9006 /* CNIC SB */ 9007 REG_WR8(bp, BAR_CSTRORM_INTMEM + 9008 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET 9009 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); 9010 9011 /* SP SB */ 9012 REG_WR8(bp, BAR_CSTRORM_INTMEM + 9013 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 9014 SB_DISABLED); 9015 9016 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 9017 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 9018 0); 9019 9020 /* Configure IGU */ 9021 if (bp->common.int_block == INT_BLOCK_HC) { 9022 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 9023 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 9024 } else { 9025 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 9026 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 9027 } 9028 9029 if (CNIC_LOADED(bp)) { 9030 /* Disable Timer scan */ 9031 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 9032 /* 9033 * Wait for at least 10ms and up to 2 second for the timers 9034 * scan to complete 9035 */ 9036 for (i = 0; i < 200; i++) { 9037 usleep_range(10000, 20000); 9038 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 9039 break; 9040 } 9041 } 9042 /* Clear ILT */ 9043 bnx2x_clear_func_ilt(bp, func); 9044 9045 /* Timers workaround bug for E2: if this is vnic-3, 9046 * we need to set the entire ilt range for this timers. 9047 */ 9048 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 9049 struct ilt_client_info ilt_cli; 9050 /* use dummy TM client */ 9051 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 9052 ilt_cli.start = 0; 9053 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 9054 ilt_cli.client_num = ILT_CLIENT_TM; 9055 9056 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 9057 } 9058 9059 /* this assumes that reset_port() called before reset_func()*/ 9060 if (!CHIP_IS_E1x(bp)) 9061 bnx2x_pf_disable(bp); 9062 9063 bp->dmae_ready = 0; 9064} 9065 9066static void bnx2x_reset_port(struct bnx2x *bp) 9067{ 9068 int port = BP_PORT(bp); 9069 u32 val; 9070 9071 /* Reset physical Link */ 9072 bnx2x__link_reset(bp); 9073 9074 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 9075 9076 /* Do not rcv packets to BRB */ 9077 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 9078 /* Do not direct rcv packets that are not for MCP to the BRB */ 9079 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 9080 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 9081 9082 /* Configure AEU */ 9083 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 9084 9085 msleep(100); 9086 /* Check for BRB port occupancy */ 9087 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 9088 if (val) 9089 DP(NETIF_MSG_IFDOWN, 9090 "BRB1 is not empty %d blocks are occupied\n", val); 9091 9092 /* TODO: Close Doorbell port? */ 9093} 9094 9095static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 9096{ 9097 struct bnx2x_func_state_params func_params = {NULL}; 9098 9099 /* Prepare parameters for function state transitions */ 9100 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 9101 9102 func_params.f_obj = &bp->func_obj; 9103 func_params.cmd = BNX2X_F_CMD_HW_RESET; 9104 9105 func_params.params.hw_init.load_phase = load_code; 9106 9107 return bnx2x_func_state_change(bp, &func_params); 9108} 9109 9110static int bnx2x_func_stop(struct bnx2x *bp) 9111{ 9112 struct bnx2x_func_state_params func_params = {NULL}; 9113 int rc; 9114 9115 /* Prepare parameters for function state transitions */ 9116 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 9117 func_params.f_obj = &bp->func_obj; 9118 func_params.cmd = BNX2X_F_CMD_STOP; 9119 9120 /* 9121 * Try to stop the function the 'good way'. If fails (in case 9122 * of a parity error during bnx2x_chip_cleanup()) and we are 9123 * not in a debug mode, perform a state transaction in order to 9124 * enable further HW_RESET transaction. 9125 */ 9126 rc = bnx2x_func_state_change(bp, &func_params); 9127 if (rc) { 9128#ifdef BNX2X_STOP_ON_ERROR 9129 return rc; 9130#else 9131 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); 9132 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 9133 return bnx2x_func_state_change(bp, &func_params); 9134#endif 9135 } 9136 9137 return 0; 9138} 9139 9140/** 9141 * bnx2x_send_unload_req - request unload mode from the MCP. 9142 * 9143 * @bp: driver handle 9144 * @unload_mode: requested function's unload mode 9145 * 9146 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 9147 */ 9148u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 9149{ 9150 u32 reset_code = 0; 9151 int port = BP_PORT(bp); 9152 9153 /* Select the UNLOAD request mode */ 9154 if (unload_mode == UNLOAD_NORMAL) 9155 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 9156 9157 else if (bp->flags & NO_WOL_FLAG) 9158 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 9159 9160 else if (bp->wol) { 9161 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 9162 const u8 *mac_addr = bp->dev->dev_addr; 9163 struct pci_dev *pdev = bp->pdev; 9164 u32 val; 9165 u16 pmc; 9166 9167 /* The mac address is written to entries 1-4 to 9168 * preserve entry 0 which is used by the PMF 9169 */ 9170 u8 entry = (BP_VN(bp) + 1)*8; 9171 9172 val = (mac_addr[0] << 8) | mac_addr[1]; 9173 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 9174 9175 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 9176 (mac_addr[4] << 8) | mac_addr[5]; 9177 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 9178 9179 /* Enable the PME and clear the status */ 9180 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); 9181 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 9182 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); 9183 9184 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 9185 9186 } else 9187 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 9188 9189 /* Send the request to the MCP */ 9190 if (!BP_NOMCP(bp)) 9191 reset_code = bnx2x_fw_command(bp, reset_code, 0); 9192 else { 9193 int path = BP_PATH(bp); 9194 9195 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", 9196 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], 9197 bnx2x_load_count[path][2]); 9198 bnx2x_load_count[path][0]--; 9199 bnx2x_load_count[path][1 + port]--; 9200 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", 9201 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], 9202 bnx2x_load_count[path][2]); 9203 if (bnx2x_load_count[path][0] == 0) 9204 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 9205 else if (bnx2x_load_count[path][1 + port] == 0) 9206 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 9207 else 9208 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 9209 } 9210 9211 return reset_code; 9212} 9213 9214/** 9215 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 9216 * 9217 * @bp: driver handle 9218 * @keep_link: true iff link should be kept up 9219 */ 9220void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) 9221{ 9222 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; 9223 9224 /* Report UNLOAD_DONE to MCP */ 9225 if (!BP_NOMCP(bp)) 9226 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); 9227} 9228 9229static int bnx2x_func_wait_started(struct bnx2x *bp) 9230{ 9231 int tout = 50; 9232 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 9233 9234 if (!bp->port.pmf) 9235 return 0; 9236 9237 /* 9238 * (assumption: No Attention from MCP at this stage) 9239 * PMF probably in the middle of TX disable/enable transaction 9240 * 1. Sync IRS for default SB 9241 * 2. Sync SP queue - this guarantees us that attention handling started 9242 * 3. Wait, that TX disable/enable transaction completes 9243 * 9244 * 1+2 guarantee that if DCBx attention was scheduled it already changed 9245 * pending bit of transaction from STARTED-->TX_STOPPED, if we already 9246 * received completion for the transaction the state is TX_STOPPED. 9247 * State will return to STARTED after completion of TX_STOPPED-->STARTED 9248 * transaction. 9249 */ 9250 9251 /* make sure default SB ISR is done */ 9252 if (msix) 9253 synchronize_irq(bp->msix_table[0].vector); 9254 else 9255 synchronize_irq(bp->pdev->irq); 9256 9257 flush_workqueue(bnx2x_wq); 9258 flush_workqueue(bnx2x_iov_wq); 9259 9260 while (bnx2x_func_get_state(bp, &bp->func_obj) != 9261 BNX2X_F_STATE_STARTED && tout--) 9262 msleep(20); 9263 9264 if (bnx2x_func_get_state(bp, &bp->func_obj) != 9265 BNX2X_F_STATE_STARTED) { 9266#ifdef BNX2X_STOP_ON_ERROR 9267 BNX2X_ERR("Wrong function state\n"); 9268 return -EBUSY; 9269#else 9270 /* 9271 * Failed to complete the transaction in a "good way" 9272 * Force both transactions with CLR bit 9273 */ 9274 struct bnx2x_func_state_params func_params = {NULL}; 9275 9276 DP(NETIF_MSG_IFDOWN, 9277 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n"); 9278 9279 func_params.f_obj = &bp->func_obj; 9280 __set_bit(RAMROD_DRV_CLR_ONLY, 9281 &func_params.ramrod_flags); 9282 9283 /* STARTED-->TX_ST0PPED */ 9284 func_params.cmd = BNX2X_F_CMD_TX_STOP; 9285 bnx2x_func_state_change(bp, &func_params); 9286 9287 /* TX_ST0PPED-->STARTED */ 9288 func_params.cmd = BNX2X_F_CMD_TX_START; 9289 return bnx2x_func_state_change(bp, &func_params); 9290#endif 9291 } 9292 9293 return 0; 9294} 9295 9296static void bnx2x_disable_ptp(struct bnx2x *bp) 9297{ 9298 int port = BP_PORT(bp); 9299 9300 /* Disable sending PTP packets to host */ 9301 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : 9302 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); 9303 9304 /* Reset PTP event detection rules */ 9305 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : 9306 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); 9307 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : 9308 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); 9309 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : 9310 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); 9311 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : 9312 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); 9313 9314 /* Disable the PTP feature */ 9315 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : 9316 NIG_REG_P0_PTP_EN, 0x0); 9317} 9318 9319/* Called during unload, to stop PTP-related stuff */ 9320static void bnx2x_stop_ptp(struct bnx2x *bp) 9321{ 9322 /* Cancel PTP work queue. Should be done after the Tx queues are 9323 * drained to prevent additional scheduling. 9324 */ 9325 cancel_work_sync(&bp->ptp_task); 9326 9327 if (bp->ptp_tx_skb) { 9328 dev_kfree_skb_any(bp->ptp_tx_skb); 9329 bp->ptp_tx_skb = NULL; 9330 } 9331 9332 /* Disable PTP in HW */ 9333 bnx2x_disable_ptp(bp); 9334 9335 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n"); 9336} 9337 9338void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) 9339{ 9340 int port = BP_PORT(bp); 9341 int i, rc = 0; 9342 u8 cos; 9343 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 9344 u32 reset_code; 9345 9346 /* Wait until tx fastpath tasks complete */ 9347 for_each_tx_queue(bp, i) { 9348 struct bnx2x_fastpath *fp = &bp->fp[i]; 9349 9350 for_each_cos_in_tx_queue(fp, cos) 9351 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); 9352#ifdef BNX2X_STOP_ON_ERROR 9353 if (rc) 9354 return; 9355#endif 9356 } 9357 9358 /* Give HW time to discard old tx messages */ 9359 usleep_range(1000, 2000); 9360 9361 /* Clean all ETH MACs */ 9362 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, 9363 false); 9364 if (rc < 0) 9365 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 9366 9367 /* Clean up UC list */ 9368 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, 9369 true); 9370 if (rc < 0) 9371 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", 9372 rc); 9373 9374 /* The whole *vlan_obj structure may be not initialized if VLAN 9375 * filtering offload is not supported by hardware. Currently this is 9376 * true for all hardware covered by CHIP_IS_E1x(). 9377 */ 9378 if (!CHIP_IS_E1x(bp)) { 9379 /* Remove all currently configured VLANs */ 9380 rc = bnx2x_del_all_vlans(bp); 9381 if (rc < 0) 9382 BNX2X_ERR("Failed to delete all VLANs\n"); 9383 } 9384 9385 /* Disable LLH */ 9386 if (!CHIP_IS_E1(bp)) 9387 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 9388 9389 /* Set "drop all" (stop Rx). 9390 * We need to take a netif_addr_lock() here in order to prevent 9391 * a race between the completion code and this code. 9392 */ 9393 netif_addr_lock_bh(bp->dev); 9394 /* Schedule the rx_mode command */ 9395 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 9396 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 9397 else if (bp->slowpath) 9398 bnx2x_set_storm_rx_mode(bp); 9399 9400 /* Cleanup multicast configuration */ 9401 rparam.mcast_obj = &bp->mcast_obj; 9402 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 9403 if (rc < 0) 9404 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 9405 9406 netif_addr_unlock_bh(bp->dev); 9407 9408 bnx2x_iov_chip_cleanup(bp); 9409 9410 /* 9411 * Send the UNLOAD_REQUEST to the MCP. This will return if 9412 * this function should perform FUNC, PORT or COMMON HW 9413 * reset. 9414 */ 9415 reset_code = bnx2x_send_unload_req(bp, unload_mode); 9416 9417 /* 9418 * (assumption: No Attention from MCP at this stage) 9419 * PMF probably in the middle of TX disable/enable transaction 9420 */ 9421 rc = bnx2x_func_wait_started(bp); 9422 if (rc) { 9423 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 9424#ifdef BNX2X_STOP_ON_ERROR 9425 return; 9426#endif 9427 } 9428 9429 /* Close multi and leading connections 9430 * Completions for ramrods are collected in a synchronous way 9431 */ 9432 for_each_eth_queue(bp, i) 9433 if (bnx2x_stop_queue(bp, i)) 9434#ifdef BNX2X_STOP_ON_ERROR 9435 return; 9436#else 9437 goto unload_error; 9438#endif 9439 9440 if (CNIC_LOADED(bp)) { 9441 for_each_cnic_queue(bp, i) 9442 if (bnx2x_stop_queue(bp, i)) 9443#ifdef BNX2X_STOP_ON_ERROR 9444 return; 9445#else 9446 goto unload_error; 9447#endif 9448 } 9449 9450 /* If SP settings didn't get completed so far - something 9451 * very wrong has happen. 9452 */ 9453 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 9454 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 9455 9456#ifndef BNX2X_STOP_ON_ERROR 9457unload_error: 9458#endif 9459 rc = bnx2x_func_stop(bp); 9460 if (rc) { 9461 BNX2X_ERR("Function stop failed!\n"); 9462#ifdef BNX2X_STOP_ON_ERROR 9463 return; 9464#endif 9465 } 9466 9467 /* stop_ptp should be after the Tx queues are drained to prevent 9468 * scheduling to the cancelled PTP work queue. It should also be after 9469 * function stop ramrod is sent, since as part of this ramrod FW access 9470 * PTP registers. 9471 */ 9472 if (bp->flags & PTP_SUPPORTED) { 9473 bnx2x_stop_ptp(bp); 9474 if (bp->ptp_clock) { 9475 ptp_clock_unregister(bp->ptp_clock); 9476 bp->ptp_clock = NULL; 9477 } 9478 } 9479 9480 if (!bp->nic_stopped) { 9481 /* Disable HW interrupts, NAPI */ 9482 bnx2x_netif_stop(bp, 1); 9483 /* Delete all NAPI objects */ 9484 bnx2x_del_all_napi(bp); 9485 if (CNIC_LOADED(bp)) 9486 bnx2x_del_all_napi_cnic(bp); 9487 9488 /* Release IRQs */ 9489 bnx2x_free_irq(bp); 9490 bp->nic_stopped = true; 9491 } 9492 9493 /* Reset the chip, unless PCI function is offline. If we reach this 9494 * point following a PCI error handling, it means device is really 9495 * in a bad state and we're about to remove it, so reset the chip 9496 * is not a good idea. 9497 */ 9498 if (!pci_channel_offline(bp->pdev)) { 9499 rc = bnx2x_reset_hw(bp, reset_code); 9500 if (rc) 9501 BNX2X_ERR("HW_RESET failed\n"); 9502 } 9503 9504 /* Report UNLOAD_DONE to MCP */ 9505 bnx2x_send_unload_done(bp, keep_link); 9506} 9507 9508void bnx2x_disable_close_the_gate(struct bnx2x *bp) 9509{ 9510 u32 val; 9511 9512 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); 9513 9514 if (CHIP_IS_E1(bp)) { 9515 int port = BP_PORT(bp); 9516 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 9517 MISC_REG_AEU_MASK_ATTN_FUNC_0; 9518 9519 val = REG_RD(bp, addr); 9520 val &= ~(0x300); 9521 REG_WR(bp, addr, val); 9522 } else { 9523 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 9524 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 9525 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 9526 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 9527 } 9528} 9529 9530/* Close gates #2, #3 and #4: */ 9531static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 9532{ 9533 u32 val; 9534 9535 /* Gates #2 and #4a are closed/opened for "not E1" only */ 9536 if (!CHIP_IS_E1(bp)) { 9537 /* #4 */ 9538 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 9539 /* #2 */ 9540 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 9541 } 9542 9543 /* #3 */ 9544 if (CHIP_IS_E1x(bp)) { 9545 /* Prevent interrupts from HC on both ports */ 9546 val = REG_RD(bp, HC_REG_CONFIG_1); 9547 REG_WR(bp, HC_REG_CONFIG_1, 9548 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 9549 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 9550 9551 val = REG_RD(bp, HC_REG_CONFIG_0); 9552 REG_WR(bp, HC_REG_CONFIG_0, 9553 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 9554 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 9555 } else { 9556 /* Prevent incoming interrupts in IGU */ 9557 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9558 9559 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 9560 (!close) ? 9561 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 9562 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 9563 } 9564 9565 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", 9566 close ? "closing" : "opening"); 9567} 9568 9569#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 9570 9571static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 9572{ 9573 /* Do some magic... */ 9574 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 9575 *magic_val = val & SHARED_MF_CLP_MAGIC; 9576 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 9577} 9578 9579/** 9580 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 9581 * 9582 * @bp: driver handle 9583 * @magic_val: old value of the `magic' bit. 9584 */ 9585static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 9586{ 9587 /* Restore the `magic' bit value... */ 9588 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 9589 MF_CFG_WR(bp, shared_mf_config.clp_mb, 9590 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 9591} 9592 9593/** 9594 * bnx2x_reset_mcp_prep - prepare for MCP reset. 9595 * 9596 * @bp: driver handle 9597 * @magic_val: old value of 'magic' bit. 9598 * 9599 * Takes care of CLP configurations. 9600 */ 9601static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 9602{ 9603 u32 shmem; 9604 u32 validity_offset; 9605 9606 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); 9607 9608 /* Set `magic' bit in order to save MF config */ 9609 if (!CHIP_IS_E1(bp)) 9610 bnx2x_clp_reset_prep(bp, magic_val); 9611 9612 /* Get shmem offset */ 9613 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 9614 validity_offset = 9615 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); 9616 9617 /* Clear validity map flags */ 9618 if (shmem > 0) 9619 REG_WR(bp, shmem + validity_offset, 0); 9620} 9621 9622#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 9623#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 9624 9625/** 9626 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 9627 * 9628 * @bp: driver handle 9629 */ 9630static void bnx2x_mcp_wait_one(struct bnx2x *bp) 9631{ 9632 /* special handling for emulation and FPGA, 9633 wait 10 times longer */ 9634 if (CHIP_REV_IS_SLOW(bp)) 9635 msleep(MCP_ONE_TIMEOUT*10); 9636 else 9637 msleep(MCP_ONE_TIMEOUT); 9638} 9639 9640/* 9641 * initializes bp->common.shmem_base and waits for validity signature to appear 9642 */ 9643static int bnx2x_init_shmem(struct bnx2x *bp) 9644{ 9645 int cnt = 0; 9646 u32 val = 0; 9647 9648 do { 9649 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 9650 9651 /* If we read all 0xFFs, means we are in PCI error state and 9652 * should bail out to avoid crashes on adapter's FW reads. 9653 */ 9654 if (bp->common.shmem_base == 0xFFFFFFFF) { 9655 bp->flags |= NO_MCP_FLAG; 9656 return -ENODEV; 9657 } 9658 9659 if (bp->common.shmem_base) { 9660 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 9661 if (val & SHR_MEM_VALIDITY_MB) 9662 return 0; 9663 } 9664 9665 bnx2x_mcp_wait_one(bp); 9666 9667 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 9668 9669 BNX2X_ERR("BAD MCP validity signature\n"); 9670 9671 return -ENODEV; 9672} 9673 9674static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 9675{ 9676 int rc = bnx2x_init_shmem(bp); 9677 9678 /* Restore the `magic' bit value */ 9679 if (!CHIP_IS_E1(bp)) 9680 bnx2x_clp_reset_done(bp, magic_val); 9681 9682 return rc; 9683} 9684 9685static void bnx2x_pxp_prep(struct bnx2x *bp) 9686{ 9687 if (!CHIP_IS_E1(bp)) { 9688 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 9689 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 9690 } 9691} 9692 9693/* 9694 * Reset the whole chip except for: 9695 * - PCIE core 9696 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 9697 * one reset bit) 9698 * - IGU 9699 * - MISC (including AEU) 9700 * - GRC 9701 * - RBCN, RBCP 9702 */ 9703static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 9704{ 9705 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 9706 u32 global_bits2, stay_reset2; 9707 9708 /* 9709 * Bits that have to be set in reset_mask2 if we want to reset 'global' 9710 * (per chip) blocks. 9711 */ 9712 global_bits2 = 9713 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 9714 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 9715 9716 /* Don't reset the following blocks. 9717 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be 9718 * reset, as in 4 port device they might still be owned 9719 * by the MCP (there is only one leader per path). 9720 */ 9721 not_reset_mask1 = 9722 MISC_REGISTERS_RESET_REG_1_RST_HC | 9723 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 9724 MISC_REGISTERS_RESET_REG_1_RST_PXP; 9725 9726 not_reset_mask2 = 9727 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 9728 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 9729 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 9730 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 9731 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 9732 MISC_REGISTERS_RESET_REG_2_RST_GRC | 9733 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 9734 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 9735 MISC_REGISTERS_RESET_REG_2_RST_ATC | 9736 MISC_REGISTERS_RESET_REG_2_PGLC | 9737 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 9738 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 9739 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 9740 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 9741 MISC_REGISTERS_RESET_REG_2_UMAC0 | 9742 MISC_REGISTERS_RESET_REG_2_UMAC1; 9743 9744 /* 9745 * Keep the following blocks in reset: 9746 * - all xxMACs are handled by the bnx2x_link code. 9747 */ 9748 stay_reset2 = 9749 MISC_REGISTERS_RESET_REG_2_XMAC | 9750 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 9751 9752 /* Full reset masks according to the chip */ 9753 reset_mask1 = 0xffffffff; 9754 9755 if (CHIP_IS_E1(bp)) 9756 reset_mask2 = 0xffff; 9757 else if (CHIP_IS_E1H(bp)) 9758 reset_mask2 = 0x1ffff; 9759 else if (CHIP_IS_E2(bp)) 9760 reset_mask2 = 0xfffff; 9761 else /* CHIP_IS_E3 */ 9762 reset_mask2 = 0x3ffffff; 9763 9764 /* Don't reset global blocks unless we need to */ 9765 if (!global) 9766 reset_mask2 &= ~global_bits2; 9767 9768 /* 9769 * In case of attention in the QM, we need to reset PXP 9770 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 9771 * because otherwise QM reset would release 'close the gates' shortly 9772 * before resetting the PXP, then the PSWRQ would send a write 9773 * request to PGLUE. Then when PXP is reset, PGLUE would try to 9774 * read the payload data from PSWWR, but PSWWR would not 9775 * respond. The write queue in PGLUE would stuck, dmae commands 9776 * would not return. Therefore it's important to reset the second 9777 * reset register (containing the 9778 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 9779 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 9780 * bit). 9781 */ 9782 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 9783 reset_mask2 & (~not_reset_mask2)); 9784 9785 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 9786 reset_mask1 & (~not_reset_mask1)); 9787 9788 barrier(); 9789 9790 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 9791 reset_mask2 & (~stay_reset2)); 9792 9793 barrier(); 9794 9795 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 9796} 9797 9798/** 9799 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 9800 * It should get cleared in no more than 1s. 9801 * 9802 * @bp: driver handle 9803 * 9804 * It should get cleared in no more than 1s. Returns 0 if 9805 * pending writes bit gets cleared. 9806 */ 9807static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 9808{ 9809 u32 cnt = 1000; 9810 u32 pend_bits = 0; 9811 9812 do { 9813 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 9814 9815 if (pend_bits == 0) 9816 break; 9817 9818 usleep_range(1000, 2000); 9819 } while (cnt-- > 0); 9820 9821 if (cnt <= 0) { 9822 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 9823 pend_bits); 9824 return -EBUSY; 9825 } 9826 9827 return 0; 9828} 9829 9830static int bnx2x_process_kill(struct bnx2x *bp, bool global) 9831{ 9832 int cnt = 1000; 9833 u32 val = 0; 9834 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 9835 u32 tags_63_32 = 0; 9836 9837 /* Empty the Tetris buffer, wait for 1s */ 9838 do { 9839 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 9840 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 9841 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 9842 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 9843 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 9844 if (CHIP_IS_E3(bp)) 9845 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); 9846 9847 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 9848 ((port_is_idle_0 & 0x1) == 0x1) && 9849 ((port_is_idle_1 & 0x1) == 0x1) && 9850 (pgl_exp_rom2 == 0xffffffff) && 9851 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) 9852 break; 9853 usleep_range(1000, 2000); 9854 } while (cnt-- > 0); 9855 9856 if (cnt <= 0) { 9857 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); 9858 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 9859 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 9860 pgl_exp_rom2); 9861 return -EAGAIN; 9862 } 9863 9864 barrier(); 9865 9866 /* Close gates #2, #3 and #4 */ 9867 bnx2x_set_234_gates(bp, true); 9868 9869 /* Poll for IGU VQs for 57712 and newer chips */ 9870 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 9871 return -EAGAIN; 9872 9873 /* TBD: Indicate that "process kill" is in progress to MCP */ 9874 9875 /* Clear "unprepared" bit */ 9876 REG_WR(bp, MISC_REG_UNPREPARED, 0); 9877 barrier(); 9878 9879 /* Wait for 1ms to empty GLUE and PCI-E core queues, 9880 * PSWHST, GRC and PSWRD Tetris buffer. 9881 */ 9882 usleep_range(1000, 2000); 9883 9884 /* Prepare to chip reset: */ 9885 /* MCP */ 9886 if (global) 9887 bnx2x_reset_mcp_prep(bp, &val); 9888 9889 /* PXP */ 9890 bnx2x_pxp_prep(bp); 9891 barrier(); 9892 9893 /* reset the chip */ 9894 bnx2x_process_kill_chip_reset(bp, global); 9895 barrier(); 9896 9897 /* clear errors in PGB */ 9898 if (!CHIP_IS_E1x(bp)) 9899 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); 9900 9901 /* Recover after reset: */ 9902 /* MCP */ 9903 if (global && bnx2x_reset_mcp_comp(bp, val)) 9904 return -EAGAIN; 9905 9906 /* TBD: Add resetting the NO_MCP mode DB here */ 9907 9908 /* Open the gates #2, #3 and #4 */ 9909 bnx2x_set_234_gates(bp, false); 9910 9911 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 9912 * reset state, re-enable attentions. */ 9913 9914 return 0; 9915} 9916 9917static int bnx2x_leader_reset(struct bnx2x *bp) 9918{ 9919 int rc = 0; 9920 bool global = bnx2x_reset_is_global(bp); 9921 u32 load_code; 9922 9923 /* if not going to reset MCP - load "fake" driver to reset HW while 9924 * driver is owner of the HW 9925 */ 9926 if (!global && !BP_NOMCP(bp)) { 9927 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 9928 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 9929 if (!load_code) { 9930 BNX2X_ERR("MCP response failure, aborting\n"); 9931 rc = -EAGAIN; 9932 goto exit_leader_reset; 9933 } 9934 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 9935 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 9936 BNX2X_ERR("MCP unexpected resp, aborting\n"); 9937 rc = -EAGAIN; 9938 goto exit_leader_reset2; 9939 } 9940 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 9941 if (!load_code) { 9942 BNX2X_ERR("MCP response failure, aborting\n"); 9943 rc = -EAGAIN; 9944 goto exit_leader_reset2; 9945 } 9946 } 9947 9948 /* Try to recover after the failure */ 9949 if (bnx2x_process_kill(bp, global)) { 9950 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", 9951 BP_PATH(bp)); 9952 rc = -EAGAIN; 9953 goto exit_leader_reset2; 9954 } 9955 9956 /* 9957 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 9958 * state. 9959 */ 9960 bnx2x_set_reset_done(bp); 9961 if (global) 9962 bnx2x_clear_reset_global(bp); 9963 9964exit_leader_reset2: 9965 /* unload "fake driver" if it was loaded */ 9966 if (!global && !BP_NOMCP(bp)) { 9967 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 9968 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 9969 } 9970exit_leader_reset: 9971 bp->is_leader = 0; 9972 bnx2x_release_leader_lock(bp); 9973 smp_mb(); 9974 return rc; 9975} 9976 9977static void bnx2x_recovery_failed(struct bnx2x *bp) 9978{ 9979 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 9980 9981 /* Disconnect this device */ 9982 netif_device_detach(bp->dev); 9983 9984 /* 9985 * Block ifup for all function on this engine until "process kill" 9986 * or power cycle. 9987 */ 9988 bnx2x_set_reset_in_progress(bp); 9989 9990 /* Shut down the power */ 9991 bnx2x_set_power_state(bp, PCI_D3hot); 9992 9993 bp->recovery_state = BNX2X_RECOVERY_FAILED; 9994 9995 smp_mb(); 9996} 9997 9998/* 9999 * Assumption: runs under rtnl lock. This together with the fact 10000 * that it's called only from bnx2x_sp_rtnl() ensure that it 10001 * will never be called when netif_running(bp->dev) is false. 10002 */ 10003static void bnx2x_parity_recover(struct bnx2x *bp) 10004{ 10005 u32 error_recovered, error_unrecovered; 10006 bool is_parity, global = false; 10007#ifdef CONFIG_BNX2X_SRIOV 10008 int vf_idx; 10009 10010 for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) { 10011 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 10012 10013 if (vf) 10014 vf->state = VF_LOST; 10015 } 10016#endif 10017 DP(NETIF_MSG_HW, "Handling parity\n"); 10018 while (1) { 10019 switch (bp->recovery_state) { 10020 case BNX2X_RECOVERY_INIT: 10021 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 10022 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 10023 WARN_ON(!is_parity); 10024 10025 /* Try to get a LEADER_LOCK HW lock */ 10026 if (bnx2x_trylock_leader_lock(bp)) { 10027 bnx2x_set_reset_in_progress(bp); 10028 /* 10029 * Check if there is a global attention and if 10030 * there was a global attention, set the global 10031 * reset bit. 10032 */ 10033 10034 if (global) 10035 bnx2x_set_reset_global(bp); 10036 10037 bp->is_leader = 1; 10038 } 10039 10040 /* Stop the driver */ 10041 /* If interface has been removed - break */ 10042 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) 10043 return; 10044 10045 bp->recovery_state = BNX2X_RECOVERY_WAIT; 10046 10047 /* Ensure "is_leader", MCP command sequence and 10048 * "recovery_state" update values are seen on other 10049 * CPUs. 10050 */ 10051 smp_mb(); 10052 break; 10053 10054 case BNX2X_RECOVERY_WAIT: 10055 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 10056 if (bp->is_leader) { 10057 int other_engine = BP_PATH(bp) ? 0 : 1; 10058 bool other_load_status = 10059 bnx2x_get_load_status(bp, other_engine); 10060 bool load_status = 10061 bnx2x_get_load_status(bp, BP_PATH(bp)); 10062 global = bnx2x_reset_is_global(bp); 10063 10064 /* 10065 * In case of a parity in a global block, let 10066 * the first leader that performs a 10067 * leader_reset() reset the global blocks in 10068 * order to clear global attentions. Otherwise 10069 * the gates will remain closed for that 10070 * engine. 10071 */ 10072 if (load_status || 10073 (global && other_load_status)) { 10074 /* Wait until all other functions get 10075 * down. 10076 */ 10077 schedule_delayed_work(&bp->sp_rtnl_task, 10078 HZ/10); 10079 return; 10080 } else { 10081 /* If all other functions got down - 10082 * try to bring the chip back to 10083 * normal. In any case it's an exit 10084 * point for a leader. 10085 */ 10086 if (bnx2x_leader_reset(bp)) { 10087 bnx2x_recovery_failed(bp); 10088 return; 10089 } 10090 10091 /* If we are here, means that the 10092 * leader has succeeded and doesn't 10093 * want to be a leader any more. Try 10094 * to continue as a none-leader. 10095 */ 10096 break; 10097 } 10098 } else { /* non-leader */ 10099 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 10100 /* Try to get a LEADER_LOCK HW lock as 10101 * long as a former leader may have 10102 * been unloaded by the user or 10103 * released a leadership by another 10104 * reason. 10105 */ 10106 if (bnx2x_trylock_leader_lock(bp)) { 10107 /* I'm a leader now! Restart a 10108 * switch case. 10109 */ 10110 bp->is_leader = 1; 10111 break; 10112 } 10113 10114 schedule_delayed_work(&bp->sp_rtnl_task, 10115 HZ/10); 10116 return; 10117 10118 } else { 10119 /* 10120 * If there was a global attention, wait 10121 * for it to be cleared. 10122 */ 10123 if (bnx2x_reset_is_global(bp)) { 10124 schedule_delayed_work( 10125 &bp->sp_rtnl_task, 10126 HZ/10); 10127 return; 10128 } 10129 10130 error_recovered = 10131 bp->eth_stats.recoverable_error; 10132 error_unrecovered = 10133 bp->eth_stats.unrecoverable_error; 10134 bp->recovery_state = 10135 BNX2X_RECOVERY_NIC_LOADING; 10136 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 10137 error_unrecovered++; 10138 netdev_err(bp->dev, 10139 "Recovery failed. Power cycle needed\n"); 10140 /* Disconnect this device */ 10141 netif_device_detach(bp->dev); 10142 /* Shut down the power */ 10143 bnx2x_set_power_state( 10144 bp, PCI_D3hot); 10145 smp_mb(); 10146 } else { 10147 bp->recovery_state = 10148 BNX2X_RECOVERY_DONE; 10149 error_recovered++; 10150 smp_mb(); 10151 } 10152 bp->eth_stats.recoverable_error = 10153 error_recovered; 10154 bp->eth_stats.unrecoverable_error = 10155 error_unrecovered; 10156 10157 return; 10158 } 10159 } 10160 default: 10161 return; 10162 } 10163 } 10164} 10165 10166static int bnx2x_udp_port_update(struct bnx2x *bp) 10167{ 10168 struct bnx2x_func_switch_update_params *switch_update_params; 10169 struct bnx2x_func_state_params func_params = {NULL}; 10170 u16 vxlan_port = 0, geneve_port = 0; 10171 int rc; 10172 10173 switch_update_params = &func_params.params.switch_update; 10174 10175 /* Prepare parameters for function state transitions */ 10176 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 10177 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 10178 10179 func_params.f_obj = &bp->func_obj; 10180 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 10181 10182 /* Function parameters */ 10183 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, 10184 &switch_update_params->changes); 10185 10186 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]) { 10187 geneve_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]; 10188 switch_update_params->geneve_dst_port = geneve_port; 10189 } 10190 10191 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]) { 10192 vxlan_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]; 10193 switch_update_params->vxlan_dst_port = vxlan_port; 10194 } 10195 10196 /* Re-enable inner-rss for the offloaded UDP tunnels */ 10197 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS, 10198 &switch_update_params->changes); 10199 10200 rc = bnx2x_func_state_change(bp, &func_params); 10201 if (rc) 10202 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n", 10203 vxlan_port, geneve_port, rc); 10204 else 10205 DP(BNX2X_MSG_SP, 10206 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n", 10207 vxlan_port, geneve_port); 10208 10209 return rc; 10210} 10211 10212static int bnx2x_udp_tunnel_sync(struct net_device *netdev, unsigned int table) 10213{ 10214 struct bnx2x *bp = netdev_priv(netdev); 10215 struct udp_tunnel_info ti; 10216 10217 udp_tunnel_nic_get_port(netdev, table, 0, &ti); 10218 bp->udp_tunnel_ports[table] = be16_to_cpu(ti.port); 10219 10220 return bnx2x_udp_port_update(bp); 10221} 10222 10223static const struct udp_tunnel_nic_info bnx2x_udp_tunnels = { 10224 .sync_table = bnx2x_udp_tunnel_sync, 10225 .flags = UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 10226 .tables = { 10227 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 10228 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 10229 }, 10230}; 10231 10232static int bnx2x_close(struct net_device *dev); 10233 10234/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 10235 * scheduled on a general queue in order to prevent a dead lock. 10236 */ 10237static void bnx2x_sp_rtnl_task(struct work_struct *work) 10238{ 10239 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 10240 10241 rtnl_lock(); 10242 10243 if (!netif_running(bp->dev)) { 10244 rtnl_unlock(); 10245 return; 10246 } 10247 10248 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 10249#ifdef BNX2X_STOP_ON_ERROR 10250 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 10251 "you will need to reboot when done\n"); 10252 goto sp_rtnl_not_reset; 10253#endif 10254 /* 10255 * Clear all pending SP commands as we are going to reset the 10256 * function anyway. 10257 */ 10258 bp->sp_rtnl_state = 0; 10259 smp_mb(); 10260 10261 bnx2x_parity_recover(bp); 10262 10263 rtnl_unlock(); 10264 return; 10265 } 10266 10267 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 10268#ifdef BNX2X_STOP_ON_ERROR 10269 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 10270 "you will need to reboot when done\n"); 10271 goto sp_rtnl_not_reset; 10272#endif 10273 10274 /* 10275 * Clear all pending SP commands as we are going to reset the 10276 * function anyway. 10277 */ 10278 bp->sp_rtnl_state = 0; 10279 smp_mb(); 10280 10281 /* Immediately indicate link as down */ 10282 bp->link_vars.link_up = 0; 10283 bp->force_link_down = true; 10284 netif_carrier_off(bp->dev); 10285 BNX2X_ERR("Indicating link is down due to Tx-timeout\n"); 10286 10287 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 10288 /* When ret value shows failure of allocation failure, 10289 * the nic is rebooted again. If open still fails, a error 10290 * message to notify the user. 10291 */ 10292 if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) { 10293 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 10294 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 10295 BNX2X_ERR("Open the NIC fails again!\n"); 10296 } 10297 rtnl_unlock(); 10298 return; 10299 } 10300#ifdef BNX2X_STOP_ON_ERROR 10301sp_rtnl_not_reset: 10302#endif 10303 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 10304 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 10305 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) 10306 bnx2x_after_function_update(bp); 10307 /* 10308 * in case of fan failure we need to reset id if the "stop on error" 10309 * debug flag is set, since we trying to prevent permanent overheating 10310 * damage 10311 */ 10312 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 10313 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); 10314 netif_device_detach(bp->dev); 10315 bnx2x_close(bp->dev); 10316 rtnl_unlock(); 10317 return; 10318 } 10319 10320 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { 10321 DP(BNX2X_MSG_SP, 10322 "sending set mcast vf pf channel message from rtnl sp-task\n"); 10323 bnx2x_vfpf_set_mcast(bp->dev); 10324 } 10325 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 10326 &bp->sp_rtnl_state)){ 10327 if (netif_carrier_ok(bp->dev)) { 10328 bnx2x_tx_disable(bp); 10329 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); 10330 } 10331 } 10332 10333 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { 10334 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); 10335 bnx2x_set_rx_mode_inner(bp); 10336 } 10337 10338 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, 10339 &bp->sp_rtnl_state)) 10340 bnx2x_pf_set_vfs_vlan(bp); 10341 10342 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { 10343 bnx2x_dcbx_stop_hw_tx(bp); 10344 bnx2x_dcbx_resume_hw_tx(bp); 10345 } 10346 10347 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION, 10348 &bp->sp_rtnl_state)) 10349 bnx2x_update_mng_version(bp); 10350 10351 if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state)) 10352 bnx2x_handle_update_svid_cmd(bp); 10353 10354 /* work which needs rtnl lock not-taken (as it takes the lock itself and 10355 * can be called from other contexts as well) 10356 */ 10357 rtnl_unlock(); 10358 10359 /* enable SR-IOV if applicable */ 10360 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, 10361 &bp->sp_rtnl_state)) { 10362 bnx2x_disable_sriov(bp); 10363 bnx2x_enable_sriov(bp); 10364 } 10365} 10366 10367static void bnx2x_period_task(struct work_struct *work) 10368{ 10369 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 10370 10371 if (!netif_running(bp->dev)) 10372 goto period_task_exit; 10373 10374 if (CHIP_REV_IS_SLOW(bp)) { 10375 BNX2X_ERR("period task called on emulation, ignoring\n"); 10376 goto period_task_exit; 10377 } 10378 10379 bnx2x_acquire_phy_lock(bp); 10380 /* 10381 * The barrier is needed to ensure the ordering between the writing to 10382 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 10383 * the reading here. 10384 */ 10385 smp_mb(); 10386 if (bp->port.pmf) { 10387 bnx2x_period_func(&bp->link_params, &bp->link_vars); 10388 10389 /* Re-queue task in 1 sec */ 10390 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 10391 } 10392 10393 bnx2x_release_phy_lock(bp); 10394period_task_exit: 10395 return; 10396} 10397 10398/* 10399 * Init service functions 10400 */ 10401 10402static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 10403{ 10404 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 10405 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 10406 return base + (BP_ABS_FUNC(bp)) * stride; 10407} 10408 10409static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, 10410 u8 port, u32 reset_reg, 10411 struct bnx2x_mac_vals *vals) 10412{ 10413 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; 10414 u32 base_addr; 10415 10416 if (!(mask & reset_reg)) 10417 return false; 10418 10419 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port); 10420 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 10421 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG; 10422 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); 10423 REG_WR(bp, vals->umac_addr[port], 0); 10424 10425 return true; 10426} 10427 10428static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, 10429 struct bnx2x_mac_vals *vals) 10430{ 10431 u32 val, base_addr, offset, mask, reset_reg; 10432 bool mac_stopped = false; 10433 u8 port = BP_PORT(bp); 10434 10435 /* reset addresses as they also mark which values were changed */ 10436 memset(vals, 0, sizeof(*vals)); 10437 10438 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); 10439 10440 if (!CHIP_IS_E3(bp)) { 10441 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); 10442 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; 10443 if ((mask & reset_reg) && val) { 10444 u32 wb_data[2]; 10445 BNX2X_DEV_INFO("Disable bmac Rx\n"); 10446 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM 10447 : NIG_REG_INGRESS_BMAC0_MEM; 10448 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL 10449 : BIGMAC_REGISTER_BMAC_CONTROL; 10450 10451 /* 10452 * use rd/wr since we cannot use dmae. This is safe 10453 * since MCP won't access the bus due to the request 10454 * to unload, and no function on the path can be 10455 * loaded at this time. 10456 */ 10457 wb_data[0] = REG_RD(bp, base_addr + offset); 10458 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); 10459 vals->bmac_addr = base_addr + offset; 10460 vals->bmac_val[0] = wb_data[0]; 10461 vals->bmac_val[1] = wb_data[1]; 10462 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 10463 REG_WR(bp, vals->bmac_addr, wb_data[0]); 10464 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); 10465 } 10466 BNX2X_DEV_INFO("Disable emac Rx\n"); 10467 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; 10468 vals->emac_val = REG_RD(bp, vals->emac_addr); 10469 REG_WR(bp, vals->emac_addr, 0); 10470 mac_stopped = true; 10471 } else { 10472 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { 10473 BNX2X_DEV_INFO("Disable xmac Rx\n"); 10474 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 10475 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); 10476 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 10477 val & ~(1 << 1)); 10478 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 10479 val | (1 << 1)); 10480 vals->xmac_addr = base_addr + XMAC_REG_CTRL; 10481 vals->xmac_val = REG_RD(bp, vals->xmac_addr); 10482 REG_WR(bp, vals->xmac_addr, 0); 10483 mac_stopped = true; 10484 } 10485 10486 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, 10487 reset_reg, vals); 10488 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, 10489 reset_reg, vals); 10490 } 10491 10492 if (mac_stopped) 10493 msleep(20); 10494} 10495 10496#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) 10497#define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \ 10498 0x1848 + ((f) << 4)) 10499#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) 10500#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) 10501#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) 10502 10503#define BCM_5710_UNDI_FW_MF_MAJOR (0x07) 10504#define BCM_5710_UNDI_FW_MF_MINOR (0x08) 10505#define BCM_5710_UNDI_FW_MF_VERS (0x05) 10506 10507static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) 10508{ 10509 /* UNDI marks its presence in DORQ - 10510 * it initializes CID offset for normal bell to 0x7 10511 */ 10512 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & 10513 MISC_REGISTERS_RESET_REG_1_RST_DORQ)) 10514 return false; 10515 10516 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { 10517 BNX2X_DEV_INFO("UNDI previously loaded\n"); 10518 return true; 10519 } 10520 10521 return false; 10522} 10523 10524static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) 10525{ 10526 u16 rcq, bd; 10527 u32 addr, tmp_reg; 10528 10529 if (BP_FUNC(bp) < 2) 10530 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); 10531 else 10532 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); 10533 10534 tmp_reg = REG_RD(bp, addr); 10535 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; 10536 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; 10537 10538 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); 10539 REG_WR(bp, addr, tmp_reg); 10540 10541 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n", 10542 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); 10543} 10544 10545static int bnx2x_prev_mcp_done(struct bnx2x *bp) 10546{ 10547 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 10548 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); 10549 if (!rc) { 10550 BNX2X_ERR("MCP response failure, aborting\n"); 10551 return -EBUSY; 10552 } 10553 10554 return 0; 10555} 10556 10557static struct bnx2x_prev_path_list * 10558 bnx2x_prev_path_get_entry(struct bnx2x *bp) 10559{ 10560 struct bnx2x_prev_path_list *tmp_list; 10561 10562 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) 10563 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && 10564 bp->pdev->bus->number == tmp_list->bus && 10565 BP_PATH(bp) == tmp_list->path) 10566 return tmp_list; 10567 10568 return NULL; 10569} 10570 10571static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) 10572{ 10573 struct bnx2x_prev_path_list *tmp_list; 10574 int rc; 10575 10576 rc = down_interruptible(&bnx2x_prev_sem); 10577 if (rc) { 10578 BNX2X_ERR("Received %d when tried to take lock\n", rc); 10579 return rc; 10580 } 10581 10582 tmp_list = bnx2x_prev_path_get_entry(bp); 10583 if (tmp_list) { 10584 tmp_list->aer = 1; 10585 rc = 0; 10586 } else { 10587 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", 10588 BP_PATH(bp)); 10589 } 10590 10591 up(&bnx2x_prev_sem); 10592 10593 return rc; 10594} 10595 10596static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) 10597{ 10598 struct bnx2x_prev_path_list *tmp_list; 10599 bool rc = false; 10600 10601 if (down_trylock(&bnx2x_prev_sem)) 10602 return false; 10603 10604 tmp_list = bnx2x_prev_path_get_entry(bp); 10605 if (tmp_list) { 10606 if (tmp_list->aer) { 10607 DP(NETIF_MSG_HW, "Path %d was marked by AER\n", 10608 BP_PATH(bp)); 10609 } else { 10610 rc = true; 10611 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", 10612 BP_PATH(bp)); 10613 } 10614 } 10615 10616 up(&bnx2x_prev_sem); 10617 10618 return rc; 10619} 10620 10621bool bnx2x_port_after_undi(struct bnx2x *bp) 10622{ 10623 struct bnx2x_prev_path_list *entry; 10624 bool val; 10625 10626 down(&bnx2x_prev_sem); 10627 10628 entry = bnx2x_prev_path_get_entry(bp); 10629 val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); 10630 10631 up(&bnx2x_prev_sem); 10632 10633 return val; 10634} 10635 10636static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) 10637{ 10638 struct bnx2x_prev_path_list *tmp_list; 10639 int rc; 10640 10641 rc = down_interruptible(&bnx2x_prev_sem); 10642 if (rc) { 10643 BNX2X_ERR("Received %d when tried to take lock\n", rc); 10644 return rc; 10645 } 10646 10647 /* Check whether the entry for this path already exists */ 10648 tmp_list = bnx2x_prev_path_get_entry(bp); 10649 if (tmp_list) { 10650 if (!tmp_list->aer) { 10651 BNX2X_ERR("Re-Marking the path.\n"); 10652 } else { 10653 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", 10654 BP_PATH(bp)); 10655 tmp_list->aer = 0; 10656 } 10657 up(&bnx2x_prev_sem); 10658 return 0; 10659 } 10660 up(&bnx2x_prev_sem); 10661 10662 /* Create an entry for this path and add it */ 10663 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); 10664 if (!tmp_list) { 10665 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); 10666 return -ENOMEM; 10667 } 10668 10669 tmp_list->bus = bp->pdev->bus->number; 10670 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); 10671 tmp_list->path = BP_PATH(bp); 10672 tmp_list->aer = 0; 10673 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; 10674 10675 rc = down_interruptible(&bnx2x_prev_sem); 10676 if (rc) { 10677 BNX2X_ERR("Received %d when tried to take lock\n", rc); 10678 kfree(tmp_list); 10679 } else { 10680 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", 10681 BP_PATH(bp)); 10682 list_add(&tmp_list->list, &bnx2x_prev_list); 10683 up(&bnx2x_prev_sem); 10684 } 10685 10686 return rc; 10687} 10688 10689static int bnx2x_do_flr(struct bnx2x *bp) 10690{ 10691 struct pci_dev *dev = bp->pdev; 10692 10693 if (CHIP_IS_E1x(bp)) { 10694 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); 10695 return -EINVAL; 10696 } 10697 10698 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ 10699 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { 10700 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", 10701 bp->common.bc_ver); 10702 return -EINVAL; 10703 } 10704 10705 if (!pci_wait_for_pending_transaction(dev)) 10706 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 10707 10708 BNX2X_DEV_INFO("Initiating FLR\n"); 10709 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); 10710 10711 return 0; 10712} 10713 10714static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) 10715{ 10716 int rc; 10717 10718 BNX2X_DEV_INFO("Uncommon unload Flow\n"); 10719 10720 /* Test if previous unload process was already finished for this path */ 10721 if (bnx2x_prev_is_path_marked(bp)) 10722 return bnx2x_prev_mcp_done(bp); 10723 10724 BNX2X_DEV_INFO("Path is unmarked\n"); 10725 10726 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */ 10727 if (bnx2x_prev_is_after_undi(bp)) 10728 goto out; 10729 10730 /* If function has FLR capabilities, and existing FW version matches 10731 * the one required, then FLR will be sufficient to clean any residue 10732 * left by previous driver 10733 */ 10734 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); 10735 10736 if (!rc) { 10737 /* fw version is good */ 10738 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); 10739 rc = bnx2x_do_flr(bp); 10740 } 10741 10742 if (!rc) { 10743 /* FLR was performed */ 10744 BNX2X_DEV_INFO("FLR successful\n"); 10745 return 0; 10746 } 10747 10748 BNX2X_DEV_INFO("Could not FLR\n"); 10749 10750out: 10751 /* Close the MCP request, return failure*/ 10752 rc = bnx2x_prev_mcp_done(bp); 10753 if (!rc) 10754 rc = BNX2X_PREV_WAIT_NEEDED; 10755 10756 return rc; 10757} 10758 10759static int bnx2x_prev_unload_common(struct bnx2x *bp) 10760{ 10761 u32 reset_reg, tmp_reg = 0, rc; 10762 bool prev_undi = false; 10763 struct bnx2x_mac_vals mac_vals; 10764 10765 /* It is possible a previous function received 'common' answer, 10766 * but hasn't loaded yet, therefore creating a scenario of 10767 * multiple functions receiving 'common' on the same path. 10768 */ 10769 BNX2X_DEV_INFO("Common unload Flow\n"); 10770 10771 memset(&mac_vals, 0, sizeof(mac_vals)); 10772 10773 if (bnx2x_prev_is_path_marked(bp)) 10774 return bnx2x_prev_mcp_done(bp); 10775 10776 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); 10777 10778 /* Reset should be performed after BRB is emptied */ 10779 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { 10780 u32 timer_count = 1000; 10781 10782 /* Close the MAC Rx to prevent BRB from filling up */ 10783 bnx2x_prev_unload_close_mac(bp, &mac_vals); 10784 10785 /* close LLH filters for both ports towards the BRB */ 10786 bnx2x_set_rx_filter(&bp->link_params, 0); 10787 bp->link_params.port ^= 1; 10788 bnx2x_set_rx_filter(&bp->link_params, 0); 10789 bp->link_params.port ^= 1; 10790 10791 /* Check if the UNDI driver was previously loaded */ 10792 if (bnx2x_prev_is_after_undi(bp)) { 10793 prev_undi = true; 10794 /* clear the UNDI indication */ 10795 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 10796 /* clear possible idle check errors */ 10797 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); 10798 } 10799 if (!CHIP_IS_E1x(bp)) 10800 /* block FW from writing to host */ 10801 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 10802 10803 /* wait until BRB is empty */ 10804 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 10805 while (timer_count) { 10806 u32 prev_brb = tmp_reg; 10807 10808 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 10809 if (!tmp_reg) 10810 break; 10811 10812 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); 10813 10814 /* reset timer as long as BRB actually gets emptied */ 10815 if (prev_brb > tmp_reg) 10816 timer_count = 1000; 10817 else 10818 timer_count--; 10819 10820 /* If UNDI resides in memory, manually increment it */ 10821 if (prev_undi) 10822 bnx2x_prev_unload_undi_inc(bp, 1); 10823 10824 udelay(10); 10825 } 10826 10827 if (!timer_count) 10828 BNX2X_ERR("Failed to empty BRB, hope for the best\n"); 10829 } 10830 10831 /* No packets are in the pipeline, path is ready for reset */ 10832 bnx2x_reset_common(bp); 10833 10834 if (mac_vals.xmac_addr) 10835 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); 10836 if (mac_vals.umac_addr[0]) 10837 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); 10838 if (mac_vals.umac_addr[1]) 10839 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); 10840 if (mac_vals.emac_addr) 10841 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); 10842 if (mac_vals.bmac_addr) { 10843 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); 10844 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); 10845 } 10846 10847 rc = bnx2x_prev_mark_path(bp, prev_undi); 10848 if (rc) { 10849 bnx2x_prev_mcp_done(bp); 10850 return rc; 10851 } 10852 10853 return bnx2x_prev_mcp_done(bp); 10854} 10855 10856static int bnx2x_prev_unload(struct bnx2x *bp) 10857{ 10858 int time_counter = 10; 10859 u32 rc, fw, hw_lock_reg, hw_lock_val; 10860 BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); 10861 10862 /* clear hw from errors which may have resulted from an interrupted 10863 * dmae transaction. 10864 */ 10865 bnx2x_clean_pglue_errors(bp); 10866 10867 /* Release previously held locks */ 10868 hw_lock_reg = (BP_FUNC(bp) <= 5) ? 10869 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : 10870 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); 10871 10872 hw_lock_val = REG_RD(bp, hw_lock_reg); 10873 if (hw_lock_val) { 10874 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { 10875 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); 10876 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 10877 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); 10878 } 10879 10880 BNX2X_DEV_INFO("Release Previously held hw lock\n"); 10881 REG_WR(bp, hw_lock_reg, 0xffffffff); 10882 } else 10883 BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); 10884 10885 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { 10886 BNX2X_DEV_INFO("Release previously held alr\n"); 10887 bnx2x_release_alr(bp); 10888 } 10889 10890 do { 10891 int aer = 0; 10892 /* Lock MCP using an unload request */ 10893 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); 10894 if (!fw) { 10895 BNX2X_ERR("MCP response failure, aborting\n"); 10896 rc = -EBUSY; 10897 break; 10898 } 10899 10900 rc = down_interruptible(&bnx2x_prev_sem); 10901 if (rc) { 10902 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", 10903 rc); 10904 } else { 10905 /* If Path is marked by EEH, ignore unload status */ 10906 aer = !!(bnx2x_prev_path_get_entry(bp) && 10907 bnx2x_prev_path_get_entry(bp)->aer); 10908 up(&bnx2x_prev_sem); 10909 } 10910 10911 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { 10912 rc = bnx2x_prev_unload_common(bp); 10913 break; 10914 } 10915 10916 /* non-common reply from MCP might require looping */ 10917 rc = bnx2x_prev_unload_uncommon(bp); 10918 if (rc != BNX2X_PREV_WAIT_NEEDED) 10919 break; 10920 10921 msleep(20); 10922 } while (--time_counter); 10923 10924 if (!time_counter || rc) { 10925 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n"); 10926 rc = -EPROBE_DEFER; 10927 } 10928 10929 /* Mark function if its port was used to boot from SAN */ 10930 if (bnx2x_port_after_undi(bp)) 10931 bp->link_params.feature_config_flags |= 10932 FEATURE_CONFIG_BOOT_FROM_SAN; 10933 10934 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); 10935 10936 return rc; 10937} 10938 10939static void bnx2x_get_common_hwinfo(struct bnx2x *bp) 10940{ 10941 u32 val, val2, val3, val4, id, boot_mode; 10942 u16 pmc; 10943 10944 /* Get the chip revision id and number. */ 10945 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 10946 val = REG_RD(bp, MISC_REG_CHIP_NUM); 10947 id = ((val & 0xffff) << 16); 10948 val = REG_RD(bp, MISC_REG_CHIP_REV); 10949 id |= ((val & 0xf) << 12); 10950 10951 /* Metal is read from PCI regs, but we can't access >=0x400 from 10952 * the configuration space (so we need to reg_rd) 10953 */ 10954 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); 10955 id |= (((val >> 24) & 0xf) << 4); 10956 val = REG_RD(bp, MISC_REG_BOND_ID); 10957 id |= (val & 0xf); 10958 bp->common.chip_id = id; 10959 10960 /* force 57811 according to MISC register */ 10961 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { 10962 if (CHIP_IS_57810(bp)) 10963 bp->common.chip_id = (CHIP_NUM_57811 << 16) | 10964 (bp->common.chip_id & 0x0000FFFF); 10965 else if (CHIP_IS_57810_MF(bp)) 10966 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | 10967 (bp->common.chip_id & 0x0000FFFF); 10968 bp->common.chip_id |= 0x1; 10969 } 10970 10971 /* Set doorbell size */ 10972 bp->db_size = (1 << BNX2X_DB_SHIFT); 10973 10974 if (!CHIP_IS_E1x(bp)) { 10975 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 10976 if ((val & 1) == 0) 10977 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 10978 else 10979 val = (val >> 1) & 1; 10980 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 10981 "2_PORT_MODE"); 10982 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 10983 CHIP_2_PORT_MODE; 10984 10985 if (CHIP_MODE_IS_4_PORT(bp)) 10986 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 10987 else 10988 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 10989 } else { 10990 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 10991 bp->pfid = bp->pf_num; /* 0..7 */ 10992 } 10993 10994 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); 10995 10996 bp->link_params.chip_id = bp->common.chip_id; 10997 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 10998 10999 val = (REG_RD(bp, 0x2874) & 0x55); 11000 if ((bp->common.chip_id & 0x1) || 11001 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 11002 bp->flags |= ONE_PORT_FLAG; 11003 BNX2X_DEV_INFO("single port device\n"); 11004 } 11005 11006 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 11007 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 11008 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 11009 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 11010 bp->common.flash_size, bp->common.flash_size); 11011 11012 bnx2x_init_shmem(bp); 11013 11014 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 11015 MISC_REG_GENERIC_CR_1 : 11016 MISC_REG_GENERIC_CR_0)); 11017 11018 bp->link_params.shmem_base = bp->common.shmem_base; 11019 bp->link_params.shmem2_base = bp->common.shmem2_base; 11020 if (SHMEM2_RD(bp, size) > 11021 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 11022 bp->link_params.lfa_base = 11023 REG_RD(bp, bp->common.shmem2_base + 11024 (u32)offsetof(struct shmem2_region, 11025 lfa_host_addr[BP_PORT(bp)])); 11026 else 11027 bp->link_params.lfa_base = 0; 11028 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 11029 bp->common.shmem_base, bp->common.shmem2_base); 11030 11031 if (!bp->common.shmem_base) { 11032 BNX2X_DEV_INFO("MCP not active\n"); 11033 bp->flags |= NO_MCP_FLAG; 11034 return; 11035 } 11036 11037 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 11038 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 11039 11040 bp->link_params.hw_led_mode = ((bp->common.hw_config & 11041 SHARED_HW_CFG_LED_MODE_MASK) >> 11042 SHARED_HW_CFG_LED_MODE_SHIFT); 11043 11044 bp->link_params.feature_config_flags = 0; 11045 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 11046 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 11047 bp->link_params.feature_config_flags |= 11048 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 11049 else 11050 bp->link_params.feature_config_flags &= 11051 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 11052 11053 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 11054 bp->common.bc_ver = val; 11055 BNX2X_DEV_INFO("bc_ver %X\n", val); 11056 if (val < BNX2X_BC_VER) { 11057 /* for now only warn 11058 * later we might need to enforce this */ 11059 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", 11060 BNX2X_BC_VER, val); 11061 } 11062 bp->link_params.feature_config_flags |= 11063 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 11064 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 11065 11066 bp->link_params.feature_config_flags |= 11067 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 11068 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 11069 bp->link_params.feature_config_flags |= 11070 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? 11071 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; 11072 bp->link_params.feature_config_flags |= 11073 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 11074 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 11075 11076 bp->link_params.feature_config_flags |= 11077 (val >= REQ_BC_VER_4_MT_SUPPORTED) ? 11078 FEATURE_CONFIG_MT_SUPPORT : 0; 11079 11080 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 11081 BC_SUPPORTS_PFC_STATS : 0; 11082 11083 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? 11084 BC_SUPPORTS_FCOE_FEATURES : 0; 11085 11086 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? 11087 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; 11088 11089 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? 11090 BC_SUPPORTS_RMMOD_CMD : 0; 11091 11092 boot_mode = SHMEM_RD(bp, 11093 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 11094 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 11095 switch (boot_mode) { 11096 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 11097 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 11098 break; 11099 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 11100 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 11101 break; 11102 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 11103 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 11104 break; 11105 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 11106 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 11107 break; 11108 } 11109 11110 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); 11111 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 11112 11113 BNX2X_DEV_INFO("%sWoL capable\n", 11114 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 11115 11116 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 11117 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 11118 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 11119 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 11120 11121 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 11122 val, val2, val3, val4); 11123} 11124 11125#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 11126#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 11127 11128static int bnx2x_get_igu_cam_info(struct bnx2x *bp) 11129{ 11130 int pfid = BP_FUNC(bp); 11131 int igu_sb_id; 11132 u32 val; 11133 u8 fid, igu_sb_cnt = 0; 11134 11135 bp->igu_base_sb = 0xff; 11136 if (CHIP_INT_MODE_IS_BC(bp)) { 11137 int vn = BP_VN(bp); 11138 igu_sb_cnt = bp->igu_sb_cnt; 11139 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 11140 FP_SB_MAX_E1x; 11141 11142 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 11143 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 11144 11145 return 0; 11146 } 11147 11148 /* IGU in normal mode - read CAM */ 11149 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 11150 igu_sb_id++) { 11151 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 11152 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 11153 continue; 11154 fid = IGU_FID(val); 11155 if ((fid & IGU_FID_ENCODE_IS_PF)) { 11156 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 11157 continue; 11158 if (IGU_VEC(val) == 0) 11159 /* default status block */ 11160 bp->igu_dsb_id = igu_sb_id; 11161 else { 11162 if (bp->igu_base_sb == 0xff) 11163 bp->igu_base_sb = igu_sb_id; 11164 igu_sb_cnt++; 11165 } 11166 } 11167 } 11168 11169#ifdef CONFIG_PCI_MSI 11170 /* Due to new PF resource allocation by MFW T7.4 and above, it's 11171 * optional that number of CAM entries will not be equal to the value 11172 * advertised in PCI. 11173 * Driver should use the minimal value of both as the actual status 11174 * block count 11175 */ 11176 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); 11177#endif 11178 11179 if (igu_sb_cnt == 0) { 11180 BNX2X_ERR("CAM configuration error\n"); 11181 return -EINVAL; 11182 } 11183 11184 return 0; 11185} 11186 11187static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) 11188{ 11189 int cfg_size = 0, idx, port = BP_PORT(bp); 11190 11191 /* Aggregation of supported attributes of all external phys */ 11192 bp->port.supported[0] = 0; 11193 bp->port.supported[1] = 0; 11194 switch (bp->link_params.num_phys) { 11195 case 1: 11196 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 11197 cfg_size = 1; 11198 break; 11199 case 2: 11200 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 11201 cfg_size = 1; 11202 break; 11203 case 3: 11204 if (bp->link_params.multi_phy_config & 11205 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 11206 bp->port.supported[1] = 11207 bp->link_params.phy[EXT_PHY1].supported; 11208 bp->port.supported[0] = 11209 bp->link_params.phy[EXT_PHY2].supported; 11210 } else { 11211 bp->port.supported[0] = 11212 bp->link_params.phy[EXT_PHY1].supported; 11213 bp->port.supported[1] = 11214 bp->link_params.phy[EXT_PHY2].supported; 11215 } 11216 cfg_size = 2; 11217 break; 11218 } 11219 11220 if (!(bp->port.supported[0] || bp->port.supported[1])) { 11221 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", 11222 SHMEM_RD(bp, 11223 dev_info.port_hw_config[port].external_phy_config), 11224 SHMEM_RD(bp, 11225 dev_info.port_hw_config[port].external_phy_config2)); 11226 return; 11227 } 11228 11229 if (CHIP_IS_E3(bp)) 11230 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 11231 else { 11232 switch (switch_cfg) { 11233 case SWITCH_CFG_1G: 11234 bp->port.phy_addr = REG_RD( 11235 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 11236 break; 11237 case SWITCH_CFG_10G: 11238 bp->port.phy_addr = REG_RD( 11239 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 11240 break; 11241 default: 11242 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 11243 bp->port.link_config[0]); 11244 return; 11245 } 11246 } 11247 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 11248 /* mask what we support according to speed_cap_mask per configuration */ 11249 for (idx = 0; idx < cfg_size; idx++) { 11250 if (!(bp->link_params.speed_cap_mask[idx] & 11251 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 11252 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 11253 11254 if (!(bp->link_params.speed_cap_mask[idx] & 11255 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 11256 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 11257 11258 if (!(bp->link_params.speed_cap_mask[idx] & 11259 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 11260 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 11261 11262 if (!(bp->link_params.speed_cap_mask[idx] & 11263 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 11264 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 11265 11266 if (!(bp->link_params.speed_cap_mask[idx] & 11267 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 11268 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 11269 SUPPORTED_1000baseT_Full); 11270 11271 if (!(bp->link_params.speed_cap_mask[idx] & 11272 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 11273 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 11274 11275 if (!(bp->link_params.speed_cap_mask[idx] & 11276 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 11277 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 11278 11279 if (!(bp->link_params.speed_cap_mask[idx] & 11280 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 11281 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; 11282 } 11283 11284 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 11285 bp->port.supported[1]); 11286} 11287 11288static void bnx2x_link_settings_requested(struct bnx2x *bp) 11289{ 11290 u32 link_config, idx, cfg_size = 0; 11291 bp->port.advertising[0] = 0; 11292 bp->port.advertising[1] = 0; 11293 switch (bp->link_params.num_phys) { 11294 case 1: 11295 case 2: 11296 cfg_size = 1; 11297 break; 11298 case 3: 11299 cfg_size = 2; 11300 break; 11301 } 11302 for (idx = 0; idx < cfg_size; idx++) { 11303 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 11304 link_config = bp->port.link_config[idx]; 11305 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 11306 case PORT_FEATURE_LINK_SPEED_AUTO: 11307 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 11308 bp->link_params.req_line_speed[idx] = 11309 SPEED_AUTO_NEG; 11310 bp->port.advertising[idx] |= 11311 bp->port.supported[idx]; 11312 if (bp->link_params.phy[EXT_PHY1].type == 11313 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 11314 bp->port.advertising[idx] |= 11315 (SUPPORTED_100baseT_Half | 11316 SUPPORTED_100baseT_Full); 11317 } else { 11318 /* force 10G, no AN */ 11319 bp->link_params.req_line_speed[idx] = 11320 SPEED_10000; 11321 bp->port.advertising[idx] |= 11322 (ADVERTISED_10000baseT_Full | 11323 ADVERTISED_FIBRE); 11324 continue; 11325 } 11326 break; 11327 11328 case PORT_FEATURE_LINK_SPEED_10M_FULL: 11329 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 11330 bp->link_params.req_line_speed[idx] = 11331 SPEED_10; 11332 bp->port.advertising[idx] |= 11333 (ADVERTISED_10baseT_Full | 11334 ADVERTISED_TP); 11335 } else { 11336 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11337 link_config, 11338 bp->link_params.speed_cap_mask[idx]); 11339 return; 11340 } 11341 break; 11342 11343 case PORT_FEATURE_LINK_SPEED_10M_HALF: 11344 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 11345 bp->link_params.req_line_speed[idx] = 11346 SPEED_10; 11347 bp->link_params.req_duplex[idx] = 11348 DUPLEX_HALF; 11349 bp->port.advertising[idx] |= 11350 (ADVERTISED_10baseT_Half | 11351 ADVERTISED_TP); 11352 } else { 11353 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11354 link_config, 11355 bp->link_params.speed_cap_mask[idx]); 11356 return; 11357 } 11358 break; 11359 11360 case PORT_FEATURE_LINK_SPEED_100M_FULL: 11361 if (bp->port.supported[idx] & 11362 SUPPORTED_100baseT_Full) { 11363 bp->link_params.req_line_speed[idx] = 11364 SPEED_100; 11365 bp->port.advertising[idx] |= 11366 (ADVERTISED_100baseT_Full | 11367 ADVERTISED_TP); 11368 } else { 11369 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11370 link_config, 11371 bp->link_params.speed_cap_mask[idx]); 11372 return; 11373 } 11374 break; 11375 11376 case PORT_FEATURE_LINK_SPEED_100M_HALF: 11377 if (bp->port.supported[idx] & 11378 SUPPORTED_100baseT_Half) { 11379 bp->link_params.req_line_speed[idx] = 11380 SPEED_100; 11381 bp->link_params.req_duplex[idx] = 11382 DUPLEX_HALF; 11383 bp->port.advertising[idx] |= 11384 (ADVERTISED_100baseT_Half | 11385 ADVERTISED_TP); 11386 } else { 11387 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11388 link_config, 11389 bp->link_params.speed_cap_mask[idx]); 11390 return; 11391 } 11392 break; 11393 11394 case PORT_FEATURE_LINK_SPEED_1G: 11395 if (bp->port.supported[idx] & 11396 SUPPORTED_1000baseT_Full) { 11397 bp->link_params.req_line_speed[idx] = 11398 SPEED_1000; 11399 bp->port.advertising[idx] |= 11400 (ADVERTISED_1000baseT_Full | 11401 ADVERTISED_TP); 11402 } else if (bp->port.supported[idx] & 11403 SUPPORTED_1000baseKX_Full) { 11404 bp->link_params.req_line_speed[idx] = 11405 SPEED_1000; 11406 bp->port.advertising[idx] |= 11407 ADVERTISED_1000baseKX_Full; 11408 } else { 11409 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11410 link_config, 11411 bp->link_params.speed_cap_mask[idx]); 11412 return; 11413 } 11414 break; 11415 11416 case PORT_FEATURE_LINK_SPEED_2_5G: 11417 if (bp->port.supported[idx] & 11418 SUPPORTED_2500baseX_Full) { 11419 bp->link_params.req_line_speed[idx] = 11420 SPEED_2500; 11421 bp->port.advertising[idx] |= 11422 (ADVERTISED_2500baseX_Full | 11423 ADVERTISED_TP); 11424 } else { 11425 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11426 link_config, 11427 bp->link_params.speed_cap_mask[idx]); 11428 return; 11429 } 11430 break; 11431 11432 case PORT_FEATURE_LINK_SPEED_10G_CX4: 11433 if (bp->port.supported[idx] & 11434 SUPPORTED_10000baseT_Full) { 11435 bp->link_params.req_line_speed[idx] = 11436 SPEED_10000; 11437 bp->port.advertising[idx] |= 11438 (ADVERTISED_10000baseT_Full | 11439 ADVERTISED_FIBRE); 11440 } else if (bp->port.supported[idx] & 11441 SUPPORTED_10000baseKR_Full) { 11442 bp->link_params.req_line_speed[idx] = 11443 SPEED_10000; 11444 bp->port.advertising[idx] |= 11445 (ADVERTISED_10000baseKR_Full | 11446 ADVERTISED_FIBRE); 11447 } else { 11448 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11449 link_config, 11450 bp->link_params.speed_cap_mask[idx]); 11451 return; 11452 } 11453 break; 11454 case PORT_FEATURE_LINK_SPEED_20G: 11455 bp->link_params.req_line_speed[idx] = SPEED_20000; 11456 11457 break; 11458 default: 11459 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", 11460 link_config); 11461 bp->link_params.req_line_speed[idx] = 11462 SPEED_AUTO_NEG; 11463 bp->port.advertising[idx] = 11464 bp->port.supported[idx]; 11465 break; 11466 } 11467 11468 bp->link_params.req_flow_ctrl[idx] = (link_config & 11469 PORT_FEATURE_FLOW_CONTROL_MASK); 11470 if (bp->link_params.req_flow_ctrl[idx] == 11471 BNX2X_FLOW_CTRL_AUTO) { 11472 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) 11473 bp->link_params.req_flow_ctrl[idx] = 11474 BNX2X_FLOW_CTRL_NONE; 11475 else 11476 bnx2x_set_requested_fc(bp); 11477 } 11478 11479 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", 11480 bp->link_params.req_line_speed[idx], 11481 bp->link_params.req_duplex[idx], 11482 bp->link_params.req_flow_ctrl[idx], 11483 bp->port.advertising[idx]); 11484 } 11485} 11486 11487static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 11488{ 11489 __be16 mac_hi_be = cpu_to_be16(mac_hi); 11490 __be32 mac_lo_be = cpu_to_be32(mac_lo); 11491 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); 11492 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); 11493} 11494 11495static void bnx2x_get_port_hwinfo(struct bnx2x *bp) 11496{ 11497 int port = BP_PORT(bp); 11498 u32 config; 11499 u32 ext_phy_type, ext_phy_config, eee_mode; 11500 11501 bp->link_params.bp = bp; 11502 bp->link_params.port = port; 11503 11504 bp->link_params.lane_config = 11505 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 11506 11507 bp->link_params.speed_cap_mask[0] = 11508 SHMEM_RD(bp, 11509 dev_info.port_hw_config[port].speed_capability_mask) & 11510 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; 11511 bp->link_params.speed_cap_mask[1] = 11512 SHMEM_RD(bp, 11513 dev_info.port_hw_config[port].speed_capability_mask2) & 11514 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; 11515 bp->port.link_config[0] = 11516 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 11517 11518 bp->port.link_config[1] = 11519 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 11520 11521 bp->link_params.multi_phy_config = 11522 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 11523 /* If the device is capable of WoL, set the default state according 11524 * to the HW 11525 */ 11526 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 11527 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 11528 (config & PORT_FEATURE_WOL_ENABLED)); 11529 11530 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 11531 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) 11532 bp->flags |= NO_ISCSI_FLAG; 11533 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 11534 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) 11535 bp->flags |= NO_FCOE_FLAG; 11536 11537 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", 11538 bp->link_params.lane_config, 11539 bp->link_params.speed_cap_mask[0], 11540 bp->port.link_config[0]); 11541 11542 bp->link_params.switch_cfg = (bp->port.link_config[0] & 11543 PORT_FEATURE_CONNECTED_SWITCH_MASK); 11544 bnx2x_phy_probe(&bp->link_params); 11545 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 11546 11547 bnx2x_link_settings_requested(bp); 11548 11549 /* 11550 * If connected directly, work with the internal PHY, otherwise, work 11551 * with the external PHY 11552 */ 11553 ext_phy_config = 11554 SHMEM_RD(bp, 11555 dev_info.port_hw_config[port].external_phy_config); 11556 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 11557 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 11558 bp->mdio.prtad = bp->port.phy_addr; 11559 11560 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 11561 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 11562 bp->mdio.prtad = 11563 XGXS_EXT_PHY_ADDR(ext_phy_config); 11564 11565 /* Configure link feature according to nvram value */ 11566 eee_mode = (((SHMEM_RD(bp, dev_info. 11567 port_feature_config[port].eee_power_mode)) & 11568 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 11569 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 11570 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { 11571 bp->link_params.eee_mode = EEE_MODE_ADV_LPI | 11572 EEE_MODE_ENABLE_LPI | 11573 EEE_MODE_OUTPUT_TIME; 11574 } else { 11575 bp->link_params.eee_mode = 0; 11576 } 11577} 11578 11579void bnx2x_get_iscsi_info(struct bnx2x *bp) 11580{ 11581 u32 no_flags = NO_ISCSI_FLAG; 11582 int port = BP_PORT(bp); 11583 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 11584 drv_lic_key[port].max_iscsi_conn); 11585 11586 if (!CNIC_SUPPORT(bp)) { 11587 bp->flags |= no_flags; 11588 return; 11589 } 11590 11591 /* Get the number of maximum allowed iSCSI connections */ 11592 bp->cnic_eth_dev.max_iscsi_conn = 11593 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 11594 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 11595 11596 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 11597 bp->cnic_eth_dev.max_iscsi_conn); 11598 11599 /* 11600 * If maximum allowed number of connections is zero - 11601 * disable the feature. 11602 */ 11603 if (!bp->cnic_eth_dev.max_iscsi_conn) 11604 bp->flags |= no_flags; 11605} 11606 11607static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) 11608{ 11609 /* Port info */ 11610 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 11611 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); 11612 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 11613 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); 11614 11615 /* Node info */ 11616 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 11617 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); 11618 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 11619 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); 11620} 11621 11622static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) 11623{ 11624 u8 count = 0; 11625 11626 if (IS_MF(bp)) { 11627 u8 fid; 11628 11629 /* iterate over absolute function ids for this path: */ 11630 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { 11631 if (IS_MF_SD(bp)) { 11632 u32 cfg = MF_CFG_RD(bp, 11633 func_mf_config[fid].config); 11634 11635 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && 11636 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == 11637 FUNC_MF_CFG_PROTOCOL_FCOE)) 11638 count++; 11639 } else { 11640 u32 cfg = MF_CFG_RD(bp, 11641 func_ext_config[fid]. 11642 func_cfg); 11643 11644 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && 11645 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) 11646 count++; 11647 } 11648 } 11649 } else { /* SF */ 11650 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; 11651 11652 for (port = 0; port < port_cnt; port++) { 11653 u32 lic = SHMEM_RD(bp, 11654 drv_lic_key[port].max_fcoe_conn) ^ 11655 FW_ENCODE_32BIT_PATTERN; 11656 if (lic) 11657 count++; 11658 } 11659 } 11660 11661 return count; 11662} 11663 11664static void bnx2x_get_fcoe_info(struct bnx2x *bp) 11665{ 11666 int port = BP_PORT(bp); 11667 int func = BP_ABS_FUNC(bp); 11668 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 11669 drv_lic_key[port].max_fcoe_conn); 11670 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); 11671 11672 if (!CNIC_SUPPORT(bp)) { 11673 bp->flags |= NO_FCOE_FLAG; 11674 return; 11675 } 11676 11677 /* Get the number of maximum allowed FCoE connections */ 11678 bp->cnic_eth_dev.max_fcoe_conn = 11679 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 11680 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 11681 11682 /* Calculate the number of maximum allowed FCoE tasks */ 11683 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; 11684 11685 /* check if FCoE resources must be shared between different functions */ 11686 if (num_fcoe_func) 11687 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; 11688 11689 /* Read the WWN: */ 11690 if (!IS_MF(bp)) { 11691 /* Port info */ 11692 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 11693 SHMEM_RD(bp, 11694 dev_info.port_hw_config[port]. 11695 fcoe_wwn_port_name_upper); 11696 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 11697 SHMEM_RD(bp, 11698 dev_info.port_hw_config[port]. 11699 fcoe_wwn_port_name_lower); 11700 11701 /* Node info */ 11702 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 11703 SHMEM_RD(bp, 11704 dev_info.port_hw_config[port]. 11705 fcoe_wwn_node_name_upper); 11706 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 11707 SHMEM_RD(bp, 11708 dev_info.port_hw_config[port]. 11709 fcoe_wwn_node_name_lower); 11710 } else if (!IS_MF_SD(bp)) { 11711 /* Read the WWN info only if the FCoE feature is enabled for 11712 * this function. 11713 */ 11714 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) 11715 bnx2x_get_ext_wwn_info(bp, func); 11716 } else { 11717 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) 11718 bnx2x_get_ext_wwn_info(bp, func); 11719 } 11720 11721 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 11722 11723 /* 11724 * If maximum allowed number of connections is zero - 11725 * disable the feature. 11726 */ 11727 if (!bp->cnic_eth_dev.max_fcoe_conn) { 11728 bp->flags |= NO_FCOE_FLAG; 11729 eth_zero_addr(bp->fip_mac); 11730 } 11731} 11732 11733static void bnx2x_get_cnic_info(struct bnx2x *bp) 11734{ 11735 /* 11736 * iSCSI may be dynamically disabled but reading 11737 * info here we will decrease memory usage by driver 11738 * if the feature is disabled for good 11739 */ 11740 bnx2x_get_iscsi_info(bp); 11741 bnx2x_get_fcoe_info(bp); 11742} 11743 11744static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) 11745{ 11746 u32 val, val2; 11747 int func = BP_ABS_FUNC(bp); 11748 int port = BP_PORT(bp); 11749 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 11750 u8 *fip_mac = bp->fip_mac; 11751 11752 if (IS_MF(bp)) { 11753 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 11754 * FCoE MAC then the appropriate feature should be disabled. 11755 * In non SD mode features configuration comes from struct 11756 * func_ext_config. 11757 */ 11758 if (!IS_MF_SD(bp)) { 11759 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 11760 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 11761 val2 = MF_CFG_RD(bp, func_ext_config[func]. 11762 iscsi_mac_addr_upper); 11763 val = MF_CFG_RD(bp, func_ext_config[func]. 11764 iscsi_mac_addr_lower); 11765 bnx2x_set_mac_buf(iscsi_mac, val, val2); 11766 BNX2X_DEV_INFO 11767 ("Read iSCSI MAC: %pM\n", iscsi_mac); 11768 } else { 11769 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 11770 } 11771 11772 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 11773 val2 = MF_CFG_RD(bp, func_ext_config[func]. 11774 fcoe_mac_addr_upper); 11775 val = MF_CFG_RD(bp, func_ext_config[func]. 11776 fcoe_mac_addr_lower); 11777 bnx2x_set_mac_buf(fip_mac, val, val2); 11778 BNX2X_DEV_INFO 11779 ("Read FCoE L2 MAC: %pM\n", fip_mac); 11780 } else { 11781 bp->flags |= NO_FCOE_FLAG; 11782 } 11783 11784 bp->mf_ext_config = cfg; 11785 11786 } else { /* SD MODE */ 11787 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { 11788 /* use primary mac as iscsi mac */ 11789 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 11790 11791 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 11792 BNX2X_DEV_INFO 11793 ("Read iSCSI MAC: %pM\n", iscsi_mac); 11794 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { 11795 /* use primary mac as fip mac */ 11796 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 11797 BNX2X_DEV_INFO("SD FCoE MODE\n"); 11798 BNX2X_DEV_INFO 11799 ("Read FIP MAC: %pM\n", fip_mac); 11800 } 11801 } 11802 11803 /* If this is a storage-only interface, use SAN mac as 11804 * primary MAC. Notice that for SD this is already the case, 11805 * as the SAN mac was copied from the primary MAC. 11806 */ 11807 if (IS_MF_FCOE_AFEX(bp)) 11808 eth_hw_addr_set(bp->dev, fip_mac); 11809 } else { 11810 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11811 iscsi_mac_upper); 11812 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11813 iscsi_mac_lower); 11814 bnx2x_set_mac_buf(iscsi_mac, val, val2); 11815 11816 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11817 fcoe_fip_mac_upper); 11818 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11819 fcoe_fip_mac_lower); 11820 bnx2x_set_mac_buf(fip_mac, val, val2); 11821 } 11822 11823 /* Disable iSCSI OOO if MAC configuration is invalid. */ 11824 if (!is_valid_ether_addr(iscsi_mac)) { 11825 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 11826 eth_zero_addr(iscsi_mac); 11827 } 11828 11829 /* Disable FCoE if MAC configuration is invalid. */ 11830 if (!is_valid_ether_addr(fip_mac)) { 11831 bp->flags |= NO_FCOE_FLAG; 11832 eth_zero_addr(bp->fip_mac); 11833 } 11834} 11835 11836static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) 11837{ 11838 u32 val, val2; 11839 int func = BP_ABS_FUNC(bp); 11840 int port = BP_PORT(bp); 11841 u8 addr[ETH_ALEN] = {}; 11842 11843 /* Zero primary MAC configuration */ 11844 eth_hw_addr_set(bp->dev, addr); 11845 11846 if (BP_NOMCP(bp)) { 11847 BNX2X_ERROR("warning: random MAC workaround active\n"); 11848 eth_hw_addr_random(bp->dev); 11849 } else if (IS_MF(bp)) { 11850 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 11851 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 11852 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 11853 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) { 11854 bnx2x_set_mac_buf(addr, val, val2); 11855 eth_hw_addr_set(bp->dev, addr); 11856 } 11857 11858 if (CNIC_SUPPORT(bp)) 11859 bnx2x_get_cnic_mac_hwinfo(bp); 11860 } else { 11861 /* in SF read MACs from port configuration */ 11862 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 11863 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 11864 bnx2x_set_mac_buf(addr, val, val2); 11865 eth_hw_addr_set(bp->dev, addr); 11866 11867 if (CNIC_SUPPORT(bp)) 11868 bnx2x_get_cnic_mac_hwinfo(bp); 11869 } 11870 11871 if (!BP_NOMCP(bp)) { 11872 /* Read physical port identifier from shmem */ 11873 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 11874 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 11875 bnx2x_set_mac_buf(bp->phys_port_id, val, val2); 11876 bp->flags |= HAS_PHYS_PORT_ID; 11877 } 11878 11879 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 11880 11881 if (!is_valid_ether_addr(bp->dev->dev_addr)) 11882 dev_err(&bp->pdev->dev, 11883 "bad Ethernet MAC address configuration: %pM\n" 11884 "change it manually before bringing up the appropriate network interface\n", 11885 bp->dev->dev_addr); 11886} 11887 11888static bool bnx2x_get_dropless_info(struct bnx2x *bp) 11889{ 11890 int tmp; 11891 u32 cfg; 11892 11893 if (IS_VF(bp)) 11894 return false; 11895 11896 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { 11897 /* Take function: tmp = func */ 11898 tmp = BP_ABS_FUNC(bp); 11899 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); 11900 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); 11901 } else { 11902 /* Take port: tmp = port */ 11903 tmp = BP_PORT(bp); 11904 cfg = SHMEM_RD(bp, 11905 dev_info.port_hw_config[tmp].generic_features); 11906 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); 11907 } 11908 return cfg; 11909} 11910 11911static void validate_set_si_mode(struct bnx2x *bp) 11912{ 11913 u8 func = BP_ABS_FUNC(bp); 11914 u32 val; 11915 11916 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 11917 11918 /* check for legal mac (upper bytes) */ 11919 if (val != 0xffff) { 11920 bp->mf_mode = MULTI_FUNCTION_SI; 11921 bp->mf_config[BP_VN(bp)] = 11922 MF_CFG_RD(bp, func_mf_config[func].config); 11923 } else 11924 BNX2X_DEV_INFO("illegal MAC address for SI\n"); 11925} 11926 11927static int bnx2x_get_hwinfo(struct bnx2x *bp) 11928{ 11929 int /*abs*/func = BP_ABS_FUNC(bp); 11930 int vn; 11931 u32 val = 0, val2 = 0; 11932 int rc = 0; 11933 11934 /* Validate that chip access is feasible */ 11935 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { 11936 dev_err(&bp->pdev->dev, 11937 "Chip read returns all Fs. Preventing probe from continuing\n"); 11938 return -EINVAL; 11939 } 11940 11941 bnx2x_get_common_hwinfo(bp); 11942 11943 /* 11944 * initialize IGU parameters 11945 */ 11946 if (CHIP_IS_E1x(bp)) { 11947 bp->common.int_block = INT_BLOCK_HC; 11948 11949 bp->igu_dsb_id = DEF_SB_IGU_ID; 11950 bp->igu_base_sb = 0; 11951 } else { 11952 bp->common.int_block = INT_BLOCK_IGU; 11953 11954 /* do not allow device reset during IGU info processing */ 11955 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 11956 11957 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 11958 11959 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 11960 int tout = 5000; 11961 11962 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 11963 11964 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 11965 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 11966 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 11967 11968 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 11969 tout--; 11970 usleep_range(1000, 2000); 11971 } 11972 11973 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 11974 dev_err(&bp->pdev->dev, 11975 "FORCING Normal Mode failed!!!\n"); 11976 bnx2x_release_hw_lock(bp, 11977 HW_LOCK_RESOURCE_RESET); 11978 return -EPERM; 11979 } 11980 } 11981 11982 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 11983 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 11984 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 11985 } else 11986 BNX2X_DEV_INFO("IGU Normal Mode\n"); 11987 11988 rc = bnx2x_get_igu_cam_info(bp); 11989 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 11990 if (rc) 11991 return rc; 11992 } 11993 11994 /* 11995 * set base FW non-default (fast path) status block id, this value is 11996 * used to initialize the fw_sb_id saved on the fp/queue structure to 11997 * determine the id used by the FW. 11998 */ 11999 if (CHIP_IS_E1x(bp)) 12000 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 12001 else /* 12002 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 12003 * the same queue are indicated on the same IGU SB). So we prefer 12004 * FW and IGU SBs to be the same value. 12005 */ 12006 bp->base_fw_ndsb = bp->igu_base_sb; 12007 12008 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 12009 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 12010 bp->igu_sb_cnt, bp->base_fw_ndsb); 12011 12012 /* 12013 * Initialize MF configuration 12014 */ 12015 bp->mf_ov = 0; 12016 bp->mf_mode = 0; 12017 bp->mf_sub_mode = 0; 12018 vn = BP_VN(bp); 12019 12020 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 12021 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 12022 bp->common.shmem2_base, SHMEM2_RD(bp, size), 12023 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 12024 12025 if (SHMEM2_HAS(bp, mf_cfg_addr)) 12026 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 12027 else 12028 bp->common.mf_cfg_base = bp->common.shmem_base + 12029 offsetof(struct shmem_region, func_mb) + 12030 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 12031 /* 12032 * get mf configuration: 12033 * 1. Existence of MF configuration 12034 * 2. MAC address must be legal (check only upper bytes) 12035 * for Switch-Independent mode; 12036 * OVLAN must be legal for Switch-Dependent mode 12037 * 3. SF_MODE configures specific MF mode 12038 */ 12039 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 12040 /* get mf configuration */ 12041 val = SHMEM_RD(bp, 12042 dev_info.shared_feature_config.config); 12043 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 12044 12045 switch (val) { 12046 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 12047 validate_set_si_mode(bp); 12048 break; 12049 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: 12050 if ((!CHIP_IS_E1x(bp)) && 12051 (MF_CFG_RD(bp, func_mf_config[func]. 12052 mac_upper) != 0xffff) && 12053 (SHMEM2_HAS(bp, 12054 afex_driver_support))) { 12055 bp->mf_mode = MULTI_FUNCTION_AFEX; 12056 bp->mf_config[vn] = MF_CFG_RD(bp, 12057 func_mf_config[func].config); 12058 } else { 12059 BNX2X_DEV_INFO("can not configure afex mode\n"); 12060 } 12061 break; 12062 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 12063 /* get OV configuration */ 12064 val = MF_CFG_RD(bp, 12065 func_mf_config[FUNC_0].e1hov_tag); 12066 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 12067 12068 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 12069 bp->mf_mode = MULTI_FUNCTION_SD; 12070 bp->mf_config[vn] = MF_CFG_RD(bp, 12071 func_mf_config[func].config); 12072 } else 12073 BNX2X_DEV_INFO("illegal OV for SD\n"); 12074 break; 12075 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE: 12076 bp->mf_mode = MULTI_FUNCTION_SD; 12077 bp->mf_sub_mode = SUB_MF_MODE_BD; 12078 bp->mf_config[vn] = 12079 MF_CFG_RD(bp, 12080 func_mf_config[func].config); 12081 12082 if (SHMEM2_HAS(bp, mtu_size)) { 12083 int mtu_idx = BP_FW_MB_IDX(bp); 12084 u16 mtu_size; 12085 u32 mtu; 12086 12087 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]); 12088 mtu_size = (u16)mtu; 12089 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n", 12090 mtu_size, mtu); 12091 12092 /* if valid: update device mtu */ 12093 if ((mtu_size >= ETH_MIN_PACKET_SIZE) && 12094 (mtu_size <= 12095 ETH_MAX_JUMBO_PACKET_SIZE)) 12096 bp->dev->mtu = mtu_size; 12097 } 12098 break; 12099 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE: 12100 bp->mf_mode = MULTI_FUNCTION_SD; 12101 bp->mf_sub_mode = SUB_MF_MODE_UFP; 12102 bp->mf_config[vn] = 12103 MF_CFG_RD(bp, 12104 func_mf_config[func].config); 12105 break; 12106 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: 12107 bp->mf_config[vn] = 0; 12108 break; 12109 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE: 12110 val2 = SHMEM_RD(bp, 12111 dev_info.shared_hw_config.config_3); 12112 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK; 12113 switch (val2) { 12114 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5: 12115 validate_set_si_mode(bp); 12116 bp->mf_sub_mode = 12117 SUB_MF_MODE_NPAR1_DOT_5; 12118 break; 12119 default: 12120 /* Unknown configuration */ 12121 bp->mf_config[vn] = 0; 12122 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n", 12123 val); 12124 } 12125 break; 12126 default: 12127 /* Unknown configuration: reset mf_config */ 12128 bp->mf_config[vn] = 0; 12129 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); 12130 } 12131 } 12132 12133 BNX2X_DEV_INFO("%s function mode\n", 12134 IS_MF(bp) ? "multi" : "single"); 12135 12136 switch (bp->mf_mode) { 12137 case MULTI_FUNCTION_SD: 12138 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 12139 FUNC_MF_CFG_E1HOV_TAG_MASK; 12140 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 12141 bp->mf_ov = val; 12142 bp->path_has_ovlan = true; 12143 12144 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", 12145 func, bp->mf_ov, bp->mf_ov); 12146 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) || 12147 (bp->mf_sub_mode == SUB_MF_MODE_BD)) { 12148 dev_err(&bp->pdev->dev, 12149 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n", 12150 func); 12151 bp->path_has_ovlan = true; 12152 } else { 12153 dev_err(&bp->pdev->dev, 12154 "No valid MF OV for func %d, aborting\n", 12155 func); 12156 return -EPERM; 12157 } 12158 break; 12159 case MULTI_FUNCTION_AFEX: 12160 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); 12161 break; 12162 case MULTI_FUNCTION_SI: 12163 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", 12164 func); 12165 break; 12166 default: 12167 if (vn) { 12168 dev_err(&bp->pdev->dev, 12169 "VN %d is in a single function mode, aborting\n", 12170 vn); 12171 return -EPERM; 12172 } 12173 break; 12174 } 12175 12176 /* check if other port on the path needs ovlan: 12177 * Since MF configuration is shared between ports 12178 * Possible mixed modes are only 12179 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 12180 */ 12181 if (CHIP_MODE_IS_4_PORT(bp) && 12182 !bp->path_has_ovlan && 12183 !IS_MF(bp) && 12184 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 12185 u8 other_port = !BP_PORT(bp); 12186 u8 other_func = BP_PATH(bp) + 2*other_port; 12187 val = MF_CFG_RD(bp, 12188 func_mf_config[other_func].e1hov_tag); 12189 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 12190 bp->path_has_ovlan = true; 12191 } 12192 } 12193 12194 /* adjust igu_sb_cnt to MF for E1H */ 12195 if (CHIP_IS_E1H(bp) && IS_MF(bp)) 12196 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); 12197 12198 /* port info */ 12199 bnx2x_get_port_hwinfo(bp); 12200 12201 /* Get MAC addresses */ 12202 bnx2x_get_mac_hwinfo(bp); 12203 12204 bnx2x_get_cnic_info(bp); 12205 12206 return rc; 12207} 12208 12209static void bnx2x_read_fwinfo(struct bnx2x *bp) 12210{ 12211 char str_id[VENDOR_ID_LEN + 1]; 12212 unsigned int vpd_len, kw_len; 12213 u8 *vpd_data; 12214 int rodi; 12215 12216 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 12217 12218 vpd_data = pci_vpd_alloc(bp->pdev, &vpd_len); 12219 if (IS_ERR(vpd_data)) 12220 return; 12221 12222 rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len, 12223 PCI_VPD_RO_KEYWORD_MFR_ID, &kw_len); 12224 if (rodi < 0 || kw_len != VENDOR_ID_LEN) 12225 goto out_not_found; 12226 12227 /* vendor specific info */ 12228 snprintf(str_id, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 12229 if (!strncasecmp(str_id, &vpd_data[rodi], VENDOR_ID_LEN)) { 12230 rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len, 12231 PCI_VPD_RO_KEYWORD_VENDOR0, 12232 &kw_len); 12233 if (rodi >= 0 && kw_len < sizeof(bp->fw_ver)) { 12234 memcpy(bp->fw_ver, &vpd_data[rodi], kw_len); 12235 bp->fw_ver[kw_len] = ' '; 12236 } 12237 } 12238out_not_found: 12239 kfree(vpd_data); 12240} 12241 12242static void bnx2x_set_modes_bitmap(struct bnx2x *bp) 12243{ 12244 u32 flags = 0; 12245 12246 if (CHIP_REV_IS_FPGA(bp)) 12247 SET_FLAGS(flags, MODE_FPGA); 12248 else if (CHIP_REV_IS_EMUL(bp)) 12249 SET_FLAGS(flags, MODE_EMUL); 12250 else 12251 SET_FLAGS(flags, MODE_ASIC); 12252 12253 if (CHIP_MODE_IS_4_PORT(bp)) 12254 SET_FLAGS(flags, MODE_PORT4); 12255 else 12256 SET_FLAGS(flags, MODE_PORT2); 12257 12258 if (CHIP_IS_E2(bp)) 12259 SET_FLAGS(flags, MODE_E2); 12260 else if (CHIP_IS_E3(bp)) { 12261 SET_FLAGS(flags, MODE_E3); 12262 if (CHIP_REV(bp) == CHIP_REV_Ax) 12263 SET_FLAGS(flags, MODE_E3_A0); 12264 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 12265 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 12266 } 12267 12268 if (IS_MF(bp)) { 12269 SET_FLAGS(flags, MODE_MF); 12270 switch (bp->mf_mode) { 12271 case MULTI_FUNCTION_SD: 12272 SET_FLAGS(flags, MODE_MF_SD); 12273 break; 12274 case MULTI_FUNCTION_SI: 12275 SET_FLAGS(flags, MODE_MF_SI); 12276 break; 12277 case MULTI_FUNCTION_AFEX: 12278 SET_FLAGS(flags, MODE_MF_AFEX); 12279 break; 12280 } 12281 } else 12282 SET_FLAGS(flags, MODE_SF); 12283 12284#if defined(__LITTLE_ENDIAN) 12285 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 12286#else /*(__BIG_ENDIAN)*/ 12287 SET_FLAGS(flags, MODE_BIG_ENDIAN); 12288#endif 12289 INIT_MODE_FLAGS(bp) = flags; 12290} 12291 12292static int bnx2x_init_bp(struct bnx2x *bp) 12293{ 12294 int func; 12295 int rc; 12296 12297 mutex_init(&bp->port.phy_mutex); 12298 mutex_init(&bp->fw_mb_mutex); 12299 mutex_init(&bp->drv_info_mutex); 12300 sema_init(&bp->stats_lock, 1); 12301 bp->drv_info_mng_owner = false; 12302 INIT_LIST_HEAD(&bp->vlan_reg); 12303 12304 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 12305 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 12306 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 12307 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); 12308 if (IS_PF(bp)) { 12309 rc = bnx2x_get_hwinfo(bp); 12310 if (rc) 12311 return rc; 12312 } else { 12313 static const u8 zero_addr[ETH_ALEN] = {}; 12314 12315 eth_hw_addr_set(bp->dev, zero_addr); 12316 } 12317 12318 bnx2x_set_modes_bitmap(bp); 12319 12320 rc = bnx2x_alloc_mem_bp(bp); 12321 if (rc) 12322 return rc; 12323 12324 bnx2x_read_fwinfo(bp); 12325 12326 func = BP_FUNC(bp); 12327 12328 /* need to reset chip if undi was active */ 12329 if (IS_PF(bp) && !BP_NOMCP(bp)) { 12330 /* init fw_seq */ 12331 bp->fw_seq = 12332 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 12333 DRV_MSG_SEQ_NUMBER_MASK; 12334 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 12335 12336 rc = bnx2x_prev_unload(bp); 12337 if (rc) { 12338 bnx2x_free_mem_bp(bp); 12339 return rc; 12340 } 12341 } 12342 12343 if (CHIP_REV_IS_FPGA(bp)) 12344 dev_err(&bp->pdev->dev, "FPGA detected\n"); 12345 12346 if (BP_NOMCP(bp) && (func == 0)) 12347 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); 12348 12349 bp->disable_tpa = disable_tpa; 12350 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); 12351 /* Reduce memory usage in kdump environment by disabling TPA */ 12352 bp->disable_tpa |= is_kdump_kernel(); 12353 12354 /* Set TPA flags */ 12355 if (bp->disable_tpa) { 12356 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 12357 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 12358 } 12359 12360 if (CHIP_IS_E1(bp)) 12361 bp->dropless_fc = false; 12362 else 12363 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); 12364 12365 bp->mrrs = mrrs; 12366 12367 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; 12368 if (IS_VF(bp)) 12369 bp->rx_ring_size = MAX_RX_AVAIL; 12370 12371 /* make sure that the numbers are in the right granularity */ 12372 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 12373 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 12374 12375 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 12376 12377 timer_setup(&bp->timer, bnx2x_timer, 0); 12378 bp->timer.expires = jiffies + bp->current_interval; 12379 12380 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && 12381 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && 12382 SHMEM2_HAS(bp, dcbx_en) && 12383 SHMEM2_RD(bp, dcbx_lldp_params_offset) && 12384 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) && 12385 SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) { 12386 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 12387 bnx2x_dcbx_init_params(bp); 12388 } else { 12389 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); 12390 } 12391 12392 if (CHIP_IS_E1x(bp)) 12393 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 12394 else 12395 bp->cnic_base_cl_id = FP_SB_MAX_E2; 12396 12397 /* multiple tx priority */ 12398 if (IS_VF(bp)) 12399 bp->max_cos = 1; 12400 else if (CHIP_IS_E1x(bp)) 12401 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 12402 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 12403 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 12404 else if (CHIP_IS_E3B0(bp)) 12405 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 12406 else 12407 BNX2X_ERR("unknown chip %x revision %x\n", 12408 CHIP_NUM(bp), CHIP_REV(bp)); 12409 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); 12410 12411 /* We need at least one default status block for slow-path events, 12412 * second status block for the L2 queue, and a third status block for 12413 * CNIC if supported. 12414 */ 12415 if (IS_VF(bp)) 12416 bp->min_msix_vec_cnt = 1; 12417 else if (CNIC_SUPPORT(bp)) 12418 bp->min_msix_vec_cnt = 3; 12419 else /* PF w/o cnic */ 12420 bp->min_msix_vec_cnt = 2; 12421 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); 12422 12423 bp->dump_preset_idx = 1; 12424 12425 return rc; 12426} 12427 12428/**************************************************************************** 12429* General service functions 12430****************************************************************************/ 12431 12432/* 12433 * net_device service functions 12434 */ 12435 12436/* called with rtnl_lock */ 12437static int bnx2x_open(struct net_device *dev) 12438{ 12439 struct bnx2x *bp = netdev_priv(dev); 12440 int rc; 12441 12442 bp->stats_init = true; 12443 12444 netif_carrier_off(dev); 12445 12446 bnx2x_set_power_state(bp, PCI_D0); 12447 12448 /* If parity had happen during the unload, then attentions 12449 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 12450 * want the first function loaded on the current engine to 12451 * complete the recovery. 12452 * Parity recovery is only relevant for PF driver. 12453 */ 12454 if (IS_PF(bp)) { 12455 int other_engine = BP_PATH(bp) ? 0 : 1; 12456 bool other_load_status, load_status; 12457 bool global = false; 12458 12459 other_load_status = bnx2x_get_load_status(bp, other_engine); 12460 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 12461 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 12462 bnx2x_chk_parity_attn(bp, &global, true)) { 12463 do { 12464 /* If there are attentions and they are in a 12465 * global blocks, set the GLOBAL_RESET bit 12466 * regardless whether it will be this function 12467 * that will complete the recovery or not. 12468 */ 12469 if (global) 12470 bnx2x_set_reset_global(bp); 12471 12472 /* Only the first function on the current 12473 * engine should try to recover in open. In case 12474 * of attentions in global blocks only the first 12475 * in the chip should try to recover. 12476 */ 12477 if ((!load_status && 12478 (!global || !other_load_status)) && 12479 bnx2x_trylock_leader_lock(bp) && 12480 !bnx2x_leader_reset(bp)) { 12481 netdev_info(bp->dev, 12482 "Recovered in open\n"); 12483 break; 12484 } 12485 12486 /* recovery has failed... */ 12487 bnx2x_set_power_state(bp, PCI_D3hot); 12488 bp->recovery_state = BNX2X_RECOVERY_FAILED; 12489 12490 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" 12491 "If you still see this message after a few retries then power cycle is required.\n"); 12492 12493 return -EAGAIN; 12494 } while (0); 12495 } 12496 } 12497 12498 bp->recovery_state = BNX2X_RECOVERY_DONE; 12499 rc = bnx2x_nic_load(bp, LOAD_OPEN); 12500 if (rc) 12501 return rc; 12502 12503 return 0; 12504} 12505 12506/* called with rtnl_lock */ 12507static int bnx2x_close(struct net_device *dev) 12508{ 12509 struct bnx2x *bp = netdev_priv(dev); 12510 12511 /* Unload the driver, release IRQs */ 12512 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); 12513 12514 return 0; 12515} 12516 12517struct bnx2x_mcast_list_elem_group 12518{ 12519 struct list_head mcast_group_link; 12520 struct bnx2x_mcast_list_elem mcast_elems[]; 12521}; 12522 12523#define MCAST_ELEMS_PER_PG \ 12524 ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \ 12525 sizeof(struct bnx2x_mcast_list_elem)) 12526 12527static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list) 12528{ 12529 struct bnx2x_mcast_list_elem_group *current_mcast_group; 12530 12531 while (!list_empty(mcast_group_list)) { 12532 current_mcast_group = list_first_entry(mcast_group_list, 12533 struct bnx2x_mcast_list_elem_group, 12534 mcast_group_link); 12535 list_del(¤t_mcast_group->mcast_group_link); 12536 free_page((unsigned long)current_mcast_group); 12537 } 12538} 12539 12540static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 12541 struct bnx2x_mcast_ramrod_params *p, 12542 struct list_head *mcast_group_list) 12543{ 12544 struct bnx2x_mcast_list_elem *mc_mac; 12545 struct netdev_hw_addr *ha; 12546 struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL; 12547 int mc_count = netdev_mc_count(bp->dev); 12548 int offset = 0; 12549 12550 INIT_LIST_HEAD(&p->mcast_list); 12551 netdev_for_each_mc_addr(ha, bp->dev) { 12552 if (!offset) { 12553 current_mcast_group = 12554 (struct bnx2x_mcast_list_elem_group *) 12555 __get_free_page(GFP_ATOMIC); 12556 if (!current_mcast_group) { 12557 bnx2x_free_mcast_macs_list(mcast_group_list); 12558 BNX2X_ERR("Failed to allocate mc MAC list\n"); 12559 return -ENOMEM; 12560 } 12561 list_add(¤t_mcast_group->mcast_group_link, 12562 mcast_group_list); 12563 } 12564 mc_mac = ¤t_mcast_group->mcast_elems[offset]; 12565 mc_mac->mac = bnx2x_mc_addr(ha); 12566 list_add_tail(&mc_mac->link, &p->mcast_list); 12567 offset++; 12568 if (offset == MCAST_ELEMS_PER_PG) 12569 offset = 0; 12570 } 12571 p->mcast_list_len = mc_count; 12572 return 0; 12573} 12574 12575/** 12576 * bnx2x_set_uc_list - configure a new unicast MACs list. 12577 * 12578 * @bp: driver handle 12579 * 12580 * We will use zero (0) as a MAC type for these MACs. 12581 */ 12582static int bnx2x_set_uc_list(struct bnx2x *bp) 12583{ 12584 int rc; 12585 struct net_device *dev = bp->dev; 12586 struct netdev_hw_addr *ha; 12587 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; 12588 unsigned long ramrod_flags = 0; 12589 12590 /* First schedule a cleanup up of old configuration */ 12591 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 12592 if (rc < 0) { 12593 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 12594 return rc; 12595 } 12596 12597 netdev_for_each_uc_addr(ha, dev) { 12598 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 12599 BNX2X_UC_LIST_MAC, &ramrod_flags); 12600 if (rc == -EEXIST) { 12601 DP(BNX2X_MSG_SP, 12602 "Failed to schedule ADD operations: %d\n", rc); 12603 /* do not treat adding same MAC as error */ 12604 rc = 0; 12605 12606 } else if (rc < 0) { 12607 12608 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 12609 rc); 12610 return rc; 12611 } 12612 } 12613 12614 /* Execute the pending commands */ 12615 __set_bit(RAMROD_CONT, &ramrod_flags); 12616 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 12617 BNX2X_UC_LIST_MAC, &ramrod_flags); 12618} 12619 12620static int bnx2x_set_mc_list_e1x(struct bnx2x *bp) 12621{ 12622 LIST_HEAD(mcast_group_list); 12623 struct net_device *dev = bp->dev; 12624 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 12625 int rc = 0; 12626 12627 rparam.mcast_obj = &bp->mcast_obj; 12628 12629 /* first, clear all configured multicast MACs */ 12630 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 12631 if (rc < 0) { 12632 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); 12633 return rc; 12634 } 12635 12636 /* then, configure a new MACs list */ 12637 if (netdev_mc_count(dev)) { 12638 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); 12639 if (rc) 12640 return rc; 12641 12642 /* Now add the new MACs */ 12643 rc = bnx2x_config_mcast(bp, &rparam, 12644 BNX2X_MCAST_CMD_ADD); 12645 if (rc < 0) 12646 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 12647 rc); 12648 12649 bnx2x_free_mcast_macs_list(&mcast_group_list); 12650 } 12651 12652 return rc; 12653} 12654 12655static int bnx2x_set_mc_list(struct bnx2x *bp) 12656{ 12657 LIST_HEAD(mcast_group_list); 12658 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 12659 struct net_device *dev = bp->dev; 12660 int rc = 0; 12661 12662 /* On older adapters, we need to flush and re-add filters */ 12663 if (CHIP_IS_E1x(bp)) 12664 return bnx2x_set_mc_list_e1x(bp); 12665 12666 rparam.mcast_obj = &bp->mcast_obj; 12667 12668 if (netdev_mc_count(dev)) { 12669 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); 12670 if (rc) 12671 return rc; 12672 12673 /* Override the curently configured set of mc filters */ 12674 rc = bnx2x_config_mcast(bp, &rparam, 12675 BNX2X_MCAST_CMD_SET); 12676 if (rc < 0) 12677 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 12678 rc); 12679 12680 bnx2x_free_mcast_macs_list(&mcast_group_list); 12681 } else { 12682 /* If no mc addresses are required, flush the configuration */ 12683 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 12684 if (rc < 0) 12685 BNX2X_ERR("Failed to clear multicast configuration %d\n", 12686 rc); 12687 } 12688 12689 return rc; 12690} 12691 12692/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 12693static void bnx2x_set_rx_mode(struct net_device *dev) 12694{ 12695 struct bnx2x *bp = netdev_priv(dev); 12696 12697 if (bp->state != BNX2X_STATE_OPEN) { 12698 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 12699 return; 12700 } else { 12701 /* Schedule an SP task to handle rest of change */ 12702 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, 12703 NETIF_MSG_IFUP); 12704 } 12705} 12706 12707void bnx2x_set_rx_mode_inner(struct bnx2x *bp) 12708{ 12709 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 12710 12711 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 12712 12713 netif_addr_lock_bh(bp->dev); 12714 12715 if (bp->dev->flags & IFF_PROMISC) { 12716 rx_mode = BNX2X_RX_MODE_PROMISC; 12717 } else if ((bp->dev->flags & IFF_ALLMULTI) || 12718 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && 12719 CHIP_IS_E1(bp))) { 12720 rx_mode = BNX2X_RX_MODE_ALLMULTI; 12721 } else { 12722 if (IS_PF(bp)) { 12723 /* some multicasts */ 12724 if (bnx2x_set_mc_list(bp) < 0) 12725 rx_mode = BNX2X_RX_MODE_ALLMULTI; 12726 12727 /* release bh lock, as bnx2x_set_uc_list might sleep */ 12728 netif_addr_unlock_bh(bp->dev); 12729 if (bnx2x_set_uc_list(bp) < 0) 12730 rx_mode = BNX2X_RX_MODE_PROMISC; 12731 netif_addr_lock_bh(bp->dev); 12732 } else { 12733 /* configuring mcast to a vf involves sleeping (when we 12734 * wait for the pf's response). 12735 */ 12736 bnx2x_schedule_sp_rtnl(bp, 12737 BNX2X_SP_RTNL_VFPF_MCAST, 0); 12738 } 12739 } 12740 12741 bp->rx_mode = rx_mode; 12742 /* handle ISCSI SD mode */ 12743 if (IS_MF_ISCSI_ONLY(bp)) 12744 bp->rx_mode = BNX2X_RX_MODE_NONE; 12745 12746 /* Schedule the rx_mode command */ 12747 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 12748 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 12749 netif_addr_unlock_bh(bp->dev); 12750 return; 12751 } 12752 12753 if (IS_PF(bp)) { 12754 bnx2x_set_storm_rx_mode(bp); 12755 netif_addr_unlock_bh(bp->dev); 12756 } else { 12757 /* VF will need to request the PF to make this change, and so 12758 * the VF needs to release the bottom-half lock prior to the 12759 * request (as it will likely require sleep on the VF side) 12760 */ 12761 netif_addr_unlock_bh(bp->dev); 12762 bnx2x_vfpf_storm_rx_mode(bp); 12763 } 12764} 12765 12766/* called with rtnl_lock */ 12767static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 12768 int devad, u16 addr) 12769{ 12770 struct bnx2x *bp = netdev_priv(netdev); 12771 u16 value; 12772 int rc; 12773 12774 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 12775 prtad, devad, addr); 12776 12777 /* The HW expects different devad if CL22 is used */ 12778 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 12779 12780 bnx2x_acquire_phy_lock(bp); 12781 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 12782 bnx2x_release_phy_lock(bp); 12783 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 12784 12785 if (!rc) 12786 rc = value; 12787 return rc; 12788} 12789 12790/* called with rtnl_lock */ 12791static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 12792 u16 addr, u16 value) 12793{ 12794 struct bnx2x *bp = netdev_priv(netdev); 12795 int rc; 12796 12797 DP(NETIF_MSG_LINK, 12798 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", 12799 prtad, devad, addr, value); 12800 12801 /* The HW expects different devad if CL22 is used */ 12802 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 12803 12804 bnx2x_acquire_phy_lock(bp); 12805 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 12806 bnx2x_release_phy_lock(bp); 12807 return rc; 12808} 12809 12810/* called with rtnl_lock */ 12811static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 12812{ 12813 struct bnx2x *bp = netdev_priv(dev); 12814 struct mii_ioctl_data *mdio = if_mii(ifr); 12815 12816 if (!netif_running(dev)) 12817 return -EAGAIN; 12818 12819 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 12820 mdio->phy_id, mdio->reg_num, mdio->val_in); 12821 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 12822} 12823 12824static int bnx2x_validate_addr(struct net_device *dev) 12825{ 12826 struct bnx2x *bp = netdev_priv(dev); 12827 12828 /* query the bulletin board for mac address configured by the PF */ 12829 if (IS_VF(bp)) 12830 bnx2x_sample_bulletin(bp); 12831 12832 if (!is_valid_ether_addr(dev->dev_addr)) { 12833 BNX2X_ERR("Non-valid Ethernet address\n"); 12834 return -EADDRNOTAVAIL; 12835 } 12836 return 0; 12837} 12838 12839static int bnx2x_get_phys_port_id(struct net_device *netdev, 12840 struct netdev_phys_item_id *ppid) 12841{ 12842 struct bnx2x *bp = netdev_priv(netdev); 12843 12844 if (!(bp->flags & HAS_PHYS_PORT_ID)) 12845 return -EOPNOTSUPP; 12846 12847 ppid->id_len = sizeof(bp->phys_port_id); 12848 memcpy(ppid->id, bp->phys_port_id, ppid->id_len); 12849 12850 return 0; 12851} 12852 12853static netdev_features_t bnx2x_features_check(struct sk_buff *skb, 12854 struct net_device *dev, 12855 netdev_features_t features) 12856{ 12857 /* 12858 * A skb with gso_size + header length > 9700 will cause a 12859 * firmware panic. Drop GSO support. 12860 * 12861 * Eventually the upper layer should not pass these packets down. 12862 * 12863 * For speed, if the gso_size is <= 9000, assume there will 12864 * not be 700 bytes of headers and pass it through. Only do a 12865 * full (slow) validation if the gso_size is > 9000. 12866 * 12867 * (Due to the way SKB_BY_FRAGS works this will also do a full 12868 * validation in that case.) 12869 */ 12870 if (unlikely(skb_is_gso(skb) && 12871 (skb_shinfo(skb)->gso_size > 9000) && 12872 !skb_gso_validate_mac_len(skb, 9700))) 12873 features &= ~NETIF_F_GSO_MASK; 12874 12875 features = vlan_features_check(skb, features); 12876 return vxlan_features_check(skb, features); 12877} 12878 12879static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add) 12880{ 12881 int rc; 12882 12883 if (IS_PF(bp)) { 12884 unsigned long ramrod_flags = 0; 12885 12886 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 12887 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj, 12888 add, &ramrod_flags); 12889 } else { 12890 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add); 12891 } 12892 12893 return rc; 12894} 12895 12896static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp) 12897{ 12898 struct bnx2x_vlan_entry *vlan; 12899 int rc = 0; 12900 12901 /* Configure all non-configured entries */ 12902 list_for_each_entry(vlan, &bp->vlan_reg, link) { 12903 if (vlan->hw) 12904 continue; 12905 12906 if (bp->vlan_cnt >= bp->vlan_credit) 12907 return -ENOBUFS; 12908 12909 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); 12910 if (rc) { 12911 BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid); 12912 return rc; 12913 } 12914 12915 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid); 12916 vlan->hw = true; 12917 bp->vlan_cnt++; 12918 } 12919 12920 return 0; 12921} 12922 12923static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode) 12924{ 12925 bool need_accept_any_vlan; 12926 12927 need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp); 12928 12929 if (bp->accept_any_vlan != need_accept_any_vlan) { 12930 bp->accept_any_vlan = need_accept_any_vlan; 12931 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n", 12932 bp->accept_any_vlan ? "raised" : "cleared"); 12933 if (set_rx_mode) { 12934 if (IS_PF(bp)) 12935 bnx2x_set_rx_mode_inner(bp); 12936 else 12937 bnx2x_vfpf_storm_rx_mode(bp); 12938 } 12939 } 12940} 12941 12942int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp) 12943{ 12944 /* Don't set rx mode here. Our caller will do it. */ 12945 bnx2x_vlan_configure(bp, false); 12946 12947 return 0; 12948} 12949 12950static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 12951{ 12952 struct bnx2x *bp = netdev_priv(dev); 12953 struct bnx2x_vlan_entry *vlan; 12954 12955 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid); 12956 12957 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL); 12958 if (!vlan) 12959 return -ENOMEM; 12960 12961 vlan->vid = vid; 12962 vlan->hw = false; 12963 list_add_tail(&vlan->link, &bp->vlan_reg); 12964 12965 if (netif_running(dev)) 12966 bnx2x_vlan_configure(bp, true); 12967 12968 return 0; 12969} 12970 12971static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 12972{ 12973 struct bnx2x *bp = netdev_priv(dev); 12974 struct bnx2x_vlan_entry *vlan; 12975 bool found = false; 12976 int rc = 0; 12977 12978 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid); 12979 12980 list_for_each_entry(vlan, &bp->vlan_reg, link) 12981 if (vlan->vid == vid) { 12982 found = true; 12983 break; 12984 } 12985 12986 if (!found) { 12987 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid); 12988 return -EINVAL; 12989 } 12990 12991 if (netif_running(dev) && vlan->hw) { 12992 rc = __bnx2x_vlan_configure_vid(bp, vid, false); 12993 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid); 12994 bp->vlan_cnt--; 12995 } 12996 12997 list_del(&vlan->link); 12998 kfree(vlan); 12999 13000 if (netif_running(dev)) 13001 bnx2x_vlan_configure(bp, true); 13002 13003 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc); 13004 13005 return rc; 13006} 13007 13008static const struct net_device_ops bnx2x_netdev_ops = { 13009 .ndo_open = bnx2x_open, 13010 .ndo_stop = bnx2x_close, 13011 .ndo_start_xmit = bnx2x_start_xmit, 13012 .ndo_select_queue = bnx2x_select_queue, 13013 .ndo_set_rx_mode = bnx2x_set_rx_mode, 13014 .ndo_set_mac_address = bnx2x_change_mac_addr, 13015 .ndo_validate_addr = bnx2x_validate_addr, 13016 .ndo_eth_ioctl = bnx2x_ioctl, 13017 .ndo_change_mtu = bnx2x_change_mtu, 13018 .ndo_fix_features = bnx2x_fix_features, 13019 .ndo_set_features = bnx2x_set_features, 13020 .ndo_tx_timeout = bnx2x_tx_timeout, 13021 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid, 13022 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid, 13023 .ndo_setup_tc = __bnx2x_setup_tc, 13024#ifdef CONFIG_BNX2X_SRIOV 13025 .ndo_set_vf_mac = bnx2x_set_vf_mac, 13026 .ndo_set_vf_vlan = bnx2x_set_vf_vlan, 13027 .ndo_get_vf_config = bnx2x_get_vf_config, 13028 .ndo_set_vf_spoofchk = bnx2x_set_vf_spoofchk, 13029#endif 13030#ifdef NETDEV_FCOE_WWNN 13031 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 13032#endif 13033 13034 .ndo_get_phys_port_id = bnx2x_get_phys_port_id, 13035 .ndo_set_vf_link_state = bnx2x_set_vf_link_state, 13036 .ndo_features_check = bnx2x_features_check, 13037 .ndo_hwtstamp_get = bnx2x_hwtstamp_get, 13038 .ndo_hwtstamp_set = bnx2x_hwtstamp_set, 13039}; 13040 13041static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, 13042 struct net_device *dev, unsigned long board_type) 13043{ 13044 int rc; 13045 u32 pci_cfg_dword; 13046 bool chip_is_e1x = (board_type == BCM57710 || 13047 board_type == BCM57711 || 13048 board_type == BCM57711E); 13049 13050 SET_NETDEV_DEV(dev, &pdev->dev); 13051 13052 bp->dev = dev; 13053 bp->pdev = pdev; 13054 13055 rc = pci_enable_device(pdev); 13056 if (rc) { 13057 dev_err(&bp->pdev->dev, 13058 "Cannot enable PCI device, aborting\n"); 13059 goto err_out; 13060 } 13061 13062 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 13063 dev_err(&bp->pdev->dev, 13064 "Cannot find PCI device base address, aborting\n"); 13065 rc = -ENODEV; 13066 goto err_out_disable; 13067 } 13068 13069 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 13070 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); 13071 rc = -ENODEV; 13072 goto err_out_disable; 13073 } 13074 13075 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); 13076 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == 13077 PCICFG_REVESION_ID_ERROR_VAL) { 13078 pr_err("PCI device error, probably due to fan failure, aborting\n"); 13079 rc = -ENODEV; 13080 goto err_out_disable; 13081 } 13082 13083 if (atomic_read(&pdev->enable_cnt) == 1) { 13084 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 13085 if (rc) { 13086 dev_err(&bp->pdev->dev, 13087 "Cannot obtain PCI resources, aborting\n"); 13088 goto err_out_disable; 13089 } 13090 13091 pci_set_master(pdev); 13092 pci_save_state(pdev); 13093 } 13094 13095 if (IS_PF(bp)) { 13096 if (!pdev->pm_cap) { 13097 dev_err(&bp->pdev->dev, 13098 "Cannot find power management capability, aborting\n"); 13099 rc = -EIO; 13100 goto err_out_release; 13101 } 13102 } 13103 13104 if (!pci_is_pcie(pdev)) { 13105 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 13106 rc = -EIO; 13107 goto err_out_release; 13108 } 13109 13110 rc = dma_set_mask_and_coherent(&bp->pdev->dev, DMA_BIT_MASK(64)); 13111 if (rc) { 13112 dev_err(&bp->pdev->dev, "System does not support DMA, aborting\n"); 13113 goto err_out_release; 13114 } 13115 13116 dev->mem_start = pci_resource_start(pdev, 0); 13117 dev->base_addr = dev->mem_start; 13118 dev->mem_end = pci_resource_end(pdev, 0); 13119 13120 dev->irq = pdev->irq; 13121 13122 bp->regview = pci_ioremap_bar(pdev, 0); 13123 if (!bp->regview) { 13124 dev_err(&bp->pdev->dev, 13125 "Cannot map register space, aborting\n"); 13126 rc = -ENOMEM; 13127 goto err_out_release; 13128 } 13129 13130 /* In E1/E1H use pci device function given by kernel. 13131 * In E2/E3 read physical function from ME register since these chips 13132 * support Physical Device Assignment where kernel BDF maybe arbitrary 13133 * (depending on hypervisor). 13134 */ 13135 if (chip_is_e1x) { 13136 bp->pf_num = PCI_FUNC(pdev->devfn); 13137 } else { 13138 /* chip is E2/3*/ 13139 pci_read_config_dword(bp->pdev, 13140 PCICFG_ME_REGISTER, &pci_cfg_dword); 13141 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 13142 ME_REG_ABS_PF_NUM_SHIFT); 13143 } 13144 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); 13145 13146 /* clean indirect addresses */ 13147 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 13148 PCICFG_VENDOR_ID_OFFSET); 13149 13150 /* Set PCIe reset type to fundamental for EEH recovery */ 13151 pdev->needs_freset = 1; 13152 13153 /* 13154 * Clean the following indirect addresses for all functions since it 13155 * is not used by the driver. 13156 */ 13157 if (IS_PF(bp)) { 13158 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 13159 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 13160 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 13161 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 13162 13163 if (chip_is_e1x) { 13164 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 13165 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 13166 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 13167 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 13168 } 13169 13170 /* Enable internal target-read (in case we are probed after PF 13171 * FLR). Must be done prior to any BAR read access. Only for 13172 * 57712 and up 13173 */ 13174 if (!chip_is_e1x) 13175 REG_WR(bp, 13176 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 13177 } 13178 13179 dev->watchdog_timeo = TX_TIMEOUT; 13180 13181 dev->netdev_ops = &bnx2x_netdev_ops; 13182 bnx2x_set_ethtool_ops(bp, dev); 13183 13184 dev->priv_flags |= IFF_UNICAST_FLT; 13185 13186 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 13187 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 13188 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | NETIF_F_GRO_HW | 13189 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; 13190 if (!chip_is_e1x) { 13191 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | 13192 NETIF_F_GSO_IPXIP4 | 13193 NETIF_F_GSO_UDP_TUNNEL | 13194 NETIF_F_GSO_UDP_TUNNEL_CSUM | 13195 NETIF_F_GSO_PARTIAL; 13196 13197 dev->hw_enc_features = 13198 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 13199 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 13200 NETIF_F_GSO_IPXIP4 | 13201 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | 13202 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM | 13203 NETIF_F_GSO_PARTIAL; 13204 13205 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM | 13206 NETIF_F_GSO_UDP_TUNNEL_CSUM; 13207 13208 if (IS_PF(bp)) 13209 dev->udp_tunnel_nic_info = &bnx2x_udp_tunnels; 13210 } 13211 13212 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 13213 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 13214 13215 if (IS_PF(bp)) { 13216 if (chip_is_e1x) 13217 bp->accept_any_vlan = true; 13218 else 13219 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 13220 } 13221 /* For VF we'll know whether to enable VLAN filtering after 13222 * getting a response to CHANNEL_TLV_ACQUIRE from PF. 13223 */ 13224 13225 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; 13226 dev->features |= NETIF_F_HIGHDMA; 13227 if (dev->features & NETIF_F_LRO) 13228 dev->features &= ~NETIF_F_GRO_HW; 13229 13230 /* Add Loopback capability to the device */ 13231 dev->hw_features |= NETIF_F_LOOPBACK; 13232 13233#ifdef BCM_DCBNL 13234 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 13235#endif 13236 13237 /* MTU range, 46 - 9600 */ 13238 dev->min_mtu = ETH_MIN_PACKET_SIZE; 13239 dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE; 13240 13241 /* get_port_hwinfo() will set prtad and mmds properly */ 13242 bp->mdio.prtad = MDIO_PRTAD_NONE; 13243 bp->mdio.mmds = 0; 13244 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 13245 bp->mdio.dev = dev; 13246 bp->mdio.mdio_read = bnx2x_mdio_read; 13247 bp->mdio.mdio_write = bnx2x_mdio_write; 13248 13249 return 0; 13250 13251err_out_release: 13252 if (atomic_read(&pdev->enable_cnt) == 1) 13253 pci_release_regions(pdev); 13254 13255err_out_disable: 13256 pci_disable_device(pdev); 13257 13258err_out: 13259 return rc; 13260} 13261 13262static int bnx2x_check_firmware(struct bnx2x *bp) 13263{ 13264 const struct firmware *firmware = bp->firmware; 13265 struct bnx2x_fw_file_hdr *fw_hdr; 13266 struct bnx2x_fw_file_section *sections; 13267 u32 offset, len, num_ops; 13268 __be16 *ops_offsets; 13269 int i; 13270 const u8 *fw_ver; 13271 13272 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { 13273 BNX2X_ERR("Wrong FW size\n"); 13274 return -EINVAL; 13275 } 13276 13277 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 13278 sections = (struct bnx2x_fw_file_section *)fw_hdr; 13279 13280 /* Make sure none of the offsets and sizes make us read beyond 13281 * the end of the firmware data */ 13282 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 13283 offset = be32_to_cpu(sections[i].offset); 13284 len = be32_to_cpu(sections[i].len); 13285 if (offset + len > firmware->size) { 13286 BNX2X_ERR("Section %d length is out of bounds\n", i); 13287 return -EINVAL; 13288 } 13289 } 13290 13291 /* Likewise for the init_ops offsets */ 13292 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 13293 ops_offsets = (__force __be16 *)(firmware->data + offset); 13294 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 13295 13296 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 13297 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 13298 BNX2X_ERR("Section offset %d is out of bounds\n", i); 13299 return -EINVAL; 13300 } 13301 } 13302 13303 /* Check FW version */ 13304 offset = be32_to_cpu(fw_hdr->fw_version.offset); 13305 fw_ver = firmware->data + offset; 13306 if (fw_ver[0] != bp->fw_major || fw_ver[1] != bp->fw_minor || 13307 fw_ver[2] != bp->fw_rev || fw_ver[3] != bp->fw_eng) { 13308 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 13309 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], 13310 bp->fw_major, bp->fw_minor, bp->fw_rev, bp->fw_eng); 13311 return -EINVAL; 13312 } 13313 13314 return 0; 13315} 13316 13317static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 13318{ 13319 const __be32 *source = (const __be32 *)_source; 13320 u32 *target = (u32 *)_target; 13321 u32 i; 13322 13323 for (i = 0; i < n/4; i++) 13324 target[i] = be32_to_cpu(source[i]); 13325} 13326 13327/* 13328 Ops array is stored in the following format: 13329 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 13330 */ 13331static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 13332{ 13333 const __be32 *source = (const __be32 *)_source; 13334 struct raw_op *target = (struct raw_op *)_target; 13335 u32 i, j, tmp; 13336 13337 for (i = 0, j = 0; i < n/8; i++, j += 2) { 13338 tmp = be32_to_cpu(source[j]); 13339 target[i].op = (tmp >> 24) & 0xff; 13340 target[i].offset = tmp & 0xffffff; 13341 target[i].raw_data = be32_to_cpu(source[j + 1]); 13342 } 13343} 13344 13345/* IRO array is stored in the following format: 13346 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 13347 */ 13348static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 13349{ 13350 const __be32 *source = (const __be32 *)_source; 13351 struct iro *target = (struct iro *)_target; 13352 u32 i, j, tmp; 13353 13354 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 13355 target[i].base = be32_to_cpu(source[j]); 13356 j++; 13357 tmp = be32_to_cpu(source[j]); 13358 target[i].m1 = (tmp >> 16) & 0xffff; 13359 target[i].m2 = tmp & 0xffff; 13360 j++; 13361 tmp = be32_to_cpu(source[j]); 13362 target[i].m3 = (tmp >> 16) & 0xffff; 13363 target[i].size = tmp & 0xffff; 13364 j++; 13365 } 13366} 13367 13368static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 13369{ 13370 const __be16 *source = (const __be16 *)_source; 13371 u16 *target = (u16 *)_target; 13372 u32 i; 13373 13374 for (i = 0; i < n/2; i++) 13375 target[i] = be16_to_cpu(source[i]); 13376} 13377 13378#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 13379do { \ 13380 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 13381 bp->arr = kmalloc(len, GFP_KERNEL); \ 13382 if (!bp->arr) \ 13383 goto lbl; \ 13384 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 13385 (u8 *)bp->arr, len); \ 13386} while (0) 13387 13388static int bnx2x_init_firmware(struct bnx2x *bp) 13389{ 13390 const char *fw_file_name, *fw_file_name_v15; 13391 struct bnx2x_fw_file_hdr *fw_hdr; 13392 int rc; 13393 13394 if (bp->firmware) 13395 return 0; 13396 13397 if (CHIP_IS_E1(bp)) { 13398 fw_file_name = FW_FILE_NAME_E1; 13399 fw_file_name_v15 = FW_FILE_NAME_E1_V15; 13400 } else if (CHIP_IS_E1H(bp)) { 13401 fw_file_name = FW_FILE_NAME_E1H; 13402 fw_file_name_v15 = FW_FILE_NAME_E1H_V15; 13403 } else if (!CHIP_IS_E1x(bp)) { 13404 fw_file_name = FW_FILE_NAME_E2; 13405 fw_file_name_v15 = FW_FILE_NAME_E2_V15; 13406 } else { 13407 BNX2X_ERR("Unsupported chip revision\n"); 13408 return -EINVAL; 13409 } 13410 13411 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 13412 13413 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); 13414 if (rc) { 13415 BNX2X_DEV_INFO("Trying to load older fw %s\n", fw_file_name_v15); 13416 13417 /* try to load prev version */ 13418 rc = request_firmware(&bp->firmware, fw_file_name_v15, &bp->pdev->dev); 13419 13420 if (rc) 13421 goto request_firmware_exit; 13422 13423 bp->fw_rev = BCM_5710_FW_REVISION_VERSION_V15; 13424 } else { 13425 bp->fw_cap |= FW_CAP_INVALIDATE_VF_FP_HSI; 13426 bp->fw_rev = BCM_5710_FW_REVISION_VERSION; 13427 } 13428 13429 bp->fw_major = BCM_5710_FW_MAJOR_VERSION; 13430 bp->fw_minor = BCM_5710_FW_MINOR_VERSION; 13431 bp->fw_eng = BCM_5710_FW_ENGINEERING_VERSION; 13432 13433 rc = bnx2x_check_firmware(bp); 13434 if (rc) { 13435 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 13436 goto request_firmware_exit; 13437 } 13438 13439 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 13440 13441 /* Initialize the pointers to the init arrays */ 13442 /* Blob */ 13443 rc = -ENOMEM; 13444 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 13445 13446 /* Opcodes */ 13447 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 13448 13449 /* Offsets */ 13450 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 13451 be16_to_cpu_n); 13452 13453 /* STORMs firmware */ 13454 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13455 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 13456 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 13457 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 13458 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13459 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 13460 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 13461 be32_to_cpu(fw_hdr->usem_pram_data.offset); 13462 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13463 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 13464 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 13465 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 13466 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13467 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 13468 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 13469 be32_to_cpu(fw_hdr->csem_pram_data.offset); 13470 /* IRO */ 13471 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 13472 13473 return 0; 13474 13475iro_alloc_err: 13476 kfree(bp->init_ops_offsets); 13477init_offsets_alloc_err: 13478 kfree(bp->init_ops); 13479init_ops_alloc_err: 13480 kfree(bp->init_data); 13481request_firmware_exit: 13482 release_firmware(bp->firmware); 13483 bp->firmware = NULL; 13484 13485 return rc; 13486} 13487 13488static void bnx2x_release_firmware(struct bnx2x *bp) 13489{ 13490 kfree(bp->init_ops_offsets); 13491 kfree(bp->init_ops); 13492 kfree(bp->init_data); 13493 release_firmware(bp->firmware); 13494 bp->firmware = NULL; 13495} 13496 13497static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 13498 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 13499 .init_hw_cmn = bnx2x_init_hw_common, 13500 .init_hw_port = bnx2x_init_hw_port, 13501 .init_hw_func = bnx2x_init_hw_func, 13502 13503 .reset_hw_cmn = bnx2x_reset_common, 13504 .reset_hw_port = bnx2x_reset_port, 13505 .reset_hw_func = bnx2x_reset_func, 13506 13507 .gunzip_init = bnx2x_gunzip_init, 13508 .gunzip_end = bnx2x_gunzip_end, 13509 13510 .init_fw = bnx2x_init_firmware, 13511 .release_fw = bnx2x_release_firmware, 13512}; 13513 13514void bnx2x__init_func_obj(struct bnx2x *bp) 13515{ 13516 /* Prepare DMAE related driver resources */ 13517 bnx2x_setup_dmae(bp); 13518 13519 bnx2x_init_func_obj(bp, &bp->func_obj, 13520 bnx2x_sp(bp, func_rdata), 13521 bnx2x_sp_mapping(bp, func_rdata), 13522 bnx2x_sp(bp, func_afex_rdata), 13523 bnx2x_sp_mapping(bp, func_afex_rdata), 13524 &bnx2x_func_sp_drv); 13525} 13526 13527/* must be called after sriov-enable */ 13528static int bnx2x_set_qm_cid_count(struct bnx2x *bp) 13529{ 13530 int cid_count = BNX2X_L2_MAX_CID(bp); 13531 13532 if (IS_SRIOV(bp)) 13533 cid_count += BNX2X_VF_CIDS; 13534 13535 if (CNIC_SUPPORT(bp)) 13536 cid_count += CNIC_CID_MAX; 13537 13538 return roundup(cid_count, QM_CID_ROUND); 13539} 13540 13541/** 13542 * bnx2x_get_num_non_def_sbs - return the number of none default SBs 13543 * @pdev: pci device 13544 * @cnic_cnt: count 13545 * 13546 */ 13547static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt) 13548{ 13549 int index; 13550 u16 control = 0; 13551 13552 /* 13553 * If MSI-X is not supported - return number of SBs needed to support 13554 * one fast path queue: one FP queue + SB for CNIC 13555 */ 13556 if (!pdev->msix_cap) { 13557 dev_info(&pdev->dev, "no msix capability found\n"); 13558 return 1 + cnic_cnt; 13559 } 13560 dev_info(&pdev->dev, "msix capability found\n"); 13561 13562 /* 13563 * The value in the PCI configuration space is the index of the last 13564 * entry, namely one less than the actual size of the table, which is 13565 * exactly what we want to return from this function: number of all SBs 13566 * without the default SB. 13567 * For VFs there is no default SB, then we return (index+1). 13568 */ 13569 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control); 13570 13571 index = control & PCI_MSIX_FLAGS_QSIZE; 13572 13573 return index; 13574} 13575 13576static int set_max_cos_est(int chip_id) 13577{ 13578 switch (chip_id) { 13579 case BCM57710: 13580 case BCM57711: 13581 case BCM57711E: 13582 return BNX2X_MULTI_TX_COS_E1X; 13583 case BCM57712: 13584 case BCM57712_MF: 13585 return BNX2X_MULTI_TX_COS_E2_E3A0; 13586 case BCM57800: 13587 case BCM57800_MF: 13588 case BCM57810: 13589 case BCM57810_MF: 13590 case BCM57840_4_10: 13591 case BCM57840_2_20: 13592 case BCM57840_O: 13593 case BCM57840_MFO: 13594 case BCM57840_MF: 13595 case BCM57811: 13596 case BCM57811_MF: 13597 return BNX2X_MULTI_TX_COS_E3B0; 13598 case BCM57712_VF: 13599 case BCM57800_VF: 13600 case BCM57810_VF: 13601 case BCM57840_VF: 13602 case BCM57811_VF: 13603 return 1; 13604 default: 13605 pr_err("Unknown board_type (%d), aborting\n", chip_id); 13606 return -ENODEV; 13607 } 13608} 13609 13610static int set_is_vf(int chip_id) 13611{ 13612 switch (chip_id) { 13613 case BCM57712_VF: 13614 case BCM57800_VF: 13615 case BCM57810_VF: 13616 case BCM57840_VF: 13617 case BCM57811_VF: 13618 return true; 13619 default: 13620 return false; 13621 } 13622} 13623 13624/* nig_tsgen registers relative address */ 13625#define tsgen_ctrl 0x0 13626#define tsgen_freecount 0x10 13627#define tsgen_synctime_t0 0x20 13628#define tsgen_offset_t0 0x28 13629#define tsgen_drift_t0 0x30 13630#define tsgen_synctime_t1 0x58 13631#define tsgen_offset_t1 0x60 13632#define tsgen_drift_t1 0x68 13633 13634/* FW workaround for setting drift */ 13635static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, 13636 int best_val, int best_period) 13637{ 13638 struct bnx2x_func_state_params func_params = {NULL}; 13639 struct bnx2x_func_set_timesync_params *set_timesync_params = 13640 &func_params.params.set_timesync; 13641 13642 /* Prepare parameters for function state transitions */ 13643 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 13644 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 13645 13646 func_params.f_obj = &bp->func_obj; 13647 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; 13648 13649 /* Function parameters */ 13650 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET; 13651 set_timesync_params->offset_cmd = TS_OFFSET_KEEP; 13652 set_timesync_params->add_sub_drift_adjust_value = 13653 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE; 13654 set_timesync_params->drift_adjust_value = best_val; 13655 set_timesync_params->drift_adjust_period = best_period; 13656 13657 return bnx2x_func_state_change(bp, &func_params); 13658} 13659 13660static int bnx2x_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 13661{ 13662 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13663 int rc; 13664 int drift_dir = 1; 13665 int val, period, period1, period2, dif, dif1, dif2; 13666 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0; 13667 s32 ppb = scaled_ppm_to_ppb(scaled_ppm); 13668 13669 DP(BNX2X_MSG_PTP, "PTP adjfine called, ppb = %d\n", ppb); 13670 13671 if (!netif_running(bp->dev)) { 13672 DP(BNX2X_MSG_PTP, 13673 "PTP adjfine called while the interface is down\n"); 13674 return -ENETDOWN; 13675 } 13676 13677 if (ppb < 0) { 13678 ppb = -ppb; 13679 drift_dir = 0; 13680 } 13681 13682 if (ppb == 0) { 13683 best_val = 1; 13684 best_period = 0x1FFFFFF; 13685 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) { 13686 best_val = 31; 13687 best_period = 1; 13688 } else { 13689 /* Changed not to allow val = 8, 16, 24 as these values 13690 * are not supported in workaround. 13691 */ 13692 for (val = 0; val <= 31; val++) { 13693 if ((val & 0x7) == 0) 13694 continue; 13695 period1 = val * 1000000 / ppb; 13696 period2 = period1 + 1; 13697 if (period1 != 0) 13698 dif1 = ppb - (val * 1000000 / period1); 13699 else 13700 dif1 = BNX2X_MAX_PHC_DRIFT; 13701 if (dif1 < 0) 13702 dif1 = -dif1; 13703 dif2 = ppb - (val * 1000000 / period2); 13704 if (dif2 < 0) 13705 dif2 = -dif2; 13706 dif = (dif1 < dif2) ? dif1 : dif2; 13707 period = (dif1 < dif2) ? period1 : period2; 13708 if (dif < best_dif) { 13709 best_dif = dif; 13710 best_val = val; 13711 best_period = period; 13712 } 13713 } 13714 } 13715 13716 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, 13717 best_period); 13718 if (rc) { 13719 BNX2X_ERR("Failed to set drift\n"); 13720 return -EFAULT; 13721 } 13722 13723 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val, 13724 best_period); 13725 13726 return 0; 13727} 13728 13729static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 13730{ 13731 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13732 13733 if (!netif_running(bp->dev)) { 13734 DP(BNX2X_MSG_PTP, 13735 "PTP adjtime called while the interface is down\n"); 13736 return -ENETDOWN; 13737 } 13738 13739 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta); 13740 13741 timecounter_adjtime(&bp->timecounter, delta); 13742 13743 return 0; 13744} 13745 13746static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 13747{ 13748 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13749 u64 ns; 13750 13751 if (!netif_running(bp->dev)) { 13752 DP(BNX2X_MSG_PTP, 13753 "PTP gettime called while the interface is down\n"); 13754 return -ENETDOWN; 13755 } 13756 13757 ns = timecounter_read(&bp->timecounter); 13758 13759 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns); 13760 13761 *ts = ns_to_timespec64(ns); 13762 13763 return 0; 13764} 13765 13766static int bnx2x_ptp_settime(struct ptp_clock_info *ptp, 13767 const struct timespec64 *ts) 13768{ 13769 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13770 u64 ns; 13771 13772 if (!netif_running(bp->dev)) { 13773 DP(BNX2X_MSG_PTP, 13774 "PTP settime called while the interface is down\n"); 13775 return -ENETDOWN; 13776 } 13777 13778 ns = timespec64_to_ns(ts); 13779 13780 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns); 13781 13782 /* Re-init the timecounter */ 13783 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); 13784 13785 return 0; 13786} 13787 13788/* Enable (or disable) ancillary features of the phc subsystem */ 13789static int bnx2x_ptp_enable(struct ptp_clock_info *ptp, 13790 struct ptp_clock_request *rq, int on) 13791{ 13792 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13793 13794 BNX2X_ERR("PHC ancillary features are not supported\n"); 13795 return -ENOTSUPP; 13796} 13797 13798void bnx2x_register_phc(struct bnx2x *bp) 13799{ 13800 /* Fill the ptp_clock_info struct and register PTP clock*/ 13801 bp->ptp_clock_info.owner = THIS_MODULE; 13802 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); 13803 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ 13804 bp->ptp_clock_info.n_alarm = 0; 13805 bp->ptp_clock_info.n_ext_ts = 0; 13806 bp->ptp_clock_info.n_per_out = 0; 13807 bp->ptp_clock_info.pps = 0; 13808 bp->ptp_clock_info.adjfine = bnx2x_ptp_adjfine; 13809 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; 13810 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; 13811 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; 13812 bp->ptp_clock_info.enable = bnx2x_ptp_enable; 13813 13814 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); 13815 if (IS_ERR(bp->ptp_clock)) { 13816 bp->ptp_clock = NULL; 13817 BNX2X_ERR("PTP clock registration failed\n"); 13818 } 13819} 13820 13821static int bnx2x_init_one(struct pci_dev *pdev, 13822 const struct pci_device_id *ent) 13823{ 13824 struct net_device *dev = NULL; 13825 struct bnx2x *bp; 13826 int rc, max_non_def_sbs; 13827 int rx_count, tx_count, rss_count, doorbell_size; 13828 int max_cos_est; 13829 bool is_vf; 13830 int cnic_cnt; 13831 13832 /* Management FW 'remembers' living interfaces. Allow it some time 13833 * to forget previously living interfaces, allowing a proper re-load. 13834 */ 13835 if (is_kdump_kernel()) { 13836 ktime_t now = ktime_get_boottime(); 13837 ktime_t fw_ready_time = ktime_set(5, 0); 13838 13839 if (ktime_before(now, fw_ready_time)) 13840 msleep(ktime_ms_delta(fw_ready_time, now)); 13841 } 13842 13843 /* An estimated maximum supported CoS number according to the chip 13844 * version. 13845 * We will try to roughly estimate the maximum number of CoSes this chip 13846 * may support in order to minimize the memory allocated for Tx 13847 * netdev_queue's. This number will be accurately calculated during the 13848 * initialization of bp->max_cos based on the chip versions AND chip 13849 * revision in the bnx2x_init_bp(). 13850 */ 13851 max_cos_est = set_max_cos_est(ent->driver_data); 13852 if (max_cos_est < 0) 13853 return max_cos_est; 13854 is_vf = set_is_vf(ent->driver_data); 13855 cnic_cnt = is_vf ? 0 : 1; 13856 13857 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt); 13858 13859 /* add another SB for VF as it has no default SB */ 13860 max_non_def_sbs += is_vf ? 1 : 0; 13861 13862 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 13863 rss_count = max_non_def_sbs - cnic_cnt; 13864 13865 if (rss_count < 1) 13866 return -EINVAL; 13867 13868 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 13869 rx_count = rss_count + cnic_cnt; 13870 13871 /* Maximum number of netdev Tx queues: 13872 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 13873 */ 13874 tx_count = rss_count * max_cos_est + cnic_cnt; 13875 13876 /* dev zeroed in init_etherdev */ 13877 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 13878 if (!dev) 13879 return -ENOMEM; 13880 13881 bp = netdev_priv(dev); 13882 13883 bp->flags = 0; 13884 if (is_vf) 13885 bp->flags |= IS_VF_FLAG; 13886 13887 bp->igu_sb_cnt = max_non_def_sbs; 13888 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; 13889 bp->msg_enable = debug; 13890 bp->cnic_support = cnic_cnt; 13891 bp->cnic_probe = bnx2x_cnic_probe; 13892 13893 pci_set_drvdata(pdev, dev); 13894 13895 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); 13896 if (rc < 0) { 13897 free_netdev(dev); 13898 return rc; 13899 } 13900 13901 BNX2X_DEV_INFO("This is a %s function\n", 13902 IS_PF(bp) ? "physical" : "virtual"); 13903 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); 13904 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); 13905 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", 13906 tx_count, rx_count); 13907 13908 rc = bnx2x_init_bp(bp); 13909 if (rc) 13910 goto init_one_exit; 13911 13912 /* Map doorbells here as we need the real value of bp->max_cos which 13913 * is initialized in bnx2x_init_bp() to determine the number of 13914 * l2 connections. 13915 */ 13916 if (IS_VF(bp)) { 13917 bp->doorbells = bnx2x_vf_doorbells(bp); 13918 rc = bnx2x_vf_pci_alloc(bp); 13919 if (rc) 13920 goto init_one_freemem; 13921 } else { 13922 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); 13923 if (doorbell_size > pci_resource_len(pdev, 2)) { 13924 dev_err(&bp->pdev->dev, 13925 "Cannot map doorbells, bar size too small, aborting\n"); 13926 rc = -ENOMEM; 13927 goto init_one_freemem; 13928 } 13929 bp->doorbells = ioremap(pci_resource_start(pdev, 2), 13930 doorbell_size); 13931 } 13932 if (!bp->doorbells) { 13933 dev_err(&bp->pdev->dev, 13934 "Cannot map doorbell space, aborting\n"); 13935 rc = -ENOMEM; 13936 goto init_one_freemem; 13937 } 13938 13939 if (IS_VF(bp)) { 13940 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); 13941 if (rc) 13942 goto init_one_freemem; 13943 13944#ifdef CONFIG_BNX2X_SRIOV 13945 /* VF with OLD Hypervisor or old PF do not support filtering */ 13946 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) { 13947 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 13948 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 13949 } 13950#endif 13951 } 13952 13953 /* Enable SRIOV if capability found in configuration space */ 13954 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); 13955 if (rc) 13956 goto init_one_freemem; 13957 13958 /* calc qm_cid_count */ 13959 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 13960 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); 13961 13962 /* disable FCOE L2 queue for E1x*/ 13963 if (CHIP_IS_E1x(bp)) 13964 bp->flags |= NO_FCOE_FLAG; 13965 13966 /* Set bp->num_queues for MSI-X mode*/ 13967 bnx2x_set_num_queues(bp); 13968 13969 /* Configure interrupt mode: try to enable MSI-X/MSI if 13970 * needed. 13971 */ 13972 rc = bnx2x_set_int_mode(bp); 13973 if (rc) { 13974 dev_err(&pdev->dev, "Cannot set interrupts\n"); 13975 goto init_one_freemem; 13976 } 13977 BNX2X_DEV_INFO("set interrupts successfully\n"); 13978 13979 /* register the net device */ 13980 rc = register_netdev(dev); 13981 if (rc) { 13982 dev_err(&pdev->dev, "Cannot register net device\n"); 13983 goto init_one_freemem; 13984 } 13985 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); 13986 13987 if (!NO_FCOE(bp)) { 13988 /* Add storage MAC address */ 13989 rtnl_lock(); 13990 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 13991 rtnl_unlock(); 13992 } 13993 BNX2X_DEV_INFO( 13994 "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n", 13995 board_info[ent->driver_data].name, 13996 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 13997 dev->base_addr, bp->pdev->irq, dev->dev_addr); 13998 pcie_print_link_status(bp->pdev); 13999 14000 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) 14001 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED); 14002 14003 return 0; 14004 14005init_one_freemem: 14006 bnx2x_free_mem_bp(bp); 14007 14008init_one_exit: 14009 if (bp->regview) 14010 iounmap(bp->regview); 14011 14012 if (IS_PF(bp) && bp->doorbells) 14013 iounmap(bp->doorbells); 14014 14015 free_netdev(dev); 14016 14017 if (atomic_read(&pdev->enable_cnt) == 1) 14018 pci_release_regions(pdev); 14019 14020 pci_disable_device(pdev); 14021 14022 return rc; 14023} 14024 14025static void __bnx2x_remove(struct pci_dev *pdev, 14026 struct net_device *dev, 14027 struct bnx2x *bp, 14028 bool remove_netdev) 14029{ 14030 /* Delete storage MAC address */ 14031 if (!NO_FCOE(bp)) { 14032 rtnl_lock(); 14033 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 14034 rtnl_unlock(); 14035 } 14036 14037#ifdef BCM_DCBNL 14038 /* Delete app tlvs from dcbnl */ 14039 bnx2x_dcbnl_update_applist(bp, true); 14040#endif 14041 14042 if (IS_PF(bp) && 14043 !BP_NOMCP(bp) && 14044 (bp->flags & BC_SUPPORTS_RMMOD_CMD)) 14045 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); 14046 14047 /* Close the interface - either directly or implicitly */ 14048 if (remove_netdev) { 14049 unregister_netdev(dev); 14050 } else { 14051 rtnl_lock(); 14052 dev_close(dev); 14053 rtnl_unlock(); 14054 } 14055 14056 bnx2x_iov_remove_one(bp); 14057 14058 /* Power on: we can't let PCI layer write to us while we are in D3 */ 14059 if (IS_PF(bp)) { 14060 bnx2x_set_power_state(bp, PCI_D0); 14061 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED); 14062 14063 /* Set endianity registers to reset values in case next driver 14064 * boots in different endianty environment. 14065 */ 14066 bnx2x_reset_endianity(bp); 14067 } 14068 14069 /* Disable MSI/MSI-X */ 14070 bnx2x_disable_msi(bp); 14071 14072 /* Power off */ 14073 if (IS_PF(bp)) 14074 bnx2x_set_power_state(bp, PCI_D3hot); 14075 14076 /* Make sure RESET task is not scheduled before continuing */ 14077 cancel_delayed_work_sync(&bp->sp_rtnl_task); 14078 14079 /* send message via vfpf channel to release the resources of this vf */ 14080 if (IS_VF(bp)) 14081 bnx2x_vfpf_release(bp); 14082 14083 /* Assumes no further PCIe PM changes will occur */ 14084 if (system_state == SYSTEM_POWER_OFF) { 14085 pci_wake_from_d3(pdev, bp->wol); 14086 pci_set_power_state(pdev, PCI_D3hot); 14087 } 14088 14089 if (remove_netdev) { 14090 if (bp->regview) 14091 iounmap(bp->regview); 14092 14093 /* For vfs, doorbells are part of the regview and were unmapped 14094 * along with it. FW is only loaded by PF. 14095 */ 14096 if (IS_PF(bp)) { 14097 if (bp->doorbells) 14098 iounmap(bp->doorbells); 14099 14100 bnx2x_release_firmware(bp); 14101 } else { 14102 bnx2x_vf_pci_dealloc(bp); 14103 } 14104 bnx2x_free_mem_bp(bp); 14105 14106 free_netdev(dev); 14107 14108 if (atomic_read(&pdev->enable_cnt) == 1) 14109 pci_release_regions(pdev); 14110 14111 pci_disable_device(pdev); 14112 } 14113} 14114 14115static void bnx2x_remove_one(struct pci_dev *pdev) 14116{ 14117 struct net_device *dev = pci_get_drvdata(pdev); 14118 struct bnx2x *bp; 14119 14120 if (!dev) { 14121 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 14122 return; 14123 } 14124 bp = netdev_priv(dev); 14125 14126 __bnx2x_remove(pdev, dev, bp, true); 14127} 14128 14129static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 14130{ 14131 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; 14132 14133 bp->rx_mode = BNX2X_RX_MODE_NONE; 14134 14135 if (CNIC_LOADED(bp)) 14136 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 14137 14138 /* Stop Tx */ 14139 bnx2x_tx_disable(bp); 14140 netdev_reset_tc(bp->dev); 14141 14142 timer_delete_sync(&bp->timer); 14143 cancel_delayed_work_sync(&bp->sp_task); 14144 cancel_delayed_work_sync(&bp->period_task); 14145 14146 if (!down_timeout(&bp->stats_lock, HZ / 10)) { 14147 bp->stats_state = STATS_STATE_DISABLED; 14148 up(&bp->stats_lock); 14149 } 14150 14151 bnx2x_save_statistics(bp); 14152 14153 netif_carrier_off(bp->dev); 14154 14155 return 0; 14156} 14157 14158/** 14159 * bnx2x_io_error_detected - called when PCI error is detected 14160 * @pdev: Pointer to PCI device 14161 * @state: The current pci connection state 14162 * 14163 * This function is called after a PCI bus error affecting 14164 * this device has been detected. 14165 */ 14166static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 14167 pci_channel_state_t state) 14168{ 14169 struct net_device *dev = pci_get_drvdata(pdev); 14170 struct bnx2x *bp = netdev_priv(dev); 14171 14172 rtnl_lock(); 14173 14174 BNX2X_ERR("IO error detected\n"); 14175 14176 netif_device_detach(dev); 14177 14178 if (state == pci_channel_io_perm_failure) { 14179 rtnl_unlock(); 14180 return PCI_ERS_RESULT_DISCONNECT; 14181 } 14182 14183 if (netif_running(dev)) 14184 bnx2x_eeh_nic_unload(bp); 14185 14186 bnx2x_prev_path_mark_eeh(bp); 14187 14188 pci_disable_device(pdev); 14189 14190 rtnl_unlock(); 14191 14192 /* Request a slot reset */ 14193 return PCI_ERS_RESULT_NEED_RESET; 14194} 14195 14196/** 14197 * bnx2x_io_slot_reset - called after the PCI bus has been reset 14198 * @pdev: Pointer to PCI device 14199 * 14200 * Restart the card from scratch, as if from a cold-boot. 14201 */ 14202static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 14203{ 14204 struct net_device *dev = pci_get_drvdata(pdev); 14205 struct bnx2x *bp = netdev_priv(dev); 14206 int i; 14207 14208 rtnl_lock(); 14209 BNX2X_ERR("IO slot reset initializing...\n"); 14210 if (pci_enable_device(pdev)) { 14211 dev_err(&pdev->dev, 14212 "Cannot re-enable PCI device after reset\n"); 14213 rtnl_unlock(); 14214 return PCI_ERS_RESULT_DISCONNECT; 14215 } 14216 14217 pci_set_master(pdev); 14218 pci_restore_state(pdev); 14219 14220 if (netif_running(dev)) 14221 bnx2x_set_power_state(bp, PCI_D0); 14222 14223 if (netif_running(dev)) { 14224 BNX2X_ERR("IO slot reset --> driver unload\n"); 14225 14226 /* MCP should have been reset; Need to wait for validity */ 14227 if (bnx2x_init_shmem(bp)) { 14228 rtnl_unlock(); 14229 return PCI_ERS_RESULT_DISCONNECT; 14230 } 14231 14232 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { 14233 u32 v; 14234 14235 v = SHMEM2_RD(bp, 14236 drv_capabilities_flag[BP_FW_MB_IDX(bp)]); 14237 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], 14238 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); 14239 } 14240 bnx2x_drain_tx_queues(bp); 14241 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); 14242 if (!bp->nic_stopped) { 14243 bnx2x_netif_stop(bp, 1); 14244 bnx2x_del_all_napi(bp); 14245 14246 if (CNIC_LOADED(bp)) 14247 bnx2x_del_all_napi_cnic(bp); 14248 14249 bnx2x_free_irq(bp); 14250 bp->nic_stopped = true; 14251 } 14252 14253 /* Report UNLOAD_DONE to MCP */ 14254 bnx2x_send_unload_done(bp, true); 14255 14256 bp->sp_state = 0; 14257 bp->port.pmf = 0; 14258 14259 bnx2x_prev_unload(bp); 14260 14261 /* We should have reseted the engine, so It's fair to 14262 * assume the FW will no longer write to the bnx2x driver. 14263 */ 14264 bnx2x_squeeze_objects(bp); 14265 bnx2x_free_skbs(bp); 14266 for_each_rx_queue(bp, i) 14267 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 14268 bnx2x_free_fp_mem(bp); 14269 bnx2x_free_mem(bp); 14270 14271 bp->state = BNX2X_STATE_CLOSED; 14272 } 14273 14274 rtnl_unlock(); 14275 14276 return PCI_ERS_RESULT_RECOVERED; 14277} 14278 14279/** 14280 * bnx2x_io_resume - called when traffic can start flowing again 14281 * @pdev: Pointer to PCI device 14282 * 14283 * This callback is called when the error recovery driver tells us that 14284 * its OK to resume normal operation. 14285 */ 14286static void bnx2x_io_resume(struct pci_dev *pdev) 14287{ 14288 struct net_device *dev = pci_get_drvdata(pdev); 14289 struct bnx2x *bp = netdev_priv(dev); 14290 14291 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 14292 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); 14293 return; 14294 } 14295 14296 rtnl_lock(); 14297 14298 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 14299 DRV_MSG_SEQ_NUMBER_MASK; 14300 14301 if (netif_running(dev)) { 14302 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 14303 netdev_err(bp->dev, "Error during driver initialization, try unloading/reloading the driver\n"); 14304 goto done; 14305 } 14306 } 14307 14308 netif_device_attach(dev); 14309 14310done: 14311 rtnl_unlock(); 14312} 14313 14314static const struct pci_error_handlers bnx2x_err_handler = { 14315 .error_detected = bnx2x_io_error_detected, 14316 .slot_reset = bnx2x_io_slot_reset, 14317 .resume = bnx2x_io_resume, 14318}; 14319 14320static void bnx2x_shutdown(struct pci_dev *pdev) 14321{ 14322 struct net_device *dev = pci_get_drvdata(pdev); 14323 struct bnx2x *bp; 14324 14325 if (!dev) 14326 return; 14327 14328 bp = netdev_priv(dev); 14329 if (!bp) 14330 return; 14331 14332 rtnl_lock(); 14333 netif_device_detach(dev); 14334 rtnl_unlock(); 14335 14336 /* Don't remove the netdevice, as there are scenarios which will cause 14337 * the kernel to hang, e.g., when trying to remove bnx2i while the 14338 * rootfs is mounted from SAN. 14339 */ 14340 __bnx2x_remove(pdev, dev, bp, false); 14341} 14342 14343static struct pci_driver bnx2x_pci_driver = { 14344 .name = DRV_MODULE_NAME, 14345 .id_table = bnx2x_pci_tbl, 14346 .probe = bnx2x_init_one, 14347 .remove = bnx2x_remove_one, 14348 .driver.pm = &bnx2x_pm_ops, 14349 .err_handler = &bnx2x_err_handler, 14350#ifdef CONFIG_BNX2X_SRIOV 14351 .sriov_configure = bnx2x_sriov_configure, 14352#endif 14353 .shutdown = bnx2x_shutdown, 14354}; 14355 14356static int __init bnx2x_init(void) 14357{ 14358 int ret; 14359 14360 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 14361 if (bnx2x_wq == NULL) { 14362 pr_err("Cannot create workqueue\n"); 14363 return -ENOMEM; 14364 } 14365 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov"); 14366 if (!bnx2x_iov_wq) { 14367 pr_err("Cannot create iov workqueue\n"); 14368 destroy_workqueue(bnx2x_wq); 14369 return -ENOMEM; 14370 } 14371 14372 ret = pci_register_driver(&bnx2x_pci_driver); 14373 if (ret) { 14374 pr_err("Cannot register driver\n"); 14375 destroy_workqueue(bnx2x_wq); 14376 destroy_workqueue(bnx2x_iov_wq); 14377 } 14378 return ret; 14379} 14380 14381static void __exit bnx2x_cleanup(void) 14382{ 14383 struct list_head *pos, *q; 14384 14385 pci_unregister_driver(&bnx2x_pci_driver); 14386 14387 destroy_workqueue(bnx2x_wq); 14388 destroy_workqueue(bnx2x_iov_wq); 14389 14390 /* Free globally allocated resources */ 14391 list_for_each_safe(pos, q, &bnx2x_prev_list) { 14392 struct bnx2x_prev_path_list *tmp = 14393 list_entry(pos, struct bnx2x_prev_path_list, list); 14394 list_del(pos); 14395 kfree(tmp); 14396 } 14397} 14398 14399void bnx2x_notify_link_changed(struct bnx2x *bp) 14400{ 14401 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 14402} 14403 14404module_init(bnx2x_init); 14405module_exit(bnx2x_cleanup); 14406 14407/** 14408 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 14409 * @bp: driver handle 14410 * 14411 * This function will wait until the ramrod completion returns. 14412 * Return 0 if success, -ENODEV if ramrod doesn't return. 14413 */ 14414static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 14415{ 14416 unsigned long ramrod_flags = 0; 14417 14418 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 14419 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 14420 &bp->iscsi_l2_mac_obj, true, 14421 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 14422} 14423 14424/* count denotes the number of new completions we have seen */ 14425static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 14426{ 14427 struct eth_spe *spe; 14428 int cxt_index, cxt_offset; 14429 14430#ifdef BNX2X_STOP_ON_ERROR 14431 if (unlikely(bp->panic)) 14432 return; 14433#endif 14434 14435 spin_lock_bh(&bp->spq_lock); 14436 BUG_ON(bp->cnic_spq_pending < count); 14437 bp->cnic_spq_pending -= count; 14438 14439 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 14440 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 14441 & SPE_HDR_CONN_TYPE) >> 14442 SPE_HDR_CONN_TYPE_SHIFT; 14443 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 14444 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 14445 14446 /* Set validation for iSCSI L2 client before sending SETUP 14447 * ramrod 14448 */ 14449 if (type == ETH_CONNECTION_TYPE) { 14450 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { 14451 cxt_index = BNX2X_ISCSI_ETH_CID(bp) / 14452 ILT_PAGE_CIDS; 14453 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - 14454 (cxt_index * ILT_PAGE_CIDS); 14455 bnx2x_set_ctx_validation(bp, 14456 &bp->context[cxt_index]. 14457 vcxt[cxt_offset].eth, 14458 BNX2X_ISCSI_ETH_CID(bp)); 14459 } 14460 } 14461 14462 /* 14463 * There may be not more than 8 L2, not more than 8 L5 SPEs 14464 * and in the air. We also check that number of outstanding 14465 * COMMON ramrods is not more than the EQ and SPQ can 14466 * accommodate. 14467 */ 14468 if (type == ETH_CONNECTION_TYPE) { 14469 if (!atomic_read(&bp->cq_spq_left)) 14470 break; 14471 else 14472 atomic_dec(&bp->cq_spq_left); 14473 } else if (type == NONE_CONNECTION_TYPE) { 14474 if (!atomic_read(&bp->eq_spq_left)) 14475 break; 14476 else 14477 atomic_dec(&bp->eq_spq_left); 14478 } else if ((type == ISCSI_CONNECTION_TYPE) || 14479 (type == FCOE_CONNECTION_TYPE)) { 14480 if (bp->cnic_spq_pending >= 14481 bp->cnic_eth_dev.max_kwqe_pending) 14482 break; 14483 else 14484 bp->cnic_spq_pending++; 14485 } else { 14486 BNX2X_ERR("Unknown SPE type: %d\n", type); 14487 bnx2x_panic(); 14488 break; 14489 } 14490 14491 spe = bnx2x_sp_get_next(bp); 14492 *spe = *bp->cnic_kwq_cons; 14493 14494 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", 14495 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 14496 14497 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 14498 bp->cnic_kwq_cons = bp->cnic_kwq; 14499 else 14500 bp->cnic_kwq_cons++; 14501 } 14502 bnx2x_sp_prod_update(bp); 14503 spin_unlock_bh(&bp->spq_lock); 14504} 14505 14506static int bnx2x_cnic_sp_queue(struct net_device *dev, 14507 struct kwqe_16 *kwqes[], u32 count) 14508{ 14509 struct bnx2x *bp = netdev_priv(dev); 14510 int i; 14511 14512#ifdef BNX2X_STOP_ON_ERROR 14513 if (unlikely(bp->panic)) { 14514 BNX2X_ERR("Can't post to SP queue while panic\n"); 14515 return -EIO; 14516 } 14517#endif 14518 14519 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 14520 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 14521 BNX2X_ERR("Handling parity error recovery. Try again later\n"); 14522 return -EAGAIN; 14523 } 14524 14525 spin_lock_bh(&bp->spq_lock); 14526 14527 for (i = 0; i < count; i++) { 14528 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 14529 14530 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 14531 break; 14532 14533 *bp->cnic_kwq_prod = *spe; 14534 14535 bp->cnic_kwq_pending++; 14536 14537 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", 14538 spe->hdr.conn_and_cmd_data, spe->hdr.type, 14539 spe->data.update_data_addr.hi, 14540 spe->data.update_data_addr.lo, 14541 bp->cnic_kwq_pending); 14542 14543 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 14544 bp->cnic_kwq_prod = bp->cnic_kwq; 14545 else 14546 bp->cnic_kwq_prod++; 14547 } 14548 14549 spin_unlock_bh(&bp->spq_lock); 14550 14551 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 14552 bnx2x_cnic_sp_post(bp, 0); 14553 14554 return i; 14555} 14556 14557static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 14558{ 14559 struct cnic_ops *c_ops; 14560 int rc = 0; 14561 14562 mutex_lock(&bp->cnic_mutex); 14563 c_ops = rcu_dereference_protected(bp->cnic_ops, 14564 lockdep_is_held(&bp->cnic_mutex)); 14565 if (c_ops) 14566 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 14567 mutex_unlock(&bp->cnic_mutex); 14568 14569 return rc; 14570} 14571 14572static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 14573{ 14574 struct cnic_ops *c_ops; 14575 int rc = 0; 14576 14577 rcu_read_lock(); 14578 c_ops = rcu_dereference(bp->cnic_ops); 14579 if (c_ops) 14580 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 14581 rcu_read_unlock(); 14582 14583 return rc; 14584} 14585 14586/* 14587 * for commands that have no data 14588 */ 14589int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 14590{ 14591 struct cnic_ctl_info ctl = {0}; 14592 14593 ctl.cmd = cmd; 14594 14595 return bnx2x_cnic_ctl_send(bp, &ctl); 14596} 14597 14598static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 14599{ 14600 struct cnic_ctl_info ctl = {0}; 14601 14602 /* first we tell CNIC and only then we count this as a completion */ 14603 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 14604 ctl.data.comp.cid = cid; 14605 ctl.data.comp.error = err; 14606 14607 bnx2x_cnic_ctl_send_bh(bp, &ctl); 14608 bnx2x_cnic_sp_post(bp, 0); 14609} 14610 14611/* Called with netif_addr_lock_bh() taken. 14612 * Sets an rx_mode config for an iSCSI ETH client. 14613 * Doesn't block. 14614 * Completion should be checked outside. 14615 */ 14616static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 14617{ 14618 unsigned long accept_flags = 0, ramrod_flags = 0; 14619 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 14620 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 14621 14622 if (start) { 14623 /* Start accepting on iSCSI L2 ring. Accept all multicasts 14624 * because it's the only way for UIO Queue to accept 14625 * multicasts (in non-promiscuous mode only one Queue per 14626 * function will receive multicast packets (leading in our 14627 * case). 14628 */ 14629 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 14630 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 14631 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 14632 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 14633 14634 /* Clear STOP_PENDING bit if START is requested */ 14635 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 14636 14637 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 14638 } else 14639 /* Clear START_PENDING bit if STOP is requested */ 14640 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 14641 14642 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 14643 set_bit(sched_state, &bp->sp_state); 14644 else { 14645 __set_bit(RAMROD_RX, &ramrod_flags); 14646 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 14647 ramrod_flags); 14648 } 14649} 14650 14651static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 14652{ 14653 struct bnx2x *bp = netdev_priv(dev); 14654 int rc = 0; 14655 14656 switch (ctl->cmd) { 14657 case DRV_CTL_CTXTBL_WR_CMD: { 14658 u32 index = ctl->data.io.offset; 14659 dma_addr_t addr = ctl->data.io.dma_addr; 14660 14661 bnx2x_ilt_wr(bp, index, addr); 14662 break; 14663 } 14664 14665 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 14666 int count = ctl->data.credit.credit_count; 14667 14668 bnx2x_cnic_sp_post(bp, count); 14669 break; 14670 } 14671 14672 /* rtnl_lock is held. */ 14673 case DRV_CTL_START_L2_CMD: { 14674 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14675 unsigned long sp_bits = 0; 14676 14677 /* Configure the iSCSI classification object */ 14678 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 14679 cp->iscsi_l2_client_id, 14680 cp->iscsi_l2_cid, BP_FUNC(bp), 14681 bnx2x_sp(bp, mac_rdata), 14682 bnx2x_sp_mapping(bp, mac_rdata), 14683 BNX2X_FILTER_MAC_PENDING, 14684 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 14685 &bp->macs_pool); 14686 14687 /* Set iSCSI MAC address */ 14688 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 14689 if (rc) 14690 break; 14691 14692 barrier(); 14693 14694 /* Start accepting on iSCSI L2 ring */ 14695 14696 netif_addr_lock_bh(dev); 14697 bnx2x_set_iscsi_eth_rx_mode(bp, true); 14698 netif_addr_unlock_bh(dev); 14699 14700 /* bits to wait on */ 14701 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 14702 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 14703 14704 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 14705 BNX2X_ERR("rx_mode completion timed out!\n"); 14706 14707 break; 14708 } 14709 14710 /* rtnl_lock is held. */ 14711 case DRV_CTL_STOP_L2_CMD: { 14712 unsigned long sp_bits = 0; 14713 14714 /* Stop accepting on iSCSI L2 ring */ 14715 netif_addr_lock_bh(dev); 14716 bnx2x_set_iscsi_eth_rx_mode(bp, false); 14717 netif_addr_unlock_bh(dev); 14718 14719 /* bits to wait on */ 14720 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 14721 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 14722 14723 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 14724 BNX2X_ERR("rx_mode completion timed out!\n"); 14725 14726 barrier(); 14727 14728 /* Unset iSCSI L2 MAC */ 14729 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 14730 BNX2X_ISCSI_ETH_MAC, true); 14731 break; 14732 } 14733 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 14734 int count = ctl->data.credit.credit_count; 14735 14736 smp_mb__before_atomic(); 14737 atomic_add(count, &bp->cq_spq_left); 14738 smp_mb__after_atomic(); 14739 break; 14740 } 14741 case DRV_CTL_ULP_REGISTER_CMD: { 14742 int ulp_type = ctl->data.register_data.ulp_type; 14743 14744 if (CHIP_IS_E3(bp)) { 14745 int idx = BP_FW_MB_IDX(bp); 14746 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 14747 int path = BP_PATH(bp); 14748 int port = BP_PORT(bp); 14749 int i; 14750 u32 scratch_offset; 14751 u32 *host_addr; 14752 14753 /* first write capability to shmem2 */ 14754 if (ulp_type == CNIC_ULP_ISCSI) 14755 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 14756 else if (ulp_type == CNIC_ULP_FCOE) 14757 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 14758 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 14759 14760 if ((ulp_type != CNIC_ULP_FCOE) || 14761 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || 14762 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) 14763 break; 14764 14765 /* if reached here - should write fcoe capabilities */ 14766 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); 14767 if (!scratch_offset) 14768 break; 14769 scratch_offset += offsetof(struct glob_ncsi_oem_data, 14770 fcoe_features[path][port]); 14771 host_addr = (u32 *) &(ctl->data.register_data. 14772 fcoe_features); 14773 for (i = 0; i < sizeof(struct fcoe_capabilities); 14774 i += 4) 14775 REG_WR(bp, scratch_offset + i, 14776 *(host_addr + i/4)); 14777 } 14778 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); 14779 break; 14780 } 14781 14782 case DRV_CTL_ULP_UNREGISTER_CMD: { 14783 int ulp_type = ctl->data.ulp_type; 14784 14785 if (CHIP_IS_E3(bp)) { 14786 int idx = BP_FW_MB_IDX(bp); 14787 u32 cap; 14788 14789 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 14790 if (ulp_type == CNIC_ULP_ISCSI) 14791 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 14792 else if (ulp_type == CNIC_ULP_FCOE) 14793 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 14794 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 14795 } 14796 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); 14797 break; 14798 } 14799 14800 default: 14801 BNX2X_ERR("unknown command %x\n", ctl->cmd); 14802 rc = -EINVAL; 14803 } 14804 14805 /* For storage-only interfaces, change driver state */ 14806 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) { 14807 switch (ctl->drv_state) { 14808 case DRV_NOP: 14809 break; 14810 case DRV_ACTIVE: 14811 bnx2x_set_os_driver_state(bp, 14812 OS_DRIVER_STATE_ACTIVE); 14813 break; 14814 case DRV_INACTIVE: 14815 bnx2x_set_os_driver_state(bp, 14816 OS_DRIVER_STATE_DISABLED); 14817 break; 14818 case DRV_UNLOADED: 14819 bnx2x_set_os_driver_state(bp, 14820 OS_DRIVER_STATE_NOT_LOADED); 14821 break; 14822 default: 14823 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state); 14824 } 14825 } 14826 14827 return rc; 14828} 14829 14830static int bnx2x_get_fc_npiv(struct net_device *dev, 14831 struct cnic_fc_npiv_tbl *cnic_tbl) 14832{ 14833 struct bnx2x *bp = netdev_priv(dev); 14834 struct bdn_fc_npiv_tbl *tbl = NULL; 14835 u32 offset, entries; 14836 int rc = -EINVAL; 14837 int i; 14838 14839 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) 14840 goto out; 14841 14842 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n"); 14843 14844 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL); 14845 if (!tbl) { 14846 BNX2X_ERR("Failed to allocate fc_npiv table\n"); 14847 goto out; 14848 } 14849 14850 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]); 14851 if (!offset) { 14852 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n"); 14853 goto out; 14854 } 14855 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset); 14856 14857 /* Read the table contents from nvram */ 14858 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) { 14859 BNX2X_ERR("Failed to read FC-NPIV table\n"); 14860 goto out; 14861 } 14862 14863 /* Since bnx2x_nvram_read() returns data in be32, we need to convert 14864 * the number of entries back to cpu endianness. 14865 */ 14866 entries = tbl->fc_npiv_cfg.num_of_npiv; 14867 entries = (__force u32)be32_to_cpu((__force __be32)entries); 14868 tbl->fc_npiv_cfg.num_of_npiv = entries; 14869 14870 if (!tbl->fc_npiv_cfg.num_of_npiv) { 14871 DP(BNX2X_MSG_MCP, 14872 "No FC-NPIV table [valid, simply not present]\n"); 14873 goto out; 14874 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) { 14875 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n", 14876 tbl->fc_npiv_cfg.num_of_npiv); 14877 goto out; 14878 } else { 14879 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n", 14880 tbl->fc_npiv_cfg.num_of_npiv); 14881 } 14882 14883 /* Copy the data into cnic-provided struct */ 14884 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv; 14885 for (i = 0; i < cnic_tbl->count; i++) { 14886 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8); 14887 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8); 14888 } 14889 14890 rc = 0; 14891out: 14892 kfree(tbl); 14893 return rc; 14894} 14895 14896void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 14897{ 14898 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14899 14900 if (bp->flags & USING_MSIX_FLAG) { 14901 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 14902 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 14903 cp->irq_arr[0].vector = bp->msix_table[1].vector; 14904 } else { 14905 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 14906 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 14907 } 14908 if (!CHIP_IS_E1x(bp)) 14909 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 14910 else 14911 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 14912 14913 cp->irq_arr[0].status_blk_map = bp->cnic_sb_mapping; 14914 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 14915 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 14916 cp->irq_arr[1].status_blk = bp->def_status_blk; 14917 cp->irq_arr[1].status_blk_map = bp->def_status_blk_mapping; 14918 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 14919 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 14920 14921 cp->num_irq = 2; 14922} 14923 14924void bnx2x_setup_cnic_info(struct bnx2x *bp) 14925{ 14926 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14927 14928 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 14929 bnx2x_cid_ilt_lines(bp); 14930 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 14931 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 14932 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 14933 14934 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n", 14935 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, 14936 cp->iscsi_l2_cid); 14937 14938 if (NO_ISCSI_OOO(bp)) 14939 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 14940} 14941 14942static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 14943 void *data) 14944{ 14945 struct bnx2x *bp = netdev_priv(dev); 14946 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14947 int rc; 14948 14949 DP(NETIF_MSG_IFUP, "Register_cnic called\n"); 14950 14951 if (ops == NULL) { 14952 BNX2X_ERR("NULL ops received\n"); 14953 return -EINVAL; 14954 } 14955 14956 if (!CNIC_SUPPORT(bp)) { 14957 BNX2X_ERR("Can't register CNIC when not supported\n"); 14958 return -EOPNOTSUPP; 14959 } 14960 14961 if (!CNIC_LOADED(bp)) { 14962 rc = bnx2x_load_cnic(bp); 14963 if (rc) { 14964 BNX2X_ERR("CNIC-related load failed\n"); 14965 return rc; 14966 } 14967 } 14968 14969 bp->cnic_enabled = true; 14970 14971 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 14972 if (!bp->cnic_kwq) 14973 return -ENOMEM; 14974 14975 bp->cnic_kwq_cons = bp->cnic_kwq; 14976 bp->cnic_kwq_prod = bp->cnic_kwq; 14977 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 14978 14979 bp->cnic_spq_pending = 0; 14980 bp->cnic_kwq_pending = 0; 14981 14982 bp->cnic_data = data; 14983 14984 cp->num_irq = 0; 14985 cp->drv_state |= CNIC_DRV_STATE_REGD; 14986 cp->iro_arr = bp->iro_arr; 14987 14988 bnx2x_setup_cnic_irq_info(bp); 14989 14990 rcu_assign_pointer(bp->cnic_ops, ops); 14991 14992 /* Schedule driver to read CNIC driver versions */ 14993 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); 14994 14995 return 0; 14996} 14997 14998static int bnx2x_unregister_cnic(struct net_device *dev) 14999{ 15000 struct bnx2x *bp = netdev_priv(dev); 15001 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 15002 15003 mutex_lock(&bp->cnic_mutex); 15004 cp->drv_state = 0; 15005 RCU_INIT_POINTER(bp->cnic_ops, NULL); 15006 mutex_unlock(&bp->cnic_mutex); 15007 synchronize_rcu(); 15008 bp->cnic_enabled = false; 15009 kfree(bp->cnic_kwq); 15010 bp->cnic_kwq = NULL; 15011 15012 return 0; 15013} 15014 15015static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 15016{ 15017 struct bnx2x *bp = netdev_priv(dev); 15018 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 15019 15020 /* If both iSCSI and FCoE are disabled - return NULL in 15021 * order to indicate CNIC that it should not try to work 15022 * with this device. 15023 */ 15024 if (NO_ISCSI(bp) && NO_FCOE(bp)) 15025 return NULL; 15026 15027 cp->drv_owner = THIS_MODULE; 15028 cp->chip_id = CHIP_ID(bp); 15029 cp->pdev = bp->pdev; 15030 cp->io_base = bp->regview; 15031 cp->io_base2 = bp->doorbells; 15032 cp->max_kwqe_pending = 8; 15033 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 15034 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 15035 bnx2x_cid_ilt_lines(bp); 15036 cp->ctx_tbl_len = CNIC_ILT_LINES; 15037 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 15038 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 15039 cp->drv_ctl = bnx2x_drv_ctl; 15040 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv; 15041 cp->drv_register_cnic = bnx2x_register_cnic; 15042 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 15043 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 15044 cp->iscsi_l2_client_id = 15045 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 15046 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 15047 15048 if (NO_ISCSI_OOO(bp)) 15049 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 15050 15051 if (NO_ISCSI(bp)) 15052 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 15053 15054 if (NO_FCOE(bp)) 15055 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 15056 15057 BNX2X_DEV_INFO( 15058 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", 15059 cp->ctx_blk_size, 15060 cp->ctx_tbl_offset, 15061 cp->ctx_tbl_len, 15062 cp->starting_cid); 15063 return cp; 15064} 15065 15066static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 15067{ 15068 struct bnx2x *bp = fp->bp; 15069 u32 offset = BAR_USTRORM_INTMEM; 15070 15071 if (IS_VF(bp)) 15072 return bnx2x_vf_ustorm_prods_offset(bp, fp); 15073 else if (!CHIP_IS_E1x(bp)) 15074 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 15075 else 15076 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 15077 15078 return offset; 15079} 15080 15081/* called only on E1H or E2. 15082 * When pretending to be PF, the pretend value is the function number 0...7 15083 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID 15084 * combination 15085 */ 15086int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) 15087{ 15088 u32 pretend_reg; 15089 15090 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) 15091 return -1; 15092 15093 /* get my own pretend register */ 15094 pretend_reg = bnx2x_get_pretend_reg(bp); 15095 REG_WR(bp, pretend_reg, pretend_func_val); 15096 REG_RD(bp, pretend_reg); 15097 return 0; 15098} 15099 15100static void bnx2x_ptp_task(struct work_struct *work) 15101{ 15102 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); 15103 int port = BP_PORT(bp); 15104 u32 val_seq; 15105 u64 timestamp, ns; 15106 struct skb_shared_hwtstamps shhwtstamps; 15107 bool bail = true; 15108 int i; 15109 15110 /* FW may take a while to complete timestamping; try a bit and if it's 15111 * still not complete, may indicate an error state - bail out then. 15112 */ 15113 for (i = 0; i < 10; i++) { 15114 /* Read Tx timestamp registers */ 15115 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : 15116 NIG_REG_P0_TLLH_PTP_BUF_SEQID); 15117 if (val_seq & 0x10000) { 15118 bail = false; 15119 break; 15120 } 15121 msleep(1 << i); 15122 } 15123 15124 if (!bail) { 15125 /* There is a valid timestamp value */ 15126 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : 15127 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB); 15128 timestamp <<= 32; 15129 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : 15130 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB); 15131 /* Reset timestamp register to allow new timestamp */ 15132 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : 15133 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); 15134 ns = timecounter_cyc2time(&bp->timecounter, timestamp); 15135 15136 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 15137 shhwtstamps.hwtstamp = ns_to_ktime(ns); 15138 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); 15139 15140 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n", 15141 timestamp, ns); 15142 } else { 15143 DP(BNX2X_MSG_PTP, 15144 "Tx timestamp is not recorded (register read=%u)\n", 15145 val_seq); 15146 bp->eth_stats.ptp_skip_tx_ts++; 15147 } 15148 15149 dev_kfree_skb_any(bp->ptp_tx_skb); 15150 bp->ptp_tx_skb = NULL; 15151} 15152 15153void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) 15154{ 15155 int port = BP_PORT(bp); 15156 u64 timestamp, ns; 15157 15158 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : 15159 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB); 15160 timestamp <<= 32; 15161 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : 15162 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB); 15163 15164 /* Reset timestamp register to allow new timestamp */ 15165 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : 15166 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); 15167 15168 ns = timecounter_cyc2time(&bp->timecounter, timestamp); 15169 15170 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); 15171 15172 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n", 15173 timestamp, ns); 15174} 15175 15176/* Read the PHC */ 15177static u64 bnx2x_cyclecounter_read(struct cyclecounter *cc) 15178{ 15179 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); 15180 int port = BP_PORT(bp); 15181 u32 wb_data[2]; 15182 u64 phc_cycles; 15183 15184 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : 15185 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2); 15186 phc_cycles = wb_data[1]; 15187 phc_cycles = (phc_cycles << 32) + wb_data[0]; 15188 15189 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles); 15190 15191 return phc_cycles; 15192} 15193 15194static void bnx2x_init_cyclecounter(struct bnx2x *bp) 15195{ 15196 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); 15197 bp->cyclecounter.read = bnx2x_cyclecounter_read; 15198 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); 15199 bp->cyclecounter.shift = 0; 15200 bp->cyclecounter.mult = 1; 15201} 15202 15203static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) 15204{ 15205 struct bnx2x_func_state_params func_params = {NULL}; 15206 struct bnx2x_func_set_timesync_params *set_timesync_params = 15207 &func_params.params.set_timesync; 15208 15209 /* Prepare parameters for function state transitions */ 15210 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 15211 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 15212 15213 func_params.f_obj = &bp->func_obj; 15214 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; 15215 15216 /* Function parameters */ 15217 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET; 15218 set_timesync_params->offset_cmd = TS_OFFSET_KEEP; 15219 15220 return bnx2x_func_state_change(bp, &func_params); 15221} 15222 15223static int bnx2x_enable_ptp_packets(struct bnx2x *bp) 15224{ 15225 struct bnx2x_queue_state_params q_params; 15226 int rc, i; 15227 15228 /* send queue update ramrod to enable PTP packets */ 15229 memset(&q_params, 0, sizeof(q_params)); 15230 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 15231 q_params.cmd = BNX2X_Q_CMD_UPDATE; 15232 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, 15233 &q_params.params.update.update_flags); 15234 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS, 15235 &q_params.params.update.update_flags); 15236 15237 /* send the ramrod on all the queues of the PF */ 15238 for_each_eth_queue(bp, i) { 15239 struct bnx2x_fastpath *fp = &bp->fp[i]; 15240 15241 /* Set the appropriate Queue object */ 15242 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 15243 15244 /* Update the Queue state */ 15245 rc = bnx2x_queue_state_change(bp, &q_params); 15246 if (rc) { 15247 BNX2X_ERR("Failed to enable PTP packets\n"); 15248 return rc; 15249 } 15250 } 15251 15252 return 0; 15253} 15254 15255#define BNX2X_P2P_DETECT_PARAM_MASK 0x5F5 15256#define BNX2X_P2P_DETECT_RULE_MASK 0x3DBB 15257#define BNX2X_PTP_TX_ON_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA) 15258#define BNX2X_PTP_TX_ON_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE) 15259#define BNX2X_PTP_V1_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EE) 15260#define BNX2X_PTP_V1_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FFE) 15261#define BNX2X_PTP_V2_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EA) 15262#define BNX2X_PTP_V2_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FEE) 15263#define BNX2X_PTP_V2_L2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6BF) 15264#define BNX2X_PTP_V2_L2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EFF) 15265#define BNX2X_PTP_V2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA) 15266#define BNX2X_PTP_V2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE) 15267 15268int bnx2x_configure_ptp_filters(struct bnx2x *bp) 15269{ 15270 int port = BP_PORT(bp); 15271 u32 param, rule; 15272 int rc; 15273 15274 if (!bp->hwtstamp_ioctl_called) 15275 return 0; 15276 15277 param = port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : 15278 NIG_REG_P0_TLLH_PTP_PARAM_MASK; 15279 rule = port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : 15280 NIG_REG_P0_TLLH_PTP_RULE_MASK; 15281 switch (bp->tx_type) { 15282 case HWTSTAMP_TX_ON: 15283 bp->flags |= TX_TIMESTAMPING_EN; 15284 REG_WR(bp, param, BNX2X_PTP_TX_ON_PARAM_MASK); 15285 REG_WR(bp, rule, BNX2X_PTP_TX_ON_RULE_MASK); 15286 break; 15287 case HWTSTAMP_TX_ONESTEP_SYNC: 15288 case HWTSTAMP_TX_ONESTEP_P2P: 15289 BNX2X_ERR("One-step timestamping is not supported\n"); 15290 return -ERANGE; 15291 } 15292 15293 param = port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : 15294 NIG_REG_P0_LLH_PTP_PARAM_MASK; 15295 rule = port ? NIG_REG_P1_LLH_PTP_RULE_MASK : 15296 NIG_REG_P0_LLH_PTP_RULE_MASK; 15297 switch (bp->rx_filter) { 15298 case HWTSTAMP_FILTER_NONE: 15299 break; 15300 case HWTSTAMP_FILTER_ALL: 15301 case HWTSTAMP_FILTER_SOME: 15302 case HWTSTAMP_FILTER_NTP_ALL: 15303 bp->rx_filter = HWTSTAMP_FILTER_NONE; 15304 break; 15305 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 15306 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 15307 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 15308 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 15309 /* Initialize PTP detection for UDP/IPv4 events */ 15310 REG_WR(bp, param, BNX2X_PTP_V1_L4_PARAM_MASK); 15311 REG_WR(bp, rule, BNX2X_PTP_V1_L4_RULE_MASK); 15312 break; 15313 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 15314 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 15315 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 15316 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 15317 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */ 15318 REG_WR(bp, param, BNX2X_PTP_V2_L4_PARAM_MASK); 15319 REG_WR(bp, rule, BNX2X_PTP_V2_L4_RULE_MASK); 15320 break; 15321 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 15322 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 15323 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 15324 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 15325 /* Initialize PTP detection L2 events */ 15326 REG_WR(bp, param, BNX2X_PTP_V2_L2_PARAM_MASK); 15327 REG_WR(bp, rule, BNX2X_PTP_V2_L2_RULE_MASK); 15328 15329 break; 15330 case HWTSTAMP_FILTER_PTP_V2_EVENT: 15331 case HWTSTAMP_FILTER_PTP_V2_SYNC: 15332 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 15333 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 15334 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */ 15335 REG_WR(bp, param, BNX2X_PTP_V2_PARAM_MASK); 15336 REG_WR(bp, rule, BNX2X_PTP_V2_RULE_MASK); 15337 break; 15338 } 15339 15340 /* Indicate to FW that this PF expects recorded PTP packets */ 15341 rc = bnx2x_enable_ptp_packets(bp); 15342 if (rc) 15343 return rc; 15344 15345 /* Enable sending PTP packets to host */ 15346 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : 15347 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1); 15348 15349 return 0; 15350} 15351 15352static int bnx2x_hwtstamp_set(struct net_device *dev, 15353 struct kernel_hwtstamp_config *config, 15354 struct netlink_ext_ack *extack) 15355{ 15356 struct bnx2x *bp = netdev_priv(dev); 15357 int rc; 15358 15359 DP(BNX2X_MSG_PTP, "HWTSTAMP SET called\n"); 15360 15361 if (!netif_running(dev)) { 15362 NL_SET_ERR_MSG_MOD(extack, "Device is down"); 15363 return -EAGAIN; 15364 } 15365 15366 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n", 15367 config->tx_type, config->rx_filter); 15368 15369 switch (config->tx_type) { 15370 case HWTSTAMP_TX_ON: 15371 case HWTSTAMP_TX_OFF: 15372 break; 15373 default: 15374 NL_SET_ERR_MSG_MOD(extack, 15375 "One-step timestamping is not supported"); 15376 return -ERANGE; 15377 } 15378 15379 bp->hwtstamp_ioctl_called = true; 15380 bp->tx_type = config->tx_type; 15381 bp->rx_filter = config->rx_filter; 15382 15383 rc = bnx2x_configure_ptp_filters(bp); 15384 if (rc) { 15385 NL_SET_ERR_MSG_MOD(extack, "HW configuration failure"); 15386 return rc; 15387 } 15388 15389 config->rx_filter = bp->rx_filter; 15390 15391 return 0; 15392} 15393 15394static int bnx2x_hwtstamp_get(struct net_device *dev, 15395 struct kernel_hwtstamp_config *config) 15396{ 15397 struct bnx2x *bp = netdev_priv(dev); 15398 15399 config->rx_filter = bp->rx_filter; 15400 config->tx_type = bp->tx_type; 15401 15402 return 0; 15403} 15404 15405/* Configures HW for PTP */ 15406static int bnx2x_configure_ptp(struct bnx2x *bp) 15407{ 15408 int rc, port = BP_PORT(bp); 15409 u32 wb_data[2]; 15410 15411 /* Reset PTP event detection rules - will be configured in the IOCTL */ 15412 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : 15413 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); 15414 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : 15415 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); 15416 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : 15417 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); 15418 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : 15419 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); 15420 15421 /* Disable PTP packets to host - will be configured in the IOCTL*/ 15422 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : 15423 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); 15424 15425 /* Enable the PTP feature */ 15426 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : 15427 NIG_REG_P0_PTP_EN, 0x3F); 15428 15429 /* Enable the free-running counter */ 15430 wb_data[0] = 0; 15431 wb_data[1] = 0; 15432 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); 15433 15434 /* Reset drift register (offset register is not reset) */ 15435 rc = bnx2x_send_reset_timesync_ramrod(bp); 15436 if (rc) { 15437 BNX2X_ERR("Failed to reset PHC drift register\n"); 15438 return -EFAULT; 15439 } 15440 15441 /* Reset possibly old timestamps */ 15442 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : 15443 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); 15444 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : 15445 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); 15446 15447 return 0; 15448} 15449 15450/* Called during load, to initialize PTP-related stuff */ 15451void bnx2x_init_ptp(struct bnx2x *bp) 15452{ 15453 int rc; 15454 15455 /* Configure PTP in HW */ 15456 rc = bnx2x_configure_ptp(bp); 15457 if (rc) { 15458 BNX2X_ERR("Stopping PTP initialization\n"); 15459 return; 15460 } 15461 15462 /* Init work queue for Tx timestamping */ 15463 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); 15464 15465 /* Init cyclecounter and timecounter. This is done only in the first 15466 * load. If done in every load, PTP application will fail when doing 15467 * unload / load (e.g. MTU change) while it is running. 15468 */ 15469 if (!bp->timecounter_init_done) { 15470 bnx2x_init_cyclecounter(bp); 15471 timecounter_init(&bp->timecounter, &bp->cyclecounter, 15472 ktime_to_ns(ktime_get_real())); 15473 bp->timecounter_init_done = true; 15474 } 15475 15476 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n"); 15477}
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