bcmasp_intf_defs.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef __BCMASP_INTF_DEFS_H
  3#define __BCMASP_INTF_DEFS_H
  4
  5#define UMC_OFFSET(intf)		\
  6	((((intf)->port) * 0x800) + 0xc000)
  7#define  UMC_CMD			0x008
  8#define   UMC_CMD_TX_EN			BIT(0)
  9#define   UMC_CMD_RX_EN			BIT(1)
 10#define   UMC_CMD_SPEED_SHIFT		0x2
 11#define    UMC_CMD_SPEED_MASK		0x3
 12#define    UMC_CMD_SPEED_10		0x0
 13#define    UMC_CMD_SPEED_100		0x1
 14#define    UMC_CMD_SPEED_1000		0x2
 15#define    UMC_CMD_SPEED_2500		0x3
 16#define   UMC_CMD_PROMISC		BIT(4)
 17#define   UMC_CMD_PAD_EN		BIT(5)
 18#define   UMC_CMD_CRC_FWD		BIT(6)
 19#define   UMC_CMD_PAUSE_FWD		BIT(7)
 20#define   UMC_CMD_RX_PAUSE_IGNORE	BIT(8)
 21#define   UMC_CMD_TX_ADDR_INS		BIT(9)
 22#define   UMC_CMD_HD_EN			BIT(10)
 23#define   UMC_CMD_SW_RESET		BIT(13)
 24#define   UMC_CMD_LCL_LOOP_EN		BIT(15)
 25#define   UMC_CMD_AUTO_CONFIG		BIT(22)
 26#define   UMC_CMD_CNTL_FRM_EN		BIT(23)
 27#define   UMC_CMD_NO_LEN_CHK		BIT(24)
 28#define   UMC_CMD_RMT_LOOP_EN		BIT(25)
 29#define   UMC_CMD_PRBL_EN		BIT(27)
 30#define   UMC_CMD_TX_PAUSE_IGNORE	BIT(28)
 31#define   UMC_CMD_TX_RX_EN		BIT(29)
 32#define   UMC_CMD_RUNT_FILTER_DIS	BIT(30)
 33#define  UMC_MAC0			0x0c
 34#define  UMC_MAC1			0x10
 35#define  UMC_FRM_LEN			0x14
 36#define  UMC_EEE_CTRL			0x64
 37#define   EN_LPI_RX_PAUSE		BIT(0)
 38#define   EN_LPI_TX_PFC			BIT(1)
 39#define   EN_LPI_TX_PAUSE		BIT(2)
 40#define   EEE_EN			BIT(3)
 41#define   RX_FIFO_CHECK			BIT(4)
 42#define   EEE_TX_CLK_DIS		BIT(5)
 43#define   DIS_EEE_10M			BIT(6)
 44#define   LP_IDLE_PREDICTION_MODE	BIT(7)
 45#define  UMC_EEE_LPI_TIMER		0x68
 46#define  UMC_PAUSE_CNTRL		0x330
 47#define  UMC_TX_FLUSH			0x334
 48#define  UMC_GR64			0x400
 49#define  UMC_GR127			0x404
 50#define  UMC_GR255			0x408
 51#define  UMC_GR511			0x40c
 52#define  UMC_GR1023			0x410
 53#define  UMC_GR1518			0x414
 54#define  UMC_GRMGV			0x418
 55#define  UMC_GR2047			0x41c
 56#define  UMC_GR4095			0x420
 57#define  UMC_GR9216			0x424
 58#define  UMC_GRPKT			0x428
 59#define  UMC_GRBYT			0x42c
 60#define  UMC_GRMCA			0x430
 61#define  UMC_GRBCA			0x434
 62#define  UMC_GRFCS			0x438
 63#define  UMC_GRXCF			0x43c
 64#define  UMC_GRXPF			0x440
 65#define  UMC_GRXUO			0x444
 66#define  UMC_GRALN			0x448
 67#define  UMC_GRFLR			0x44c
 68#define  UMC_GRCDE			0x450
 69#define  UMC_GRFCR			0x454
 70#define  UMC_GROVR			0x458
 71#define  UMC_GRJBR			0x45c
 72#define  UMC_GRMTUE			0x460
 73#define  UMC_GRPOK			0x464
 74#define  UMC_GRUC			0x468
 75#define  UMC_GRPPP			0x46c
 76#define  UMC_GRMCRC			0x470
 77#define  UMC_TR64			0x480
 78#define  UMC_TR127			0x484
 79#define  UMC_TR255			0x488
 80#define  UMC_TR511			0x48c
 81#define  UMC_TR1023			0x490
 82#define  UMC_TR1518			0x494
 83#define  UMC_TRMGV			0x498
 84#define  UMC_TR2047			0x49c
 85#define  UMC_TR4095			0x4a0
 86#define  UMC_TR9216			0x4a4
 87#define  UMC_GTPKT			0x4a8
 88#define  UMC_GTMCA			0x4ac
 89#define  UMC_GTBCA			0x4b0
 90#define  UMC_GTXPF			0x4b4
 91#define  UMC_GTXCF			0x4b8
 92#define  UMC_GTFCS			0x4bc
 93#define  UMC_GTOVR			0x4c0
 94#define  UMC_GTDRF			0x4c4
 95#define  UMC_GTEDF			0x4c8
 96#define  UMC_GTSCL			0x4cc
 97#define  UMC_GTMCL			0x4d0
 98#define  UMC_GTLCL			0x4d4
 99#define  UMC_GTXCL			0x4d8
100#define  UMC_GTFRG			0x4dc
101#define  UMC_GTNCL			0x4e0
102#define  UMC_GTJBR			0x4e4
103#define  UMC_GTBYT			0x4e8
104#define  UMC_GTPOK			0x4ec
105#define  UMC_GTUC			0x4f0
106#define  UMC_RRPKT			0x500
107#define  UMC_RRUND			0x504
108#define  UMC_RRFRG			0x508
109#define  UMC_RRBYT			0x50c
110#define  UMC_MIB_CNTRL			0x580
111#define   UMC_MIB_CNTRL_RX_CNT_RST	BIT(0)
112#define   UMC_MIB_CNTRL_RUNT_CNT_RST	BIT(1)
113#define   UMC_MIB_CNTRL_TX_CNT_RST	BIT(2)
114#define  UMC_RX_MAX_PKT_SZ		0x608
115#define  UMC_MPD_CTRL			0x620
116#define   UMC_MPD_CTRL_MPD_EN		BIT(0)
117#define   UMC_MPD_CTRL_PSW_EN		BIT(27)
118#define  UMC_PSW_MS			0x624
119#define  UMC_PSW_LS			0x628
120
121#define UMAC2FB_OFFSET			0x9f044
122#define  UMAC2FB_CFG			0x0
123#define   UMAC2FB_CFG_OPUT_EN		BIT(0)
124#define   UMAC2FB_CFG_VLAN_EN		BIT(1)
125#define   UMAC2FB_CFG_SNAP_EN		BIT(2)
126#define   UMAC2FB_CFG_BCM_TG_EN		BIT(3)
127#define   UMAC2FB_CFG_IPUT_EN		BIT(4)
128#define   UMAC2FB_CFG_CHID_SHIFT	8
129#define   UMAC2FB_CFG_OK_SEND_SHIFT	24
130#define   UMAC2FB_CFG_DEFAULT_EN	\
131		(UMAC2FB_CFG_OPUT_EN | UMAC2FB_CFG_VLAN_EN \
132		| UMAC2FB_CFG_SNAP_EN | UMAC2FB_CFG_IPUT_EN)
133
134#define RGMII_OFFSET(intf)	\
135	((((intf)->port) * 0x100) + 0xd000)
136#define  RGMII_EPHY_CNTRL		0x00
137#define    RGMII_EPHY_CFG_IDDQ_BIAS	BIT(0)
138#define    RGMII_EPHY_CFG_EXT_PWRDOWN	BIT(1)
139#define    RGMII_EPHY_CFG_FORCE_DLL_EN	BIT(2)
140#define    RGMII_EPHY_CFG_IDDQ_GLOBAL	BIT(3)
141#define    RGMII_EPHY_CK25_DIS		BIT(4)
142#define    RGMII_EPHY_RESET		BIT(7)
143#define  RGMII_OOB_CNTRL		0x0c
144#define   RGMII_LINK			BIT(4)
145#define   RGMII_OOB_DIS			BIT(5)
146#define   RGMII_MODE_EN			BIT(6)
147#define   RGMII_ID_MODE_DIS		BIT(16)
148
149#define RGMII_PORT_CNTRL		0x60
150#define   RGMII_PORT_MODE_EPHY		0
151#define   RGMII_PORT_MODE_GPHY		1
152#define   RGMII_PORT_MODE_EXT_EPHY	2
153#define   RGMII_PORT_MODE_EXT_GPHY	3
154#define   RGMII_PORT_MODE_EXT_RVMII	4
155#define   RGMII_PORT_MODE_MASK		GENMASK(2, 0)
156
157#define RGMII_SYS_LED_CNTRL		0x74
158#define  RGMII_SYS_LED_CNTRL_LINK_OVRD	BIT(15)
159
160#define TX_SPB_DMA_OFFSET(intf) \
161	((((intf)->channel) * 0x30) + 0x48180)
162#define  TX_SPB_DMA_READ		0x00
163#define  TX_SPB_DMA_BASE		0x08
164#define  TX_SPB_DMA_END			0x10
165#define  TX_SPB_DMA_VALID		0x18
166#define  TX_SPB_DMA_FIFO_CTRL		0x20
167#define   TX_SPB_DMA_FIFO_FLUSH		BIT(0)
168#define  TX_SPB_DMA_FIFO_STATUS		0x24
169
170#define TX_SPB_CTRL_OFFSET(intf) \
171	((((intf)->channel) * 0x68) + 0x49340)
172#define  TX_SPB_CTRL_ENABLE		0x0
173#define   TX_SPB_CTRL_ENABLE_EN		BIT(0)
174#define  TX_SPB_CTRL_XF_CTRL2		0x20
175#define   TX_SPB_CTRL_XF_BID_SHIFT	16
176
177#define TX_SPB_TOP_OFFSET(intf) \
178	((((intf)->channel) * 0x1c) + 0x4a0e0)
179#define TX_SPB_TOP_BLKOUT		0x0
180#define TX_SPB_TOP_SPRE_BW_CTRL		0x4
181
182#define TX_EPKT_C_OFFSET(intf) \
183	((((intf)->channel) * 0x120) + 0x40900)
184#define  TX_EPKT_C_CFG_MISC		0x0
185#define   TX_EPKT_C_CFG_MISC_EN		BIT(0)
186#define   TX_EPKT_C_CFG_MISC_PT		BIT(1)
187#define   TX_EPKT_C_CFG_MISC_PS_SHIFT	14
188#define   TX_EPKT_C_CFG_MISC_FD_SHIFT	20
189
190#define TX_PAUSE_CTRL_OFFSET(intf) \
191	((((intf)->channel * 0xc) + 0x49a20))
192#define  TX_PAUSE_MAP_VECTOR		0x8
193
194#define RX_EDPKT_DMA_OFFSET(intf) \
195	((((intf)->channel) * 0x38) + 0x9ca00)
196#define  RX_EDPKT_DMA_WRITE		0x00
197#define  RX_EDPKT_DMA_READ		0x08
198#define  RX_EDPKT_DMA_BASE		0x10
199#define  RX_EDPKT_DMA_END		0x18
200#define  RX_EDPKT_DMA_VALID		0x20
201#define  RX_EDPKT_DMA_FULLNESS		0x28
202#define  RX_EDPKT_DMA_MIN_THRES		0x2c
203#define  RX_EDPKT_DMA_CH_XONOFF		0x30
204
205#define RX_EDPKT_CFG_OFFSET(intf) \
206	((((intf)->channel) * 0x70) + 0x9c600)
207#define  RX_EDPKT_CFG_CFG0		0x0
208#define   RX_EDPKT_CFG_CFG0_DBUF_SHIFT	9
209#define    RX_EDPKT_CFG_CFG0_RBUF	0x0
210#define    RX_EDPKT_CFG_CFG0_RBUF_4K	0x1
211#define    RX_EDPKT_CFG_CFG0_BUF_4K	0x2
212/* EFRM STUFF, 0 = no byte stuff, 1 = two byte stuff */
213#define   RX_EDPKT_CFG_CFG0_EFRM_STUF	BIT(11)
214#define   RX_EDPKT_CFG_CFG0_BALN_SHIFT	12
215#define    RX_EDPKT_CFG_CFG0_NO_ALN	0
216#define    RX_EDPKT_CFG_CFG0_4_ALN	2
217#define    RX_EDPKT_CFG_CFG0_64_ALN	6
218#define  RX_EDPKT_RING_BUFFER_WRITE	0x38
219#define  RX_EDPKT_RING_BUFFER_READ	0x40
220#define  RX_EDPKT_RING_BUFFER_BASE	0x48
221#define  RX_EDPKT_RING_BUFFER_END	0x50
222#define  RX_EDPKT_RING_BUFFER_VALID	0x58
223#define  RX_EDPKT_CFG_ENABLE		0x6c
224#define   RX_EDPKT_CFG_ENABLE_EN	BIT(0)
225
226#define RX_SPB_DMA_OFFSET(intf) \
227	((((intf)->channel) * 0x30) + 0xa0000)
228#define  RX_SPB_DMA_READ		0x00
229#define  RX_SPB_DMA_BASE		0x08
230#define  RX_SPB_DMA_END			0x10
231#define  RX_SPB_DMA_VALID		0x18
232#define  RX_SPB_DMA_FIFO_CTRL		0x20
233#define   RX_SPB_DMA_FIFO_FLUSH		BIT(0)
234#define  RX_SPB_DMA_FIFO_STATUS		0x24
235
236#define RX_SPB_CTRL_OFFSET(intf) \
237	((((intf)->channel - 6) * 0x68) + 0xa1000)
238#define  RX_SPB_CTRL_ENABLE		0x00
239#define   RX_SPB_CTRL_ENABLE_EN		BIT(0)
240
241#define RX_PAUSE_CTRL_OFFSET(intf) \
242	((((intf)->channel - 6) * 0x4) + 0xa1138)
243#define  RX_PAUSE_MAP_VECTOR		0x00
244
245#define RX_SPB_TOP_CTRL_OFFSET(intf) \
246	((((intf)->channel - 6) * 0x14) + 0xa2000)
247#define  RX_SPB_TOP_BLKOUT		0x00
248
249#define NUM_4K_BUFFERS			32
250#define RING_BUFFER_SIZE		(PAGE_SIZE * NUM_4K_BUFFERS)
251
252#define DESC_RING_COUNT			(64 * NUM_4K_BUFFERS)
253#define DESC_SIZE			16
254#define DESC_RING_SIZE			(DESC_RING_COUNT * DESC_SIZE)
255
256#endif